1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
29 enum NodeType : unsigned {
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
38 /// Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// These operations represent an abstract X86 call
60 /// instruction, which includes a bunch of information. In particular the
61 /// operands of these node are:
63 /// #0 - The incoming token chain
65 /// #2 - The number of arg bytes the caller pushes on the stack.
66 /// #3 - The number of arg bytes the callee pops off the stack.
67 /// #4 - The value to pass in AL/AX/EAX (optional)
68 /// #5 - The value to pass in DL/DX/EDX (optional)
70 /// The result values of these nodes are:
72 /// #0 - The outgoing token chain
73 /// #1 - The first register result value (optional)
74 /// #2 - The second register result value (optional)
78 /// This operation implements the lowering for readcyclecounter
81 /// X86 Read Time-Stamp Counter and Processor ID.
84 /// X86 Read Performance Monitoring Counters.
87 /// X86 compare and logical compare instructions.
90 /// X86 bit-test instructions.
93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94 /// operand, usually produced by a CMP instruction.
100 // Same as SETCC except it's materialized with a sbb and the value is all
101 // one's or all zero's.
102 SETCC_CARRY, // R = carry_bit ? ~0 : 0
104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105 /// Operands are two FP values to compare; result is a mask of
106 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
109 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
110 /// result in an integer GPR. Needs masking for scalar result.
113 /// X86 conditional moves. Operand 0 and operand 1 are the two values
114 /// to select from. Operand 2 is the condition code, and operand 3 is the
115 /// flag operand produced by a CMP or TEST instruction. It also writes a
119 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120 /// is the block to branch if condition is true, operand 2 is the
121 /// condition code, and operand 3 is the flag operand produced by a CMP
122 /// or TEST instruction.
125 /// Return with a flag operand. Operand 0 is the chain operand, operand
126 /// 1 is the number of bytes of stack to pop.
129 /// Repeat fill, corresponds to X86::REP_STOSx.
132 /// Repeat move, corresponds to X86::REP_MOVSx.
135 /// On Darwin, this node represents the result of the popl
136 /// at function entry, used for PIC code.
139 /// A wrapper node for TargetConstantPool,
140 /// TargetExternalSymbol, and TargetGlobalAddress.
143 /// Special wrapper used under X86-64 PIC mode for RIP
144 /// relative displacements.
147 /// Copies a 64-bit value from the low word of an XMM vector
148 /// to an MMX vector. If you think this is too close to the previous
149 /// mnemonic, so do I; blame Intel.
152 /// Copies a 32-bit value from the low word of a MMX
156 /// Copies a GPR into the low 32-bit word of a MMX vector
157 /// and zero out the high word.
160 /// Extract an 8-bit value from a vector and zero extend it to
161 /// i32, corresponds to X86::PEXTRB.
164 /// Extract a 16-bit value from a vector and zero extend it to
165 /// i32, corresponds to X86::PEXTRW.
168 /// Insert any element of a 4 x float vector into any element
169 /// of a destination 4 x floatvector.
172 /// Insert the lower 8-bits of a 32-bit value to a vector,
173 /// corresponds to X86::PINSRB.
176 /// Insert the lower 16-bits of a 32-bit value to a vector,
177 /// corresponds to X86::PINSRW.
180 /// Shuffle 16 8-bit values within a vector.
183 /// Compute Sum of Absolute Differences.
186 /// Bitwise Logical AND NOT of Packed FP values.
189 /// Copy integer sign.
192 /// Blend where the selector is an immediate.
195 /// Blend where the condition has been shrunk.
196 /// This is used to emphasize that the condition mask is
197 /// no more valid for generic VSELECT optimizations.
200 /// Combined add and sub on an FP vector.
202 // FP vector ops with rounding mode.
210 // Integer add/sub with unsigned saturation.
213 // Integer add/sub with signed saturation.
217 /// Integer horizontal add.
220 /// Integer horizontal sub.
223 /// Floating point horizontal add.
226 /// Floating point horizontal sub.
229 /// Unsigned integer max and min.
232 /// Signed integer max and min.
235 /// Floating point max and min.
238 /// Commutative FMIN and FMAX.
241 /// Floating point reciprocal-sqrt and reciprocal approximation.
242 /// Note that these typically require refinement
243 /// in order to obtain suitable precision.
246 // Thread Local Storage.
249 // Thread Local Storage. A call to get the start address
250 // of the TLS block for the current module.
253 // Thread Local Storage. When calling to an OS provided
254 // thunk at the address from an earlier relocation.
257 // Exception Handling helpers.
260 // SjLj exception handling setjmp.
263 // SjLj exception handling longjmp.
266 /// Tail call return. See X86TargetLowering::LowerCall for
267 /// the list of operands.
270 // Vector move to low scalar and zero higher vector elements.
273 // Vector integer zero-extend.
276 // Vector integer signed-extend.
279 // Vector integer truncate.
282 // Vector integer truncate with mask.
291 // 128-bit vector logical left / right shift
294 // Vector shift elements
297 // Vector shift elements by immediate
300 // Vector packed double/float comparison.
303 // Vector integer comparisons.
305 // Vector integer comparisons, the result is in a mask vector.
308 /// Vector comparison generating mask bits for fp and
309 /// integer signed and unsigned data types.
312 // Vector comparison with rounding mode for FP values
315 // Arithmetic operations with FLAGS results.
316 ADD, SUB, ADC, SBB, SMUL,
317 INC, DEC, OR, XOR, AND,
319 BEXTR, // Bit field extract
321 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
323 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
326 // 8-bit divrem that zero-extend the high result (AH).
330 // X86-specific multiply by immediate.
333 // Vector bitwise comparisons.
336 // Vector packed fp sign bitwise comparisons.
339 // Vector "test" in AVX-512, the result is in a mask vector.
343 // OR/AND test for masks
346 // Several flavors of instructions with vector shuffle behaviors.
351 // AVX512 inter-lane alignr
357 //Shuffle Packed Values at 128-bit granularity
378 //Fix Up Special Packed Float32/64 values
380 //Range Restriction Calculation For Packed Pairs of Float32/64 values
382 // Broadcast scalar to vector
384 // Broadcast subvector to vector
386 // Insert/Extract vector element
390 // Vector multiply packed unsigned doubleword integers
392 // Vector multiply packed signed doubleword integers
402 // FMA with rounding mode
411 // Compress and expand
415 // Save xmm argument registers to the stack, according to %al. An operator
416 // is needed so that this can be expanded with control flow.
417 VASTART_SAVE_XMM_REGS,
419 // Windows's _chkstk call to do stack probing.
422 // For allocating variable amounts of stack space when using
423 // segmented stacks. Check if the current stacklet has enough space, and
424 // falls back to heap allocation if not.
427 // Windows's _ftol2 runtime routine to do fptoui.
436 // Store FP status word into i16 register.
439 // Store contents of %ah into %eflags.
442 // Get a random integer and indicate whether it is valid in CF.
445 // Get a NIST SP800-90B & C compliant random integer and
446 // indicate whether it is valid in CF.
452 // Test if in transactional execution.
456 RSQRT28, RCP28, EXP2,
459 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
463 // Load, scalar_to_vector, and zero extend.
466 // Store FP control world into i16 memory.
469 /// This instruction implements FP_TO_SINT with the
470 /// integer destination in memory and a FP reg source. This corresponds
471 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
472 /// has two inputs (token chain and address) and two outputs (int value
473 /// and token chain).
478 /// This instruction implements SINT_TO_FP with the
479 /// integer source in memory and FP reg result. This corresponds to the
480 /// X86::FILD*m instructions. It has three inputs (token chain, address,
481 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
482 /// also produces a flag).
486 /// This instruction implements an extending load to FP stack slots.
487 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
488 /// operand, ptr to load from, and a ValueType node indicating the type
492 /// This instruction implements a truncating store to FP stack
493 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
494 /// chain operand, value to store, address, and a ValueType to store it
498 /// This instruction grabs the address of the next argument
499 /// from a va_list. (reads and modifies the va_list in memory)
502 // WARNING: Do not add anything in the end unless you want the node to
503 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
504 // thought as target memory ops!
508 /// Define some predicates that are used for node matching.
510 /// Return true if the specified
511 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
512 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
513 bool isVEXTRACT128Index(SDNode *N);
515 /// Return true if the specified
516 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
517 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
518 bool isVINSERT128Index(SDNode *N);
520 /// Return true if the specified
521 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
522 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
523 bool isVEXTRACT256Index(SDNode *N);
525 /// Return true if the specified
526 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
527 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
528 bool isVINSERT256Index(SDNode *N);
530 /// Return the appropriate
531 /// immediate to extract the specified EXTRACT_SUBVECTOR index
532 /// with VEXTRACTF128, VEXTRACTI128 instructions.
533 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
535 /// Return the appropriate
536 /// immediate to insert at the specified INSERT_SUBVECTOR index
537 /// with VINSERTF128, VINSERT128 instructions.
538 unsigned getInsertVINSERT128Immediate(SDNode *N);
540 /// Return the appropriate
541 /// immediate to extract the specified EXTRACT_SUBVECTOR index
542 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
543 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
545 /// Return the appropriate
546 /// immediate to insert at the specified INSERT_SUBVECTOR index
547 /// with VINSERTF64x4, VINSERTI64x4 instructions.
548 unsigned getInsertVINSERT256Immediate(SDNode *N);
550 /// Returns true if Elt is a constant zero or floating point constant +0.0.
551 bool isZeroNode(SDValue Elt);
553 /// Returns true of the given offset can be
554 /// fit into displacement field of the instruction.
555 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
556 bool hasSymbolicDisplacement = true);
559 /// Determines whether the callee is required to pop its
560 /// own arguments. Callee pop is necessary to support tail calls.
561 bool isCalleePop(CallingConv::ID CallingConv,
562 bool is64Bit, bool IsVarArg, bool TailCallOpt);
564 /// AVX512 static rounding constants. These need to match the values in
566 enum STATIC_ROUNDING {
575 //===--------------------------------------------------------------------===//
576 // X86 Implementation of the TargetLowering interface
577 class X86TargetLowering final : public TargetLowering {
579 explicit X86TargetLowering(const X86TargetMachine &TM,
580 const X86Subtarget &STI);
582 unsigned getJumpTableEncoding() const override;
583 bool useSoftFloat() const override;
585 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }
588 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
589 const MachineBasicBlock *MBB, unsigned uid,
590 MCContext &Ctx) const override;
592 /// Returns relocation base for the given PIC jumptable.
593 SDValue getPICJumpTableRelocBase(SDValue Table,
594 SelectionDAG &DAG) const override;
596 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
597 unsigned JTI, MCContext &Ctx) const override;
599 /// Return the desired alignment for ByVal aggregate
600 /// function arguments in the caller parameter area. For X86, aggregates
601 /// that contains are placed at 16-byte boundaries while the rest are at
602 /// 4-byte boundaries.
603 unsigned getByValTypeAlignment(Type *Ty) const override;
605 /// Returns the target specific optimal type for load
606 /// and store operations as a result of memset, memcpy, and memmove
607 /// lowering. If DstAlign is zero that means it's safe to destination
608 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
609 /// means there isn't a need to check it against alignment requirement,
610 /// probably because the source does not need to be loaded. If 'IsMemset' is
611 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
612 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
613 /// source is constant so it does not need to be loaded.
614 /// It returns EVT::Other if the type should be determined using generic
615 /// target-independent logic.
616 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
617 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
618 MachineFunction &MF) const override;
620 /// Returns true if it's safe to use load / store of the
621 /// specified type to expand memcpy / memset inline. This is mostly true
622 /// for all types except for some special cases. For example, on X86
623 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
624 /// also does type conversion. Note the specified type doesn't have to be
625 /// legal as the hook is used before type legalization.
626 bool isSafeMemOpType(MVT VT) const override;
628 /// Returns true if the target allows
629 /// unaligned memory accesses. of the specified type. Returns whether it
630 /// is "fast" by reference in the second argument.
631 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
632 bool *Fast) const override;
634 /// Provide custom lowering hooks for some operations.
636 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
638 /// Replace the results of node with an illegal result
639 /// type with new values built out of custom code.
641 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
642 SelectionDAG &DAG) const override;
645 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
647 /// Return true if the target has native support for
648 /// the specified value type and it is 'desirable' to use the type for the
649 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
650 /// instruction encodings are longer and some i16 instructions are slow.
651 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
653 /// Return true if the target has native support for the
654 /// specified value type and it is 'desirable' to use the type. e.g. On x86
655 /// i16 is legal, but undesirable since i16 instruction encodings are longer
656 /// and some i16 instructions are slow.
657 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
660 EmitInstrWithCustomInserter(MachineInstr *MI,
661 MachineBasicBlock *MBB) const override;
664 /// This method returns the name of a target specific DAG node.
665 const char *getTargetNodeName(unsigned Opcode) const override;
667 bool isCheapToSpeculateCttz() const override;
669 bool isCheapToSpeculateCtlz() const override;
671 /// Return the value type to use for ISD::SETCC.
672 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
674 /// Determine which of the bits specified in Mask are known to be either
675 /// zero or one and return them in the KnownZero/KnownOne bitsets.
676 void computeKnownBitsForTargetNode(const SDValue Op,
679 const SelectionDAG &DAG,
680 unsigned Depth = 0) const override;
682 /// Determine the number of bits in the operation that are sign bits.
683 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
684 const SelectionDAG &DAG,
685 unsigned Depth) const override;
687 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
688 int64_t &Offset) const override;
690 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
692 bool ExpandInlineAsm(CallInst *CI) const override;
695 getConstraintType(const std::string &Constraint) const override;
697 /// Examine constraint string and operand type and determine a weight value.
698 /// The operand object must already have been set up with the operand type.
700 getSingleConstraintMatchWeight(AsmOperandInfo &info,
701 const char *constraint) const override;
703 const char *LowerXConstraint(EVT ConstraintVT) const override;
705 /// Lower the specified operand into the Ops vector. If it is invalid, don't
706 /// add anything to Ops. If hasMemory is true it means one of the asm
707 /// constraint of the inline asm instruction being processed is 'm'.
708 void LowerAsmOperandForConstraint(SDValue Op,
709 std::string &Constraint,
710 std::vector<SDValue> &Ops,
711 SelectionDAG &DAG) const override;
713 unsigned getInlineAsmMemConstraint(
714 const std::string &ConstraintCode) const override {
715 if (ConstraintCode == "i")
716 return InlineAsm::Constraint_i;
717 else if (ConstraintCode == "o")
718 return InlineAsm::Constraint_o;
719 else if (ConstraintCode == "v")
720 return InlineAsm::Constraint_v;
721 else if (ConstraintCode == "X")
722 return InlineAsm::Constraint_X;
723 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
726 /// Given a physical register constraint
727 /// (e.g. {edx}), return the register number and the register class for the
728 /// register. This should only be used for C_Register constraints. On
729 /// error, this returns a register number of 0.
730 std::pair<unsigned, const TargetRegisterClass *>
731 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
732 const std::string &Constraint,
733 MVT VT) const override;
735 /// Return true if the addressing mode represented
736 /// by AM is legal for this target, for a load/store of the specified type.
737 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty,
738 unsigned AS) const override;
740 /// Return true if the specified immediate is legal
741 /// icmp immediate, that is the target has icmp instructions which can
742 /// compare a register against the immediate without having to materialize
743 /// the immediate into a register.
744 bool isLegalICmpImmediate(int64_t Imm) const override;
746 /// Return true if the specified immediate is legal
747 /// add immediate, that is the target has add instructions which can
748 /// add a register and the immediate without having to materialize
749 /// the immediate into a register.
750 bool isLegalAddImmediate(int64_t Imm) const override;
752 /// \brief Return the cost of the scaling factor used in the addressing
753 /// mode represented by AM for this target, for a load/store
754 /// of the specified type.
755 /// If the AM is supported, the return value must be >= 0.
756 /// If the AM is not supported, it returns a negative value.
757 int getScalingFactorCost(const AddrMode &AM, Type *Ty,
758 unsigned AS) const override;
760 bool isVectorShiftByScalarCheap(Type *Ty) const override;
762 /// Return true if it's free to truncate a value of
763 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
764 /// register EAX to i16 by referencing its sub-register AX.
765 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
766 bool isTruncateFree(EVT VT1, EVT VT2) const override;
768 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
770 /// Return true if any actual instruction that defines a
771 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
772 /// register. This does not necessarily include registers defined in
773 /// unknown ways, such as incoming arguments, or copies from unknown
774 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
775 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
776 /// all instructions that define 32-bit values implicit zero-extend the
777 /// result out to 64 bits.
778 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
779 bool isZExtFree(EVT VT1, EVT VT2) const override;
780 bool isZExtFree(SDValue Val, EVT VT2) const override;
782 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
783 /// extend node) is profitable.
784 bool isVectorLoadExtDesirable(SDValue) const override;
786 /// Return true if an FMA operation is faster than a pair of fmul and fadd
787 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
788 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
789 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
791 /// Return true if it's profitable to narrow
792 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
793 /// from i32 to i8 but not from i32 to i16.
794 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
796 /// Returns true if the target can instruction select the
797 /// specified FP immediate natively. If false, the legalizer will
798 /// materialize the FP immediate as a load from a constant pool.
799 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
801 /// Targets can use this to indicate that they only support *some*
802 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
803 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
805 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
806 EVT VT) const override;
808 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
809 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
810 /// replace a VAND with a constant pool entry.
811 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
812 EVT VT) const override;
814 /// If true, then instruction selection should
815 /// seek to shrink the FP constant of the specified type to a smaller type
816 /// in order to save space and / or reduce runtime.
817 bool ShouldShrinkFPConstant(EVT VT) const override {
818 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
819 // expensive than a straight movsd. On the other hand, it's important to
820 // shrink long double fp constant since fldt is very slow.
821 return !X86ScalarSSEf64 || VT == MVT::f80;
824 /// Return true if we believe it is correct and profitable to reduce the
825 /// load node to a smaller type.
826 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
827 EVT NewVT) const override;
829 /// Return true if the specified scalar FP type is computed in an SSE
830 /// register, not on the X87 floating point stack.
831 bool isScalarFPTypeInSSEReg(EVT VT) const {
832 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
833 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
836 /// Return true if the target uses the MSVC _ftol2 routine for fptoui.
837 bool isTargetFTOL() const;
839 /// Return true if the MSVC _ftol2 routine should be used for fptoui to the
841 bool isIntegerTypeFTOL(EVT VT) const {
842 return isTargetFTOL() && VT == MVT::i64;
845 /// \brief Returns true if it is beneficial to convert a load of a constant
846 /// to just the constant itself.
847 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
848 Type *Ty) const override;
850 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
852 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
854 /// Intel processors have a unified instruction and data cache
855 const char * getClearCacheBuiltinName() const override {
856 return nullptr; // nothing to do, move along.
859 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
861 /// This method returns a target specific FastISel object,
862 /// or null if the target does not support "fast" ISel.
863 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
864 const TargetLibraryInfo *libInfo) const override;
866 /// Return true if the target stores stack protector cookies at a fixed
867 /// offset in some non-standard address space, and populates the address
868 /// space and offset as appropriate.
869 bool getStackCookieLocation(unsigned &AddressSpace,
870 unsigned &Offset) const override;
872 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
873 SelectionDAG &DAG) const;
875 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
877 bool useLoadStackGuardNode() const override;
878 /// \brief Customize the preferred legalization strategy for certain types.
879 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
882 std::pair<const TargetRegisterClass *, uint8_t>
883 findRepresentativeClass(const TargetRegisterInfo *TRI,
884 MVT VT) const override;
887 /// Keep a pointer to the X86Subtarget around so that we can
888 /// make the right decision when generating code for different targets.
889 const X86Subtarget *Subtarget;
890 const DataLayout *TD;
892 /// Select between SSE or x87 floating point ops.
893 /// When SSE is available, use it for f32 operations.
894 /// When SSE2 is available, use it for f64 operations.
895 bool X86ScalarSSEf32;
896 bool X86ScalarSSEf64;
898 /// A list of legal FP immediates.
899 std::vector<APFloat> LegalFPImmediates;
901 /// Indicate that this x86 target can instruction
902 /// select the specified FP immediate natively.
903 void addLegalFPImmediate(const APFloat& Imm) {
904 LegalFPImmediates.push_back(Imm);
907 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
908 CallingConv::ID CallConv, bool isVarArg,
909 const SmallVectorImpl<ISD::InputArg> &Ins,
910 SDLoc dl, SelectionDAG &DAG,
911 SmallVectorImpl<SDValue> &InVals) const;
912 SDValue LowerMemArgument(SDValue Chain,
913 CallingConv::ID CallConv,
914 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
915 SDLoc dl, SelectionDAG &DAG,
916 const CCValAssign &VA, MachineFrameInfo *MFI,
918 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
919 SDLoc dl, SelectionDAG &DAG,
920 const CCValAssign &VA,
921 ISD::ArgFlagsTy Flags) const;
923 // Call lowering helpers.
925 /// Check whether the call is eligible for tail call optimization. Targets
926 /// that want to do tail call optimization should implement this function.
927 bool IsEligibleForTailCallOptimization(SDValue Callee,
928 CallingConv::ID CalleeCC,
930 bool isCalleeStructRet,
931 bool isCallerStructRet,
933 const SmallVectorImpl<ISD::OutputArg> &Outs,
934 const SmallVectorImpl<SDValue> &OutVals,
935 const SmallVectorImpl<ISD::InputArg> &Ins,
936 SelectionDAG& DAG) const;
937 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
938 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
939 SDValue Chain, bool IsTailCall, bool Is64Bit,
940 int FPDiff, SDLoc dl) const;
942 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
943 SelectionDAG &DAG) const;
945 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
947 bool isReplace) const;
949 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
950 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
951 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
952 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
953 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
954 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
955 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
957 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
958 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
959 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
960 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
961 int64_t Offset, SelectionDAG &DAG) const;
962 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
963 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
964 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
965 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
966 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
967 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
968 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
969 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
970 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
971 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
972 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
973 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
974 SDLoc dl, SelectionDAG &DAG) const;
975 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
976 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
977 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
978 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
979 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
980 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
981 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
982 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
983 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
984 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
985 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
986 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
987 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
988 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
989 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
990 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
991 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
992 SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
993 SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
996 LowerFormalArguments(SDValue Chain,
997 CallingConv::ID CallConv, bool isVarArg,
998 const SmallVectorImpl<ISD::InputArg> &Ins,
999 SDLoc dl, SelectionDAG &DAG,
1000 SmallVectorImpl<SDValue> &InVals) const override;
1001 SDValue LowerCall(CallLoweringInfo &CLI,
1002 SmallVectorImpl<SDValue> &InVals) const override;
1004 SDValue LowerReturn(SDValue Chain,
1005 CallingConv::ID CallConv, bool isVarArg,
1006 const SmallVectorImpl<ISD::OutputArg> &Outs,
1007 const SmallVectorImpl<SDValue> &OutVals,
1008 SDLoc dl, SelectionDAG &DAG) const override;
1010 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1012 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
1014 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1015 ISD::NodeType ExtendKind) const override;
1017 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1019 const SmallVectorImpl<ISD::OutputArg> &Outs,
1020 LLVMContext &Context) const override;
1022 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1024 bool shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1025 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1026 TargetLoweringBase::AtomicRMWExpansionKind
1027 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1030 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1032 bool needsCmpXchgNb(const Type *MemType) const;
1034 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1035 /// nand, max, min, umax, umin). It takes the corresponding instruction to
1036 /// expand, the associated machine basic block, and the associated X86
1037 /// opcodes for reg/reg.
1038 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
1039 MachineBasicBlock *MBB) const;
1041 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1042 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
1043 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
1044 MachineBasicBlock *MBB) const;
1046 // Utility function to emit the low-level va_arg code for X86-64.
1047 MachineBasicBlock *EmitVAARG64WithCustomInserter(
1049 MachineBasicBlock *MBB) const;
1051 /// Utility function to emit the xmm reg save portion of va_start.
1052 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
1053 MachineInstr *BInstr,
1054 MachineBasicBlock *BB) const;
1056 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
1057 MachineBasicBlock *BB) const;
1059 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
1060 MachineBasicBlock *BB) const;
1062 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1063 MachineBasicBlock *BB) const;
1065 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1066 MachineBasicBlock *BB) const;
1068 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
1069 MachineBasicBlock *BB) const;
1071 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1072 MachineBasicBlock *MBB) const;
1074 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1075 MachineBasicBlock *MBB) const;
1077 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1078 MachineBasicBlock *MBB) const;
1080 /// Emit nodes that will be selected as "test Op0,Op0", or something
1081 /// equivalent, for use with the given x86 condition code.
1082 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1083 SelectionDAG &DAG) const;
1085 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1086 /// equivalent, for use with the given x86 condition code.
1087 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1088 SelectionDAG &DAG) const;
1090 /// Convert a comparison if required by the subtarget.
1091 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1093 /// Use rsqrt* to speed up sqrt calculations.
1094 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1095 unsigned &RefinementSteps,
1096 bool &UseOneConstNR) const override;
1098 /// Use rcp* to speed up fdiv calculations.
1099 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1100 unsigned &RefinementSteps) const override;
1102 /// Reassociate floating point divisions into multiply by reciprocal.
1103 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
1107 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1108 const TargetLibraryInfo *libInfo);
1112 #endif // X86ISELLOWERING_H