1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
27 // X86 Specific DAG Nodes
29 // Start the numbering where the builtin ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
32 /// BSF - Bit scan forward.
33 /// BSR - Bit scan reverse.
37 /// SHLD, SHRD - Double shift instructions. These correspond to
38 /// X86::SHLDxx and X86::SHRDxx instructions.
42 /// FAND - Bitwise logical AND of floating point values. This corresponds
43 /// to X86::ANDPS or X86::ANDPD.
46 /// FOR - Bitwise logical OR of floating point values. This corresponds
47 /// to X86::ORPS or X86::ORPD.
50 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
51 /// to X86::XORPS or X86::XORPD.
54 /// FSRL - Bitwise logical right shift of floating point values. These
55 /// corresponds to X86::PSRLDQ.
58 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
59 /// integer source in memory and FP reg result. This corresponds to the
60 /// X86::FILD*m instructions. It has three inputs (token chain, address,
61 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
62 /// also produces a flag).
66 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
67 /// integer destination in memory and a FP reg source. This corresponds
68 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
69 /// has two inputs (token chain and address) and two outputs (int value
75 /// FLD - This instruction implements an extending load to FP stack slots.
76 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
77 /// operand, ptr to load from, and a ValueType node indicating the type
81 /// FST - This instruction implements a truncating store to FP stack
82 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
83 /// chain operand, value to store, address, and a ValueType to store it
87 /// CALL/TAILCALL - These operations represent an abstract X86 call
88 /// instruction, which includes a bunch of information. In particular the
89 /// operands of these node are:
91 /// #0 - The incoming token chain
93 /// #2 - The number of arg bytes the caller pushes on the stack.
94 /// #3 - The number of arg bytes the callee pops off the stack.
95 /// #4 - The value to pass in AL/AX/EAX (optional)
96 /// #5 - The value to pass in DL/DX/EDX (optional)
98 /// The result values of these nodes are:
100 /// #0 - The outgoing token chain
101 /// #1 - The first register result value (optional)
102 /// #2 - The second register result value (optional)
104 /// The CALL vs TAILCALL distinction boils down to whether the callee is
105 /// known not to modify the caller's stack frame, as is standard with
110 /// RDTSC_DAG - This operation implements the lowering for
114 /// X86 compare and logical compare instructions.
117 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
118 /// operand produced by a CMP instruction.
121 /// X86 conditional moves. Operand 1 and operand 2 are the two values
122 /// to select from (operand 1 is a R/W operand). Operand 3 is the
123 /// condition code, and operand 4 is the flag operand produced by a CMP
124 /// or TEST instruction. It also writes a flag result.
127 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
128 /// is the block to branch if condition is true, operand 3 is the
129 /// condition code, and operand 4 is the flag operand produced by a CMP
130 /// or TEST instruction.
133 /// Return with a flag operand. Operand 1 is the chain operand, operand
134 /// 2 is the number of bytes of stack to pop.
137 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
140 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
143 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
144 /// at function entry, used for PIC code.
147 /// Wrapper - A wrapper node for TargetConstantPool,
148 /// TargetExternalSymbol, and TargetGlobalAddress.
151 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
152 /// relative displacements.
155 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
156 /// i32, corresponds to X86::PEXTRB.
159 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
160 /// i32, corresponds to X86::PEXTRW.
163 /// INSERTPS - Insert any element of a 4 x float vector into any element
164 /// of a destination 4 x floatvector.
167 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
168 /// corresponds to X86::PINSRB.
171 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
172 /// corresponds to X86::PINSRW.
175 /// FMAX, FMIN - Floating point max and min.
179 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
180 /// approximation. Note that these typically require refinement
181 /// in order to obtain suitable precision.
184 // TLSADDR, THREAThread - Thread Local Storage.
185 TLSADDR, THREAD_POINTER,
187 // EH_RETURN - Exception Handling helpers.
190 /// TC_RETURN - Tail call return.
192 /// operand #1 callee (register or absolute)
193 /// operand #2 stack adjustment
194 /// operand #3 optional in flag
197 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
201 // FNSTCW16m - Store FP control world into i16 memory.
204 // VZEXT_MOVL - Vector move low and zero extend.
207 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
210 // VSHL, VSRL - Vector logical left / right shift.
213 // CMPPD, CMPPS - Vector double/float comparison.
216 // PCMP* - Vector integer comparisons.
217 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
218 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ
222 /// Define some predicates that are used for node matching.
224 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
225 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
226 bool isPSHUFDMask(SDNode *N);
228 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
229 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
230 bool isPSHUFHWMask(SDNode *N);
232 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
233 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
234 bool isPSHUFLWMask(SDNode *N);
236 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
237 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
238 bool isSHUFPMask(SDNode *N);
240 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
241 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
242 bool isMOVHLPSMask(SDNode *N);
244 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
245 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
247 bool isMOVHLPS_v_undef_Mask(SDNode *N);
249 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
250 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
251 bool isMOVLPMask(SDNode *N);
253 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
254 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
255 /// as well as MOVLHPS.
256 bool isMOVHPMask(SDNode *N);
258 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
259 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
260 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
262 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
263 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
264 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
266 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
267 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
269 bool isUNPCKL_v_undef_Mask(SDNode *N);
271 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
272 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
274 bool isUNPCKH_v_undef_Mask(SDNode *N);
276 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
277 /// specifies a shuffle of elements that is suitable for input to MOVSS,
278 /// MOVSD, and MOVD, i.e. setting the lowest element.
279 bool isMOVLMask(SDNode *N);
281 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
282 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
283 bool isMOVSHDUPMask(SDNode *N);
285 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
286 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
287 bool isMOVSLDUPMask(SDNode *N);
289 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
290 /// specifies a splat of a single element.
291 bool isSplatMask(SDNode *N);
293 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
294 /// specifies a splat of zero element.
295 bool isSplatLoMask(SDNode *N);
297 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
298 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
300 unsigned getShuffleSHUFImmediate(SDNode *N);
302 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
303 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
305 unsigned getShufflePSHUFHWImmediate(SDNode *N);
307 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
308 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
310 unsigned getShufflePSHUFLWImmediate(SDNode *N);
313 //===--------------------------------------------------------------------===//
314 // X86TargetLowering - X86 Implementation of the TargetLowering interface
315 class X86TargetLowering : public TargetLowering {
316 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
317 int RegSaveFrameIndex; // X86-64 vararg func register save area.
318 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
319 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
320 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
321 int BytesCallerReserves; // Number of arg bytes caller makes.
324 explicit X86TargetLowering(X86TargetMachine &TM);
326 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
328 SDValue getPICJumpTableRelocBase(SDValue Table,
329 SelectionDAG &DAG) const;
331 // Return the number of bytes that a function should pop when it returns (in
332 // addition to the space used by the return address).
334 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
336 // Return the number of bytes that the caller reserves for arguments passed
338 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
340 /// getStackPtrReg - Return the stack pointer register we are using: either
342 unsigned getStackPtrReg() const { return X86StackPtr; }
344 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
345 /// function arguments in the caller parameter area. For X86, aggregates
346 /// that contains are placed at 16-byte boundaries while the rest are at
347 /// 4-byte boundaries.
348 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
350 /// getOptimalMemOpType - Returns the target specific optimal type for load
351 /// and store operations as a result of memset, memcpy, and memmove
352 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
355 MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
356 bool isSrcConst, bool isSrcStr) const;
358 /// LowerOperation - Provide custom lowering hooks for some operations.
360 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
362 /// ReplaceNodeResults - Replace a node with an illegal result type
363 /// with a new node built out of custom code.
365 virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
368 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
370 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
371 MachineBasicBlock *MBB);
374 /// getTargetNodeName - This method returns the name of a target specific
376 virtual const char *getTargetNodeName(unsigned Opcode) const;
378 /// getSetCCResultType - Return the ISD::SETCC ValueType
379 virtual MVT getSetCCResultType(const SDValue &) const;
381 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
382 /// in Mask are known to be either zero or one and return them in the
383 /// KnownZero/KnownOne bitsets.
384 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
388 const SelectionDAG &DAG,
389 unsigned Depth = 0) const;
392 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
394 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
396 ConstraintType getConstraintType(const std::string &Constraint) const;
398 std::vector<unsigned>
399 getRegClassForInlineAsmConstraint(const std::string &Constraint,
402 virtual const char *LowerXConstraint(MVT ConstraintVT) const;
404 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
405 /// vector. If it is invalid, don't add anything to Ops.
406 virtual void LowerAsmOperandForConstraint(SDValue Op,
407 char ConstraintLetter,
408 std::vector<SDValue> &Ops,
409 SelectionDAG &DAG) const;
411 /// getRegForInlineAsmConstraint - Given a physical register constraint
412 /// (e.g. {edx}), return the register number and the register class for the
413 /// register. This should only be used for C_Register constraints. On
414 /// error, this returns a register number of 0.
415 std::pair<unsigned, const TargetRegisterClass*>
416 getRegForInlineAsmConstraint(const std::string &Constraint,
419 /// isLegalAddressingMode - Return true if the addressing mode represented
420 /// by AM is legal for this target, for a load/store of the specified type.
421 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
423 /// isTruncateFree - Return true if it's free to truncate a value of
424 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
425 /// register EAX to i16 by referencing its sub-register AX.
426 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
427 virtual bool isTruncateFree(MVT VT1, MVT VT2) const;
429 /// isShuffleMaskLegal - Targets can use this to indicate that they only
430 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
431 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
432 /// values are assumed to be legal.
433 virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const;
435 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
436 /// used by Targets can use this to indicate if there is a suitable
437 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
439 virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
440 MVT EVT, SelectionDAG &DAG) const;
442 /// ShouldShrinkFPConstant - If true, then instruction selection should
443 /// seek to shrink the FP constant of the specified type to a smaller type
444 /// in order to save space and / or reduce runtime.
445 virtual bool ShouldShrinkFPConstant(MVT VT) const {
446 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
447 // expensive than a straight movsd. On the other hand, it's important to
448 // shrink long double fp constant since fldt is very slow.
449 return !X86ScalarSSEf64 || VT == MVT::f80;
452 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
453 /// for tail call optimization. Target which want to do tail call
454 /// optimization should implement this function.
455 virtual bool IsEligibleForTailCallOptimization(SDValue Call,
457 SelectionDAG &DAG) const;
459 virtual const X86Subtarget* getSubtarget() {
463 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
464 /// computed in an SSE register, not on the X87 floating point stack.
465 bool isScalarFPTypeInSSEReg(MVT VT) const {
466 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
467 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
471 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
472 /// make the right decision when generating code for different targets.
473 const X86Subtarget *Subtarget;
474 const X86RegisterInfo *RegInfo;
476 /// X86StackPtr - X86 physical register used as stack ptr.
477 unsigned X86StackPtr;
479 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
480 /// floating point ops.
481 /// When SSE is available, use it for f32 operations.
482 /// When SSE2 is available, use it for f64 operations.
483 bool X86ScalarSSEf32;
484 bool X86ScalarSSEf64;
486 SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, SDNode*TheCall,
487 unsigned CallingConv, SelectionDAG &DAG);
489 SDValue LowerMemArgument(SDValue Op, SelectionDAG &DAG,
490 const CCValAssign &VA, MachineFrameInfo *MFI,
491 unsigned CC, SDValue Root, unsigned i);
493 SDValue LowerMemOpCallTo(SDValue Op, SelectionDAG &DAG,
494 const SDValue &StackPtr,
495 const CCValAssign &VA, SDValue Chain,
498 // Call lowering helpers.
499 bool IsCalleePop(SDValue Op);
500 bool CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall);
501 bool CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall);
502 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
503 SDValue Chain, bool IsTailCall, bool Is64Bit,
506 CCAssignFn *CCAssignFnForNode(SDValue Op) const;
507 NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDValue Op);
508 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
510 std::pair<SDValue,SDValue> FP_TO_SINTHelper(SDValue Op,
513 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
514 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
515 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
516 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
517 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
518 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
519 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
520 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
521 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
522 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
523 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
524 SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
525 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
526 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
527 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG);
528 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG);
529 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG);
530 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
531 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG);
532 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
533 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
534 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG);
535 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
536 SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
537 SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
538 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
539 SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
540 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
541 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
542 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG);
543 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
544 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
545 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
546 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG);
547 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG);
548 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
549 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
550 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG);
551 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
552 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
553 SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
554 SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
555 SDNode *ExpandATOMIC_CMP_SWAP(SDNode *N, SelectionDAG &DAG);
556 SDNode *ExpandATOMIC_LOAD_SUB(SDNode *N, SelectionDAG &DAG);
558 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG,
560 SDValue Dst, SDValue Src,
561 SDValue Size, unsigned Align,
562 const Value *DstSV, uint64_t DstSVOff);
563 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG,
565 SDValue Dst, SDValue Src,
566 SDValue Size, unsigned Align,
568 const Value *DstSV, uint64_t DstSVOff,
569 const Value *SrcSV, uint64_t SrcSVOff);
571 /// Utility function to emit atomic bitwise operations (and, or, xor).
572 // It takes the bitwise instruction to expand, the associated machine basic
573 // block, and the associated X86 opcodes for reg/reg and reg/imm.
574 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
575 MachineInstr *BInstr,
576 MachineBasicBlock *BB,
579 bool invSrc = false);
581 /// Utility function to emit atomic min and max. It takes the min/max
582 // instruction to expand, the associated basic block, and the associated
583 // cmov opcode for moving the min or max value.
584 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
585 MachineBasicBlock *BB,
590 #endif // X86ISELLOWERING_H