1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 #define DEBUG_TYPE "x86-isel"
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
63 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
64 SelectionDAG &DAG, SDLoc dl,
65 unsigned vectorWidth) {
66 assert((vectorWidth == 128 || vectorWidth == 256) &&
67 "Unsupported vector width");
68 EVT VT = Vec.getValueType();
69 EVT ElVT = VT.getVectorElementType();
70 unsigned Factor = VT.getSizeInBits()/vectorWidth;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
79 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
81 // This is the index of the first element of the vectorWidth-bit chunk
83 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
86 // If the input is a buildvector just emit a smaller one.
87 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
88 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
89 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
92 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
99 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
100 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
101 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
102 /// instructions or a simple subregister reference. Idx is an index in the
103 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
104 /// lowering EXTRACT_VECTOR_ELT operations easier.
105 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
106 SelectionDAG &DAG, SDLoc dl) {
107 assert((Vec.getValueType().is256BitVector() ||
108 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
109 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
112 /// Generate a DAG to grab 256-bits from a 512-bit vector.
113 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
114 SelectionDAG &DAG, SDLoc dl) {
115 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
116 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
119 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
120 unsigned IdxVal, SelectionDAG &DAG,
121 SDLoc dl, unsigned vectorWidth) {
122 assert((vectorWidth == 128 || vectorWidth == 256) &&
123 "Unsupported vector width");
124 // Inserting UNDEF is Result
125 if (Vec.getOpcode() == ISD::UNDEF)
127 EVT VT = Vec.getValueType();
128 EVT ElVT = VT.getVectorElementType();
129 EVT ResultVT = Result.getValueType();
131 // Insert the relevant vectorWidth bits.
132 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
134 // This is the index of the first element of the vectorWidth-bit chunk
136 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
139 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
140 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
143 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
144 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
145 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
146 /// simple superregister reference. Idx is an index in the 128 bits
147 /// we want. It need not be aligned to a 128-bit bounday. That makes
148 /// lowering INSERT_VECTOR_ELT operations easier.
149 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
150 unsigned IdxVal, SelectionDAG &DAG,
152 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
153 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
156 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
157 unsigned IdxVal, SelectionDAG &DAG,
159 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
160 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
163 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
164 /// instructions. This is used because creating CONCAT_VECTOR nodes of
165 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
166 /// large BUILD_VECTORS.
167 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
168 unsigned NumElems, SelectionDAG &DAG,
170 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
171 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
174 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
175 unsigned NumElems, SelectionDAG &DAG,
177 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
178 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
181 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
182 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
183 bool is64Bit = Subtarget->is64Bit();
185 if (Subtarget->isTargetMacho()) {
187 return new X86_64MachoTargetObjectFile();
188 return new TargetLoweringObjectFileMachO();
191 if (Subtarget->isTargetLinux())
192 return new X86LinuxTargetObjectFile();
193 if (Subtarget->isTargetELF())
194 return new TargetLoweringObjectFileELF();
195 if (Subtarget->isTargetKnownWindowsMSVC())
196 return new X86WindowsTargetObjectFile();
197 if (Subtarget->isTargetCOFF())
198 return new TargetLoweringObjectFileCOFF();
199 llvm_unreachable("unknown subtarget type");
202 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
203 : TargetLowering(TM, createTLOF(TM)) {
204 Subtarget = &TM.getSubtarget<X86Subtarget>();
205 X86ScalarSSEf64 = Subtarget->hasSSE2();
206 X86ScalarSSEf32 = Subtarget->hasSSE1();
207 TD = getDataLayout();
209 resetOperationActions();
212 void X86TargetLowering::resetOperationActions() {
213 const TargetMachine &TM = getTargetMachine();
214 static bool FirstTimeThrough = true;
216 // If none of the target options have changed, then we don't need to reset the
217 // operation actions.
218 if (!FirstTimeThrough && TO == TM.Options) return;
220 if (!FirstTimeThrough) {
221 // Reinitialize the actions.
223 FirstTimeThrough = false;
228 // Set up the TargetLowering object.
229 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
231 // X86 is weird, it always uses i8 for shift amounts and setcc results.
232 setBooleanContents(ZeroOrOneBooleanContent);
233 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
234 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
236 // For 64-bit since we have so many registers use the ILP scheduler, for
237 // 32-bit code use the register pressure specific scheduling.
238 // For Atom, always use ILP scheduling.
239 if (Subtarget->isAtom())
240 setSchedulingPreference(Sched::ILP);
241 else if (Subtarget->is64Bit())
242 setSchedulingPreference(Sched::ILP);
244 setSchedulingPreference(Sched::RegPressure);
245 const X86RegisterInfo *RegInfo =
246 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
247 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
249 // Bypass expensive divides on Atom when compiling with O2
250 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
251 addBypassSlowDiv(32, 8);
252 if (Subtarget->is64Bit())
253 addBypassSlowDiv(64, 16);
256 if (Subtarget->isTargetKnownWindowsMSVC()) {
257 // Setup Windows compiler runtime calls.
258 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
259 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
260 setLibcallName(RTLIB::SREM_I64, "_allrem");
261 setLibcallName(RTLIB::UREM_I64, "_aullrem");
262 setLibcallName(RTLIB::MUL_I64, "_allmul");
263 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
266 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
269 // The _ftol2 runtime function has an unusual calling conv, which
270 // is modeled by a special pseudo-instruction.
271 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
273 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
274 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
277 if (Subtarget->isTargetDarwin()) {
278 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
279 setUseUnderscoreSetJmp(false);
280 setUseUnderscoreLongJmp(false);
281 } else if (Subtarget->isTargetWindowsGNU()) {
282 // MS runtime is weird: it exports _setjmp, but longjmp!
283 setUseUnderscoreSetJmp(true);
284 setUseUnderscoreLongJmp(false);
286 setUseUnderscoreSetJmp(true);
287 setUseUnderscoreLongJmp(true);
290 // Set up the register classes.
291 addRegisterClass(MVT::i8, &X86::GR8RegClass);
292 addRegisterClass(MVT::i16, &X86::GR16RegClass);
293 addRegisterClass(MVT::i32, &X86::GR32RegClass);
294 if (Subtarget->is64Bit())
295 addRegisterClass(MVT::i64, &X86::GR64RegClass);
297 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
299 // We don't accept any truncstore of integer registers.
300 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
301 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
302 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
303 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
304 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
305 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
307 // SETOEQ and SETUNE require checking two conditions.
308 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
311 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
315 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
317 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 } else if (!TM.Options.UseSoftFloat) {
325 // We have an algorithm for SSE2->double, and we turn this into a
326 // 64-bit FILD followed by conditional FADD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 // We have an algorithm for SSE2, and we turn this into a 64-bit
329 // FILD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
333 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
335 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
336 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
338 if (!TM.Options.UseSoftFloat) {
339 // SSE has no i16 to fp conversion, only i32
340 if (X86ScalarSSEf32) {
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
342 // f32 and f64 cases are Legal, f80 case is not
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
353 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
354 // are Legal, f80 is custom lowered.
355 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
356 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
358 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
360 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
361 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
363 if (X86ScalarSSEf32) {
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
365 // f32 and f64 cases are Legal, f80 case is not
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 // Handle FP_TO_UINT by promoting the destination to a larger signed
374 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
378 if (Subtarget->is64Bit()) {
379 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
381 } else if (!TM.Options.UseSoftFloat) {
382 // Since AVX is a superset of SSE3, only check for SSE here.
383 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
384 // Expand FP_TO_UINT into a select.
385 // FIXME: We would like to use a Custom expander here eventually to do
386 // the optimal thing for SSE vs. the default expansion in the legalizer.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
389 // With SSE3 we can use fisttpll to convert to a signed i64; without
390 // SSE, we're stuck with a fistpll.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
394 if (isTargetFTOL()) {
395 // Use the _ftol2 runtime function, which has a pseudo-instruction
396 // to handle its weird calling convention.
397 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
400 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
401 if (!X86ScalarSSEf64) {
402 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
403 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
406 // Without SSE, i64->f64 goes through memory.
407 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
411 // Scalar integer divide and remainder are lowered to use operations that
412 // produce two results, to match the available instructions. This exposes
413 // the two-result form to trivial CSE, which is able to combine x/y and x%y
414 // into a single instruction.
416 // Scalar integer multiply-high is also lowered to use two-result
417 // operations, to match the available instructions. However, plain multiply
418 // (low) operations are left as Legal, as there are single-result
419 // instructions for this in x86. Using the two-result multiply instructions
420 // when both high and low results are needed must be arranged by dagcombine.
421 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
423 setOperationAction(ISD::MULHS, VT, Expand);
424 setOperationAction(ISD::MULHU, VT, Expand);
425 setOperationAction(ISD::SDIV, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::SREM, VT, Expand);
428 setOperationAction(ISD::UREM, VT, Expand);
430 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
431 setOperationAction(ISD::ADDC, VT, Custom);
432 setOperationAction(ISD::ADDE, VT, Custom);
433 setOperationAction(ISD::SUBC, VT, Custom);
434 setOperationAction(ISD::SUBE, VT, Custom);
437 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
438 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
439 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
446 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
447 if (Subtarget->is64Bit())
448 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
449 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
450 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
451 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
452 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
453 setOperationAction(ISD::FREM , MVT::f32 , Expand);
454 setOperationAction(ISD::FREM , MVT::f64 , Expand);
455 setOperationAction(ISD::FREM , MVT::f80 , Expand);
456 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
458 // Promote the i8 variants and force them on up to i32 which has a shorter
460 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
461 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
463 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
464 if (Subtarget->hasBMI()) {
465 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
466 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
467 if (Subtarget->is64Bit())
468 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
470 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
471 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
472 if (Subtarget->is64Bit())
473 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
476 if (Subtarget->hasLZCNT()) {
477 // When promoting the i8 variants, force them to i32 for a shorter
479 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
480 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
482 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
483 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
489 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
490 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
494 if (Subtarget->is64Bit()) {
495 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
496 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
500 if (Subtarget->hasPOPCNT()) {
501 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
503 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
504 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
505 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
506 if (Subtarget->is64Bit())
507 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
510 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
512 if (!Subtarget->hasMOVBE())
513 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
515 // These should be promoted to a larger select which is supported.
516 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
517 // X86 wants to expand cmov itself.
518 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
519 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
520 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
521 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
522 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
523 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
524 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
526 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
527 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
528 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
529 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
530 if (Subtarget->is64Bit()) {
531 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
532 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
534 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
535 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
536 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
537 // support continuation, user-level threading, and etc.. As a result, no
538 // other SjLj exception interfaces are implemented and please don't build
539 // your own exception handling based on them.
540 // LLVM/Clang supports zero-cost DWARF exception handling.
541 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
542 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
545 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
546 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
547 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
548 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
549 if (Subtarget->is64Bit())
550 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
551 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
552 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
553 if (Subtarget->is64Bit()) {
554 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
555 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
556 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
557 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
558 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
560 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
561 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
562 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
563 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
564 if (Subtarget->is64Bit()) {
565 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
566 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
567 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
570 if (Subtarget->hasSSE1())
571 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
573 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
575 // Expand certain atomics
576 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
578 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
580 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
583 if (!Subtarget->is64Bit()) {
584 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
590 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
591 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
592 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
593 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
594 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
595 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
598 if (Subtarget->hasCmpxchg16b()) {
599 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
602 // FIXME - use subtarget debug flags
603 if (!Subtarget->isTargetDarwin() &&
604 !Subtarget->isTargetELF() &&
605 !Subtarget->isTargetCygMing()) {
606 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
609 if (Subtarget->is64Bit()) {
610 setExceptionPointerRegister(X86::RAX);
611 setExceptionSelectorRegister(X86::RDX);
613 setExceptionPointerRegister(X86::EAX);
614 setExceptionSelectorRegister(X86::EDX);
616 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
617 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
619 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
620 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
622 setOperationAction(ISD::TRAP, MVT::Other, Legal);
623 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
625 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
626 setOperationAction(ISD::VASTART , MVT::Other, Custom);
627 setOperationAction(ISD::VAEND , MVT::Other, Expand);
628 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
629 // TargetInfo::X86_64ABIBuiltinVaList
630 setOperationAction(ISD::VAARG , MVT::Other, Custom);
631 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
633 // TargetInfo::CharPtrBuiltinVaList
634 setOperationAction(ISD::VAARG , MVT::Other, Expand);
635 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
638 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
639 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
641 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
642 MVT::i64 : MVT::i32, Custom);
644 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
645 // f32 and f64 use SSE.
646 // Set up the FP register classes.
647 addRegisterClass(MVT::f32, &X86::FR32RegClass);
648 addRegisterClass(MVT::f64, &X86::FR64RegClass);
650 // Use ANDPD to simulate FABS.
651 setOperationAction(ISD::FABS , MVT::f64, Custom);
652 setOperationAction(ISD::FABS , MVT::f32, Custom);
654 // Use XORP to simulate FNEG.
655 setOperationAction(ISD::FNEG , MVT::f64, Custom);
656 setOperationAction(ISD::FNEG , MVT::f32, Custom);
658 // Use ANDPD and ORPD to simulate FCOPYSIGN.
659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
662 // Lower this to FGETSIGNx86 plus an AND.
663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
666 // We don't support sin/cos/fmod
667 setOperationAction(ISD::FSIN , MVT::f64, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN , MVT::f32, Expand);
671 setOperationAction(ISD::FCOS , MVT::f32, Expand);
672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
674 // Expand FP immediates into loads from the stack, except for the special
676 addLegalFPImmediate(APFloat(+0.0)); // xorpd
677 addLegalFPImmediate(APFloat(+0.0f)); // xorps
678 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
679 // Use SSE for f32, x87 for f64.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f32, &X86::FR32RegClass);
682 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
684 // Use ANDPS to simulate FABS.
685 setOperationAction(ISD::FABS , MVT::f32, Custom);
687 // Use XORP to simulate FNEG.
688 setOperationAction(ISD::FNEG , MVT::f32, Custom);
690 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
692 // Use ANDPS and ORPS to simulate FCOPYSIGN.
693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
696 // We don't support sin/cos/fmod
697 setOperationAction(ISD::FSIN , MVT::f32, Expand);
698 setOperationAction(ISD::FCOS , MVT::f32, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
701 // Special cases we handle for FP constants.
702 addLegalFPImmediate(APFloat(+0.0f)); // xorps
703 addLegalFPImmediate(APFloat(+0.0)); // FLD0
704 addLegalFPImmediate(APFloat(+1.0)); // FLD1
705 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
706 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
708 if (!TM.Options.UnsafeFPMath) {
709 setOperationAction(ISD::FSIN , MVT::f64, Expand);
710 setOperationAction(ISD::FCOS , MVT::f64, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
713 } else if (!TM.Options.UseSoftFloat) {
714 // f32 and f64 in x87.
715 // Set up the FP register classes.
716 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
717 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
719 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
720 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
724 if (!TM.Options.UnsafeFPMath) {
725 setOperationAction(ISD::FSIN , MVT::f64, Expand);
726 setOperationAction(ISD::FSIN , MVT::f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
732 addLegalFPImmediate(APFloat(+0.0)); // FLD0
733 addLegalFPImmediate(APFloat(+1.0)); // FLD1
734 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
735 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
736 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
737 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
738 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
739 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
742 // We don't support FMA.
743 setOperationAction(ISD::FMA, MVT::f64, Expand);
744 setOperationAction(ISD::FMA, MVT::f32, Expand);
746 // Long double always uses X87.
747 if (!TM.Options.UseSoftFloat) {
748 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
752 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
753 addLegalFPImmediate(TmpFlt); // FLD0
755 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
758 APFloat TmpFlt2(+1.0);
759 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
761 addLegalFPImmediate(TmpFlt2); // FLD1
762 TmpFlt2.changeSign();
763 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
766 if (!TM.Options.UnsafeFPMath) {
767 setOperationAction(ISD::FSIN , MVT::f80, Expand);
768 setOperationAction(ISD::FCOS , MVT::f80, Expand);
769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
773 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
775 setOperationAction(ISD::FRINT, MVT::f80, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
777 setOperationAction(ISD::FMA, MVT::f80, Expand);
780 // Always use a library call for pow.
781 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
782 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
785 setOperationAction(ISD::FLOG, MVT::f80, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
788 setOperationAction(ISD::FEXP, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
791 // First set operation action for all vector types to either promote
792 // (for widening) or expand (for scalarization). Then we will selectively
793 // turn on ones that can be effectively codegen'd.
794 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
796 MVT VT = (MVT::SimpleValueType)i;
797 setOperationAction(ISD::ADD , VT, Expand);
798 setOperationAction(ISD::SUB , VT, Expand);
799 setOperationAction(ISD::FADD, VT, Expand);
800 setOperationAction(ISD::FNEG, VT, Expand);
801 setOperationAction(ISD::FSUB, VT, Expand);
802 setOperationAction(ISD::MUL , VT, Expand);
803 setOperationAction(ISD::FMUL, VT, Expand);
804 setOperationAction(ISD::SDIV, VT, Expand);
805 setOperationAction(ISD::UDIV, VT, Expand);
806 setOperationAction(ISD::FDIV, VT, Expand);
807 setOperationAction(ISD::SREM, VT, Expand);
808 setOperationAction(ISD::UREM, VT, Expand);
809 setOperationAction(ISD::LOAD, VT, Expand);
810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
812 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
813 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
814 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::FABS, VT, Expand);
816 setOperationAction(ISD::FSIN, VT, Expand);
817 setOperationAction(ISD::FSINCOS, VT, Expand);
818 setOperationAction(ISD::FCOS, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FREM, VT, Expand);
821 setOperationAction(ISD::FMA, VT, Expand);
822 setOperationAction(ISD::FPOWI, VT, Expand);
823 setOperationAction(ISD::FSQRT, VT, Expand);
824 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
825 setOperationAction(ISD::FFLOOR, VT, Expand);
826 setOperationAction(ISD::FCEIL, VT, Expand);
827 setOperationAction(ISD::FTRUNC, VT, Expand);
828 setOperationAction(ISD::FRINT, VT, Expand);
829 setOperationAction(ISD::FNEARBYINT, VT, Expand);
830 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
831 setOperationAction(ISD::MULHS, VT, Expand);
832 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::MULHU, VT, Expand);
834 setOperationAction(ISD::SDIVREM, VT, Expand);
835 setOperationAction(ISD::UDIVREM, VT, Expand);
836 setOperationAction(ISD::FPOW, VT, Expand);
837 setOperationAction(ISD::CTPOP, VT, Expand);
838 setOperationAction(ISD::CTTZ, VT, Expand);
839 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::CTLZ, VT, Expand);
841 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
842 setOperationAction(ISD::SHL, VT, Expand);
843 setOperationAction(ISD::SRA, VT, Expand);
844 setOperationAction(ISD::SRL, VT, Expand);
845 setOperationAction(ISD::ROTL, VT, Expand);
846 setOperationAction(ISD::ROTR, VT, Expand);
847 setOperationAction(ISD::BSWAP, VT, Expand);
848 setOperationAction(ISD::SETCC, VT, Expand);
849 setOperationAction(ISD::FLOG, VT, Expand);
850 setOperationAction(ISD::FLOG2, VT, Expand);
851 setOperationAction(ISD::FLOG10, VT, Expand);
852 setOperationAction(ISD::FEXP, VT, Expand);
853 setOperationAction(ISD::FEXP2, VT, Expand);
854 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
855 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
856 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
859 setOperationAction(ISD::TRUNCATE, VT, Expand);
860 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
861 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
862 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
863 setOperationAction(ISD::VSELECT, VT, Expand);
864 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
865 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
866 setTruncStoreAction(VT,
867 (MVT::SimpleValueType)InnerVT, Expand);
868 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
870 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
873 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
874 // with -msoft-float, disable use of MMX as well.
875 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
876 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
877 // No operations on x86mmx supported, everything uses intrinsics.
880 // MMX-sized vectors (other than x86mmx) are expected to be expanded
881 // into smaller operations.
882 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
883 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
884 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
885 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
886 setOperationAction(ISD::AND, MVT::v8i8, Expand);
887 setOperationAction(ISD::AND, MVT::v4i16, Expand);
888 setOperationAction(ISD::AND, MVT::v2i32, Expand);
889 setOperationAction(ISD::AND, MVT::v1i64, Expand);
890 setOperationAction(ISD::OR, MVT::v8i8, Expand);
891 setOperationAction(ISD::OR, MVT::v4i16, Expand);
892 setOperationAction(ISD::OR, MVT::v2i32, Expand);
893 setOperationAction(ISD::OR, MVT::v1i64, Expand);
894 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
895 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
896 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
897 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
901 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
903 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
904 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
905 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
906 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
910 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
912 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
913 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
915 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
916 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
917 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
918 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
919 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
920 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
921 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
922 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
923 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
924 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
925 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
926 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
929 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
930 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
932 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
933 // registers cannot be used even for integer operations.
934 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
935 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
936 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
937 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
939 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
940 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
941 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
942 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
943 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
944 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
945 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
946 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
947 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
948 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
949 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
950 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
951 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
952 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
953 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
954 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
955 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
956 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
957 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
958 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
959 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
960 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
962 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
963 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
964 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
965 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
967 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
968 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
969 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
970 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
971 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
973 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
974 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
975 MVT VT = (MVT::SimpleValueType)i;
976 // Do not attempt to custom lower non-power-of-2 vectors
977 if (!isPowerOf2_32(VT.getVectorNumElements()))
979 // Do not attempt to custom lower non-128-bit vectors
980 if (!VT.is128BitVector())
982 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
984 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
987 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
988 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
989 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
990 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
994 if (Subtarget->is64Bit()) {
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
996 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
999 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1000 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1001 MVT VT = (MVT::SimpleValueType)i;
1003 // Do not attempt to promote non-128-bit vectors
1004 if (!VT.is128BitVector())
1007 setOperationAction(ISD::AND, VT, Promote);
1008 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1009 setOperationAction(ISD::OR, VT, Promote);
1010 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1011 setOperationAction(ISD::XOR, VT, Promote);
1012 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1013 setOperationAction(ISD::LOAD, VT, Promote);
1014 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1015 setOperationAction(ISD::SELECT, VT, Promote);
1016 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1019 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1021 // Custom lower v2i64 and v2f64 selects.
1022 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1023 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1024 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1025 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1027 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1028 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1030 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1031 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1032 // As there is no 64-bit GPR available, we need build a special custom
1033 // sequence to convert from v2i32 to v2f32.
1034 if (!Subtarget->is64Bit())
1035 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1037 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1038 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1040 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1042 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1043 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1044 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1047 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1048 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1049 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1050 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1051 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1052 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1053 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1054 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1055 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1056 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1057 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1059 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1060 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1061 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1062 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1063 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1064 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1065 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1066 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1067 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1068 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1070 // FIXME: Do we need to handle scalar-to-vector here?
1071 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1073 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1074 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1075 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1076 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1077 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1078 // There is no BLENDI for byte vectors. We don't need to custom lower
1079 // some vselects for now.
1080 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1082 // i8 and i16 vectors are custom , because the source register and source
1083 // source memory operand types are not the same width. f32 vectors are
1084 // custom since the immediate controlling the insert encodes additional
1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1087 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1088 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1089 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1091 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1092 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1093 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1094 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1096 // FIXME: these should be Legal but thats only for the case where
1097 // the index is constant. For now custom expand to deal with that.
1098 if (Subtarget->is64Bit()) {
1099 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1100 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1104 if (Subtarget->hasSSE2()) {
1105 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1106 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1108 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1109 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1111 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1112 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1114 // In the customized shift lowering, the legal cases in AVX2 will be
1116 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1117 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1119 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1120 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1122 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1125 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1126 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1127 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1128 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1129 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1130 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1131 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1133 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1134 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1135 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1137 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1139 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1140 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1141 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1142 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1143 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1144 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1145 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1146 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1147 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1148 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1150 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1152 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1153 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1154 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1155 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1156 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1157 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1158 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1159 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1160 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1161 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1163 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1164 // even though v8i16 is a legal type.
1165 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1166 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1167 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1169 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1170 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1171 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1173 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1174 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1176 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1178 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1179 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1181 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1182 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1184 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1185 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1187 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1188 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1189 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1190 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1192 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1193 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1194 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1196 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1197 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1198 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1199 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1201 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1202 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1203 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1204 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1205 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1206 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1207 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1208 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1209 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1210 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1211 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1212 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1214 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1215 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1216 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1217 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1218 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1219 setOperationAction(ISD::FMA, MVT::f32, Legal);
1220 setOperationAction(ISD::FMA, MVT::f64, Legal);
1223 if (Subtarget->hasInt256()) {
1224 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1225 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1226 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1227 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1229 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1230 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1231 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1232 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1234 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1235 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1236 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1237 // Don't lower v32i8 because there is no 128-bit byte mul
1239 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1240 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1241 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1242 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1244 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1247 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1248 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1249 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1250 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1252 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1253 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1255 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1257 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1258 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1259 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1260 // Don't lower v32i8 because there is no 128-bit byte mul
1263 // In the customized shift lowering, the legal cases in AVX2 will be
1265 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1266 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1268 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1269 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1271 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1273 // Custom lower several nodes for 256-bit types.
1274 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1275 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1276 MVT VT = (MVT::SimpleValueType)i;
1278 // Extract subvector is special because the value type
1279 // (result) is 128-bit but the source is 256-bit wide.
1280 if (VT.is128BitVector())
1281 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1283 // Do not attempt to custom lower other non-256-bit vectors
1284 if (!VT.is256BitVector())
1287 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1288 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1289 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1290 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1291 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1292 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1293 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1296 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1297 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1298 MVT VT = (MVT::SimpleValueType)i;
1300 // Do not attempt to promote non-256-bit vectors
1301 if (!VT.is256BitVector())
1304 setOperationAction(ISD::AND, VT, Promote);
1305 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1306 setOperationAction(ISD::OR, VT, Promote);
1307 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1308 setOperationAction(ISD::XOR, VT, Promote);
1309 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1310 setOperationAction(ISD::LOAD, VT, Promote);
1311 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1312 setOperationAction(ISD::SELECT, VT, Promote);
1313 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1317 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1318 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1319 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1320 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1321 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1323 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1324 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1325 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1327 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1328 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1329 setOperationAction(ISD::XOR, MVT::i1, Legal);
1330 setOperationAction(ISD::OR, MVT::i1, Legal);
1331 setOperationAction(ISD::AND, MVT::i1, Legal);
1332 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1333 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1334 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1335 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1336 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1337 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1339 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1341 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1343 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1346 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1348 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1350 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1352 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1355 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1356 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1357 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1359 if (Subtarget->is64Bit()) {
1360 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1361 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1362 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1363 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1365 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1366 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1367 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1368 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1369 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1371 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1372 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1373 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1374 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1376 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1377 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1378 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1379 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1380 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1381 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1382 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1383 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1384 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1385 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1386 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1387 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1388 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1390 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1391 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1392 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1393 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1394 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1395 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1397 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1398 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1400 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1402 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1403 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1404 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1405 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1406 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1407 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1408 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1409 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1410 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1412 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1413 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1415 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1416 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1418 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1420 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1421 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1423 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1424 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1426 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1427 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1429 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1430 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1431 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1432 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1433 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1434 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1436 // Custom lower several nodes.
1437 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1438 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1439 MVT VT = (MVT::SimpleValueType)i;
1441 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1442 // Extract subvector is special because the value type
1443 // (result) is 256/128-bit but the source is 512-bit wide.
1444 if (VT.is128BitVector() || VT.is256BitVector())
1445 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1447 if (VT.getVectorElementType() == MVT::i1)
1448 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1450 // Do not attempt to custom lower other non-512-bit vectors
1451 if (!VT.is512BitVector())
1454 if ( EltSize >= 32) {
1455 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1456 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1457 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1458 setOperationAction(ISD::VSELECT, VT, Legal);
1459 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1461 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1464 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1465 MVT VT = (MVT::SimpleValueType)i;
1467 // Do not attempt to promote non-256-bit vectors
1468 if (!VT.is512BitVector())
1471 setOperationAction(ISD::SELECT, VT, Promote);
1472 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1476 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1477 // of this type with custom code.
1478 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1479 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1480 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1484 // We want to custom lower some of our intrinsics.
1485 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1486 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1487 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1488 if (!Subtarget->is64Bit())
1489 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1491 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1492 // handle type legalization for these operations here.
1494 // FIXME: We really should do custom legalization for addition and
1495 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1496 // than generic legalization for 64-bit multiplication-with-overflow, though.
1497 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1498 // Add/Sub/Mul with overflow operations are custom lowered.
1500 setOperationAction(ISD::SADDO, VT, Custom);
1501 setOperationAction(ISD::UADDO, VT, Custom);
1502 setOperationAction(ISD::SSUBO, VT, Custom);
1503 setOperationAction(ISD::USUBO, VT, Custom);
1504 setOperationAction(ISD::SMULO, VT, Custom);
1505 setOperationAction(ISD::UMULO, VT, Custom);
1508 // There are no 8-bit 3-address imul/mul instructions
1509 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1510 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1512 if (!Subtarget->is64Bit()) {
1513 // These libcalls are not available in 32-bit.
1514 setLibcallName(RTLIB::SHL_I128, nullptr);
1515 setLibcallName(RTLIB::SRL_I128, nullptr);
1516 setLibcallName(RTLIB::SRA_I128, nullptr);
1519 // Combine sin / cos into one node or libcall if possible.
1520 if (Subtarget->hasSinCos()) {
1521 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1522 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1523 if (Subtarget->isTargetDarwin()) {
1524 // For MacOSX, we don't want to the normal expansion of a libcall to
1525 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1527 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1528 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1532 if (Subtarget->isTargetWin64()) {
1533 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1534 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1535 setOperationAction(ISD::SREM, MVT::i128, Custom);
1536 setOperationAction(ISD::UREM, MVT::i128, Custom);
1537 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1538 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1541 // We have target-specific dag combine patterns for the following nodes:
1542 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1543 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1544 setTargetDAGCombine(ISD::VSELECT);
1545 setTargetDAGCombine(ISD::SELECT);
1546 setTargetDAGCombine(ISD::SHL);
1547 setTargetDAGCombine(ISD::SRA);
1548 setTargetDAGCombine(ISD::SRL);
1549 setTargetDAGCombine(ISD::OR);
1550 setTargetDAGCombine(ISD::AND);
1551 setTargetDAGCombine(ISD::ADD);
1552 setTargetDAGCombine(ISD::FADD);
1553 setTargetDAGCombine(ISD::FSUB);
1554 setTargetDAGCombine(ISD::FMA);
1555 setTargetDAGCombine(ISD::SUB);
1556 setTargetDAGCombine(ISD::LOAD);
1557 setTargetDAGCombine(ISD::STORE);
1558 setTargetDAGCombine(ISD::ZERO_EXTEND);
1559 setTargetDAGCombine(ISD::ANY_EXTEND);
1560 setTargetDAGCombine(ISD::SIGN_EXTEND);
1561 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1562 setTargetDAGCombine(ISD::TRUNCATE);
1563 setTargetDAGCombine(ISD::SINT_TO_FP);
1564 setTargetDAGCombine(ISD::SETCC);
1565 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1566 if (Subtarget->is64Bit())
1567 setTargetDAGCombine(ISD::MUL);
1568 setTargetDAGCombine(ISD::XOR);
1570 computeRegisterProperties();
1572 // On Darwin, -Os means optimize for size without hurting performance,
1573 // do not reduce the limit.
1574 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1575 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1576 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1577 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1578 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1579 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1580 setPrefLoopAlignment(4); // 2^4 bytes.
1582 // Predictable cmov don't hurt on atom because it's in-order.
1583 PredictableSelectIsExpensive = !Subtarget->isAtom();
1585 setPrefFunctionAlignment(4); // 2^4 bytes.
1588 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1590 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1592 if (Subtarget->hasAVX512())
1593 switch(VT.getVectorNumElements()) {
1594 case 8: return MVT::v8i1;
1595 case 16: return MVT::v16i1;
1598 return VT.changeVectorElementTypeToInteger();
1601 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1602 /// the desired ByVal argument alignment.
1603 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1606 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1607 if (VTy->getBitWidth() == 128)
1609 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1610 unsigned EltAlign = 0;
1611 getMaxByValAlign(ATy->getElementType(), EltAlign);
1612 if (EltAlign > MaxAlign)
1613 MaxAlign = EltAlign;
1614 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1615 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1616 unsigned EltAlign = 0;
1617 getMaxByValAlign(STy->getElementType(i), EltAlign);
1618 if (EltAlign > MaxAlign)
1619 MaxAlign = EltAlign;
1626 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1627 /// function arguments in the caller parameter area. For X86, aggregates
1628 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1629 /// are at 4-byte boundaries.
1630 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1631 if (Subtarget->is64Bit()) {
1632 // Max of 8 and alignment of type.
1633 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1640 if (Subtarget->hasSSE1())
1641 getMaxByValAlign(Ty, Align);
1645 /// getOptimalMemOpType - Returns the target specific optimal type for load
1646 /// and store operations as a result of memset, memcpy, and memmove
1647 /// lowering. If DstAlign is zero that means it's safe to destination
1648 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1649 /// means there isn't a need to check it against alignment requirement,
1650 /// probably because the source does not need to be loaded. If 'IsMemset' is
1651 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1652 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1653 /// source is constant so it does not need to be loaded.
1654 /// It returns EVT::Other if the type should be determined using generic
1655 /// target-independent logic.
1657 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1658 unsigned DstAlign, unsigned SrcAlign,
1659 bool IsMemset, bool ZeroMemset,
1661 MachineFunction &MF) const {
1662 const Function *F = MF.getFunction();
1663 if ((!IsMemset || ZeroMemset) &&
1664 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1665 Attribute::NoImplicitFloat)) {
1667 (Subtarget->isUnalignedMemAccessFast() ||
1668 ((DstAlign == 0 || DstAlign >= 16) &&
1669 (SrcAlign == 0 || SrcAlign >= 16)))) {
1671 if (Subtarget->hasInt256())
1673 if (Subtarget->hasFp256())
1676 if (Subtarget->hasSSE2())
1678 if (Subtarget->hasSSE1())
1680 } else if (!MemcpyStrSrc && Size >= 8 &&
1681 !Subtarget->is64Bit() &&
1682 Subtarget->hasSSE2()) {
1683 // Do not use f64 to lower memcpy if source is string constant. It's
1684 // better to use i32 to avoid the loads.
1688 if (Subtarget->is64Bit() && Size >= 8)
1693 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1695 return X86ScalarSSEf32;
1696 else if (VT == MVT::f64)
1697 return X86ScalarSSEf64;
1702 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
1706 *Fast = Subtarget->isUnalignedMemAccessFast();
1710 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1711 /// current function. The returned value is a member of the
1712 /// MachineJumpTableInfo::JTEntryKind enum.
1713 unsigned X86TargetLowering::getJumpTableEncoding() const {
1714 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1716 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1717 Subtarget->isPICStyleGOT())
1718 return MachineJumpTableInfo::EK_Custom32;
1720 // Otherwise, use the normal jump table encoding heuristics.
1721 return TargetLowering::getJumpTableEncoding();
1725 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1726 const MachineBasicBlock *MBB,
1727 unsigned uid,MCContext &Ctx) const{
1728 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1729 Subtarget->isPICStyleGOT());
1730 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1732 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1733 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1736 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1738 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1739 SelectionDAG &DAG) const {
1740 if (!Subtarget->is64Bit())
1741 // This doesn't have SDLoc associated with it, but is not really the
1742 // same as a Register.
1743 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1747 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1748 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1750 const MCExpr *X86TargetLowering::
1751 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1752 MCContext &Ctx) const {
1753 // X86-64 uses RIP relative addressing based on the jump table label.
1754 if (Subtarget->isPICStyleRIPRel())
1755 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1757 // Otherwise, the reference is relative to the PIC base.
1758 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1761 // FIXME: Why this routine is here? Move to RegInfo!
1762 std::pair<const TargetRegisterClass*, uint8_t>
1763 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1764 const TargetRegisterClass *RRC = nullptr;
1766 switch (VT.SimpleTy) {
1768 return TargetLowering::findRepresentativeClass(VT);
1769 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1770 RRC = Subtarget->is64Bit() ?
1771 (const TargetRegisterClass*)&X86::GR64RegClass :
1772 (const TargetRegisterClass*)&X86::GR32RegClass;
1775 RRC = &X86::VR64RegClass;
1777 case MVT::f32: case MVT::f64:
1778 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1779 case MVT::v4f32: case MVT::v2f64:
1780 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1782 RRC = &X86::VR128RegClass;
1785 return std::make_pair(RRC, Cost);
1788 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1789 unsigned &Offset) const {
1790 if (!Subtarget->isTargetLinux())
1793 if (Subtarget->is64Bit()) {
1794 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1796 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1808 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1809 unsigned DestAS) const {
1810 assert(SrcAS != DestAS && "Expected different address spaces!");
1812 return SrcAS < 256 && DestAS < 256;
1815 //===----------------------------------------------------------------------===//
1816 // Return Value Calling Convention Implementation
1817 //===----------------------------------------------------------------------===//
1819 #include "X86GenCallingConv.inc"
1822 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1823 MachineFunction &MF, bool isVarArg,
1824 const SmallVectorImpl<ISD::OutputArg> &Outs,
1825 LLVMContext &Context) const {
1826 SmallVector<CCValAssign, 16> RVLocs;
1827 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1829 return CCInfo.CheckReturn(Outs, RetCC_X86);
1832 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1833 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1838 X86TargetLowering::LowerReturn(SDValue Chain,
1839 CallingConv::ID CallConv, bool isVarArg,
1840 const SmallVectorImpl<ISD::OutputArg> &Outs,
1841 const SmallVectorImpl<SDValue> &OutVals,
1842 SDLoc dl, SelectionDAG &DAG) const {
1843 MachineFunction &MF = DAG.getMachineFunction();
1844 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1846 SmallVector<CCValAssign, 16> RVLocs;
1847 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1848 RVLocs, *DAG.getContext());
1849 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1852 SmallVector<SDValue, 6> RetOps;
1853 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1854 // Operand #1 = Bytes To Pop
1855 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1858 // Copy the result values into the output registers.
1859 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1860 CCValAssign &VA = RVLocs[i];
1861 assert(VA.isRegLoc() && "Can only return in registers!");
1862 SDValue ValToCopy = OutVals[i];
1863 EVT ValVT = ValToCopy.getValueType();
1865 // Promote values to the appropriate types
1866 if (VA.getLocInfo() == CCValAssign::SExt)
1867 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1868 else if (VA.getLocInfo() == CCValAssign::ZExt)
1869 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1870 else if (VA.getLocInfo() == CCValAssign::AExt)
1871 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1872 else if (VA.getLocInfo() == CCValAssign::BCvt)
1873 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1875 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1876 "Unexpected FP-extend for return value.");
1878 // If this is x86-64, and we disabled SSE, we can't return FP values,
1879 // or SSE or MMX vectors.
1880 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1881 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1882 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1883 report_fatal_error("SSE register return with SSE disabled");
1885 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1886 // llvm-gcc has never done it right and no one has noticed, so this
1887 // should be OK for now.
1888 if (ValVT == MVT::f64 &&
1889 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1890 report_fatal_error("SSE2 register return with SSE2 disabled");
1892 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1893 // the RET instruction and handled by the FP Stackifier.
1894 if (VA.getLocReg() == X86::ST0 ||
1895 VA.getLocReg() == X86::ST1) {
1896 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1897 // change the value to the FP stack register class.
1898 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1899 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1900 RetOps.push_back(ValToCopy);
1901 // Don't emit a copytoreg.
1905 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1906 // which is returned in RAX / RDX.
1907 if (Subtarget->is64Bit()) {
1908 if (ValVT == MVT::x86mmx) {
1909 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1910 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1911 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1913 // If we don't have SSE2 available, convert to v4f32 so the generated
1914 // register is legal.
1915 if (!Subtarget->hasSSE2())
1916 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1921 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1922 Flag = Chain.getValue(1);
1923 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1926 // The x86-64 ABIs require that for returning structs by value we copy
1927 // the sret argument into %rax/%eax (depending on ABI) for the return.
1928 // Win32 requires us to put the sret argument to %eax as well.
1929 // We saved the argument into a virtual register in the entry block,
1930 // so now we copy the value out and into %rax/%eax.
1931 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1932 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
1933 MachineFunction &MF = DAG.getMachineFunction();
1934 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1935 unsigned Reg = FuncInfo->getSRetReturnReg();
1937 "SRetReturnReg should have been set in LowerFormalArguments().");
1938 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1941 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1942 X86::RAX : X86::EAX;
1943 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1944 Flag = Chain.getValue(1);
1946 // RAX/EAX now acts like a return value.
1947 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1950 RetOps[0] = Chain; // Update chain.
1952 // Add the flag if we have it.
1954 RetOps.push_back(Flag);
1956 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
1959 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1960 if (N->getNumValues() != 1)
1962 if (!N->hasNUsesOfValue(1, 0))
1965 SDValue TCChain = Chain;
1966 SDNode *Copy = *N->use_begin();
1967 if (Copy->getOpcode() == ISD::CopyToReg) {
1968 // If the copy has a glue operand, we conservatively assume it isn't safe to
1969 // perform a tail call.
1970 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1972 TCChain = Copy->getOperand(0);
1973 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1976 bool HasRet = false;
1977 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1979 if (UI->getOpcode() != X86ISD::RET_FLAG)
1992 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1993 ISD::NodeType ExtendKind) const {
1995 // TODO: Is this also valid on 32-bit?
1996 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1997 ReturnMVT = MVT::i8;
1999 ReturnMVT = MVT::i32;
2001 MVT MinVT = getRegisterType(ReturnMVT);
2002 return VT.bitsLT(MinVT) ? MinVT : VT;
2005 /// LowerCallResult - Lower the result values of a call into the
2006 /// appropriate copies out of appropriate physical registers.
2009 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2010 CallingConv::ID CallConv, bool isVarArg,
2011 const SmallVectorImpl<ISD::InputArg> &Ins,
2012 SDLoc dl, SelectionDAG &DAG,
2013 SmallVectorImpl<SDValue> &InVals) const {
2015 // Assign locations to each value returned by this call.
2016 SmallVector<CCValAssign, 16> RVLocs;
2017 bool Is64Bit = Subtarget->is64Bit();
2018 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2019 getTargetMachine(), RVLocs, *DAG.getContext());
2020 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2022 // Copy all of the result registers out of their specified physreg.
2023 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2024 CCValAssign &VA = RVLocs[i];
2025 EVT CopyVT = VA.getValVT();
2027 // If this is x86-64, and we disabled SSE, we can't return FP values
2028 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2029 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2030 report_fatal_error("SSE register return with SSE disabled");
2035 // If this is a call to a function that returns an fp value on the floating
2036 // point stack, we must guarantee the value is popped from the stack, so
2037 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2038 // if the return value is not used. We use the FpPOP_RETVAL instruction
2040 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2041 // If we prefer to use the value in xmm registers, copy it out as f80 and
2042 // use a truncate to move it from fp stack reg to xmm reg.
2043 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2044 SDValue Ops[] = { Chain, InFlag };
2045 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2046 MVT::Other, MVT::Glue, Ops), 1);
2047 Val = Chain.getValue(0);
2049 // Round the f80 to the right size, which also moves it to the appropriate
2051 if (CopyVT != VA.getValVT())
2052 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2053 // This truncation won't change the value.
2054 DAG.getIntPtrConstant(1));
2056 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2057 CopyVT, InFlag).getValue(1);
2058 Val = Chain.getValue(0);
2060 InFlag = Chain.getValue(2);
2061 InVals.push_back(Val);
2067 //===----------------------------------------------------------------------===//
2068 // C & StdCall & Fast Calling Convention implementation
2069 //===----------------------------------------------------------------------===//
2070 // StdCall calling convention seems to be standard for many Windows' API
2071 // routines and around. It differs from C calling convention just a little:
2072 // callee should clean up the stack, not caller. Symbols should be also
2073 // decorated in some fancy way :) It doesn't support any vector arguments.
2074 // For info on fast calling convention see Fast Calling Convention (tail call)
2075 // implementation LowerX86_32FastCCCallTo.
2077 /// CallIsStructReturn - Determines whether a call uses struct return
2079 enum StructReturnType {
2084 static StructReturnType
2085 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2087 return NotStructReturn;
2089 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2090 if (!Flags.isSRet())
2091 return NotStructReturn;
2092 if (Flags.isInReg())
2093 return RegStructReturn;
2094 return StackStructReturn;
2097 /// ArgsAreStructReturn - Determines whether a function uses struct
2098 /// return semantics.
2099 static StructReturnType
2100 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2102 return NotStructReturn;
2104 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2105 if (!Flags.isSRet())
2106 return NotStructReturn;
2107 if (Flags.isInReg())
2108 return RegStructReturn;
2109 return StackStructReturn;
2112 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2113 /// by "Src" to address "Dst" with size and alignment information specified by
2114 /// the specific parameter attribute. The copy will be passed as a byval
2115 /// function parameter.
2117 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2118 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2120 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2122 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2123 /*isVolatile*/false, /*AlwaysInline=*/true,
2124 MachinePointerInfo(), MachinePointerInfo());
2127 /// IsTailCallConvention - Return true if the calling convention is one that
2128 /// supports tail call optimization.
2129 static bool IsTailCallConvention(CallingConv::ID CC) {
2130 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2131 CC == CallingConv::HiPE);
2134 /// \brief Return true if the calling convention is a C calling convention.
2135 static bool IsCCallConvention(CallingConv::ID CC) {
2136 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2137 CC == CallingConv::X86_64_SysV);
2140 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2141 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2145 CallingConv::ID CalleeCC = CS.getCallingConv();
2146 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2152 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2153 /// a tailcall target by changing its ABI.
2154 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2155 bool GuaranteedTailCallOpt) {
2156 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2160 X86TargetLowering::LowerMemArgument(SDValue Chain,
2161 CallingConv::ID CallConv,
2162 const SmallVectorImpl<ISD::InputArg> &Ins,
2163 SDLoc dl, SelectionDAG &DAG,
2164 const CCValAssign &VA,
2165 MachineFrameInfo *MFI,
2167 // Create the nodes corresponding to a load from this parameter slot.
2168 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2169 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2170 getTargetMachine().Options.GuaranteedTailCallOpt);
2171 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2174 // If value is passed by pointer we have address passed instead of the value
2176 if (VA.getLocInfo() == CCValAssign::Indirect)
2177 ValVT = VA.getLocVT();
2179 ValVT = VA.getValVT();
2181 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2182 // changed with more analysis.
2183 // In case of tail call optimization mark all arguments mutable. Since they
2184 // could be overwritten by lowering of arguments in case of a tail call.
2185 if (Flags.isByVal()) {
2186 unsigned Bytes = Flags.getByValSize();
2187 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2188 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2189 return DAG.getFrameIndex(FI, getPointerTy());
2191 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2192 VA.getLocMemOffset(), isImmutable);
2193 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2194 return DAG.getLoad(ValVT, dl, Chain, FIN,
2195 MachinePointerInfo::getFixedStack(FI),
2196 false, false, false, 0);
2201 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2202 CallingConv::ID CallConv,
2204 const SmallVectorImpl<ISD::InputArg> &Ins,
2207 SmallVectorImpl<SDValue> &InVals)
2209 MachineFunction &MF = DAG.getMachineFunction();
2210 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2212 const Function* Fn = MF.getFunction();
2213 if (Fn->hasExternalLinkage() &&
2214 Subtarget->isTargetCygMing() &&
2215 Fn->getName() == "main")
2216 FuncInfo->setForceFramePointer(true);
2218 MachineFrameInfo *MFI = MF.getFrameInfo();
2219 bool Is64Bit = Subtarget->is64Bit();
2220 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2222 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2223 "Var args not supported with calling convention fastcc, ghc or hipe");
2225 // Assign locations to all of the incoming arguments.
2226 SmallVector<CCValAssign, 16> ArgLocs;
2227 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2228 ArgLocs, *DAG.getContext());
2230 // Allocate shadow area for Win64
2232 CCInfo.AllocateStack(32, 8);
2234 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2236 unsigned LastVal = ~0U;
2238 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2239 CCValAssign &VA = ArgLocs[i];
2240 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2242 assert(VA.getValNo() != LastVal &&
2243 "Don't support value assigned to multiple locs yet");
2245 LastVal = VA.getValNo();
2247 if (VA.isRegLoc()) {
2248 EVT RegVT = VA.getLocVT();
2249 const TargetRegisterClass *RC;
2250 if (RegVT == MVT::i32)
2251 RC = &X86::GR32RegClass;
2252 else if (Is64Bit && RegVT == MVT::i64)
2253 RC = &X86::GR64RegClass;
2254 else if (RegVT == MVT::f32)
2255 RC = &X86::FR32RegClass;
2256 else if (RegVT == MVT::f64)
2257 RC = &X86::FR64RegClass;
2258 else if (RegVT.is512BitVector())
2259 RC = &X86::VR512RegClass;
2260 else if (RegVT.is256BitVector())
2261 RC = &X86::VR256RegClass;
2262 else if (RegVT.is128BitVector())
2263 RC = &X86::VR128RegClass;
2264 else if (RegVT == MVT::x86mmx)
2265 RC = &X86::VR64RegClass;
2266 else if (RegVT == MVT::i1)
2267 RC = &X86::VK1RegClass;
2268 else if (RegVT == MVT::v8i1)
2269 RC = &X86::VK8RegClass;
2270 else if (RegVT == MVT::v16i1)
2271 RC = &X86::VK16RegClass;
2273 llvm_unreachable("Unknown argument type!");
2275 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2276 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2278 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2279 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2281 if (VA.getLocInfo() == CCValAssign::SExt)
2282 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2283 DAG.getValueType(VA.getValVT()));
2284 else if (VA.getLocInfo() == CCValAssign::ZExt)
2285 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2286 DAG.getValueType(VA.getValVT()));
2287 else if (VA.getLocInfo() == CCValAssign::BCvt)
2288 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2290 if (VA.isExtInLoc()) {
2291 // Handle MMX values passed in XMM regs.
2292 if (RegVT.isVector())
2293 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2295 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2298 assert(VA.isMemLoc());
2299 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2302 // If value is passed via pointer - do a load.
2303 if (VA.getLocInfo() == CCValAssign::Indirect)
2304 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2305 MachinePointerInfo(), false, false, false, 0);
2307 InVals.push_back(ArgValue);
2310 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2311 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2312 // The x86-64 ABIs require that for returning structs by value we copy
2313 // the sret argument into %rax/%eax (depending on ABI) for the return.
2314 // Win32 requires us to put the sret argument to %eax as well.
2315 // Save the argument into a virtual register so that we can access it
2316 // from the return points.
2317 if (Ins[i].Flags.isSRet()) {
2318 unsigned Reg = FuncInfo->getSRetReturnReg();
2320 MVT PtrTy = getPointerTy();
2321 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2322 FuncInfo->setSRetReturnReg(Reg);
2324 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2325 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2331 unsigned StackSize = CCInfo.getNextStackOffset();
2332 // Align stack specially for tail calls.
2333 if (FuncIsMadeTailCallSafe(CallConv,
2334 MF.getTarget().Options.GuaranteedTailCallOpt))
2335 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2337 // If the function takes variable number of arguments, make a frame index for
2338 // the start of the first vararg value... for expansion of llvm.va_start.
2340 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2341 CallConv != CallingConv::X86_ThisCall)) {
2342 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2345 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2347 // FIXME: We should really autogenerate these arrays
2348 static const MCPhysReg GPR64ArgRegsWin64[] = {
2349 X86::RCX, X86::RDX, X86::R8, X86::R9
2351 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2352 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2354 static const MCPhysReg XMMArgRegs64Bit[] = {
2355 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2356 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2358 const MCPhysReg *GPR64ArgRegs;
2359 unsigned NumXMMRegs = 0;
2362 // The XMM registers which might contain var arg parameters are shadowed
2363 // in their paired GPR. So we only need to save the GPR to their home
2365 TotalNumIntRegs = 4;
2366 GPR64ArgRegs = GPR64ArgRegsWin64;
2368 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2369 GPR64ArgRegs = GPR64ArgRegs64Bit;
2371 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2374 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2377 bool NoImplicitFloatOps = Fn->getAttributes().
2378 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2379 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2380 "SSE register cannot be used when SSE is disabled!");
2381 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2382 NoImplicitFloatOps) &&
2383 "SSE register cannot be used when SSE is disabled!");
2384 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2385 !Subtarget->hasSSE1())
2386 // Kernel mode asks for SSE to be disabled, so don't push them
2388 TotalNumXMMRegs = 0;
2391 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2392 // Get to the caller-allocated home save location. Add 8 to account
2393 // for the return address.
2394 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2395 FuncInfo->setRegSaveFrameIndex(
2396 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2397 // Fixup to set vararg frame on shadow area (4 x i64).
2399 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2401 // For X86-64, if there are vararg parameters that are passed via
2402 // registers, then we must store them to their spots on the stack so
2403 // they may be loaded by deferencing the result of va_next.
2404 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2405 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2406 FuncInfo->setRegSaveFrameIndex(
2407 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2411 // Store the integer parameter registers.
2412 SmallVector<SDValue, 8> MemOps;
2413 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2415 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2416 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2417 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2418 DAG.getIntPtrConstant(Offset));
2419 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2420 &X86::GR64RegClass);
2421 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2423 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2424 MachinePointerInfo::getFixedStack(
2425 FuncInfo->getRegSaveFrameIndex(), Offset),
2427 MemOps.push_back(Store);
2431 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2432 // Now store the XMM (fp + vector) parameter registers.
2433 SmallVector<SDValue, 11> SaveXMMOps;
2434 SaveXMMOps.push_back(Chain);
2436 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2437 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2438 SaveXMMOps.push_back(ALVal);
2440 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2441 FuncInfo->getRegSaveFrameIndex()));
2442 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2443 FuncInfo->getVarArgsFPOffset()));
2445 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2446 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2447 &X86::VR128RegClass);
2448 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2449 SaveXMMOps.push_back(Val);
2451 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2452 MVT::Other, SaveXMMOps));
2455 if (!MemOps.empty())
2456 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2460 // Some CCs need callee pop.
2461 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2462 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2463 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2465 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2466 // If this is an sret function, the return should pop the hidden pointer.
2467 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2468 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2469 argsAreStructReturn(Ins) == StackStructReturn)
2470 FuncInfo->setBytesToPopOnReturn(4);
2474 // RegSaveFrameIndex is X86-64 only.
2475 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2476 if (CallConv == CallingConv::X86_FastCall ||
2477 CallConv == CallingConv::X86_ThisCall)
2478 // fastcc functions can't have varargs.
2479 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2482 FuncInfo->setArgumentStackSize(StackSize);
2488 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2489 SDValue StackPtr, SDValue Arg,
2490 SDLoc dl, SelectionDAG &DAG,
2491 const CCValAssign &VA,
2492 ISD::ArgFlagsTy Flags) const {
2493 unsigned LocMemOffset = VA.getLocMemOffset();
2494 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2495 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2496 if (Flags.isByVal())
2497 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2499 return DAG.getStore(Chain, dl, Arg, PtrOff,
2500 MachinePointerInfo::getStack(LocMemOffset),
2504 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2505 /// optimization is performed and it is required.
2507 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2508 SDValue &OutRetAddr, SDValue Chain,
2509 bool IsTailCall, bool Is64Bit,
2510 int FPDiff, SDLoc dl) const {
2511 // Adjust the Return address stack slot.
2512 EVT VT = getPointerTy();
2513 OutRetAddr = getReturnAddressFrameIndex(DAG);
2515 // Load the "old" Return address.
2516 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2517 false, false, false, 0);
2518 return SDValue(OutRetAddr.getNode(), 1);
2521 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2522 /// optimization is performed and it is required (FPDiff!=0).
2523 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2524 SDValue Chain, SDValue RetAddrFrIdx,
2525 EVT PtrVT, unsigned SlotSize,
2526 int FPDiff, SDLoc dl) {
2527 // Store the return address to the appropriate stack slot.
2528 if (!FPDiff) return Chain;
2529 // Calculate the new stack slot for the return address.
2530 int NewReturnAddrFI =
2531 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2533 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2534 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2535 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2541 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2542 SmallVectorImpl<SDValue> &InVals) const {
2543 SelectionDAG &DAG = CLI.DAG;
2545 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2546 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2547 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2548 SDValue Chain = CLI.Chain;
2549 SDValue Callee = CLI.Callee;
2550 CallingConv::ID CallConv = CLI.CallConv;
2551 bool &isTailCall = CLI.IsTailCall;
2552 bool isVarArg = CLI.IsVarArg;
2554 MachineFunction &MF = DAG.getMachineFunction();
2555 bool Is64Bit = Subtarget->is64Bit();
2556 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2557 StructReturnType SR = callIsStructReturn(Outs);
2558 bool IsSibcall = false;
2560 if (MF.getTarget().Options.DisableTailCalls)
2563 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2565 // Force this to be a tail call. The verifier rules are enough to ensure
2566 // that we can lower this successfully without moving the return address
2569 } else if (isTailCall) {
2570 // Check if it's really possible to do a tail call.
2571 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2572 isVarArg, SR != NotStructReturn,
2573 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2574 Outs, OutVals, Ins, DAG);
2576 // Sibcalls are automatically detected tailcalls which do not require
2578 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2585 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2586 "Var args not supported with calling convention fastcc, ghc or hipe");
2588 // Analyze operands of the call, assigning locations to each operand.
2589 SmallVector<CCValAssign, 16> ArgLocs;
2590 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2591 ArgLocs, *DAG.getContext());
2593 // Allocate shadow area for Win64
2595 CCInfo.AllocateStack(32, 8);
2597 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2599 // Get a count of how many bytes are to be pushed on the stack.
2600 unsigned NumBytes = CCInfo.getNextStackOffset();
2602 // This is a sibcall. The memory operands are available in caller's
2603 // own caller's stack.
2605 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2606 IsTailCallConvention(CallConv))
2607 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2610 if (isTailCall && !IsSibcall && !IsMustTail) {
2611 // Lower arguments at fp - stackoffset + fpdiff.
2612 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2613 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2615 FPDiff = NumBytesCallerPushed - NumBytes;
2617 // Set the delta of movement of the returnaddr stackslot.
2618 // But only set if delta is greater than previous delta.
2619 if (FPDiff < X86Info->getTCReturnAddrDelta())
2620 X86Info->setTCReturnAddrDelta(FPDiff);
2623 unsigned NumBytesToPush = NumBytes;
2624 unsigned NumBytesToPop = NumBytes;
2626 // If we have an inalloca argument, all stack space has already been allocated
2627 // for us and be right at the top of the stack. We don't support multiple
2628 // arguments passed in memory when using inalloca.
2629 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2631 assert(ArgLocs.back().getLocMemOffset() == 0 &&
2632 "an inalloca argument must be the only memory argument");
2636 Chain = DAG.getCALLSEQ_START(
2637 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2639 SDValue RetAddrFrIdx;
2640 // Load return address for tail calls.
2641 if (isTailCall && FPDiff)
2642 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2643 Is64Bit, FPDiff, dl);
2645 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2646 SmallVector<SDValue, 8> MemOpChains;
2649 // Walk the register/memloc assignments, inserting copies/loads. In the case
2650 // of tail call optimization arguments are handle later.
2651 const X86RegisterInfo *RegInfo =
2652 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2653 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2654 // Skip inalloca arguments, they have already been written.
2655 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2656 if (Flags.isInAlloca())
2659 CCValAssign &VA = ArgLocs[i];
2660 EVT RegVT = VA.getLocVT();
2661 SDValue Arg = OutVals[i];
2662 bool isByVal = Flags.isByVal();
2664 // Promote the value if needed.
2665 switch (VA.getLocInfo()) {
2666 default: llvm_unreachable("Unknown loc info!");
2667 case CCValAssign::Full: break;
2668 case CCValAssign::SExt:
2669 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2671 case CCValAssign::ZExt:
2672 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2674 case CCValAssign::AExt:
2675 if (RegVT.is128BitVector()) {
2676 // Special case: passing MMX values in XMM registers.
2677 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2678 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2679 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2681 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2683 case CCValAssign::BCvt:
2684 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2686 case CCValAssign::Indirect: {
2687 // Store the argument.
2688 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2689 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2690 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2691 MachinePointerInfo::getFixedStack(FI),
2698 if (VA.isRegLoc()) {
2699 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2700 if (isVarArg && IsWin64) {
2701 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2702 // shadow reg if callee is a varargs function.
2703 unsigned ShadowReg = 0;
2704 switch (VA.getLocReg()) {
2705 case X86::XMM0: ShadowReg = X86::RCX; break;
2706 case X86::XMM1: ShadowReg = X86::RDX; break;
2707 case X86::XMM2: ShadowReg = X86::R8; break;
2708 case X86::XMM3: ShadowReg = X86::R9; break;
2711 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2713 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2714 assert(VA.isMemLoc());
2715 if (!StackPtr.getNode())
2716 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2718 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2719 dl, DAG, VA, Flags));
2723 if (!MemOpChains.empty())
2724 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2726 if (Subtarget->isPICStyleGOT()) {
2727 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2730 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2731 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2733 // If we are tail calling and generating PIC/GOT style code load the
2734 // address of the callee into ECX. The value in ecx is used as target of
2735 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2736 // for tail calls on PIC/GOT architectures. Normally we would just put the
2737 // address of GOT into ebx and then call target@PLT. But for tail calls
2738 // ebx would be restored (since ebx is callee saved) before jumping to the
2741 // Note: The actual moving to ECX is done further down.
2742 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2743 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2744 !G->getGlobal()->hasProtectedVisibility())
2745 Callee = LowerGlobalAddress(Callee, DAG);
2746 else if (isa<ExternalSymbolSDNode>(Callee))
2747 Callee = LowerExternalSymbol(Callee, DAG);
2751 if (Is64Bit && isVarArg && !IsWin64) {
2752 // From AMD64 ABI document:
2753 // For calls that may call functions that use varargs or stdargs
2754 // (prototype-less calls or calls to functions containing ellipsis (...) in
2755 // the declaration) %al is used as hidden argument to specify the number
2756 // of SSE registers used. The contents of %al do not need to match exactly
2757 // the number of registers, but must be an ubound on the number of SSE
2758 // registers used and is in the range 0 - 8 inclusive.
2760 // Count the number of XMM registers allocated.
2761 static const MCPhysReg XMMArgRegs[] = {
2762 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2763 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2765 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2766 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2767 && "SSE registers cannot be used when SSE is disabled");
2769 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2770 DAG.getConstant(NumXMMRegs, MVT::i8)));
2773 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2774 // don't need this because the eligibility check rejects calls that require
2775 // shuffling arguments passed in memory.
2776 if (!IsSibcall && isTailCall) {
2777 // Force all the incoming stack arguments to be loaded from the stack
2778 // before any new outgoing arguments are stored to the stack, because the
2779 // outgoing stack slots may alias the incoming argument stack slots, and
2780 // the alias isn't otherwise explicit. This is slightly more conservative
2781 // than necessary, because it means that each store effectively depends
2782 // on every argument instead of just those arguments it would clobber.
2783 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2785 SmallVector<SDValue, 8> MemOpChains2;
2788 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2789 CCValAssign &VA = ArgLocs[i];
2792 assert(VA.isMemLoc());
2793 SDValue Arg = OutVals[i];
2794 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2795 // Skip inalloca arguments. They don't require any work.
2796 if (Flags.isInAlloca())
2798 // Create frame index.
2799 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2800 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2801 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2802 FIN = DAG.getFrameIndex(FI, getPointerTy());
2804 if (Flags.isByVal()) {
2805 // Copy relative to framepointer.
2806 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2807 if (!StackPtr.getNode())
2808 StackPtr = DAG.getCopyFromReg(Chain, dl,
2809 RegInfo->getStackRegister(),
2811 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2813 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2817 // Store relative to framepointer.
2818 MemOpChains2.push_back(
2819 DAG.getStore(ArgChain, dl, Arg, FIN,
2820 MachinePointerInfo::getFixedStack(FI),
2825 if (!MemOpChains2.empty())
2826 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2828 // Store the return address to the appropriate stack slot.
2829 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2830 getPointerTy(), RegInfo->getSlotSize(),
2834 // Build a sequence of copy-to-reg nodes chained together with token chain
2835 // and flag operands which copy the outgoing args into registers.
2837 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2838 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2839 RegsToPass[i].second, InFlag);
2840 InFlag = Chain.getValue(1);
2843 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2844 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2845 // In the 64-bit large code model, we have to make all calls
2846 // through a register, since the call instruction's 32-bit
2847 // pc-relative offset may not be large enough to hold the whole
2849 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2850 // If the callee is a GlobalAddress node (quite common, every direct call
2851 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2854 // We should use extra load for direct calls to dllimported functions in
2856 const GlobalValue *GV = G->getGlobal();
2857 if (!GV->hasDLLImportStorageClass()) {
2858 unsigned char OpFlags = 0;
2859 bool ExtraLoad = false;
2860 unsigned WrapperKind = ISD::DELETED_NODE;
2862 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2863 // external symbols most go through the PLT in PIC mode. If the symbol
2864 // has hidden or protected visibility, or if it is static or local, then
2865 // we don't need to use the PLT - we can directly call it.
2866 if (Subtarget->isTargetELF() &&
2867 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2868 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2869 OpFlags = X86II::MO_PLT;
2870 } else if (Subtarget->isPICStyleStubAny() &&
2871 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2872 (!Subtarget->getTargetTriple().isMacOSX() ||
2873 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2874 // PC-relative references to external symbols should go through $stub,
2875 // unless we're building with the leopard linker or later, which
2876 // automatically synthesizes these stubs.
2877 OpFlags = X86II::MO_DARWIN_STUB;
2878 } else if (Subtarget->isPICStyleRIPRel() &&
2879 isa<Function>(GV) &&
2880 cast<Function>(GV)->getAttributes().
2881 hasAttribute(AttributeSet::FunctionIndex,
2882 Attribute::NonLazyBind)) {
2883 // If the function is marked as non-lazy, generate an indirect call
2884 // which loads from the GOT directly. This avoids runtime overhead
2885 // at the cost of eager binding (and one extra byte of encoding).
2886 OpFlags = X86II::MO_GOTPCREL;
2887 WrapperKind = X86ISD::WrapperRIP;
2891 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2892 G->getOffset(), OpFlags);
2894 // Add a wrapper if needed.
2895 if (WrapperKind != ISD::DELETED_NODE)
2896 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2897 // Add extra indirection if needed.
2899 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2900 MachinePointerInfo::getGOT(),
2901 false, false, false, 0);
2903 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2904 unsigned char OpFlags = 0;
2906 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2907 // external symbols should go through the PLT.
2908 if (Subtarget->isTargetELF() &&
2909 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2910 OpFlags = X86II::MO_PLT;
2911 } else if (Subtarget->isPICStyleStubAny() &&
2912 (!Subtarget->getTargetTriple().isMacOSX() ||
2913 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2914 // PC-relative references to external symbols should go through $stub,
2915 // unless we're building with the leopard linker or later, which
2916 // automatically synthesizes these stubs.
2917 OpFlags = X86II::MO_DARWIN_STUB;
2920 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2924 // Returns a chain & a flag for retval copy to use.
2925 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2926 SmallVector<SDValue, 8> Ops;
2928 if (!IsSibcall && isTailCall) {
2929 Chain = DAG.getCALLSEQ_END(Chain,
2930 DAG.getIntPtrConstant(NumBytesToPop, true),
2931 DAG.getIntPtrConstant(0, true), InFlag, dl);
2932 InFlag = Chain.getValue(1);
2935 Ops.push_back(Chain);
2936 Ops.push_back(Callee);
2939 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2941 // Add argument registers to the end of the list so that they are known live
2943 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2944 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2945 RegsToPass[i].second.getValueType()));
2947 // Add a register mask operand representing the call-preserved registers.
2948 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2949 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2950 assert(Mask && "Missing call preserved mask for calling convention");
2951 Ops.push_back(DAG.getRegisterMask(Mask));
2953 if (InFlag.getNode())
2954 Ops.push_back(InFlag);
2958 //// If this is the first return lowered for this function, add the regs
2959 //// to the liveout set for the function.
2960 // This isn't right, although it's probably harmless on x86; liveouts
2961 // should be computed from returns not tail calls. Consider a void
2962 // function making a tail call to a function returning int.
2963 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
2966 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
2967 InFlag = Chain.getValue(1);
2969 // Create the CALLSEQ_END node.
2970 unsigned NumBytesForCalleeToPop;
2971 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2972 getTargetMachine().Options.GuaranteedTailCallOpt))
2973 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
2974 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2975 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2976 SR == StackStructReturn)
2977 // If this is a call to a struct-return function, the callee
2978 // pops the hidden struct pointer, so we have to push it back.
2979 // This is common for Darwin/X86, Linux & Mingw32 targets.
2980 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2981 NumBytesForCalleeToPop = 4;
2983 NumBytesForCalleeToPop = 0; // Callee pops nothing.
2985 // Returns a flag for retval copy to use.
2987 Chain = DAG.getCALLSEQ_END(Chain,
2988 DAG.getIntPtrConstant(NumBytesToPop, true),
2989 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
2992 InFlag = Chain.getValue(1);
2995 // Handle result values, copying them out of physregs into vregs that we
2997 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2998 Ins, dl, DAG, InVals);
3001 //===----------------------------------------------------------------------===//
3002 // Fast Calling Convention (tail call) implementation
3003 //===----------------------------------------------------------------------===//
3005 // Like std call, callee cleans arguments, convention except that ECX is
3006 // reserved for storing the tail called function address. Only 2 registers are
3007 // free for argument passing (inreg). Tail call optimization is performed
3009 // * tailcallopt is enabled
3010 // * caller/callee are fastcc
3011 // On X86_64 architecture with GOT-style position independent code only local
3012 // (within module) calls are supported at the moment.
3013 // To keep the stack aligned according to platform abi the function
3014 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3015 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3016 // If a tail called function callee has more arguments than the caller the
3017 // caller needs to make sure that there is room to move the RETADDR to. This is
3018 // achieved by reserving an area the size of the argument delta right after the
3019 // original REtADDR, but before the saved framepointer or the spilled registers
3020 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3032 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3033 /// for a 16 byte align requirement.
3035 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3036 SelectionDAG& DAG) const {
3037 MachineFunction &MF = DAG.getMachineFunction();
3038 const TargetMachine &TM = MF.getTarget();
3039 const X86RegisterInfo *RegInfo =
3040 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
3041 const TargetFrameLowering &TFI = *TM.getFrameLowering();
3042 unsigned StackAlignment = TFI.getStackAlignment();
3043 uint64_t AlignMask = StackAlignment - 1;
3044 int64_t Offset = StackSize;
3045 unsigned SlotSize = RegInfo->getSlotSize();
3046 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3047 // Number smaller than 12 so just add the difference.
3048 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3050 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3051 Offset = ((~AlignMask) & Offset) + StackAlignment +
3052 (StackAlignment-SlotSize);
3057 /// MatchingStackOffset - Return true if the given stack call argument is
3058 /// already available in the same position (relatively) of the caller's
3059 /// incoming argument stack.
3061 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3062 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3063 const X86InstrInfo *TII) {
3064 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3066 if (Arg.getOpcode() == ISD::CopyFromReg) {
3067 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3068 if (!TargetRegisterInfo::isVirtualRegister(VR))
3070 MachineInstr *Def = MRI->getVRegDef(VR);
3073 if (!Flags.isByVal()) {
3074 if (!TII->isLoadFromStackSlot(Def, FI))
3077 unsigned Opcode = Def->getOpcode();
3078 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3079 Def->getOperand(1).isFI()) {
3080 FI = Def->getOperand(1).getIndex();
3081 Bytes = Flags.getByValSize();
3085 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3086 if (Flags.isByVal())
3087 // ByVal argument is passed in as a pointer but it's now being
3088 // dereferenced. e.g.
3089 // define @foo(%struct.X* %A) {
3090 // tail call @bar(%struct.X* byval %A)
3093 SDValue Ptr = Ld->getBasePtr();
3094 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3097 FI = FINode->getIndex();
3098 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3099 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3100 FI = FINode->getIndex();
3101 Bytes = Flags.getByValSize();
3105 assert(FI != INT_MAX);
3106 if (!MFI->isFixedObjectIndex(FI))
3108 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3111 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3112 /// for tail call optimization. Targets which want to do tail call
3113 /// optimization should implement this function.
3115 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3116 CallingConv::ID CalleeCC,
3118 bool isCalleeStructRet,
3119 bool isCallerStructRet,
3121 const SmallVectorImpl<ISD::OutputArg> &Outs,
3122 const SmallVectorImpl<SDValue> &OutVals,
3123 const SmallVectorImpl<ISD::InputArg> &Ins,
3124 SelectionDAG &DAG) const {
3125 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3128 // If -tailcallopt is specified, make fastcc functions tail-callable.
3129 const MachineFunction &MF = DAG.getMachineFunction();
3130 const Function *CallerF = MF.getFunction();
3132 // If the function return type is x86_fp80 and the callee return type is not,
3133 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3134 // perform a tailcall optimization here.
3135 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3138 CallingConv::ID CallerCC = CallerF->getCallingConv();
3139 bool CCMatch = CallerCC == CalleeCC;
3140 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3141 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3143 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3144 if (IsTailCallConvention(CalleeCC) && CCMatch)
3149 // Look for obvious safe cases to perform tail call optimization that do not
3150 // require ABI changes. This is what gcc calls sibcall.
3152 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3153 // emit a special epilogue.
3154 const X86RegisterInfo *RegInfo =
3155 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3156 if (RegInfo->needsStackRealignment(MF))
3159 // Also avoid sibcall optimization if either caller or callee uses struct
3160 // return semantics.
3161 if (isCalleeStructRet || isCallerStructRet)
3164 // An stdcall/thiscall caller is expected to clean up its arguments; the
3165 // callee isn't going to do that.
3166 // FIXME: this is more restrictive than needed. We could produce a tailcall
3167 // when the stack adjustment matches. For example, with a thiscall that takes
3168 // only one argument.
3169 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3170 CallerCC == CallingConv::X86_ThisCall))
3173 // Do not sibcall optimize vararg calls unless all arguments are passed via
3175 if (isVarArg && !Outs.empty()) {
3177 // Optimizing for varargs on Win64 is unlikely to be safe without
3178 // additional testing.
3179 if (IsCalleeWin64 || IsCallerWin64)
3182 SmallVector<CCValAssign, 16> ArgLocs;
3183 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3184 getTargetMachine(), ArgLocs, *DAG.getContext());
3186 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3187 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3188 if (!ArgLocs[i].isRegLoc())
3192 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3193 // stack. Therefore, if it's not used by the call it is not safe to optimize
3194 // this into a sibcall.
3195 bool Unused = false;
3196 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3203 SmallVector<CCValAssign, 16> RVLocs;
3204 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3205 getTargetMachine(), RVLocs, *DAG.getContext());
3206 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3207 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3208 CCValAssign &VA = RVLocs[i];
3209 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3214 // If the calling conventions do not match, then we'd better make sure the
3215 // results are returned in the same way as what the caller expects.
3217 SmallVector<CCValAssign, 16> RVLocs1;
3218 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3219 getTargetMachine(), RVLocs1, *DAG.getContext());
3220 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3222 SmallVector<CCValAssign, 16> RVLocs2;
3223 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3224 getTargetMachine(), RVLocs2, *DAG.getContext());
3225 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3227 if (RVLocs1.size() != RVLocs2.size())
3229 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3230 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3232 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3234 if (RVLocs1[i].isRegLoc()) {
3235 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3238 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3244 // If the callee takes no arguments then go on to check the results of the
3246 if (!Outs.empty()) {
3247 // Check if stack adjustment is needed. For now, do not do this if any
3248 // argument is passed on the stack.
3249 SmallVector<CCValAssign, 16> ArgLocs;
3250 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3251 getTargetMachine(), ArgLocs, *DAG.getContext());
3253 // Allocate shadow area for Win64
3255 CCInfo.AllocateStack(32, 8);
3257 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3258 if (CCInfo.getNextStackOffset()) {
3259 MachineFunction &MF = DAG.getMachineFunction();
3260 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3263 // Check if the arguments are already laid out in the right way as
3264 // the caller's fixed stack objects.
3265 MachineFrameInfo *MFI = MF.getFrameInfo();
3266 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3267 const X86InstrInfo *TII =
3268 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3269 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3270 CCValAssign &VA = ArgLocs[i];
3271 SDValue Arg = OutVals[i];
3272 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3273 if (VA.getLocInfo() == CCValAssign::Indirect)
3275 if (!VA.isRegLoc()) {
3276 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3283 // If the tailcall address may be in a register, then make sure it's
3284 // possible to register allocate for it. In 32-bit, the call address can
3285 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3286 // callee-saved registers are restored. These happen to be the same
3287 // registers used to pass 'inreg' arguments so watch out for those.
3288 if (!Subtarget->is64Bit() &&
3289 ((!isa<GlobalAddressSDNode>(Callee) &&
3290 !isa<ExternalSymbolSDNode>(Callee)) ||
3291 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3292 unsigned NumInRegs = 0;
3293 // In PIC we need an extra register to formulate the address computation
3295 unsigned MaxInRegs =
3296 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3298 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3299 CCValAssign &VA = ArgLocs[i];
3302 unsigned Reg = VA.getLocReg();
3305 case X86::EAX: case X86::EDX: case X86::ECX:
3306 if (++NumInRegs == MaxInRegs)
3318 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3319 const TargetLibraryInfo *libInfo) const {
3320 return X86::createFastISel(funcInfo, libInfo);
3323 //===----------------------------------------------------------------------===//
3324 // Other Lowering Hooks
3325 //===----------------------------------------------------------------------===//
3327 static bool MayFoldLoad(SDValue Op) {
3328 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3331 static bool MayFoldIntoStore(SDValue Op) {
3332 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3335 static bool isTargetShuffle(unsigned Opcode) {
3337 default: return false;
3338 case X86ISD::PSHUFD:
3339 case X86ISD::PSHUFHW:
3340 case X86ISD::PSHUFLW:
3342 case X86ISD::PALIGNR:
3343 case X86ISD::MOVLHPS:
3344 case X86ISD::MOVLHPD:
3345 case X86ISD::MOVHLPS:
3346 case X86ISD::MOVLPS:
3347 case X86ISD::MOVLPD:
3348 case X86ISD::MOVSHDUP:
3349 case X86ISD::MOVSLDUP:
3350 case X86ISD::MOVDDUP:
3353 case X86ISD::UNPCKL:
3354 case X86ISD::UNPCKH:
3355 case X86ISD::VPERMILP:
3356 case X86ISD::VPERM2X128:
3357 case X86ISD::VPERMI:
3362 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3363 SDValue V1, SelectionDAG &DAG) {
3365 default: llvm_unreachable("Unknown x86 shuffle node");
3366 case X86ISD::MOVSHDUP:
3367 case X86ISD::MOVSLDUP:
3368 case X86ISD::MOVDDUP:
3369 return DAG.getNode(Opc, dl, VT, V1);
3373 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3374 SDValue V1, unsigned TargetMask,
3375 SelectionDAG &DAG) {
3377 default: llvm_unreachable("Unknown x86 shuffle node");
3378 case X86ISD::PSHUFD:
3379 case X86ISD::PSHUFHW:
3380 case X86ISD::PSHUFLW:
3381 case X86ISD::VPERMILP:
3382 case X86ISD::VPERMI:
3383 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3387 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3388 SDValue V1, SDValue V2, unsigned TargetMask,
3389 SelectionDAG &DAG) {
3391 default: llvm_unreachable("Unknown x86 shuffle node");
3392 case X86ISD::PALIGNR:
3394 case X86ISD::VPERM2X128:
3395 return DAG.getNode(Opc, dl, VT, V1, V2,
3396 DAG.getConstant(TargetMask, MVT::i8));
3400 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3401 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3403 default: llvm_unreachable("Unknown x86 shuffle node");
3404 case X86ISD::MOVLHPS:
3405 case X86ISD::MOVLHPD:
3406 case X86ISD::MOVHLPS:
3407 case X86ISD::MOVLPS:
3408 case X86ISD::MOVLPD:
3411 case X86ISD::UNPCKL:
3412 case X86ISD::UNPCKH:
3413 return DAG.getNode(Opc, dl, VT, V1, V2);
3417 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3418 MachineFunction &MF = DAG.getMachineFunction();
3419 const X86RegisterInfo *RegInfo =
3420 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3421 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3422 int ReturnAddrIndex = FuncInfo->getRAIndex();
3424 if (ReturnAddrIndex == 0) {
3425 // Set up a frame object for the return address.
3426 unsigned SlotSize = RegInfo->getSlotSize();
3427 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3430 FuncInfo->setRAIndex(ReturnAddrIndex);
3433 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3436 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3437 bool hasSymbolicDisplacement) {
3438 // Offset should fit into 32 bit immediate field.
3439 if (!isInt<32>(Offset))
3442 // If we don't have a symbolic displacement - we don't have any extra
3444 if (!hasSymbolicDisplacement)
3447 // FIXME: Some tweaks might be needed for medium code model.
3448 if (M != CodeModel::Small && M != CodeModel::Kernel)
3451 // For small code model we assume that latest object is 16MB before end of 31
3452 // bits boundary. We may also accept pretty large negative constants knowing
3453 // that all objects are in the positive half of address space.
3454 if (M == CodeModel::Small && Offset < 16*1024*1024)
3457 // For kernel code model we know that all object resist in the negative half
3458 // of 32bits address space. We may not accept negative offsets, since they may
3459 // be just off and we may accept pretty large positive ones.
3460 if (M == CodeModel::Kernel && Offset > 0)
3466 /// isCalleePop - Determines whether the callee is required to pop its
3467 /// own arguments. Callee pop is necessary to support tail calls.
3468 bool X86::isCalleePop(CallingConv::ID CallingConv,
3469 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3473 switch (CallingConv) {
3476 case CallingConv::X86_StdCall:
3478 case CallingConv::X86_FastCall:
3480 case CallingConv::X86_ThisCall:
3482 case CallingConv::Fast:
3484 case CallingConv::GHC:
3486 case CallingConv::HiPE:
3491 /// \brief Return true if the condition is an unsigned comparison operation.
3492 static bool isX86CCUnsigned(unsigned X86CC) {
3494 default: llvm_unreachable("Invalid integer condition!");
3495 case X86::COND_E: return true;
3496 case X86::COND_G: return false;
3497 case X86::COND_GE: return false;
3498 case X86::COND_L: return false;
3499 case X86::COND_LE: return false;
3500 case X86::COND_NE: return true;
3501 case X86::COND_B: return true;
3502 case X86::COND_A: return true;
3503 case X86::COND_BE: return true;
3504 case X86::COND_AE: return true;
3506 llvm_unreachable("covered switch fell through?!");
3509 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3510 /// specific condition code, returning the condition code and the LHS/RHS of the
3511 /// comparison to make.
3512 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3513 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3515 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3516 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3517 // X > -1 -> X == 0, jump !sign.
3518 RHS = DAG.getConstant(0, RHS.getValueType());
3519 return X86::COND_NS;
3521 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3522 // X < 0 -> X == 0, jump on sign.
3525 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3527 RHS = DAG.getConstant(0, RHS.getValueType());
3528 return X86::COND_LE;
3532 switch (SetCCOpcode) {
3533 default: llvm_unreachable("Invalid integer condition!");
3534 case ISD::SETEQ: return X86::COND_E;
3535 case ISD::SETGT: return X86::COND_G;
3536 case ISD::SETGE: return X86::COND_GE;
3537 case ISD::SETLT: return X86::COND_L;
3538 case ISD::SETLE: return X86::COND_LE;
3539 case ISD::SETNE: return X86::COND_NE;
3540 case ISD::SETULT: return X86::COND_B;
3541 case ISD::SETUGT: return X86::COND_A;
3542 case ISD::SETULE: return X86::COND_BE;
3543 case ISD::SETUGE: return X86::COND_AE;
3547 // First determine if it is required or is profitable to flip the operands.
3549 // If LHS is a foldable load, but RHS is not, flip the condition.
3550 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3551 !ISD::isNON_EXTLoad(RHS.getNode())) {
3552 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3553 std::swap(LHS, RHS);
3556 switch (SetCCOpcode) {
3562 std::swap(LHS, RHS);
3566 // On a floating point condition, the flags are set as follows:
3568 // 0 | 0 | 0 | X > Y
3569 // 0 | 0 | 1 | X < Y
3570 // 1 | 0 | 0 | X == Y
3571 // 1 | 1 | 1 | unordered
3572 switch (SetCCOpcode) {
3573 default: llvm_unreachable("Condcode should be pre-legalized away");
3575 case ISD::SETEQ: return X86::COND_E;
3576 case ISD::SETOLT: // flipped
3578 case ISD::SETGT: return X86::COND_A;
3579 case ISD::SETOLE: // flipped
3581 case ISD::SETGE: return X86::COND_AE;
3582 case ISD::SETUGT: // flipped
3584 case ISD::SETLT: return X86::COND_B;
3585 case ISD::SETUGE: // flipped
3587 case ISD::SETLE: return X86::COND_BE;
3589 case ISD::SETNE: return X86::COND_NE;
3590 case ISD::SETUO: return X86::COND_P;
3591 case ISD::SETO: return X86::COND_NP;
3593 case ISD::SETUNE: return X86::COND_INVALID;
3597 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3598 /// code. Current x86 isa includes the following FP cmov instructions:
3599 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3600 static bool hasFPCMov(unsigned X86CC) {
3616 /// isFPImmLegal - Returns true if the target can instruction select the
3617 /// specified FP immediate natively. If false, the legalizer will
3618 /// materialize the FP immediate as a load from a constant pool.
3619 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3620 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3621 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3627 /// \brief Returns true if it is beneficial to convert a load of a constant
3628 /// to just the constant itself.
3629 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3631 assert(Ty->isIntegerTy());
3633 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3634 if (BitSize == 0 || BitSize > 64)
3639 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3640 /// the specified range (L, H].
3641 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3642 return (Val < 0) || (Val >= Low && Val < Hi);
3645 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3646 /// specified value.
3647 static bool isUndefOrEqual(int Val, int CmpVal) {
3648 return (Val < 0 || Val == CmpVal);
3651 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3652 /// from position Pos and ending in Pos+Size, falls within the specified
3653 /// sequential range (L, L+Pos]. or is undef.
3654 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3655 unsigned Pos, unsigned Size, int Low) {
3656 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3657 if (!isUndefOrEqual(Mask[i], Low))
3662 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3663 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3664 /// the second operand.
3665 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3666 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3667 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3668 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3669 return (Mask[0] < 2 && Mask[1] < 2);
3673 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3674 /// is suitable for input to PSHUFHW.
3675 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3676 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3679 // Lower quadword copied in order or undef.
3680 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3683 // Upper quadword shuffled.
3684 for (unsigned i = 4; i != 8; ++i)
3685 if (!isUndefOrInRange(Mask[i], 4, 8))
3688 if (VT == MVT::v16i16) {
3689 // Lower quadword copied in order or undef.
3690 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3693 // Upper quadword shuffled.
3694 for (unsigned i = 12; i != 16; ++i)
3695 if (!isUndefOrInRange(Mask[i], 12, 16))
3702 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3703 /// is suitable for input to PSHUFLW.
3704 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3705 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3708 // Upper quadword copied in order.
3709 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3712 // Lower quadword shuffled.
3713 for (unsigned i = 0; i != 4; ++i)
3714 if (!isUndefOrInRange(Mask[i], 0, 4))
3717 if (VT == MVT::v16i16) {
3718 // Upper quadword copied in order.
3719 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3722 // Lower quadword shuffled.
3723 for (unsigned i = 8; i != 12; ++i)
3724 if (!isUndefOrInRange(Mask[i], 8, 12))
3731 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3732 /// is suitable for input to PALIGNR.
3733 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3734 const X86Subtarget *Subtarget) {
3735 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3736 (VT.is256BitVector() && !Subtarget->hasInt256()))
3739 unsigned NumElts = VT.getVectorNumElements();
3740 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3741 unsigned NumLaneElts = NumElts/NumLanes;
3743 // Do not handle 64-bit element shuffles with palignr.
3744 if (NumLaneElts == 2)
3747 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3749 for (i = 0; i != NumLaneElts; ++i) {
3754 // Lane is all undef, go to next lane
3755 if (i == NumLaneElts)
3758 int Start = Mask[i+l];
3760 // Make sure its in this lane in one of the sources
3761 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3762 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3765 // If not lane 0, then we must match lane 0
3766 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3769 // Correct second source to be contiguous with first source
3770 if (Start >= (int)NumElts)
3771 Start -= NumElts - NumLaneElts;
3773 // Make sure we're shifting in the right direction.
3774 if (Start <= (int)(i+l))
3779 // Check the rest of the elements to see if they are consecutive.
3780 for (++i; i != NumLaneElts; ++i) {
3781 int Idx = Mask[i+l];
3783 // Make sure its in this lane
3784 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3785 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3788 // If not lane 0, then we must match lane 0
3789 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3792 if (Idx >= (int)NumElts)
3793 Idx -= NumElts - NumLaneElts;
3795 if (!isUndefOrEqual(Idx, Start+i))
3804 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3805 /// the two vector operands have swapped position.
3806 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3807 unsigned NumElems) {
3808 for (unsigned i = 0; i != NumElems; ++i) {
3812 else if (idx < (int)NumElems)
3813 Mask[i] = idx + NumElems;
3815 Mask[i] = idx - NumElems;
3819 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3820 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3821 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3822 /// reverse of what x86 shuffles want.
3823 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3825 unsigned NumElems = VT.getVectorNumElements();
3826 unsigned NumLanes = VT.getSizeInBits()/128;
3827 unsigned NumLaneElems = NumElems/NumLanes;
3829 if (NumLaneElems != 2 && NumLaneElems != 4)
3832 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3833 bool symetricMaskRequired =
3834 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3836 // VSHUFPSY divides the resulting vector into 4 chunks.
3837 // The sources are also splitted into 4 chunks, and each destination
3838 // chunk must come from a different source chunk.
3840 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3841 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3843 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3844 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3846 // VSHUFPDY divides the resulting vector into 4 chunks.
3847 // The sources are also splitted into 4 chunks, and each destination
3848 // chunk must come from a different source chunk.
3850 // SRC1 => X3 X2 X1 X0
3851 // SRC2 => Y3 Y2 Y1 Y0
3853 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3855 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3856 unsigned HalfLaneElems = NumLaneElems/2;
3857 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3858 for (unsigned i = 0; i != NumLaneElems; ++i) {
3859 int Idx = Mask[i+l];
3860 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3861 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3863 // For VSHUFPSY, the mask of the second half must be the same as the
3864 // first but with the appropriate offsets. This works in the same way as
3865 // VPERMILPS works with masks.
3866 if (!symetricMaskRequired || Idx < 0)
3868 if (MaskVal[i] < 0) {
3869 MaskVal[i] = Idx - l;
3872 if ((signed)(Idx - l) != MaskVal[i])
3880 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3881 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3882 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3883 if (!VT.is128BitVector())
3886 unsigned NumElems = VT.getVectorNumElements();
3891 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3892 return isUndefOrEqual(Mask[0], 6) &&
3893 isUndefOrEqual(Mask[1], 7) &&
3894 isUndefOrEqual(Mask[2], 2) &&
3895 isUndefOrEqual(Mask[3], 3);
3898 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3899 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3901 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3902 if (!VT.is128BitVector())
3905 unsigned NumElems = VT.getVectorNumElements();
3910 return isUndefOrEqual(Mask[0], 2) &&
3911 isUndefOrEqual(Mask[1], 3) &&
3912 isUndefOrEqual(Mask[2], 2) &&
3913 isUndefOrEqual(Mask[3], 3);
3916 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3917 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3918 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3919 if (!VT.is128BitVector())
3922 unsigned NumElems = VT.getVectorNumElements();
3924 if (NumElems != 2 && NumElems != 4)
3927 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3928 if (!isUndefOrEqual(Mask[i], i + NumElems))
3931 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3932 if (!isUndefOrEqual(Mask[i], i))
3938 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3939 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3940 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3941 if (!VT.is128BitVector())
3944 unsigned NumElems = VT.getVectorNumElements();
3946 if (NumElems != 2 && NumElems != 4)
3949 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3950 if (!isUndefOrEqual(Mask[i], i))
3953 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3954 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3960 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
3961 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
3962 /// i. e: If all but one element come from the same vector.
3963 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
3964 // TODO: Deal with AVX's VINSERTPS
3965 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
3968 unsigned CorrectPosV1 = 0;
3969 unsigned CorrectPosV2 = 0;
3970 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i)
3973 else if (Mask[i] == i + 4)
3976 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
3977 // We have 3 elements from one vector, and one from another.
3984 // Some special combinations that can be optimized.
3987 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3988 SelectionDAG &DAG) {
3989 MVT VT = SVOp->getSimpleValueType(0);
3992 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3995 ArrayRef<int> Mask = SVOp->getMask();
3997 // These are the special masks that may be optimized.
3998 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3999 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4000 bool MatchEvenMask = true;
4001 bool MatchOddMask = true;
4002 for (int i=0; i<8; ++i) {
4003 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4004 MatchEvenMask = false;
4005 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4006 MatchOddMask = false;
4009 if (!MatchEvenMask && !MatchOddMask)
4012 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4014 SDValue Op0 = SVOp->getOperand(0);
4015 SDValue Op1 = SVOp->getOperand(1);
4017 if (MatchEvenMask) {
4018 // Shift the second operand right to 32 bits.
4019 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4020 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4022 // Shift the first operand left to 32 bits.
4023 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4024 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4026 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4027 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4030 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4031 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4032 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4033 bool HasInt256, bool V2IsSplat = false) {
4035 assert(VT.getSizeInBits() >= 128 &&
4036 "Unsupported vector type for unpckl");
4038 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4040 unsigned NumOf256BitLanes;
4041 unsigned NumElts = VT.getVectorNumElements();
4042 if (VT.is256BitVector()) {
4043 if (NumElts != 4 && NumElts != 8 &&
4044 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4047 NumOf256BitLanes = 1;
4048 } else if (VT.is512BitVector()) {
4049 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4050 "Unsupported vector type for unpckh");
4052 NumOf256BitLanes = 2;
4055 NumOf256BitLanes = 1;
4058 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4059 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4061 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4062 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4063 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4064 int BitI = Mask[l256*NumEltsInStride+l+i];
4065 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4066 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4068 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4070 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4078 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4079 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4080 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4081 bool HasInt256, bool V2IsSplat = false) {
4082 assert(VT.getSizeInBits() >= 128 &&
4083 "Unsupported vector type for unpckh");
4085 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4087 unsigned NumOf256BitLanes;
4088 unsigned NumElts = VT.getVectorNumElements();
4089 if (VT.is256BitVector()) {
4090 if (NumElts != 4 && NumElts != 8 &&
4091 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4094 NumOf256BitLanes = 1;
4095 } else if (VT.is512BitVector()) {
4096 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4097 "Unsupported vector type for unpckh");
4099 NumOf256BitLanes = 2;
4102 NumOf256BitLanes = 1;
4105 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4106 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4108 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4109 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4110 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4111 int BitI = Mask[l256*NumEltsInStride+l+i];
4112 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4113 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4115 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4117 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4125 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4126 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4128 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4129 unsigned NumElts = VT.getVectorNumElements();
4130 bool Is256BitVec = VT.is256BitVector();
4132 if (VT.is512BitVector())
4134 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4135 "Unsupported vector type for unpckh");
4137 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4138 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4141 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4142 // FIXME: Need a better way to get rid of this, there's no latency difference
4143 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4144 // the former later. We should also remove the "_undef" special mask.
4145 if (NumElts == 4 && Is256BitVec)
4148 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4149 // independently on 128-bit lanes.
4150 unsigned NumLanes = VT.getSizeInBits()/128;
4151 unsigned NumLaneElts = NumElts/NumLanes;
4153 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4154 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4155 int BitI = Mask[l+i];
4156 int BitI1 = Mask[l+i+1];
4158 if (!isUndefOrEqual(BitI, j))
4160 if (!isUndefOrEqual(BitI1, j))
4168 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4169 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4171 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4172 unsigned NumElts = VT.getVectorNumElements();
4174 if (VT.is512BitVector())
4177 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4178 "Unsupported vector type for unpckh");
4180 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4181 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4184 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4185 // independently on 128-bit lanes.
4186 unsigned NumLanes = VT.getSizeInBits()/128;
4187 unsigned NumLaneElts = NumElts/NumLanes;
4189 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4190 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4191 int BitI = Mask[l+i];
4192 int BitI1 = Mask[l+i+1];
4193 if (!isUndefOrEqual(BitI, j))
4195 if (!isUndefOrEqual(BitI1, j))
4202 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4203 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4204 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4205 if (!VT.is512BitVector())
4208 unsigned NumElts = VT.getVectorNumElements();
4209 unsigned HalfSize = NumElts/2;
4210 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4211 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4216 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4217 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4225 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4226 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4227 /// MOVSD, and MOVD, i.e. setting the lowest element.
4228 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4229 if (VT.getVectorElementType().getSizeInBits() < 32)
4231 if (!VT.is128BitVector())
4234 unsigned NumElts = VT.getVectorNumElements();
4236 if (!isUndefOrEqual(Mask[0], NumElts))
4239 for (unsigned i = 1; i != NumElts; ++i)
4240 if (!isUndefOrEqual(Mask[i], i))
4246 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4247 /// as permutations between 128-bit chunks or halves. As an example: this
4249 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4250 /// The first half comes from the second half of V1 and the second half from the
4251 /// the second half of V2.
4252 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4253 if (!HasFp256 || !VT.is256BitVector())
4256 // The shuffle result is divided into half A and half B. In total the two
4257 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4258 // B must come from C, D, E or F.
4259 unsigned HalfSize = VT.getVectorNumElements()/2;
4260 bool MatchA = false, MatchB = false;
4262 // Check if A comes from one of C, D, E, F.
4263 for (unsigned Half = 0; Half != 4; ++Half) {
4264 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4270 // Check if B comes from one of C, D, E, F.
4271 for (unsigned Half = 0; Half != 4; ++Half) {
4272 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4278 return MatchA && MatchB;
4281 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4282 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4283 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4284 MVT VT = SVOp->getSimpleValueType(0);
4286 unsigned HalfSize = VT.getVectorNumElements()/2;
4288 unsigned FstHalf = 0, SndHalf = 0;
4289 for (unsigned i = 0; i < HalfSize; ++i) {
4290 if (SVOp->getMaskElt(i) > 0) {
4291 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4295 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4296 if (SVOp->getMaskElt(i) > 0) {
4297 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4302 return (FstHalf | (SndHalf << 4));
4305 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4306 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4307 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4311 unsigned NumElts = VT.getVectorNumElements();
4313 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4314 for (unsigned i = 0; i != NumElts; ++i) {
4317 Imm8 |= Mask[i] << (i*2);
4322 unsigned LaneSize = 4;
4323 SmallVector<int, 4> MaskVal(LaneSize, -1);
4325 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4326 for (unsigned i = 0; i != LaneSize; ++i) {
4327 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4331 if (MaskVal[i] < 0) {
4332 MaskVal[i] = Mask[i+l] - l;
4333 Imm8 |= MaskVal[i] << (i*2);
4336 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4343 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4344 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4345 /// Note that VPERMIL mask matching is different depending whether theunderlying
4346 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4347 /// to the same elements of the low, but to the higher half of the source.
4348 /// In VPERMILPD the two lanes could be shuffled independently of each other
4349 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4350 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4351 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4352 if (VT.getSizeInBits() < 256 || EltSize < 32)
4354 bool symetricMaskRequired = (EltSize == 32);
4355 unsigned NumElts = VT.getVectorNumElements();
4357 unsigned NumLanes = VT.getSizeInBits()/128;
4358 unsigned LaneSize = NumElts/NumLanes;
4359 // 2 or 4 elements in one lane
4361 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4362 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4363 for (unsigned i = 0; i != LaneSize; ++i) {
4364 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4366 if (symetricMaskRequired) {
4367 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4368 ExpectedMaskVal[i] = Mask[i+l] - l;
4371 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4379 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4380 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4381 /// element of vector 2 and the other elements to come from vector 1 in order.
4382 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4383 bool V2IsSplat = false, bool V2IsUndef = false) {
4384 if (!VT.is128BitVector())
4387 unsigned NumOps = VT.getVectorNumElements();
4388 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4391 if (!isUndefOrEqual(Mask[0], 0))
4394 for (unsigned i = 1; i != NumOps; ++i)
4395 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4396 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4397 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4403 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4404 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4405 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4406 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4407 const X86Subtarget *Subtarget) {
4408 if (!Subtarget->hasSSE3())
4411 unsigned NumElems = VT.getVectorNumElements();
4413 if ((VT.is128BitVector() && NumElems != 4) ||
4414 (VT.is256BitVector() && NumElems != 8) ||
4415 (VT.is512BitVector() && NumElems != 16))
4418 // "i+1" is the value the indexed mask element must have
4419 for (unsigned i = 0; i != NumElems; i += 2)
4420 if (!isUndefOrEqual(Mask[i], i+1) ||
4421 !isUndefOrEqual(Mask[i+1], i+1))
4427 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4428 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4429 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4430 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4431 const X86Subtarget *Subtarget) {
4432 if (!Subtarget->hasSSE3())
4435 unsigned NumElems = VT.getVectorNumElements();
4437 if ((VT.is128BitVector() && NumElems != 4) ||
4438 (VT.is256BitVector() && NumElems != 8) ||
4439 (VT.is512BitVector() && NumElems != 16))
4442 // "i" is the value the indexed mask element must have
4443 for (unsigned i = 0; i != NumElems; i += 2)
4444 if (!isUndefOrEqual(Mask[i], i) ||
4445 !isUndefOrEqual(Mask[i+1], i))
4451 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4452 /// specifies a shuffle of elements that is suitable for input to 256-bit
4453 /// version of MOVDDUP.
4454 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4455 if (!HasFp256 || !VT.is256BitVector())
4458 unsigned NumElts = VT.getVectorNumElements();
4462 for (unsigned i = 0; i != NumElts/2; ++i)
4463 if (!isUndefOrEqual(Mask[i], 0))
4465 for (unsigned i = NumElts/2; i != NumElts; ++i)
4466 if (!isUndefOrEqual(Mask[i], NumElts/2))
4471 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4472 /// specifies a shuffle of elements that is suitable for input to 128-bit
4473 /// version of MOVDDUP.
4474 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4475 if (!VT.is128BitVector())
4478 unsigned e = VT.getVectorNumElements() / 2;
4479 for (unsigned i = 0; i != e; ++i)
4480 if (!isUndefOrEqual(Mask[i], i))
4482 for (unsigned i = 0; i != e; ++i)
4483 if (!isUndefOrEqual(Mask[e+i], i))
4488 /// isVEXTRACTIndex - Return true if the specified
4489 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4490 /// suitable for instruction that extract 128 or 256 bit vectors
4491 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4492 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4493 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4496 // The index should be aligned on a vecWidth-bit boundary.
4498 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4500 MVT VT = N->getSimpleValueType(0);
4501 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4502 bool Result = (Index * ElSize) % vecWidth == 0;
4507 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4508 /// operand specifies a subvector insert that is suitable for input to
4509 /// insertion of 128 or 256-bit subvectors
4510 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4511 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4512 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4514 // The index should be aligned on a vecWidth-bit boundary.
4516 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4518 MVT VT = N->getSimpleValueType(0);
4519 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4520 bool Result = (Index * ElSize) % vecWidth == 0;
4525 bool X86::isVINSERT128Index(SDNode *N) {
4526 return isVINSERTIndex(N, 128);
4529 bool X86::isVINSERT256Index(SDNode *N) {
4530 return isVINSERTIndex(N, 256);
4533 bool X86::isVEXTRACT128Index(SDNode *N) {
4534 return isVEXTRACTIndex(N, 128);
4537 bool X86::isVEXTRACT256Index(SDNode *N) {
4538 return isVEXTRACTIndex(N, 256);
4541 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4542 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4543 /// Handles 128-bit and 256-bit.
4544 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4545 MVT VT = N->getSimpleValueType(0);
4547 assert((VT.getSizeInBits() >= 128) &&
4548 "Unsupported vector type for PSHUF/SHUFP");
4550 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4551 // independently on 128-bit lanes.
4552 unsigned NumElts = VT.getVectorNumElements();
4553 unsigned NumLanes = VT.getSizeInBits()/128;
4554 unsigned NumLaneElts = NumElts/NumLanes;
4556 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4557 "Only supports 2, 4 or 8 elements per lane");
4559 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4561 for (unsigned i = 0; i != NumElts; ++i) {
4562 int Elt = N->getMaskElt(i);
4563 if (Elt < 0) continue;
4564 Elt &= NumLaneElts - 1;
4565 unsigned ShAmt = (i << Shift) % 8;
4566 Mask |= Elt << ShAmt;
4572 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4573 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4574 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4575 MVT VT = N->getSimpleValueType(0);
4577 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4578 "Unsupported vector type for PSHUFHW");
4580 unsigned NumElts = VT.getVectorNumElements();
4583 for (unsigned l = 0; l != NumElts; l += 8) {
4584 // 8 nodes per lane, but we only care about the last 4.
4585 for (unsigned i = 0; i < 4; ++i) {
4586 int Elt = N->getMaskElt(l+i+4);
4587 if (Elt < 0) continue;
4588 Elt &= 0x3; // only 2-bits.
4589 Mask |= Elt << (i * 2);
4596 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4597 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4598 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4599 MVT VT = N->getSimpleValueType(0);
4601 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4602 "Unsupported vector type for PSHUFHW");
4604 unsigned NumElts = VT.getVectorNumElements();
4607 for (unsigned l = 0; l != NumElts; l += 8) {
4608 // 8 nodes per lane, but we only care about the first 4.
4609 for (unsigned i = 0; i < 4; ++i) {
4610 int Elt = N->getMaskElt(l+i);
4611 if (Elt < 0) continue;
4612 Elt &= 0x3; // only 2-bits
4613 Mask |= Elt << (i * 2);
4620 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4621 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4622 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4623 MVT VT = SVOp->getSimpleValueType(0);
4624 unsigned EltSize = VT.is512BitVector() ? 1 :
4625 VT.getVectorElementType().getSizeInBits() >> 3;
4627 unsigned NumElts = VT.getVectorNumElements();
4628 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4629 unsigned NumLaneElts = NumElts/NumLanes;
4633 for (i = 0; i != NumElts; ++i) {
4634 Val = SVOp->getMaskElt(i);
4638 if (Val >= (int)NumElts)
4639 Val -= NumElts - NumLaneElts;
4641 assert(Val - i > 0 && "PALIGNR imm should be positive");
4642 return (Val - i) * EltSize;
4645 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4646 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4647 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4648 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4651 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4653 MVT VecVT = N->getOperand(0).getSimpleValueType();
4654 MVT ElVT = VecVT.getVectorElementType();
4656 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4657 return Index / NumElemsPerChunk;
4660 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4661 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4662 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4663 llvm_unreachable("Illegal insert subvector for VINSERT");
4666 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4668 MVT VecVT = N->getSimpleValueType(0);
4669 MVT ElVT = VecVT.getVectorElementType();
4671 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4672 return Index / NumElemsPerChunk;
4675 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4676 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4677 /// and VINSERTI128 instructions.
4678 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4679 return getExtractVEXTRACTImmediate(N, 128);
4682 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4683 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4684 /// and VINSERTI64x4 instructions.
4685 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4686 return getExtractVEXTRACTImmediate(N, 256);
4689 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4690 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4691 /// and VINSERTI128 instructions.
4692 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4693 return getInsertVINSERTImmediate(N, 128);
4696 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4697 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4698 /// and VINSERTI64x4 instructions.
4699 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4700 return getInsertVINSERTImmediate(N, 256);
4703 /// isZero - Returns true if Elt is a constant integer zero
4704 static bool isZero(SDValue V) {
4705 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4706 return C && C->isNullValue();
4709 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4711 bool X86::isZeroNode(SDValue Elt) {
4714 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4715 return CFP->getValueAPF().isPosZero();
4719 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4720 /// their permute mask.
4721 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4722 SelectionDAG &DAG) {
4723 MVT VT = SVOp->getSimpleValueType(0);
4724 unsigned NumElems = VT.getVectorNumElements();
4725 SmallVector<int, 8> MaskVec;
4727 for (unsigned i = 0; i != NumElems; ++i) {
4728 int Idx = SVOp->getMaskElt(i);
4730 if (Idx < (int)NumElems)
4735 MaskVec.push_back(Idx);
4737 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4738 SVOp->getOperand(0), &MaskVec[0]);
4741 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4742 /// match movhlps. The lower half elements should come from upper half of
4743 /// V1 (and in order), and the upper half elements should come from the upper
4744 /// half of V2 (and in order).
4745 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4746 if (!VT.is128BitVector())
4748 if (VT.getVectorNumElements() != 4)
4750 for (unsigned i = 0, e = 2; i != e; ++i)
4751 if (!isUndefOrEqual(Mask[i], i+2))
4753 for (unsigned i = 2; i != 4; ++i)
4754 if (!isUndefOrEqual(Mask[i], i+4))
4759 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4760 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4762 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4763 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4765 N = N->getOperand(0).getNode();
4766 if (!ISD::isNON_EXTLoad(N))
4769 *LD = cast<LoadSDNode>(N);
4773 // Test whether the given value is a vector value which will be legalized
4775 static bool WillBeConstantPoolLoad(SDNode *N) {
4776 if (N->getOpcode() != ISD::BUILD_VECTOR)
4779 // Check for any non-constant elements.
4780 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4781 switch (N->getOperand(i).getNode()->getOpcode()) {
4783 case ISD::ConstantFP:
4790 // Vectors of all-zeros and all-ones are materialized with special
4791 // instructions rather than being loaded.
4792 return !ISD::isBuildVectorAllZeros(N) &&
4793 !ISD::isBuildVectorAllOnes(N);
4796 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4797 /// match movlp{s|d}. The lower half elements should come from lower half of
4798 /// V1 (and in order), and the upper half elements should come from the upper
4799 /// half of V2 (and in order). And since V1 will become the source of the
4800 /// MOVLP, it must be either a vector load or a scalar load to vector.
4801 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4802 ArrayRef<int> Mask, MVT VT) {
4803 if (!VT.is128BitVector())
4806 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4808 // Is V2 is a vector load, don't do this transformation. We will try to use
4809 // load folding shufps op.
4810 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4813 unsigned NumElems = VT.getVectorNumElements();
4815 if (NumElems != 2 && NumElems != 4)
4817 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4818 if (!isUndefOrEqual(Mask[i], i))
4820 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4821 if (!isUndefOrEqual(Mask[i], i+NumElems))
4826 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4828 static bool isSplatVector(SDNode *N) {
4829 if (N->getOpcode() != ISD::BUILD_VECTOR)
4832 SDValue SplatValue = N->getOperand(0);
4833 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4834 if (N->getOperand(i) != SplatValue)
4839 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4840 /// to an zero vector.
4841 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4842 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4843 SDValue V1 = N->getOperand(0);
4844 SDValue V2 = N->getOperand(1);
4845 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4846 for (unsigned i = 0; i != NumElems; ++i) {
4847 int Idx = N->getMaskElt(i);
4848 if (Idx >= (int)NumElems) {
4849 unsigned Opc = V2.getOpcode();
4850 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4852 if (Opc != ISD::BUILD_VECTOR ||
4853 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4855 } else if (Idx >= 0) {
4856 unsigned Opc = V1.getOpcode();
4857 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4859 if (Opc != ISD::BUILD_VECTOR ||
4860 !X86::isZeroNode(V1.getOperand(Idx)))
4867 /// getZeroVector - Returns a vector of specified type with all zero elements.
4869 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4870 SelectionDAG &DAG, SDLoc dl) {
4871 assert(VT.isVector() && "Expected a vector type");
4873 // Always build SSE zero vectors as <4 x i32> bitcasted
4874 // to their dest type. This ensures they get CSE'd.
4876 if (VT.is128BitVector()) { // SSE
4877 if (Subtarget->hasSSE2()) { // SSE2
4878 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4879 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4881 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4882 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4884 } else if (VT.is256BitVector()) { // AVX
4885 if (Subtarget->hasInt256()) { // AVX2
4886 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4887 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4888 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4890 // 256-bit logic and arithmetic instructions in AVX are all
4891 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4892 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4893 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4894 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4896 } else if (VT.is512BitVector()) { // AVX-512
4897 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4898 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4899 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4900 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4901 } else if (VT.getScalarType() == MVT::i1) {
4902 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4903 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4904 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4905 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4907 llvm_unreachable("Unexpected vector type");
4909 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4912 /// getOnesVector - Returns a vector of specified type with all bits set.
4913 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4914 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4915 /// Then bitcast to their original type, ensuring they get CSE'd.
4916 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4918 assert(VT.isVector() && "Expected a vector type");
4920 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4922 if (VT.is256BitVector()) {
4923 if (HasInt256) { // AVX2
4924 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4925 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4927 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4928 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4930 } else if (VT.is128BitVector()) {
4931 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4933 llvm_unreachable("Unexpected vector type");
4935 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4938 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4939 /// that point to V2 points to its first element.
4940 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4941 for (unsigned i = 0; i != NumElems; ++i) {
4942 if (Mask[i] > (int)NumElems) {
4948 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4949 /// operation of specified width.
4950 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4952 unsigned NumElems = VT.getVectorNumElements();
4953 SmallVector<int, 8> Mask;
4954 Mask.push_back(NumElems);
4955 for (unsigned i = 1; i != NumElems; ++i)
4957 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4960 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4961 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4963 unsigned NumElems = VT.getVectorNumElements();
4964 SmallVector<int, 8> Mask;
4965 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4967 Mask.push_back(i + NumElems);
4969 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4972 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4973 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4975 unsigned NumElems = VT.getVectorNumElements();
4976 SmallVector<int, 8> Mask;
4977 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4978 Mask.push_back(i + Half);
4979 Mask.push_back(i + NumElems + Half);
4981 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4984 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4985 // a generic shuffle instruction because the target has no such instructions.
4986 // Generate shuffles which repeat i16 and i8 several times until they can be
4987 // represented by v4f32 and then be manipulated by target suported shuffles.
4988 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4989 MVT VT = V.getSimpleValueType();
4990 int NumElems = VT.getVectorNumElements();
4993 while (NumElems > 4) {
4994 if (EltNo < NumElems/2) {
4995 V = getUnpackl(DAG, dl, VT, V, V);
4997 V = getUnpackh(DAG, dl, VT, V, V);
4998 EltNo -= NumElems/2;
5005 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5006 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5007 MVT VT = V.getSimpleValueType();
5010 if (VT.is128BitVector()) {
5011 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5012 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5013 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5015 } else if (VT.is256BitVector()) {
5016 // To use VPERMILPS to splat scalars, the second half of indicies must
5017 // refer to the higher part, which is a duplication of the lower one,
5018 // because VPERMILPS can only handle in-lane permutations.
5019 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5020 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5022 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5023 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5026 llvm_unreachable("Vector size not supported");
5028 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5031 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5032 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5033 MVT SrcVT = SV->getSimpleValueType(0);
5034 SDValue V1 = SV->getOperand(0);
5037 int EltNo = SV->getSplatIndex();
5038 int NumElems = SrcVT.getVectorNumElements();
5039 bool Is256BitVec = SrcVT.is256BitVector();
5041 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5042 "Unknown how to promote splat for type");
5044 // Extract the 128-bit part containing the splat element and update
5045 // the splat element index when it refers to the higher register.
5047 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5048 if (EltNo >= NumElems/2)
5049 EltNo -= NumElems/2;
5052 // All i16 and i8 vector types can't be used directly by a generic shuffle
5053 // instruction because the target has no such instruction. Generate shuffles
5054 // which repeat i16 and i8 several times until they fit in i32, and then can
5055 // be manipulated by target suported shuffles.
5056 MVT EltVT = SrcVT.getVectorElementType();
5057 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5058 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5060 // Recreate the 256-bit vector and place the same 128-bit vector
5061 // into the low and high part. This is necessary because we want
5062 // to use VPERM* to shuffle the vectors
5064 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5067 return getLegalSplat(DAG, V1, EltNo);
5070 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5071 /// vector of zero or undef vector. This produces a shuffle where the low
5072 /// element of V2 is swizzled into the zero/undef vector, landing at element
5073 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5074 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5076 const X86Subtarget *Subtarget,
5077 SelectionDAG &DAG) {
5078 MVT VT = V2.getSimpleValueType();
5080 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5081 unsigned NumElems = VT.getVectorNumElements();
5082 SmallVector<int, 16> MaskVec;
5083 for (unsigned i = 0; i != NumElems; ++i)
5084 // If this is the insertion idx, put the low elt of V2 here.
5085 MaskVec.push_back(i == Idx ? NumElems : i);
5086 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5089 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5090 /// target specific opcode. Returns true if the Mask could be calculated.
5091 /// Sets IsUnary to true if only uses one source.
5092 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5093 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5094 unsigned NumElems = VT.getVectorNumElements();
5098 switch(N->getOpcode()) {
5100 ImmN = N->getOperand(N->getNumOperands()-1);
5101 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5103 case X86ISD::UNPCKH:
5104 DecodeUNPCKHMask(VT, Mask);
5106 case X86ISD::UNPCKL:
5107 DecodeUNPCKLMask(VT, Mask);
5109 case X86ISD::MOVHLPS:
5110 DecodeMOVHLPSMask(NumElems, Mask);
5112 case X86ISD::MOVLHPS:
5113 DecodeMOVLHPSMask(NumElems, Mask);
5115 case X86ISD::PALIGNR:
5116 ImmN = N->getOperand(N->getNumOperands()-1);
5117 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5119 case X86ISD::PSHUFD:
5120 case X86ISD::VPERMILP:
5121 ImmN = N->getOperand(N->getNumOperands()-1);
5122 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5125 case X86ISD::PSHUFHW:
5126 ImmN = N->getOperand(N->getNumOperands()-1);
5127 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5130 case X86ISD::PSHUFLW:
5131 ImmN = N->getOperand(N->getNumOperands()-1);
5132 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5135 case X86ISD::VPERMI:
5136 ImmN = N->getOperand(N->getNumOperands()-1);
5137 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5141 case X86ISD::MOVSD: {
5142 // The index 0 always comes from the first element of the second source,
5143 // this is why MOVSS and MOVSD are used in the first place. The other
5144 // elements come from the other positions of the first source vector
5145 Mask.push_back(NumElems);
5146 for (unsigned i = 1; i != NumElems; ++i) {
5151 case X86ISD::VPERM2X128:
5152 ImmN = N->getOperand(N->getNumOperands()-1);
5153 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5154 if (Mask.empty()) return false;
5156 case X86ISD::MOVDDUP:
5157 case X86ISD::MOVLHPD:
5158 case X86ISD::MOVLPD:
5159 case X86ISD::MOVLPS:
5160 case X86ISD::MOVSHDUP:
5161 case X86ISD::MOVSLDUP:
5162 // Not yet implemented
5164 default: llvm_unreachable("unknown target shuffle node");
5170 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5171 /// element of the result of the vector shuffle.
5172 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5175 return SDValue(); // Limit search depth.
5177 SDValue V = SDValue(N, 0);
5178 EVT VT = V.getValueType();
5179 unsigned Opcode = V.getOpcode();
5181 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5182 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5183 int Elt = SV->getMaskElt(Index);
5186 return DAG.getUNDEF(VT.getVectorElementType());
5188 unsigned NumElems = VT.getVectorNumElements();
5189 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5190 : SV->getOperand(1);
5191 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5194 // Recurse into target specific vector shuffles to find scalars.
5195 if (isTargetShuffle(Opcode)) {
5196 MVT ShufVT = V.getSimpleValueType();
5197 unsigned NumElems = ShufVT.getVectorNumElements();
5198 SmallVector<int, 16> ShuffleMask;
5201 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5204 int Elt = ShuffleMask[Index];
5206 return DAG.getUNDEF(ShufVT.getVectorElementType());
5208 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5210 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5214 // Actual nodes that may contain scalar elements
5215 if (Opcode == ISD::BITCAST) {
5216 V = V.getOperand(0);
5217 EVT SrcVT = V.getValueType();
5218 unsigned NumElems = VT.getVectorNumElements();
5220 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5224 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5225 return (Index == 0) ? V.getOperand(0)
5226 : DAG.getUNDEF(VT.getVectorElementType());
5228 if (V.getOpcode() == ISD::BUILD_VECTOR)
5229 return V.getOperand(Index);
5234 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5235 /// shuffle operation which come from a consecutively from a zero. The
5236 /// search can start in two different directions, from left or right.
5237 /// We count undefs as zeros until PreferredNum is reached.
5238 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5239 unsigned NumElems, bool ZerosFromLeft,
5241 unsigned PreferredNum = -1U) {
5242 unsigned NumZeros = 0;
5243 for (unsigned i = 0; i != NumElems; ++i) {
5244 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5245 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5249 if (X86::isZeroNode(Elt))
5251 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5252 NumZeros = std::min(NumZeros + 1, PreferredNum);
5260 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5261 /// correspond consecutively to elements from one of the vector operands,
5262 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5264 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5265 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5266 unsigned NumElems, unsigned &OpNum) {
5267 bool SeenV1 = false;
5268 bool SeenV2 = false;
5270 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5271 int Idx = SVOp->getMaskElt(i);
5272 // Ignore undef indicies
5276 if (Idx < (int)NumElems)
5281 // Only accept consecutive elements from the same vector
5282 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5286 OpNum = SeenV1 ? 0 : 1;
5290 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5291 /// logical left shift of a vector.
5292 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5293 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5295 SVOp->getSimpleValueType(0).getVectorNumElements();
5296 unsigned NumZeros = getNumOfConsecutiveZeros(
5297 SVOp, NumElems, false /* check zeros from right */, DAG,
5298 SVOp->getMaskElt(0));
5304 // Considering the elements in the mask that are not consecutive zeros,
5305 // check if they consecutively come from only one of the source vectors.
5307 // V1 = {X, A, B, C} 0
5309 // vector_shuffle V1, V2 <1, 2, 3, X>
5311 if (!isShuffleMaskConsecutive(SVOp,
5312 0, // Mask Start Index
5313 NumElems-NumZeros, // Mask End Index(exclusive)
5314 NumZeros, // Where to start looking in the src vector
5315 NumElems, // Number of elements in vector
5316 OpSrc)) // Which source operand ?
5321 ShVal = SVOp->getOperand(OpSrc);
5325 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5326 /// logical left shift of a vector.
5327 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5328 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5330 SVOp->getSimpleValueType(0).getVectorNumElements();
5331 unsigned NumZeros = getNumOfConsecutiveZeros(
5332 SVOp, NumElems, true /* check zeros from left */, DAG,
5333 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5339 // Considering the elements in the mask that are not consecutive zeros,
5340 // check if they consecutively come from only one of the source vectors.
5342 // 0 { A, B, X, X } = V2
5344 // vector_shuffle V1, V2 <X, X, 4, 5>
5346 if (!isShuffleMaskConsecutive(SVOp,
5347 NumZeros, // Mask Start Index
5348 NumElems, // Mask End Index(exclusive)
5349 0, // Where to start looking in the src vector
5350 NumElems, // Number of elements in vector
5351 OpSrc)) // Which source operand ?
5356 ShVal = SVOp->getOperand(OpSrc);
5360 /// isVectorShift - Returns true if the shuffle can be implemented as a
5361 /// logical left or right shift of a vector.
5362 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5363 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5364 // Although the logic below support any bitwidth size, there are no
5365 // shift instructions which handle more than 128-bit vectors.
5366 if (!SVOp->getSimpleValueType(0).is128BitVector())
5369 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5370 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5376 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5378 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5379 unsigned NumNonZero, unsigned NumZero,
5381 const X86Subtarget* Subtarget,
5382 const TargetLowering &TLI) {
5389 for (unsigned i = 0; i < 16; ++i) {
5390 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5391 if (ThisIsNonZero && First) {
5393 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5395 V = DAG.getUNDEF(MVT::v8i16);
5400 SDValue ThisElt, LastElt;
5401 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5402 if (LastIsNonZero) {
5403 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5404 MVT::i16, Op.getOperand(i-1));
5406 if (ThisIsNonZero) {
5407 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5408 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5409 ThisElt, DAG.getConstant(8, MVT::i8));
5411 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5415 if (ThisElt.getNode())
5416 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5417 DAG.getIntPtrConstant(i/2));
5421 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5424 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5426 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5427 unsigned NumNonZero, unsigned NumZero,
5429 const X86Subtarget* Subtarget,
5430 const TargetLowering &TLI) {
5437 for (unsigned i = 0; i < 8; ++i) {
5438 bool isNonZero = (NonZeros & (1 << i)) != 0;
5442 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5444 V = DAG.getUNDEF(MVT::v8i16);
5447 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5448 MVT::v8i16, V, Op.getOperand(i),
5449 DAG.getIntPtrConstant(i));
5456 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5457 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5458 unsigned NonZeros, unsigned NumNonZero,
5459 unsigned NumZero, SelectionDAG &DAG,
5460 const X86Subtarget *Subtarget,
5461 const TargetLowering &TLI) {
5462 // We know there's at least one non-zero element
5463 unsigned FirstNonZeroIdx = 0;
5464 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5465 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5466 X86::isZeroNode(FirstNonZero)) {
5468 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5471 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5472 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5475 SDValue V = FirstNonZero.getOperand(0);
5476 MVT VVT = V.getSimpleValueType();
5477 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5480 unsigned FirstNonZeroDst =
5481 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5482 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5483 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5484 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5486 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5487 SDValue Elem = Op.getOperand(Idx);
5488 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5491 // TODO: What else can be here? Deal with it.
5492 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5495 // TODO: Some optimizations are still possible here
5496 // ex: Getting one element from a vector, and the rest from another.
5497 if (Elem.getOperand(0) != V)
5500 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5503 else if (IncorrectIdx == -1U) {
5507 // There was already one element with an incorrect index.
5508 // We can't optimize this case to an insertps.
5512 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5514 EVT VT = Op.getSimpleValueType();
5515 unsigned ElementMoveMask = 0;
5516 if (IncorrectIdx == -1U)
5517 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5519 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5521 SDValue InsertpsMask =
5522 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5523 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5529 /// getVShift - Return a vector logical shift node.
5531 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5532 unsigned NumBits, SelectionDAG &DAG,
5533 const TargetLowering &TLI, SDLoc dl) {
5534 assert(VT.is128BitVector() && "Unknown type for VShift");
5535 EVT ShVT = MVT::v2i64;
5536 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5537 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5538 return DAG.getNode(ISD::BITCAST, dl, VT,
5539 DAG.getNode(Opc, dl, ShVT, SrcOp,
5540 DAG.getConstant(NumBits,
5541 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5545 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5547 // Check if the scalar load can be widened into a vector load. And if
5548 // the address is "base + cst" see if the cst can be "absorbed" into
5549 // the shuffle mask.
5550 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5551 SDValue Ptr = LD->getBasePtr();
5552 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5554 EVT PVT = LD->getValueType(0);
5555 if (PVT != MVT::i32 && PVT != MVT::f32)
5560 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5561 FI = FINode->getIndex();
5563 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5564 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5565 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5566 Offset = Ptr.getConstantOperandVal(1);
5567 Ptr = Ptr.getOperand(0);
5572 // FIXME: 256-bit vector instructions don't require a strict alignment,
5573 // improve this code to support it better.
5574 unsigned RequiredAlign = VT.getSizeInBits()/8;
5575 SDValue Chain = LD->getChain();
5576 // Make sure the stack object alignment is at least 16 or 32.
5577 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5578 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5579 if (MFI->isFixedObjectIndex(FI)) {
5580 // Can't change the alignment. FIXME: It's possible to compute
5581 // the exact stack offset and reference FI + adjust offset instead.
5582 // If someone *really* cares about this. That's the way to implement it.
5585 MFI->setObjectAlignment(FI, RequiredAlign);
5589 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5590 // Ptr + (Offset & ~15).
5593 if ((Offset % RequiredAlign) & 3)
5595 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5597 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5598 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5600 int EltNo = (Offset - StartOffset) >> 2;
5601 unsigned NumElems = VT.getVectorNumElements();
5603 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5604 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5605 LD->getPointerInfo().getWithOffset(StartOffset),
5606 false, false, false, 0);
5608 SmallVector<int, 8> Mask;
5609 for (unsigned i = 0; i != NumElems; ++i)
5610 Mask.push_back(EltNo);
5612 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5618 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5619 /// vector of type 'VT', see if the elements can be replaced by a single large
5620 /// load which has the same value as a build_vector whose operands are 'elts'.
5622 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5624 /// FIXME: we'd also like to handle the case where the last elements are zero
5625 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5626 /// There's even a handy isZeroNode for that purpose.
5627 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5628 SDLoc &DL, SelectionDAG &DAG,
5629 bool isAfterLegalize) {
5630 EVT EltVT = VT.getVectorElementType();
5631 unsigned NumElems = Elts.size();
5633 LoadSDNode *LDBase = nullptr;
5634 unsigned LastLoadedElt = -1U;
5636 // For each element in the initializer, see if we've found a load or an undef.
5637 // If we don't find an initial load element, or later load elements are
5638 // non-consecutive, bail out.
5639 for (unsigned i = 0; i < NumElems; ++i) {
5640 SDValue Elt = Elts[i];
5642 if (!Elt.getNode() ||
5643 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5646 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5648 LDBase = cast<LoadSDNode>(Elt.getNode());
5652 if (Elt.getOpcode() == ISD::UNDEF)
5655 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5656 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5661 // If we have found an entire vector of loads and undefs, then return a large
5662 // load of the entire vector width starting at the base pointer. If we found
5663 // consecutive loads for the low half, generate a vzext_load node.
5664 if (LastLoadedElt == NumElems - 1) {
5666 if (isAfterLegalize &&
5667 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5670 SDValue NewLd = SDValue();
5672 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5673 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5674 LDBase->getPointerInfo(),
5675 LDBase->isVolatile(), LDBase->isNonTemporal(),
5676 LDBase->isInvariant(), 0);
5677 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5678 LDBase->getPointerInfo(),
5679 LDBase->isVolatile(), LDBase->isNonTemporal(),
5680 LDBase->isInvariant(), LDBase->getAlignment());
5682 if (LDBase->hasAnyUseOfValue(1)) {
5683 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5685 SDValue(NewLd.getNode(), 1));
5686 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5687 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5688 SDValue(NewLd.getNode(), 1));
5693 if (NumElems == 4 && LastLoadedElt == 1 &&
5694 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5695 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5696 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5698 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5699 LDBase->getPointerInfo(),
5700 LDBase->getAlignment(),
5701 false/*isVolatile*/, true/*ReadMem*/,
5704 // Make sure the newly-created LOAD is in the same position as LDBase in
5705 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5706 // update uses of LDBase's output chain to use the TokenFactor.
5707 if (LDBase->hasAnyUseOfValue(1)) {
5708 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5709 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5710 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5711 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5712 SDValue(ResNode.getNode(), 1));
5715 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5720 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5721 /// to generate a splat value for the following cases:
5722 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5723 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5724 /// a scalar load, or a constant.
5725 /// The VBROADCAST node is returned when a pattern is found,
5726 /// or SDValue() otherwise.
5727 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5728 SelectionDAG &DAG) {
5729 if (!Subtarget->hasFp256())
5732 MVT VT = Op.getSimpleValueType();
5735 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5736 "Unsupported vector type for broadcast.");
5741 switch (Op.getOpcode()) {
5743 // Unknown pattern found.
5746 case ISD::BUILD_VECTOR: {
5747 // The BUILD_VECTOR node must be a splat.
5748 if (!isSplatVector(Op.getNode()))
5751 Ld = Op.getOperand(0);
5752 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5753 Ld.getOpcode() == ISD::ConstantFP);
5755 // The suspected load node has several users. Make sure that all
5756 // of its users are from the BUILD_VECTOR node.
5757 // Constants may have multiple users.
5758 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5763 case ISD::VECTOR_SHUFFLE: {
5764 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5766 // Shuffles must have a splat mask where the first element is
5768 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5771 SDValue Sc = Op.getOperand(0);
5772 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5773 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5775 if (!Subtarget->hasInt256())
5778 // Use the register form of the broadcast instruction available on AVX2.
5779 if (VT.getSizeInBits() >= 256)
5780 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5781 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5784 Ld = Sc.getOperand(0);
5785 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5786 Ld.getOpcode() == ISD::ConstantFP);
5788 // The scalar_to_vector node and the suspected
5789 // load node must have exactly one user.
5790 // Constants may have multiple users.
5792 // AVX-512 has register version of the broadcast
5793 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5794 Ld.getValueType().getSizeInBits() >= 32;
5795 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5802 bool IsGE256 = (VT.getSizeInBits() >= 256);
5804 // Handle the broadcasting a single constant scalar from the constant pool
5805 // into a vector. On Sandybridge it is still better to load a constant vector
5806 // from the constant pool and not to broadcast it from a scalar.
5807 if (ConstSplatVal && Subtarget->hasInt256()) {
5808 EVT CVT = Ld.getValueType();
5809 assert(!CVT.isVector() && "Must not broadcast a vector type");
5810 unsigned ScalarSize = CVT.getSizeInBits();
5812 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5813 const Constant *C = nullptr;
5814 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5815 C = CI->getConstantIntValue();
5816 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5817 C = CF->getConstantFPValue();
5819 assert(C && "Invalid constant type");
5821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5822 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5823 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5824 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5825 MachinePointerInfo::getConstantPool(),
5826 false, false, false, Alignment);
5828 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5832 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5833 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5835 // Handle AVX2 in-register broadcasts.
5836 if (!IsLoad && Subtarget->hasInt256() &&
5837 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5838 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5840 // The scalar source must be a normal load.
5844 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5845 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5847 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5848 // double since there is no vbroadcastsd xmm
5849 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5850 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5851 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5854 // Unsupported broadcast.
5858 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5859 /// underlying vector and index.
5861 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5863 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5865 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5866 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5869 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5871 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5873 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5874 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5877 // In this case the vector is the extract_subvector expression and the index
5878 // is 2, as specified by the shuffle.
5879 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5880 SDValue ShuffleVec = SVOp->getOperand(0);
5881 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5882 assert(ShuffleVecVT.getVectorElementType() ==
5883 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5885 int ShuffleIdx = SVOp->getMaskElt(Idx);
5886 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5887 ExtractedFromVec = ShuffleVec;
5893 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5894 MVT VT = Op.getSimpleValueType();
5896 // Skip if insert_vec_elt is not supported.
5897 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5898 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5902 unsigned NumElems = Op.getNumOperands();
5906 SmallVector<unsigned, 4> InsertIndices;
5907 SmallVector<int, 8> Mask(NumElems, -1);
5909 for (unsigned i = 0; i != NumElems; ++i) {
5910 unsigned Opc = Op.getOperand(i).getOpcode();
5912 if (Opc == ISD::UNDEF)
5915 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5916 // Quit if more than 1 elements need inserting.
5917 if (InsertIndices.size() > 1)
5920 InsertIndices.push_back(i);
5924 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5925 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5926 // Quit if non-constant index.
5927 if (!isa<ConstantSDNode>(ExtIdx))
5929 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5931 // Quit if extracted from vector of different type.
5932 if (ExtractedFromVec.getValueType() != VT)
5935 if (!VecIn1.getNode())
5936 VecIn1 = ExtractedFromVec;
5937 else if (VecIn1 != ExtractedFromVec) {
5938 if (!VecIn2.getNode())
5939 VecIn2 = ExtractedFromVec;
5940 else if (VecIn2 != ExtractedFromVec)
5941 // Quit if more than 2 vectors to shuffle
5945 if (ExtractedFromVec == VecIn1)
5947 else if (ExtractedFromVec == VecIn2)
5948 Mask[i] = Idx + NumElems;
5951 if (!VecIn1.getNode())
5954 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5955 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5956 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5957 unsigned Idx = InsertIndices[i];
5958 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5959 DAG.getIntPtrConstant(Idx));
5965 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5967 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5969 MVT VT = Op.getSimpleValueType();
5970 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5971 "Unexpected type in LowerBUILD_VECTORvXi1!");
5974 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5975 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5976 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5977 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5980 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5981 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5982 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5983 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5986 bool AllContants = true;
5987 uint64_t Immediate = 0;
5988 int NonConstIdx = -1;
5989 bool IsSplat = true;
5990 unsigned NumNonConsts = 0;
5991 unsigned NumConsts = 0;
5992 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5993 SDValue In = Op.getOperand(idx);
5994 if (In.getOpcode() == ISD::UNDEF)
5996 if (!isa<ConstantSDNode>(In)) {
5997 AllContants = false;
6003 if (cast<ConstantSDNode>(In)->getZExtValue())
6004 Immediate |= (1ULL << idx);
6006 if (In != Op.getOperand(0))
6011 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6012 DAG.getConstant(Immediate, MVT::i16));
6013 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6014 DAG.getIntPtrConstant(0));
6017 if (NumNonConsts == 1 && NonConstIdx != 0) {
6020 SDValue VecAsImm = DAG.getConstant(Immediate,
6021 MVT::getIntegerVT(VT.getSizeInBits()));
6022 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6025 DstVec = DAG.getUNDEF(VT);
6026 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6027 Op.getOperand(NonConstIdx),
6028 DAG.getIntPtrConstant(NonConstIdx));
6030 if (!IsSplat && (NonConstIdx != 0))
6031 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6032 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6035 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6036 DAG.getConstant(-1, SelectVT),
6037 DAG.getConstant(0, SelectVT));
6039 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6040 DAG.getConstant((Immediate | 1), SelectVT),
6041 DAG.getConstant(Immediate, SelectVT));
6042 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6046 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6049 MVT VT = Op.getSimpleValueType();
6050 MVT ExtVT = VT.getVectorElementType();
6051 unsigned NumElems = Op.getNumOperands();
6053 // Generate vectors for predicate vectors.
6054 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6055 return LowerBUILD_VECTORvXi1(Op, DAG);
6057 // Vectors containing all zeros can be matched by pxor and xorps later
6058 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6059 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6060 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6061 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6064 return getZeroVector(VT, Subtarget, DAG, dl);
6067 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6068 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6069 // vpcmpeqd on 256-bit vectors.
6070 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6071 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6074 if (!VT.is512BitVector())
6075 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6078 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6079 if (Broadcast.getNode())
6082 unsigned EVTBits = ExtVT.getSizeInBits();
6084 unsigned NumZero = 0;
6085 unsigned NumNonZero = 0;
6086 unsigned NonZeros = 0;
6087 bool IsAllConstants = true;
6088 SmallSet<SDValue, 8> Values;
6089 for (unsigned i = 0; i < NumElems; ++i) {
6090 SDValue Elt = Op.getOperand(i);
6091 if (Elt.getOpcode() == ISD::UNDEF)
6094 if (Elt.getOpcode() != ISD::Constant &&
6095 Elt.getOpcode() != ISD::ConstantFP)
6096 IsAllConstants = false;
6097 if (X86::isZeroNode(Elt))
6100 NonZeros |= (1 << i);
6105 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6106 if (NumNonZero == 0)
6107 return DAG.getUNDEF(VT);
6109 // Special case for single non-zero, non-undef, element.
6110 if (NumNonZero == 1) {
6111 unsigned Idx = countTrailingZeros(NonZeros);
6112 SDValue Item = Op.getOperand(Idx);
6114 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6115 // the value are obviously zero, truncate the value to i32 and do the
6116 // insertion that way. Only do this if the value is non-constant or if the
6117 // value is a constant being inserted into element 0. It is cheaper to do
6118 // a constant pool load than it is to do a movd + shuffle.
6119 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6120 (!IsAllConstants || Idx == 0)) {
6121 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6123 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6124 EVT VecVT = MVT::v4i32;
6125 unsigned VecElts = 4;
6127 // Truncate the value (which may itself be a constant) to i32, and
6128 // convert it to a vector with movd (S2V+shuffle to zero extend).
6129 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6130 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6131 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6133 // Now we have our 32-bit value zero extended in the low element of
6134 // a vector. If Idx != 0, swizzle it into place.
6136 SmallVector<int, 4> Mask;
6137 Mask.push_back(Idx);
6138 for (unsigned i = 1; i != VecElts; ++i)
6140 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6143 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6147 // If we have a constant or non-constant insertion into the low element of
6148 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6149 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6150 // depending on what the source datatype is.
6153 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6155 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6156 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6157 if (VT.is256BitVector() || VT.is512BitVector()) {
6158 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6159 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6160 Item, DAG.getIntPtrConstant(0));
6162 assert(VT.is128BitVector() && "Expected an SSE value type!");
6163 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6164 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6165 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6168 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6169 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6170 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6171 if (VT.is256BitVector()) {
6172 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6173 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6175 assert(VT.is128BitVector() && "Expected an SSE value type!");
6176 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6178 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6182 // Is it a vector logical left shift?
6183 if (NumElems == 2 && Idx == 1 &&
6184 X86::isZeroNode(Op.getOperand(0)) &&
6185 !X86::isZeroNode(Op.getOperand(1))) {
6186 unsigned NumBits = VT.getSizeInBits();
6187 return getVShift(true, VT,
6188 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6189 VT, Op.getOperand(1)),
6190 NumBits/2, DAG, *this, dl);
6193 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6196 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6197 // is a non-constant being inserted into an element other than the low one,
6198 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6199 // movd/movss) to move this into the low element, then shuffle it into
6201 if (EVTBits == 32) {
6202 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6204 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6205 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6206 SmallVector<int, 8> MaskVec;
6207 for (unsigned i = 0; i != NumElems; ++i)
6208 MaskVec.push_back(i == Idx ? 0 : 1);
6209 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6213 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6214 if (Values.size() == 1) {
6215 if (EVTBits == 32) {
6216 // Instead of a shuffle like this:
6217 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6218 // Check if it's possible to issue this instead.
6219 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6220 unsigned Idx = countTrailingZeros(NonZeros);
6221 SDValue Item = Op.getOperand(Idx);
6222 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6223 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6228 // A vector full of immediates; various special cases are already
6229 // handled, so this is best done with a single constant-pool load.
6233 // For AVX-length vectors, build the individual 128-bit pieces and use
6234 // shuffles to put them in place.
6235 if (VT.is256BitVector() || VT.is512BitVector()) {
6236 SmallVector<SDValue, 64> V;
6237 for (unsigned i = 0; i != NumElems; ++i)
6238 V.push_back(Op.getOperand(i));
6240 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6242 // Build both the lower and upper subvector.
6243 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6244 makeArrayRef(&V[0], NumElems/2));
6245 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6246 makeArrayRef(&V[NumElems / 2], NumElems/2));
6248 // Recreate the wider vector with the lower and upper part.
6249 if (VT.is256BitVector())
6250 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6251 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6254 // Let legalizer expand 2-wide build_vectors.
6255 if (EVTBits == 64) {
6256 if (NumNonZero == 1) {
6257 // One half is zero or undef.
6258 unsigned Idx = countTrailingZeros(NonZeros);
6259 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6260 Op.getOperand(Idx));
6261 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6266 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6267 if (EVTBits == 8 && NumElems == 16) {
6268 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6270 if (V.getNode()) return V;
6273 if (EVTBits == 16 && NumElems == 8) {
6274 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6276 if (V.getNode()) return V;
6279 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6280 if (EVTBits == 32 && NumElems == 4) {
6281 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6282 NumZero, DAG, Subtarget, *this);
6287 // If element VT is == 32 bits, turn it into a number of shuffles.
6288 SmallVector<SDValue, 8> V(NumElems);
6289 if (NumElems == 4 && NumZero > 0) {
6290 for (unsigned i = 0; i < 4; ++i) {
6291 bool isZero = !(NonZeros & (1 << i));
6293 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6295 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6298 for (unsigned i = 0; i < 2; ++i) {
6299 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6302 V[i] = V[i*2]; // Must be a zero vector.
6305 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6308 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6311 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6316 bool Reverse1 = (NonZeros & 0x3) == 2;
6317 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6321 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6322 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6324 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6327 if (Values.size() > 1 && VT.is128BitVector()) {
6328 // Check for a build vector of consecutive loads.
6329 for (unsigned i = 0; i < NumElems; ++i)
6330 V[i] = Op.getOperand(i);
6332 // Check for elements which are consecutive loads.
6333 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6337 // Check for a build vector from mostly shuffle plus few inserting.
6338 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6342 // For SSE 4.1, use insertps to put the high elements into the low element.
6343 if (getSubtarget()->hasSSE41()) {
6345 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6346 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6348 Result = DAG.getUNDEF(VT);
6350 for (unsigned i = 1; i < NumElems; ++i) {
6351 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6352 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6353 Op.getOperand(i), DAG.getIntPtrConstant(i));
6358 // Otherwise, expand into a number of unpckl*, start by extending each of
6359 // our (non-undef) elements to the full vector width with the element in the
6360 // bottom slot of the vector (which generates no code for SSE).
6361 for (unsigned i = 0; i < NumElems; ++i) {
6362 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6363 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6365 V[i] = DAG.getUNDEF(VT);
6368 // Next, we iteratively mix elements, e.g. for v4f32:
6369 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6370 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6371 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6372 unsigned EltStride = NumElems >> 1;
6373 while (EltStride != 0) {
6374 for (unsigned i = 0; i < EltStride; ++i) {
6375 // If V[i+EltStride] is undef and this is the first round of mixing,
6376 // then it is safe to just drop this shuffle: V[i] is already in the
6377 // right place, the one element (since it's the first round) being
6378 // inserted as undef can be dropped. This isn't safe for successive
6379 // rounds because they will permute elements within both vectors.
6380 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6381 EltStride == NumElems/2)
6384 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6393 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6394 // to create 256-bit vectors from two other 128-bit ones.
6395 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6397 MVT ResVT = Op.getSimpleValueType();
6399 assert((ResVT.is256BitVector() ||
6400 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6402 SDValue V1 = Op.getOperand(0);
6403 SDValue V2 = Op.getOperand(1);
6404 unsigned NumElems = ResVT.getVectorNumElements();
6405 if(ResVT.is256BitVector())
6406 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6408 if (Op.getNumOperands() == 4) {
6409 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6410 ResVT.getVectorNumElements()/2);
6411 SDValue V3 = Op.getOperand(2);
6412 SDValue V4 = Op.getOperand(3);
6413 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6414 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6416 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6419 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6420 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6421 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6422 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6423 Op.getNumOperands() == 4)));
6425 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6426 // from two other 128-bit ones.
6428 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6429 return LowerAVXCONCAT_VECTORS(Op, DAG);
6432 // Try to lower a shuffle node into a simple blend instruction.
6434 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6435 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6436 SDValue V1 = SVOp->getOperand(0);
6437 SDValue V2 = SVOp->getOperand(1);
6439 MVT VT = SVOp->getSimpleValueType(0);
6440 MVT EltVT = VT.getVectorElementType();
6441 unsigned NumElems = VT.getVectorNumElements();
6443 // There is no blend with immediate in AVX-512.
6444 if (VT.is512BitVector())
6447 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6449 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6452 // Check the mask for BLEND and build the value.
6453 unsigned MaskValue = 0;
6454 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6455 unsigned NumLanes = (NumElems-1)/8 + 1;
6456 unsigned NumElemsInLane = NumElems / NumLanes;
6458 // Blend for v16i16 should be symetric for the both lanes.
6459 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6461 int SndLaneEltIdx = (NumLanes == 2) ?
6462 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6463 int EltIdx = SVOp->getMaskElt(i);
6465 if ((EltIdx < 0 || EltIdx == (int)i) &&
6466 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6469 if (((unsigned)EltIdx == (i + NumElems)) &&
6470 (SndLaneEltIdx < 0 ||
6471 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6472 MaskValue |= (1<<i);
6477 // Convert i32 vectors to floating point if it is not AVX2.
6478 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6480 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6481 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6483 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6484 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6487 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6488 DAG.getConstant(MaskValue, MVT::i32));
6489 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6492 /// In vector type \p VT, return true if the element at index \p InputIdx
6493 /// falls on a different 128-bit lane than \p OutputIdx.
6494 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
6495 unsigned OutputIdx) {
6496 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6497 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
6500 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
6501 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
6502 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
6503 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
6505 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
6506 SelectionDAG &DAG) {
6507 MVT VT = V1.getSimpleValueType();
6508 assert(VT.is128BitVector() || VT.is256BitVector());
6510 MVT EltVT = VT.getVectorElementType();
6511 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
6512 unsigned NumElts = VT.getVectorNumElements();
6514 SmallVector<SDValue, 32> PshufbMask;
6515 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
6516 int InputIdx = MaskVals[OutputIdx];
6517 unsigned InputByteIdx;
6519 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
6520 InputByteIdx = 0x80;
6522 // Cross lane is not allowed.
6523 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
6525 InputByteIdx = InputIdx * EltSizeInBytes;
6526 // Index is an byte offset within the 128-bit lane.
6527 InputByteIdx &= 0xf;
6530 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
6531 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
6532 if (InputByteIdx != 0x80)
6537 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
6539 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
6540 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
6541 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
6544 // v8i16 shuffles - Prefer shuffles in the following order:
6545 // 1. [all] pshuflw, pshufhw, optional move
6546 // 2. [ssse3] 1 x pshufb
6547 // 3. [ssse3] 2 x pshufb + 1 x por
6548 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6550 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6551 SelectionDAG &DAG) {
6552 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6553 SDValue V1 = SVOp->getOperand(0);
6554 SDValue V2 = SVOp->getOperand(1);
6556 SmallVector<int, 8> MaskVals;
6558 // Determine if more than 1 of the words in each of the low and high quadwords
6559 // of the result come from the same quadword of one of the two inputs. Undef
6560 // mask values count as coming from any quadword, for better codegen.
6562 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
6563 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
6564 unsigned LoQuad[] = { 0, 0, 0, 0 };
6565 unsigned HiQuad[] = { 0, 0, 0, 0 };
6566 // Indices of quads used.
6567 std::bitset<4> InputQuads;
6568 for (unsigned i = 0; i < 8; ++i) {
6569 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6570 int EltIdx = SVOp->getMaskElt(i);
6571 MaskVals.push_back(EltIdx);
6580 InputQuads.set(EltIdx / 4);
6583 int BestLoQuad = -1;
6584 unsigned MaxQuad = 1;
6585 for (unsigned i = 0; i < 4; ++i) {
6586 if (LoQuad[i] > MaxQuad) {
6588 MaxQuad = LoQuad[i];
6592 int BestHiQuad = -1;
6594 for (unsigned i = 0; i < 4; ++i) {
6595 if (HiQuad[i] > MaxQuad) {
6597 MaxQuad = HiQuad[i];
6601 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6602 // of the two input vectors, shuffle them into one input vector so only a
6603 // single pshufb instruction is necessary. If there are more than 2 input
6604 // quads, disable the next transformation since it does not help SSSE3.
6605 bool V1Used = InputQuads[0] || InputQuads[1];
6606 bool V2Used = InputQuads[2] || InputQuads[3];
6607 if (Subtarget->hasSSSE3()) {
6608 if (InputQuads.count() == 2 && V1Used && V2Used) {
6609 BestLoQuad = InputQuads[0] ? 0 : 1;
6610 BestHiQuad = InputQuads[2] ? 2 : 3;
6612 if (InputQuads.count() > 2) {
6618 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6619 // the shuffle mask. If a quad is scored as -1, that means that it contains
6620 // words from all 4 input quadwords.
6622 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6624 BestLoQuad < 0 ? 0 : BestLoQuad,
6625 BestHiQuad < 0 ? 1 : BestHiQuad
6627 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6628 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6629 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6630 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6632 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6633 // source words for the shuffle, to aid later transformations.
6634 bool AllWordsInNewV = true;
6635 bool InOrder[2] = { true, true };
6636 for (unsigned i = 0; i != 8; ++i) {
6637 int idx = MaskVals[i];
6639 InOrder[i/4] = false;
6640 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6642 AllWordsInNewV = false;
6646 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6647 if (AllWordsInNewV) {
6648 for (int i = 0; i != 8; ++i) {
6649 int idx = MaskVals[i];
6652 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6653 if ((idx != i) && idx < 4)
6655 if ((idx != i) && idx > 3)
6664 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6665 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6666 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6667 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6668 unsigned TargetMask = 0;
6669 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6670 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6671 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6672 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6673 getShufflePSHUFLWImmediate(SVOp);
6674 V1 = NewV.getOperand(0);
6675 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6679 // Promote splats to a larger type which usually leads to more efficient code.
6680 // FIXME: Is this true if pshufb is available?
6681 if (SVOp->isSplat())
6682 return PromoteSplat(SVOp, DAG);
6684 // If we have SSSE3, and all words of the result are from 1 input vector,
6685 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6686 // is present, fall back to case 4.
6687 if (Subtarget->hasSSSE3()) {
6688 SmallVector<SDValue,16> pshufbMask;
6690 // If we have elements from both input vectors, set the high bit of the
6691 // shuffle mask element to zero out elements that come from V2 in the V1
6692 // mask, and elements that come from V1 in the V2 mask, so that the two
6693 // results can be OR'd together.
6694 bool TwoInputs = V1Used && V2Used;
6695 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
6697 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6699 // Calculate the shuffle mask for the second input, shuffle it, and
6700 // OR it with the first shuffled input.
6701 CommuteVectorShuffleMask(MaskVals, 8);
6702 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
6703 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6704 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6707 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6708 // and update MaskVals with new element order.
6709 std::bitset<8> InOrder;
6710 if (BestLoQuad >= 0) {
6711 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6712 for (int i = 0; i != 4; ++i) {
6713 int idx = MaskVals[i];
6716 } else if ((idx / 4) == BestLoQuad) {
6721 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6724 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
6725 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6726 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6728 getShufflePSHUFLWImmediate(SVOp), DAG);
6732 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6733 // and update MaskVals with the new element order.
6734 if (BestHiQuad >= 0) {
6735 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6736 for (unsigned i = 4; i != 8; ++i) {
6737 int idx = MaskVals[i];
6740 } else if ((idx / 4) == BestHiQuad) {
6741 MaskV[i] = (idx & 3) + 4;
6745 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6748 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
6749 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6750 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6752 getShufflePSHUFHWImmediate(SVOp), DAG);
6756 // In case BestHi & BestLo were both -1, which means each quadword has a word
6757 // from each of the four input quadwords, calculate the InOrder bitvector now
6758 // before falling through to the insert/extract cleanup.
6759 if (BestLoQuad == -1 && BestHiQuad == -1) {
6761 for (int i = 0; i != 8; ++i)
6762 if (MaskVals[i] < 0 || MaskVals[i] == i)
6766 // The other elements are put in the right place using pextrw and pinsrw.
6767 for (unsigned i = 0; i != 8; ++i) {
6770 int EltIdx = MaskVals[i];
6773 SDValue ExtOp = (EltIdx < 8) ?
6774 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6775 DAG.getIntPtrConstant(EltIdx)) :
6776 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6777 DAG.getIntPtrConstant(EltIdx - 8));
6778 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6779 DAG.getIntPtrConstant(i));
6784 /// \brief v16i16 shuffles
6786 /// FIXME: We only support generation of a single pshufb currently. We can
6787 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
6788 /// well (e.g 2 x pshufb + 1 x por).
6790 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
6791 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6792 SDValue V1 = SVOp->getOperand(0);
6793 SDValue V2 = SVOp->getOperand(1);
6796 if (V2.getOpcode() != ISD::UNDEF)
6799 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6800 return getPSHUFB(MaskVals, V1, dl, DAG);
6803 // v16i8 shuffles - Prefer shuffles in the following order:
6804 // 1. [ssse3] 1 x pshufb
6805 // 2. [ssse3] 2 x pshufb + 1 x por
6806 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6807 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6808 const X86Subtarget* Subtarget,
6809 SelectionDAG &DAG) {
6810 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6811 SDValue V1 = SVOp->getOperand(0);
6812 SDValue V2 = SVOp->getOperand(1);
6814 ArrayRef<int> MaskVals = SVOp->getMask();
6816 // Promote splats to a larger type which usually leads to more efficient code.
6817 // FIXME: Is this true if pshufb is available?
6818 if (SVOp->isSplat())
6819 return PromoteSplat(SVOp, DAG);
6821 // If we have SSSE3, case 1 is generated when all result bytes come from
6822 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6823 // present, fall back to case 3.
6825 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6826 if (Subtarget->hasSSSE3()) {
6827 SmallVector<SDValue,16> pshufbMask;
6829 // If all result elements are from one input vector, then only translate
6830 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6832 // Otherwise, we have elements from both input vectors, and must zero out
6833 // elements that come from V2 in the first mask, and V1 in the second mask
6834 // so that we can OR them together.
6835 for (unsigned i = 0; i != 16; ++i) {
6836 int EltIdx = MaskVals[i];
6837 if (EltIdx < 0 || EltIdx >= 16)
6839 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6841 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6842 DAG.getNode(ISD::BUILD_VECTOR, dl,
6843 MVT::v16i8, pshufbMask));
6845 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6846 // the 2nd operand if it's undefined or zero.
6847 if (V2.getOpcode() == ISD::UNDEF ||
6848 ISD::isBuildVectorAllZeros(V2.getNode()))
6851 // Calculate the shuffle mask for the second input, shuffle it, and
6852 // OR it with the first shuffled input.
6854 for (unsigned i = 0; i != 16; ++i) {
6855 int EltIdx = MaskVals[i];
6856 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6857 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6859 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6860 DAG.getNode(ISD::BUILD_VECTOR, dl,
6861 MVT::v16i8, pshufbMask));
6862 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6865 // No SSSE3 - Calculate in place words and then fix all out of place words
6866 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6867 // the 16 different words that comprise the two doublequadword input vectors.
6868 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6869 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6871 for (int i = 0; i != 8; ++i) {
6872 int Elt0 = MaskVals[i*2];
6873 int Elt1 = MaskVals[i*2+1];
6875 // This word of the result is all undef, skip it.
6876 if (Elt0 < 0 && Elt1 < 0)
6879 // This word of the result is already in the correct place, skip it.
6880 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6883 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6884 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6887 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6888 // using a single extract together, load it and store it.
6889 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6890 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6891 DAG.getIntPtrConstant(Elt1 / 2));
6892 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6893 DAG.getIntPtrConstant(i));
6897 // If Elt1 is defined, extract it from the appropriate source. If the
6898 // source byte is not also odd, shift the extracted word left 8 bits
6899 // otherwise clear the bottom 8 bits if we need to do an or.
6901 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6902 DAG.getIntPtrConstant(Elt1 / 2));
6903 if ((Elt1 & 1) == 0)
6904 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6906 TLI.getShiftAmountTy(InsElt.getValueType())));
6908 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6909 DAG.getConstant(0xFF00, MVT::i16));
6911 // If Elt0 is defined, extract it from the appropriate source. If the
6912 // source byte is not also even, shift the extracted word right 8 bits. If
6913 // Elt1 was also defined, OR the extracted values together before
6914 // inserting them in the result.
6916 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6917 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6918 if ((Elt0 & 1) != 0)
6919 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6921 TLI.getShiftAmountTy(InsElt0.getValueType())));
6923 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6924 DAG.getConstant(0x00FF, MVT::i16));
6925 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6928 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6929 DAG.getIntPtrConstant(i));
6931 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6934 // v32i8 shuffles - Translate to VPSHUFB if possible.
6936 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6937 const X86Subtarget *Subtarget,
6938 SelectionDAG &DAG) {
6939 MVT VT = SVOp->getSimpleValueType(0);
6940 SDValue V1 = SVOp->getOperand(0);
6941 SDValue V2 = SVOp->getOperand(1);
6943 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6945 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6946 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6947 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6949 // VPSHUFB may be generated if
6950 // (1) one of input vector is undefined or zeroinitializer.
6951 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6952 // And (2) the mask indexes don't cross the 128-bit lane.
6953 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6954 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6957 if (V1IsAllZero && !V2IsAllZero) {
6958 CommuteVectorShuffleMask(MaskVals, 32);
6961 return getPSHUFB(MaskVals, V1, dl, DAG);
6964 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6965 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6966 /// done when every pair / quad of shuffle mask elements point to elements in
6967 /// the right sequence. e.g.
6968 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6970 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6971 SelectionDAG &DAG) {
6972 MVT VT = SVOp->getSimpleValueType(0);
6974 unsigned NumElems = VT.getVectorNumElements();
6977 switch (VT.SimpleTy) {
6978 default: llvm_unreachable("Unexpected!");
6981 return SDValue(SVOp, 0);
6982 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6983 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6984 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6985 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6986 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6987 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6990 SmallVector<int, 8> MaskVec;
6991 for (unsigned i = 0; i != NumElems; i += Scale) {
6993 for (unsigned j = 0; j != Scale; ++j) {
6994 int EltIdx = SVOp->getMaskElt(i+j);
6998 StartIdx = (EltIdx / Scale);
6999 if (EltIdx != (int)(StartIdx*Scale + j))
7002 MaskVec.push_back(StartIdx);
7005 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
7006 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
7007 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
7010 /// getVZextMovL - Return a zero-extending vector move low node.
7012 static SDValue getVZextMovL(MVT VT, MVT OpVT,
7013 SDValue SrcOp, SelectionDAG &DAG,
7014 const X86Subtarget *Subtarget, SDLoc dl) {
7015 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
7016 LoadSDNode *LD = nullptr;
7017 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
7018 LD = dyn_cast<LoadSDNode>(SrcOp);
7020 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
7022 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
7023 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
7024 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7025 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
7026 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
7028 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
7029 return DAG.getNode(ISD::BITCAST, dl, VT,
7030 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
7031 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7039 return DAG.getNode(ISD::BITCAST, dl, VT,
7040 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
7041 DAG.getNode(ISD::BITCAST, dl,
7045 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
7046 /// which could not be matched by any known target speficic shuffle
7048 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
7050 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
7051 if (NewOp.getNode())
7054 MVT VT = SVOp->getSimpleValueType(0);
7056 unsigned NumElems = VT.getVectorNumElements();
7057 unsigned NumLaneElems = NumElems / 2;
7060 MVT EltVT = VT.getVectorElementType();
7061 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
7064 SmallVector<int, 16> Mask;
7065 for (unsigned l = 0; l < 2; ++l) {
7066 // Build a shuffle mask for the output, discovering on the fly which
7067 // input vectors to use as shuffle operands (recorded in InputUsed).
7068 // If building a suitable shuffle vector proves too hard, then bail
7069 // out with UseBuildVector set.
7070 bool UseBuildVector = false;
7071 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
7072 unsigned LaneStart = l * NumLaneElems;
7073 for (unsigned i = 0; i != NumLaneElems; ++i) {
7074 // The mask element. This indexes into the input.
7075 int Idx = SVOp->getMaskElt(i+LaneStart);
7077 // the mask element does not index into any input vector.
7082 // The input vector this mask element indexes into.
7083 int Input = Idx / NumLaneElems;
7085 // Turn the index into an offset from the start of the input vector.
7086 Idx -= Input * NumLaneElems;
7088 // Find or create a shuffle vector operand to hold this input.
7090 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
7091 if (InputUsed[OpNo] == Input)
7092 // This input vector is already an operand.
7094 if (InputUsed[OpNo] < 0) {
7095 // Create a new operand for this input vector.
7096 InputUsed[OpNo] = Input;
7101 if (OpNo >= array_lengthof(InputUsed)) {
7102 // More than two input vectors used! Give up on trying to create a
7103 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
7104 UseBuildVector = true;
7108 // Add the mask index for the new shuffle vector.
7109 Mask.push_back(Idx + OpNo * NumLaneElems);
7112 if (UseBuildVector) {
7113 SmallVector<SDValue, 16> SVOps;
7114 for (unsigned i = 0; i != NumLaneElems; ++i) {
7115 // The mask element. This indexes into the input.
7116 int Idx = SVOp->getMaskElt(i+LaneStart);
7118 SVOps.push_back(DAG.getUNDEF(EltVT));
7122 // The input vector this mask element indexes into.
7123 int Input = Idx / NumElems;
7125 // Turn the index into an offset from the start of the input vector.
7126 Idx -= Input * NumElems;
7128 // Extract the vector element by hand.
7129 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
7130 SVOp->getOperand(Input),
7131 DAG.getIntPtrConstant(Idx)));
7134 // Construct the output using a BUILD_VECTOR.
7135 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
7136 } else if (InputUsed[0] < 0) {
7137 // No input vectors were used! The result is undefined.
7138 Output[l] = DAG.getUNDEF(NVT);
7140 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
7141 (InputUsed[0] % 2) * NumLaneElems,
7143 // If only one input was used, use an undefined vector for the other.
7144 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
7145 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
7146 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
7147 // At least one input vector was used. Create a new shuffle vector.
7148 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
7154 // Concatenate the result back
7155 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
7158 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
7159 /// 4 elements, and match them with several different shuffle types.
7161 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
7162 SDValue V1 = SVOp->getOperand(0);
7163 SDValue V2 = SVOp->getOperand(1);
7165 MVT VT = SVOp->getSimpleValueType(0);
7167 assert(VT.is128BitVector() && "Unsupported vector size");
7169 std::pair<int, int> Locs[4];
7170 int Mask1[] = { -1, -1, -1, -1 };
7171 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
7175 for (unsigned i = 0; i != 4; ++i) {
7176 int Idx = PermMask[i];
7178 Locs[i] = std::make_pair(-1, -1);
7180 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
7182 Locs[i] = std::make_pair(0, NumLo);
7186 Locs[i] = std::make_pair(1, NumHi);
7188 Mask1[2+NumHi] = Idx;
7194 if (NumLo <= 2 && NumHi <= 2) {
7195 // If no more than two elements come from either vector. This can be
7196 // implemented with two shuffles. First shuffle gather the elements.
7197 // The second shuffle, which takes the first shuffle as both of its
7198 // vector operands, put the elements into the right order.
7199 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7201 int Mask2[] = { -1, -1, -1, -1 };
7203 for (unsigned i = 0; i != 4; ++i)
7204 if (Locs[i].first != -1) {
7205 unsigned Idx = (i < 2) ? 0 : 4;
7206 Idx += Locs[i].first * 2 + Locs[i].second;
7210 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
7213 if (NumLo == 3 || NumHi == 3) {
7214 // Otherwise, we must have three elements from one vector, call it X, and
7215 // one element from the other, call it Y. First, use a shufps to build an
7216 // intermediate vector with the one element from Y and the element from X
7217 // that will be in the same half in the final destination (the indexes don't
7218 // matter). Then, use a shufps to build the final vector, taking the half
7219 // containing the element from Y from the intermediate, and the other half
7222 // Normalize it so the 3 elements come from V1.
7223 CommuteVectorShuffleMask(PermMask, 4);
7227 // Find the element from V2.
7229 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
7230 int Val = PermMask[HiIndex];
7237 Mask1[0] = PermMask[HiIndex];
7239 Mask1[2] = PermMask[HiIndex^1];
7241 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7244 Mask1[0] = PermMask[0];
7245 Mask1[1] = PermMask[1];
7246 Mask1[2] = HiIndex & 1 ? 6 : 4;
7247 Mask1[3] = HiIndex & 1 ? 4 : 6;
7248 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7251 Mask1[0] = HiIndex & 1 ? 2 : 0;
7252 Mask1[1] = HiIndex & 1 ? 0 : 2;
7253 Mask1[2] = PermMask[2];
7254 Mask1[3] = PermMask[3];
7259 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
7262 // Break it into (shuffle shuffle_hi, shuffle_lo).
7263 int LoMask[] = { -1, -1, -1, -1 };
7264 int HiMask[] = { -1, -1, -1, -1 };
7266 int *MaskPtr = LoMask;
7267 unsigned MaskIdx = 0;
7270 for (unsigned i = 0; i != 4; ++i) {
7277 int Idx = PermMask[i];
7279 Locs[i] = std::make_pair(-1, -1);
7280 } else if (Idx < 4) {
7281 Locs[i] = std::make_pair(MaskIdx, LoIdx);
7282 MaskPtr[LoIdx] = Idx;
7285 Locs[i] = std::make_pair(MaskIdx, HiIdx);
7286 MaskPtr[HiIdx] = Idx;
7291 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
7292 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
7293 int MaskOps[] = { -1, -1, -1, -1 };
7294 for (unsigned i = 0; i != 4; ++i)
7295 if (Locs[i].first != -1)
7296 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7297 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7300 static bool MayFoldVectorLoad(SDValue V) {
7301 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7302 V = V.getOperand(0);
7304 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7305 V = V.getOperand(0);
7306 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7307 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7308 // BUILD_VECTOR (load), undef
7309 V = V.getOperand(0);
7311 return MayFoldLoad(V);
7315 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7316 MVT VT = Op.getSimpleValueType();
7318 // Canonizalize to v2f64.
7319 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7320 return DAG.getNode(ISD::BITCAST, dl, VT,
7321 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7326 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7328 SDValue V1 = Op.getOperand(0);
7329 SDValue V2 = Op.getOperand(1);
7330 MVT VT = Op.getSimpleValueType();
7332 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7334 if (HasSSE2 && VT == MVT::v2f64)
7335 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7337 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7338 return DAG.getNode(ISD::BITCAST, dl, VT,
7339 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7340 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7341 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7345 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7346 SDValue V1 = Op.getOperand(0);
7347 SDValue V2 = Op.getOperand(1);
7348 MVT VT = Op.getSimpleValueType();
7350 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7351 "unsupported shuffle type");
7353 if (V2.getOpcode() == ISD::UNDEF)
7357 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7361 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7362 SDValue V1 = Op.getOperand(0);
7363 SDValue V2 = Op.getOperand(1);
7364 MVT VT = Op.getSimpleValueType();
7365 unsigned NumElems = VT.getVectorNumElements();
7367 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7368 // operand of these instructions is only memory, so check if there's a
7369 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7371 bool CanFoldLoad = false;
7373 // Trivial case, when V2 comes from a load.
7374 if (MayFoldVectorLoad(V2))
7377 // When V1 is a load, it can be folded later into a store in isel, example:
7378 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7380 // (MOVLPSmr addr:$src1, VR128:$src2)
7381 // So, recognize this potential and also use MOVLPS or MOVLPD
7382 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7385 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7387 if (HasSSE2 && NumElems == 2)
7388 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7391 // If we don't care about the second element, proceed to use movss.
7392 if (SVOp->getMaskElt(1) != -1)
7393 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7396 // movl and movlp will both match v2i64, but v2i64 is never matched by
7397 // movl earlier because we make it strict to avoid messing with the movlp load
7398 // folding logic (see the code above getMOVLP call). Match it here then,
7399 // this is horrible, but will stay like this until we move all shuffle
7400 // matching to x86 specific nodes. Note that for the 1st condition all
7401 // types are matched with movsd.
7403 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7404 // as to remove this logic from here, as much as possible
7405 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7406 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7407 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7410 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7412 // Invert the operand order and use SHUFPS to match it.
7413 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7414 getShuffleSHUFImmediate(SVOp), DAG);
7417 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
7418 SelectionDAG &DAG) {
7420 MVT VT = Load->getSimpleValueType(0);
7421 MVT EVT = VT.getVectorElementType();
7422 SDValue Addr = Load->getOperand(1);
7423 SDValue NewAddr = DAG.getNode(
7424 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
7425 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
7428 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
7429 DAG.getMachineFunction().getMachineMemOperand(
7430 Load->getMemOperand(), 0, EVT.getStoreSize()));
7434 // It is only safe to call this function if isINSERTPSMask is true for
7435 // this shufflevector mask.
7436 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
7437 SelectionDAG &DAG) {
7438 // Generate an insertps instruction when inserting an f32 from memory onto a
7439 // v4f32 or when copying a member from one v4f32 to another.
7440 // We also use it for transferring i32 from one register to another,
7441 // since it simply copies the same bits.
7442 // If we're transferring an i32 from memory to a specific element in a
7443 // register, we output a generic DAG that will match the PINSRD
7445 MVT VT = SVOp->getSimpleValueType(0);
7446 MVT EVT = VT.getVectorElementType();
7447 SDValue V1 = SVOp->getOperand(0);
7448 SDValue V2 = SVOp->getOperand(1);
7449 auto Mask = SVOp->getMask();
7450 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
7451 "unsupported vector type for insertps/pinsrd");
7453 int FromV1 = std::count_if(Mask.begin(), Mask.end(),
7454 [](const int &i) { return i < 4; });
7462 DestIndex = std::find_if(Mask.begin(), Mask.end(),
7463 [](const int &i) { return i < 4; }) -
7468 DestIndex = std::find_if(Mask.begin(), Mask.end(),
7469 [](const int &i) { return i >= 4; }) -
7473 if (MayFoldLoad(From)) {
7474 // Trivial case, when From comes from a load and is only used by the
7475 // shuffle. Make it use insertps from the vector that we need from that
7478 NarrowVectorLoadToElement(cast<LoadSDNode>(From), DestIndex, DAG);
7479 if (!NewLoad.getNode())
7482 if (EVT == MVT::f32) {
7483 // Create this as a scalar to vector to match the instruction pattern.
7484 SDValue LoadScalarToVector =
7485 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
7486 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
7487 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
7489 } else { // EVT == MVT::i32
7490 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
7491 // instruction, to match the PINSRD instruction, which loads an i32 to a
7492 // certain vector element.
7493 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
7494 DAG.getConstant(DestIndex, MVT::i32));
7498 // Vector-element-to-vector
7499 unsigned SrcIndex = Mask[DestIndex] % 4;
7500 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
7501 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
7504 // Reduce a vector shuffle to zext.
7505 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7506 SelectionDAG &DAG) {
7507 // PMOVZX is only available from SSE41.
7508 if (!Subtarget->hasSSE41())
7511 MVT VT = Op.getSimpleValueType();
7513 // Only AVX2 support 256-bit vector integer extending.
7514 if (!Subtarget->hasInt256() && VT.is256BitVector())
7517 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7519 SDValue V1 = Op.getOperand(0);
7520 SDValue V2 = Op.getOperand(1);
7521 unsigned NumElems = VT.getVectorNumElements();
7523 // Extending is an unary operation and the element type of the source vector
7524 // won't be equal to or larger than i64.
7525 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7526 VT.getVectorElementType() == MVT::i64)
7529 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7530 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7531 while ((1U << Shift) < NumElems) {
7532 if (SVOp->getMaskElt(1U << Shift) == 1)
7535 // The maximal ratio is 8, i.e. from i8 to i64.
7540 // Check the shuffle mask.
7541 unsigned Mask = (1U << Shift) - 1;
7542 for (unsigned i = 0; i != NumElems; ++i) {
7543 int EltIdx = SVOp->getMaskElt(i);
7544 if ((i & Mask) != 0 && EltIdx != -1)
7546 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7550 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7551 MVT NeVT = MVT::getIntegerVT(NBits);
7552 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7554 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7557 // Simplify the operand as it's prepared to be fed into shuffle.
7558 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7559 if (V1.getOpcode() == ISD::BITCAST &&
7560 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7561 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7562 V1.getOperand(0).getOperand(0)
7563 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7564 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7565 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7566 ConstantSDNode *CIdx =
7567 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7568 // If it's foldable, i.e. normal load with single use, we will let code
7569 // selection to fold it. Otherwise, we will short the conversion sequence.
7570 if (CIdx && CIdx->getZExtValue() == 0 &&
7571 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7572 MVT FullVT = V.getSimpleValueType();
7573 MVT V1VT = V1.getSimpleValueType();
7574 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7575 // The "ext_vec_elt" node is wider than the result node.
7576 // In this case we should extract subvector from V.
7577 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7578 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7579 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7580 FullVT.getVectorNumElements()/Ratio);
7581 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7582 DAG.getIntPtrConstant(0));
7584 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7588 return DAG.getNode(ISD::BITCAST, DL, VT,
7589 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7592 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7593 SelectionDAG &DAG) {
7594 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7595 MVT VT = Op.getSimpleValueType();
7597 SDValue V1 = Op.getOperand(0);
7598 SDValue V2 = Op.getOperand(1);
7600 if (isZeroShuffle(SVOp))
7601 return getZeroVector(VT, Subtarget, DAG, dl);
7603 // Handle splat operations
7604 if (SVOp->isSplat()) {
7605 // Use vbroadcast whenever the splat comes from a foldable load
7606 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7607 if (Broadcast.getNode())
7611 // Check integer expanding shuffles.
7612 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7613 if (NewOp.getNode())
7616 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7618 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
7620 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7621 if (NewOp.getNode())
7622 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7623 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
7624 // FIXME: Figure out a cleaner way to do this.
7625 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7626 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7627 if (NewOp.getNode()) {
7628 MVT NewVT = NewOp.getSimpleValueType();
7629 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7630 NewVT, true, false))
7631 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
7634 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7635 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7636 if (NewOp.getNode()) {
7637 MVT NewVT = NewOp.getSimpleValueType();
7638 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7639 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
7648 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7649 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7650 SDValue V1 = Op.getOperand(0);
7651 SDValue V2 = Op.getOperand(1);
7652 MVT VT = Op.getSimpleValueType();
7654 unsigned NumElems = VT.getVectorNumElements();
7655 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7656 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7657 bool V1IsSplat = false;
7658 bool V2IsSplat = false;
7659 bool HasSSE2 = Subtarget->hasSSE2();
7660 bool HasFp256 = Subtarget->hasFp256();
7661 bool HasInt256 = Subtarget->hasInt256();
7662 MachineFunction &MF = DAG.getMachineFunction();
7663 bool OptForSize = MF.getFunction()->getAttributes().
7664 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7666 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7668 if (V1IsUndef && V2IsUndef)
7669 return DAG.getUNDEF(VT);
7671 // When we create a shuffle node we put the UNDEF node to second operand,
7672 // but in some cases the first operand may be transformed to UNDEF.
7673 // In this case we should just commute the node.
7675 return CommuteVectorShuffle(SVOp, DAG);
7677 // Vector shuffle lowering takes 3 steps:
7679 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7680 // narrowing and commutation of operands should be handled.
7681 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7683 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7684 // so the shuffle can be broken into other shuffles and the legalizer can
7685 // try the lowering again.
7687 // The general idea is that no vector_shuffle operation should be left to
7688 // be matched during isel, all of them must be converted to a target specific
7691 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7692 // narrowing and commutation of operands should be handled. The actual code
7693 // doesn't include all of those, work in progress...
7694 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7695 if (NewOp.getNode())
7698 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7700 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7701 // unpckh_undef). Only use pshufd if speed is more important than size.
7702 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7703 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7704 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7705 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7707 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7708 V2IsUndef && MayFoldVectorLoad(V1))
7709 return getMOVDDup(Op, dl, V1, DAG);
7711 if (isMOVHLPS_v_undef_Mask(M, VT))
7712 return getMOVHighToLow(Op, dl, DAG);
7714 // Use to match splats
7715 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7716 (VT == MVT::v2f64 || VT == MVT::v2i64))
7717 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7719 if (isPSHUFDMask(M, VT)) {
7720 // The actual implementation will match the mask in the if above and then
7721 // during isel it can match several different instructions, not only pshufd
7722 // as its name says, sad but true, emulate the behavior for now...
7723 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7724 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7726 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7728 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7729 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7731 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7732 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7735 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7739 if (isPALIGNRMask(M, VT, Subtarget))
7740 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7741 getShufflePALIGNRImmediate(SVOp),
7744 // Check if this can be converted into a logical shift.
7745 bool isLeft = false;
7748 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7749 if (isShift && ShVal.hasOneUse()) {
7750 // If the shifted value has multiple uses, it may be cheaper to use
7751 // v_set0 + movlhps or movhlps, etc.
7752 MVT EltVT = VT.getVectorElementType();
7753 ShAmt *= EltVT.getSizeInBits();
7754 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7757 if (isMOVLMask(M, VT)) {
7758 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7759 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7760 if (!isMOVLPMask(M, VT)) {
7761 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7762 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7764 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7765 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7769 // FIXME: fold these into legal mask.
7770 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7771 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7773 if (isMOVHLPSMask(M, VT))
7774 return getMOVHighToLow(Op, dl, DAG);
7776 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7777 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7779 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7780 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7782 if (isMOVLPMask(M, VT))
7783 return getMOVLP(Op, dl, DAG, HasSSE2);
7785 if (ShouldXformToMOVHLPS(M, VT) ||
7786 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7787 return CommuteVectorShuffle(SVOp, DAG);
7790 // No better options. Use a vshldq / vsrldq.
7791 MVT EltVT = VT.getVectorElementType();
7792 ShAmt *= EltVT.getSizeInBits();
7793 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7796 bool Commuted = false;
7797 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7798 // 1,1,1,1 -> v8i16 though.
7799 V1IsSplat = isSplatVector(V1.getNode());
7800 V2IsSplat = isSplatVector(V2.getNode());
7802 // Canonicalize the splat or undef, if present, to be on the RHS.
7803 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7804 CommuteVectorShuffleMask(M, NumElems);
7806 std::swap(V1IsSplat, V2IsSplat);
7810 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7811 // Shuffling low element of v1 into undef, just return v1.
7814 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7815 // the instruction selector will not match, so get a canonical MOVL with
7816 // swapped operands to undo the commute.
7817 return getMOVL(DAG, dl, VT, V2, V1);
7820 if (isUNPCKLMask(M, VT, HasInt256))
7821 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7823 if (isUNPCKHMask(M, VT, HasInt256))
7824 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7827 // Normalize mask so all entries that point to V2 points to its first
7828 // element then try to match unpck{h|l} again. If match, return a
7829 // new vector_shuffle with the corrected mask.p
7830 SmallVector<int, 8> NewMask(M.begin(), M.end());
7831 NormalizeMask(NewMask, NumElems);
7832 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7833 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7834 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7835 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7839 // Commute is back and try unpck* again.
7840 // FIXME: this seems wrong.
7841 CommuteVectorShuffleMask(M, NumElems);
7843 std::swap(V1IsSplat, V2IsSplat);
7845 if (isUNPCKLMask(M, VT, HasInt256))
7846 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7848 if (isUNPCKHMask(M, VT, HasInt256))
7849 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7852 // Normalize the node to match x86 shuffle ops if needed
7853 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7854 return CommuteVectorShuffle(SVOp, DAG);
7856 // The checks below are all present in isShuffleMaskLegal, but they are
7857 // inlined here right now to enable us to directly emit target specific
7858 // nodes, and remove one by one until they don't return Op anymore.
7860 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7861 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7862 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7863 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7866 if (isPSHUFHWMask(M, VT, HasInt256))
7867 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7868 getShufflePSHUFHWImmediate(SVOp),
7871 if (isPSHUFLWMask(M, VT, HasInt256))
7872 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7873 getShufflePSHUFLWImmediate(SVOp),
7876 if (isSHUFPMask(M, VT))
7877 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7878 getShuffleSHUFImmediate(SVOp), DAG);
7880 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7881 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7882 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7883 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7885 //===--------------------------------------------------------------------===//
7886 // Generate target specific nodes for 128 or 256-bit shuffles only
7887 // supported in the AVX instruction set.
7890 // Handle VMOVDDUPY permutations
7891 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7892 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7894 // Handle VPERMILPS/D* permutations
7895 if (isVPERMILPMask(M, VT)) {
7896 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7897 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7898 getShuffleSHUFImmediate(SVOp), DAG);
7899 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7900 getShuffleSHUFImmediate(SVOp), DAG);
7904 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
7905 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
7906 Idx*(NumElems/2), DAG, dl);
7908 // Handle VPERM2F128/VPERM2I128 permutations
7909 if (isVPERM2X128Mask(M, VT, HasFp256))
7910 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7911 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7913 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7914 if (BlendOp.getNode())
7917 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
7918 return getINSERTPS(SVOp, dl, DAG);
7921 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7922 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7924 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7925 VT.is512BitVector()) {
7926 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7927 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7928 SmallVector<SDValue, 16> permclMask;
7929 for (unsigned i = 0; i != NumElems; ++i) {
7930 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7933 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
7935 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7936 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7937 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7938 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
7939 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
7942 //===--------------------------------------------------------------------===//
7943 // Since no target specific shuffle was selected for this generic one,
7944 // lower it into other known shuffles. FIXME: this isn't true yet, but
7945 // this is the plan.
7948 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7949 if (VT == MVT::v8i16) {
7950 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7951 if (NewOp.getNode())
7955 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
7956 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
7957 if (NewOp.getNode())
7961 if (VT == MVT::v16i8) {
7962 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7963 if (NewOp.getNode())
7967 if (VT == MVT::v32i8) {
7968 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7969 if (NewOp.getNode())
7973 // Handle all 128-bit wide vectors with 4 elements, and match them with
7974 // several different shuffle types.
7975 if (NumElems == 4 && VT.is128BitVector())
7976 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7978 // Handle general 256-bit shuffles
7979 if (VT.is256BitVector())
7980 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7985 // This function assumes its argument is a BUILD_VECTOR of constants or
7986 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
7988 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
7989 unsigned &MaskValue) {
7991 unsigned NumElems = BuildVector->getNumOperands();
7992 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
7993 unsigned NumLanes = (NumElems - 1) / 8 + 1;
7994 unsigned NumElemsInLane = NumElems / NumLanes;
7996 // Blend for v16i16 should be symetric for the both lanes.
7997 for (unsigned i = 0; i < NumElemsInLane; ++i) {
7998 SDValue EltCond = BuildVector->getOperand(i);
7999 SDValue SndLaneEltCond =
8000 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
8002 int Lane1Cond = -1, Lane2Cond = -1;
8003 if (isa<ConstantSDNode>(EltCond))
8004 Lane1Cond = !isZero(EltCond);
8005 if (isa<ConstantSDNode>(SndLaneEltCond))
8006 Lane2Cond = !isZero(SndLaneEltCond);
8008 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
8009 // Lane1Cond != 0, means we want the first argument.
8010 // Lane1Cond == 0, means we want the second argument.
8011 // The encoding of this argument is 0 for the first argument, 1
8012 // for the second. Therefore, invert the condition.
8013 MaskValue |= !Lane1Cond << i;
8014 else if (Lane1Cond < 0)
8015 MaskValue |= !Lane2Cond << i;
8022 // Try to lower a vselect node into a simple blend instruction.
8023 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
8024 SelectionDAG &DAG) {
8025 SDValue Cond = Op.getOperand(0);
8026 SDValue LHS = Op.getOperand(1);
8027 SDValue RHS = Op.getOperand(2);
8029 MVT VT = Op.getSimpleValueType();
8030 MVT EltVT = VT.getVectorElementType();
8031 unsigned NumElems = VT.getVectorNumElements();
8033 // There is no blend with immediate in AVX-512.
8034 if (VT.is512BitVector())
8037 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
8039 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
8042 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
8045 // Check the mask for BLEND and build the value.
8046 unsigned MaskValue = 0;
8047 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
8050 // Convert i32 vectors to floating point if it is not AVX2.
8051 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8053 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8054 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8056 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
8057 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
8060 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
8061 DAG.getConstant(MaskValue, MVT::i32));
8062 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8065 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
8066 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
8067 if (BlendOp.getNode())
8070 // Some types for vselect were previously set to Expand, not Legal or
8071 // Custom. Return an empty SDValue so we fall-through to Expand, after
8072 // the Custom lowering phase.
8073 MVT VT = Op.getSimpleValueType();
8074 switch (VT.SimpleTy) {
8082 // We couldn't create a "Blend with immediate" node.
8083 // This node should still be legal, but we'll have to emit a blendv*
8088 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
8089 MVT VT = Op.getSimpleValueType();
8092 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
8095 if (VT.getSizeInBits() == 8) {
8096 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
8097 Op.getOperand(0), Op.getOperand(1));
8098 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
8099 DAG.getValueType(VT));
8100 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
8103 if (VT.getSizeInBits() == 16) {
8104 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8105 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
8107 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
8108 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
8109 DAG.getNode(ISD::BITCAST, dl,
8113 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
8114 Op.getOperand(0), Op.getOperand(1));
8115 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
8116 DAG.getValueType(VT));
8117 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
8120 if (VT == MVT::f32) {
8121 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
8122 // the result back to FR32 register. It's only worth matching if the
8123 // result has a single use which is a store or a bitcast to i32. And in
8124 // the case of a store, it's not worth it if the index is a constant 0,
8125 // because a MOVSSmr can be used instead, which is smaller and faster.
8126 if (!Op.hasOneUse())
8128 SDNode *User = *Op.getNode()->use_begin();
8129 if ((User->getOpcode() != ISD::STORE ||
8130 (isa<ConstantSDNode>(Op.getOperand(1)) &&
8131 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
8132 (User->getOpcode() != ISD::BITCAST ||
8133 User->getValueType(0) != MVT::i32))
8135 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
8136 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
8139 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
8142 if (VT == MVT::i32 || VT == MVT::i64) {
8143 // ExtractPS/pextrq works with constant index.
8144 if (isa<ConstantSDNode>(Op.getOperand(1)))
8150 /// Extract one bit from mask vector, like v16i1 or v8i1.
8151 /// AVX-512 feature.
8153 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
8154 SDValue Vec = Op.getOperand(0);
8156 MVT VecVT = Vec.getSimpleValueType();
8157 SDValue Idx = Op.getOperand(1);
8158 MVT EltVT = Op.getSimpleValueType();
8160 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
8162 // variable index can't be handled in mask registers,
8163 // extend vector to VR512
8164 if (!isa<ConstantSDNode>(Idx)) {
8165 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
8166 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
8167 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
8168 ExtVT.getVectorElementType(), Ext, Idx);
8169 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
8172 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8173 const TargetRegisterClass* rc = getRegClassFor(VecVT);
8174 unsigned MaxSift = rc->getSize()*8 - 1;
8175 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
8176 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
8177 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
8178 DAG.getConstant(MaxSift, MVT::i8));
8179 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
8180 DAG.getIntPtrConstant(0));
8184 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
8185 SelectionDAG &DAG) const {
8187 SDValue Vec = Op.getOperand(0);
8188 MVT VecVT = Vec.getSimpleValueType();
8189 SDValue Idx = Op.getOperand(1);
8191 if (Op.getSimpleValueType() == MVT::i1)
8192 return ExtractBitFromMaskVector(Op, DAG);
8194 if (!isa<ConstantSDNode>(Idx)) {
8195 if (VecVT.is512BitVector() ||
8196 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
8197 VecVT.getVectorElementType().getSizeInBits() == 32)) {
8200 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
8201 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
8202 MaskEltVT.getSizeInBits());
8204 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
8205 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
8206 getZeroVector(MaskVT, Subtarget, DAG, dl),
8207 Idx, DAG.getConstant(0, getPointerTy()));
8208 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
8209 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
8210 Perm, DAG.getConstant(0, getPointerTy()));
8215 // If this is a 256-bit vector result, first extract the 128-bit vector and
8216 // then extract the element from the 128-bit vector.
8217 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
8219 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8220 // Get the 128-bit vector.
8221 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
8222 MVT EltVT = VecVT.getVectorElementType();
8224 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
8226 //if (IdxVal >= NumElems/2)
8227 // IdxVal -= NumElems/2;
8228 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
8229 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
8230 DAG.getConstant(IdxVal, MVT::i32));
8233 assert(VecVT.is128BitVector() && "Unexpected vector length");
8235 if (Subtarget->hasSSE41()) {
8236 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
8241 MVT VT = Op.getSimpleValueType();
8242 // TODO: handle v16i8.
8243 if (VT.getSizeInBits() == 16) {
8244 SDValue Vec = Op.getOperand(0);
8245 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8247 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
8248 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
8249 DAG.getNode(ISD::BITCAST, dl,
8252 // Transform it so it match pextrw which produces a 32-bit result.
8253 MVT EltVT = MVT::i32;
8254 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
8255 Op.getOperand(0), Op.getOperand(1));
8256 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
8257 DAG.getValueType(VT));
8258 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
8261 if (VT.getSizeInBits() == 32) {
8262 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8266 // SHUFPS the element to the lowest double word, then movss.
8267 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
8268 MVT VVT = Op.getOperand(0).getSimpleValueType();
8269 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
8270 DAG.getUNDEF(VVT), Mask);
8271 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
8272 DAG.getIntPtrConstant(0));
8275 if (VT.getSizeInBits() == 64) {
8276 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
8277 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
8278 // to match extract_elt for f64.
8279 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8283 // UNPCKHPD the element to the lowest double word, then movsd.
8284 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
8285 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
8286 int Mask[2] = { 1, -1 };
8287 MVT VVT = Op.getOperand(0).getSimpleValueType();
8288 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
8289 DAG.getUNDEF(VVT), Mask);
8290 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
8291 DAG.getIntPtrConstant(0));
8297 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
8298 MVT VT = Op.getSimpleValueType();
8299 MVT EltVT = VT.getVectorElementType();
8302 SDValue N0 = Op.getOperand(0);
8303 SDValue N1 = Op.getOperand(1);
8304 SDValue N2 = Op.getOperand(2);
8306 if (!VT.is128BitVector())
8309 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
8310 isa<ConstantSDNode>(N2)) {
8312 if (VT == MVT::v8i16)
8313 Opc = X86ISD::PINSRW;
8314 else if (VT == MVT::v16i8)
8315 Opc = X86ISD::PINSRB;
8317 Opc = X86ISD::PINSRB;
8319 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
8321 if (N1.getValueType() != MVT::i32)
8322 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
8323 if (N2.getValueType() != MVT::i32)
8324 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
8325 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
8328 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
8329 // Bits [7:6] of the constant are the source select. This will always be
8330 // zero here. The DAG Combiner may combine an extract_elt index into these
8331 // bits. For example (insert (extract, 3), 2) could be matched by putting
8332 // the '3' into bits [7:6] of X86ISD::INSERTPS.
8333 // Bits [5:4] of the constant are the destination select. This is the
8334 // value of the incoming immediate.
8335 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
8336 // combine either bitwise AND or insert of float 0.0 to set these bits.
8337 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
8338 // Create this as a scalar to vector..
8339 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
8340 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
8343 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
8344 // PINSR* works with constant index.
8350 /// Insert one bit to mask vector, like v16i1 or v8i1.
8351 /// AVX-512 feature.
8353 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
8355 SDValue Vec = Op.getOperand(0);
8356 SDValue Elt = Op.getOperand(1);
8357 SDValue Idx = Op.getOperand(2);
8358 MVT VecVT = Vec.getSimpleValueType();
8360 if (!isa<ConstantSDNode>(Idx)) {
8361 // Non constant index. Extend source and destination,
8362 // insert element and then truncate the result.
8363 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
8364 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
8365 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
8366 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
8367 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
8368 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
8371 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8372 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
8373 if (Vec.getOpcode() == ISD::UNDEF)
8374 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
8375 DAG.getConstant(IdxVal, MVT::i8));
8376 const TargetRegisterClass* rc = getRegClassFor(VecVT);
8377 unsigned MaxSift = rc->getSize()*8 - 1;
8378 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
8379 DAG.getConstant(MaxSift, MVT::i8));
8380 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
8381 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
8382 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
8385 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
8386 MVT VT = Op.getSimpleValueType();
8387 MVT EltVT = VT.getVectorElementType();
8389 if (EltVT == MVT::i1)
8390 return InsertBitToMaskVector(Op, DAG);
8393 SDValue N0 = Op.getOperand(0);
8394 SDValue N1 = Op.getOperand(1);
8395 SDValue N2 = Op.getOperand(2);
8397 // If this is a 256-bit vector result, first extract the 128-bit vector,
8398 // insert the element into the extracted half and then place it back.
8399 if (VT.is256BitVector() || VT.is512BitVector()) {
8400 if (!isa<ConstantSDNode>(N2))
8403 // Get the desired 128-bit vector half.
8404 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
8405 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
8407 // Insert the element into the desired half.
8408 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
8409 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
8411 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
8412 DAG.getConstant(IdxIn128, MVT::i32));
8414 // Insert the changed part back to the 256-bit vector
8415 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
8418 if (Subtarget->hasSSE41())
8419 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
8421 if (EltVT == MVT::i8)
8424 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
8425 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
8426 // as its second argument.
8427 if (N1.getValueType() != MVT::i32)
8428 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
8429 if (N2.getValueType() != MVT::i32)
8430 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
8431 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
8436 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
8438 MVT OpVT = Op.getSimpleValueType();
8440 // If this is a 256-bit vector result, first insert into a 128-bit
8441 // vector and then insert into the 256-bit vector.
8442 if (!OpVT.is128BitVector()) {
8443 // Insert into a 128-bit vector.
8444 unsigned SizeFactor = OpVT.getSizeInBits()/128;
8445 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
8446 OpVT.getVectorNumElements() / SizeFactor);
8448 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
8450 // Insert the 128-bit vector.
8451 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
8454 if (OpVT == MVT::v1i64 &&
8455 Op.getOperand(0).getValueType() == MVT::i64)
8456 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
8458 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
8459 assert(OpVT.is128BitVector() && "Expected an SSE type!");
8460 return DAG.getNode(ISD::BITCAST, dl, OpVT,
8461 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
8464 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
8465 // a simple subregister reference or explicit instructions to grab
8466 // upper bits of a vector.
8467 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8468 SelectionDAG &DAG) {
8470 SDValue In = Op.getOperand(0);
8471 SDValue Idx = Op.getOperand(1);
8472 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8473 MVT ResVT = Op.getSimpleValueType();
8474 MVT InVT = In.getSimpleValueType();
8476 if (Subtarget->hasFp256()) {
8477 if (ResVT.is128BitVector() &&
8478 (InVT.is256BitVector() || InVT.is512BitVector()) &&
8479 isa<ConstantSDNode>(Idx)) {
8480 return Extract128BitVector(In, IdxVal, DAG, dl);
8482 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
8483 isa<ConstantSDNode>(Idx)) {
8484 return Extract256BitVector(In, IdxVal, DAG, dl);
8490 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
8491 // simple superregister reference or explicit instructions to insert
8492 // the upper bits of a vector.
8493 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8494 SelectionDAG &DAG) {
8495 if (Subtarget->hasFp256()) {
8496 SDLoc dl(Op.getNode());
8497 SDValue Vec = Op.getNode()->getOperand(0);
8498 SDValue SubVec = Op.getNode()->getOperand(1);
8499 SDValue Idx = Op.getNode()->getOperand(2);
8501 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
8502 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
8503 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
8504 isa<ConstantSDNode>(Idx)) {
8505 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8506 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
8509 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
8510 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
8511 isa<ConstantSDNode>(Idx)) {
8512 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8513 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
8519 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
8520 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
8521 // one of the above mentioned nodes. It has to be wrapped because otherwise
8522 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
8523 // be used to form addressing mode. These wrapped nodes will be selected
8526 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
8527 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
8529 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8531 unsigned char OpFlag = 0;
8532 unsigned WrapperKind = X86ISD::Wrapper;
8533 CodeModel::Model M = getTargetMachine().getCodeModel();
8535 if (Subtarget->isPICStyleRIPRel() &&
8536 (M == CodeModel::Small || M == CodeModel::Kernel))
8537 WrapperKind = X86ISD::WrapperRIP;
8538 else if (Subtarget->isPICStyleGOT())
8539 OpFlag = X86II::MO_GOTOFF;
8540 else if (Subtarget->isPICStyleStubPIC())
8541 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8543 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
8545 CP->getOffset(), OpFlag);
8547 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8548 // With PIC, the address is actually $g + Offset.
8550 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8551 DAG.getNode(X86ISD::GlobalBaseReg,
8552 SDLoc(), getPointerTy()),
8559 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
8560 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
8562 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8564 unsigned char OpFlag = 0;
8565 unsigned WrapperKind = X86ISD::Wrapper;
8566 CodeModel::Model M = getTargetMachine().getCodeModel();
8568 if (Subtarget->isPICStyleRIPRel() &&
8569 (M == CodeModel::Small || M == CodeModel::Kernel))
8570 WrapperKind = X86ISD::WrapperRIP;
8571 else if (Subtarget->isPICStyleGOT())
8572 OpFlag = X86II::MO_GOTOFF;
8573 else if (Subtarget->isPICStyleStubPIC())
8574 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8576 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8579 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8581 // With PIC, the address is actually $g + Offset.
8583 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8584 DAG.getNode(X86ISD::GlobalBaseReg,
8585 SDLoc(), getPointerTy()),
8592 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8593 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8595 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8597 unsigned char OpFlag = 0;
8598 unsigned WrapperKind = X86ISD::Wrapper;
8599 CodeModel::Model M = getTargetMachine().getCodeModel();
8601 if (Subtarget->isPICStyleRIPRel() &&
8602 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8603 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8604 OpFlag = X86II::MO_GOTPCREL;
8605 WrapperKind = X86ISD::WrapperRIP;
8606 } else if (Subtarget->isPICStyleGOT()) {
8607 OpFlag = X86II::MO_GOT;
8608 } else if (Subtarget->isPICStyleStubPIC()) {
8609 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8610 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8611 OpFlag = X86II::MO_DARWIN_NONLAZY;
8614 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8617 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8619 // With PIC, the address is actually $g + Offset.
8620 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8621 !Subtarget->is64Bit()) {
8622 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8623 DAG.getNode(X86ISD::GlobalBaseReg,
8624 SDLoc(), getPointerTy()),
8628 // For symbols that require a load from a stub to get the address, emit the
8630 if (isGlobalStubReference(OpFlag))
8631 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8632 MachinePointerInfo::getGOT(), false, false, false, 0);
8638 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8639 // Create the TargetBlockAddressAddress node.
8640 unsigned char OpFlags =
8641 Subtarget->ClassifyBlockAddressReference();
8642 CodeModel::Model M = getTargetMachine().getCodeModel();
8643 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8644 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8646 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8649 if (Subtarget->isPICStyleRIPRel() &&
8650 (M == CodeModel::Small || M == CodeModel::Kernel))
8651 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8653 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8655 // With PIC, the address is actually $g + Offset.
8656 if (isGlobalRelativeToPICBase(OpFlags)) {
8657 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8658 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8666 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8667 int64_t Offset, SelectionDAG &DAG) const {
8668 // Create the TargetGlobalAddress node, folding in the constant
8669 // offset if it is legal.
8670 unsigned char OpFlags =
8671 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8672 CodeModel::Model M = getTargetMachine().getCodeModel();
8674 if (OpFlags == X86II::MO_NO_FLAG &&
8675 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8676 // A direct static reference to a global.
8677 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8680 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8683 if (Subtarget->isPICStyleRIPRel() &&
8684 (M == CodeModel::Small || M == CodeModel::Kernel))
8685 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8687 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8689 // With PIC, the address is actually $g + Offset.
8690 if (isGlobalRelativeToPICBase(OpFlags)) {
8691 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8692 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8696 // For globals that require a load from a stub to get the address, emit the
8698 if (isGlobalStubReference(OpFlags))
8699 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8700 MachinePointerInfo::getGOT(), false, false, false, 0);
8702 // If there was a non-zero offset that we didn't fold, create an explicit
8705 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8706 DAG.getConstant(Offset, getPointerTy()));
8712 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8713 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8714 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8715 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8719 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8720 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8721 unsigned char OperandFlags, bool LocalDynamic = false) {
8722 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8723 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8725 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8726 GA->getValueType(0),
8730 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8734 SDValue Ops[] = { Chain, TGA, *InFlag };
8735 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
8737 SDValue Ops[] = { Chain, TGA };
8738 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
8741 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8742 MFI->setAdjustsStack(true);
8744 SDValue Flag = Chain.getValue(1);
8745 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8748 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8750 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8753 SDLoc dl(GA); // ? function entry point might be better
8754 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8755 DAG.getNode(X86ISD::GlobalBaseReg,
8756 SDLoc(), PtrVT), InFlag);
8757 InFlag = Chain.getValue(1);
8759 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8762 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8764 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8766 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
8767 X86::RAX, X86II::MO_TLSGD);
8770 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8776 // Get the start address of the TLS block for this module.
8777 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8778 .getInfo<X86MachineFunctionInfo>();
8779 MFI->incNumLocalDynamicTLSAccesses();
8783 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
8784 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8787 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8788 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8789 InFlag = Chain.getValue(1);
8790 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8791 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8794 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8798 unsigned char OperandFlags = X86II::MO_DTPOFF;
8799 unsigned WrapperKind = X86ISD::Wrapper;
8800 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8801 GA->getValueType(0),
8802 GA->getOffset(), OperandFlags);
8803 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8805 // Add x@dtpoff with the base.
8806 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8809 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8810 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8811 const EVT PtrVT, TLSModel::Model model,
8812 bool is64Bit, bool isPIC) {
8815 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8816 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8817 is64Bit ? 257 : 256));
8819 SDValue ThreadPointer =
8820 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8821 MachinePointerInfo(Ptr), false, false, false, 0);
8823 unsigned char OperandFlags = 0;
8824 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8826 unsigned WrapperKind = X86ISD::Wrapper;
8827 if (model == TLSModel::LocalExec) {
8828 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8829 } else if (model == TLSModel::InitialExec) {
8831 OperandFlags = X86II::MO_GOTTPOFF;
8832 WrapperKind = X86ISD::WrapperRIP;
8834 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8837 llvm_unreachable("Unexpected model");
8840 // emit "addl x@ntpoff,%eax" (local exec)
8841 // or "addl x@indntpoff,%eax" (initial exec)
8842 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8844 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8845 GA->getOffset(), OperandFlags);
8846 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8848 if (model == TLSModel::InitialExec) {
8849 if (isPIC && !is64Bit) {
8850 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8851 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8855 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8856 MachinePointerInfo::getGOT(), false, false, false, 0);
8859 // The address of the thread local variable is the add of the thread
8860 // pointer with the offset of the variable.
8861 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8865 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8867 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8868 const GlobalValue *GV = GA->getGlobal();
8870 if (Subtarget->isTargetELF()) {
8871 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8874 case TLSModel::GeneralDynamic:
8875 if (Subtarget->is64Bit())
8876 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8877 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8878 case TLSModel::LocalDynamic:
8879 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8880 Subtarget->is64Bit());
8881 case TLSModel::InitialExec:
8882 case TLSModel::LocalExec:
8883 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8884 Subtarget->is64Bit(),
8885 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8887 llvm_unreachable("Unknown TLS model.");
8890 if (Subtarget->isTargetDarwin()) {
8891 // Darwin only has one model of TLS. Lower to that.
8892 unsigned char OpFlag = 0;
8893 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8894 X86ISD::WrapperRIP : X86ISD::Wrapper;
8896 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8898 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8899 !Subtarget->is64Bit();
8901 OpFlag = X86II::MO_TLVP_PIC_BASE;
8903 OpFlag = X86II::MO_TLVP;
8905 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8906 GA->getValueType(0),
8907 GA->getOffset(), OpFlag);
8908 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8910 // With PIC32, the address is actually $g + Offset.
8912 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8913 DAG.getNode(X86ISD::GlobalBaseReg,
8914 SDLoc(), getPointerTy()),
8917 // Lowering the machine isd will make sure everything is in the right
8919 SDValue Chain = DAG.getEntryNode();
8920 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8921 SDValue Args[] = { Chain, Offset };
8922 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
8924 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8925 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8926 MFI->setAdjustsStack(true);
8928 // And our return value (tls address) is in the standard call return value
8930 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8931 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8935 if (Subtarget->isTargetKnownWindowsMSVC() ||
8936 Subtarget->isTargetWindowsGNU()) {
8937 // Just use the implicit TLS architecture
8938 // Need to generate someting similar to:
8939 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8941 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8942 // mov rcx, qword [rdx+rcx*8]
8943 // mov eax, .tls$:tlsvar
8944 // [rax+rcx] contains the address
8945 // Windows 64bit: gs:0x58
8946 // Windows 32bit: fs:__tls_array
8949 SDValue Chain = DAG.getEntryNode();
8951 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8952 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8953 // use its literal value of 0x2C.
8954 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8955 ? Type::getInt8PtrTy(*DAG.getContext(),
8957 : Type::getInt32PtrTy(*DAG.getContext(),
8961 Subtarget->is64Bit()
8962 ? DAG.getIntPtrConstant(0x58)
8963 : (Subtarget->isTargetWindowsGNU()
8964 ? DAG.getIntPtrConstant(0x2C)
8965 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
8967 SDValue ThreadPointer =
8968 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8969 MachinePointerInfo(Ptr), false, false, false, 0);
8971 // Load the _tls_index variable
8972 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8973 if (Subtarget->is64Bit())
8974 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8975 IDX, MachinePointerInfo(), MVT::i32,
8978 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8979 false, false, false, 0);
8981 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8983 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8985 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8986 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8987 false, false, false, 0);
8989 // Get the offset of start of .tls section
8990 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8991 GA->getValueType(0),
8992 GA->getOffset(), X86II::MO_SECREL);
8993 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8995 // The address of the thread local variable is the add of the thread
8996 // pointer with the offset of the variable.
8997 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
9000 llvm_unreachable("TLS not implemented for this target.");
9003 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
9004 /// and take a 2 x i32 value to shift plus a shift amount.
9005 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
9006 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
9007 MVT VT = Op.getSimpleValueType();
9008 unsigned VTBits = VT.getSizeInBits();
9010 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
9011 SDValue ShOpLo = Op.getOperand(0);
9012 SDValue ShOpHi = Op.getOperand(1);
9013 SDValue ShAmt = Op.getOperand(2);
9014 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
9015 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
9017 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
9018 DAG.getConstant(VTBits - 1, MVT::i8));
9019 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
9020 DAG.getConstant(VTBits - 1, MVT::i8))
9021 : DAG.getConstant(0, VT);
9024 if (Op.getOpcode() == ISD::SHL_PARTS) {
9025 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
9026 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
9028 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
9029 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
9032 // If the shift amount is larger or equal than the width of a part we can't
9033 // rely on the results of shld/shrd. Insert a test and select the appropriate
9034 // values for large shift amounts.
9035 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
9036 DAG.getConstant(VTBits, MVT::i8));
9037 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9038 AndNode, DAG.getConstant(0, MVT::i8));
9041 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9042 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
9043 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
9045 if (Op.getOpcode() == ISD::SHL_PARTS) {
9046 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
9047 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
9049 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
9050 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
9053 SDValue Ops[2] = { Lo, Hi };
9054 return DAG.getMergeValues(Ops, dl);
9057 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
9058 SelectionDAG &DAG) const {
9059 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
9061 if (SrcVT.isVector())
9064 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
9065 "Unknown SINT_TO_FP to lower!");
9067 // These are really Legal; return the operand so the caller accepts it as
9069 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
9071 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
9072 Subtarget->is64Bit()) {
9077 unsigned Size = SrcVT.getSizeInBits()/8;
9078 MachineFunction &MF = DAG.getMachineFunction();
9079 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
9080 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9081 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
9083 MachinePointerInfo::getFixedStack(SSFI),
9085 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
9088 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
9090 SelectionDAG &DAG) const {
9094 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
9096 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
9098 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
9100 unsigned ByteSize = SrcVT.getSizeInBits()/8;
9102 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
9103 MachineMemOperand *MMO;
9105 int SSFI = FI->getIndex();
9107 DAG.getMachineFunction()
9108 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9109 MachineMemOperand::MOLoad, ByteSize, ByteSize);
9111 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
9112 StackSlot = StackSlot.getOperand(1);
9114 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
9115 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
9117 Tys, Ops, SrcVT, MMO);
9120 Chain = Result.getValue(1);
9121 SDValue InFlag = Result.getValue(2);
9123 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
9124 // shouldn't be necessary except that RFP cannot be live across
9125 // multiple blocks. When stackifier is fixed, they can be uncoupled.
9126 MachineFunction &MF = DAG.getMachineFunction();
9127 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
9128 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
9129 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9130 Tys = DAG.getVTList(MVT::Other);
9132 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
9134 MachineMemOperand *MMO =
9135 DAG.getMachineFunction()
9136 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9137 MachineMemOperand::MOStore, SSFISize, SSFISize);
9139 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
9140 Ops, Op.getValueType(), MMO);
9141 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
9142 MachinePointerInfo::getFixedStack(SSFI),
9143 false, false, false, 0);
9149 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
9150 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
9151 SelectionDAG &DAG) const {
9152 // This algorithm is not obvious. Here it is what we're trying to output:
9155 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
9156 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
9160 pshufd $0x4e, %xmm0, %xmm1
9166 LLVMContext *Context = DAG.getContext();
9168 // Build some magic constants.
9169 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
9170 Constant *C0 = ConstantDataVector::get(*Context, CV0);
9171 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
9173 SmallVector<Constant*,2> CV1;
9175 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9176 APInt(64, 0x4330000000000000ULL))));
9178 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9179 APInt(64, 0x4530000000000000ULL))));
9180 Constant *C1 = ConstantVector::get(CV1);
9181 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
9183 // Load the 64-bit value into an XMM register.
9184 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
9186 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
9187 MachinePointerInfo::getConstantPool(),
9188 false, false, false, 16);
9189 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
9190 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
9193 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
9194 MachinePointerInfo::getConstantPool(),
9195 false, false, false, 16);
9196 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
9197 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
9200 if (Subtarget->hasSSE3()) {
9201 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
9202 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
9204 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
9205 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
9207 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
9208 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
9212 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
9213 DAG.getIntPtrConstant(0));
9216 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
9217 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
9218 SelectionDAG &DAG) const {
9220 // FP constant to bias correct the final result.
9221 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
9224 // Load the 32-bit value into an XMM register.
9225 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
9228 // Zero out the upper parts of the register.
9229 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
9231 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
9232 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
9233 DAG.getIntPtrConstant(0));
9235 // Or the load with the bias.
9236 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
9237 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
9238 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
9240 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
9241 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
9242 MVT::v2f64, Bias)));
9243 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
9244 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
9245 DAG.getIntPtrConstant(0));
9247 // Subtract the bias.
9248 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
9250 // Handle final rounding.
9251 EVT DestVT = Op.getValueType();
9253 if (DestVT.bitsLT(MVT::f64))
9254 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
9255 DAG.getIntPtrConstant(0));
9256 if (DestVT.bitsGT(MVT::f64))
9257 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
9259 // Handle final rounding.
9263 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
9264 SelectionDAG &DAG) const {
9265 SDValue N0 = Op.getOperand(0);
9266 MVT SVT = N0.getSimpleValueType();
9269 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
9270 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
9271 "Custom UINT_TO_FP is not supported!");
9273 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
9274 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
9275 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
9278 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
9279 SelectionDAG &DAG) const {
9280 SDValue N0 = Op.getOperand(0);
9283 if (Op.getValueType().isVector())
9284 return lowerUINT_TO_FP_vec(Op, DAG);
9286 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
9287 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
9288 // the optimization here.
9289 if (DAG.SignBitIsZero(N0))
9290 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
9292 MVT SrcVT = N0.getSimpleValueType();
9293 MVT DstVT = Op.getSimpleValueType();
9294 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
9295 return LowerUINT_TO_FP_i64(Op, DAG);
9296 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
9297 return LowerUINT_TO_FP_i32(Op, DAG);
9298 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
9301 // Make a 64-bit buffer, and use it to build an FILD.
9302 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
9303 if (SrcVT == MVT::i32) {
9304 SDValue WordOff = DAG.getConstant(4, getPointerTy());
9305 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
9306 getPointerTy(), StackSlot, WordOff);
9307 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
9308 StackSlot, MachinePointerInfo(),
9310 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
9311 OffsetSlot, MachinePointerInfo(),
9313 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
9317 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
9318 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
9319 StackSlot, MachinePointerInfo(),
9321 // For i64 source, we need to add the appropriate power of 2 if the input
9322 // was negative. This is the same as the optimization in
9323 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
9324 // we must be careful to do the computation in x87 extended precision, not
9325 // in SSE. (The generic code can't know it's OK to do this, or how to.)
9326 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
9327 MachineMemOperand *MMO =
9328 DAG.getMachineFunction()
9329 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9330 MachineMemOperand::MOLoad, 8, 8);
9332 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
9333 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
9334 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
9337 APInt FF(32, 0x5F800000ULL);
9339 // Check whether the sign bit is set.
9340 SDValue SignSet = DAG.getSetCC(dl,
9341 getSetCCResultType(*DAG.getContext(), MVT::i64),
9342 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
9345 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
9346 SDValue FudgePtr = DAG.getConstantPool(
9347 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
9350 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
9351 SDValue Zero = DAG.getIntPtrConstant(0);
9352 SDValue Four = DAG.getIntPtrConstant(4);
9353 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
9355 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
9357 // Load the value out, extending it from f32 to f80.
9358 // FIXME: Avoid the extend by constructing the right constant pool?
9359 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
9360 FudgePtr, MachinePointerInfo::getConstantPool(),
9361 MVT::f32, false, false, 4);
9362 // Extend everything to 80 bits to force it to be done on x87.
9363 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
9364 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
9367 std::pair<SDValue,SDValue>
9368 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
9369 bool IsSigned, bool IsReplace) const {
9372 EVT DstTy = Op.getValueType();
9374 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
9375 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
9379 assert(DstTy.getSimpleVT() <= MVT::i64 &&
9380 DstTy.getSimpleVT() >= MVT::i16 &&
9381 "Unknown FP_TO_INT to lower!");
9383 // These are really Legal.
9384 if (DstTy == MVT::i32 &&
9385 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
9386 return std::make_pair(SDValue(), SDValue());
9387 if (Subtarget->is64Bit() &&
9388 DstTy == MVT::i64 &&
9389 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
9390 return std::make_pair(SDValue(), SDValue());
9392 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
9393 // stack slot, or into the FTOL runtime function.
9394 MachineFunction &MF = DAG.getMachineFunction();
9395 unsigned MemSize = DstTy.getSizeInBits()/8;
9396 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
9397 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9400 if (!IsSigned && isIntegerTypeFTOL(DstTy))
9401 Opc = X86ISD::WIN_FTOL;
9403 switch (DstTy.getSimpleVT().SimpleTy) {
9404 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
9405 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
9406 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
9407 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
9410 SDValue Chain = DAG.getEntryNode();
9411 SDValue Value = Op.getOperand(0);
9412 EVT TheVT = Op.getOperand(0).getValueType();
9413 // FIXME This causes a redundant load/store if the SSE-class value is already
9414 // in memory, such as if it is on the callstack.
9415 if (isScalarFPTypeInSSEReg(TheVT)) {
9416 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
9417 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
9418 MachinePointerInfo::getFixedStack(SSFI),
9420 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
9422 Chain, StackSlot, DAG.getValueType(TheVT)
9425 MachineMemOperand *MMO =
9426 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9427 MachineMemOperand::MOLoad, MemSize, MemSize);
9428 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
9429 Chain = Value.getValue(1);
9430 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
9431 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9434 MachineMemOperand *MMO =
9435 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9436 MachineMemOperand::MOStore, MemSize, MemSize);
9438 if (Opc != X86ISD::WIN_FTOL) {
9439 // Build the FP_TO_INT*_IN_MEM
9440 SDValue Ops[] = { Chain, Value, StackSlot };
9441 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
9443 return std::make_pair(FIST, StackSlot);
9445 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
9446 DAG.getVTList(MVT::Other, MVT::Glue),
9448 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
9449 MVT::i32, ftol.getValue(1));
9450 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
9451 MVT::i32, eax.getValue(2));
9452 SDValue Ops[] = { eax, edx };
9453 SDValue pair = IsReplace
9454 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
9455 : DAG.getMergeValues(Ops, DL);
9456 return std::make_pair(pair, SDValue());
9460 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
9461 const X86Subtarget *Subtarget) {
9462 MVT VT = Op->getSimpleValueType(0);
9463 SDValue In = Op->getOperand(0);
9464 MVT InVT = In.getSimpleValueType();
9467 // Optimize vectors in AVX mode:
9470 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
9471 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
9472 // Concat upper and lower parts.
9475 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
9476 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
9477 // Concat upper and lower parts.
9480 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
9481 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
9482 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
9485 if (Subtarget->hasInt256())
9486 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
9488 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
9489 SDValue Undef = DAG.getUNDEF(InVT);
9490 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
9491 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9492 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9494 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
9495 VT.getVectorNumElements()/2);
9497 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
9498 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
9500 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9503 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
9504 SelectionDAG &DAG) {
9505 MVT VT = Op->getSimpleValueType(0);
9506 SDValue In = Op->getOperand(0);
9507 MVT InVT = In.getSimpleValueType();
9509 unsigned int NumElts = VT.getVectorNumElements();
9510 if (NumElts != 8 && NumElts != 16)
9513 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
9514 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
9516 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
9517 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9518 // Now we have only mask extension
9519 assert(InVT.getVectorElementType() == MVT::i1);
9520 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
9521 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9522 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
9523 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9524 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9525 MachinePointerInfo::getConstantPool(),
9526 false, false, false, Alignment);
9528 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
9529 if (VT.is512BitVector())
9531 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
9534 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9535 SelectionDAG &DAG) {
9536 if (Subtarget->hasFp256()) {
9537 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9545 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9546 SelectionDAG &DAG) {
9548 MVT VT = Op.getSimpleValueType();
9549 SDValue In = Op.getOperand(0);
9550 MVT SVT = In.getSimpleValueType();
9552 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
9553 return LowerZERO_EXTEND_AVX512(Op, DAG);
9555 if (Subtarget->hasFp256()) {
9556 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9561 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
9562 VT.getVectorNumElements() != SVT.getVectorNumElements());
9566 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
9568 MVT VT = Op.getSimpleValueType();
9569 SDValue In = Op.getOperand(0);
9570 MVT InVT = In.getSimpleValueType();
9572 if (VT == MVT::i1) {
9573 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
9574 "Invalid scalar TRUNCATE operation");
9575 if (InVT == MVT::i32)
9577 if (InVT.getSizeInBits() == 64)
9578 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
9579 else if (InVT.getSizeInBits() < 32)
9580 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
9581 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
9583 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
9584 "Invalid TRUNCATE operation");
9586 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
9587 if (VT.getVectorElementType().getSizeInBits() >=8)
9588 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9590 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9591 unsigned NumElts = InVT.getVectorNumElements();
9592 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9593 if (InVT.getSizeInBits() < 512) {
9594 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9595 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9599 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9600 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9601 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9602 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9603 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9604 MachinePointerInfo::getConstantPool(),
9605 false, false, false, Alignment);
9606 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9607 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9608 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9611 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9612 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9613 if (Subtarget->hasInt256()) {
9614 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9615 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9616 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9618 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9619 DAG.getIntPtrConstant(0));
9622 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9623 DAG.getIntPtrConstant(0));
9624 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9625 DAG.getIntPtrConstant(2));
9626 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9627 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9628 static const int ShufMask[] = {0, 2, 4, 6};
9629 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
9632 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9633 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9634 if (Subtarget->hasInt256()) {
9635 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9637 SmallVector<SDValue,32> pshufbMask;
9638 for (unsigned i = 0; i < 2; ++i) {
9639 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9640 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9641 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9642 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9643 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9644 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9645 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9646 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9647 for (unsigned j = 0; j < 8; ++j)
9648 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9650 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
9651 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9652 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9654 static const int ShufMask[] = {0, 2, -1, -1};
9655 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9657 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9658 DAG.getIntPtrConstant(0));
9659 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9662 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9663 DAG.getIntPtrConstant(0));
9665 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9666 DAG.getIntPtrConstant(4));
9668 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9669 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9672 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9673 -1, -1, -1, -1, -1, -1, -1, -1};
9675 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9676 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9677 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9679 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9680 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9682 // The MOVLHPS Mask:
9683 static const int ShufMask2[] = {0, 1, 4, 5};
9684 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9685 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9688 // Handle truncation of V256 to V128 using shuffles.
9689 if (!VT.is128BitVector() || !InVT.is256BitVector())
9692 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9694 unsigned NumElems = VT.getVectorNumElements();
9695 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
9697 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9698 // Prepare truncation shuffle mask
9699 for (unsigned i = 0; i != NumElems; ++i)
9701 SDValue V = DAG.getVectorShuffle(NVT, DL,
9702 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9703 DAG.getUNDEF(NVT), &MaskVec[0]);
9704 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9705 DAG.getIntPtrConstant(0));
9708 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9709 SelectionDAG &DAG) const {
9710 assert(!Op.getSimpleValueType().isVector());
9712 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9713 /*IsSigned=*/ true, /*IsReplace=*/ false);
9714 SDValue FIST = Vals.first, StackSlot = Vals.second;
9715 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9716 if (!FIST.getNode()) return Op;
9718 if (StackSlot.getNode())
9720 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9721 FIST, StackSlot, MachinePointerInfo(),
9722 false, false, false, 0);
9724 // The node is the result.
9728 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9729 SelectionDAG &DAG) const {
9730 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9731 /*IsSigned=*/ false, /*IsReplace=*/ false);
9732 SDValue FIST = Vals.first, StackSlot = Vals.second;
9733 assert(FIST.getNode() && "Unexpected failure");
9735 if (StackSlot.getNode())
9737 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9738 FIST, StackSlot, MachinePointerInfo(),
9739 false, false, false, 0);
9741 // The node is the result.
9745 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9747 MVT VT = Op.getSimpleValueType();
9748 SDValue In = Op.getOperand(0);
9749 MVT SVT = In.getSimpleValueType();
9751 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9753 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9754 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9755 In, DAG.getUNDEF(SVT)));
9758 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
9759 LLVMContext *Context = DAG.getContext();
9761 MVT VT = Op.getSimpleValueType();
9763 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9764 if (VT.isVector()) {
9765 EltVT = VT.getVectorElementType();
9766 NumElts = VT.getVectorNumElements();
9769 if (EltVT == MVT::f64)
9770 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9771 APInt(64, ~(1ULL << 63))));
9773 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9774 APInt(32, ~(1U << 31))));
9775 C = ConstantVector::getSplat(NumElts, C);
9776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9777 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9778 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9779 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9780 MachinePointerInfo::getConstantPool(),
9781 false, false, false, Alignment);
9782 if (VT.isVector()) {
9783 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9784 return DAG.getNode(ISD::BITCAST, dl, VT,
9785 DAG.getNode(ISD::AND, dl, ANDVT,
9786 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9788 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9790 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9793 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
9794 LLVMContext *Context = DAG.getContext();
9796 MVT VT = Op.getSimpleValueType();
9798 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9799 if (VT.isVector()) {
9800 EltVT = VT.getVectorElementType();
9801 NumElts = VT.getVectorNumElements();
9804 if (EltVT == MVT::f64)
9805 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9806 APInt(64, 1ULL << 63)));
9808 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9809 APInt(32, 1U << 31)));
9810 C = ConstantVector::getSplat(NumElts, C);
9811 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9812 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9813 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9814 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9815 MachinePointerInfo::getConstantPool(),
9816 false, false, false, Alignment);
9817 if (VT.isVector()) {
9818 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9819 return DAG.getNode(ISD::BITCAST, dl, VT,
9820 DAG.getNode(ISD::XOR, dl, XORVT,
9821 DAG.getNode(ISD::BITCAST, dl, XORVT,
9823 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9826 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9829 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
9830 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9831 LLVMContext *Context = DAG.getContext();
9832 SDValue Op0 = Op.getOperand(0);
9833 SDValue Op1 = Op.getOperand(1);
9835 MVT VT = Op.getSimpleValueType();
9836 MVT SrcVT = Op1.getSimpleValueType();
9838 // If second operand is smaller, extend it first.
9839 if (SrcVT.bitsLT(VT)) {
9840 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9843 // And if it is bigger, shrink it first.
9844 if (SrcVT.bitsGT(VT)) {
9845 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9849 // At this point the operands and the result should have the same
9850 // type, and that won't be f80 since that is not custom lowered.
9852 // First get the sign bit of second operand.
9853 SmallVector<Constant*,4> CV;
9854 if (SrcVT == MVT::f64) {
9855 const fltSemantics &Sem = APFloat::IEEEdouble;
9856 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9857 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9859 const fltSemantics &Sem = APFloat::IEEEsingle;
9860 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9861 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9862 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9863 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9865 Constant *C = ConstantVector::get(CV);
9866 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9867 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9868 MachinePointerInfo::getConstantPool(),
9869 false, false, false, 16);
9870 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9872 // Shift sign bit right or left if the two operands have different types.
9873 if (SrcVT.bitsGT(VT)) {
9874 // Op0 is MVT::f32, Op1 is MVT::f64.
9875 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9876 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9877 DAG.getConstant(32, MVT::i32));
9878 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9879 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9880 DAG.getIntPtrConstant(0));
9883 // Clear first operand sign bit.
9885 if (VT == MVT::f64) {
9886 const fltSemantics &Sem = APFloat::IEEEdouble;
9887 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9888 APInt(64, ~(1ULL << 63)))));
9889 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9891 const fltSemantics &Sem = APFloat::IEEEsingle;
9892 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9893 APInt(32, ~(1U << 31)))));
9894 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9895 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9896 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9898 C = ConstantVector::get(CV);
9899 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9900 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9901 MachinePointerInfo::getConstantPool(),
9902 false, false, false, 16);
9903 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9905 // Or the value with the sign bit.
9906 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9909 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9910 SDValue N0 = Op.getOperand(0);
9912 MVT VT = Op.getSimpleValueType();
9914 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9915 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9916 DAG.getConstant(1, VT));
9917 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9920 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9922 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9923 SelectionDAG &DAG) {
9924 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9926 if (!Subtarget->hasSSE41())
9929 if (!Op->hasOneUse())
9932 SDNode *N = Op.getNode();
9935 SmallVector<SDValue, 8> Opnds;
9936 DenseMap<SDValue, unsigned> VecInMap;
9937 SmallVector<SDValue, 8> VecIns;
9938 EVT VT = MVT::Other;
9940 // Recognize a special case where a vector is casted into wide integer to
9942 Opnds.push_back(N->getOperand(0));
9943 Opnds.push_back(N->getOperand(1));
9945 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9946 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9947 // BFS traverse all OR'd operands.
9948 if (I->getOpcode() == ISD::OR) {
9949 Opnds.push_back(I->getOperand(0));
9950 Opnds.push_back(I->getOperand(1));
9951 // Re-evaluate the number of nodes to be traversed.
9952 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9956 // Quit if a non-EXTRACT_VECTOR_ELT
9957 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9960 // Quit if without a constant index.
9961 SDValue Idx = I->getOperand(1);
9962 if (!isa<ConstantSDNode>(Idx))
9965 SDValue ExtractedFromVec = I->getOperand(0);
9966 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9967 if (M == VecInMap.end()) {
9968 VT = ExtractedFromVec.getValueType();
9969 // Quit if not 128/256-bit vector.
9970 if (!VT.is128BitVector() && !VT.is256BitVector())
9972 // Quit if not the same type.
9973 if (VecInMap.begin() != VecInMap.end() &&
9974 VT != VecInMap.begin()->first.getValueType())
9976 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9977 VecIns.push_back(ExtractedFromVec);
9979 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9982 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9983 "Not extracted from 128-/256-bit vector.");
9985 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9987 for (DenseMap<SDValue, unsigned>::const_iterator
9988 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9989 // Quit if not all elements are used.
9990 if (I->second != FullMask)
9994 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9996 // Cast all vectors into TestVT for PTEST.
9997 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9998 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
10000 // If more than one full vectors are evaluated, OR them first before PTEST.
10001 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
10002 // Each iteration will OR 2 nodes and append the result until there is only
10003 // 1 node left, i.e. the final OR'd value of all vectors.
10004 SDValue LHS = VecIns[Slot];
10005 SDValue RHS = VecIns[Slot + 1];
10006 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
10009 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
10010 VecIns.back(), VecIns.back());
10013 /// \brief return true if \c Op has a use that doesn't just read flags.
10014 static bool hasNonFlagsUse(SDValue Op) {
10015 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
10017 SDNode *User = *UI;
10018 unsigned UOpNo = UI.getOperandNo();
10019 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
10020 // Look pass truncate.
10021 UOpNo = User->use_begin().getOperandNo();
10022 User = *User->use_begin();
10025 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
10026 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
10032 /// Emit nodes that will be selected as "test Op0,Op0", or something
10034 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
10035 SelectionDAG &DAG) const {
10036 if (Op.getValueType() == MVT::i1)
10037 // KORTEST instruction should be selected
10038 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
10039 DAG.getConstant(0, Op.getValueType()));
10041 // CF and OF aren't always set the way we want. Determine which
10042 // of these we need.
10043 bool NeedCF = false;
10044 bool NeedOF = false;
10047 case X86::COND_A: case X86::COND_AE:
10048 case X86::COND_B: case X86::COND_BE:
10051 case X86::COND_G: case X86::COND_GE:
10052 case X86::COND_L: case X86::COND_LE:
10053 case X86::COND_O: case X86::COND_NO:
10057 // See if we can use the EFLAGS value from the operand instead of
10058 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
10059 // we prove that the arithmetic won't overflow, we can't use OF or CF.
10060 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
10061 // Emit a CMP with 0, which is the TEST pattern.
10062 //if (Op.getValueType() == MVT::i1)
10063 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
10064 // DAG.getConstant(0, MVT::i1));
10065 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
10066 DAG.getConstant(0, Op.getValueType()));
10068 unsigned Opcode = 0;
10069 unsigned NumOperands = 0;
10071 // Truncate operations may prevent the merge of the SETCC instruction
10072 // and the arithmetic instruction before it. Attempt to truncate the operands
10073 // of the arithmetic instruction and use a reduced bit-width instruction.
10074 bool NeedTruncation = false;
10075 SDValue ArithOp = Op;
10076 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
10077 SDValue Arith = Op->getOperand(0);
10078 // Both the trunc and the arithmetic op need to have one user each.
10079 if (Arith->hasOneUse())
10080 switch (Arith.getOpcode()) {
10087 NeedTruncation = true;
10093 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
10094 // which may be the result of a CAST. We use the variable 'Op', which is the
10095 // non-casted variable when we check for possible users.
10096 switch (ArithOp.getOpcode()) {
10098 // Due to an isel shortcoming, be conservative if this add is likely to be
10099 // selected as part of a load-modify-store instruction. When the root node
10100 // in a match is a store, isel doesn't know how to remap non-chain non-flag
10101 // uses of other nodes in the match, such as the ADD in this case. This
10102 // leads to the ADD being left around and reselected, with the result being
10103 // two adds in the output. Alas, even if none our users are stores, that
10104 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
10105 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
10106 // climbing the DAG back to the root, and it doesn't seem to be worth the
10108 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
10109 UE = Op.getNode()->use_end(); UI != UE; ++UI)
10110 if (UI->getOpcode() != ISD::CopyToReg &&
10111 UI->getOpcode() != ISD::SETCC &&
10112 UI->getOpcode() != ISD::STORE)
10115 if (ConstantSDNode *C =
10116 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
10117 // An add of one will be selected as an INC.
10118 if (C->getAPIntValue() == 1) {
10119 Opcode = X86ISD::INC;
10124 // An add of negative one (subtract of one) will be selected as a DEC.
10125 if (C->getAPIntValue().isAllOnesValue()) {
10126 Opcode = X86ISD::DEC;
10132 // Otherwise use a regular EFLAGS-setting add.
10133 Opcode = X86ISD::ADD;
10138 // If we have a constant logical shift that's only used in a comparison
10139 // against zero turn it into an equivalent AND. This allows turning it into
10140 // a TEST instruction later.
10141 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) &&
10142 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
10143 EVT VT = Op.getValueType();
10144 unsigned BitWidth = VT.getSizeInBits();
10145 unsigned ShAmt = Op->getConstantOperandVal(1);
10146 if (ShAmt >= BitWidth) // Avoid undefined shifts.
10148 APInt Mask = ArithOp.getOpcode() == ISD::SRL
10149 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
10150 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
10151 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
10153 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
10154 DAG.getConstant(Mask, VT));
10155 DAG.ReplaceAllUsesWith(Op, New);
10161 // If the primary and result isn't used, don't bother using X86ISD::AND,
10162 // because a TEST instruction will be better.
10163 if (!hasNonFlagsUse(Op))
10169 // Due to the ISEL shortcoming noted above, be conservative if this op is
10170 // likely to be selected as part of a load-modify-store instruction.
10171 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
10172 UE = Op.getNode()->use_end(); UI != UE; ++UI)
10173 if (UI->getOpcode() == ISD::STORE)
10176 // Otherwise use a regular EFLAGS-setting instruction.
10177 switch (ArithOp.getOpcode()) {
10178 default: llvm_unreachable("unexpected operator!");
10179 case ISD::SUB: Opcode = X86ISD::SUB; break;
10180 case ISD::XOR: Opcode = X86ISD::XOR; break;
10181 case ISD::AND: Opcode = X86ISD::AND; break;
10183 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
10184 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
10185 if (EFLAGS.getNode())
10188 Opcode = X86ISD::OR;
10202 return SDValue(Op.getNode(), 1);
10208 // If we found that truncation is beneficial, perform the truncation and
10210 if (NeedTruncation) {
10211 EVT VT = Op.getValueType();
10212 SDValue WideVal = Op->getOperand(0);
10213 EVT WideVT = WideVal.getValueType();
10214 unsigned ConvertedOp = 0;
10215 // Use a target machine opcode to prevent further DAGCombine
10216 // optimizations that may separate the arithmetic operations
10217 // from the setcc node.
10218 switch (WideVal.getOpcode()) {
10220 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
10221 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
10222 case ISD::AND: ConvertedOp = X86ISD::AND; break;
10223 case ISD::OR: ConvertedOp = X86ISD::OR; break;
10224 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
10228 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10229 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
10230 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
10231 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
10232 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
10238 // Emit a CMP with 0, which is the TEST pattern.
10239 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
10240 DAG.getConstant(0, Op.getValueType()));
10242 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10243 SmallVector<SDValue, 4> Ops;
10244 for (unsigned i = 0; i != NumOperands; ++i)
10245 Ops.push_back(Op.getOperand(i));
10247 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
10248 DAG.ReplaceAllUsesWith(Op, New);
10249 return SDValue(New.getNode(), 1);
10252 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
10254 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
10255 SDLoc dl, SelectionDAG &DAG) const {
10256 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
10257 if (C->getAPIntValue() == 0)
10258 return EmitTest(Op0, X86CC, dl, DAG);
10260 if (Op0.getValueType() == MVT::i1)
10261 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
10264 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
10265 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
10266 // Do the comparison at i32 if it's smaller, besides the Atom case.
10267 // This avoids subregister aliasing issues. Keep the smaller reference
10268 // if we're optimizing for size, however, as that'll allow better folding
10269 // of memory operations.
10270 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
10271 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
10272 AttributeSet::FunctionIndex, Attribute::MinSize) &&
10273 !Subtarget->isAtom()) {
10274 unsigned ExtendOp =
10275 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
10276 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
10277 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
10279 // Use SUB instead of CMP to enable CSE between SUB and CMP.
10280 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
10281 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
10283 return SDValue(Sub.getNode(), 1);
10285 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
10288 /// Convert a comparison if required by the subtarget.
10289 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
10290 SelectionDAG &DAG) const {
10291 // If the subtarget does not support the FUCOMI instruction, floating-point
10292 // comparisons have to be converted.
10293 if (Subtarget->hasCMov() ||
10294 Cmp.getOpcode() != X86ISD::CMP ||
10295 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
10296 !Cmp.getOperand(1).getValueType().isFloatingPoint())
10299 // The instruction selector will select an FUCOM instruction instead of
10300 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
10301 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
10302 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
10304 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
10305 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
10306 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
10307 DAG.getConstant(8, MVT::i8));
10308 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
10309 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
10312 static bool isAllOnes(SDValue V) {
10313 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10314 return C && C->isAllOnesValue();
10317 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
10318 /// if it's possible.
10319 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
10320 SDLoc dl, SelectionDAG &DAG) const {
10321 SDValue Op0 = And.getOperand(0);
10322 SDValue Op1 = And.getOperand(1);
10323 if (Op0.getOpcode() == ISD::TRUNCATE)
10324 Op0 = Op0.getOperand(0);
10325 if (Op1.getOpcode() == ISD::TRUNCATE)
10326 Op1 = Op1.getOperand(0);
10329 if (Op1.getOpcode() == ISD::SHL)
10330 std::swap(Op0, Op1);
10331 if (Op0.getOpcode() == ISD::SHL) {
10332 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
10333 if (And00C->getZExtValue() == 1) {
10334 // If we looked past a truncate, check that it's only truncating away
10336 unsigned BitWidth = Op0.getValueSizeInBits();
10337 unsigned AndBitWidth = And.getValueSizeInBits();
10338 if (BitWidth > AndBitWidth) {
10340 DAG.computeKnownBits(Op0, Zeros, Ones);
10341 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
10345 RHS = Op0.getOperand(1);
10347 } else if (Op1.getOpcode() == ISD::Constant) {
10348 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
10349 uint64_t AndRHSVal = AndRHS->getZExtValue();
10350 SDValue AndLHS = Op0;
10352 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
10353 LHS = AndLHS.getOperand(0);
10354 RHS = AndLHS.getOperand(1);
10357 // Use BT if the immediate can't be encoded in a TEST instruction.
10358 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
10360 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
10364 if (LHS.getNode()) {
10365 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
10366 // instruction. Since the shift amount is in-range-or-undefined, we know
10367 // that doing a bittest on the i32 value is ok. We extend to i32 because
10368 // the encoding for the i16 version is larger than the i32 version.
10369 // Also promote i16 to i32 for performance / code size reason.
10370 if (LHS.getValueType() == MVT::i8 ||
10371 LHS.getValueType() == MVT::i16)
10372 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
10374 // If the operand types disagree, extend the shift amount to match. Since
10375 // BT ignores high bits (like shifts) we can use anyextend.
10376 if (LHS.getValueType() != RHS.getValueType())
10377 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
10379 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
10380 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
10381 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10382 DAG.getConstant(Cond, MVT::i8), BT);
10388 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
10390 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
10395 // SSE Condition code mapping:
10404 switch (SetCCOpcode) {
10405 default: llvm_unreachable("Unexpected SETCC condition");
10407 case ISD::SETEQ: SSECC = 0; break;
10409 case ISD::SETGT: Swap = true; // Fallthrough
10411 case ISD::SETOLT: SSECC = 1; break;
10413 case ISD::SETGE: Swap = true; // Fallthrough
10415 case ISD::SETOLE: SSECC = 2; break;
10416 case ISD::SETUO: SSECC = 3; break;
10418 case ISD::SETNE: SSECC = 4; break;
10419 case ISD::SETULE: Swap = true; // Fallthrough
10420 case ISD::SETUGE: SSECC = 5; break;
10421 case ISD::SETULT: Swap = true; // Fallthrough
10422 case ISD::SETUGT: SSECC = 6; break;
10423 case ISD::SETO: SSECC = 7; break;
10425 case ISD::SETONE: SSECC = 8; break;
10428 std::swap(Op0, Op1);
10433 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
10434 // ones, and then concatenate the result back.
10435 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
10436 MVT VT = Op.getSimpleValueType();
10438 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
10439 "Unsupported value type for operation");
10441 unsigned NumElems = VT.getVectorNumElements();
10443 SDValue CC = Op.getOperand(2);
10445 // Extract the LHS vectors
10446 SDValue LHS = Op.getOperand(0);
10447 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10448 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10450 // Extract the RHS vectors
10451 SDValue RHS = Op.getOperand(1);
10452 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10453 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10455 // Issue the operation on the smaller types and concatenate the result back
10456 MVT EltVT = VT.getVectorElementType();
10457 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10458 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10459 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
10460 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
10463 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
10464 const X86Subtarget *Subtarget) {
10465 SDValue Op0 = Op.getOperand(0);
10466 SDValue Op1 = Op.getOperand(1);
10467 SDValue CC = Op.getOperand(2);
10468 MVT VT = Op.getSimpleValueType();
10471 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
10472 Op.getValueType().getScalarType() == MVT::i1 &&
10473 "Cannot set masked compare for this operation");
10475 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10477 bool Unsigned = false;
10480 switch (SetCCOpcode) {
10481 default: llvm_unreachable("Unexpected SETCC condition");
10482 case ISD::SETNE: SSECC = 4; break;
10483 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
10484 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
10485 case ISD::SETLT: Swap = true; //fall-through
10486 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
10487 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
10488 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
10489 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
10490 case ISD::SETULE: Unsigned = true; //fall-through
10491 case ISD::SETLE: SSECC = 2; break;
10495 std::swap(Op0, Op1);
10497 return DAG.getNode(Opc, dl, VT, Op0, Op1);
10498 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
10499 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10500 DAG.getConstant(SSECC, MVT::i8));
10503 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
10504 /// operand \p Op1. If non-trivial (for example because it's not constant)
10505 /// return an empty value.
10506 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
10508 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
10512 MVT VT = Op1.getSimpleValueType();
10513 MVT EVT = VT.getVectorElementType();
10514 unsigned n = VT.getVectorNumElements();
10515 SmallVector<SDValue, 8> ULTOp1;
10517 for (unsigned i = 0; i < n; ++i) {
10518 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
10519 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
10522 // Avoid underflow.
10523 APInt Val = Elt->getAPIntValue();
10527 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
10530 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
10533 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
10534 SelectionDAG &DAG) {
10535 SDValue Op0 = Op.getOperand(0);
10536 SDValue Op1 = Op.getOperand(1);
10537 SDValue CC = Op.getOperand(2);
10538 MVT VT = Op.getSimpleValueType();
10539 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10540 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
10545 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
10546 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
10549 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
10550 unsigned Opc = X86ISD::CMPP;
10551 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
10552 assert(VT.getVectorNumElements() <= 16);
10553 Opc = X86ISD::CMPM;
10555 // In the two special cases we can't handle, emit two comparisons.
10558 unsigned CombineOpc;
10559 if (SetCCOpcode == ISD::SETUEQ) {
10560 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
10562 assert(SetCCOpcode == ISD::SETONE);
10563 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
10566 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10567 DAG.getConstant(CC0, MVT::i8));
10568 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10569 DAG.getConstant(CC1, MVT::i8));
10570 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
10572 // Handle all other FP comparisons here.
10573 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10574 DAG.getConstant(SSECC, MVT::i8));
10577 // Break 256-bit integer vector compare into smaller ones.
10578 if (VT.is256BitVector() && !Subtarget->hasInt256())
10579 return Lower256IntVSETCC(Op, DAG);
10581 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
10582 EVT OpVT = Op1.getValueType();
10583 if (Subtarget->hasAVX512()) {
10584 if (Op1.getValueType().is512BitVector() ||
10585 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
10586 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
10588 // In AVX-512 architecture setcc returns mask with i1 elements,
10589 // But there is no compare instruction for i8 and i16 elements.
10590 // We are not talking about 512-bit operands in this case, these
10591 // types are illegal.
10593 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
10594 OpVT.getVectorElementType().getSizeInBits() >= 8))
10595 return DAG.getNode(ISD::TRUNCATE, dl, VT,
10596 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
10599 // We are handling one of the integer comparisons here. Since SSE only has
10600 // GT and EQ comparisons for integer, swapping operands and multiple
10601 // operations may be required for some comparisons.
10603 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
10604 bool Subus = false;
10606 switch (SetCCOpcode) {
10607 default: llvm_unreachable("Unexpected SETCC condition");
10608 case ISD::SETNE: Invert = true;
10609 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
10610 case ISD::SETLT: Swap = true;
10611 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
10612 case ISD::SETGE: Swap = true;
10613 case ISD::SETLE: Opc = X86ISD::PCMPGT;
10614 Invert = true; break;
10615 case ISD::SETULT: Swap = true;
10616 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
10617 FlipSigns = true; break;
10618 case ISD::SETUGE: Swap = true;
10619 case ISD::SETULE: Opc = X86ISD::PCMPGT;
10620 FlipSigns = true; Invert = true; break;
10623 // Special case: Use min/max operations for SETULE/SETUGE
10624 MVT VET = VT.getVectorElementType();
10626 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
10627 || (Subtarget->hasSSE2() && (VET == MVT::i8));
10630 switch (SetCCOpcode) {
10632 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
10633 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
10636 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
10639 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
10640 if (!MinMax && hasSubus) {
10641 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
10643 // t = psubus Op0, Op1
10644 // pcmpeq t, <0..0>
10645 switch (SetCCOpcode) {
10647 case ISD::SETULT: {
10648 // If the comparison is against a constant we can turn this into a
10649 // setule. With psubus, setule does not require a swap. This is
10650 // beneficial because the constant in the register is no longer
10651 // destructed as the destination so it can be hoisted out of a loop.
10652 // Only do this pre-AVX since vpcmp* is no longer destructive.
10653 if (Subtarget->hasAVX())
10655 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
10656 if (ULEOp1.getNode()) {
10658 Subus = true; Invert = false; Swap = false;
10662 // Psubus is better than flip-sign because it requires no inversion.
10663 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
10664 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
10668 Opc = X86ISD::SUBUS;
10674 std::swap(Op0, Op1);
10676 // Check that the operation in question is available (most are plain SSE2,
10677 // but PCMPGTQ and PCMPEQQ have different requirements).
10678 if (VT == MVT::v2i64) {
10679 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
10680 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
10682 // First cast everything to the right type.
10683 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10684 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10686 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10687 // bits of the inputs before performing those operations. The lower
10688 // compare is always unsigned.
10691 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10693 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10694 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10695 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10696 Sign, Zero, Sign, Zero);
10698 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10699 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10701 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10702 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10703 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10705 // Create masks for only the low parts/high parts of the 64 bit integers.
10706 static const int MaskHi[] = { 1, 1, 3, 3 };
10707 static const int MaskLo[] = { 0, 0, 2, 2 };
10708 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10709 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10710 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10712 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10713 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10716 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10718 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10721 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10722 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10723 // pcmpeqd + pshufd + pand.
10724 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10726 // First cast everything to the right type.
10727 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10728 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10731 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10733 // Make sure the lower and upper halves are both all-ones.
10734 static const int Mask[] = { 1, 0, 3, 2 };
10735 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10736 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10739 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10741 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10745 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10746 // bits of the inputs before performing those operations.
10748 EVT EltVT = VT.getVectorElementType();
10749 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10750 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10751 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10754 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10756 // If the logical-not of the result is required, perform that now.
10758 Result = DAG.getNOT(dl, Result, VT);
10761 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10764 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
10765 getZeroVector(VT, Subtarget, DAG, dl));
10770 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10772 MVT VT = Op.getSimpleValueType();
10774 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10776 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
10777 && "SetCC type must be 8-bit or 1-bit integer");
10778 SDValue Op0 = Op.getOperand(0);
10779 SDValue Op1 = Op.getOperand(1);
10781 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10783 // Optimize to BT if possible.
10784 // Lower (X & (1 << N)) == 0 to BT(X, N).
10785 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10786 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10787 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10788 Op1.getOpcode() == ISD::Constant &&
10789 cast<ConstantSDNode>(Op1)->isNullValue() &&
10790 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10791 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10792 if (NewSetCC.getNode())
10796 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10798 if (Op1.getOpcode() == ISD::Constant &&
10799 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10800 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10801 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10803 // If the input is a setcc, then reuse the input setcc or use a new one with
10804 // the inverted condition.
10805 if (Op0.getOpcode() == X86ISD::SETCC) {
10806 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10807 bool Invert = (CC == ISD::SETNE) ^
10808 cast<ConstantSDNode>(Op1)->isNullValue();
10812 CCode = X86::GetOppositeBranchCondition(CCode);
10813 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10814 DAG.getConstant(CCode, MVT::i8),
10815 Op0.getOperand(1));
10817 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10821 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
10822 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
10823 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10825 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
10826 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
10829 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10830 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10831 if (X86CC == X86::COND_INVALID)
10834 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
10835 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10836 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10837 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10839 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10843 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10844 static bool isX86LogicalCmp(SDValue Op) {
10845 unsigned Opc = Op.getNode()->getOpcode();
10846 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10847 Opc == X86ISD::SAHF)
10849 if (Op.getResNo() == 1 &&
10850 (Opc == X86ISD::ADD ||
10851 Opc == X86ISD::SUB ||
10852 Opc == X86ISD::ADC ||
10853 Opc == X86ISD::SBB ||
10854 Opc == X86ISD::SMUL ||
10855 Opc == X86ISD::UMUL ||
10856 Opc == X86ISD::INC ||
10857 Opc == X86ISD::DEC ||
10858 Opc == X86ISD::OR ||
10859 Opc == X86ISD::XOR ||
10860 Opc == X86ISD::AND))
10863 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10869 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10870 if (V.getOpcode() != ISD::TRUNCATE)
10873 SDValue VOp0 = V.getOperand(0);
10874 unsigned InBits = VOp0.getValueSizeInBits();
10875 unsigned Bits = V.getValueSizeInBits();
10876 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10879 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10880 bool addTest = true;
10881 SDValue Cond = Op.getOperand(0);
10882 SDValue Op1 = Op.getOperand(1);
10883 SDValue Op2 = Op.getOperand(2);
10885 EVT VT = Op1.getValueType();
10888 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10889 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10890 // sequence later on.
10891 if (Cond.getOpcode() == ISD::SETCC &&
10892 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10893 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10894 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10895 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10896 int SSECC = translateX86FSETCC(
10897 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10900 if (Subtarget->hasAVX512()) {
10901 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
10902 DAG.getConstant(SSECC, MVT::i8));
10903 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
10905 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
10906 DAG.getConstant(SSECC, MVT::i8));
10907 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10908 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10909 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10913 if (Cond.getOpcode() == ISD::SETCC) {
10914 SDValue NewCond = LowerSETCC(Cond, DAG);
10915 if (NewCond.getNode())
10919 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10920 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10921 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10922 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10923 if (Cond.getOpcode() == X86ISD::SETCC &&
10924 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10925 isZero(Cond.getOperand(1).getOperand(1))) {
10926 SDValue Cmp = Cond.getOperand(1);
10928 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10930 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10931 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10932 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10934 SDValue CmpOp0 = Cmp.getOperand(0);
10935 // Apply further optimizations for special cases
10936 // (select (x != 0), -1, 0) -> neg & sbb
10937 // (select (x == 0), 0, -1) -> neg & sbb
10938 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10939 if (YC->isNullValue() &&
10940 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10941 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10942 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10943 DAG.getConstant(0, CmpOp0.getValueType()),
10945 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10946 DAG.getConstant(X86::COND_B, MVT::i8),
10947 SDValue(Neg.getNode(), 1));
10951 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10952 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10953 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10955 SDValue Res = // Res = 0 or -1.
10956 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10957 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10959 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10960 Res = DAG.getNOT(DL, Res, Res.getValueType());
10962 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10963 if (!N2C || !N2C->isNullValue())
10964 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10969 // Look past (and (setcc_carry (cmp ...)), 1).
10970 if (Cond.getOpcode() == ISD::AND &&
10971 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10972 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10973 if (C && C->getAPIntValue() == 1)
10974 Cond = Cond.getOperand(0);
10977 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10978 // setting operand in place of the X86ISD::SETCC.
10979 unsigned CondOpcode = Cond.getOpcode();
10980 if (CondOpcode == X86ISD::SETCC ||
10981 CondOpcode == X86ISD::SETCC_CARRY) {
10982 CC = Cond.getOperand(0);
10984 SDValue Cmp = Cond.getOperand(1);
10985 unsigned Opc = Cmp.getOpcode();
10986 MVT VT = Op.getSimpleValueType();
10988 bool IllegalFPCMov = false;
10989 if (VT.isFloatingPoint() && !VT.isVector() &&
10990 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10991 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10993 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10994 Opc == X86ISD::BT) { // FIXME
10998 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10999 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
11000 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
11001 Cond.getOperand(0).getValueType() != MVT::i8)) {
11002 SDValue LHS = Cond.getOperand(0);
11003 SDValue RHS = Cond.getOperand(1);
11004 unsigned X86Opcode;
11007 switch (CondOpcode) {
11008 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
11009 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
11010 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
11011 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
11012 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
11013 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
11014 default: llvm_unreachable("unexpected overflowing operator");
11016 if (CondOpcode == ISD::UMULO)
11017 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
11020 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
11022 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
11024 if (CondOpcode == ISD::UMULO)
11025 Cond = X86Op.getValue(2);
11027 Cond = X86Op.getValue(1);
11029 CC = DAG.getConstant(X86Cond, MVT::i8);
11034 // Look pass the truncate if the high bits are known zero.
11035 if (isTruncWithZeroHighBitsInput(Cond, DAG))
11036 Cond = Cond.getOperand(0);
11038 // We know the result of AND is compared against zero. Try to match
11040 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
11041 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
11042 if (NewSetCC.getNode()) {
11043 CC = NewSetCC.getOperand(0);
11044 Cond = NewSetCC.getOperand(1);
11051 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11052 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
11055 // a < b ? -1 : 0 -> RES = ~setcc_carry
11056 // a < b ? 0 : -1 -> RES = setcc_carry
11057 // a >= b ? -1 : 0 -> RES = setcc_carry
11058 // a >= b ? 0 : -1 -> RES = ~setcc_carry
11059 if (Cond.getOpcode() == X86ISD::SUB) {
11060 Cond = ConvertCmpIfNecessary(Cond, DAG);
11061 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
11063 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
11064 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
11065 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
11066 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
11067 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
11068 return DAG.getNOT(DL, Res, Res.getValueType());
11073 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
11074 // widen the cmov and push the truncate through. This avoids introducing a new
11075 // branch during isel and doesn't add any extensions.
11076 if (Op.getValueType() == MVT::i8 &&
11077 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
11078 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
11079 if (T1.getValueType() == T2.getValueType() &&
11080 // Blacklist CopyFromReg to avoid partial register stalls.
11081 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
11082 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
11083 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
11084 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
11088 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
11089 // condition is true.
11090 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
11091 SDValue Ops[] = { Op2, Op1, CC, Cond };
11092 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
11095 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
11096 MVT VT = Op->getSimpleValueType(0);
11097 SDValue In = Op->getOperand(0);
11098 MVT InVT = In.getSimpleValueType();
11101 unsigned int NumElts = VT.getVectorNumElements();
11102 if (NumElts != 8 && NumElts != 16)
11105 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11106 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
11108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11109 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11111 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
11112 Constant *C = ConstantInt::get(*DAG.getContext(),
11113 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
11115 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11116 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11117 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
11118 MachinePointerInfo::getConstantPool(),
11119 false, false, false, Alignment);
11120 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
11121 if (VT.is512BitVector())
11123 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
11126 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11127 SelectionDAG &DAG) {
11128 MVT VT = Op->getSimpleValueType(0);
11129 SDValue In = Op->getOperand(0);
11130 MVT InVT = In.getSimpleValueType();
11133 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
11134 return LowerSIGN_EXTEND_AVX512(Op, DAG);
11136 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
11137 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
11138 (VT != MVT::v16i16 || InVT != MVT::v16i8))
11141 if (Subtarget->hasInt256())
11142 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
11144 // Optimize vectors in AVX mode
11145 // Sign extend v8i16 to v8i32 and
11148 // Divide input vector into two parts
11149 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
11150 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
11151 // concat the vectors to original VT
11153 unsigned NumElems = InVT.getVectorNumElements();
11154 SDValue Undef = DAG.getUNDEF(InVT);
11156 SmallVector<int,8> ShufMask1(NumElems, -1);
11157 for (unsigned i = 0; i != NumElems/2; ++i)
11160 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
11162 SmallVector<int,8> ShufMask2(NumElems, -1);
11163 for (unsigned i = 0; i != NumElems/2; ++i)
11164 ShufMask2[i] = i + NumElems/2;
11166 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
11168 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
11169 VT.getVectorNumElements()/2);
11171 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
11172 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
11174 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11177 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
11178 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
11179 // from the AND / OR.
11180 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
11181 Opc = Op.getOpcode();
11182 if (Opc != ISD::OR && Opc != ISD::AND)
11184 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
11185 Op.getOperand(0).hasOneUse() &&
11186 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
11187 Op.getOperand(1).hasOneUse());
11190 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
11191 // 1 and that the SETCC node has a single use.
11192 static bool isXor1OfSetCC(SDValue Op) {
11193 if (Op.getOpcode() != ISD::XOR)
11195 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
11196 if (N1C && N1C->getAPIntValue() == 1) {
11197 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
11198 Op.getOperand(0).hasOneUse();
11203 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
11204 bool addTest = true;
11205 SDValue Chain = Op.getOperand(0);
11206 SDValue Cond = Op.getOperand(1);
11207 SDValue Dest = Op.getOperand(2);
11210 bool Inverted = false;
11212 if (Cond.getOpcode() == ISD::SETCC) {
11213 // Check for setcc([su]{add,sub,mul}o == 0).
11214 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
11215 isa<ConstantSDNode>(Cond.getOperand(1)) &&
11216 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
11217 Cond.getOperand(0).getResNo() == 1 &&
11218 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
11219 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
11220 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
11221 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
11222 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
11223 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
11225 Cond = Cond.getOperand(0);
11227 SDValue NewCond = LowerSETCC(Cond, DAG);
11228 if (NewCond.getNode())
11233 // FIXME: LowerXALUO doesn't handle these!!
11234 else if (Cond.getOpcode() == X86ISD::ADD ||
11235 Cond.getOpcode() == X86ISD::SUB ||
11236 Cond.getOpcode() == X86ISD::SMUL ||
11237 Cond.getOpcode() == X86ISD::UMUL)
11238 Cond = LowerXALUO(Cond, DAG);
11241 // Look pass (and (setcc_carry (cmp ...)), 1).
11242 if (Cond.getOpcode() == ISD::AND &&
11243 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
11244 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
11245 if (C && C->getAPIntValue() == 1)
11246 Cond = Cond.getOperand(0);
11249 // If condition flag is set by a X86ISD::CMP, then use it as the condition
11250 // setting operand in place of the X86ISD::SETCC.
11251 unsigned CondOpcode = Cond.getOpcode();
11252 if (CondOpcode == X86ISD::SETCC ||
11253 CondOpcode == X86ISD::SETCC_CARRY) {
11254 CC = Cond.getOperand(0);
11256 SDValue Cmp = Cond.getOperand(1);
11257 unsigned Opc = Cmp.getOpcode();
11258 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
11259 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
11263 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
11267 // These can only come from an arithmetic instruction with overflow,
11268 // e.g. SADDO, UADDO.
11269 Cond = Cond.getNode()->getOperand(1);
11275 CondOpcode = Cond.getOpcode();
11276 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
11277 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
11278 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
11279 Cond.getOperand(0).getValueType() != MVT::i8)) {
11280 SDValue LHS = Cond.getOperand(0);
11281 SDValue RHS = Cond.getOperand(1);
11282 unsigned X86Opcode;
11285 // Keep this in sync with LowerXALUO, otherwise we might create redundant
11286 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
11288 switch (CondOpcode) {
11289 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
11291 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11293 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
11296 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
11297 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
11299 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11301 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
11304 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
11305 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
11306 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
11307 default: llvm_unreachable("unexpected overflowing operator");
11310 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
11311 if (CondOpcode == ISD::UMULO)
11312 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
11315 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
11317 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
11319 if (CondOpcode == ISD::UMULO)
11320 Cond = X86Op.getValue(2);
11322 Cond = X86Op.getValue(1);
11324 CC = DAG.getConstant(X86Cond, MVT::i8);
11328 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
11329 SDValue Cmp = Cond.getOperand(0).getOperand(1);
11330 if (CondOpc == ISD::OR) {
11331 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
11332 // two branches instead of an explicit OR instruction with a
11334 if (Cmp == Cond.getOperand(1).getOperand(1) &&
11335 isX86LogicalCmp(Cmp)) {
11336 CC = Cond.getOperand(0).getOperand(0);
11337 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11338 Chain, Dest, CC, Cmp);
11339 CC = Cond.getOperand(1).getOperand(0);
11343 } else { // ISD::AND
11344 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
11345 // two branches instead of an explicit AND instruction with a
11346 // separate test. However, we only do this if this block doesn't
11347 // have a fall-through edge, because this requires an explicit
11348 // jmp when the condition is false.
11349 if (Cmp == Cond.getOperand(1).getOperand(1) &&
11350 isX86LogicalCmp(Cmp) &&
11351 Op.getNode()->hasOneUse()) {
11352 X86::CondCode CCode =
11353 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
11354 CCode = X86::GetOppositeBranchCondition(CCode);
11355 CC = DAG.getConstant(CCode, MVT::i8);
11356 SDNode *User = *Op.getNode()->use_begin();
11357 // Look for an unconditional branch following this conditional branch.
11358 // We need this because we need to reverse the successors in order
11359 // to implement FCMP_OEQ.
11360 if (User->getOpcode() == ISD::BR) {
11361 SDValue FalseBB = User->getOperand(1);
11363 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
11364 assert(NewBR == User);
11368 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11369 Chain, Dest, CC, Cmp);
11370 X86::CondCode CCode =
11371 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
11372 CCode = X86::GetOppositeBranchCondition(CCode);
11373 CC = DAG.getConstant(CCode, MVT::i8);
11379 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
11380 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
11381 // It should be transformed during dag combiner except when the condition
11382 // is set by a arithmetics with overflow node.
11383 X86::CondCode CCode =
11384 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
11385 CCode = X86::GetOppositeBranchCondition(CCode);
11386 CC = DAG.getConstant(CCode, MVT::i8);
11387 Cond = Cond.getOperand(0).getOperand(1);
11389 } else if (Cond.getOpcode() == ISD::SETCC &&
11390 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
11391 // For FCMP_OEQ, we can emit
11392 // two branches instead of an explicit AND instruction with a
11393 // separate test. However, we only do this if this block doesn't
11394 // have a fall-through edge, because this requires an explicit
11395 // jmp when the condition is false.
11396 if (Op.getNode()->hasOneUse()) {
11397 SDNode *User = *Op.getNode()->use_begin();
11398 // Look for an unconditional branch following this conditional branch.
11399 // We need this because we need to reverse the successors in order
11400 // to implement FCMP_OEQ.
11401 if (User->getOpcode() == ISD::BR) {
11402 SDValue FalseBB = User->getOperand(1);
11404 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
11405 assert(NewBR == User);
11409 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11410 Cond.getOperand(0), Cond.getOperand(1));
11411 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
11412 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11413 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11414 Chain, Dest, CC, Cmp);
11415 CC = DAG.getConstant(X86::COND_P, MVT::i8);
11420 } else if (Cond.getOpcode() == ISD::SETCC &&
11421 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
11422 // For FCMP_UNE, we can emit
11423 // two branches instead of an explicit AND instruction with a
11424 // separate test. However, we only do this if this block doesn't
11425 // have a fall-through edge, because this requires an explicit
11426 // jmp when the condition is false.
11427 if (Op.getNode()->hasOneUse()) {
11428 SDNode *User = *Op.getNode()->use_begin();
11429 // Look for an unconditional branch following this conditional branch.
11430 // We need this because we need to reverse the successors in order
11431 // to implement FCMP_UNE.
11432 if (User->getOpcode() == ISD::BR) {
11433 SDValue FalseBB = User->getOperand(1);
11435 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
11436 assert(NewBR == User);
11439 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11440 Cond.getOperand(0), Cond.getOperand(1));
11441 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
11442 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11443 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11444 Chain, Dest, CC, Cmp);
11445 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
11455 // Look pass the truncate if the high bits are known zero.
11456 if (isTruncWithZeroHighBitsInput(Cond, DAG))
11457 Cond = Cond.getOperand(0);
11459 // We know the result of AND is compared against zero. Try to match
11461 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
11462 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
11463 if (NewSetCC.getNode()) {
11464 CC = NewSetCC.getOperand(0);
11465 Cond = NewSetCC.getOperand(1);
11472 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11473 Cond = EmitTest(Cond, X86::COND_NE, dl, DAG);
11475 Cond = ConvertCmpIfNecessary(Cond, DAG);
11476 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11477 Chain, Dest, CC, Cond);
11480 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
11481 // Calls to _alloca is needed to probe the stack when allocating more than 4k
11482 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
11483 // that the guard pages used by the OS virtual memory manager are allocated in
11484 // correct sequence.
11486 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
11487 SelectionDAG &DAG) const {
11488 MachineFunction &MF = DAG.getMachineFunction();
11489 bool SplitStack = MF.shouldSplitStack();
11490 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
11495 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11496 SDNode* Node = Op.getNode();
11498 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
11499 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
11500 " not tell us which reg is the stack pointer!");
11501 EVT VT = Node->getValueType(0);
11502 SDValue Tmp1 = SDValue(Node, 0);
11503 SDValue Tmp2 = SDValue(Node, 1);
11504 SDValue Tmp3 = Node->getOperand(2);
11505 SDValue Chain = Tmp1.getOperand(0);
11507 // Chain the dynamic stack allocation so that it doesn't modify the stack
11508 // pointer when other instructions are using the stack.
11509 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
11512 SDValue Size = Tmp2.getOperand(1);
11513 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
11514 Chain = SP.getValue(1);
11515 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
11516 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
11517 unsigned StackAlign = TFI.getStackAlignment();
11518 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
11519 if (Align > StackAlign)
11520 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
11521 DAG.getConstant(-(uint64_t)Align, VT));
11522 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
11524 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
11525 DAG.getIntPtrConstant(0, true), SDValue(),
11528 SDValue Ops[2] = { Tmp1, Tmp2 };
11529 return DAG.getMergeValues(Ops, dl);
11533 SDValue Chain = Op.getOperand(0);
11534 SDValue Size = Op.getOperand(1);
11535 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
11536 EVT VT = Op.getNode()->getValueType(0);
11538 bool Is64Bit = Subtarget->is64Bit();
11539 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
11542 MachineRegisterInfo &MRI = MF.getRegInfo();
11545 // The 64 bit implementation of segmented stacks needs to clobber both r10
11546 // r11. This makes it impossible to use it along with nested parameters.
11547 const Function *F = MF.getFunction();
11549 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
11551 if (I->hasNestAttr())
11552 report_fatal_error("Cannot use segmented stacks with functions that "
11553 "have nested arguments.");
11556 const TargetRegisterClass *AddrRegClass =
11557 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
11558 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
11559 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
11560 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
11561 DAG.getRegister(Vreg, SPTy));
11562 SDValue Ops1[2] = { Value, Chain };
11563 return DAG.getMergeValues(Ops1, dl);
11566 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
11568 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
11569 Flag = Chain.getValue(1);
11570 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11572 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
11574 const X86RegisterInfo *RegInfo =
11575 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11576 unsigned SPReg = RegInfo->getStackRegister();
11577 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
11578 Chain = SP.getValue(1);
11581 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
11582 DAG.getConstant(-(uint64_t)Align, VT));
11583 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
11586 SDValue Ops1[2] = { SP, Chain };
11587 return DAG.getMergeValues(Ops1, dl);
11591 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
11592 MachineFunction &MF = DAG.getMachineFunction();
11593 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
11595 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11598 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
11599 // vastart just stores the address of the VarArgsFrameIndex slot into the
11600 // memory location argument.
11601 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11603 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
11604 MachinePointerInfo(SV), false, false, 0);
11608 // gp_offset (0 - 6 * 8)
11609 // fp_offset (48 - 48 + 8 * 16)
11610 // overflow_arg_area (point to parameters coming in memory).
11612 SmallVector<SDValue, 8> MemOps;
11613 SDValue FIN = Op.getOperand(1);
11615 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
11616 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
11618 FIN, MachinePointerInfo(SV), false, false, 0);
11619 MemOps.push_back(Store);
11622 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11623 FIN, DAG.getIntPtrConstant(4));
11624 Store = DAG.getStore(Op.getOperand(0), DL,
11625 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
11627 FIN, MachinePointerInfo(SV, 4), false, false, 0);
11628 MemOps.push_back(Store);
11630 // Store ptr to overflow_arg_area
11631 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11632 FIN, DAG.getIntPtrConstant(4));
11633 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11635 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
11636 MachinePointerInfo(SV, 8),
11638 MemOps.push_back(Store);
11640 // Store ptr to reg_save_area.
11641 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11642 FIN, DAG.getIntPtrConstant(8));
11643 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
11645 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
11646 MachinePointerInfo(SV, 16), false, false, 0);
11647 MemOps.push_back(Store);
11648 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
11651 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
11652 assert(Subtarget->is64Bit() &&
11653 "LowerVAARG only handles 64-bit va_arg!");
11654 assert((Subtarget->isTargetLinux() ||
11655 Subtarget->isTargetDarwin()) &&
11656 "Unhandled target in LowerVAARG");
11657 assert(Op.getNode()->getNumOperands() == 4);
11658 SDValue Chain = Op.getOperand(0);
11659 SDValue SrcPtr = Op.getOperand(1);
11660 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11661 unsigned Align = Op.getConstantOperandVal(3);
11664 EVT ArgVT = Op.getNode()->getValueType(0);
11665 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11666 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
11669 // Decide which area this value should be read from.
11670 // TODO: Implement the AMD64 ABI in its entirety. This simple
11671 // selection mechanism works only for the basic types.
11672 if (ArgVT == MVT::f80) {
11673 llvm_unreachable("va_arg for f80 not yet implemented");
11674 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
11675 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
11676 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
11677 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
11679 llvm_unreachable("Unhandled argument type in LowerVAARG");
11682 if (ArgMode == 2) {
11683 // Sanity Check: Make sure using fp_offset makes sense.
11684 assert(!getTargetMachine().Options.UseSoftFloat &&
11685 !(DAG.getMachineFunction()
11686 .getFunction()->getAttributes()
11687 .hasAttribute(AttributeSet::FunctionIndex,
11688 Attribute::NoImplicitFloat)) &&
11689 Subtarget->hasSSE1());
11692 // Insert VAARG_64 node into the DAG
11693 // VAARG_64 returns two values: Variable Argument Address, Chain
11694 SmallVector<SDValue, 11> InstOps;
11695 InstOps.push_back(Chain);
11696 InstOps.push_back(SrcPtr);
11697 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
11698 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
11699 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
11700 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
11701 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
11702 VTs, InstOps, MVT::i64,
11703 MachinePointerInfo(SV),
11705 /*Volatile=*/false,
11707 /*WriteMem=*/true);
11708 Chain = VAARG.getValue(1);
11710 // Load the next argument and return it
11711 return DAG.getLoad(ArgVT, dl,
11714 MachinePointerInfo(),
11715 false, false, false, 0);
11718 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
11719 SelectionDAG &DAG) {
11720 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
11721 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
11722 SDValue Chain = Op.getOperand(0);
11723 SDValue DstPtr = Op.getOperand(1);
11724 SDValue SrcPtr = Op.getOperand(2);
11725 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
11726 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11729 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
11730 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
11732 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
11735 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
11736 // amount is a constant. Takes immediate version of shift as input.
11737 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
11738 SDValue SrcOp, uint64_t ShiftAmt,
11739 SelectionDAG &DAG) {
11740 MVT ElementType = VT.getVectorElementType();
11742 // Fold this packed shift into its first operand if ShiftAmt is 0.
11746 // Check for ShiftAmt >= element width
11747 if (ShiftAmt >= ElementType.getSizeInBits()) {
11748 if (Opc == X86ISD::VSRAI)
11749 ShiftAmt = ElementType.getSizeInBits() - 1;
11751 return DAG.getConstant(0, VT);
11754 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
11755 && "Unknown target vector shift-by-constant node");
11757 // Fold this packed vector shift into a build vector if SrcOp is a
11758 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
11759 if (VT == SrcOp.getSimpleValueType() &&
11760 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
11761 SmallVector<SDValue, 8> Elts;
11762 unsigned NumElts = SrcOp->getNumOperands();
11763 ConstantSDNode *ND;
11766 default: llvm_unreachable(nullptr);
11767 case X86ISD::VSHLI:
11768 for (unsigned i=0; i!=NumElts; ++i) {
11769 SDValue CurrentOp = SrcOp->getOperand(i);
11770 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11771 Elts.push_back(CurrentOp);
11774 ND = cast<ConstantSDNode>(CurrentOp);
11775 const APInt &C = ND->getAPIntValue();
11776 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
11779 case X86ISD::VSRLI:
11780 for (unsigned i=0; i!=NumElts; ++i) {
11781 SDValue CurrentOp = SrcOp->getOperand(i);
11782 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11783 Elts.push_back(CurrentOp);
11786 ND = cast<ConstantSDNode>(CurrentOp);
11787 const APInt &C = ND->getAPIntValue();
11788 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
11791 case X86ISD::VSRAI:
11792 for (unsigned i=0; i!=NumElts; ++i) {
11793 SDValue CurrentOp = SrcOp->getOperand(i);
11794 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11795 Elts.push_back(CurrentOp);
11798 ND = cast<ConstantSDNode>(CurrentOp);
11799 const APInt &C = ND->getAPIntValue();
11800 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
11805 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
11808 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
11811 // getTargetVShiftNode - Handle vector element shifts where the shift amount
11812 // may or may not be a constant. Takes immediate version of shift as input.
11813 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
11814 SDValue SrcOp, SDValue ShAmt,
11815 SelectionDAG &DAG) {
11816 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11818 // Catch shift-by-constant.
11819 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11820 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11821 CShAmt->getZExtValue(), DAG);
11823 // Change opcode to non-immediate version
11825 default: llvm_unreachable("Unknown target vector shift node");
11826 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11827 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11828 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11831 // Need to build a vector containing shift amount
11832 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11835 ShOps[1] = DAG.getConstant(0, MVT::i32);
11836 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11837 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
11839 // The return type has to be a 128-bit type with the same element
11840 // type as the input type.
11841 MVT EltVT = VT.getVectorElementType();
11842 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11844 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11845 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11848 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11850 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11852 default: return SDValue(); // Don't custom lower most intrinsics.
11853 // Comparison intrinsics.
11854 case Intrinsic::x86_sse_comieq_ss:
11855 case Intrinsic::x86_sse_comilt_ss:
11856 case Intrinsic::x86_sse_comile_ss:
11857 case Intrinsic::x86_sse_comigt_ss:
11858 case Intrinsic::x86_sse_comige_ss:
11859 case Intrinsic::x86_sse_comineq_ss:
11860 case Intrinsic::x86_sse_ucomieq_ss:
11861 case Intrinsic::x86_sse_ucomilt_ss:
11862 case Intrinsic::x86_sse_ucomile_ss:
11863 case Intrinsic::x86_sse_ucomigt_ss:
11864 case Intrinsic::x86_sse_ucomige_ss:
11865 case Intrinsic::x86_sse_ucomineq_ss:
11866 case Intrinsic::x86_sse2_comieq_sd:
11867 case Intrinsic::x86_sse2_comilt_sd:
11868 case Intrinsic::x86_sse2_comile_sd:
11869 case Intrinsic::x86_sse2_comigt_sd:
11870 case Intrinsic::x86_sse2_comige_sd:
11871 case Intrinsic::x86_sse2_comineq_sd:
11872 case Intrinsic::x86_sse2_ucomieq_sd:
11873 case Intrinsic::x86_sse2_ucomilt_sd:
11874 case Intrinsic::x86_sse2_ucomile_sd:
11875 case Intrinsic::x86_sse2_ucomigt_sd:
11876 case Intrinsic::x86_sse2_ucomige_sd:
11877 case Intrinsic::x86_sse2_ucomineq_sd: {
11881 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11882 case Intrinsic::x86_sse_comieq_ss:
11883 case Intrinsic::x86_sse2_comieq_sd:
11884 Opc = X86ISD::COMI;
11887 case Intrinsic::x86_sse_comilt_ss:
11888 case Intrinsic::x86_sse2_comilt_sd:
11889 Opc = X86ISD::COMI;
11892 case Intrinsic::x86_sse_comile_ss:
11893 case Intrinsic::x86_sse2_comile_sd:
11894 Opc = X86ISD::COMI;
11897 case Intrinsic::x86_sse_comigt_ss:
11898 case Intrinsic::x86_sse2_comigt_sd:
11899 Opc = X86ISD::COMI;
11902 case Intrinsic::x86_sse_comige_ss:
11903 case Intrinsic::x86_sse2_comige_sd:
11904 Opc = X86ISD::COMI;
11907 case Intrinsic::x86_sse_comineq_ss:
11908 case Intrinsic::x86_sse2_comineq_sd:
11909 Opc = X86ISD::COMI;
11912 case Intrinsic::x86_sse_ucomieq_ss:
11913 case Intrinsic::x86_sse2_ucomieq_sd:
11914 Opc = X86ISD::UCOMI;
11917 case Intrinsic::x86_sse_ucomilt_ss:
11918 case Intrinsic::x86_sse2_ucomilt_sd:
11919 Opc = X86ISD::UCOMI;
11922 case Intrinsic::x86_sse_ucomile_ss:
11923 case Intrinsic::x86_sse2_ucomile_sd:
11924 Opc = X86ISD::UCOMI;
11927 case Intrinsic::x86_sse_ucomigt_ss:
11928 case Intrinsic::x86_sse2_ucomigt_sd:
11929 Opc = X86ISD::UCOMI;
11932 case Intrinsic::x86_sse_ucomige_ss:
11933 case Intrinsic::x86_sse2_ucomige_sd:
11934 Opc = X86ISD::UCOMI;
11937 case Intrinsic::x86_sse_ucomineq_ss:
11938 case Intrinsic::x86_sse2_ucomineq_sd:
11939 Opc = X86ISD::UCOMI;
11944 SDValue LHS = Op.getOperand(1);
11945 SDValue RHS = Op.getOperand(2);
11946 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11947 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11948 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11949 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11950 DAG.getConstant(X86CC, MVT::i8), Cond);
11951 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11954 // Arithmetic intrinsics.
11955 case Intrinsic::x86_sse2_pmulu_dq:
11956 case Intrinsic::x86_avx2_pmulu_dq:
11957 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11958 Op.getOperand(1), Op.getOperand(2));
11960 case Intrinsic::x86_sse41_pmuldq:
11961 case Intrinsic::x86_avx2_pmul_dq:
11962 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
11963 Op.getOperand(1), Op.getOperand(2));
11965 case Intrinsic::x86_sse2_pmulhu_w:
11966 case Intrinsic::x86_avx2_pmulhu_w:
11967 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
11968 Op.getOperand(1), Op.getOperand(2));
11970 case Intrinsic::x86_sse2_pmulh_w:
11971 case Intrinsic::x86_avx2_pmulh_w:
11972 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
11973 Op.getOperand(1), Op.getOperand(2));
11975 // SSE2/AVX2 sub with unsigned saturation intrinsics
11976 case Intrinsic::x86_sse2_psubus_b:
11977 case Intrinsic::x86_sse2_psubus_w:
11978 case Intrinsic::x86_avx2_psubus_b:
11979 case Intrinsic::x86_avx2_psubus_w:
11980 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11981 Op.getOperand(1), Op.getOperand(2));
11983 // SSE3/AVX horizontal add/sub intrinsics
11984 case Intrinsic::x86_sse3_hadd_ps:
11985 case Intrinsic::x86_sse3_hadd_pd:
11986 case Intrinsic::x86_avx_hadd_ps_256:
11987 case Intrinsic::x86_avx_hadd_pd_256:
11988 case Intrinsic::x86_sse3_hsub_ps:
11989 case Intrinsic::x86_sse3_hsub_pd:
11990 case Intrinsic::x86_avx_hsub_ps_256:
11991 case Intrinsic::x86_avx_hsub_pd_256:
11992 case Intrinsic::x86_ssse3_phadd_w_128:
11993 case Intrinsic::x86_ssse3_phadd_d_128:
11994 case Intrinsic::x86_avx2_phadd_w:
11995 case Intrinsic::x86_avx2_phadd_d:
11996 case Intrinsic::x86_ssse3_phsub_w_128:
11997 case Intrinsic::x86_ssse3_phsub_d_128:
11998 case Intrinsic::x86_avx2_phsub_w:
11999 case Intrinsic::x86_avx2_phsub_d: {
12002 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12003 case Intrinsic::x86_sse3_hadd_ps:
12004 case Intrinsic::x86_sse3_hadd_pd:
12005 case Intrinsic::x86_avx_hadd_ps_256:
12006 case Intrinsic::x86_avx_hadd_pd_256:
12007 Opcode = X86ISD::FHADD;
12009 case Intrinsic::x86_sse3_hsub_ps:
12010 case Intrinsic::x86_sse3_hsub_pd:
12011 case Intrinsic::x86_avx_hsub_ps_256:
12012 case Intrinsic::x86_avx_hsub_pd_256:
12013 Opcode = X86ISD::FHSUB;
12015 case Intrinsic::x86_ssse3_phadd_w_128:
12016 case Intrinsic::x86_ssse3_phadd_d_128:
12017 case Intrinsic::x86_avx2_phadd_w:
12018 case Intrinsic::x86_avx2_phadd_d:
12019 Opcode = X86ISD::HADD;
12021 case Intrinsic::x86_ssse3_phsub_w_128:
12022 case Intrinsic::x86_ssse3_phsub_d_128:
12023 case Intrinsic::x86_avx2_phsub_w:
12024 case Intrinsic::x86_avx2_phsub_d:
12025 Opcode = X86ISD::HSUB;
12028 return DAG.getNode(Opcode, dl, Op.getValueType(),
12029 Op.getOperand(1), Op.getOperand(2));
12032 // SSE2/SSE41/AVX2 integer max/min intrinsics.
12033 case Intrinsic::x86_sse2_pmaxu_b:
12034 case Intrinsic::x86_sse41_pmaxuw:
12035 case Intrinsic::x86_sse41_pmaxud:
12036 case Intrinsic::x86_avx2_pmaxu_b:
12037 case Intrinsic::x86_avx2_pmaxu_w:
12038 case Intrinsic::x86_avx2_pmaxu_d:
12039 case Intrinsic::x86_sse2_pminu_b:
12040 case Intrinsic::x86_sse41_pminuw:
12041 case Intrinsic::x86_sse41_pminud:
12042 case Intrinsic::x86_avx2_pminu_b:
12043 case Intrinsic::x86_avx2_pminu_w:
12044 case Intrinsic::x86_avx2_pminu_d:
12045 case Intrinsic::x86_sse41_pmaxsb:
12046 case Intrinsic::x86_sse2_pmaxs_w:
12047 case Intrinsic::x86_sse41_pmaxsd:
12048 case Intrinsic::x86_avx2_pmaxs_b:
12049 case Intrinsic::x86_avx2_pmaxs_w:
12050 case Intrinsic::x86_avx2_pmaxs_d:
12051 case Intrinsic::x86_sse41_pminsb:
12052 case Intrinsic::x86_sse2_pmins_w:
12053 case Intrinsic::x86_sse41_pminsd:
12054 case Intrinsic::x86_avx2_pmins_b:
12055 case Intrinsic::x86_avx2_pmins_w:
12056 case Intrinsic::x86_avx2_pmins_d: {
12059 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12060 case Intrinsic::x86_sse2_pmaxu_b:
12061 case Intrinsic::x86_sse41_pmaxuw:
12062 case Intrinsic::x86_sse41_pmaxud:
12063 case Intrinsic::x86_avx2_pmaxu_b:
12064 case Intrinsic::x86_avx2_pmaxu_w:
12065 case Intrinsic::x86_avx2_pmaxu_d:
12066 Opcode = X86ISD::UMAX;
12068 case Intrinsic::x86_sse2_pminu_b:
12069 case Intrinsic::x86_sse41_pminuw:
12070 case Intrinsic::x86_sse41_pminud:
12071 case Intrinsic::x86_avx2_pminu_b:
12072 case Intrinsic::x86_avx2_pminu_w:
12073 case Intrinsic::x86_avx2_pminu_d:
12074 Opcode = X86ISD::UMIN;
12076 case Intrinsic::x86_sse41_pmaxsb:
12077 case Intrinsic::x86_sse2_pmaxs_w:
12078 case Intrinsic::x86_sse41_pmaxsd:
12079 case Intrinsic::x86_avx2_pmaxs_b:
12080 case Intrinsic::x86_avx2_pmaxs_w:
12081 case Intrinsic::x86_avx2_pmaxs_d:
12082 Opcode = X86ISD::SMAX;
12084 case Intrinsic::x86_sse41_pminsb:
12085 case Intrinsic::x86_sse2_pmins_w:
12086 case Intrinsic::x86_sse41_pminsd:
12087 case Intrinsic::x86_avx2_pmins_b:
12088 case Intrinsic::x86_avx2_pmins_w:
12089 case Intrinsic::x86_avx2_pmins_d:
12090 Opcode = X86ISD::SMIN;
12093 return DAG.getNode(Opcode, dl, Op.getValueType(),
12094 Op.getOperand(1), Op.getOperand(2));
12097 // SSE/SSE2/AVX floating point max/min intrinsics.
12098 case Intrinsic::x86_sse_max_ps:
12099 case Intrinsic::x86_sse2_max_pd:
12100 case Intrinsic::x86_avx_max_ps_256:
12101 case Intrinsic::x86_avx_max_pd_256:
12102 case Intrinsic::x86_sse_min_ps:
12103 case Intrinsic::x86_sse2_min_pd:
12104 case Intrinsic::x86_avx_min_ps_256:
12105 case Intrinsic::x86_avx_min_pd_256: {
12108 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12109 case Intrinsic::x86_sse_max_ps:
12110 case Intrinsic::x86_sse2_max_pd:
12111 case Intrinsic::x86_avx_max_ps_256:
12112 case Intrinsic::x86_avx_max_pd_256:
12113 Opcode = X86ISD::FMAX;
12115 case Intrinsic::x86_sse_min_ps:
12116 case Intrinsic::x86_sse2_min_pd:
12117 case Intrinsic::x86_avx_min_ps_256:
12118 case Intrinsic::x86_avx_min_pd_256:
12119 Opcode = X86ISD::FMIN;
12122 return DAG.getNode(Opcode, dl, Op.getValueType(),
12123 Op.getOperand(1), Op.getOperand(2));
12126 // AVX2 variable shift intrinsics
12127 case Intrinsic::x86_avx2_psllv_d:
12128 case Intrinsic::x86_avx2_psllv_q:
12129 case Intrinsic::x86_avx2_psllv_d_256:
12130 case Intrinsic::x86_avx2_psllv_q_256:
12131 case Intrinsic::x86_avx2_psrlv_d:
12132 case Intrinsic::x86_avx2_psrlv_q:
12133 case Intrinsic::x86_avx2_psrlv_d_256:
12134 case Intrinsic::x86_avx2_psrlv_q_256:
12135 case Intrinsic::x86_avx2_psrav_d:
12136 case Intrinsic::x86_avx2_psrav_d_256: {
12139 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12140 case Intrinsic::x86_avx2_psllv_d:
12141 case Intrinsic::x86_avx2_psllv_q:
12142 case Intrinsic::x86_avx2_psllv_d_256:
12143 case Intrinsic::x86_avx2_psllv_q_256:
12146 case Intrinsic::x86_avx2_psrlv_d:
12147 case Intrinsic::x86_avx2_psrlv_q:
12148 case Intrinsic::x86_avx2_psrlv_d_256:
12149 case Intrinsic::x86_avx2_psrlv_q_256:
12152 case Intrinsic::x86_avx2_psrav_d:
12153 case Intrinsic::x86_avx2_psrav_d_256:
12157 return DAG.getNode(Opcode, dl, Op.getValueType(),
12158 Op.getOperand(1), Op.getOperand(2));
12161 case Intrinsic::x86_ssse3_pshuf_b_128:
12162 case Intrinsic::x86_avx2_pshuf_b:
12163 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
12164 Op.getOperand(1), Op.getOperand(2));
12166 case Intrinsic::x86_ssse3_psign_b_128:
12167 case Intrinsic::x86_ssse3_psign_w_128:
12168 case Intrinsic::x86_ssse3_psign_d_128:
12169 case Intrinsic::x86_avx2_psign_b:
12170 case Intrinsic::x86_avx2_psign_w:
12171 case Intrinsic::x86_avx2_psign_d:
12172 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
12173 Op.getOperand(1), Op.getOperand(2));
12175 case Intrinsic::x86_sse41_insertps:
12176 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
12177 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
12179 case Intrinsic::x86_avx_vperm2f128_ps_256:
12180 case Intrinsic::x86_avx_vperm2f128_pd_256:
12181 case Intrinsic::x86_avx_vperm2f128_si_256:
12182 case Intrinsic::x86_avx2_vperm2i128:
12183 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
12184 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
12186 case Intrinsic::x86_avx2_permd:
12187 case Intrinsic::x86_avx2_permps:
12188 // Operands intentionally swapped. Mask is last operand to intrinsic,
12189 // but second operand for node/instruction.
12190 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
12191 Op.getOperand(2), Op.getOperand(1));
12193 case Intrinsic::x86_sse_sqrt_ps:
12194 case Intrinsic::x86_sse2_sqrt_pd:
12195 case Intrinsic::x86_avx_sqrt_ps_256:
12196 case Intrinsic::x86_avx_sqrt_pd_256:
12197 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
12199 // ptest and testp intrinsics. The intrinsic these come from are designed to
12200 // return an integer value, not just an instruction so lower it to the ptest
12201 // or testp pattern and a setcc for the result.
12202 case Intrinsic::x86_sse41_ptestz:
12203 case Intrinsic::x86_sse41_ptestc:
12204 case Intrinsic::x86_sse41_ptestnzc:
12205 case Intrinsic::x86_avx_ptestz_256:
12206 case Intrinsic::x86_avx_ptestc_256:
12207 case Intrinsic::x86_avx_ptestnzc_256:
12208 case Intrinsic::x86_avx_vtestz_ps:
12209 case Intrinsic::x86_avx_vtestc_ps:
12210 case Intrinsic::x86_avx_vtestnzc_ps:
12211 case Intrinsic::x86_avx_vtestz_pd:
12212 case Intrinsic::x86_avx_vtestc_pd:
12213 case Intrinsic::x86_avx_vtestnzc_pd:
12214 case Intrinsic::x86_avx_vtestz_ps_256:
12215 case Intrinsic::x86_avx_vtestc_ps_256:
12216 case Intrinsic::x86_avx_vtestnzc_ps_256:
12217 case Intrinsic::x86_avx_vtestz_pd_256:
12218 case Intrinsic::x86_avx_vtestc_pd_256:
12219 case Intrinsic::x86_avx_vtestnzc_pd_256: {
12220 bool IsTestPacked = false;
12223 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
12224 case Intrinsic::x86_avx_vtestz_ps:
12225 case Intrinsic::x86_avx_vtestz_pd:
12226 case Intrinsic::x86_avx_vtestz_ps_256:
12227 case Intrinsic::x86_avx_vtestz_pd_256:
12228 IsTestPacked = true; // Fallthrough
12229 case Intrinsic::x86_sse41_ptestz:
12230 case Intrinsic::x86_avx_ptestz_256:
12232 X86CC = X86::COND_E;
12234 case Intrinsic::x86_avx_vtestc_ps:
12235 case Intrinsic::x86_avx_vtestc_pd:
12236 case Intrinsic::x86_avx_vtestc_ps_256:
12237 case Intrinsic::x86_avx_vtestc_pd_256:
12238 IsTestPacked = true; // Fallthrough
12239 case Intrinsic::x86_sse41_ptestc:
12240 case Intrinsic::x86_avx_ptestc_256:
12242 X86CC = X86::COND_B;
12244 case Intrinsic::x86_avx_vtestnzc_ps:
12245 case Intrinsic::x86_avx_vtestnzc_pd:
12246 case Intrinsic::x86_avx_vtestnzc_ps_256:
12247 case Intrinsic::x86_avx_vtestnzc_pd_256:
12248 IsTestPacked = true; // Fallthrough
12249 case Intrinsic::x86_sse41_ptestnzc:
12250 case Intrinsic::x86_avx_ptestnzc_256:
12252 X86CC = X86::COND_A;
12256 SDValue LHS = Op.getOperand(1);
12257 SDValue RHS = Op.getOperand(2);
12258 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
12259 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
12260 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
12261 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
12262 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
12264 case Intrinsic::x86_avx512_kortestz_w:
12265 case Intrinsic::x86_avx512_kortestc_w: {
12266 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
12267 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
12268 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
12269 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
12270 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
12271 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
12272 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
12275 // SSE/AVX shift intrinsics
12276 case Intrinsic::x86_sse2_psll_w:
12277 case Intrinsic::x86_sse2_psll_d:
12278 case Intrinsic::x86_sse2_psll_q:
12279 case Intrinsic::x86_avx2_psll_w:
12280 case Intrinsic::x86_avx2_psll_d:
12281 case Intrinsic::x86_avx2_psll_q:
12282 case Intrinsic::x86_sse2_psrl_w:
12283 case Intrinsic::x86_sse2_psrl_d:
12284 case Intrinsic::x86_sse2_psrl_q:
12285 case Intrinsic::x86_avx2_psrl_w:
12286 case Intrinsic::x86_avx2_psrl_d:
12287 case Intrinsic::x86_avx2_psrl_q:
12288 case Intrinsic::x86_sse2_psra_w:
12289 case Intrinsic::x86_sse2_psra_d:
12290 case Intrinsic::x86_avx2_psra_w:
12291 case Intrinsic::x86_avx2_psra_d: {
12294 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12295 case Intrinsic::x86_sse2_psll_w:
12296 case Intrinsic::x86_sse2_psll_d:
12297 case Intrinsic::x86_sse2_psll_q:
12298 case Intrinsic::x86_avx2_psll_w:
12299 case Intrinsic::x86_avx2_psll_d:
12300 case Intrinsic::x86_avx2_psll_q:
12301 Opcode = X86ISD::VSHL;
12303 case Intrinsic::x86_sse2_psrl_w:
12304 case Intrinsic::x86_sse2_psrl_d:
12305 case Intrinsic::x86_sse2_psrl_q:
12306 case Intrinsic::x86_avx2_psrl_w:
12307 case Intrinsic::x86_avx2_psrl_d:
12308 case Intrinsic::x86_avx2_psrl_q:
12309 Opcode = X86ISD::VSRL;
12311 case Intrinsic::x86_sse2_psra_w:
12312 case Intrinsic::x86_sse2_psra_d:
12313 case Intrinsic::x86_avx2_psra_w:
12314 case Intrinsic::x86_avx2_psra_d:
12315 Opcode = X86ISD::VSRA;
12318 return DAG.getNode(Opcode, dl, Op.getValueType(),
12319 Op.getOperand(1), Op.getOperand(2));
12322 // SSE/AVX immediate shift intrinsics
12323 case Intrinsic::x86_sse2_pslli_w:
12324 case Intrinsic::x86_sse2_pslli_d:
12325 case Intrinsic::x86_sse2_pslli_q:
12326 case Intrinsic::x86_avx2_pslli_w:
12327 case Intrinsic::x86_avx2_pslli_d:
12328 case Intrinsic::x86_avx2_pslli_q:
12329 case Intrinsic::x86_sse2_psrli_w:
12330 case Intrinsic::x86_sse2_psrli_d:
12331 case Intrinsic::x86_sse2_psrli_q:
12332 case Intrinsic::x86_avx2_psrli_w:
12333 case Intrinsic::x86_avx2_psrli_d:
12334 case Intrinsic::x86_avx2_psrli_q:
12335 case Intrinsic::x86_sse2_psrai_w:
12336 case Intrinsic::x86_sse2_psrai_d:
12337 case Intrinsic::x86_avx2_psrai_w:
12338 case Intrinsic::x86_avx2_psrai_d: {
12341 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12342 case Intrinsic::x86_sse2_pslli_w:
12343 case Intrinsic::x86_sse2_pslli_d:
12344 case Intrinsic::x86_sse2_pslli_q:
12345 case Intrinsic::x86_avx2_pslli_w:
12346 case Intrinsic::x86_avx2_pslli_d:
12347 case Intrinsic::x86_avx2_pslli_q:
12348 Opcode = X86ISD::VSHLI;
12350 case Intrinsic::x86_sse2_psrli_w:
12351 case Intrinsic::x86_sse2_psrli_d:
12352 case Intrinsic::x86_sse2_psrli_q:
12353 case Intrinsic::x86_avx2_psrli_w:
12354 case Intrinsic::x86_avx2_psrli_d:
12355 case Intrinsic::x86_avx2_psrli_q:
12356 Opcode = X86ISD::VSRLI;
12358 case Intrinsic::x86_sse2_psrai_w:
12359 case Intrinsic::x86_sse2_psrai_d:
12360 case Intrinsic::x86_avx2_psrai_w:
12361 case Intrinsic::x86_avx2_psrai_d:
12362 Opcode = X86ISD::VSRAI;
12365 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
12366 Op.getOperand(1), Op.getOperand(2), DAG);
12369 case Intrinsic::x86_sse42_pcmpistria128:
12370 case Intrinsic::x86_sse42_pcmpestria128:
12371 case Intrinsic::x86_sse42_pcmpistric128:
12372 case Intrinsic::x86_sse42_pcmpestric128:
12373 case Intrinsic::x86_sse42_pcmpistrio128:
12374 case Intrinsic::x86_sse42_pcmpestrio128:
12375 case Intrinsic::x86_sse42_pcmpistris128:
12376 case Intrinsic::x86_sse42_pcmpestris128:
12377 case Intrinsic::x86_sse42_pcmpistriz128:
12378 case Intrinsic::x86_sse42_pcmpestriz128: {
12382 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12383 case Intrinsic::x86_sse42_pcmpistria128:
12384 Opcode = X86ISD::PCMPISTRI;
12385 X86CC = X86::COND_A;
12387 case Intrinsic::x86_sse42_pcmpestria128:
12388 Opcode = X86ISD::PCMPESTRI;
12389 X86CC = X86::COND_A;
12391 case Intrinsic::x86_sse42_pcmpistric128:
12392 Opcode = X86ISD::PCMPISTRI;
12393 X86CC = X86::COND_B;
12395 case Intrinsic::x86_sse42_pcmpestric128:
12396 Opcode = X86ISD::PCMPESTRI;
12397 X86CC = X86::COND_B;
12399 case Intrinsic::x86_sse42_pcmpistrio128:
12400 Opcode = X86ISD::PCMPISTRI;
12401 X86CC = X86::COND_O;
12403 case Intrinsic::x86_sse42_pcmpestrio128:
12404 Opcode = X86ISD::PCMPESTRI;
12405 X86CC = X86::COND_O;
12407 case Intrinsic::x86_sse42_pcmpistris128:
12408 Opcode = X86ISD::PCMPISTRI;
12409 X86CC = X86::COND_S;
12411 case Intrinsic::x86_sse42_pcmpestris128:
12412 Opcode = X86ISD::PCMPESTRI;
12413 X86CC = X86::COND_S;
12415 case Intrinsic::x86_sse42_pcmpistriz128:
12416 Opcode = X86ISD::PCMPISTRI;
12417 X86CC = X86::COND_E;
12419 case Intrinsic::x86_sse42_pcmpestriz128:
12420 Opcode = X86ISD::PCMPESTRI;
12421 X86CC = X86::COND_E;
12424 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
12425 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12426 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
12427 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12428 DAG.getConstant(X86CC, MVT::i8),
12429 SDValue(PCMP.getNode(), 1));
12430 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
12433 case Intrinsic::x86_sse42_pcmpistri128:
12434 case Intrinsic::x86_sse42_pcmpestri128: {
12436 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
12437 Opcode = X86ISD::PCMPISTRI;
12439 Opcode = X86ISD::PCMPESTRI;
12441 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
12442 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12443 return DAG.getNode(Opcode, dl, VTs, NewOps);
12445 case Intrinsic::x86_fma_vfmadd_ps:
12446 case Intrinsic::x86_fma_vfmadd_pd:
12447 case Intrinsic::x86_fma_vfmsub_ps:
12448 case Intrinsic::x86_fma_vfmsub_pd:
12449 case Intrinsic::x86_fma_vfnmadd_ps:
12450 case Intrinsic::x86_fma_vfnmadd_pd:
12451 case Intrinsic::x86_fma_vfnmsub_ps:
12452 case Intrinsic::x86_fma_vfnmsub_pd:
12453 case Intrinsic::x86_fma_vfmaddsub_ps:
12454 case Intrinsic::x86_fma_vfmaddsub_pd:
12455 case Intrinsic::x86_fma_vfmsubadd_ps:
12456 case Intrinsic::x86_fma_vfmsubadd_pd:
12457 case Intrinsic::x86_fma_vfmadd_ps_256:
12458 case Intrinsic::x86_fma_vfmadd_pd_256:
12459 case Intrinsic::x86_fma_vfmsub_ps_256:
12460 case Intrinsic::x86_fma_vfmsub_pd_256:
12461 case Intrinsic::x86_fma_vfnmadd_ps_256:
12462 case Intrinsic::x86_fma_vfnmadd_pd_256:
12463 case Intrinsic::x86_fma_vfnmsub_ps_256:
12464 case Intrinsic::x86_fma_vfnmsub_pd_256:
12465 case Intrinsic::x86_fma_vfmaddsub_ps_256:
12466 case Intrinsic::x86_fma_vfmaddsub_pd_256:
12467 case Intrinsic::x86_fma_vfmsubadd_ps_256:
12468 case Intrinsic::x86_fma_vfmsubadd_pd_256:
12469 case Intrinsic::x86_fma_vfmadd_ps_512:
12470 case Intrinsic::x86_fma_vfmadd_pd_512:
12471 case Intrinsic::x86_fma_vfmsub_ps_512:
12472 case Intrinsic::x86_fma_vfmsub_pd_512:
12473 case Intrinsic::x86_fma_vfnmadd_ps_512:
12474 case Intrinsic::x86_fma_vfnmadd_pd_512:
12475 case Intrinsic::x86_fma_vfnmsub_ps_512:
12476 case Intrinsic::x86_fma_vfnmsub_pd_512:
12477 case Intrinsic::x86_fma_vfmaddsub_ps_512:
12478 case Intrinsic::x86_fma_vfmaddsub_pd_512:
12479 case Intrinsic::x86_fma_vfmsubadd_ps_512:
12480 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
12483 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12484 case Intrinsic::x86_fma_vfmadd_ps:
12485 case Intrinsic::x86_fma_vfmadd_pd:
12486 case Intrinsic::x86_fma_vfmadd_ps_256:
12487 case Intrinsic::x86_fma_vfmadd_pd_256:
12488 case Intrinsic::x86_fma_vfmadd_ps_512:
12489 case Intrinsic::x86_fma_vfmadd_pd_512:
12490 Opc = X86ISD::FMADD;
12492 case Intrinsic::x86_fma_vfmsub_ps:
12493 case Intrinsic::x86_fma_vfmsub_pd:
12494 case Intrinsic::x86_fma_vfmsub_ps_256:
12495 case Intrinsic::x86_fma_vfmsub_pd_256:
12496 case Intrinsic::x86_fma_vfmsub_ps_512:
12497 case Intrinsic::x86_fma_vfmsub_pd_512:
12498 Opc = X86ISD::FMSUB;
12500 case Intrinsic::x86_fma_vfnmadd_ps:
12501 case Intrinsic::x86_fma_vfnmadd_pd:
12502 case Intrinsic::x86_fma_vfnmadd_ps_256:
12503 case Intrinsic::x86_fma_vfnmadd_pd_256:
12504 case Intrinsic::x86_fma_vfnmadd_ps_512:
12505 case Intrinsic::x86_fma_vfnmadd_pd_512:
12506 Opc = X86ISD::FNMADD;
12508 case Intrinsic::x86_fma_vfnmsub_ps:
12509 case Intrinsic::x86_fma_vfnmsub_pd:
12510 case Intrinsic::x86_fma_vfnmsub_ps_256:
12511 case Intrinsic::x86_fma_vfnmsub_pd_256:
12512 case Intrinsic::x86_fma_vfnmsub_ps_512:
12513 case Intrinsic::x86_fma_vfnmsub_pd_512:
12514 Opc = X86ISD::FNMSUB;
12516 case Intrinsic::x86_fma_vfmaddsub_ps:
12517 case Intrinsic::x86_fma_vfmaddsub_pd:
12518 case Intrinsic::x86_fma_vfmaddsub_ps_256:
12519 case Intrinsic::x86_fma_vfmaddsub_pd_256:
12520 case Intrinsic::x86_fma_vfmaddsub_ps_512:
12521 case Intrinsic::x86_fma_vfmaddsub_pd_512:
12522 Opc = X86ISD::FMADDSUB;
12524 case Intrinsic::x86_fma_vfmsubadd_ps:
12525 case Intrinsic::x86_fma_vfmsubadd_pd:
12526 case Intrinsic::x86_fma_vfmsubadd_ps_256:
12527 case Intrinsic::x86_fma_vfmsubadd_pd_256:
12528 case Intrinsic::x86_fma_vfmsubadd_ps_512:
12529 case Intrinsic::x86_fma_vfmsubadd_pd_512:
12530 Opc = X86ISD::FMSUBADD;
12534 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
12535 Op.getOperand(2), Op.getOperand(3));
12540 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12541 SDValue Src, SDValue Mask, SDValue Base,
12542 SDValue Index, SDValue ScaleOp, SDValue Chain,
12543 const X86Subtarget * Subtarget) {
12545 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12546 assert(C && "Invalid scale type");
12547 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12548 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12549 Index.getSimpleValueType().getVectorNumElements());
12551 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
12553 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
12555 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12556 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
12557 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12558 SDValue Segment = DAG.getRegister(0, MVT::i32);
12559 if (Src.getOpcode() == ISD::UNDEF)
12560 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
12561 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
12562 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12563 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
12564 return DAG.getMergeValues(RetOps, dl);
12567 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12568 SDValue Src, SDValue Mask, SDValue Base,
12569 SDValue Index, SDValue ScaleOp, SDValue Chain) {
12571 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12572 assert(C && "Invalid scale type");
12573 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12574 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12575 SDValue Segment = DAG.getRegister(0, MVT::i32);
12576 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12577 Index.getSimpleValueType().getVectorNumElements());
12579 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
12581 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
12583 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12584 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
12585 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
12586 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12587 return SDValue(Res, 1);
12590 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12591 SDValue Mask, SDValue Base, SDValue Index,
12592 SDValue ScaleOp, SDValue Chain) {
12594 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12595 assert(C && "Invalid scale type");
12596 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12597 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12598 SDValue Segment = DAG.getRegister(0, MVT::i32);
12600 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
12602 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
12604 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
12606 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12607 //SDVTList VTs = DAG.getVTList(MVT::Other);
12608 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
12609 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
12610 return SDValue(Res, 0);
12613 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
12614 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
12615 // also used to custom lower READCYCLECOUNTER nodes.
12616 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
12617 SelectionDAG &DAG, const X86Subtarget *Subtarget,
12618 SmallVectorImpl<SDValue> &Results) {
12619 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12620 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
12623 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
12624 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
12625 // and the EAX register is loaded with the low-order 32 bits.
12626 if (Subtarget->is64Bit()) {
12627 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
12628 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
12631 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
12632 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
12635 SDValue Chain = HI.getValue(1);
12637 if (Opcode == X86ISD::RDTSCP_DAG) {
12638 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
12640 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
12641 // the ECX register. Add 'ecx' explicitly to the chain.
12642 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
12644 // Explicitly store the content of ECX at the location passed in input
12645 // to the 'rdtscp' intrinsic.
12646 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
12647 MachinePointerInfo(), false, false, 0);
12650 if (Subtarget->is64Bit()) {
12651 // The EDX register is loaded with the high-order 32 bits of the MSR, and
12652 // the EAX register is loaded with the low-order 32 bits.
12653 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
12654 DAG.getConstant(32, MVT::i8));
12655 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
12656 Results.push_back(Chain);
12660 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
12661 SDValue Ops[] = { LO, HI };
12662 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
12663 Results.push_back(Pair);
12664 Results.push_back(Chain);
12667 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
12668 SelectionDAG &DAG) {
12669 SmallVector<SDValue, 2> Results;
12671 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
12673 return DAG.getMergeValues(Results, DL);
12676 enum IntrinsicType {
12677 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDTSC, XTEST
12680 struct IntrinsicData {
12681 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
12682 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
12683 IntrinsicType Type;
12688 std::map < unsigned, IntrinsicData> IntrMap;
12689 static void InitIntinsicsMap() {
12690 static bool Initialized = false;
12693 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
12694 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
12695 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
12696 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
12697 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
12698 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
12699 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
12700 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
12701 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
12702 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
12703 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
12704 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
12705 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
12706 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
12707 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
12708 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
12709 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
12710 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
12712 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
12713 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
12714 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
12715 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
12716 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
12717 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
12718 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
12719 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
12720 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
12721 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
12722 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
12723 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
12724 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
12725 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
12726 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
12727 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
12729 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
12730 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
12731 X86::VGATHERPF1QPSm)));
12732 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
12733 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
12734 X86::VGATHERPF1QPDm)));
12735 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
12736 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
12737 X86::VGATHERPF1DPDm)));
12738 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
12739 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
12740 X86::VGATHERPF1DPSm)));
12741 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
12742 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
12743 X86::VSCATTERPF1QPSm)));
12744 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
12745 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
12746 X86::VSCATTERPF1QPDm)));
12747 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
12748 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
12749 X86::VSCATTERPF1DPDm)));
12750 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
12751 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
12752 X86::VSCATTERPF1DPSm)));
12753 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
12754 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
12755 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
12756 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
12757 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
12758 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
12759 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
12760 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
12761 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
12762 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
12763 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
12764 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
12765 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
12766 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
12767 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
12768 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
12769 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
12770 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
12771 Initialized = true;
12774 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
12775 SelectionDAG &DAG) {
12776 InitIntinsicsMap();
12777 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12778 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
12779 if (itr == IntrMap.end())
12783 IntrinsicData Intr = itr->second;
12784 switch(Intr.Type) {
12787 // Emit the node with the right value type.
12788 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
12789 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
12791 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
12792 // Otherwise return the value from Rand, which is always 0, casted to i32.
12793 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
12794 DAG.getConstant(1, Op->getValueType(1)),
12795 DAG.getConstant(X86::COND_B, MVT::i32),
12796 SDValue(Result.getNode(), 1) };
12797 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
12798 DAG.getVTList(Op->getValueType(1), MVT::Glue),
12801 // Return { result, isValid, chain }.
12802 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
12803 SDValue(Result.getNode(), 2));
12806 //gather(v1, mask, index, base, scale);
12807 SDValue Chain = Op.getOperand(0);
12808 SDValue Src = Op.getOperand(2);
12809 SDValue Base = Op.getOperand(3);
12810 SDValue Index = Op.getOperand(4);
12811 SDValue Mask = Op.getOperand(5);
12812 SDValue Scale = Op.getOperand(6);
12813 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
12817 //scatter(base, mask, index, v1, scale);
12818 SDValue Chain = Op.getOperand(0);
12819 SDValue Base = Op.getOperand(2);
12820 SDValue Mask = Op.getOperand(3);
12821 SDValue Index = Op.getOperand(4);
12822 SDValue Src = Op.getOperand(5);
12823 SDValue Scale = Op.getOperand(6);
12824 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
12827 SDValue Hint = Op.getOperand(6);
12829 if (dyn_cast<ConstantSDNode> (Hint) == 0 ||
12830 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
12831 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
12832 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
12833 SDValue Chain = Op.getOperand(0);
12834 SDValue Mask = Op.getOperand(2);
12835 SDValue Index = Op.getOperand(3);
12836 SDValue Base = Op.getOperand(4);
12837 SDValue Scale = Op.getOperand(5);
12838 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
12840 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
12842 SmallVector<SDValue, 2> Results;
12843 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
12844 return DAG.getMergeValues(Results, dl);
12846 // XTEST intrinsics.
12848 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
12849 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
12850 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12851 DAG.getConstant(X86::COND_NE, MVT::i8),
12853 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12854 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
12855 Ret, SDValue(InTrans.getNode(), 1));
12858 llvm_unreachable("Unknown Intrinsic Type");
12861 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12862 SelectionDAG &DAG) const {
12863 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12864 MFI->setReturnAddressIsTaken(true);
12866 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
12869 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12871 EVT PtrVT = getPointerTy();
12874 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12875 const X86RegisterInfo *RegInfo =
12876 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12877 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12878 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12879 DAG.getNode(ISD::ADD, dl, PtrVT,
12880 FrameAddr, Offset),
12881 MachinePointerInfo(), false, false, false, 0);
12884 // Just load the return address.
12885 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12886 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12887 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12890 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12891 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12892 MFI->setFrameAddressIsTaken(true);
12894 EVT VT = Op.getValueType();
12895 SDLoc dl(Op); // FIXME probably not meaningful
12896 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12897 const X86RegisterInfo *RegInfo =
12898 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12899 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12900 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12901 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12902 "Invalid Frame Register!");
12903 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12905 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12906 MachinePointerInfo(),
12907 false, false, false, 0);
12911 // FIXME? Maybe this could be a TableGen attribute on some registers and
12912 // this table could be generated automatically from RegInfo.
12913 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
12915 unsigned Reg = StringSwitch<unsigned>(RegName)
12916 .Case("esp", X86::ESP)
12917 .Case("rsp", X86::RSP)
12921 report_fatal_error("Invalid register name global variable");
12924 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12925 SelectionDAG &DAG) const {
12926 const X86RegisterInfo *RegInfo =
12927 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12928 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12931 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12932 SDValue Chain = Op.getOperand(0);
12933 SDValue Offset = Op.getOperand(1);
12934 SDValue Handler = Op.getOperand(2);
12937 EVT PtrVT = getPointerTy();
12938 const X86RegisterInfo *RegInfo =
12939 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12940 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12941 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12942 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12943 "Invalid Frame Register!");
12944 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12945 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12947 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12948 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12949 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12950 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12952 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12954 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12955 DAG.getRegister(StoreAddrReg, PtrVT));
12958 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12959 SelectionDAG &DAG) const {
12961 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12962 DAG.getVTList(MVT::i32, MVT::Other),
12963 Op.getOperand(0), Op.getOperand(1));
12966 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12967 SelectionDAG &DAG) const {
12969 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12970 Op.getOperand(0), Op.getOperand(1));
12973 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12974 return Op.getOperand(0);
12977 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12978 SelectionDAG &DAG) const {
12979 SDValue Root = Op.getOperand(0);
12980 SDValue Trmp = Op.getOperand(1); // trampoline
12981 SDValue FPtr = Op.getOperand(2); // nested function
12982 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12985 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12986 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12988 if (Subtarget->is64Bit()) {
12989 SDValue OutChains[6];
12991 // Large code-model.
12992 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12993 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12995 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12996 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12998 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
13000 // Load the pointer to the nested function into R11.
13001 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
13002 SDValue Addr = Trmp;
13003 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
13004 Addr, MachinePointerInfo(TrmpAddr),
13007 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
13008 DAG.getConstant(2, MVT::i64));
13009 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
13010 MachinePointerInfo(TrmpAddr, 2),
13013 // Load the 'nest' parameter value into R10.
13014 // R10 is specified in X86CallingConv.td
13015 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
13016 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
13017 DAG.getConstant(10, MVT::i64));
13018 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
13019 Addr, MachinePointerInfo(TrmpAddr, 10),
13022 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
13023 DAG.getConstant(12, MVT::i64));
13024 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
13025 MachinePointerInfo(TrmpAddr, 12),
13028 // Jump to the nested function.
13029 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
13030 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
13031 DAG.getConstant(20, MVT::i64));
13032 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
13033 Addr, MachinePointerInfo(TrmpAddr, 20),
13036 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
13037 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
13038 DAG.getConstant(22, MVT::i64));
13039 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
13040 MachinePointerInfo(TrmpAddr, 22),
13043 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
13045 const Function *Func =
13046 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
13047 CallingConv::ID CC = Func->getCallingConv();
13052 llvm_unreachable("Unsupported calling convention");
13053 case CallingConv::C:
13054 case CallingConv::X86_StdCall: {
13055 // Pass 'nest' parameter in ECX.
13056 // Must be kept in sync with X86CallingConv.td
13057 NestReg = X86::ECX;
13059 // Check that ECX wasn't needed by an 'inreg' parameter.
13060 FunctionType *FTy = Func->getFunctionType();
13061 const AttributeSet &Attrs = Func->getAttributes();
13063 if (!Attrs.isEmpty() && !Func->isVarArg()) {
13064 unsigned InRegCount = 0;
13067 for (FunctionType::param_iterator I = FTy->param_begin(),
13068 E = FTy->param_end(); I != E; ++I, ++Idx)
13069 if (Attrs.hasAttribute(Idx, Attribute::InReg))
13070 // FIXME: should only count parameters that are lowered to integers.
13071 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
13073 if (InRegCount > 2) {
13074 report_fatal_error("Nest register in use - reduce number of inreg"
13080 case CallingConv::X86_FastCall:
13081 case CallingConv::X86_ThisCall:
13082 case CallingConv::Fast:
13083 // Pass 'nest' parameter in EAX.
13084 // Must be kept in sync with X86CallingConv.td
13085 NestReg = X86::EAX;
13089 SDValue OutChains[4];
13090 SDValue Addr, Disp;
13092 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
13093 DAG.getConstant(10, MVT::i32));
13094 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
13096 // This is storing the opcode for MOV32ri.
13097 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
13098 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
13099 OutChains[0] = DAG.getStore(Root, dl,
13100 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
13101 Trmp, MachinePointerInfo(TrmpAddr),
13104 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
13105 DAG.getConstant(1, MVT::i32));
13106 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
13107 MachinePointerInfo(TrmpAddr, 1),
13110 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
13111 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
13112 DAG.getConstant(5, MVT::i32));
13113 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
13114 MachinePointerInfo(TrmpAddr, 5),
13117 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
13118 DAG.getConstant(6, MVT::i32));
13119 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
13120 MachinePointerInfo(TrmpAddr, 6),
13123 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
13127 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
13128 SelectionDAG &DAG) const {
13130 The rounding mode is in bits 11:10 of FPSR, and has the following
13132 00 Round to nearest
13137 FLT_ROUNDS, on the other hand, expects the following:
13144 To perform the conversion, we do:
13145 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
13148 MachineFunction &MF = DAG.getMachineFunction();
13149 const TargetMachine &TM = MF.getTarget();
13150 const TargetFrameLowering &TFI = *TM.getFrameLowering();
13151 unsigned StackAlignment = TFI.getStackAlignment();
13152 MVT VT = Op.getSimpleValueType();
13155 // Save FP Control Word to stack slot
13156 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
13157 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13159 MachineMemOperand *MMO =
13160 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13161 MachineMemOperand::MOStore, 2, 2);
13163 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
13164 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
13165 DAG.getVTList(MVT::Other),
13166 Ops, MVT::i16, MMO);
13168 // Load FP Control Word from stack slot
13169 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
13170 MachinePointerInfo(), false, false, false, 0);
13172 // Transform as necessary
13174 DAG.getNode(ISD::SRL, DL, MVT::i16,
13175 DAG.getNode(ISD::AND, DL, MVT::i16,
13176 CWD, DAG.getConstant(0x800, MVT::i16)),
13177 DAG.getConstant(11, MVT::i8));
13179 DAG.getNode(ISD::SRL, DL, MVT::i16,
13180 DAG.getNode(ISD::AND, DL, MVT::i16,
13181 CWD, DAG.getConstant(0x400, MVT::i16)),
13182 DAG.getConstant(9, MVT::i8));
13185 DAG.getNode(ISD::AND, DL, MVT::i16,
13186 DAG.getNode(ISD::ADD, DL, MVT::i16,
13187 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
13188 DAG.getConstant(1, MVT::i16)),
13189 DAG.getConstant(3, MVT::i16));
13191 return DAG.getNode((VT.getSizeInBits() < 16 ?
13192 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
13195 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
13196 MVT VT = Op.getSimpleValueType();
13198 unsigned NumBits = VT.getSizeInBits();
13201 Op = Op.getOperand(0);
13202 if (VT == MVT::i8) {
13203 // Zero extend to i32 since there is not an i8 bsr.
13205 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
13208 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
13209 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
13210 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
13212 // If src is zero (i.e. bsr sets ZF), returns NumBits.
13215 DAG.getConstant(NumBits+NumBits-1, OpVT),
13216 DAG.getConstant(X86::COND_E, MVT::i8),
13219 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
13221 // Finally xor with NumBits-1.
13222 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
13225 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
13229 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
13230 MVT VT = Op.getSimpleValueType();
13232 unsigned NumBits = VT.getSizeInBits();
13235 Op = Op.getOperand(0);
13236 if (VT == MVT::i8) {
13237 // Zero extend to i32 since there is not an i8 bsr.
13239 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
13242 // Issue a bsr (scan bits in reverse).
13243 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
13244 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
13246 // And xor with NumBits-1.
13247 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
13250 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
13254 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
13255 MVT VT = Op.getSimpleValueType();
13256 unsigned NumBits = VT.getSizeInBits();
13258 Op = Op.getOperand(0);
13260 // Issue a bsf (scan bits forward) which also sets EFLAGS.
13261 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13262 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
13264 // If src is zero (i.e. bsf sets ZF), returns NumBits.
13267 DAG.getConstant(NumBits, VT),
13268 DAG.getConstant(X86::COND_E, MVT::i8),
13271 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
13274 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
13275 // ones, and then concatenate the result back.
13276 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
13277 MVT VT = Op.getSimpleValueType();
13279 assert(VT.is256BitVector() && VT.isInteger() &&
13280 "Unsupported value type for operation");
13282 unsigned NumElems = VT.getVectorNumElements();
13285 // Extract the LHS vectors
13286 SDValue LHS = Op.getOperand(0);
13287 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13288 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13290 // Extract the RHS vectors
13291 SDValue RHS = Op.getOperand(1);
13292 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13293 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13295 MVT EltVT = VT.getVectorElementType();
13296 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13298 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13299 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
13300 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
13303 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
13304 assert(Op.getSimpleValueType().is256BitVector() &&
13305 Op.getSimpleValueType().isInteger() &&
13306 "Only handle AVX 256-bit vector integer operation");
13307 return Lower256IntArith(Op, DAG);
13310 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
13311 assert(Op.getSimpleValueType().is256BitVector() &&
13312 Op.getSimpleValueType().isInteger() &&
13313 "Only handle AVX 256-bit vector integer operation");
13314 return Lower256IntArith(Op, DAG);
13317 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
13318 SelectionDAG &DAG) {
13320 MVT VT = Op.getSimpleValueType();
13322 // Decompose 256-bit ops into smaller 128-bit ops.
13323 if (VT.is256BitVector() && !Subtarget->hasInt256())
13324 return Lower256IntArith(Op, DAG);
13326 SDValue A = Op.getOperand(0);
13327 SDValue B = Op.getOperand(1);
13329 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
13330 if (VT == MVT::v4i32) {
13331 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
13332 "Should not custom lower when pmuldq is available!");
13334 // Extract the odd parts.
13335 static const int UnpackMask[] = { 1, -1, 3, -1 };
13336 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
13337 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
13339 // Multiply the even parts.
13340 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
13341 // Now multiply odd parts.
13342 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
13344 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
13345 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
13347 // Merge the two vectors back together with a shuffle. This expands into 2
13349 static const int ShufMask[] = { 0, 4, 2, 6 };
13350 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
13353 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
13354 "Only know how to lower V2I64/V4I64/V8I64 multiply");
13356 // Ahi = psrlqi(a, 32);
13357 // Bhi = psrlqi(b, 32);
13359 // AloBlo = pmuludq(a, b);
13360 // AloBhi = pmuludq(a, Bhi);
13361 // AhiBlo = pmuludq(Ahi, b);
13363 // AloBhi = psllqi(AloBhi, 32);
13364 // AhiBlo = psllqi(AhiBlo, 32);
13365 // return AloBlo + AloBhi + AhiBlo;
13367 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
13368 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
13370 // Bit cast to 32-bit vectors for MULUDQ
13371 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
13372 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
13373 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
13374 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
13375 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
13376 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
13378 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
13379 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
13380 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
13382 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
13383 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
13385 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
13386 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
13389 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
13390 assert(Subtarget->isTargetWin64() && "Unexpected target");
13391 EVT VT = Op.getValueType();
13392 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
13393 "Unexpected return type for lowering");
13397 switch (Op->getOpcode()) {
13398 default: llvm_unreachable("Unexpected request for libcall!");
13399 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
13400 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
13401 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
13402 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
13403 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
13404 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
13408 SDValue InChain = DAG.getEntryNode();
13410 TargetLowering::ArgListTy Args;
13411 TargetLowering::ArgListEntry Entry;
13412 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
13413 EVT ArgVT = Op->getOperand(i).getValueType();
13414 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
13415 "Unexpected argument type for lowering");
13416 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
13417 Entry.Node = StackPtr;
13418 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
13420 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13421 Entry.Ty = PointerType::get(ArgTy,0);
13422 Entry.isSExt = false;
13423 Entry.isZExt = false;
13424 Args.push_back(Entry);
13427 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
13430 TargetLowering::CallLoweringInfo CLI(DAG);
13431 CLI.setDebugLoc(dl).setChain(InChain)
13432 .setCallee(getLibcallCallingConv(LC),
13433 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
13435 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
13437 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
13438 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
13441 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
13442 SelectionDAG &DAG) {
13443 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
13444 EVT VT = Op0.getValueType();
13447 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
13448 (VT == MVT::v8i32 && Subtarget->hasInt256()));
13450 // Get the high parts.
13451 const int Mask[] = {1, 2, 3, 4, 5, 6, 7, 8};
13452 SDValue Hi0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
13453 SDValue Hi1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
13455 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
13457 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
13458 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
13460 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
13461 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
13462 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
13463 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
13464 DAG.getNode(Opcode, dl, MulVT, Hi0, Hi1));
13466 // Shuffle it back into the right order.
13467 const int HighMask[] = {1, 5, 3, 7, 9, 13, 11, 15};
13468 SDValue Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
13469 const int LowMask[] = {0, 4, 2, 6, 8, 12, 10, 14};
13470 SDValue Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
13472 // If we have a signed multiply but no PMULDQ fix up the high parts of a
13473 // unsigned multiply.
13474 if (IsSigned && !Subtarget->hasSSE41()) {
13476 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
13477 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
13478 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
13479 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
13480 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
13482 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
13483 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
13486 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getValueType(), Highs, Lows);
13489 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
13490 const X86Subtarget *Subtarget) {
13491 MVT VT = Op.getSimpleValueType();
13493 SDValue R = Op.getOperand(0);
13494 SDValue Amt = Op.getOperand(1);
13496 // Optimize shl/srl/sra with constant shift amount.
13497 if (isSplatVector(Amt.getNode())) {
13498 SDValue SclrAmt = Amt->getOperand(0);
13499 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
13500 uint64_t ShiftAmt = C->getZExtValue();
13502 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
13503 (Subtarget->hasInt256() &&
13504 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
13505 (Subtarget->hasAVX512() &&
13506 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
13507 if (Op.getOpcode() == ISD::SHL)
13508 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
13510 if (Op.getOpcode() == ISD::SRL)
13511 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
13513 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
13514 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
13518 if (VT == MVT::v16i8) {
13519 if (Op.getOpcode() == ISD::SHL) {
13520 // Make a large shift.
13521 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
13522 MVT::v8i16, R, ShiftAmt,
13524 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
13525 // Zero out the rightmost bits.
13526 SmallVector<SDValue, 16> V(16,
13527 DAG.getConstant(uint8_t(-1U << ShiftAmt),
13529 return DAG.getNode(ISD::AND, dl, VT, SHL,
13530 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
13532 if (Op.getOpcode() == ISD::SRL) {
13533 // Make a large shift.
13534 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
13535 MVT::v8i16, R, ShiftAmt,
13537 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
13538 // Zero out the leftmost bits.
13539 SmallVector<SDValue, 16> V(16,
13540 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
13542 return DAG.getNode(ISD::AND, dl, VT, SRL,
13543 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
13545 if (Op.getOpcode() == ISD::SRA) {
13546 if (ShiftAmt == 7) {
13547 // R s>> 7 === R s< 0
13548 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13549 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
13552 // R s>> a === ((R u>> a) ^ m) - m
13553 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
13554 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
13556 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
13557 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
13558 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
13561 llvm_unreachable("Unknown shift opcode.");
13564 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
13565 if (Op.getOpcode() == ISD::SHL) {
13566 // Make a large shift.
13567 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
13568 MVT::v16i16, R, ShiftAmt,
13570 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
13571 // Zero out the rightmost bits.
13572 SmallVector<SDValue, 32> V(32,
13573 DAG.getConstant(uint8_t(-1U << ShiftAmt),
13575 return DAG.getNode(ISD::AND, dl, VT, SHL,
13576 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
13578 if (Op.getOpcode() == ISD::SRL) {
13579 // Make a large shift.
13580 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
13581 MVT::v16i16, R, ShiftAmt,
13583 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
13584 // Zero out the leftmost bits.
13585 SmallVector<SDValue, 32> V(32,
13586 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
13588 return DAG.getNode(ISD::AND, dl, VT, SRL,
13589 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
13591 if (Op.getOpcode() == ISD::SRA) {
13592 if (ShiftAmt == 7) {
13593 // R s>> 7 === R s< 0
13594 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13595 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
13598 // R s>> a === ((R u>> a) ^ m) - m
13599 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
13600 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
13602 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
13603 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
13604 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
13607 llvm_unreachable("Unknown shift opcode.");
13612 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
13613 if (!Subtarget->is64Bit() &&
13614 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
13615 Amt.getOpcode() == ISD::BITCAST &&
13616 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
13617 Amt = Amt.getOperand(0);
13618 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
13619 VT.getVectorNumElements();
13620 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
13621 uint64_t ShiftAmt = 0;
13622 for (unsigned i = 0; i != Ratio; ++i) {
13623 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
13627 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
13629 // Check remaining shift amounts.
13630 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
13631 uint64_t ShAmt = 0;
13632 for (unsigned j = 0; j != Ratio; ++j) {
13633 ConstantSDNode *C =
13634 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
13638 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
13640 if (ShAmt != ShiftAmt)
13643 switch (Op.getOpcode()) {
13645 llvm_unreachable("Unknown shift opcode!");
13647 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
13650 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
13653 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
13661 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
13662 const X86Subtarget* Subtarget) {
13663 MVT VT = Op.getSimpleValueType();
13665 SDValue R = Op.getOperand(0);
13666 SDValue Amt = Op.getOperand(1);
13668 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
13669 VT == MVT::v4i32 || VT == MVT::v8i16 ||
13670 (Subtarget->hasInt256() &&
13671 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
13672 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
13673 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
13675 EVT EltVT = VT.getVectorElementType();
13677 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13678 unsigned NumElts = VT.getVectorNumElements();
13680 for (i = 0; i != NumElts; ++i) {
13681 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
13685 for (j = i; j != NumElts; ++j) {
13686 SDValue Arg = Amt.getOperand(j);
13687 if (Arg.getOpcode() == ISD::UNDEF) continue;
13688 if (Arg != Amt.getOperand(i))
13691 if (i != NumElts && j == NumElts)
13692 BaseShAmt = Amt.getOperand(i);
13694 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
13695 Amt = Amt.getOperand(0);
13696 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
13697 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
13698 SDValue InVec = Amt.getOperand(0);
13699 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13700 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13702 for (; i != NumElts; ++i) {
13703 SDValue Arg = InVec.getOperand(i);
13704 if (Arg.getOpcode() == ISD::UNDEF) continue;
13708 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13709 if (ConstantSDNode *C =
13710 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13711 unsigned SplatIdx =
13712 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
13713 if (C->getZExtValue() == SplatIdx)
13714 BaseShAmt = InVec.getOperand(1);
13717 if (!BaseShAmt.getNode())
13718 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
13719 DAG.getIntPtrConstant(0));
13723 if (BaseShAmt.getNode()) {
13724 if (EltVT.bitsGT(MVT::i32))
13725 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
13726 else if (EltVT.bitsLT(MVT::i32))
13727 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
13729 switch (Op.getOpcode()) {
13731 llvm_unreachable("Unknown shift opcode!");
13733 switch (VT.SimpleTy) {
13734 default: return SDValue();
13743 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
13746 switch (VT.SimpleTy) {
13747 default: return SDValue();
13754 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
13757 switch (VT.SimpleTy) {
13758 default: return SDValue();
13767 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
13773 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
13774 if (!Subtarget->is64Bit() &&
13775 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
13776 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
13777 Amt.getOpcode() == ISD::BITCAST &&
13778 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
13779 Amt = Amt.getOperand(0);
13780 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
13781 VT.getVectorNumElements();
13782 std::vector<SDValue> Vals(Ratio);
13783 for (unsigned i = 0; i != Ratio; ++i)
13784 Vals[i] = Amt.getOperand(i);
13785 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
13786 for (unsigned j = 0; j != Ratio; ++j)
13787 if (Vals[j] != Amt.getOperand(i + j))
13790 switch (Op.getOpcode()) {
13792 llvm_unreachable("Unknown shift opcode!");
13794 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
13796 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
13798 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
13805 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
13806 SelectionDAG &DAG) {
13808 MVT VT = Op.getSimpleValueType();
13810 SDValue R = Op.getOperand(0);
13811 SDValue Amt = Op.getOperand(1);
13814 if (!Subtarget->hasSSE2())
13817 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
13821 V = LowerScalarVariableShift(Op, DAG, Subtarget);
13825 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
13827 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
13828 if (Subtarget->hasInt256()) {
13829 if (Op.getOpcode() == ISD::SRL &&
13830 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13831 VT == MVT::v4i64 || VT == MVT::v8i32))
13833 if (Op.getOpcode() == ISD::SHL &&
13834 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13835 VT == MVT::v4i64 || VT == MVT::v8i32))
13837 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
13841 // If possible, lower this packed shift into a vector multiply instead of
13842 // expanding it into a sequence of scalar shifts.
13843 // Do this only if the vector shift count is a constant build_vector.
13844 if (Op.getOpcode() == ISD::SHL &&
13845 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
13846 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
13847 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
13848 SmallVector<SDValue, 8> Elts;
13849 EVT SVT = VT.getScalarType();
13850 unsigned SVTBits = SVT.getSizeInBits();
13851 const APInt &One = APInt(SVTBits, 1);
13852 unsigned NumElems = VT.getVectorNumElements();
13854 for (unsigned i=0; i !=NumElems; ++i) {
13855 SDValue Op = Amt->getOperand(i);
13856 if (Op->getOpcode() == ISD::UNDEF) {
13857 Elts.push_back(Op);
13861 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
13862 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
13863 uint64_t ShAmt = C.getZExtValue();
13864 if (ShAmt >= SVTBits) {
13865 Elts.push_back(DAG.getUNDEF(SVT));
13868 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
13870 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
13871 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
13874 // Lower SHL with variable shift amount.
13875 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
13876 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
13878 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
13879 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
13880 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
13881 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
13884 // If possible, lower this shift as a sequence of two shifts by
13885 // constant plus a MOVSS/MOVSD instead of scalarizing it.
13887 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
13889 // Could be rewritten as:
13890 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
13892 // The advantage is that the two shifts from the example would be
13893 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
13894 // the vector shift into four scalar shifts plus four pairs of vector
13896 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
13897 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
13898 unsigned TargetOpcode = X86ISD::MOVSS;
13899 bool CanBeSimplified;
13900 // The splat value for the first packed shift (the 'X' from the example).
13901 SDValue Amt1 = Amt->getOperand(0);
13902 // The splat value for the second packed shift (the 'Y' from the example).
13903 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
13904 Amt->getOperand(2);
13906 // See if it is possible to replace this node with a sequence of
13907 // two shifts followed by a MOVSS/MOVSD
13908 if (VT == MVT::v4i32) {
13909 // Check if it is legal to use a MOVSS.
13910 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
13911 Amt2 == Amt->getOperand(3);
13912 if (!CanBeSimplified) {
13913 // Otherwise, check if we can still simplify this node using a MOVSD.
13914 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
13915 Amt->getOperand(2) == Amt->getOperand(3);
13916 TargetOpcode = X86ISD::MOVSD;
13917 Amt2 = Amt->getOperand(2);
13920 // Do similar checks for the case where the machine value type
13922 CanBeSimplified = Amt1 == Amt->getOperand(1);
13923 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
13924 CanBeSimplified = Amt2 == Amt->getOperand(i);
13926 if (!CanBeSimplified) {
13927 TargetOpcode = X86ISD::MOVSD;
13928 CanBeSimplified = true;
13929 Amt2 = Amt->getOperand(4);
13930 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
13931 CanBeSimplified = Amt1 == Amt->getOperand(i);
13932 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
13933 CanBeSimplified = Amt2 == Amt->getOperand(j);
13937 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
13938 isa<ConstantSDNode>(Amt2)) {
13939 // Replace this node with two shifts followed by a MOVSS/MOVSD.
13940 EVT CastVT = MVT::v4i32;
13942 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
13943 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
13945 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
13946 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
13947 if (TargetOpcode == X86ISD::MOVSD)
13948 CastVT = MVT::v2i64;
13949 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
13950 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
13951 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
13953 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13957 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
13958 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
13961 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
13962 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
13964 // Turn 'a' into a mask suitable for VSELECT
13965 SDValue VSelM = DAG.getConstant(0x80, VT);
13966 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13967 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13969 SDValue CM1 = DAG.getConstant(0x0f, VT);
13970 SDValue CM2 = DAG.getConstant(0x3f, VT);
13972 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
13973 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
13974 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
13975 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13976 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13979 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13980 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13981 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13983 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
13984 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
13985 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
13986 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13987 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13990 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13991 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13992 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13994 // return VSELECT(r, r+r, a);
13995 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
13996 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
14000 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
14001 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
14002 // solution better.
14003 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
14004 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
14006 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
14007 R = DAG.getNode(ExtOpc, dl, NewVT, R);
14008 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
14009 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14010 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
14013 // Decompose 256-bit shifts into smaller 128-bit shifts.
14014 if (VT.is256BitVector()) {
14015 unsigned NumElems = VT.getVectorNumElements();
14016 MVT EltVT = VT.getVectorElementType();
14017 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14019 // Extract the two vectors
14020 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
14021 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
14023 // Recreate the shift amount vectors
14024 SDValue Amt1, Amt2;
14025 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
14026 // Constant shift amount
14027 SmallVector<SDValue, 4> Amt1Csts;
14028 SmallVector<SDValue, 4> Amt2Csts;
14029 for (unsigned i = 0; i != NumElems/2; ++i)
14030 Amt1Csts.push_back(Amt->getOperand(i));
14031 for (unsigned i = NumElems/2; i != NumElems; ++i)
14032 Amt2Csts.push_back(Amt->getOperand(i));
14034 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
14035 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
14037 // Variable shift amount
14038 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
14039 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
14042 // Issue new vector shifts for the smaller types
14043 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
14044 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
14046 // Concatenate the result back
14047 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
14053 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
14054 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
14055 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
14056 // looks for this combo and may remove the "setcc" instruction if the "setcc"
14057 // has only one use.
14058 SDNode *N = Op.getNode();
14059 SDValue LHS = N->getOperand(0);
14060 SDValue RHS = N->getOperand(1);
14061 unsigned BaseOp = 0;
14064 switch (Op.getOpcode()) {
14065 default: llvm_unreachable("Unknown ovf instruction!");
14067 // A subtract of one will be selected as a INC. Note that INC doesn't
14068 // set CF, so we can't do this for UADDO.
14069 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14071 BaseOp = X86ISD::INC;
14072 Cond = X86::COND_O;
14075 BaseOp = X86ISD::ADD;
14076 Cond = X86::COND_O;
14079 BaseOp = X86ISD::ADD;
14080 Cond = X86::COND_B;
14083 // A subtract of one will be selected as a DEC. Note that DEC doesn't
14084 // set CF, so we can't do this for USUBO.
14085 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14087 BaseOp = X86ISD::DEC;
14088 Cond = X86::COND_O;
14091 BaseOp = X86ISD::SUB;
14092 Cond = X86::COND_O;
14095 BaseOp = X86ISD::SUB;
14096 Cond = X86::COND_B;
14099 BaseOp = X86ISD::SMUL;
14100 Cond = X86::COND_O;
14102 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
14103 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
14105 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
14108 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
14109 DAG.getConstant(X86::COND_O, MVT::i32),
14110 SDValue(Sum.getNode(), 2));
14112 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
14116 // Also sets EFLAGS.
14117 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
14118 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
14121 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
14122 DAG.getConstant(Cond, MVT::i32),
14123 SDValue(Sum.getNode(), 1));
14125 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
14128 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
14129 SelectionDAG &DAG) const {
14131 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
14132 MVT VT = Op.getSimpleValueType();
14134 if (!Subtarget->hasSSE2() || !VT.isVector())
14137 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
14138 ExtraVT.getScalarType().getSizeInBits();
14140 switch (VT.SimpleTy) {
14141 default: return SDValue();
14144 if (!Subtarget->hasFp256())
14146 if (!Subtarget->hasInt256()) {
14147 // needs to be split
14148 unsigned NumElems = VT.getVectorNumElements();
14150 // Extract the LHS vectors
14151 SDValue LHS = Op.getOperand(0);
14152 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14153 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14155 MVT EltVT = VT.getVectorElementType();
14156 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14158 EVT ExtraEltVT = ExtraVT.getVectorElementType();
14159 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
14160 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
14162 SDValue Extra = DAG.getValueType(ExtraVT);
14164 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
14165 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
14167 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
14172 SDValue Op0 = Op.getOperand(0);
14173 SDValue Op00 = Op0.getOperand(0);
14175 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
14176 if (Op0.getOpcode() == ISD::BITCAST &&
14177 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
14178 // (sext (vzext x)) -> (vsext x)
14179 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
14180 if (Tmp1.getNode()) {
14181 EVT ExtraEltVT = ExtraVT.getVectorElementType();
14182 // This folding is only valid when the in-reg type is a vector of i8,
14184 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
14185 ExtraEltVT == MVT::i32) {
14186 SDValue Tmp1Op0 = Tmp1.getOperand(0);
14187 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
14188 "This optimization is invalid without a VZEXT.");
14189 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
14195 // If the above didn't work, then just use Shift-Left + Shift-Right.
14196 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
14198 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
14204 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
14205 SelectionDAG &DAG) {
14207 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
14208 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
14209 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
14210 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
14212 // The only fence that needs an instruction is a sequentially-consistent
14213 // cross-thread fence.
14214 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
14215 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
14216 // no-sse2). There isn't any reason to disable it if the target processor
14218 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
14219 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
14221 SDValue Chain = Op.getOperand(0);
14222 SDValue Zero = DAG.getConstant(0, MVT::i32);
14224 DAG.getRegister(X86::ESP, MVT::i32), // Base
14225 DAG.getTargetConstant(1, MVT::i8), // Scale
14226 DAG.getRegister(0, MVT::i32), // Index
14227 DAG.getTargetConstant(0, MVT::i32), // Disp
14228 DAG.getRegister(0, MVT::i32), // Segment.
14232 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
14233 return SDValue(Res, 0);
14236 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
14237 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
14240 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
14241 SelectionDAG &DAG) {
14242 MVT T = Op.getSimpleValueType();
14246 switch(T.SimpleTy) {
14247 default: llvm_unreachable("Invalid value type!");
14248 case MVT::i8: Reg = X86::AL; size = 1; break;
14249 case MVT::i16: Reg = X86::AX; size = 2; break;
14250 case MVT::i32: Reg = X86::EAX; size = 4; break;
14252 assert(Subtarget->is64Bit() && "Node not type legal!");
14253 Reg = X86::RAX; size = 8;
14256 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
14257 Op.getOperand(2), SDValue());
14258 SDValue Ops[] = { cpIn.getValue(0),
14261 DAG.getTargetConstant(size, MVT::i8),
14262 cpIn.getValue(1) };
14263 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14264 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
14265 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
14268 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
14272 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
14273 SelectionDAG &DAG) {
14274 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
14275 MVT DstVT = Op.getSimpleValueType();
14277 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
14278 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
14279 if (DstVT != MVT::f64)
14280 // This conversion needs to be expanded.
14283 SDValue InVec = Op->getOperand(0);
14285 unsigned NumElts = SrcVT.getVectorNumElements();
14286 EVT SVT = SrcVT.getVectorElementType();
14288 // Widen the vector in input in the case of MVT::v2i32.
14289 // Example: from MVT::v2i32 to MVT::v4i32.
14290 SmallVector<SDValue, 16> Elts;
14291 for (unsigned i = 0, e = NumElts; i != e; ++i)
14292 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
14293 DAG.getIntPtrConstant(i)));
14295 // Explicitly mark the extra elements as Undef.
14296 SDValue Undef = DAG.getUNDEF(SVT);
14297 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
14298 Elts.push_back(Undef);
14300 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
14301 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
14302 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
14303 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
14304 DAG.getIntPtrConstant(0));
14307 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
14308 Subtarget->hasMMX() && "Unexpected custom BITCAST");
14309 assert((DstVT == MVT::i64 ||
14310 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
14311 "Unexpected custom BITCAST");
14312 // i64 <=> MMX conversions are Legal.
14313 if (SrcVT==MVT::i64 && DstVT.isVector())
14315 if (DstVT==MVT::i64 && SrcVT.isVector())
14317 // MMX <=> MMX conversions are Legal.
14318 if (SrcVT.isVector() && DstVT.isVector())
14320 // All other conversions need to be expanded.
14324 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
14325 SDNode *Node = Op.getNode();
14327 EVT T = Node->getValueType(0);
14328 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
14329 DAG.getConstant(0, T), Node->getOperand(2));
14330 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
14331 cast<AtomicSDNode>(Node)->getMemoryVT(),
14332 Node->getOperand(0),
14333 Node->getOperand(1), negOp,
14334 cast<AtomicSDNode>(Node)->getMemOperand(),
14335 cast<AtomicSDNode>(Node)->getOrdering(),
14336 cast<AtomicSDNode>(Node)->getSynchScope());
14339 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
14340 SDNode *Node = Op.getNode();
14342 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
14344 // Convert seq_cst store -> xchg
14345 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
14346 // FIXME: On 32-bit, store -> fist or movq would be more efficient
14347 // (The only way to get a 16-byte store is cmpxchg16b)
14348 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
14349 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
14350 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14351 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
14352 cast<AtomicSDNode>(Node)->getMemoryVT(),
14353 Node->getOperand(0),
14354 Node->getOperand(1), Node->getOperand(2),
14355 cast<AtomicSDNode>(Node)->getMemOperand(),
14356 cast<AtomicSDNode>(Node)->getOrdering(),
14357 cast<AtomicSDNode>(Node)->getSynchScope());
14358 return Swap.getValue(1);
14360 // Other atomic stores have a simple pattern.
14364 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
14365 EVT VT = Op.getNode()->getSimpleValueType(0);
14367 // Let legalize expand this if it isn't a legal type yet.
14368 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
14371 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
14374 bool ExtraOp = false;
14375 switch (Op.getOpcode()) {
14376 default: llvm_unreachable("Invalid code");
14377 case ISD::ADDC: Opc = X86ISD::ADD; break;
14378 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
14379 case ISD::SUBC: Opc = X86ISD::SUB; break;
14380 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
14384 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
14386 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
14387 Op.getOperand(1), Op.getOperand(2));
14390 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
14391 SelectionDAG &DAG) {
14392 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
14394 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
14395 // which returns the values as { float, float } (in XMM0) or
14396 // { double, double } (which is returned in XMM0, XMM1).
14398 SDValue Arg = Op.getOperand(0);
14399 EVT ArgVT = Arg.getValueType();
14400 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14402 TargetLowering::ArgListTy Args;
14403 TargetLowering::ArgListEntry Entry;
14407 Entry.isSExt = false;
14408 Entry.isZExt = false;
14409 Args.push_back(Entry);
14411 bool isF64 = ArgVT == MVT::f64;
14412 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
14413 // the small struct {f32, f32} is returned in (eax, edx). For f64,
14414 // the results are returned via SRet in memory.
14415 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
14416 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14417 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
14419 Type *RetTy = isF64
14420 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
14421 : (Type*)VectorType::get(ArgTy, 4);
14423 TargetLowering::CallLoweringInfo CLI(DAG);
14424 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
14425 .setCallee(CallingConv::C, RetTy, Callee, &Args, 0);
14427 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
14430 // Returned in xmm0 and xmm1.
14431 return CallResult.first;
14433 // Returned in bits 0:31 and 32:64 xmm0.
14434 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
14435 CallResult.first, DAG.getIntPtrConstant(0));
14436 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
14437 CallResult.first, DAG.getIntPtrConstant(1));
14438 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
14439 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
14442 /// LowerOperation - Provide custom lowering hooks for some operations.
14444 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
14445 switch (Op.getOpcode()) {
14446 default: llvm_unreachable("Should not custom lower this!");
14447 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
14448 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
14449 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
14450 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
14451 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
14452 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
14453 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
14454 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
14455 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
14456 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
14457 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
14458 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
14459 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
14460 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
14461 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
14462 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
14463 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
14464 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
14465 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
14466 case ISD::SHL_PARTS:
14467 case ISD::SRA_PARTS:
14468 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
14469 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
14470 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
14471 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
14472 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
14473 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
14474 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
14475 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
14476 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
14477 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
14478 case ISD::FABS: return LowerFABS(Op, DAG);
14479 case ISD::FNEG: return LowerFNEG(Op, DAG);
14480 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
14481 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
14482 case ISD::SETCC: return LowerSETCC(Op, DAG);
14483 case ISD::SELECT: return LowerSELECT(Op, DAG);
14484 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
14485 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
14486 case ISD::VASTART: return LowerVASTART(Op, DAG);
14487 case ISD::VAARG: return LowerVAARG(Op, DAG);
14488 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
14489 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
14490 case ISD::INTRINSIC_VOID:
14491 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
14492 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
14493 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
14494 case ISD::FRAME_TO_ARGS_OFFSET:
14495 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
14496 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
14497 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
14498 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
14499 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
14500 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
14501 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
14502 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
14503 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
14504 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
14505 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
14506 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
14507 case ISD::UMUL_LOHI:
14508 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
14511 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
14517 case ISD::UMULO: return LowerXALUO(Op, DAG);
14518 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
14519 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
14523 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
14524 case ISD::ADD: return LowerADD(Op, DAG);
14525 case ISD::SUB: return LowerSUB(Op, DAG);
14526 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
14530 static void ReplaceATOMIC_LOAD(SDNode *Node,
14531 SmallVectorImpl<SDValue> &Results,
14532 SelectionDAG &DAG) {
14534 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
14536 // Convert wide load -> cmpxchg8b/cmpxchg16b
14537 // FIXME: On 32-bit, load -> fild or movq would be more efficient
14538 // (The only way to get a 16-byte load is cmpxchg16b)
14539 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
14540 SDValue Zero = DAG.getConstant(0, VT);
14541 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
14542 Node->getOperand(0),
14543 Node->getOperand(1), Zero, Zero,
14544 cast<AtomicSDNode>(Node)->getMemOperand(),
14545 cast<AtomicSDNode>(Node)->getOrdering(),
14546 cast<AtomicSDNode>(Node)->getOrdering(),
14547 cast<AtomicSDNode>(Node)->getSynchScope());
14548 Results.push_back(Swap.getValue(0));
14549 Results.push_back(Swap.getValue(1));
14553 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
14554 SelectionDAG &DAG, unsigned NewOp) {
14556 assert (Node->getValueType(0) == MVT::i64 &&
14557 "Only know how to expand i64 atomics");
14559 SDValue Chain = Node->getOperand(0);
14560 SDValue In1 = Node->getOperand(1);
14561 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
14562 Node->getOperand(2), DAG.getIntPtrConstant(0));
14563 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
14564 Node->getOperand(2), DAG.getIntPtrConstant(1));
14565 SDValue Ops[] = { Chain, In1, In2L, In2H };
14566 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
14568 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, MVT::i64,
14569 cast<MemSDNode>(Node)->getMemOperand());
14570 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
14571 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF));
14572 Results.push_back(Result.getValue(2));
14575 /// ReplaceNodeResults - Replace a node with an illegal result type
14576 /// with a new node built out of custom code.
14577 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
14578 SmallVectorImpl<SDValue>&Results,
14579 SelectionDAG &DAG) const {
14581 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14582 switch (N->getOpcode()) {
14584 llvm_unreachable("Do not know how to custom type legalize this operation!");
14585 case ISD::SIGN_EXTEND_INREG:
14590 // We don't want to expand or promote these.
14597 case ISD::UDIVREM: {
14598 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
14599 Results.push_back(V);
14602 case ISD::FP_TO_SINT:
14603 case ISD::FP_TO_UINT: {
14604 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
14606 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
14609 std::pair<SDValue,SDValue> Vals =
14610 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
14611 SDValue FIST = Vals.first, StackSlot = Vals.second;
14612 if (FIST.getNode()) {
14613 EVT VT = N->getValueType(0);
14614 // Return a load from the stack slot.
14615 if (StackSlot.getNode())
14616 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
14617 MachinePointerInfo(),
14618 false, false, false, 0));
14620 Results.push_back(FIST);
14624 case ISD::UINT_TO_FP: {
14625 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
14626 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
14627 N->getValueType(0) != MVT::v2f32)
14629 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
14631 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
14633 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
14634 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
14635 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
14636 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
14637 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
14638 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
14641 case ISD::FP_ROUND: {
14642 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
14644 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
14645 Results.push_back(V);
14648 case ISD::INTRINSIC_W_CHAIN: {
14649 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
14651 default : llvm_unreachable("Do not know how to custom type "
14652 "legalize this intrinsic operation!");
14653 case Intrinsic::x86_rdtsc:
14654 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
14656 case Intrinsic::x86_rdtscp:
14657 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
14661 case ISD::READCYCLECOUNTER: {
14662 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
14665 case ISD::ATOMIC_CMP_SWAP: {
14666 EVT T = N->getValueType(0);
14667 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
14668 bool Regs64bit = T == MVT::i128;
14669 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
14670 SDValue cpInL, cpInH;
14671 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
14672 DAG.getConstant(0, HalfT));
14673 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
14674 DAG.getConstant(1, HalfT));
14675 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
14676 Regs64bit ? X86::RAX : X86::EAX,
14678 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
14679 Regs64bit ? X86::RDX : X86::EDX,
14680 cpInH, cpInL.getValue(1));
14681 SDValue swapInL, swapInH;
14682 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
14683 DAG.getConstant(0, HalfT));
14684 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
14685 DAG.getConstant(1, HalfT));
14686 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
14687 Regs64bit ? X86::RBX : X86::EBX,
14688 swapInL, cpInH.getValue(1));
14689 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
14690 Regs64bit ? X86::RCX : X86::ECX,
14691 swapInH, swapInL.getValue(1));
14692 SDValue Ops[] = { swapInH.getValue(0),
14694 swapInH.getValue(1) };
14695 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14696 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
14697 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
14698 X86ISD::LCMPXCHG8_DAG;
14699 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
14700 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
14701 Regs64bit ? X86::RAX : X86::EAX,
14702 HalfT, Result.getValue(1));
14703 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
14704 Regs64bit ? X86::RDX : X86::EDX,
14705 HalfT, cpOutL.getValue(2));
14706 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
14707 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
14708 Results.push_back(cpOutH.getValue(1));
14711 case ISD::ATOMIC_LOAD_ADD:
14712 case ISD::ATOMIC_LOAD_AND:
14713 case ISD::ATOMIC_LOAD_NAND:
14714 case ISD::ATOMIC_LOAD_OR:
14715 case ISD::ATOMIC_LOAD_SUB:
14716 case ISD::ATOMIC_LOAD_XOR:
14717 case ISD::ATOMIC_LOAD_MAX:
14718 case ISD::ATOMIC_LOAD_MIN:
14719 case ISD::ATOMIC_LOAD_UMAX:
14720 case ISD::ATOMIC_LOAD_UMIN:
14721 case ISD::ATOMIC_SWAP: {
14723 switch (N->getOpcode()) {
14724 default: llvm_unreachable("Unexpected opcode");
14725 case ISD::ATOMIC_LOAD_ADD:
14726 Opc = X86ISD::ATOMADD64_DAG;
14728 case ISD::ATOMIC_LOAD_AND:
14729 Opc = X86ISD::ATOMAND64_DAG;
14731 case ISD::ATOMIC_LOAD_NAND:
14732 Opc = X86ISD::ATOMNAND64_DAG;
14734 case ISD::ATOMIC_LOAD_OR:
14735 Opc = X86ISD::ATOMOR64_DAG;
14737 case ISD::ATOMIC_LOAD_SUB:
14738 Opc = X86ISD::ATOMSUB64_DAG;
14740 case ISD::ATOMIC_LOAD_XOR:
14741 Opc = X86ISD::ATOMXOR64_DAG;
14743 case ISD::ATOMIC_LOAD_MAX:
14744 Opc = X86ISD::ATOMMAX64_DAG;
14746 case ISD::ATOMIC_LOAD_MIN:
14747 Opc = X86ISD::ATOMMIN64_DAG;
14749 case ISD::ATOMIC_LOAD_UMAX:
14750 Opc = X86ISD::ATOMUMAX64_DAG;
14752 case ISD::ATOMIC_LOAD_UMIN:
14753 Opc = X86ISD::ATOMUMIN64_DAG;
14755 case ISD::ATOMIC_SWAP:
14756 Opc = X86ISD::ATOMSWAP64_DAG;
14759 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
14762 case ISD::ATOMIC_LOAD: {
14763 ReplaceATOMIC_LOAD(N, Results, DAG);
14766 case ISD::BITCAST: {
14767 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
14768 EVT DstVT = N->getValueType(0);
14769 EVT SrcVT = N->getOperand(0)->getValueType(0);
14771 if (SrcVT != MVT::f64 ||
14772 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
14775 unsigned NumElts = DstVT.getVectorNumElements();
14776 EVT SVT = DstVT.getVectorElementType();
14777 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
14778 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14779 MVT::v2f64, N->getOperand(0));
14780 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
14782 SmallVector<SDValue, 8> Elts;
14783 for (unsigned i = 0, e = NumElts; i != e; ++i)
14784 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
14785 ToVecInt, DAG.getIntPtrConstant(i)));
14787 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
14792 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
14794 default: return nullptr;
14795 case X86ISD::BSF: return "X86ISD::BSF";
14796 case X86ISD::BSR: return "X86ISD::BSR";
14797 case X86ISD::SHLD: return "X86ISD::SHLD";
14798 case X86ISD::SHRD: return "X86ISD::SHRD";
14799 case X86ISD::FAND: return "X86ISD::FAND";
14800 case X86ISD::FANDN: return "X86ISD::FANDN";
14801 case X86ISD::FOR: return "X86ISD::FOR";
14802 case X86ISD::FXOR: return "X86ISD::FXOR";
14803 case X86ISD::FSRL: return "X86ISD::FSRL";
14804 case X86ISD::FILD: return "X86ISD::FILD";
14805 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
14806 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
14807 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
14808 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
14809 case X86ISD::FLD: return "X86ISD::FLD";
14810 case X86ISD::FST: return "X86ISD::FST";
14811 case X86ISD::CALL: return "X86ISD::CALL";
14812 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
14813 case X86ISD::BT: return "X86ISD::BT";
14814 case X86ISD::CMP: return "X86ISD::CMP";
14815 case X86ISD::COMI: return "X86ISD::COMI";
14816 case X86ISD::UCOMI: return "X86ISD::UCOMI";
14817 case X86ISD::CMPM: return "X86ISD::CMPM";
14818 case X86ISD::CMPMU: return "X86ISD::CMPMU";
14819 case X86ISD::SETCC: return "X86ISD::SETCC";
14820 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
14821 case X86ISD::FSETCC: return "X86ISD::FSETCC";
14822 case X86ISD::CMOV: return "X86ISD::CMOV";
14823 case X86ISD::BRCOND: return "X86ISD::BRCOND";
14824 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
14825 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
14826 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
14827 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
14828 case X86ISD::Wrapper: return "X86ISD::Wrapper";
14829 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
14830 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
14831 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
14832 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
14833 case X86ISD::PINSRB: return "X86ISD::PINSRB";
14834 case X86ISD::PINSRW: return "X86ISD::PINSRW";
14835 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
14836 case X86ISD::ANDNP: return "X86ISD::ANDNP";
14837 case X86ISD::PSIGN: return "X86ISD::PSIGN";
14838 case X86ISD::BLENDV: return "X86ISD::BLENDV";
14839 case X86ISD::BLENDI: return "X86ISD::BLENDI";
14840 case X86ISD::SUBUS: return "X86ISD::SUBUS";
14841 case X86ISD::HADD: return "X86ISD::HADD";
14842 case X86ISD::HSUB: return "X86ISD::HSUB";
14843 case X86ISD::FHADD: return "X86ISD::FHADD";
14844 case X86ISD::FHSUB: return "X86ISD::FHSUB";
14845 case X86ISD::UMAX: return "X86ISD::UMAX";
14846 case X86ISD::UMIN: return "X86ISD::UMIN";
14847 case X86ISD::SMAX: return "X86ISD::SMAX";
14848 case X86ISD::SMIN: return "X86ISD::SMIN";
14849 case X86ISD::FMAX: return "X86ISD::FMAX";
14850 case X86ISD::FMIN: return "X86ISD::FMIN";
14851 case X86ISD::FMAXC: return "X86ISD::FMAXC";
14852 case X86ISD::FMINC: return "X86ISD::FMINC";
14853 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
14854 case X86ISD::FRCP: return "X86ISD::FRCP";
14855 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
14856 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
14857 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
14858 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
14859 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
14860 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
14861 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
14862 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
14863 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
14864 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
14865 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
14866 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
14867 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
14868 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
14869 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
14870 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
14871 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
14872 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
14873 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
14874 case X86ISD::VZEXT: return "X86ISD::VZEXT";
14875 case X86ISD::VSEXT: return "X86ISD::VSEXT";
14876 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
14877 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
14878 case X86ISD::VINSERT: return "X86ISD::VINSERT";
14879 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
14880 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
14881 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
14882 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
14883 case X86ISD::VSHL: return "X86ISD::VSHL";
14884 case X86ISD::VSRL: return "X86ISD::VSRL";
14885 case X86ISD::VSRA: return "X86ISD::VSRA";
14886 case X86ISD::VSHLI: return "X86ISD::VSHLI";
14887 case X86ISD::VSRLI: return "X86ISD::VSRLI";
14888 case X86ISD::VSRAI: return "X86ISD::VSRAI";
14889 case X86ISD::CMPP: return "X86ISD::CMPP";
14890 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
14891 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
14892 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
14893 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
14894 case X86ISD::ADD: return "X86ISD::ADD";
14895 case X86ISD::SUB: return "X86ISD::SUB";
14896 case X86ISD::ADC: return "X86ISD::ADC";
14897 case X86ISD::SBB: return "X86ISD::SBB";
14898 case X86ISD::SMUL: return "X86ISD::SMUL";
14899 case X86ISD::UMUL: return "X86ISD::UMUL";
14900 case X86ISD::INC: return "X86ISD::INC";
14901 case X86ISD::DEC: return "X86ISD::DEC";
14902 case X86ISD::OR: return "X86ISD::OR";
14903 case X86ISD::XOR: return "X86ISD::XOR";
14904 case X86ISD::AND: return "X86ISD::AND";
14905 case X86ISD::BEXTR: return "X86ISD::BEXTR";
14906 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
14907 case X86ISD::PTEST: return "X86ISD::PTEST";
14908 case X86ISD::TESTP: return "X86ISD::TESTP";
14909 case X86ISD::TESTM: return "X86ISD::TESTM";
14910 case X86ISD::TESTNM: return "X86ISD::TESTNM";
14911 case X86ISD::KORTEST: return "X86ISD::KORTEST";
14912 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
14913 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
14914 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
14915 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
14916 case X86ISD::SHUFP: return "X86ISD::SHUFP";
14917 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
14918 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
14919 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
14920 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
14921 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
14922 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
14923 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
14924 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
14925 case X86ISD::MOVSD: return "X86ISD::MOVSD";
14926 case X86ISD::MOVSS: return "X86ISD::MOVSS";
14927 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
14928 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
14929 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
14930 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
14931 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
14932 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
14933 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
14934 case X86ISD::VPERMV: return "X86ISD::VPERMV";
14935 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
14936 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
14937 case X86ISD::VPERMI: return "X86ISD::VPERMI";
14938 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
14939 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
14940 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
14941 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
14942 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
14943 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
14944 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
14945 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
14946 case X86ISD::SAHF: return "X86ISD::SAHF";
14947 case X86ISD::RDRAND: return "X86ISD::RDRAND";
14948 case X86ISD::RDSEED: return "X86ISD::RDSEED";
14949 case X86ISD::FMADD: return "X86ISD::FMADD";
14950 case X86ISD::FMSUB: return "X86ISD::FMSUB";
14951 case X86ISD::FNMADD: return "X86ISD::FNMADD";
14952 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
14953 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
14954 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
14955 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
14956 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
14957 case X86ISD::XTEST: return "X86ISD::XTEST";
14961 // isLegalAddressingMode - Return true if the addressing mode represented
14962 // by AM is legal for this target, for a load/store of the specified type.
14963 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
14965 // X86 supports extremely general addressing modes.
14966 CodeModel::Model M = getTargetMachine().getCodeModel();
14967 Reloc::Model R = getTargetMachine().getRelocationModel();
14969 // X86 allows a sign-extended 32-bit immediate field as a displacement.
14970 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
14975 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
14977 // If a reference to this global requires an extra load, we can't fold it.
14978 if (isGlobalStubReference(GVFlags))
14981 // If BaseGV requires a register for the PIC base, we cannot also have a
14982 // BaseReg specified.
14983 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
14986 // If lower 4G is not available, then we must use rip-relative addressing.
14987 if ((M != CodeModel::Small || R != Reloc::Static) &&
14988 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
14992 switch (AM.Scale) {
14998 // These scales always work.
15003 // These scales are formed with basereg+scalereg. Only accept if there is
15008 default: // Other stuff never works.
15015 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
15016 unsigned Bits = Ty->getScalarSizeInBits();
15018 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
15019 // particularly cheaper than those without.
15023 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
15024 // variable shifts just as cheap as scalar ones.
15025 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
15028 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
15029 // fully general vector.
15033 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
15034 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
15036 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
15037 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
15038 return NumBits1 > NumBits2;
15041 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
15042 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
15045 if (!isTypeLegal(EVT::getEVT(Ty1)))
15048 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
15050 // Assuming the caller doesn't have a zeroext or signext return parameter,
15051 // truncation all the way down to i1 is valid.
15055 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
15056 return isInt<32>(Imm);
15059 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
15060 // Can also use sub to handle negated immediates.
15061 return isInt<32>(Imm);
15064 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
15065 if (!VT1.isInteger() || !VT2.isInteger())
15067 unsigned NumBits1 = VT1.getSizeInBits();
15068 unsigned NumBits2 = VT2.getSizeInBits();
15069 return NumBits1 > NumBits2;
15072 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
15073 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
15074 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
15077 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
15078 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
15079 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
15082 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
15083 EVT VT1 = Val.getValueType();
15084 if (isZExtFree(VT1, VT2))
15087 if (Val.getOpcode() != ISD::LOAD)
15090 if (!VT1.isSimple() || !VT1.isInteger() ||
15091 !VT2.isSimple() || !VT2.isInteger())
15094 switch (VT1.getSimpleVT().SimpleTy) {
15099 // X86 has 8, 16, and 32-bit zero-extending loads.
15107 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
15108 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
15111 VT = VT.getScalarType();
15113 if (!VT.isSimple())
15116 switch (VT.getSimpleVT().SimpleTy) {
15127 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
15128 // i16 instructions are longer (0x66 prefix) and potentially slower.
15129 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
15132 /// isShuffleMaskLegal - Targets can use this to indicate that they only
15133 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
15134 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
15135 /// are assumed to be legal.
15137 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
15139 if (!VT.isSimple())
15142 MVT SVT = VT.getSimpleVT();
15144 // Very little shuffling can be done for 64-bit vectors right now.
15145 if (VT.getSizeInBits() == 64)
15148 // If this is a single-input shuffle with no 128 bit lane crossings we can
15149 // lower it into pshufb.
15150 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
15151 (SVT.is256BitVector() && Subtarget->hasInt256())) {
15152 bool isLegal = true;
15153 for (unsigned I = 0, E = M.size(); I != E; ++I) {
15154 if (M[I] >= (int)SVT.getVectorNumElements() ||
15155 ShuffleCrosses128bitLane(SVT, I, M[I])) {
15164 // FIXME: blends, shifts.
15165 return (SVT.getVectorNumElements() == 2 ||
15166 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
15167 isMOVLMask(M, SVT) ||
15168 isSHUFPMask(M, SVT) ||
15169 isPSHUFDMask(M, SVT) ||
15170 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
15171 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
15172 isPALIGNRMask(M, SVT, Subtarget) ||
15173 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
15174 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
15175 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
15176 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
15180 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
15182 if (!VT.isSimple())
15185 MVT SVT = VT.getSimpleVT();
15186 unsigned NumElts = SVT.getVectorNumElements();
15187 // FIXME: This collection of masks seems suspect.
15190 if (NumElts == 4 && SVT.is128BitVector()) {
15191 return (isMOVLMask(Mask, SVT) ||
15192 isCommutedMOVLMask(Mask, SVT, true) ||
15193 isSHUFPMask(Mask, SVT) ||
15194 isSHUFPMask(Mask, SVT, /* Commuted */ true));
15199 //===----------------------------------------------------------------------===//
15200 // X86 Scheduler Hooks
15201 //===----------------------------------------------------------------------===//
15203 /// Utility function to emit xbegin specifying the start of an RTM region.
15204 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
15205 const TargetInstrInfo *TII) {
15206 DebugLoc DL = MI->getDebugLoc();
15208 const BasicBlock *BB = MBB->getBasicBlock();
15209 MachineFunction::iterator I = MBB;
15212 // For the v = xbegin(), we generate
15223 MachineBasicBlock *thisMBB = MBB;
15224 MachineFunction *MF = MBB->getParent();
15225 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15226 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15227 MF->insert(I, mainMBB);
15228 MF->insert(I, sinkMBB);
15230 // Transfer the remainder of BB and its successor edges to sinkMBB.
15231 sinkMBB->splice(sinkMBB->begin(), MBB,
15232 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
15233 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15237 // # fallthrough to mainMBB
15238 // # abortion to sinkMBB
15239 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
15240 thisMBB->addSuccessor(mainMBB);
15241 thisMBB->addSuccessor(sinkMBB);
15245 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
15246 mainMBB->addSuccessor(sinkMBB);
15249 // EAX is live into the sinkMBB
15250 sinkMBB->addLiveIn(X86::EAX);
15251 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15252 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15255 MI->eraseFromParent();
15259 // Get CMPXCHG opcode for the specified data type.
15260 static unsigned getCmpXChgOpcode(EVT VT) {
15261 switch (VT.getSimpleVT().SimpleTy) {
15262 case MVT::i8: return X86::LCMPXCHG8;
15263 case MVT::i16: return X86::LCMPXCHG16;
15264 case MVT::i32: return X86::LCMPXCHG32;
15265 case MVT::i64: return X86::LCMPXCHG64;
15269 llvm_unreachable("Invalid operand size!");
15272 // Get LOAD opcode for the specified data type.
15273 static unsigned getLoadOpcode(EVT VT) {
15274 switch (VT.getSimpleVT().SimpleTy) {
15275 case MVT::i8: return X86::MOV8rm;
15276 case MVT::i16: return X86::MOV16rm;
15277 case MVT::i32: return X86::MOV32rm;
15278 case MVT::i64: return X86::MOV64rm;
15282 llvm_unreachable("Invalid operand size!");
15285 // Get opcode of the non-atomic one from the specified atomic instruction.
15286 static unsigned getNonAtomicOpcode(unsigned Opc) {
15288 case X86::ATOMAND8: return X86::AND8rr;
15289 case X86::ATOMAND16: return X86::AND16rr;
15290 case X86::ATOMAND32: return X86::AND32rr;
15291 case X86::ATOMAND64: return X86::AND64rr;
15292 case X86::ATOMOR8: return X86::OR8rr;
15293 case X86::ATOMOR16: return X86::OR16rr;
15294 case X86::ATOMOR32: return X86::OR32rr;
15295 case X86::ATOMOR64: return X86::OR64rr;
15296 case X86::ATOMXOR8: return X86::XOR8rr;
15297 case X86::ATOMXOR16: return X86::XOR16rr;
15298 case X86::ATOMXOR32: return X86::XOR32rr;
15299 case X86::ATOMXOR64: return X86::XOR64rr;
15301 llvm_unreachable("Unhandled atomic-load-op opcode!");
15304 // Get opcode of the non-atomic one from the specified atomic instruction with
15306 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
15307 unsigned &ExtraOpc) {
15309 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
15310 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
15311 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
15312 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
15313 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
15314 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
15315 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
15316 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
15317 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
15318 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
15319 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
15320 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
15321 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
15322 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
15323 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
15324 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
15325 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
15326 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
15327 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
15328 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
15330 llvm_unreachable("Unhandled atomic-load-op opcode!");
15333 // Get opcode of the non-atomic one from the specified atomic instruction for
15334 // 64-bit data type on 32-bit target.
15335 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
15337 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
15338 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
15339 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
15340 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
15341 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
15342 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
15343 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
15344 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
15345 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
15346 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
15348 llvm_unreachable("Unhandled atomic-load-op opcode!");
15351 // Get opcode of the non-atomic one from the specified atomic instruction for
15352 // 64-bit data type on 32-bit target with extra opcode.
15353 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
15355 unsigned &ExtraOpc) {
15357 case X86::ATOMNAND6432:
15358 ExtraOpc = X86::NOT32r;
15359 HiOpc = X86::AND32rr;
15360 return X86::AND32rr;
15362 llvm_unreachable("Unhandled atomic-load-op opcode!");
15365 // Get pseudo CMOV opcode from the specified data type.
15366 static unsigned getPseudoCMOVOpc(EVT VT) {
15367 switch (VT.getSimpleVT().SimpleTy) {
15368 case MVT::i8: return X86::CMOV_GR8;
15369 case MVT::i16: return X86::CMOV_GR16;
15370 case MVT::i32: return X86::CMOV_GR32;
15374 llvm_unreachable("Unknown CMOV opcode!");
15377 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
15378 // They will be translated into a spin-loop or compare-exchange loop from
15381 // dst = atomic-fetch-op MI.addr, MI.val
15387 // t1 = LOAD MI.addr
15389 // t4 = phi(t1, t3 / loop)
15390 // t2 = OP MI.val, t4
15392 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
15398 MachineBasicBlock *
15399 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
15400 MachineBasicBlock *MBB) const {
15401 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15402 DebugLoc DL = MI->getDebugLoc();
15404 MachineFunction *MF = MBB->getParent();
15405 MachineRegisterInfo &MRI = MF->getRegInfo();
15407 const BasicBlock *BB = MBB->getBasicBlock();
15408 MachineFunction::iterator I = MBB;
15411 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
15412 "Unexpected number of operands");
15414 assert(MI->hasOneMemOperand() &&
15415 "Expected atomic-load-op to have one memoperand");
15417 // Memory Reference
15418 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15419 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15421 unsigned DstReg, SrcReg;
15422 unsigned MemOpndSlot;
15424 unsigned CurOp = 0;
15426 DstReg = MI->getOperand(CurOp++).getReg();
15427 MemOpndSlot = CurOp;
15428 CurOp += X86::AddrNumOperands;
15429 SrcReg = MI->getOperand(CurOp++).getReg();
15431 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15432 MVT::SimpleValueType VT = *RC->vt_begin();
15433 unsigned t1 = MRI.createVirtualRegister(RC);
15434 unsigned t2 = MRI.createVirtualRegister(RC);
15435 unsigned t3 = MRI.createVirtualRegister(RC);
15436 unsigned t4 = MRI.createVirtualRegister(RC);
15437 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
15439 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
15440 unsigned LOADOpc = getLoadOpcode(VT);
15442 // For the atomic load-arith operator, we generate
15445 // t1 = LOAD [MI.addr]
15447 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
15448 // t1 = OP MI.val, EAX
15450 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
15456 MachineBasicBlock *thisMBB = MBB;
15457 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15458 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15459 MF->insert(I, mainMBB);
15460 MF->insert(I, sinkMBB);
15462 MachineInstrBuilder MIB;
15464 // Transfer the remainder of BB and its successor edges to sinkMBB.
15465 sinkMBB->splice(sinkMBB->begin(), MBB,
15466 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
15467 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15470 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
15471 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15472 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15474 NewMO.setIsKill(false);
15475 MIB.addOperand(NewMO);
15477 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
15478 unsigned flags = (*MMOI)->getFlags();
15479 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
15480 MachineMemOperand *MMO =
15481 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
15482 (*MMOI)->getSize(),
15483 (*MMOI)->getBaseAlignment(),
15484 (*MMOI)->getTBAAInfo(),
15485 (*MMOI)->getRanges());
15486 MIB.addMemOperand(MMO);
15489 thisMBB->addSuccessor(mainMBB);
15492 MachineBasicBlock *origMainMBB = mainMBB;
15495 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
15496 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
15498 unsigned Opc = MI->getOpcode();
15501 llvm_unreachable("Unhandled atomic-load-op opcode!");
15502 case X86::ATOMAND8:
15503 case X86::ATOMAND16:
15504 case X86::ATOMAND32:
15505 case X86::ATOMAND64:
15507 case X86::ATOMOR16:
15508 case X86::ATOMOR32:
15509 case X86::ATOMOR64:
15510 case X86::ATOMXOR8:
15511 case X86::ATOMXOR16:
15512 case X86::ATOMXOR32:
15513 case X86::ATOMXOR64: {
15514 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
15515 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
15519 case X86::ATOMNAND8:
15520 case X86::ATOMNAND16:
15521 case X86::ATOMNAND32:
15522 case X86::ATOMNAND64: {
15523 unsigned Tmp = MRI.createVirtualRegister(RC);
15525 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
15526 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
15528 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
15531 case X86::ATOMMAX8:
15532 case X86::ATOMMAX16:
15533 case X86::ATOMMAX32:
15534 case X86::ATOMMAX64:
15535 case X86::ATOMMIN8:
15536 case X86::ATOMMIN16:
15537 case X86::ATOMMIN32:
15538 case X86::ATOMMIN64:
15539 case X86::ATOMUMAX8:
15540 case X86::ATOMUMAX16:
15541 case X86::ATOMUMAX32:
15542 case X86::ATOMUMAX64:
15543 case X86::ATOMUMIN8:
15544 case X86::ATOMUMIN16:
15545 case X86::ATOMUMIN32:
15546 case X86::ATOMUMIN64: {
15548 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
15550 BuildMI(mainMBB, DL, TII->get(CMPOpc))
15554 if (Subtarget->hasCMov()) {
15555 if (VT != MVT::i8) {
15557 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
15561 // Promote i8 to i32 to use CMOV32
15562 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15563 const TargetRegisterClass *RC32 =
15564 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
15565 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
15566 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
15567 unsigned Tmp = MRI.createVirtualRegister(RC32);
15569 unsigned Undef = MRI.createVirtualRegister(RC32);
15570 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
15572 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
15575 .addImm(X86::sub_8bit);
15576 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
15579 .addImm(X86::sub_8bit);
15581 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
15585 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
15586 .addReg(Tmp, 0, X86::sub_8bit);
15589 // Use pseudo select and lower them.
15590 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
15591 "Invalid atomic-load-op transformation!");
15592 unsigned SelOpc = getPseudoCMOVOpc(VT);
15593 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
15594 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
15595 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
15596 .addReg(SrcReg).addReg(t4)
15598 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15599 // Replace the original PHI node as mainMBB is changed after CMOV
15601 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
15602 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
15603 Phi->eraseFromParent();
15609 // Copy PhyReg back from virtual register.
15610 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
15613 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
15614 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15615 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15617 NewMO.setIsKill(false);
15618 MIB.addOperand(NewMO);
15621 MIB.setMemRefs(MMOBegin, MMOEnd);
15623 // Copy PhyReg back to virtual register.
15624 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
15627 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
15629 mainMBB->addSuccessor(origMainMBB);
15630 mainMBB->addSuccessor(sinkMBB);
15633 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15634 TII->get(TargetOpcode::COPY), DstReg)
15637 MI->eraseFromParent();
15641 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
15642 // instructions. They will be translated into a spin-loop or compare-exchange
15646 // dst = atomic-fetch-op MI.addr, MI.val
15652 // t1L = LOAD [MI.addr + 0]
15653 // t1H = LOAD [MI.addr + 4]
15655 // t4L = phi(t1L, t3L / loop)
15656 // t4H = phi(t1H, t3H / loop)
15657 // t2L = OP MI.val.lo, t4L
15658 // t2H = OP MI.val.hi, t4H
15663 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
15671 MachineBasicBlock *
15672 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
15673 MachineBasicBlock *MBB) const {
15674 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15675 DebugLoc DL = MI->getDebugLoc();
15677 MachineFunction *MF = MBB->getParent();
15678 MachineRegisterInfo &MRI = MF->getRegInfo();
15680 const BasicBlock *BB = MBB->getBasicBlock();
15681 MachineFunction::iterator I = MBB;
15684 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
15685 "Unexpected number of operands");
15687 assert(MI->hasOneMemOperand() &&
15688 "Expected atomic-load-op32 to have one memoperand");
15690 // Memory Reference
15691 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15692 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15694 unsigned DstLoReg, DstHiReg;
15695 unsigned SrcLoReg, SrcHiReg;
15696 unsigned MemOpndSlot;
15698 unsigned CurOp = 0;
15700 DstLoReg = MI->getOperand(CurOp++).getReg();
15701 DstHiReg = MI->getOperand(CurOp++).getReg();
15702 MemOpndSlot = CurOp;
15703 CurOp += X86::AddrNumOperands;
15704 SrcLoReg = MI->getOperand(CurOp++).getReg();
15705 SrcHiReg = MI->getOperand(CurOp++).getReg();
15707 const TargetRegisterClass *RC = &X86::GR32RegClass;
15708 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
15710 unsigned t1L = MRI.createVirtualRegister(RC);
15711 unsigned t1H = MRI.createVirtualRegister(RC);
15712 unsigned t2L = MRI.createVirtualRegister(RC);
15713 unsigned t2H = MRI.createVirtualRegister(RC);
15714 unsigned t3L = MRI.createVirtualRegister(RC);
15715 unsigned t3H = MRI.createVirtualRegister(RC);
15716 unsigned t4L = MRI.createVirtualRegister(RC);
15717 unsigned t4H = MRI.createVirtualRegister(RC);
15719 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
15720 unsigned LOADOpc = X86::MOV32rm;
15722 // For the atomic load-arith operator, we generate
15725 // t1L = LOAD [MI.addr + 0]
15726 // t1H = LOAD [MI.addr + 4]
15728 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
15729 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
15730 // t2L = OP MI.val.lo, t4L
15731 // t2H = OP MI.val.hi, t4H
15734 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
15742 MachineBasicBlock *thisMBB = MBB;
15743 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15744 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15745 MF->insert(I, mainMBB);
15746 MF->insert(I, sinkMBB);
15748 MachineInstrBuilder MIB;
15750 // Transfer the remainder of BB and its successor edges to sinkMBB.
15751 sinkMBB->splice(sinkMBB->begin(), MBB,
15752 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
15753 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15757 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
15758 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15759 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15761 NewMO.setIsKill(false);
15762 MIB.addOperand(NewMO);
15764 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
15765 unsigned flags = (*MMOI)->getFlags();
15766 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
15767 MachineMemOperand *MMO =
15768 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
15769 (*MMOI)->getSize(),
15770 (*MMOI)->getBaseAlignment(),
15771 (*MMOI)->getTBAAInfo(),
15772 (*MMOI)->getRanges());
15773 MIB.addMemOperand(MMO);
15775 MachineInstr *LowMI = MIB;
15778 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
15779 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15780 if (i == X86::AddrDisp) {
15781 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
15783 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15785 NewMO.setIsKill(false);
15786 MIB.addOperand(NewMO);
15789 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
15791 thisMBB->addSuccessor(mainMBB);
15794 MachineBasicBlock *origMainMBB = mainMBB;
15797 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
15798 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
15799 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
15800 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
15802 unsigned Opc = MI->getOpcode();
15805 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
15806 case X86::ATOMAND6432:
15807 case X86::ATOMOR6432:
15808 case X86::ATOMXOR6432:
15809 case X86::ATOMADD6432:
15810 case X86::ATOMSUB6432: {
15812 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15813 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
15815 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
15819 case X86::ATOMNAND6432: {
15820 unsigned HiOpc, NOTOpc;
15821 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
15822 unsigned TmpL = MRI.createVirtualRegister(RC);
15823 unsigned TmpH = MRI.createVirtualRegister(RC);
15824 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
15826 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
15828 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
15829 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
15832 case X86::ATOMMAX6432:
15833 case X86::ATOMMIN6432:
15834 case X86::ATOMUMAX6432:
15835 case X86::ATOMUMIN6432: {
15837 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15838 unsigned cL = MRI.createVirtualRegister(RC8);
15839 unsigned cH = MRI.createVirtualRegister(RC8);
15840 unsigned cL32 = MRI.createVirtualRegister(RC);
15841 unsigned cH32 = MRI.createVirtualRegister(RC);
15842 unsigned cc = MRI.createVirtualRegister(RC);
15843 // cl := cmp src_lo, lo
15844 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
15845 .addReg(SrcLoReg).addReg(t4L);
15846 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
15847 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
15848 // ch := cmp src_hi, hi
15849 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
15850 .addReg(SrcHiReg).addReg(t4H);
15851 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
15852 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
15853 // cc := if (src_hi == hi) ? cl : ch;
15854 if (Subtarget->hasCMov()) {
15855 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
15856 .addReg(cH32).addReg(cL32);
15858 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
15859 .addReg(cH32).addReg(cL32)
15860 .addImm(X86::COND_E);
15861 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15863 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
15864 if (Subtarget->hasCMov()) {
15865 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
15866 .addReg(SrcLoReg).addReg(t4L);
15867 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
15868 .addReg(SrcHiReg).addReg(t4H);
15870 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
15871 .addReg(SrcLoReg).addReg(t4L)
15872 .addImm(X86::COND_NE);
15873 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15874 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
15875 // 2nd CMOV lowering.
15876 mainMBB->addLiveIn(X86::EFLAGS);
15877 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
15878 .addReg(SrcHiReg).addReg(t4H)
15879 .addImm(X86::COND_NE);
15880 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15881 // Replace the original PHI node as mainMBB is changed after CMOV
15883 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
15884 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
15885 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
15886 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
15887 PhiL->eraseFromParent();
15888 PhiH->eraseFromParent();
15892 case X86::ATOMSWAP6432: {
15894 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15895 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
15896 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
15901 // Copy EDX:EAX back from HiReg:LoReg
15902 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
15903 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
15904 // Copy ECX:EBX from t1H:t1L
15905 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
15906 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
15908 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
15909 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15910 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15912 NewMO.setIsKill(false);
15913 MIB.addOperand(NewMO);
15915 MIB.setMemRefs(MMOBegin, MMOEnd);
15917 // Copy EDX:EAX back to t3H:t3L
15918 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
15919 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
15921 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
15923 mainMBB->addSuccessor(origMainMBB);
15924 mainMBB->addSuccessor(sinkMBB);
15927 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15928 TII->get(TargetOpcode::COPY), DstLoReg)
15930 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15931 TII->get(TargetOpcode::COPY), DstHiReg)
15934 MI->eraseFromParent();
15938 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
15939 // or XMM0_V32I8 in AVX all of this code can be replaced with that
15940 // in the .td file.
15941 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
15942 const TargetInstrInfo *TII) {
15944 switch (MI->getOpcode()) {
15945 default: llvm_unreachable("illegal opcode!");
15946 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
15947 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
15948 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
15949 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
15950 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
15951 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
15952 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
15953 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
15956 DebugLoc dl = MI->getDebugLoc();
15957 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15959 unsigned NumArgs = MI->getNumOperands();
15960 for (unsigned i = 1; i < NumArgs; ++i) {
15961 MachineOperand &Op = MI->getOperand(i);
15962 if (!(Op.isReg() && Op.isImplicit()))
15963 MIB.addOperand(Op);
15965 if (MI->hasOneMemOperand())
15966 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15968 BuildMI(*BB, MI, dl,
15969 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15970 .addReg(X86::XMM0);
15972 MI->eraseFromParent();
15976 // FIXME: Custom handling because TableGen doesn't support multiple implicit
15977 // defs in an instruction pattern
15978 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
15979 const TargetInstrInfo *TII) {
15981 switch (MI->getOpcode()) {
15982 default: llvm_unreachable("illegal opcode!");
15983 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
15984 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
15985 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
15986 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
15987 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
15988 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
15989 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
15990 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
15993 DebugLoc dl = MI->getDebugLoc();
15994 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15996 unsigned NumArgs = MI->getNumOperands(); // remove the results
15997 for (unsigned i = 1; i < NumArgs; ++i) {
15998 MachineOperand &Op = MI->getOperand(i);
15999 if (!(Op.isReg() && Op.isImplicit()))
16000 MIB.addOperand(Op);
16002 if (MI->hasOneMemOperand())
16003 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
16005 BuildMI(*BB, MI, dl,
16006 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
16009 MI->eraseFromParent();
16013 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
16014 const TargetInstrInfo *TII,
16015 const X86Subtarget* Subtarget) {
16016 DebugLoc dl = MI->getDebugLoc();
16018 // Address into RAX/EAX, other two args into ECX, EDX.
16019 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
16020 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
16021 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
16022 for (int i = 0; i < X86::AddrNumOperands; ++i)
16023 MIB.addOperand(MI->getOperand(i));
16025 unsigned ValOps = X86::AddrNumOperands;
16026 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
16027 .addReg(MI->getOperand(ValOps).getReg());
16028 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
16029 .addReg(MI->getOperand(ValOps+1).getReg());
16031 // The instruction doesn't actually take any operands though.
16032 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
16034 MI->eraseFromParent(); // The pseudo is gone now.
16038 MachineBasicBlock *
16039 X86TargetLowering::EmitVAARG64WithCustomInserter(
16041 MachineBasicBlock *MBB) const {
16042 // Emit va_arg instruction on X86-64.
16044 // Operands to this pseudo-instruction:
16045 // 0 ) Output : destination address (reg)
16046 // 1-5) Input : va_list address (addr, i64mem)
16047 // 6 ) ArgSize : Size (in bytes) of vararg type
16048 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
16049 // 8 ) Align : Alignment of type
16050 // 9 ) EFLAGS (implicit-def)
16052 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
16053 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
16055 unsigned DestReg = MI->getOperand(0).getReg();
16056 MachineOperand &Base = MI->getOperand(1);
16057 MachineOperand &Scale = MI->getOperand(2);
16058 MachineOperand &Index = MI->getOperand(3);
16059 MachineOperand &Disp = MI->getOperand(4);
16060 MachineOperand &Segment = MI->getOperand(5);
16061 unsigned ArgSize = MI->getOperand(6).getImm();
16062 unsigned ArgMode = MI->getOperand(7).getImm();
16063 unsigned Align = MI->getOperand(8).getImm();
16065 // Memory Reference
16066 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
16067 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
16068 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
16070 // Machine Information
16071 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16072 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
16073 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
16074 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
16075 DebugLoc DL = MI->getDebugLoc();
16077 // struct va_list {
16080 // i64 overflow_area (address)
16081 // i64 reg_save_area (address)
16083 // sizeof(va_list) = 24
16084 // alignment(va_list) = 8
16086 unsigned TotalNumIntRegs = 6;
16087 unsigned TotalNumXMMRegs = 8;
16088 bool UseGPOffset = (ArgMode == 1);
16089 bool UseFPOffset = (ArgMode == 2);
16090 unsigned MaxOffset = TotalNumIntRegs * 8 +
16091 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
16093 /* Align ArgSize to a multiple of 8 */
16094 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
16095 bool NeedsAlign = (Align > 8);
16097 MachineBasicBlock *thisMBB = MBB;
16098 MachineBasicBlock *overflowMBB;
16099 MachineBasicBlock *offsetMBB;
16100 MachineBasicBlock *endMBB;
16102 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
16103 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
16104 unsigned OffsetReg = 0;
16106 if (!UseGPOffset && !UseFPOffset) {
16107 // If we only pull from the overflow region, we don't create a branch.
16108 // We don't need to alter control flow.
16109 OffsetDestReg = 0; // unused
16110 OverflowDestReg = DestReg;
16112 offsetMBB = nullptr;
16113 overflowMBB = thisMBB;
16116 // First emit code to check if gp_offset (or fp_offset) is below the bound.
16117 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
16118 // If not, pull from overflow_area. (branch to overflowMBB)
16123 // offsetMBB overflowMBB
16128 // Registers for the PHI in endMBB
16129 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
16130 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
16132 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
16133 MachineFunction *MF = MBB->getParent();
16134 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
16135 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
16136 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
16138 MachineFunction::iterator MBBIter = MBB;
16141 // Insert the new basic blocks
16142 MF->insert(MBBIter, offsetMBB);
16143 MF->insert(MBBIter, overflowMBB);
16144 MF->insert(MBBIter, endMBB);
16146 // Transfer the remainder of MBB and its successor edges to endMBB.
16147 endMBB->splice(endMBB->begin(), thisMBB,
16148 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
16149 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
16151 // Make offsetMBB and overflowMBB successors of thisMBB
16152 thisMBB->addSuccessor(offsetMBB);
16153 thisMBB->addSuccessor(overflowMBB);
16155 // endMBB is a successor of both offsetMBB and overflowMBB
16156 offsetMBB->addSuccessor(endMBB);
16157 overflowMBB->addSuccessor(endMBB);
16159 // Load the offset value into a register
16160 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
16161 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
16165 .addDisp(Disp, UseFPOffset ? 4 : 0)
16166 .addOperand(Segment)
16167 .setMemRefs(MMOBegin, MMOEnd);
16169 // Check if there is enough room left to pull this argument.
16170 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
16172 .addImm(MaxOffset + 8 - ArgSizeA8);
16174 // Branch to "overflowMBB" if offset >= max
16175 // Fall through to "offsetMBB" otherwise
16176 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
16177 .addMBB(overflowMBB);
16180 // In offsetMBB, emit code to use the reg_save_area.
16182 assert(OffsetReg != 0);
16184 // Read the reg_save_area address.
16185 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
16186 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
16191 .addOperand(Segment)
16192 .setMemRefs(MMOBegin, MMOEnd);
16194 // Zero-extend the offset
16195 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
16196 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
16199 .addImm(X86::sub_32bit);
16201 // Add the offset to the reg_save_area to get the final address.
16202 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
16203 .addReg(OffsetReg64)
16204 .addReg(RegSaveReg);
16206 // Compute the offset for the next argument
16207 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
16208 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
16210 .addImm(UseFPOffset ? 16 : 8);
16212 // Store it back into the va_list.
16213 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
16217 .addDisp(Disp, UseFPOffset ? 4 : 0)
16218 .addOperand(Segment)
16219 .addReg(NextOffsetReg)
16220 .setMemRefs(MMOBegin, MMOEnd);
16223 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
16228 // Emit code to use overflow area
16231 // Load the overflow_area address into a register.
16232 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
16233 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
16238 .addOperand(Segment)
16239 .setMemRefs(MMOBegin, MMOEnd);
16241 // If we need to align it, do so. Otherwise, just copy the address
16242 // to OverflowDestReg.
16244 // Align the overflow address
16245 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
16246 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
16248 // aligned_addr = (addr + (align-1)) & ~(align-1)
16249 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
16250 .addReg(OverflowAddrReg)
16253 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
16255 .addImm(~(uint64_t)(Align-1));
16257 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
16258 .addReg(OverflowAddrReg);
16261 // Compute the next overflow address after this argument.
16262 // (the overflow address should be kept 8-byte aligned)
16263 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
16264 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
16265 .addReg(OverflowDestReg)
16266 .addImm(ArgSizeA8);
16268 // Store the new overflow address.
16269 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
16274 .addOperand(Segment)
16275 .addReg(NextAddrReg)
16276 .setMemRefs(MMOBegin, MMOEnd);
16278 // If we branched, emit the PHI to the front of endMBB.
16280 BuildMI(*endMBB, endMBB->begin(), DL,
16281 TII->get(X86::PHI), DestReg)
16282 .addReg(OffsetDestReg).addMBB(offsetMBB)
16283 .addReg(OverflowDestReg).addMBB(overflowMBB);
16286 // Erase the pseudo instruction
16287 MI->eraseFromParent();
16292 MachineBasicBlock *
16293 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
16295 MachineBasicBlock *MBB) const {
16296 // Emit code to save XMM registers to the stack. The ABI says that the
16297 // number of registers to save is given in %al, so it's theoretically
16298 // possible to do an indirect jump trick to avoid saving all of them,
16299 // however this code takes a simpler approach and just executes all
16300 // of the stores if %al is non-zero. It's less code, and it's probably
16301 // easier on the hardware branch predictor, and stores aren't all that
16302 // expensive anyway.
16304 // Create the new basic blocks. One block contains all the XMM stores,
16305 // and one block is the final destination regardless of whether any
16306 // stores were performed.
16307 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
16308 MachineFunction *F = MBB->getParent();
16309 MachineFunction::iterator MBBIter = MBB;
16311 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
16312 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
16313 F->insert(MBBIter, XMMSaveMBB);
16314 F->insert(MBBIter, EndMBB);
16316 // Transfer the remainder of MBB and its successor edges to EndMBB.
16317 EndMBB->splice(EndMBB->begin(), MBB,
16318 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
16319 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
16321 // The original block will now fall through to the XMM save block.
16322 MBB->addSuccessor(XMMSaveMBB);
16323 // The XMMSaveMBB will fall through to the end block.
16324 XMMSaveMBB->addSuccessor(EndMBB);
16326 // Now add the instructions.
16327 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16328 DebugLoc DL = MI->getDebugLoc();
16330 unsigned CountReg = MI->getOperand(0).getReg();
16331 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
16332 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
16334 if (!Subtarget->isTargetWin64()) {
16335 // If %al is 0, branch around the XMM save block.
16336 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
16337 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
16338 MBB->addSuccessor(EndMBB);
16341 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
16342 // that was just emitted, but clearly shouldn't be "saved".
16343 assert((MI->getNumOperands() <= 3 ||
16344 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
16345 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
16346 && "Expected last argument to be EFLAGS");
16347 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
16348 // In the XMM save block, save all the XMM argument registers.
16349 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
16350 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
16351 MachineMemOperand *MMO =
16352 F->getMachineMemOperand(
16353 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
16354 MachineMemOperand::MOStore,
16355 /*Size=*/16, /*Align=*/16);
16356 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
16357 .addFrameIndex(RegSaveFrameIndex)
16358 .addImm(/*Scale=*/1)
16359 .addReg(/*IndexReg=*/0)
16360 .addImm(/*Disp=*/Offset)
16361 .addReg(/*Segment=*/0)
16362 .addReg(MI->getOperand(i).getReg())
16363 .addMemOperand(MMO);
16366 MI->eraseFromParent(); // The pseudo instruction is gone now.
16371 // The EFLAGS operand of SelectItr might be missing a kill marker
16372 // because there were multiple uses of EFLAGS, and ISel didn't know
16373 // which to mark. Figure out whether SelectItr should have had a
16374 // kill marker, and set it if it should. Returns the correct kill
16376 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
16377 MachineBasicBlock* BB,
16378 const TargetRegisterInfo* TRI) {
16379 // Scan forward through BB for a use/def of EFLAGS.
16380 MachineBasicBlock::iterator miI(std::next(SelectItr));
16381 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
16382 const MachineInstr& mi = *miI;
16383 if (mi.readsRegister(X86::EFLAGS))
16385 if (mi.definesRegister(X86::EFLAGS))
16386 break; // Should have kill-flag - update below.
16389 // If we hit the end of the block, check whether EFLAGS is live into a
16391 if (miI == BB->end()) {
16392 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
16393 sEnd = BB->succ_end();
16394 sItr != sEnd; ++sItr) {
16395 MachineBasicBlock* succ = *sItr;
16396 if (succ->isLiveIn(X86::EFLAGS))
16401 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
16402 // out. SelectMI should have a kill flag on EFLAGS.
16403 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
16407 MachineBasicBlock *
16408 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
16409 MachineBasicBlock *BB) const {
16410 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16411 DebugLoc DL = MI->getDebugLoc();
16413 // To "insert" a SELECT_CC instruction, we actually have to insert the
16414 // diamond control-flow pattern. The incoming instruction knows the
16415 // destination vreg to set, the condition code register to branch on, the
16416 // true/false values to select between, and a branch opcode to use.
16417 const BasicBlock *LLVM_BB = BB->getBasicBlock();
16418 MachineFunction::iterator It = BB;
16424 // cmpTY ccX, r1, r2
16426 // fallthrough --> copy0MBB
16427 MachineBasicBlock *thisMBB = BB;
16428 MachineFunction *F = BB->getParent();
16429 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
16430 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
16431 F->insert(It, copy0MBB);
16432 F->insert(It, sinkMBB);
16434 // If the EFLAGS register isn't dead in the terminator, then claim that it's
16435 // live into the sink and copy blocks.
16436 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
16437 if (!MI->killsRegister(X86::EFLAGS) &&
16438 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
16439 copy0MBB->addLiveIn(X86::EFLAGS);
16440 sinkMBB->addLiveIn(X86::EFLAGS);
16443 // Transfer the remainder of BB and its successor edges to sinkMBB.
16444 sinkMBB->splice(sinkMBB->begin(), BB,
16445 std::next(MachineBasicBlock::iterator(MI)), BB->end());
16446 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
16448 // Add the true and fallthrough blocks as its successors.
16449 BB->addSuccessor(copy0MBB);
16450 BB->addSuccessor(sinkMBB);
16452 // Create the conditional branch instruction.
16454 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
16455 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
16458 // %FalseValue = ...
16459 // # fallthrough to sinkMBB
16460 copy0MBB->addSuccessor(sinkMBB);
16463 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
16465 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
16466 TII->get(X86::PHI), MI->getOperand(0).getReg())
16467 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
16468 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
16470 MI->eraseFromParent(); // The pseudo instruction is gone now.
16474 MachineBasicBlock *
16475 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
16476 bool Is64Bit) const {
16477 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16478 DebugLoc DL = MI->getDebugLoc();
16479 MachineFunction *MF = BB->getParent();
16480 const BasicBlock *LLVM_BB = BB->getBasicBlock();
16482 assert(MF->shouldSplitStack());
16484 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
16485 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
16488 // ... [Till the alloca]
16489 // If stacklet is not large enough, jump to mallocMBB
16492 // Allocate by subtracting from RSP
16493 // Jump to continueMBB
16496 // Allocate by call to runtime
16500 // [rest of original BB]
16503 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
16504 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
16505 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
16507 MachineRegisterInfo &MRI = MF->getRegInfo();
16508 const TargetRegisterClass *AddrRegClass =
16509 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
16511 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
16512 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
16513 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
16514 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
16515 sizeVReg = MI->getOperand(1).getReg(),
16516 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
16518 MachineFunction::iterator MBBIter = BB;
16521 MF->insert(MBBIter, bumpMBB);
16522 MF->insert(MBBIter, mallocMBB);
16523 MF->insert(MBBIter, continueMBB);
16525 continueMBB->splice(continueMBB->begin(), BB,
16526 std::next(MachineBasicBlock::iterator(MI)), BB->end());
16527 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
16529 // Add code to the main basic block to check if the stack limit has been hit,
16530 // and if so, jump to mallocMBB otherwise to bumpMBB.
16531 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
16532 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
16533 .addReg(tmpSPVReg).addReg(sizeVReg);
16534 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
16535 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
16536 .addReg(SPLimitVReg);
16537 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
16539 // bumpMBB simply decreases the stack pointer, since we know the current
16540 // stacklet has enough space.
16541 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
16542 .addReg(SPLimitVReg);
16543 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
16544 .addReg(SPLimitVReg);
16545 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
16547 // Calls into a routine in libgcc to allocate more space from the heap.
16548 const uint32_t *RegMask =
16549 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
16551 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
16553 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
16554 .addExternalSymbol("__morestack_allocate_stack_space")
16555 .addRegMask(RegMask)
16556 .addReg(X86::RDI, RegState::Implicit)
16557 .addReg(X86::RAX, RegState::ImplicitDefine);
16559 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
16561 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
16562 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
16563 .addExternalSymbol("__morestack_allocate_stack_space")
16564 .addRegMask(RegMask)
16565 .addReg(X86::EAX, RegState::ImplicitDefine);
16569 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
16572 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
16573 .addReg(Is64Bit ? X86::RAX : X86::EAX);
16574 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
16576 // Set up the CFG correctly.
16577 BB->addSuccessor(bumpMBB);
16578 BB->addSuccessor(mallocMBB);
16579 mallocMBB->addSuccessor(continueMBB);
16580 bumpMBB->addSuccessor(continueMBB);
16582 // Take care of the PHI nodes.
16583 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
16584 MI->getOperand(0).getReg())
16585 .addReg(mallocPtrVReg).addMBB(mallocMBB)
16586 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
16588 // Delete the original pseudo instruction.
16589 MI->eraseFromParent();
16592 return continueMBB;
16595 MachineBasicBlock *
16596 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
16597 MachineBasicBlock *BB) const {
16598 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16599 DebugLoc DL = MI->getDebugLoc();
16601 assert(!Subtarget->isTargetMacho());
16603 // The lowering is pretty easy: we're just emitting the call to _alloca. The
16604 // non-trivial part is impdef of ESP.
16606 if (Subtarget->isTargetWin64()) {
16607 if (Subtarget->isTargetCygMing()) {
16608 // ___chkstk(Mingw64):
16609 // Clobbers R10, R11, RAX and EFLAGS.
16611 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
16612 .addExternalSymbol("___chkstk")
16613 .addReg(X86::RAX, RegState::Implicit)
16614 .addReg(X86::RSP, RegState::Implicit)
16615 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
16616 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
16617 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
16619 // __chkstk(MSVCRT): does not update stack pointer.
16620 // Clobbers R10, R11 and EFLAGS.
16621 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
16622 .addExternalSymbol("__chkstk")
16623 .addReg(X86::RAX, RegState::Implicit)
16624 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
16625 // RAX has the offset to be subtracted from RSP.
16626 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
16631 const char *StackProbeSymbol =
16632 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
16634 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
16635 .addExternalSymbol(StackProbeSymbol)
16636 .addReg(X86::EAX, RegState::Implicit)
16637 .addReg(X86::ESP, RegState::Implicit)
16638 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
16639 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
16640 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
16643 MI->eraseFromParent(); // The pseudo instruction is gone now.
16647 MachineBasicBlock *
16648 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
16649 MachineBasicBlock *BB) const {
16650 // This is pretty easy. We're taking the value that we received from
16651 // our load from the relocation, sticking it in either RDI (x86-64)
16652 // or EAX and doing an indirect call. The return value will then
16653 // be in the normal return register.
16654 const X86InstrInfo *TII
16655 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
16656 DebugLoc DL = MI->getDebugLoc();
16657 MachineFunction *F = BB->getParent();
16659 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
16660 assert(MI->getOperand(3).isGlobal() && "This should be a global");
16662 // Get a register mask for the lowered call.
16663 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
16664 // proper register mask.
16665 const uint32_t *RegMask =
16666 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
16667 if (Subtarget->is64Bit()) {
16668 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
16669 TII->get(X86::MOV64rm), X86::RDI)
16671 .addImm(0).addReg(0)
16672 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
16673 MI->getOperand(3).getTargetFlags())
16675 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
16676 addDirectMem(MIB, X86::RDI);
16677 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
16678 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
16679 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
16680 TII->get(X86::MOV32rm), X86::EAX)
16682 .addImm(0).addReg(0)
16683 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
16684 MI->getOperand(3).getTargetFlags())
16686 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
16687 addDirectMem(MIB, X86::EAX);
16688 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
16690 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
16691 TII->get(X86::MOV32rm), X86::EAX)
16692 .addReg(TII->getGlobalBaseReg(F))
16693 .addImm(0).addReg(0)
16694 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
16695 MI->getOperand(3).getTargetFlags())
16697 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
16698 addDirectMem(MIB, X86::EAX);
16699 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
16702 MI->eraseFromParent(); // The pseudo instruction is gone now.
16706 MachineBasicBlock *
16707 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
16708 MachineBasicBlock *MBB) const {
16709 DebugLoc DL = MI->getDebugLoc();
16710 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16712 MachineFunction *MF = MBB->getParent();
16713 MachineRegisterInfo &MRI = MF->getRegInfo();
16715 const BasicBlock *BB = MBB->getBasicBlock();
16716 MachineFunction::iterator I = MBB;
16719 // Memory Reference
16720 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
16721 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
16724 unsigned MemOpndSlot = 0;
16726 unsigned CurOp = 0;
16728 DstReg = MI->getOperand(CurOp++).getReg();
16729 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
16730 assert(RC->hasType(MVT::i32) && "Invalid destination!");
16731 unsigned mainDstReg = MRI.createVirtualRegister(RC);
16732 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
16734 MemOpndSlot = CurOp;
16736 MVT PVT = getPointerTy();
16737 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
16738 "Invalid Pointer Size!");
16740 // For v = setjmp(buf), we generate
16743 // buf[LabelOffset] = restoreMBB
16744 // SjLjSetup restoreMBB
16750 // v = phi(main, restore)
16755 MachineBasicBlock *thisMBB = MBB;
16756 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
16757 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
16758 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
16759 MF->insert(I, mainMBB);
16760 MF->insert(I, sinkMBB);
16761 MF->push_back(restoreMBB);
16763 MachineInstrBuilder MIB;
16765 // Transfer the remainder of BB and its successor edges to sinkMBB.
16766 sinkMBB->splice(sinkMBB->begin(), MBB,
16767 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
16768 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
16771 unsigned PtrStoreOpc = 0;
16772 unsigned LabelReg = 0;
16773 const int64_t LabelOffset = 1 * PVT.getStoreSize();
16774 Reloc::Model RM = getTargetMachine().getRelocationModel();
16775 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
16776 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
16778 // Prepare IP either in reg or imm.
16779 if (!UseImmLabel) {
16780 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
16781 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
16782 LabelReg = MRI.createVirtualRegister(PtrRC);
16783 if (Subtarget->is64Bit()) {
16784 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
16788 .addMBB(restoreMBB)
16791 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
16792 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
16793 .addReg(XII->getGlobalBaseReg(MF))
16796 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
16800 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
16802 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
16803 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16804 if (i == X86::AddrDisp)
16805 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
16807 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
16810 MIB.addReg(LabelReg);
16812 MIB.addMBB(restoreMBB);
16813 MIB.setMemRefs(MMOBegin, MMOEnd);
16815 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
16816 .addMBB(restoreMBB);
16818 const X86RegisterInfo *RegInfo =
16819 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
16820 MIB.addRegMask(RegInfo->getNoPreservedMask());
16821 thisMBB->addSuccessor(mainMBB);
16822 thisMBB->addSuccessor(restoreMBB);
16826 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
16827 mainMBB->addSuccessor(sinkMBB);
16830 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
16831 TII->get(X86::PHI), DstReg)
16832 .addReg(mainDstReg).addMBB(mainMBB)
16833 .addReg(restoreDstReg).addMBB(restoreMBB);
16836 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
16837 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
16838 restoreMBB->addSuccessor(sinkMBB);
16840 MI->eraseFromParent();
16844 MachineBasicBlock *
16845 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
16846 MachineBasicBlock *MBB) const {
16847 DebugLoc DL = MI->getDebugLoc();
16848 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16850 MachineFunction *MF = MBB->getParent();
16851 MachineRegisterInfo &MRI = MF->getRegInfo();
16853 // Memory Reference
16854 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
16855 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
16857 MVT PVT = getPointerTy();
16858 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
16859 "Invalid Pointer Size!");
16861 const TargetRegisterClass *RC =
16862 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
16863 unsigned Tmp = MRI.createVirtualRegister(RC);
16864 // Since FP is only updated here but NOT referenced, it's treated as GPR.
16865 const X86RegisterInfo *RegInfo =
16866 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
16867 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
16868 unsigned SP = RegInfo->getStackRegister();
16870 MachineInstrBuilder MIB;
16872 const int64_t LabelOffset = 1 * PVT.getStoreSize();
16873 const int64_t SPOffset = 2 * PVT.getStoreSize();
16875 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
16876 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
16879 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
16880 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
16881 MIB.addOperand(MI->getOperand(i));
16882 MIB.setMemRefs(MMOBegin, MMOEnd);
16884 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
16885 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16886 if (i == X86::AddrDisp)
16887 MIB.addDisp(MI->getOperand(i), LabelOffset);
16889 MIB.addOperand(MI->getOperand(i));
16891 MIB.setMemRefs(MMOBegin, MMOEnd);
16893 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
16894 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16895 if (i == X86::AddrDisp)
16896 MIB.addDisp(MI->getOperand(i), SPOffset);
16898 MIB.addOperand(MI->getOperand(i));
16900 MIB.setMemRefs(MMOBegin, MMOEnd);
16902 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
16904 MI->eraseFromParent();
16908 // Replace 213-type (isel default) FMA3 instructions with 231-type for
16909 // accumulator loops. Writing back to the accumulator allows the coalescer
16910 // to remove extra copies in the loop.
16911 MachineBasicBlock *
16912 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
16913 MachineBasicBlock *MBB) const {
16914 MachineOperand &AddendOp = MI->getOperand(3);
16916 // Bail out early if the addend isn't a register - we can't switch these.
16917 if (!AddendOp.isReg())
16920 MachineFunction &MF = *MBB->getParent();
16921 MachineRegisterInfo &MRI = MF.getRegInfo();
16923 // Check whether the addend is defined by a PHI:
16924 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
16925 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
16926 if (!AddendDef.isPHI())
16929 // Look for the following pattern:
16931 // %addend = phi [%entry, 0], [%loop, %result]
16933 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
16937 // %addend = phi [%entry, 0], [%loop, %result]
16939 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
16941 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
16942 assert(AddendDef.getOperand(i).isReg());
16943 MachineOperand PHISrcOp = AddendDef.getOperand(i);
16944 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
16945 if (&PHISrcInst == MI) {
16946 // Found a matching instruction.
16947 unsigned NewFMAOpc = 0;
16948 switch (MI->getOpcode()) {
16949 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
16950 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
16951 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
16952 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
16953 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
16954 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
16955 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
16956 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
16957 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
16958 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
16959 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
16960 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
16961 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
16962 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
16963 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
16964 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
16965 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
16966 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
16967 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
16968 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
16969 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
16970 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
16971 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
16972 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
16973 default: llvm_unreachable("Unrecognized FMA variant.");
16976 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
16977 MachineInstrBuilder MIB =
16978 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
16979 .addOperand(MI->getOperand(0))
16980 .addOperand(MI->getOperand(3))
16981 .addOperand(MI->getOperand(2))
16982 .addOperand(MI->getOperand(1));
16983 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
16984 MI->eraseFromParent();
16991 MachineBasicBlock *
16992 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
16993 MachineBasicBlock *BB) const {
16994 switch (MI->getOpcode()) {
16995 default: llvm_unreachable("Unexpected instr type to insert");
16996 case X86::TAILJMPd64:
16997 case X86::TAILJMPr64:
16998 case X86::TAILJMPm64:
16999 llvm_unreachable("TAILJMP64 would not be touched here.");
17000 case X86::TCRETURNdi64:
17001 case X86::TCRETURNri64:
17002 case X86::TCRETURNmi64:
17004 case X86::WIN_ALLOCA:
17005 return EmitLoweredWinAlloca(MI, BB);
17006 case X86::SEG_ALLOCA_32:
17007 return EmitLoweredSegAlloca(MI, BB, false);
17008 case X86::SEG_ALLOCA_64:
17009 return EmitLoweredSegAlloca(MI, BB, true);
17010 case X86::TLSCall_32:
17011 case X86::TLSCall_64:
17012 return EmitLoweredTLSCall(MI, BB);
17013 case X86::CMOV_GR8:
17014 case X86::CMOV_FR32:
17015 case X86::CMOV_FR64:
17016 case X86::CMOV_V4F32:
17017 case X86::CMOV_V2F64:
17018 case X86::CMOV_V2I64:
17019 case X86::CMOV_V8F32:
17020 case X86::CMOV_V4F64:
17021 case X86::CMOV_V4I64:
17022 case X86::CMOV_V16F32:
17023 case X86::CMOV_V8F64:
17024 case X86::CMOV_V8I64:
17025 case X86::CMOV_GR16:
17026 case X86::CMOV_GR32:
17027 case X86::CMOV_RFP32:
17028 case X86::CMOV_RFP64:
17029 case X86::CMOV_RFP80:
17030 return EmitLoweredSelect(MI, BB);
17032 case X86::FP32_TO_INT16_IN_MEM:
17033 case X86::FP32_TO_INT32_IN_MEM:
17034 case X86::FP32_TO_INT64_IN_MEM:
17035 case X86::FP64_TO_INT16_IN_MEM:
17036 case X86::FP64_TO_INT32_IN_MEM:
17037 case X86::FP64_TO_INT64_IN_MEM:
17038 case X86::FP80_TO_INT16_IN_MEM:
17039 case X86::FP80_TO_INT32_IN_MEM:
17040 case X86::FP80_TO_INT64_IN_MEM: {
17041 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
17042 DebugLoc DL = MI->getDebugLoc();
17044 // Change the floating point control register to use "round towards zero"
17045 // mode when truncating to an integer value.
17046 MachineFunction *F = BB->getParent();
17047 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
17048 addFrameReference(BuildMI(*BB, MI, DL,
17049 TII->get(X86::FNSTCW16m)), CWFrameIdx);
17051 // Load the old value of the high byte of the control word...
17053 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
17054 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
17057 // Set the high part to be round to zero...
17058 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
17061 // Reload the modified control word now...
17062 addFrameReference(BuildMI(*BB, MI, DL,
17063 TII->get(X86::FLDCW16m)), CWFrameIdx);
17065 // Restore the memory image of control word to original value
17066 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
17069 // Get the X86 opcode to use.
17071 switch (MI->getOpcode()) {
17072 default: llvm_unreachable("illegal opcode!");
17073 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
17074 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
17075 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
17076 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
17077 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
17078 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
17079 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
17080 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
17081 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
17085 MachineOperand &Op = MI->getOperand(0);
17087 AM.BaseType = X86AddressMode::RegBase;
17088 AM.Base.Reg = Op.getReg();
17090 AM.BaseType = X86AddressMode::FrameIndexBase;
17091 AM.Base.FrameIndex = Op.getIndex();
17093 Op = MI->getOperand(1);
17095 AM.Scale = Op.getImm();
17096 Op = MI->getOperand(2);
17098 AM.IndexReg = Op.getImm();
17099 Op = MI->getOperand(3);
17100 if (Op.isGlobal()) {
17101 AM.GV = Op.getGlobal();
17103 AM.Disp = Op.getImm();
17105 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
17106 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
17108 // Reload the original control word now.
17109 addFrameReference(BuildMI(*BB, MI, DL,
17110 TII->get(X86::FLDCW16m)), CWFrameIdx);
17112 MI->eraseFromParent(); // The pseudo instruction is gone now.
17115 // String/text processing lowering.
17116 case X86::PCMPISTRM128REG:
17117 case X86::VPCMPISTRM128REG:
17118 case X86::PCMPISTRM128MEM:
17119 case X86::VPCMPISTRM128MEM:
17120 case X86::PCMPESTRM128REG:
17121 case X86::VPCMPESTRM128REG:
17122 case X86::PCMPESTRM128MEM:
17123 case X86::VPCMPESTRM128MEM:
17124 assert(Subtarget->hasSSE42() &&
17125 "Target must have SSE4.2 or AVX features enabled");
17126 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
17128 // String/text processing lowering.
17129 case X86::PCMPISTRIREG:
17130 case X86::VPCMPISTRIREG:
17131 case X86::PCMPISTRIMEM:
17132 case X86::VPCMPISTRIMEM:
17133 case X86::PCMPESTRIREG:
17134 case X86::VPCMPESTRIREG:
17135 case X86::PCMPESTRIMEM:
17136 case X86::VPCMPESTRIMEM:
17137 assert(Subtarget->hasSSE42() &&
17138 "Target must have SSE4.2 or AVX features enabled");
17139 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
17141 // Thread synchronization.
17143 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
17147 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
17149 // Atomic Lowering.
17150 case X86::ATOMAND8:
17151 case X86::ATOMAND16:
17152 case X86::ATOMAND32:
17153 case X86::ATOMAND64:
17156 case X86::ATOMOR16:
17157 case X86::ATOMOR32:
17158 case X86::ATOMOR64:
17160 case X86::ATOMXOR16:
17161 case X86::ATOMXOR8:
17162 case X86::ATOMXOR32:
17163 case X86::ATOMXOR64:
17165 case X86::ATOMNAND8:
17166 case X86::ATOMNAND16:
17167 case X86::ATOMNAND32:
17168 case X86::ATOMNAND64:
17170 case X86::ATOMMAX8:
17171 case X86::ATOMMAX16:
17172 case X86::ATOMMAX32:
17173 case X86::ATOMMAX64:
17175 case X86::ATOMMIN8:
17176 case X86::ATOMMIN16:
17177 case X86::ATOMMIN32:
17178 case X86::ATOMMIN64:
17180 case X86::ATOMUMAX8:
17181 case X86::ATOMUMAX16:
17182 case X86::ATOMUMAX32:
17183 case X86::ATOMUMAX64:
17185 case X86::ATOMUMIN8:
17186 case X86::ATOMUMIN16:
17187 case X86::ATOMUMIN32:
17188 case X86::ATOMUMIN64:
17189 return EmitAtomicLoadArith(MI, BB);
17191 // This group does 64-bit operations on a 32-bit host.
17192 case X86::ATOMAND6432:
17193 case X86::ATOMOR6432:
17194 case X86::ATOMXOR6432:
17195 case X86::ATOMNAND6432:
17196 case X86::ATOMADD6432:
17197 case X86::ATOMSUB6432:
17198 case X86::ATOMMAX6432:
17199 case X86::ATOMMIN6432:
17200 case X86::ATOMUMAX6432:
17201 case X86::ATOMUMIN6432:
17202 case X86::ATOMSWAP6432:
17203 return EmitAtomicLoadArith6432(MI, BB);
17205 case X86::VASTART_SAVE_XMM_REGS:
17206 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
17208 case X86::VAARG_64:
17209 return EmitVAARG64WithCustomInserter(MI, BB);
17211 case X86::EH_SjLj_SetJmp32:
17212 case X86::EH_SjLj_SetJmp64:
17213 return emitEHSjLjSetJmp(MI, BB);
17215 case X86::EH_SjLj_LongJmp32:
17216 case X86::EH_SjLj_LongJmp64:
17217 return emitEHSjLjLongJmp(MI, BB);
17219 case TargetOpcode::STACKMAP:
17220 case TargetOpcode::PATCHPOINT:
17221 return emitPatchPoint(MI, BB);
17223 case X86::VFMADDPDr213r:
17224 case X86::VFMADDPSr213r:
17225 case X86::VFMADDSDr213r:
17226 case X86::VFMADDSSr213r:
17227 case X86::VFMSUBPDr213r:
17228 case X86::VFMSUBPSr213r:
17229 case X86::VFMSUBSDr213r:
17230 case X86::VFMSUBSSr213r:
17231 case X86::VFNMADDPDr213r:
17232 case X86::VFNMADDPSr213r:
17233 case X86::VFNMADDSDr213r:
17234 case X86::VFNMADDSSr213r:
17235 case X86::VFNMSUBPDr213r:
17236 case X86::VFNMSUBPSr213r:
17237 case X86::VFNMSUBSDr213r:
17238 case X86::VFNMSUBSSr213r:
17239 case X86::VFMADDPDr213rY:
17240 case X86::VFMADDPSr213rY:
17241 case X86::VFMSUBPDr213rY:
17242 case X86::VFMSUBPSr213rY:
17243 case X86::VFNMADDPDr213rY:
17244 case X86::VFNMADDPSr213rY:
17245 case X86::VFNMSUBPDr213rY:
17246 case X86::VFNMSUBPSr213rY:
17247 return emitFMA3Instr(MI, BB);
17251 //===----------------------------------------------------------------------===//
17252 // X86 Optimization Hooks
17253 //===----------------------------------------------------------------------===//
17255 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
17258 const SelectionDAG &DAG,
17259 unsigned Depth) const {
17260 unsigned BitWidth = KnownZero.getBitWidth();
17261 unsigned Opc = Op.getOpcode();
17262 assert((Opc >= ISD::BUILTIN_OP_END ||
17263 Opc == ISD::INTRINSIC_WO_CHAIN ||
17264 Opc == ISD::INTRINSIC_W_CHAIN ||
17265 Opc == ISD::INTRINSIC_VOID) &&
17266 "Should use MaskedValueIsZero if you don't know whether Op"
17267 " is a target node!");
17269 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
17283 // These nodes' second result is a boolean.
17284 if (Op.getResNo() == 0)
17287 case X86ISD::SETCC:
17288 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
17290 case ISD::INTRINSIC_WO_CHAIN: {
17291 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17292 unsigned NumLoBits = 0;
17295 case Intrinsic::x86_sse_movmsk_ps:
17296 case Intrinsic::x86_avx_movmsk_ps_256:
17297 case Intrinsic::x86_sse2_movmsk_pd:
17298 case Intrinsic::x86_avx_movmsk_pd_256:
17299 case Intrinsic::x86_mmx_pmovmskb:
17300 case Intrinsic::x86_sse2_pmovmskb_128:
17301 case Intrinsic::x86_avx2_pmovmskb: {
17302 // High bits of movmskp{s|d}, pmovmskb are known zero.
17304 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17305 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
17306 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
17307 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
17308 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
17309 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
17310 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
17311 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
17313 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
17322 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
17324 const SelectionDAG &,
17325 unsigned Depth) const {
17326 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
17327 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
17328 return Op.getValueType().getScalarType().getSizeInBits();
17334 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
17335 /// node is a GlobalAddress + offset.
17336 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
17337 const GlobalValue* &GA,
17338 int64_t &Offset) const {
17339 if (N->getOpcode() == X86ISD::Wrapper) {
17340 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
17341 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
17342 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
17346 return TargetLowering::isGAPlusOffset(N, GA, Offset);
17349 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
17350 /// same as extracting the high 128-bit part of 256-bit vector and then
17351 /// inserting the result into the low part of a new 256-bit vector
17352 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
17353 EVT VT = SVOp->getValueType(0);
17354 unsigned NumElems = VT.getVectorNumElements();
17356 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
17357 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
17358 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
17359 SVOp->getMaskElt(j) >= 0)
17365 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
17366 /// same as extracting the low 128-bit part of 256-bit vector and then
17367 /// inserting the result into the high part of a new 256-bit vector
17368 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
17369 EVT VT = SVOp->getValueType(0);
17370 unsigned NumElems = VT.getVectorNumElements();
17372 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
17373 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
17374 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
17375 SVOp->getMaskElt(j) >= 0)
17381 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
17382 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
17383 TargetLowering::DAGCombinerInfo &DCI,
17384 const X86Subtarget* Subtarget) {
17386 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
17387 SDValue V1 = SVOp->getOperand(0);
17388 SDValue V2 = SVOp->getOperand(1);
17389 EVT VT = SVOp->getValueType(0);
17390 unsigned NumElems = VT.getVectorNumElements();
17392 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
17393 V2.getOpcode() == ISD::CONCAT_VECTORS) {
17397 // V UNDEF BUILD_VECTOR UNDEF
17399 // CONCAT_VECTOR CONCAT_VECTOR
17402 // RESULT: V + zero extended
17404 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
17405 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
17406 V1.getOperand(1).getOpcode() != ISD::UNDEF)
17409 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
17412 // To match the shuffle mask, the first half of the mask should
17413 // be exactly the first vector, and all the rest a splat with the
17414 // first element of the second one.
17415 for (unsigned i = 0; i != NumElems/2; ++i)
17416 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
17417 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
17420 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
17421 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
17422 if (Ld->hasNUsesOfValue(1, 0)) {
17423 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
17424 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
17426 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
17428 Ld->getPointerInfo(),
17429 Ld->getAlignment(),
17430 false/*isVolatile*/, true/*ReadMem*/,
17431 false/*WriteMem*/);
17433 // Make sure the newly-created LOAD is in the same position as Ld in
17434 // terms of dependency. We create a TokenFactor for Ld and ResNode,
17435 // and update uses of Ld's output chain to use the TokenFactor.
17436 if (Ld->hasAnyUseOfValue(1)) {
17437 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17438 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
17439 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
17440 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
17441 SDValue(ResNode.getNode(), 1));
17444 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
17448 // Emit a zeroed vector and insert the desired subvector on its
17450 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17451 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
17452 return DCI.CombineTo(N, InsV);
17455 //===--------------------------------------------------------------------===//
17456 // Combine some shuffles into subvector extracts and inserts:
17459 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
17460 if (isShuffleHigh128VectorInsertLow(SVOp)) {
17461 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
17462 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
17463 return DCI.CombineTo(N, InsV);
17466 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
17467 if (isShuffleLow128VectorInsertHigh(SVOp)) {
17468 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
17469 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
17470 return DCI.CombineTo(N, InsV);
17476 /// PerformShuffleCombine - Performs several different shuffle combines.
17477 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
17478 TargetLowering::DAGCombinerInfo &DCI,
17479 const X86Subtarget *Subtarget) {
17481 EVT VT = N->getValueType(0);
17483 // Don't create instructions with illegal types after legalize types has run.
17484 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17485 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
17488 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
17489 if (Subtarget->hasFp256() && VT.is256BitVector() &&
17490 N->getOpcode() == ISD::VECTOR_SHUFFLE)
17491 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
17493 // Only handle 128 wide vector from here on.
17494 if (!VT.is128BitVector())
17497 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
17498 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
17499 // consecutive, non-overlapping, and in the right order.
17500 SmallVector<SDValue, 16> Elts;
17501 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
17502 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
17504 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
17507 /// PerformTruncateCombine - Converts truncate operation to
17508 /// a sequence of vector shuffle operations.
17509 /// It is possible when we truncate 256-bit vector to 128-bit vector
17510 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
17511 TargetLowering::DAGCombinerInfo &DCI,
17512 const X86Subtarget *Subtarget) {
17516 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
17517 /// specific shuffle of a load can be folded into a single element load.
17518 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
17519 /// shuffles have been customed lowered so we need to handle those here.
17520 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
17521 TargetLowering::DAGCombinerInfo &DCI) {
17522 if (DCI.isBeforeLegalizeOps())
17525 SDValue InVec = N->getOperand(0);
17526 SDValue EltNo = N->getOperand(1);
17528 if (!isa<ConstantSDNode>(EltNo))
17531 EVT VT = InVec.getValueType();
17533 bool HasShuffleIntoBitcast = false;
17534 if (InVec.getOpcode() == ISD::BITCAST) {
17535 // Don't duplicate a load with other uses.
17536 if (!InVec.hasOneUse())
17538 EVT BCVT = InVec.getOperand(0).getValueType();
17539 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
17541 InVec = InVec.getOperand(0);
17542 HasShuffleIntoBitcast = true;
17545 if (!isTargetShuffle(InVec.getOpcode()))
17548 // Don't duplicate a load with other uses.
17549 if (!InVec.hasOneUse())
17552 SmallVector<int, 16> ShuffleMask;
17554 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
17558 // Select the input vector, guarding against out of range extract vector.
17559 unsigned NumElems = VT.getVectorNumElements();
17560 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
17561 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
17562 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
17563 : InVec.getOperand(1);
17565 // If inputs to shuffle are the same for both ops, then allow 2 uses
17566 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
17568 if (LdNode.getOpcode() == ISD::BITCAST) {
17569 // Don't duplicate a load with other uses.
17570 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
17573 AllowedUses = 1; // only allow 1 load use if we have a bitcast
17574 LdNode = LdNode.getOperand(0);
17577 if (!ISD::isNormalLoad(LdNode.getNode()))
17580 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
17582 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
17585 if (HasShuffleIntoBitcast) {
17586 // If there's a bitcast before the shuffle, check if the load type and
17587 // alignment is valid.
17588 unsigned Align = LN0->getAlignment();
17589 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17590 unsigned NewAlign = TLI.getDataLayout()->
17591 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
17593 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
17597 // All checks match so transform back to vector_shuffle so that DAG combiner
17598 // can finish the job
17601 // Create shuffle node taking into account the case that its a unary shuffle
17602 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
17603 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
17604 InVec.getOperand(0), Shuffle,
17606 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
17607 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
17611 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
17612 /// generation and convert it from being a bunch of shuffles and extracts
17613 /// to a simple store and scalar loads to extract the elements.
17614 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
17615 TargetLowering::DAGCombinerInfo &DCI) {
17616 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
17617 if (NewOp.getNode())
17620 SDValue InputVector = N->getOperand(0);
17622 // Detect whether we are trying to convert from mmx to i32 and the bitcast
17623 // from mmx to v2i32 has a single usage.
17624 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
17625 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
17626 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
17627 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
17628 N->getValueType(0),
17629 InputVector.getNode()->getOperand(0));
17631 // Only operate on vectors of 4 elements, where the alternative shuffling
17632 // gets to be more expensive.
17633 if (InputVector.getValueType() != MVT::v4i32)
17636 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
17637 // single use which is a sign-extend or zero-extend, and all elements are
17639 SmallVector<SDNode *, 4> Uses;
17640 unsigned ExtractedElements = 0;
17641 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
17642 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
17643 if (UI.getUse().getResNo() != InputVector.getResNo())
17646 SDNode *Extract = *UI;
17647 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
17650 if (Extract->getValueType(0) != MVT::i32)
17652 if (!Extract->hasOneUse())
17654 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
17655 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
17657 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
17660 // Record which element was extracted.
17661 ExtractedElements |=
17662 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
17664 Uses.push_back(Extract);
17667 // If not all the elements were used, this may not be worthwhile.
17668 if (ExtractedElements != 15)
17671 // Ok, we've now decided to do the transformation.
17672 SDLoc dl(InputVector);
17674 // Store the value to a temporary stack slot.
17675 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
17676 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
17677 MachinePointerInfo(), false, false, 0);
17679 // Replace each use (extract) with a load of the appropriate element.
17680 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
17681 UE = Uses.end(); UI != UE; ++UI) {
17682 SDNode *Extract = *UI;
17684 // cOMpute the element's address.
17685 SDValue Idx = Extract->getOperand(1);
17687 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
17688 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
17689 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17690 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
17692 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
17693 StackPtr, OffsetVal);
17695 // Load the scalar.
17696 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
17697 ScalarAddr, MachinePointerInfo(),
17698 false, false, false, 0);
17700 // Replace the exact with the load.
17701 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
17704 // The replacement was made in place; don't return anything.
17708 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
17709 static std::pair<unsigned, bool>
17710 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
17711 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
17712 if (!VT.isVector())
17713 return std::make_pair(0, false);
17715 bool NeedSplit = false;
17716 switch (VT.getSimpleVT().SimpleTy) {
17717 default: return std::make_pair(0, false);
17721 if (!Subtarget->hasAVX2())
17723 if (!Subtarget->hasAVX())
17724 return std::make_pair(0, false);
17729 if (!Subtarget->hasSSE2())
17730 return std::make_pair(0, false);
17733 // SSE2 has only a small subset of the operations.
17734 bool hasUnsigned = Subtarget->hasSSE41() ||
17735 (Subtarget->hasSSE2() && VT == MVT::v16i8);
17736 bool hasSigned = Subtarget->hasSSE41() ||
17737 (Subtarget->hasSSE2() && VT == MVT::v8i16);
17739 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17742 // Check for x CC y ? x : y.
17743 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17744 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17749 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
17752 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
17755 Opc = hasSigned ? X86ISD::SMIN : 0; break;
17758 Opc = hasSigned ? X86ISD::SMAX : 0; break;
17760 // Check for x CC y ? y : x -- a min/max with reversed arms.
17761 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
17762 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
17767 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
17770 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
17773 Opc = hasSigned ? X86ISD::SMAX : 0; break;
17776 Opc = hasSigned ? X86ISD::SMIN : 0; break;
17780 return std::make_pair(Opc, NeedSplit);
17784 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
17785 const X86Subtarget *Subtarget) {
17787 SDValue Cond = N->getOperand(0);
17788 SDValue LHS = N->getOperand(1);
17789 SDValue RHS = N->getOperand(2);
17791 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
17792 SDValue CondSrc = Cond->getOperand(0);
17793 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
17794 Cond = CondSrc->getOperand(0);
17797 MVT VT = N->getSimpleValueType(0);
17798 MVT EltVT = VT.getVectorElementType();
17799 unsigned NumElems = VT.getVectorNumElements();
17800 // There is no blend with immediate in AVX-512.
17801 if (VT.is512BitVector())
17804 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
17806 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
17809 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
17812 unsigned MaskValue = 0;
17813 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
17816 SmallVector<int, 8> ShuffleMask(NumElems, -1);
17817 for (unsigned i = 0; i < NumElems; ++i) {
17818 // Be sure we emit undef where we can.
17819 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
17820 ShuffleMask[i] = -1;
17822 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
17825 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
17828 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
17830 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
17831 TargetLowering::DAGCombinerInfo &DCI,
17832 const X86Subtarget *Subtarget) {
17834 SDValue Cond = N->getOperand(0);
17835 // Get the LHS/RHS of the select.
17836 SDValue LHS = N->getOperand(1);
17837 SDValue RHS = N->getOperand(2);
17838 EVT VT = LHS.getValueType();
17839 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17841 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
17842 // instructions match the semantics of the common C idiom x<y?x:y but not
17843 // x<=y?x:y, because of how they handle negative zero (which can be
17844 // ignored in unsafe-math mode).
17845 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
17846 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
17847 (Subtarget->hasSSE2() ||
17848 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
17849 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17851 unsigned Opcode = 0;
17852 // Check for x CC y ? x : y.
17853 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17854 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17858 // Converting this to a min would handle NaNs incorrectly, and swapping
17859 // the operands would cause it to handle comparisons between positive
17860 // and negative zero incorrectly.
17861 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
17862 if (!DAG.getTarget().Options.UnsafeFPMath &&
17863 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
17865 std::swap(LHS, RHS);
17867 Opcode = X86ISD::FMIN;
17870 // Converting this to a min would handle comparisons between positive
17871 // and negative zero incorrectly.
17872 if (!DAG.getTarget().Options.UnsafeFPMath &&
17873 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
17875 Opcode = X86ISD::FMIN;
17878 // Converting this to a min would handle both negative zeros and NaNs
17879 // incorrectly, but we can swap the operands to fix both.
17880 std::swap(LHS, RHS);
17884 Opcode = X86ISD::FMIN;
17888 // Converting this to a max would handle comparisons between positive
17889 // and negative zero incorrectly.
17890 if (!DAG.getTarget().Options.UnsafeFPMath &&
17891 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
17893 Opcode = X86ISD::FMAX;
17896 // Converting this to a max would handle NaNs incorrectly, and swapping
17897 // the operands would cause it to handle comparisons between positive
17898 // and negative zero incorrectly.
17899 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
17900 if (!DAG.getTarget().Options.UnsafeFPMath &&
17901 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
17903 std::swap(LHS, RHS);
17905 Opcode = X86ISD::FMAX;
17908 // Converting this to a max would handle both negative zeros and NaNs
17909 // incorrectly, but we can swap the operands to fix both.
17910 std::swap(LHS, RHS);
17914 Opcode = X86ISD::FMAX;
17917 // Check for x CC y ? y : x -- a min/max with reversed arms.
17918 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
17919 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
17923 // Converting this to a min would handle comparisons between positive
17924 // and negative zero incorrectly, and swapping the operands would
17925 // cause it to handle NaNs incorrectly.
17926 if (!DAG.getTarget().Options.UnsafeFPMath &&
17927 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
17928 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17930 std::swap(LHS, RHS);
17932 Opcode = X86ISD::FMIN;
17935 // Converting this to a min would handle NaNs incorrectly.
17936 if (!DAG.getTarget().Options.UnsafeFPMath &&
17937 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
17939 Opcode = X86ISD::FMIN;
17942 // Converting this to a min would handle both negative zeros and NaNs
17943 // incorrectly, but we can swap the operands to fix both.
17944 std::swap(LHS, RHS);
17948 Opcode = X86ISD::FMIN;
17952 // Converting this to a max would handle NaNs incorrectly.
17953 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17955 Opcode = X86ISD::FMAX;
17958 // Converting this to a max would handle comparisons between positive
17959 // and negative zero incorrectly, and swapping the operands would
17960 // cause it to handle NaNs incorrectly.
17961 if (!DAG.getTarget().Options.UnsafeFPMath &&
17962 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
17963 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17965 std::swap(LHS, RHS);
17967 Opcode = X86ISD::FMAX;
17970 // Converting this to a max would handle both negative zeros and NaNs
17971 // incorrectly, but we can swap the operands to fix both.
17972 std::swap(LHS, RHS);
17976 Opcode = X86ISD::FMAX;
17982 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
17985 EVT CondVT = Cond.getValueType();
17986 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
17987 CondVT.getVectorElementType() == MVT::i1) {
17988 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
17989 // lowering on AVX-512. In this case we convert it to
17990 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
17991 // The same situation for all 128 and 256-bit vectors of i8 and i16
17992 EVT OpVT = LHS.getValueType();
17993 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
17994 (OpVT.getVectorElementType() == MVT::i8 ||
17995 OpVT.getVectorElementType() == MVT::i16)) {
17996 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
17997 DCI.AddToWorklist(Cond.getNode());
17998 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
18001 // If this is a select between two integer constants, try to do some
18003 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
18004 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
18005 // Don't do this for crazy integer types.
18006 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
18007 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
18008 // so that TrueC (the true value) is larger than FalseC.
18009 bool NeedsCondInvert = false;
18011 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
18012 // Efficiently invertible.
18013 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
18014 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
18015 isa<ConstantSDNode>(Cond.getOperand(1))))) {
18016 NeedsCondInvert = true;
18017 std::swap(TrueC, FalseC);
18020 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
18021 if (FalseC->getAPIntValue() == 0 &&
18022 TrueC->getAPIntValue().isPowerOf2()) {
18023 if (NeedsCondInvert) // Invert the condition if needed.
18024 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
18025 DAG.getConstant(1, Cond.getValueType()));
18027 // Zero extend the condition if needed.
18028 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
18030 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
18031 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
18032 DAG.getConstant(ShAmt, MVT::i8));
18035 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
18036 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
18037 if (NeedsCondInvert) // Invert the condition if needed.
18038 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
18039 DAG.getConstant(1, Cond.getValueType()));
18041 // Zero extend the condition if needed.
18042 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
18043 FalseC->getValueType(0), Cond);
18044 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
18045 SDValue(FalseC, 0));
18048 // Optimize cases that will turn into an LEA instruction. This requires
18049 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
18050 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
18051 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
18052 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
18054 bool isFastMultiplier = false;
18056 switch ((unsigned char)Diff) {
18058 case 1: // result = add base, cond
18059 case 2: // result = lea base( , cond*2)
18060 case 3: // result = lea base(cond, cond*2)
18061 case 4: // result = lea base( , cond*4)
18062 case 5: // result = lea base(cond, cond*4)
18063 case 8: // result = lea base( , cond*8)
18064 case 9: // result = lea base(cond, cond*8)
18065 isFastMultiplier = true;
18070 if (isFastMultiplier) {
18071 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
18072 if (NeedsCondInvert) // Invert the condition if needed.
18073 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
18074 DAG.getConstant(1, Cond.getValueType()));
18076 // Zero extend the condition if needed.
18077 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
18079 // Scale the condition by the difference.
18081 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
18082 DAG.getConstant(Diff, Cond.getValueType()));
18084 // Add the base if non-zero.
18085 if (FalseC->getAPIntValue() != 0)
18086 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
18087 SDValue(FalseC, 0));
18094 // Canonicalize max and min:
18095 // (x > y) ? x : y -> (x >= y) ? x : y
18096 // (x < y) ? x : y -> (x <= y) ? x : y
18097 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
18098 // the need for an extra compare
18099 // against zero. e.g.
18100 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
18102 // testl %edi, %edi
18104 // cmovgl %edi, %eax
18108 // cmovsl %eax, %edi
18109 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
18110 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
18111 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
18112 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
18117 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
18118 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
18119 Cond.getOperand(0), Cond.getOperand(1), NewCC);
18120 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
18125 // Early exit check
18126 if (!TLI.isTypeLegal(VT))
18129 // Match VSELECTs into subs with unsigned saturation.
18130 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
18131 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
18132 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
18133 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
18134 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
18136 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
18137 // left side invert the predicate to simplify logic below.
18139 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
18141 CC = ISD::getSetCCInverse(CC, true);
18142 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
18146 if (Other.getNode() && Other->getNumOperands() == 2 &&
18147 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
18148 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
18149 SDValue CondRHS = Cond->getOperand(1);
18151 // Look for a general sub with unsigned saturation first.
18152 // x >= y ? x-y : 0 --> subus x, y
18153 // x > y ? x-y : 0 --> subus x, y
18154 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
18155 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
18156 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
18158 // If the RHS is a constant we have to reverse the const canonicalization.
18159 // x > C-1 ? x+-C : 0 --> subus x, C
18160 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
18161 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
18162 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
18163 if (CondRHS.getConstantOperandVal(0) == -A-1)
18164 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
18165 DAG.getConstant(-A, VT));
18168 // Another special case: If C was a sign bit, the sub has been
18169 // canonicalized into a xor.
18170 // FIXME: Would it be better to use computeKnownBits to determine whether
18171 // it's safe to decanonicalize the xor?
18172 // x s< 0 ? x^C : 0 --> subus x, C
18173 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
18174 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
18175 isSplatVector(OpRHS.getNode())) {
18176 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
18178 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
18183 // Try to match a min/max vector operation.
18184 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
18185 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
18186 unsigned Opc = ret.first;
18187 bool NeedSplit = ret.second;
18189 if (Opc && NeedSplit) {
18190 unsigned NumElems = VT.getVectorNumElements();
18191 // Extract the LHS vectors
18192 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
18193 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
18195 // Extract the RHS vectors
18196 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
18197 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
18199 // Create min/max for each subvector
18200 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
18201 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
18203 // Merge the result
18204 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
18206 return DAG.getNode(Opc, DL, VT, LHS, RHS);
18209 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
18210 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
18211 // Check if SETCC has already been promoted
18212 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
18213 // Check that condition value type matches vselect operand type
18216 assert(Cond.getValueType().isVector() &&
18217 "vector select expects a vector selector!");
18219 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
18220 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
18222 if (!TValIsAllOnes && !FValIsAllZeros) {
18223 // Try invert the condition if true value is not all 1s and false value
18225 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
18226 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
18228 if (TValIsAllZeros || FValIsAllOnes) {
18229 SDValue CC = Cond.getOperand(2);
18230 ISD::CondCode NewCC =
18231 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
18232 Cond.getOperand(0).getValueType().isInteger());
18233 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
18234 std::swap(LHS, RHS);
18235 TValIsAllOnes = FValIsAllOnes;
18236 FValIsAllZeros = TValIsAllZeros;
18240 if (TValIsAllOnes || FValIsAllZeros) {
18243 if (TValIsAllOnes && FValIsAllZeros)
18245 else if (TValIsAllOnes)
18246 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
18247 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
18248 else if (FValIsAllZeros)
18249 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
18250 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
18252 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
18256 // Try to fold this VSELECT into a MOVSS/MOVSD
18257 if (N->getOpcode() == ISD::VSELECT &&
18258 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
18259 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
18260 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
18261 bool CanFold = false;
18262 unsigned NumElems = Cond.getNumOperands();
18266 if (isZero(Cond.getOperand(0))) {
18269 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
18270 // fold (vselect <0,-1> -> (movsd A, B)
18271 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
18272 CanFold = isAllOnes(Cond.getOperand(i));
18273 } else if (isAllOnes(Cond.getOperand(0))) {
18277 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
18278 // fold (vselect <-1,0> -> (movsd B, A)
18279 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
18280 CanFold = isZero(Cond.getOperand(i));
18284 if (VT == MVT::v4i32 || VT == MVT::v4f32)
18285 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
18286 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
18289 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
18290 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
18291 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
18292 // (v2i64 (bitcast B)))))
18294 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
18295 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
18296 // (v2f64 (bitcast B)))))
18298 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
18299 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
18300 // (v2i64 (bitcast A)))))
18302 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
18303 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
18304 // (v2f64 (bitcast A)))))
18306 CanFold = (isZero(Cond.getOperand(0)) &&
18307 isZero(Cond.getOperand(1)) &&
18308 isAllOnes(Cond.getOperand(2)) &&
18309 isAllOnes(Cond.getOperand(3)));
18311 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
18312 isAllOnes(Cond.getOperand(1)) &&
18313 isZero(Cond.getOperand(2)) &&
18314 isZero(Cond.getOperand(3))) {
18316 std::swap(LHS, RHS);
18320 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
18321 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
18322 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
18323 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
18325 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
18331 // If we know that this node is legal then we know that it is going to be
18332 // matched by one of the SSE/AVX BLEND instructions. These instructions only
18333 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
18334 // to simplify previous instructions.
18335 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
18336 !DCI.isBeforeLegalize() &&
18337 // We explicitly check against v8i16 and v16i16 because, although
18338 // they're marked as Custom, they might only be legal when Cond is a
18339 // build_vector of constants. This will be taken care in a later
18341 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
18342 VT != MVT::v8i16)) {
18343 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
18345 // Don't optimize vector selects that map to mask-registers.
18349 // Check all uses of that condition operand to check whether it will be
18350 // consumed by non-BLEND instructions, which may depend on all bits are set
18352 for (SDNode::use_iterator I = Cond->use_begin(),
18353 E = Cond->use_end(); I != E; ++I)
18354 if (I->getOpcode() != ISD::VSELECT)
18355 // TODO: Add other opcodes eventually lowered into BLEND.
18358 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
18359 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
18361 APInt KnownZero, KnownOne;
18362 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
18363 DCI.isBeforeLegalizeOps());
18364 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
18365 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
18366 DCI.CommitTargetLoweringOpt(TLO);
18369 // We should generate an X86ISD::BLENDI from a vselect if its argument
18370 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
18371 // constants. This specific pattern gets generated when we split a
18372 // selector for a 512 bit vector in a machine without AVX512 (but with
18373 // 256-bit vectors), during legalization:
18375 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
18377 // Iff we find this pattern and the build_vectors are built from
18378 // constants, we translate the vselect into a shuffle_vector that we
18379 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
18380 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
18381 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
18382 if (Shuffle.getNode())
18389 // Check whether a boolean test is testing a boolean value generated by
18390 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
18393 // Simplify the following patterns:
18394 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
18395 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
18396 // to (Op EFLAGS Cond)
18398 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
18399 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
18400 // to (Op EFLAGS !Cond)
18402 // where Op could be BRCOND or CMOV.
18404 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
18405 // Quit if not CMP and SUB with its value result used.
18406 if (Cmp.getOpcode() != X86ISD::CMP &&
18407 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
18410 // Quit if not used as a boolean value.
18411 if (CC != X86::COND_E && CC != X86::COND_NE)
18414 // Check CMP operands. One of them should be 0 or 1 and the other should be
18415 // an SetCC or extended from it.
18416 SDValue Op1 = Cmp.getOperand(0);
18417 SDValue Op2 = Cmp.getOperand(1);
18420 const ConstantSDNode* C = nullptr;
18421 bool needOppositeCond = (CC == X86::COND_E);
18422 bool checkAgainstTrue = false; // Is it a comparison against 1?
18424 if ((C = dyn_cast<ConstantSDNode>(Op1)))
18426 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
18428 else // Quit if all operands are not constants.
18431 if (C->getZExtValue() == 1) {
18432 needOppositeCond = !needOppositeCond;
18433 checkAgainstTrue = true;
18434 } else if (C->getZExtValue() != 0)
18435 // Quit if the constant is neither 0 or 1.
18438 bool truncatedToBoolWithAnd = false;
18439 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
18440 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
18441 SetCC.getOpcode() == ISD::TRUNCATE ||
18442 SetCC.getOpcode() == ISD::AND) {
18443 if (SetCC.getOpcode() == ISD::AND) {
18445 ConstantSDNode *CS;
18446 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
18447 CS->getZExtValue() == 1)
18449 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
18450 CS->getZExtValue() == 1)
18454 SetCC = SetCC.getOperand(OpIdx);
18455 truncatedToBoolWithAnd = true;
18457 SetCC = SetCC.getOperand(0);
18460 switch (SetCC.getOpcode()) {
18461 case X86ISD::SETCC_CARRY:
18462 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
18463 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
18464 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
18465 // truncated to i1 using 'and'.
18466 if (checkAgainstTrue && !truncatedToBoolWithAnd)
18468 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
18469 "Invalid use of SETCC_CARRY!");
18471 case X86ISD::SETCC:
18472 // Set the condition code or opposite one if necessary.
18473 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
18474 if (needOppositeCond)
18475 CC = X86::GetOppositeBranchCondition(CC);
18476 return SetCC.getOperand(1);
18477 case X86ISD::CMOV: {
18478 // Check whether false/true value has canonical one, i.e. 0 or 1.
18479 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
18480 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
18481 // Quit if true value is not a constant.
18484 // Quit if false value is not a constant.
18486 SDValue Op = SetCC.getOperand(0);
18487 // Skip 'zext' or 'trunc' node.
18488 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
18489 Op.getOpcode() == ISD::TRUNCATE)
18490 Op = Op.getOperand(0);
18491 // A special case for rdrand/rdseed, where 0 is set if false cond is
18493 if ((Op.getOpcode() != X86ISD::RDRAND &&
18494 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
18497 // Quit if false value is not the constant 0 or 1.
18498 bool FValIsFalse = true;
18499 if (FVal && FVal->getZExtValue() != 0) {
18500 if (FVal->getZExtValue() != 1)
18502 // If FVal is 1, opposite cond is needed.
18503 needOppositeCond = !needOppositeCond;
18504 FValIsFalse = false;
18506 // Quit if TVal is not the constant opposite of FVal.
18507 if (FValIsFalse && TVal->getZExtValue() != 1)
18509 if (!FValIsFalse && TVal->getZExtValue() != 0)
18511 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
18512 if (needOppositeCond)
18513 CC = X86::GetOppositeBranchCondition(CC);
18514 return SetCC.getOperand(3);
18521 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
18522 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
18523 TargetLowering::DAGCombinerInfo &DCI,
18524 const X86Subtarget *Subtarget) {
18527 // If the flag operand isn't dead, don't touch this CMOV.
18528 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
18531 SDValue FalseOp = N->getOperand(0);
18532 SDValue TrueOp = N->getOperand(1);
18533 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
18534 SDValue Cond = N->getOperand(3);
18536 if (CC == X86::COND_E || CC == X86::COND_NE) {
18537 switch (Cond.getOpcode()) {
18541 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
18542 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
18543 return (CC == X86::COND_E) ? FalseOp : TrueOp;
18549 Flags = checkBoolTestSetCCCombine(Cond, CC);
18550 if (Flags.getNode() &&
18551 // Extra check as FCMOV only supports a subset of X86 cond.
18552 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
18553 SDValue Ops[] = { FalseOp, TrueOp,
18554 DAG.getConstant(CC, MVT::i8), Flags };
18555 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
18558 // If this is a select between two integer constants, try to do some
18559 // optimizations. Note that the operands are ordered the opposite of SELECT
18561 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
18562 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
18563 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
18564 // larger than FalseC (the false value).
18565 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
18566 CC = X86::GetOppositeBranchCondition(CC);
18567 std::swap(TrueC, FalseC);
18568 std::swap(TrueOp, FalseOp);
18571 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
18572 // This is efficient for any integer data type (including i8/i16) and
18574 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
18575 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18576 DAG.getConstant(CC, MVT::i8), Cond);
18578 // Zero extend the condition if needed.
18579 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
18581 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
18582 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
18583 DAG.getConstant(ShAmt, MVT::i8));
18584 if (N->getNumValues() == 2) // Dead flag value?
18585 return DCI.CombineTo(N, Cond, SDValue());
18589 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
18590 // for any integer data type, including i8/i16.
18591 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
18592 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18593 DAG.getConstant(CC, MVT::i8), Cond);
18595 // Zero extend the condition if needed.
18596 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
18597 FalseC->getValueType(0), Cond);
18598 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
18599 SDValue(FalseC, 0));
18601 if (N->getNumValues() == 2) // Dead flag value?
18602 return DCI.CombineTo(N, Cond, SDValue());
18606 // Optimize cases that will turn into an LEA instruction. This requires
18607 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
18608 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
18609 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
18610 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
18612 bool isFastMultiplier = false;
18614 switch ((unsigned char)Diff) {
18616 case 1: // result = add base, cond
18617 case 2: // result = lea base( , cond*2)
18618 case 3: // result = lea base(cond, cond*2)
18619 case 4: // result = lea base( , cond*4)
18620 case 5: // result = lea base(cond, cond*4)
18621 case 8: // result = lea base( , cond*8)
18622 case 9: // result = lea base(cond, cond*8)
18623 isFastMultiplier = true;
18628 if (isFastMultiplier) {
18629 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
18630 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18631 DAG.getConstant(CC, MVT::i8), Cond);
18632 // Zero extend the condition if needed.
18633 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
18635 // Scale the condition by the difference.
18637 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
18638 DAG.getConstant(Diff, Cond.getValueType()));
18640 // Add the base if non-zero.
18641 if (FalseC->getAPIntValue() != 0)
18642 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
18643 SDValue(FalseC, 0));
18644 if (N->getNumValues() == 2) // Dead flag value?
18645 return DCI.CombineTo(N, Cond, SDValue());
18652 // Handle these cases:
18653 // (select (x != c), e, c) -> select (x != c), e, x),
18654 // (select (x == c), c, e) -> select (x == c), x, e)
18655 // where the c is an integer constant, and the "select" is the combination
18656 // of CMOV and CMP.
18658 // The rationale for this change is that the conditional-move from a constant
18659 // needs two instructions, however, conditional-move from a register needs
18660 // only one instruction.
18662 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
18663 // some instruction-combining opportunities. This opt needs to be
18664 // postponed as late as possible.
18666 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
18667 // the DCI.xxxx conditions are provided to postpone the optimization as
18668 // late as possible.
18670 ConstantSDNode *CmpAgainst = nullptr;
18671 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
18672 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
18673 !isa<ConstantSDNode>(Cond.getOperand(0))) {
18675 if (CC == X86::COND_NE &&
18676 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
18677 CC = X86::GetOppositeBranchCondition(CC);
18678 std::swap(TrueOp, FalseOp);
18681 if (CC == X86::COND_E &&
18682 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
18683 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
18684 DAG.getConstant(CC, MVT::i8), Cond };
18685 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
18693 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
18694 const X86Subtarget *Subtarget) {
18695 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
18697 default: return SDValue();
18698 // SSE/AVX/AVX2 blend intrinsics.
18699 case Intrinsic::x86_avx2_pblendvb:
18700 case Intrinsic::x86_avx2_pblendw:
18701 case Intrinsic::x86_avx2_pblendd_128:
18702 case Intrinsic::x86_avx2_pblendd_256:
18703 // Don't try to simplify this intrinsic if we don't have AVX2.
18704 if (!Subtarget->hasAVX2())
18707 case Intrinsic::x86_avx_blend_pd_256:
18708 case Intrinsic::x86_avx_blend_ps_256:
18709 case Intrinsic::x86_avx_blendv_pd_256:
18710 case Intrinsic::x86_avx_blendv_ps_256:
18711 // Don't try to simplify this intrinsic if we don't have AVX.
18712 if (!Subtarget->hasAVX())
18715 case Intrinsic::x86_sse41_pblendw:
18716 case Intrinsic::x86_sse41_blendpd:
18717 case Intrinsic::x86_sse41_blendps:
18718 case Intrinsic::x86_sse41_blendvps:
18719 case Intrinsic::x86_sse41_blendvpd:
18720 case Intrinsic::x86_sse41_pblendvb: {
18721 SDValue Op0 = N->getOperand(1);
18722 SDValue Op1 = N->getOperand(2);
18723 SDValue Mask = N->getOperand(3);
18725 // Don't try to simplify this intrinsic if we don't have SSE4.1.
18726 if (!Subtarget->hasSSE41())
18729 // fold (blend A, A, Mask) -> A
18732 // fold (blend A, B, allZeros) -> A
18733 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
18735 // fold (blend A, B, allOnes) -> B
18736 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
18739 // Simplify the case where the mask is a constant i32 value.
18740 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
18741 if (C->isNullValue())
18743 if (C->isAllOnesValue())
18748 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
18749 case Intrinsic::x86_sse2_psrai_w:
18750 case Intrinsic::x86_sse2_psrai_d:
18751 case Intrinsic::x86_avx2_psrai_w:
18752 case Intrinsic::x86_avx2_psrai_d:
18753 case Intrinsic::x86_sse2_psra_w:
18754 case Intrinsic::x86_sse2_psra_d:
18755 case Intrinsic::x86_avx2_psra_w:
18756 case Intrinsic::x86_avx2_psra_d: {
18757 SDValue Op0 = N->getOperand(1);
18758 SDValue Op1 = N->getOperand(2);
18759 EVT VT = Op0.getValueType();
18760 assert(VT.isVector() && "Expected a vector type!");
18762 if (isa<BuildVectorSDNode>(Op1))
18763 Op1 = Op1.getOperand(0);
18765 if (!isa<ConstantSDNode>(Op1))
18768 EVT SVT = VT.getVectorElementType();
18769 unsigned SVTBits = SVT.getSizeInBits();
18771 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
18772 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
18773 uint64_t ShAmt = C.getZExtValue();
18775 // Don't try to convert this shift into a ISD::SRA if the shift
18776 // count is bigger than or equal to the element size.
18777 if (ShAmt >= SVTBits)
18780 // Trivial case: if the shift count is zero, then fold this
18781 // into the first operand.
18785 // Replace this packed shift intrinsic with a target independent
18787 SDValue Splat = DAG.getConstant(C, VT);
18788 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
18793 /// PerformMulCombine - Optimize a single multiply with constant into two
18794 /// in order to implement it with two cheaper instructions, e.g.
18795 /// LEA + SHL, LEA + LEA.
18796 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
18797 TargetLowering::DAGCombinerInfo &DCI) {
18798 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
18801 EVT VT = N->getValueType(0);
18802 if (VT != MVT::i64)
18805 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
18808 uint64_t MulAmt = C->getZExtValue();
18809 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
18812 uint64_t MulAmt1 = 0;
18813 uint64_t MulAmt2 = 0;
18814 if ((MulAmt % 9) == 0) {
18816 MulAmt2 = MulAmt / 9;
18817 } else if ((MulAmt % 5) == 0) {
18819 MulAmt2 = MulAmt / 5;
18820 } else if ((MulAmt % 3) == 0) {
18822 MulAmt2 = MulAmt / 3;
18825 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
18828 if (isPowerOf2_64(MulAmt2) &&
18829 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
18830 // If second multiplifer is pow2, issue it first. We want the multiply by
18831 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
18833 std::swap(MulAmt1, MulAmt2);
18836 if (isPowerOf2_64(MulAmt1))
18837 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
18838 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
18840 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
18841 DAG.getConstant(MulAmt1, VT));
18843 if (isPowerOf2_64(MulAmt2))
18844 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
18845 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
18847 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
18848 DAG.getConstant(MulAmt2, VT));
18850 // Do not add new nodes to DAG combiner worklist.
18851 DCI.CombineTo(N, NewMul, false);
18856 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
18857 SDValue N0 = N->getOperand(0);
18858 SDValue N1 = N->getOperand(1);
18859 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
18860 EVT VT = N0.getValueType();
18862 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
18863 // since the result of setcc_c is all zero's or all ones.
18864 if (VT.isInteger() && !VT.isVector() &&
18865 N1C && N0.getOpcode() == ISD::AND &&
18866 N0.getOperand(1).getOpcode() == ISD::Constant) {
18867 SDValue N00 = N0.getOperand(0);
18868 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
18869 ((N00.getOpcode() == ISD::ANY_EXTEND ||
18870 N00.getOpcode() == ISD::ZERO_EXTEND) &&
18871 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
18872 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
18873 APInt ShAmt = N1C->getAPIntValue();
18874 Mask = Mask.shl(ShAmt);
18876 return DAG.getNode(ISD::AND, SDLoc(N), VT,
18877 N00, DAG.getConstant(Mask, VT));
18881 // Hardware support for vector shifts is sparse which makes us scalarize the
18882 // vector operations in many cases. Also, on sandybridge ADD is faster than
18884 // (shl V, 1) -> add V,V
18885 if (isSplatVector(N1.getNode())) {
18886 assert(N0.getValueType().isVector() && "Invalid vector shift type");
18887 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
18888 // We shift all of the values by one. In many cases we do not have
18889 // hardware support for this operation. This is better expressed as an ADD
18891 if (N1C && (1 == N1C->getZExtValue())) {
18892 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
18899 /// \brief Returns a vector of 0s if the node in input is a vector logical
18900 /// shift by a constant amount which is known to be bigger than or equal
18901 /// to the vector element size in bits.
18902 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
18903 const X86Subtarget *Subtarget) {
18904 EVT VT = N->getValueType(0);
18906 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
18907 (!Subtarget->hasInt256() ||
18908 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
18911 SDValue Amt = N->getOperand(1);
18913 if (isSplatVector(Amt.getNode())) {
18914 SDValue SclrAmt = Amt->getOperand(0);
18915 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
18916 APInt ShiftAmt = C->getAPIntValue();
18917 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
18919 // SSE2/AVX2 logical shifts always return a vector of 0s
18920 // if the shift amount is bigger than or equal to
18921 // the element size. The constant shift amount will be
18922 // encoded as a 8-bit immediate.
18923 if (ShiftAmt.trunc(8).uge(MaxAmount))
18924 return getZeroVector(VT, Subtarget, DAG, DL);
18931 /// PerformShiftCombine - Combine shifts.
18932 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
18933 TargetLowering::DAGCombinerInfo &DCI,
18934 const X86Subtarget *Subtarget) {
18935 if (N->getOpcode() == ISD::SHL) {
18936 SDValue V = PerformSHLCombine(N, DAG);
18937 if (V.getNode()) return V;
18940 if (N->getOpcode() != ISD::SRA) {
18941 // Try to fold this logical shift into a zero vector.
18942 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
18943 if (V.getNode()) return V;
18949 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
18950 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
18951 // and friends. Likewise for OR -> CMPNEQSS.
18952 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
18953 TargetLowering::DAGCombinerInfo &DCI,
18954 const X86Subtarget *Subtarget) {
18957 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
18958 // we're requiring SSE2 for both.
18959 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
18960 SDValue N0 = N->getOperand(0);
18961 SDValue N1 = N->getOperand(1);
18962 SDValue CMP0 = N0->getOperand(1);
18963 SDValue CMP1 = N1->getOperand(1);
18966 // The SETCCs should both refer to the same CMP.
18967 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
18970 SDValue CMP00 = CMP0->getOperand(0);
18971 SDValue CMP01 = CMP0->getOperand(1);
18972 EVT VT = CMP00.getValueType();
18974 if (VT == MVT::f32 || VT == MVT::f64) {
18975 bool ExpectingFlags = false;
18976 // Check for any users that want flags:
18977 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
18978 !ExpectingFlags && UI != UE; ++UI)
18979 switch (UI->getOpcode()) {
18984 ExpectingFlags = true;
18986 case ISD::CopyToReg:
18987 case ISD::SIGN_EXTEND:
18988 case ISD::ZERO_EXTEND:
18989 case ISD::ANY_EXTEND:
18993 if (!ExpectingFlags) {
18994 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
18995 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
18997 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
18998 X86::CondCode tmp = cc0;
19003 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
19004 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
19005 // FIXME: need symbolic constants for these magic numbers.
19006 // See X86ATTInstPrinter.cpp:printSSECC().
19007 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
19008 if (Subtarget->hasAVX512()) {
19009 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
19010 CMP01, DAG.getConstant(x86cc, MVT::i8));
19011 if (N->getValueType(0) != MVT::i1)
19012 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
19016 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
19017 CMP00.getValueType(), CMP00, CMP01,
19018 DAG.getConstant(x86cc, MVT::i8));
19020 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
19021 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
19023 if (is64BitFP && !Subtarget->is64Bit()) {
19024 // On a 32-bit target, we cannot bitcast the 64-bit float to a
19025 // 64-bit integer, since that's not a legal type. Since
19026 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
19027 // bits, but can do this little dance to extract the lowest 32 bits
19028 // and work with those going forward.
19029 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
19031 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
19033 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
19034 Vector32, DAG.getIntPtrConstant(0));
19038 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
19039 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
19040 DAG.getConstant(1, IntVT));
19041 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
19042 return OneBitOfTruth;
19050 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
19051 /// so it can be folded inside ANDNP.
19052 static bool CanFoldXORWithAllOnes(const SDNode *N) {
19053 EVT VT = N->getValueType(0);
19055 // Match direct AllOnes for 128 and 256-bit vectors
19056 if (ISD::isBuildVectorAllOnes(N))
19059 // Look through a bit convert.
19060 if (N->getOpcode() == ISD::BITCAST)
19061 N = N->getOperand(0).getNode();
19063 // Sometimes the operand may come from a insert_subvector building a 256-bit
19065 if (VT.is256BitVector() &&
19066 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
19067 SDValue V1 = N->getOperand(0);
19068 SDValue V2 = N->getOperand(1);
19070 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
19071 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
19072 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
19073 ISD::isBuildVectorAllOnes(V2.getNode()))
19080 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
19081 // register. In most cases we actually compare or select YMM-sized registers
19082 // and mixing the two types creates horrible code. This method optimizes
19083 // some of the transition sequences.
19084 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
19085 TargetLowering::DAGCombinerInfo &DCI,
19086 const X86Subtarget *Subtarget) {
19087 EVT VT = N->getValueType(0);
19088 if (!VT.is256BitVector())
19091 assert((N->getOpcode() == ISD::ANY_EXTEND ||
19092 N->getOpcode() == ISD::ZERO_EXTEND ||
19093 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
19095 SDValue Narrow = N->getOperand(0);
19096 EVT NarrowVT = Narrow->getValueType(0);
19097 if (!NarrowVT.is128BitVector())
19100 if (Narrow->getOpcode() != ISD::XOR &&
19101 Narrow->getOpcode() != ISD::AND &&
19102 Narrow->getOpcode() != ISD::OR)
19105 SDValue N0 = Narrow->getOperand(0);
19106 SDValue N1 = Narrow->getOperand(1);
19109 // The Left side has to be a trunc.
19110 if (N0.getOpcode() != ISD::TRUNCATE)
19113 // The type of the truncated inputs.
19114 EVT WideVT = N0->getOperand(0)->getValueType(0);
19118 // The right side has to be a 'trunc' or a constant vector.
19119 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
19120 bool RHSConst = (isSplatVector(N1.getNode()) &&
19121 isa<ConstantSDNode>(N1->getOperand(0)));
19122 if (!RHSTrunc && !RHSConst)
19125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19127 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
19130 // Set N0 and N1 to hold the inputs to the new wide operation.
19131 N0 = N0->getOperand(0);
19133 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
19134 N1->getOperand(0));
19135 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
19136 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
19137 } else if (RHSTrunc) {
19138 N1 = N1->getOperand(0);
19141 // Generate the wide operation.
19142 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
19143 unsigned Opcode = N->getOpcode();
19145 case ISD::ANY_EXTEND:
19147 case ISD::ZERO_EXTEND: {
19148 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
19149 APInt Mask = APInt::getAllOnesValue(InBits);
19150 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
19151 return DAG.getNode(ISD::AND, DL, VT,
19152 Op, DAG.getConstant(Mask, VT));
19154 case ISD::SIGN_EXTEND:
19155 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
19156 Op, DAG.getValueType(NarrowVT));
19158 llvm_unreachable("Unexpected opcode");
19162 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
19163 TargetLowering::DAGCombinerInfo &DCI,
19164 const X86Subtarget *Subtarget) {
19165 EVT VT = N->getValueType(0);
19166 if (DCI.isBeforeLegalizeOps())
19169 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
19173 // Create BEXTR instructions
19174 // BEXTR is ((X >> imm) & (2**size-1))
19175 if (VT == MVT::i32 || VT == MVT::i64) {
19176 SDValue N0 = N->getOperand(0);
19177 SDValue N1 = N->getOperand(1);
19180 // Check for BEXTR.
19181 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
19182 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
19183 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
19184 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
19185 if (MaskNode && ShiftNode) {
19186 uint64_t Mask = MaskNode->getZExtValue();
19187 uint64_t Shift = ShiftNode->getZExtValue();
19188 if (isMask_64(Mask)) {
19189 uint64_t MaskSize = CountPopulation_64(Mask);
19190 if (Shift + MaskSize <= VT.getSizeInBits())
19191 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
19192 DAG.getConstant(Shift | (MaskSize << 8), VT));
19200 // Want to form ANDNP nodes:
19201 // 1) In the hopes of then easily combining them with OR and AND nodes
19202 // to form PBLEND/PSIGN.
19203 // 2) To match ANDN packed intrinsics
19204 if (VT != MVT::v2i64 && VT != MVT::v4i64)
19207 SDValue N0 = N->getOperand(0);
19208 SDValue N1 = N->getOperand(1);
19211 // Check LHS for vnot
19212 if (N0.getOpcode() == ISD::XOR &&
19213 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
19214 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
19215 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
19217 // Check RHS for vnot
19218 if (N1.getOpcode() == ISD::XOR &&
19219 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
19220 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
19221 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
19226 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
19227 TargetLowering::DAGCombinerInfo &DCI,
19228 const X86Subtarget *Subtarget) {
19229 if (DCI.isBeforeLegalizeOps())
19232 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
19236 SDValue N0 = N->getOperand(0);
19237 SDValue N1 = N->getOperand(1);
19238 EVT VT = N->getValueType(0);
19240 // look for psign/blend
19241 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
19242 if (!Subtarget->hasSSSE3() ||
19243 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
19246 // Canonicalize pandn to RHS
19247 if (N0.getOpcode() == X86ISD::ANDNP)
19249 // or (and (m, y), (pandn m, x))
19250 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
19251 SDValue Mask = N1.getOperand(0);
19252 SDValue X = N1.getOperand(1);
19254 if (N0.getOperand(0) == Mask)
19255 Y = N0.getOperand(1);
19256 if (N0.getOperand(1) == Mask)
19257 Y = N0.getOperand(0);
19259 // Check to see if the mask appeared in both the AND and ANDNP and
19263 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
19264 // Look through mask bitcast.
19265 if (Mask.getOpcode() == ISD::BITCAST)
19266 Mask = Mask.getOperand(0);
19267 if (X.getOpcode() == ISD::BITCAST)
19268 X = X.getOperand(0);
19269 if (Y.getOpcode() == ISD::BITCAST)
19270 Y = Y.getOperand(0);
19272 EVT MaskVT = Mask.getValueType();
19274 // Validate that the Mask operand is a vector sra node.
19275 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
19276 // there is no psrai.b
19277 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
19278 unsigned SraAmt = ~0;
19279 if (Mask.getOpcode() == ISD::SRA) {
19280 SDValue Amt = Mask.getOperand(1);
19281 if (isSplatVector(Amt.getNode())) {
19282 SDValue SclrAmt = Amt->getOperand(0);
19283 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
19284 SraAmt = C->getZExtValue();
19286 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
19287 SDValue SraC = Mask.getOperand(1);
19288 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
19290 if ((SraAmt + 1) != EltBits)
19295 // Now we know we at least have a plendvb with the mask val. See if
19296 // we can form a psignb/w/d.
19297 // psign = x.type == y.type == mask.type && y = sub(0, x);
19298 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
19299 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
19300 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
19301 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
19302 "Unsupported VT for PSIGN");
19303 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
19304 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
19306 // PBLENDVB only available on SSE 4.1
19307 if (!Subtarget->hasSSE41())
19310 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
19312 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
19313 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
19314 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
19315 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
19316 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
19320 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
19323 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
19324 MachineFunction &MF = DAG.getMachineFunction();
19325 bool OptForSize = MF.getFunction()->getAttributes().
19326 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
19328 // SHLD/SHRD instructions have lower register pressure, but on some
19329 // platforms they have higher latency than the equivalent
19330 // series of shifts/or that would otherwise be generated.
19331 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
19332 // have higher latencies and we are not optimizing for size.
19333 if (!OptForSize && Subtarget->isSHLDSlow())
19336 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
19338 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
19340 if (!N0.hasOneUse() || !N1.hasOneUse())
19343 SDValue ShAmt0 = N0.getOperand(1);
19344 if (ShAmt0.getValueType() != MVT::i8)
19346 SDValue ShAmt1 = N1.getOperand(1);
19347 if (ShAmt1.getValueType() != MVT::i8)
19349 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
19350 ShAmt0 = ShAmt0.getOperand(0);
19351 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
19352 ShAmt1 = ShAmt1.getOperand(0);
19355 unsigned Opc = X86ISD::SHLD;
19356 SDValue Op0 = N0.getOperand(0);
19357 SDValue Op1 = N1.getOperand(0);
19358 if (ShAmt0.getOpcode() == ISD::SUB) {
19359 Opc = X86ISD::SHRD;
19360 std::swap(Op0, Op1);
19361 std::swap(ShAmt0, ShAmt1);
19364 unsigned Bits = VT.getSizeInBits();
19365 if (ShAmt1.getOpcode() == ISD::SUB) {
19366 SDValue Sum = ShAmt1.getOperand(0);
19367 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
19368 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
19369 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
19370 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
19371 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
19372 return DAG.getNode(Opc, DL, VT,
19374 DAG.getNode(ISD::TRUNCATE, DL,
19377 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
19378 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
19380 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
19381 return DAG.getNode(Opc, DL, VT,
19382 N0.getOperand(0), N1.getOperand(0),
19383 DAG.getNode(ISD::TRUNCATE, DL,
19390 // Generate NEG and CMOV for integer abs.
19391 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
19392 EVT VT = N->getValueType(0);
19394 // Since X86 does not have CMOV for 8-bit integer, we don't convert
19395 // 8-bit integer abs to NEG and CMOV.
19396 if (VT.isInteger() && VT.getSizeInBits() == 8)
19399 SDValue N0 = N->getOperand(0);
19400 SDValue N1 = N->getOperand(1);
19403 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
19404 // and change it to SUB and CMOV.
19405 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
19406 N0.getOpcode() == ISD::ADD &&
19407 N0.getOperand(1) == N1 &&
19408 N1.getOpcode() == ISD::SRA &&
19409 N1.getOperand(0) == N0.getOperand(0))
19410 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
19411 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
19412 // Generate SUB & CMOV.
19413 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
19414 DAG.getConstant(0, VT), N0.getOperand(0));
19416 SDValue Ops[] = { N0.getOperand(0), Neg,
19417 DAG.getConstant(X86::COND_GE, MVT::i8),
19418 SDValue(Neg.getNode(), 1) };
19419 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
19424 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
19425 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
19426 TargetLowering::DAGCombinerInfo &DCI,
19427 const X86Subtarget *Subtarget) {
19428 if (DCI.isBeforeLegalizeOps())
19431 if (Subtarget->hasCMov()) {
19432 SDValue RV = performIntegerAbsCombine(N, DAG);
19440 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
19441 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
19442 TargetLowering::DAGCombinerInfo &DCI,
19443 const X86Subtarget *Subtarget) {
19444 LoadSDNode *Ld = cast<LoadSDNode>(N);
19445 EVT RegVT = Ld->getValueType(0);
19446 EVT MemVT = Ld->getMemoryVT();
19448 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19449 unsigned RegSz = RegVT.getSizeInBits();
19451 // On Sandybridge unaligned 256bit loads are inefficient.
19452 ISD::LoadExtType Ext = Ld->getExtensionType();
19453 unsigned Alignment = Ld->getAlignment();
19454 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
19455 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
19456 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
19457 unsigned NumElems = RegVT.getVectorNumElements();
19461 SDValue Ptr = Ld->getBasePtr();
19462 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
19464 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
19466 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
19467 Ld->getPointerInfo(), Ld->isVolatile(),
19468 Ld->isNonTemporal(), Ld->isInvariant(),
19470 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
19471 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
19472 Ld->getPointerInfo(), Ld->isVolatile(),
19473 Ld->isNonTemporal(), Ld->isInvariant(),
19474 std::min(16U, Alignment));
19475 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19477 Load2.getValue(1));
19479 SDValue NewVec = DAG.getUNDEF(RegVT);
19480 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
19481 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
19482 return DCI.CombineTo(N, NewVec, TF, true);
19485 // If this is a vector EXT Load then attempt to optimize it using a
19486 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
19487 // expansion is still better than scalar code.
19488 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
19489 // emit a shuffle and a arithmetic shift.
19490 // TODO: It is possible to support ZExt by zeroing the undef values
19491 // during the shuffle phase or after the shuffle.
19492 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
19493 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
19494 assert(MemVT != RegVT && "Cannot extend to the same type");
19495 assert(MemVT.isVector() && "Must load a vector from memory");
19497 unsigned NumElems = RegVT.getVectorNumElements();
19498 unsigned MemSz = MemVT.getSizeInBits();
19499 assert(RegSz > MemSz && "Register size must be greater than the mem size");
19501 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
19504 // All sizes must be a power of two.
19505 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
19508 // Attempt to load the original value using scalar loads.
19509 // Find the largest scalar type that divides the total loaded size.
19510 MVT SclrLoadTy = MVT::i8;
19511 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
19512 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
19513 MVT Tp = (MVT::SimpleValueType)tp;
19514 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
19519 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
19520 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
19522 SclrLoadTy = MVT::f64;
19524 // Calculate the number of scalar loads that we need to perform
19525 // in order to load our vector from memory.
19526 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
19527 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
19530 unsigned loadRegZize = RegSz;
19531 if (Ext == ISD::SEXTLOAD && RegSz == 256)
19534 // Represent our vector as a sequence of elements which are the
19535 // largest scalar that we can load.
19536 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
19537 loadRegZize/SclrLoadTy.getSizeInBits());
19539 // Represent the data using the same element type that is stored in
19540 // memory. In practice, we ''widen'' MemVT.
19542 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
19543 loadRegZize/MemVT.getScalarType().getSizeInBits());
19545 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
19546 "Invalid vector type");
19548 // We can't shuffle using an illegal type.
19549 if (!TLI.isTypeLegal(WideVecVT))
19552 SmallVector<SDValue, 8> Chains;
19553 SDValue Ptr = Ld->getBasePtr();
19554 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
19555 TLI.getPointerTy());
19556 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
19558 for (unsigned i = 0; i < NumLoads; ++i) {
19559 // Perform a single load.
19560 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
19561 Ptr, Ld->getPointerInfo(),
19562 Ld->isVolatile(), Ld->isNonTemporal(),
19563 Ld->isInvariant(), Ld->getAlignment());
19564 Chains.push_back(ScalarLoad.getValue(1));
19565 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
19566 // another round of DAGCombining.
19568 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
19570 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
19571 ScalarLoad, DAG.getIntPtrConstant(i));
19573 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
19576 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
19578 // Bitcast the loaded value to a vector of the original element type, in
19579 // the size of the target vector type.
19580 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
19581 unsigned SizeRatio = RegSz/MemSz;
19583 if (Ext == ISD::SEXTLOAD) {
19584 // If we have SSE4.1 we can directly emit a VSEXT node.
19585 if (Subtarget->hasSSE41()) {
19586 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
19587 return DCI.CombineTo(N, Sext, TF, true);
19590 // Otherwise we'll shuffle the small elements in the high bits of the
19591 // larger type and perform an arithmetic shift. If the shift is not legal
19592 // it's better to scalarize.
19593 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
19596 // Redistribute the loaded elements into the different locations.
19597 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
19598 for (unsigned i = 0; i != NumElems; ++i)
19599 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
19601 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
19602 DAG.getUNDEF(WideVecVT),
19605 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
19607 // Build the arithmetic shift.
19608 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
19609 MemVT.getVectorElementType().getSizeInBits();
19610 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
19611 DAG.getConstant(Amt, RegVT));
19613 return DCI.CombineTo(N, Shuff, TF, true);
19616 // Redistribute the loaded elements into the different locations.
19617 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
19618 for (unsigned i = 0; i != NumElems; ++i)
19619 ShuffleVec[i*SizeRatio] = i;
19621 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
19622 DAG.getUNDEF(WideVecVT),
19625 // Bitcast to the requested type.
19626 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
19627 // Replace the original load with the new sequence
19628 // and return the new chain.
19629 return DCI.CombineTo(N, Shuff, TF, true);
19635 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
19636 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
19637 const X86Subtarget *Subtarget) {
19638 StoreSDNode *St = cast<StoreSDNode>(N);
19639 EVT VT = St->getValue().getValueType();
19640 EVT StVT = St->getMemoryVT();
19642 SDValue StoredVal = St->getOperand(1);
19643 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19645 // If we are saving a concatenation of two XMM registers, perform two stores.
19646 // On Sandy Bridge, 256-bit memory operations are executed by two
19647 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
19648 // memory operation.
19649 unsigned Alignment = St->getAlignment();
19650 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
19651 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
19652 StVT == VT && !IsAligned) {
19653 unsigned NumElems = VT.getVectorNumElements();
19657 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
19658 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
19660 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
19661 SDValue Ptr0 = St->getBasePtr();
19662 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
19664 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
19665 St->getPointerInfo(), St->isVolatile(),
19666 St->isNonTemporal(), Alignment);
19667 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
19668 St->getPointerInfo(), St->isVolatile(),
19669 St->isNonTemporal(),
19670 std::min(16U, Alignment));
19671 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
19674 // Optimize trunc store (of multiple scalars) to shuffle and store.
19675 // First, pack all of the elements in one place. Next, store to memory
19676 // in fewer chunks.
19677 if (St->isTruncatingStore() && VT.isVector()) {
19678 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19679 unsigned NumElems = VT.getVectorNumElements();
19680 assert(StVT != VT && "Cannot truncate to the same type");
19681 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
19682 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
19684 // From, To sizes and ElemCount must be pow of two
19685 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
19686 // We are going to use the original vector elt for storing.
19687 // Accumulated smaller vector elements must be a multiple of the store size.
19688 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
19690 unsigned SizeRatio = FromSz / ToSz;
19692 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
19694 // Create a type on which we perform the shuffle
19695 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
19696 StVT.getScalarType(), NumElems*SizeRatio);
19698 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
19700 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
19701 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
19702 for (unsigned i = 0; i != NumElems; ++i)
19703 ShuffleVec[i] = i * SizeRatio;
19705 // Can't shuffle using an illegal type.
19706 if (!TLI.isTypeLegal(WideVecVT))
19709 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
19710 DAG.getUNDEF(WideVecVT),
19712 // At this point all of the data is stored at the bottom of the
19713 // register. We now need to save it to mem.
19715 // Find the largest store unit
19716 MVT StoreType = MVT::i8;
19717 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
19718 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
19719 MVT Tp = (MVT::SimpleValueType)tp;
19720 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
19724 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
19725 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
19726 (64 <= NumElems * ToSz))
19727 StoreType = MVT::f64;
19729 // Bitcast the original vector into a vector of store-size units
19730 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
19731 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
19732 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
19733 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
19734 SmallVector<SDValue, 8> Chains;
19735 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
19736 TLI.getPointerTy());
19737 SDValue Ptr = St->getBasePtr();
19739 // Perform one or more big stores into memory.
19740 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
19741 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
19742 StoreType, ShuffWide,
19743 DAG.getIntPtrConstant(i));
19744 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
19745 St->getPointerInfo(), St->isVolatile(),
19746 St->isNonTemporal(), St->getAlignment());
19747 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
19748 Chains.push_back(Ch);
19751 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
19754 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
19755 // the FP state in cases where an emms may be missing.
19756 // A preferable solution to the general problem is to figure out the right
19757 // places to insert EMMS. This qualifies as a quick hack.
19759 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
19760 if (VT.getSizeInBits() != 64)
19763 const Function *F = DAG.getMachineFunction().getFunction();
19764 bool NoImplicitFloatOps = F->getAttributes().
19765 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
19766 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
19767 && Subtarget->hasSSE2();
19768 if ((VT.isVector() ||
19769 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
19770 isa<LoadSDNode>(St->getValue()) &&
19771 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
19772 St->getChain().hasOneUse() && !St->isVolatile()) {
19773 SDNode* LdVal = St->getValue().getNode();
19774 LoadSDNode *Ld = nullptr;
19775 int TokenFactorIndex = -1;
19776 SmallVector<SDValue, 8> Ops;
19777 SDNode* ChainVal = St->getChain().getNode();
19778 // Must be a store of a load. We currently handle two cases: the load
19779 // is a direct child, and it's under an intervening TokenFactor. It is
19780 // possible to dig deeper under nested TokenFactors.
19781 if (ChainVal == LdVal)
19782 Ld = cast<LoadSDNode>(St->getChain());
19783 else if (St->getValue().hasOneUse() &&
19784 ChainVal->getOpcode() == ISD::TokenFactor) {
19785 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
19786 if (ChainVal->getOperand(i).getNode() == LdVal) {
19787 TokenFactorIndex = i;
19788 Ld = cast<LoadSDNode>(St->getValue());
19790 Ops.push_back(ChainVal->getOperand(i));
19794 if (!Ld || !ISD::isNormalLoad(Ld))
19797 // If this is not the MMX case, i.e. we are just turning i64 load/store
19798 // into f64 load/store, avoid the transformation if there are multiple
19799 // uses of the loaded value.
19800 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
19805 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
19806 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
19808 if (Subtarget->is64Bit() || F64IsLegal) {
19809 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
19810 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
19811 Ld->getPointerInfo(), Ld->isVolatile(),
19812 Ld->isNonTemporal(), Ld->isInvariant(),
19813 Ld->getAlignment());
19814 SDValue NewChain = NewLd.getValue(1);
19815 if (TokenFactorIndex != -1) {
19816 Ops.push_back(NewChain);
19817 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
19819 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
19820 St->getPointerInfo(),
19821 St->isVolatile(), St->isNonTemporal(),
19822 St->getAlignment());
19825 // Otherwise, lower to two pairs of 32-bit loads / stores.
19826 SDValue LoAddr = Ld->getBasePtr();
19827 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
19828 DAG.getConstant(4, MVT::i32));
19830 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
19831 Ld->getPointerInfo(),
19832 Ld->isVolatile(), Ld->isNonTemporal(),
19833 Ld->isInvariant(), Ld->getAlignment());
19834 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
19835 Ld->getPointerInfo().getWithOffset(4),
19836 Ld->isVolatile(), Ld->isNonTemporal(),
19838 MinAlign(Ld->getAlignment(), 4));
19840 SDValue NewChain = LoLd.getValue(1);
19841 if (TokenFactorIndex != -1) {
19842 Ops.push_back(LoLd);
19843 Ops.push_back(HiLd);
19844 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
19847 LoAddr = St->getBasePtr();
19848 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
19849 DAG.getConstant(4, MVT::i32));
19851 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
19852 St->getPointerInfo(),
19853 St->isVolatile(), St->isNonTemporal(),
19854 St->getAlignment());
19855 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
19856 St->getPointerInfo().getWithOffset(4),
19858 St->isNonTemporal(),
19859 MinAlign(St->getAlignment(), 4));
19860 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
19865 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
19866 /// and return the operands for the horizontal operation in LHS and RHS. A
19867 /// horizontal operation performs the binary operation on successive elements
19868 /// of its first operand, then on successive elements of its second operand,
19869 /// returning the resulting values in a vector. For example, if
19870 /// A = < float a0, float a1, float a2, float a3 >
19872 /// B = < float b0, float b1, float b2, float b3 >
19873 /// then the result of doing a horizontal operation on A and B is
19874 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
19875 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
19876 /// A horizontal-op B, for some already available A and B, and if so then LHS is
19877 /// set to A, RHS to B, and the routine returns 'true'.
19878 /// Note that the binary operation should have the property that if one of the
19879 /// operands is UNDEF then the result is UNDEF.
19880 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
19881 // Look for the following pattern: if
19882 // A = < float a0, float a1, float a2, float a3 >
19883 // B = < float b0, float b1, float b2, float b3 >
19885 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
19886 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
19887 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
19888 // which is A horizontal-op B.
19890 // At least one of the operands should be a vector shuffle.
19891 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
19892 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
19895 MVT VT = LHS.getSimpleValueType();
19897 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19898 "Unsupported vector type for horizontal add/sub");
19900 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
19901 // operate independently on 128-bit lanes.
19902 unsigned NumElts = VT.getVectorNumElements();
19903 unsigned NumLanes = VT.getSizeInBits()/128;
19904 unsigned NumLaneElts = NumElts / NumLanes;
19905 assert((NumLaneElts % 2 == 0) &&
19906 "Vector type should have an even number of elements in each lane");
19907 unsigned HalfLaneElts = NumLaneElts/2;
19909 // View LHS in the form
19910 // LHS = VECTOR_SHUFFLE A, B, LMask
19911 // If LHS is not a shuffle then pretend it is the shuffle
19912 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
19913 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
19916 SmallVector<int, 16> LMask(NumElts);
19917 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
19918 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
19919 A = LHS.getOperand(0);
19920 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
19921 B = LHS.getOperand(1);
19922 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
19923 std::copy(Mask.begin(), Mask.end(), LMask.begin());
19925 if (LHS.getOpcode() != ISD::UNDEF)
19927 for (unsigned i = 0; i != NumElts; ++i)
19931 // Likewise, view RHS in the form
19932 // RHS = VECTOR_SHUFFLE C, D, RMask
19934 SmallVector<int, 16> RMask(NumElts);
19935 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
19936 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
19937 C = RHS.getOperand(0);
19938 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
19939 D = RHS.getOperand(1);
19940 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
19941 std::copy(Mask.begin(), Mask.end(), RMask.begin());
19943 if (RHS.getOpcode() != ISD::UNDEF)
19945 for (unsigned i = 0; i != NumElts; ++i)
19949 // Check that the shuffles are both shuffling the same vectors.
19950 if (!(A == C && B == D) && !(A == D && B == C))
19953 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
19954 if (!A.getNode() && !B.getNode())
19957 // If A and B occur in reverse order in RHS, then "swap" them (which means
19958 // rewriting the mask).
19960 CommuteVectorShuffleMask(RMask, NumElts);
19962 // At this point LHS and RHS are equivalent to
19963 // LHS = VECTOR_SHUFFLE A, B, LMask
19964 // RHS = VECTOR_SHUFFLE A, B, RMask
19965 // Check that the masks correspond to performing a horizontal operation.
19966 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
19967 for (unsigned i = 0; i != NumLaneElts; ++i) {
19968 int LIdx = LMask[i+l], RIdx = RMask[i+l];
19970 // Ignore any UNDEF components.
19971 if (LIdx < 0 || RIdx < 0 ||
19972 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
19973 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
19976 // Check that successive elements are being operated on. If not, this is
19977 // not a horizontal operation.
19978 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
19979 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
19980 if (!(LIdx == Index && RIdx == Index + 1) &&
19981 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
19986 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
19987 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
19991 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
19992 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
19993 const X86Subtarget *Subtarget) {
19994 EVT VT = N->getValueType(0);
19995 SDValue LHS = N->getOperand(0);
19996 SDValue RHS = N->getOperand(1);
19998 // Try to synthesize horizontal adds from adds of shuffles.
19999 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
20000 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
20001 isHorizontalBinOp(LHS, RHS, true))
20002 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
20006 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
20007 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
20008 const X86Subtarget *Subtarget) {
20009 EVT VT = N->getValueType(0);
20010 SDValue LHS = N->getOperand(0);
20011 SDValue RHS = N->getOperand(1);
20013 // Try to synthesize horizontal subs from subs of shuffles.
20014 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
20015 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
20016 isHorizontalBinOp(LHS, RHS, false))
20017 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
20021 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
20022 /// X86ISD::FXOR nodes.
20023 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
20024 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
20025 // F[X]OR(0.0, x) -> x
20026 // F[X]OR(x, 0.0) -> x
20027 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
20028 if (C->getValueAPF().isPosZero())
20029 return N->getOperand(1);
20030 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
20031 if (C->getValueAPF().isPosZero())
20032 return N->getOperand(0);
20036 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
20037 /// X86ISD::FMAX nodes.
20038 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
20039 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
20041 // Only perform optimizations if UnsafeMath is used.
20042 if (!DAG.getTarget().Options.UnsafeFPMath)
20045 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
20046 // into FMINC and FMAXC, which are Commutative operations.
20047 unsigned NewOp = 0;
20048 switch (N->getOpcode()) {
20049 default: llvm_unreachable("unknown opcode");
20050 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
20051 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
20054 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
20055 N->getOperand(0), N->getOperand(1));
20058 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
20059 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
20060 // FAND(0.0, x) -> 0.0
20061 // FAND(x, 0.0) -> 0.0
20062 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
20063 if (C->getValueAPF().isPosZero())
20064 return N->getOperand(0);
20065 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
20066 if (C->getValueAPF().isPosZero())
20067 return N->getOperand(1);
20071 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
20072 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
20073 // FANDN(x, 0.0) -> 0.0
20074 // FANDN(0.0, x) -> x
20075 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
20076 if (C->getValueAPF().isPosZero())
20077 return N->getOperand(1);
20078 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
20079 if (C->getValueAPF().isPosZero())
20080 return N->getOperand(1);
20084 static SDValue PerformBTCombine(SDNode *N,
20086 TargetLowering::DAGCombinerInfo &DCI) {
20087 // BT ignores high bits in the bit index operand.
20088 SDValue Op1 = N->getOperand(1);
20089 if (Op1.hasOneUse()) {
20090 unsigned BitWidth = Op1.getValueSizeInBits();
20091 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
20092 APInt KnownZero, KnownOne;
20093 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
20094 !DCI.isBeforeLegalizeOps());
20095 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20096 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
20097 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
20098 DCI.CommitTargetLoweringOpt(TLO);
20103 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
20104 SDValue Op = N->getOperand(0);
20105 if (Op.getOpcode() == ISD::BITCAST)
20106 Op = Op.getOperand(0);
20107 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
20108 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
20109 VT.getVectorElementType().getSizeInBits() ==
20110 OpVT.getVectorElementType().getSizeInBits()) {
20111 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
20116 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
20117 const X86Subtarget *Subtarget) {
20118 EVT VT = N->getValueType(0);
20119 if (!VT.isVector())
20122 SDValue N0 = N->getOperand(0);
20123 SDValue N1 = N->getOperand(1);
20124 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
20127 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
20128 // both SSE and AVX2 since there is no sign-extended shift right
20129 // operation on a vector with 64-bit elements.
20130 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
20131 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
20132 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
20133 N0.getOpcode() == ISD::SIGN_EXTEND)) {
20134 SDValue N00 = N0.getOperand(0);
20136 // EXTLOAD has a better solution on AVX2,
20137 // it may be replaced with X86ISD::VSEXT node.
20138 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
20139 if (!ISD::isNormalLoad(N00.getNode()))
20142 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
20143 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
20145 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
20151 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
20152 TargetLowering::DAGCombinerInfo &DCI,
20153 const X86Subtarget *Subtarget) {
20154 if (!DCI.isBeforeLegalizeOps())
20157 if (!Subtarget->hasFp256())
20160 EVT VT = N->getValueType(0);
20161 if (VT.isVector() && VT.getSizeInBits() == 256) {
20162 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
20170 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
20171 const X86Subtarget* Subtarget) {
20173 EVT VT = N->getValueType(0);
20175 // Let legalize expand this if it isn't a legal type yet.
20176 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
20179 EVT ScalarVT = VT.getScalarType();
20180 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
20181 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
20184 SDValue A = N->getOperand(0);
20185 SDValue B = N->getOperand(1);
20186 SDValue C = N->getOperand(2);
20188 bool NegA = (A.getOpcode() == ISD::FNEG);
20189 bool NegB = (B.getOpcode() == ISD::FNEG);
20190 bool NegC = (C.getOpcode() == ISD::FNEG);
20192 // Negative multiplication when NegA xor NegB
20193 bool NegMul = (NegA != NegB);
20195 A = A.getOperand(0);
20197 B = B.getOperand(0);
20199 C = C.getOperand(0);
20203 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
20205 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
20207 return DAG.getNode(Opcode, dl, VT, A, B, C);
20210 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
20211 TargetLowering::DAGCombinerInfo &DCI,
20212 const X86Subtarget *Subtarget) {
20213 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
20214 // (and (i32 x86isd::setcc_carry), 1)
20215 // This eliminates the zext. This transformation is necessary because
20216 // ISD::SETCC is always legalized to i8.
20218 SDValue N0 = N->getOperand(0);
20219 EVT VT = N->getValueType(0);
20221 if (N0.getOpcode() == ISD::AND &&
20223 N0.getOperand(0).hasOneUse()) {
20224 SDValue N00 = N0.getOperand(0);
20225 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
20226 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
20227 if (!C || C->getZExtValue() != 1)
20229 return DAG.getNode(ISD::AND, dl, VT,
20230 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
20231 N00.getOperand(0), N00.getOperand(1)),
20232 DAG.getConstant(1, VT));
20236 if (N0.getOpcode() == ISD::TRUNCATE &&
20238 N0.getOperand(0).hasOneUse()) {
20239 SDValue N00 = N0.getOperand(0);
20240 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
20241 return DAG.getNode(ISD::AND, dl, VT,
20242 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
20243 N00.getOperand(0), N00.getOperand(1)),
20244 DAG.getConstant(1, VT));
20247 if (VT.is256BitVector()) {
20248 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
20256 // Optimize x == -y --> x+y == 0
20257 // x != -y --> x+y != 0
20258 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
20259 const X86Subtarget* Subtarget) {
20260 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
20261 SDValue LHS = N->getOperand(0);
20262 SDValue RHS = N->getOperand(1);
20263 EVT VT = N->getValueType(0);
20266 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
20267 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
20268 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
20269 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
20270 LHS.getValueType(), RHS, LHS.getOperand(1));
20271 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
20272 addV, DAG.getConstant(0, addV.getValueType()), CC);
20274 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
20275 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
20276 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
20277 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
20278 RHS.getValueType(), LHS, RHS.getOperand(1));
20279 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
20280 addV, DAG.getConstant(0, addV.getValueType()), CC);
20283 if (VT.getScalarType() == MVT::i1) {
20284 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
20285 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
20286 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
20287 if (!IsSEXT0 && !IsVZero0)
20289 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
20290 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
20291 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
20293 if (!IsSEXT1 && !IsVZero1)
20296 if (IsSEXT0 && IsVZero1) {
20297 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
20298 if (CC == ISD::SETEQ)
20299 return DAG.getNOT(DL, LHS.getOperand(0), VT);
20300 return LHS.getOperand(0);
20302 if (IsSEXT1 && IsVZero0) {
20303 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
20304 if (CC == ISD::SETEQ)
20305 return DAG.getNOT(DL, RHS.getOperand(0), VT);
20306 return RHS.getOperand(0);
20313 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
20314 const X86Subtarget *Subtarget) {
20316 MVT VT = N->getOperand(1)->getSimpleValueType(0);
20317 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
20318 "X86insertps is only defined for v4x32");
20320 SDValue Ld = N->getOperand(1);
20321 if (MayFoldLoad(Ld)) {
20322 // Extract the countS bits from the immediate so we can get the proper
20323 // address when narrowing the vector load to a specific element.
20324 // When the second source op is a memory address, interps doesn't use
20325 // countS and just gets an f32 from that address.
20326 unsigned DestIndex =
20327 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
20328 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
20332 // Create this as a scalar to vector to match the instruction pattern.
20333 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
20334 // countS bits are ignored when loading from memory on insertps, which
20335 // means we don't need to explicitly set them to 0.
20336 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
20337 LoadScalarToVector, N->getOperand(2));
20340 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
20341 // as "sbb reg,reg", since it can be extended without zext and produces
20342 // an all-ones bit which is more useful than 0/1 in some cases.
20343 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
20346 return DAG.getNode(ISD::AND, DL, VT,
20347 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
20348 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
20349 DAG.getConstant(1, VT));
20350 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
20351 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
20352 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
20353 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
20356 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
20357 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
20358 TargetLowering::DAGCombinerInfo &DCI,
20359 const X86Subtarget *Subtarget) {
20361 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
20362 SDValue EFLAGS = N->getOperand(1);
20364 if (CC == X86::COND_A) {
20365 // Try to convert COND_A into COND_B in an attempt to facilitate
20366 // materializing "setb reg".
20368 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
20369 // cannot take an immediate as its first operand.
20371 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
20372 EFLAGS.getValueType().isInteger() &&
20373 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
20374 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
20375 EFLAGS.getNode()->getVTList(),
20376 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
20377 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
20378 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
20382 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
20383 // a zext and produces an all-ones bit which is more useful than 0/1 in some
20385 if (CC == X86::COND_B)
20386 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
20390 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
20391 if (Flags.getNode()) {
20392 SDValue Cond = DAG.getConstant(CC, MVT::i8);
20393 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
20399 // Optimize branch condition evaluation.
20401 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
20402 TargetLowering::DAGCombinerInfo &DCI,
20403 const X86Subtarget *Subtarget) {
20405 SDValue Chain = N->getOperand(0);
20406 SDValue Dest = N->getOperand(1);
20407 SDValue EFLAGS = N->getOperand(3);
20408 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
20412 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
20413 if (Flags.getNode()) {
20414 SDValue Cond = DAG.getConstant(CC, MVT::i8);
20415 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
20422 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
20423 const X86TargetLowering *XTLI) {
20424 SDValue Op0 = N->getOperand(0);
20425 EVT InVT = Op0->getValueType(0);
20427 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
20428 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
20430 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
20431 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
20432 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
20435 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
20436 // a 32-bit target where SSE doesn't support i64->FP operations.
20437 if (Op0.getOpcode() == ISD::LOAD) {
20438 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
20439 EVT VT = Ld->getValueType(0);
20440 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
20441 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
20442 !XTLI->getSubtarget()->is64Bit() &&
20444 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
20445 Ld->getChain(), Op0, DAG);
20446 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
20453 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
20454 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
20455 X86TargetLowering::DAGCombinerInfo &DCI) {
20456 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
20457 // the result is either zero or one (depending on the input carry bit).
20458 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
20459 if (X86::isZeroNode(N->getOperand(0)) &&
20460 X86::isZeroNode(N->getOperand(1)) &&
20461 // We don't have a good way to replace an EFLAGS use, so only do this when
20463 SDValue(N, 1).use_empty()) {
20465 EVT VT = N->getValueType(0);
20466 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
20467 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
20468 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
20469 DAG.getConstant(X86::COND_B,MVT::i8),
20471 DAG.getConstant(1, VT));
20472 return DCI.CombineTo(N, Res1, CarryOut);
20478 // fold (add Y, (sete X, 0)) -> adc 0, Y
20479 // (add Y, (setne X, 0)) -> sbb -1, Y
20480 // (sub (sete X, 0), Y) -> sbb 0, Y
20481 // (sub (setne X, 0), Y) -> adc -1, Y
20482 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
20485 // Look through ZExts.
20486 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
20487 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
20490 SDValue SetCC = Ext.getOperand(0);
20491 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
20494 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
20495 if (CC != X86::COND_E && CC != X86::COND_NE)
20498 SDValue Cmp = SetCC.getOperand(1);
20499 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
20500 !X86::isZeroNode(Cmp.getOperand(1)) ||
20501 !Cmp.getOperand(0).getValueType().isInteger())
20504 SDValue CmpOp0 = Cmp.getOperand(0);
20505 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
20506 DAG.getConstant(1, CmpOp0.getValueType()));
20508 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
20509 if (CC == X86::COND_NE)
20510 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
20511 DL, OtherVal.getValueType(), OtherVal,
20512 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
20513 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
20514 DL, OtherVal.getValueType(), OtherVal,
20515 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
20518 /// PerformADDCombine - Do target-specific dag combines on integer adds.
20519 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
20520 const X86Subtarget *Subtarget) {
20521 EVT VT = N->getValueType(0);
20522 SDValue Op0 = N->getOperand(0);
20523 SDValue Op1 = N->getOperand(1);
20525 // Try to synthesize horizontal adds from adds of shuffles.
20526 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
20527 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
20528 isHorizontalBinOp(Op0, Op1, true))
20529 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
20531 return OptimizeConditionalInDecrement(N, DAG);
20534 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
20535 const X86Subtarget *Subtarget) {
20536 SDValue Op0 = N->getOperand(0);
20537 SDValue Op1 = N->getOperand(1);
20539 // X86 can't encode an immediate LHS of a sub. See if we can push the
20540 // negation into a preceding instruction.
20541 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
20542 // If the RHS of the sub is a XOR with one use and a constant, invert the
20543 // immediate. Then add one to the LHS of the sub so we can turn
20544 // X-Y -> X+~Y+1, saving one register.
20545 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
20546 isa<ConstantSDNode>(Op1.getOperand(1))) {
20547 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
20548 EVT VT = Op0.getValueType();
20549 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
20551 DAG.getConstant(~XorC, VT));
20552 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
20553 DAG.getConstant(C->getAPIntValue()+1, VT));
20557 // Try to synthesize horizontal adds from adds of shuffles.
20558 EVT VT = N->getValueType(0);
20559 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
20560 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
20561 isHorizontalBinOp(Op0, Op1, true))
20562 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
20564 return OptimizeConditionalInDecrement(N, DAG);
20567 /// performVZEXTCombine - Performs build vector combines
20568 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
20569 TargetLowering::DAGCombinerInfo &DCI,
20570 const X86Subtarget *Subtarget) {
20571 // (vzext (bitcast (vzext (x)) -> (vzext x)
20572 SDValue In = N->getOperand(0);
20573 while (In.getOpcode() == ISD::BITCAST)
20574 In = In.getOperand(0);
20576 if (In.getOpcode() != X86ISD::VZEXT)
20579 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
20583 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
20584 DAGCombinerInfo &DCI) const {
20585 SelectionDAG &DAG = DCI.DAG;
20586 switch (N->getOpcode()) {
20588 case ISD::EXTRACT_VECTOR_ELT:
20589 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
20591 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
20592 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
20593 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
20594 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
20595 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
20596 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
20599 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
20600 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
20601 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
20602 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
20603 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
20604 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
20605 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
20606 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
20607 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
20609 case X86ISD::FOR: return PerformFORCombine(N, DAG);
20611 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
20612 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
20613 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
20614 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
20615 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
20616 case ISD::ANY_EXTEND:
20617 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
20618 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
20619 case ISD::SIGN_EXTEND_INREG:
20620 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
20621 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
20622 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
20623 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
20624 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
20625 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
20626 case X86ISD::SHUFP: // Handle all target specific shuffles
20627 case X86ISD::PALIGNR:
20628 case X86ISD::UNPCKH:
20629 case X86ISD::UNPCKL:
20630 case X86ISD::MOVHLPS:
20631 case X86ISD::MOVLHPS:
20632 case X86ISD::PSHUFD:
20633 case X86ISD::PSHUFHW:
20634 case X86ISD::PSHUFLW:
20635 case X86ISD::MOVSS:
20636 case X86ISD::MOVSD:
20637 case X86ISD::VPERMILP:
20638 case X86ISD::VPERM2X128:
20639 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
20640 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
20641 case ISD::INTRINSIC_WO_CHAIN:
20642 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
20643 case X86ISD::INSERTPS:
20644 return PerformINSERTPSCombine(N, DAG, Subtarget);
20650 /// isTypeDesirableForOp - Return true if the target has native support for
20651 /// the specified value type and it is 'desirable' to use the type for the
20652 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
20653 /// instruction encodings are longer and some i16 instructions are slow.
20654 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
20655 if (!isTypeLegal(VT))
20657 if (VT != MVT::i16)
20664 case ISD::SIGN_EXTEND:
20665 case ISD::ZERO_EXTEND:
20666 case ISD::ANY_EXTEND:
20679 /// IsDesirableToPromoteOp - This method query the target whether it is
20680 /// beneficial for dag combiner to promote the specified node. If true, it
20681 /// should return the desired promotion type by reference.
20682 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
20683 EVT VT = Op.getValueType();
20684 if (VT != MVT::i16)
20687 bool Promote = false;
20688 bool Commute = false;
20689 switch (Op.getOpcode()) {
20692 LoadSDNode *LD = cast<LoadSDNode>(Op);
20693 // If the non-extending load has a single use and it's not live out, then it
20694 // might be folded.
20695 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
20696 Op.hasOneUse()*/) {
20697 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
20698 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
20699 // The only case where we'd want to promote LOAD (rather then it being
20700 // promoted as an operand is when it's only use is liveout.
20701 if (UI->getOpcode() != ISD::CopyToReg)
20708 case ISD::SIGN_EXTEND:
20709 case ISD::ZERO_EXTEND:
20710 case ISD::ANY_EXTEND:
20715 SDValue N0 = Op.getOperand(0);
20716 // Look out for (store (shl (load), x)).
20717 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
20730 SDValue N0 = Op.getOperand(0);
20731 SDValue N1 = Op.getOperand(1);
20732 if (!Commute && MayFoldLoad(N1))
20734 // Avoid disabling potential load folding opportunities.
20735 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
20737 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
20747 //===----------------------------------------------------------------------===//
20748 // X86 Inline Assembly Support
20749 //===----------------------------------------------------------------------===//
20752 // Helper to match a string separated by whitespace.
20753 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
20754 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
20756 for (unsigned i = 0, e = args.size(); i != e; ++i) {
20757 StringRef piece(*args[i]);
20758 if (!s.startswith(piece)) // Check if the piece matches.
20761 s = s.substr(piece.size());
20762 StringRef::size_type pos = s.find_first_not_of(" \t");
20763 if (pos == 0) // We matched a prefix.
20771 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
20774 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
20776 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
20777 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
20778 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
20779 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
20781 if (AsmPieces.size() == 3)
20783 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
20790 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
20791 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
20793 std::string AsmStr = IA->getAsmString();
20795 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
20796 if (!Ty || Ty->getBitWidth() % 16 != 0)
20799 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
20800 SmallVector<StringRef, 4> AsmPieces;
20801 SplitString(AsmStr, AsmPieces, ";\n");
20803 switch (AsmPieces.size()) {
20804 default: return false;
20806 // FIXME: this should verify that we are targeting a 486 or better. If not,
20807 // we will turn this bswap into something that will be lowered to logical
20808 // ops instead of emitting the bswap asm. For now, we don't support 486 or
20809 // lower so don't worry about this.
20811 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
20812 matchAsm(AsmPieces[0], "bswapl", "$0") ||
20813 matchAsm(AsmPieces[0], "bswapq", "$0") ||
20814 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
20815 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
20816 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
20817 // No need to check constraints, nothing other than the equivalent of
20818 // "=r,0" would be valid here.
20819 return IntrinsicLowering::LowerToByteSwap(CI);
20822 // rorw $$8, ${0:w} --> llvm.bswap.i16
20823 if (CI->getType()->isIntegerTy(16) &&
20824 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
20825 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
20826 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
20828 const std::string &ConstraintsStr = IA->getConstraintString();
20829 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
20830 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
20831 if (clobbersFlagRegisters(AsmPieces))
20832 return IntrinsicLowering::LowerToByteSwap(CI);
20836 if (CI->getType()->isIntegerTy(32) &&
20837 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
20838 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
20839 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
20840 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
20842 const std::string &ConstraintsStr = IA->getConstraintString();
20843 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
20844 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
20845 if (clobbersFlagRegisters(AsmPieces))
20846 return IntrinsicLowering::LowerToByteSwap(CI);
20849 if (CI->getType()->isIntegerTy(64)) {
20850 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
20851 if (Constraints.size() >= 2 &&
20852 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
20853 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
20854 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
20855 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
20856 matchAsm(AsmPieces[1], "bswap", "%edx") &&
20857 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
20858 return IntrinsicLowering::LowerToByteSwap(CI);
20866 /// getConstraintType - Given a constraint letter, return the type of
20867 /// constraint it is for this target.
20868 X86TargetLowering::ConstraintType
20869 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
20870 if (Constraint.size() == 1) {
20871 switch (Constraint[0]) {
20882 return C_RegisterClass;
20906 return TargetLowering::getConstraintType(Constraint);
20909 /// Examine constraint type and operand type and determine a weight value.
20910 /// This object must already have been set up with the operand type
20911 /// and the current alternative constraint selected.
20912 TargetLowering::ConstraintWeight
20913 X86TargetLowering::getSingleConstraintMatchWeight(
20914 AsmOperandInfo &info, const char *constraint) const {
20915 ConstraintWeight weight = CW_Invalid;
20916 Value *CallOperandVal = info.CallOperandVal;
20917 // If we don't have a value, we can't do a match,
20918 // but allow it at the lowest weight.
20919 if (!CallOperandVal)
20921 Type *type = CallOperandVal->getType();
20922 // Look at the constraint type.
20923 switch (*constraint) {
20925 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
20936 if (CallOperandVal->getType()->isIntegerTy())
20937 weight = CW_SpecificReg;
20942 if (type->isFloatingPointTy())
20943 weight = CW_SpecificReg;
20946 if (type->isX86_MMXTy() && Subtarget->hasMMX())
20947 weight = CW_SpecificReg;
20951 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
20952 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
20953 weight = CW_Register;
20956 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
20957 if (C->getZExtValue() <= 31)
20958 weight = CW_Constant;
20962 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20963 if (C->getZExtValue() <= 63)
20964 weight = CW_Constant;
20968 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20969 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
20970 weight = CW_Constant;
20974 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20975 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
20976 weight = CW_Constant;
20980 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20981 if (C->getZExtValue() <= 3)
20982 weight = CW_Constant;
20986 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20987 if (C->getZExtValue() <= 0xff)
20988 weight = CW_Constant;
20993 if (dyn_cast<ConstantFP>(CallOperandVal)) {
20994 weight = CW_Constant;
20998 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20999 if ((C->getSExtValue() >= -0x80000000LL) &&
21000 (C->getSExtValue() <= 0x7fffffffLL))
21001 weight = CW_Constant;
21005 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
21006 if (C->getZExtValue() <= 0xffffffff)
21007 weight = CW_Constant;
21014 /// LowerXConstraint - try to replace an X constraint, which matches anything,
21015 /// with another that has more specific requirements based on the type of the
21016 /// corresponding operand.
21017 const char *X86TargetLowering::
21018 LowerXConstraint(EVT ConstraintVT) const {
21019 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
21020 // 'f' like normal targets.
21021 if (ConstraintVT.isFloatingPoint()) {
21022 if (Subtarget->hasSSE2())
21024 if (Subtarget->hasSSE1())
21028 return TargetLowering::LowerXConstraint(ConstraintVT);
21031 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
21032 /// vector. If it is invalid, don't add anything to Ops.
21033 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
21034 std::string &Constraint,
21035 std::vector<SDValue>&Ops,
21036 SelectionDAG &DAG) const {
21039 // Only support length 1 constraints for now.
21040 if (Constraint.length() > 1) return;
21042 char ConstraintLetter = Constraint[0];
21043 switch (ConstraintLetter) {
21046 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
21047 if (C->getZExtValue() <= 31) {
21048 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
21054 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
21055 if (C->getZExtValue() <= 63) {
21056 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
21062 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
21063 if (isInt<8>(C->getSExtValue())) {
21064 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
21070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
21071 if (C->getZExtValue() <= 255) {
21072 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
21078 // 32-bit signed value
21079 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
21080 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
21081 C->getSExtValue())) {
21082 // Widen to 64 bits here to get it sign extended.
21083 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
21086 // FIXME gcc accepts some relocatable values here too, but only in certain
21087 // memory models; it's complicated.
21092 // 32-bit unsigned value
21093 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
21094 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
21095 C->getZExtValue())) {
21096 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
21100 // FIXME gcc accepts some relocatable values here too, but only in certain
21101 // memory models; it's complicated.
21105 // Literal immediates are always ok.
21106 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
21107 // Widen to 64 bits here to get it sign extended.
21108 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
21112 // In any sort of PIC mode addresses need to be computed at runtime by
21113 // adding in a register or some sort of table lookup. These can't
21114 // be used as immediates.
21115 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
21118 // If we are in non-pic codegen mode, we allow the address of a global (with
21119 // an optional displacement) to be used with 'i'.
21120 GlobalAddressSDNode *GA = nullptr;
21121 int64_t Offset = 0;
21123 // Match either (GA), (GA+C), (GA+C1+C2), etc.
21125 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
21126 Offset += GA->getOffset();
21128 } else if (Op.getOpcode() == ISD::ADD) {
21129 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
21130 Offset += C->getZExtValue();
21131 Op = Op.getOperand(0);
21134 } else if (Op.getOpcode() == ISD::SUB) {
21135 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
21136 Offset += -C->getZExtValue();
21137 Op = Op.getOperand(0);
21142 // Otherwise, this isn't something we can handle, reject it.
21146 const GlobalValue *GV = GA->getGlobal();
21147 // If we require an extra load to get this address, as in PIC mode, we
21148 // can't accept it.
21149 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
21150 getTargetMachine())))
21153 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
21154 GA->getValueType(0), Offset);
21159 if (Result.getNode()) {
21160 Ops.push_back(Result);
21163 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
21166 std::pair<unsigned, const TargetRegisterClass*>
21167 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
21169 // First, see if this is a constraint that directly corresponds to an LLVM
21171 if (Constraint.size() == 1) {
21172 // GCC Constraint Letters
21173 switch (Constraint[0]) {
21175 // TODO: Slight differences here in allocation order and leaving
21176 // RIP in the class. Do they matter any more here than they do
21177 // in the normal allocation?
21178 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
21179 if (Subtarget->is64Bit()) {
21180 if (VT == MVT::i32 || VT == MVT::f32)
21181 return std::make_pair(0U, &X86::GR32RegClass);
21182 if (VT == MVT::i16)
21183 return std::make_pair(0U, &X86::GR16RegClass);
21184 if (VT == MVT::i8 || VT == MVT::i1)
21185 return std::make_pair(0U, &X86::GR8RegClass);
21186 if (VT == MVT::i64 || VT == MVT::f64)
21187 return std::make_pair(0U, &X86::GR64RegClass);
21190 // 32-bit fallthrough
21191 case 'Q': // Q_REGS
21192 if (VT == MVT::i32 || VT == MVT::f32)
21193 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
21194 if (VT == MVT::i16)
21195 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
21196 if (VT == MVT::i8 || VT == MVT::i1)
21197 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
21198 if (VT == MVT::i64)
21199 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
21201 case 'r': // GENERAL_REGS
21202 case 'l': // INDEX_REGS
21203 if (VT == MVT::i8 || VT == MVT::i1)
21204 return std::make_pair(0U, &X86::GR8RegClass);
21205 if (VT == MVT::i16)
21206 return std::make_pair(0U, &X86::GR16RegClass);
21207 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
21208 return std::make_pair(0U, &X86::GR32RegClass);
21209 return std::make_pair(0U, &X86::GR64RegClass);
21210 case 'R': // LEGACY_REGS
21211 if (VT == MVT::i8 || VT == MVT::i1)
21212 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
21213 if (VT == MVT::i16)
21214 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
21215 if (VT == MVT::i32 || !Subtarget->is64Bit())
21216 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
21217 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
21218 case 'f': // FP Stack registers.
21219 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
21220 // value to the correct fpstack register class.
21221 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
21222 return std::make_pair(0U, &X86::RFP32RegClass);
21223 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
21224 return std::make_pair(0U, &X86::RFP64RegClass);
21225 return std::make_pair(0U, &X86::RFP80RegClass);
21226 case 'y': // MMX_REGS if MMX allowed.
21227 if (!Subtarget->hasMMX()) break;
21228 return std::make_pair(0U, &X86::VR64RegClass);
21229 case 'Y': // SSE_REGS if SSE2 allowed
21230 if (!Subtarget->hasSSE2()) break;
21232 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
21233 if (!Subtarget->hasSSE1()) break;
21235 switch (VT.SimpleTy) {
21237 // Scalar SSE types.
21240 return std::make_pair(0U, &X86::FR32RegClass);
21243 return std::make_pair(0U, &X86::FR64RegClass);
21251 return std::make_pair(0U, &X86::VR128RegClass);
21259 return std::make_pair(0U, &X86::VR256RegClass);
21264 return std::make_pair(0U, &X86::VR512RegClass);
21270 // Use the default implementation in TargetLowering to convert the register
21271 // constraint into a member of a register class.
21272 std::pair<unsigned, const TargetRegisterClass*> Res;
21273 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
21275 // Not found as a standard register?
21277 // Map st(0) -> st(7) -> ST0
21278 if (Constraint.size() == 7 && Constraint[0] == '{' &&
21279 tolower(Constraint[1]) == 's' &&
21280 tolower(Constraint[2]) == 't' &&
21281 Constraint[3] == '(' &&
21282 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
21283 Constraint[5] == ')' &&
21284 Constraint[6] == '}') {
21286 Res.first = X86::ST0+Constraint[4]-'0';
21287 Res.second = &X86::RFP80RegClass;
21291 // GCC allows "st(0)" to be called just plain "st".
21292 if (StringRef("{st}").equals_lower(Constraint)) {
21293 Res.first = X86::ST0;
21294 Res.second = &X86::RFP80RegClass;
21299 if (StringRef("{flags}").equals_lower(Constraint)) {
21300 Res.first = X86::EFLAGS;
21301 Res.second = &X86::CCRRegClass;
21305 // 'A' means EAX + EDX.
21306 if (Constraint == "A") {
21307 Res.first = X86::EAX;
21308 Res.second = &X86::GR32_ADRegClass;
21314 // Otherwise, check to see if this is a register class of the wrong value
21315 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
21316 // turn into {ax},{dx}.
21317 if (Res.second->hasType(VT))
21318 return Res; // Correct type already, nothing to do.
21320 // All of the single-register GCC register classes map their values onto
21321 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
21322 // really want an 8-bit or 32-bit register, map to the appropriate register
21323 // class and return the appropriate register.
21324 if (Res.second == &X86::GR16RegClass) {
21325 if (VT == MVT::i8 || VT == MVT::i1) {
21326 unsigned DestReg = 0;
21327 switch (Res.first) {
21329 case X86::AX: DestReg = X86::AL; break;
21330 case X86::DX: DestReg = X86::DL; break;
21331 case X86::CX: DestReg = X86::CL; break;
21332 case X86::BX: DestReg = X86::BL; break;
21335 Res.first = DestReg;
21336 Res.second = &X86::GR8RegClass;
21338 } else if (VT == MVT::i32 || VT == MVT::f32) {
21339 unsigned DestReg = 0;
21340 switch (Res.first) {
21342 case X86::AX: DestReg = X86::EAX; break;
21343 case X86::DX: DestReg = X86::EDX; break;
21344 case X86::CX: DestReg = X86::ECX; break;
21345 case X86::BX: DestReg = X86::EBX; break;
21346 case X86::SI: DestReg = X86::ESI; break;
21347 case X86::DI: DestReg = X86::EDI; break;
21348 case X86::BP: DestReg = X86::EBP; break;
21349 case X86::SP: DestReg = X86::ESP; break;
21352 Res.first = DestReg;
21353 Res.second = &X86::GR32RegClass;
21355 } else if (VT == MVT::i64 || VT == MVT::f64) {
21356 unsigned DestReg = 0;
21357 switch (Res.first) {
21359 case X86::AX: DestReg = X86::RAX; break;
21360 case X86::DX: DestReg = X86::RDX; break;
21361 case X86::CX: DestReg = X86::RCX; break;
21362 case X86::BX: DestReg = X86::RBX; break;
21363 case X86::SI: DestReg = X86::RSI; break;
21364 case X86::DI: DestReg = X86::RDI; break;
21365 case X86::BP: DestReg = X86::RBP; break;
21366 case X86::SP: DestReg = X86::RSP; break;
21369 Res.first = DestReg;
21370 Res.second = &X86::GR64RegClass;
21373 } else if (Res.second == &X86::FR32RegClass ||
21374 Res.second == &X86::FR64RegClass ||
21375 Res.second == &X86::VR128RegClass ||
21376 Res.second == &X86::VR256RegClass ||
21377 Res.second == &X86::FR32XRegClass ||
21378 Res.second == &X86::FR64XRegClass ||
21379 Res.second == &X86::VR128XRegClass ||
21380 Res.second == &X86::VR256XRegClass ||
21381 Res.second == &X86::VR512RegClass) {
21382 // Handle references to XMM physical registers that got mapped into the
21383 // wrong class. This can happen with constraints like {xmm0} where the
21384 // target independent register mapper will just pick the first match it can
21385 // find, ignoring the required type.
21387 if (VT == MVT::f32 || VT == MVT::i32)
21388 Res.second = &X86::FR32RegClass;
21389 else if (VT == MVT::f64 || VT == MVT::i64)
21390 Res.second = &X86::FR64RegClass;
21391 else if (X86::VR128RegClass.hasType(VT))
21392 Res.second = &X86::VR128RegClass;
21393 else if (X86::VR256RegClass.hasType(VT))
21394 Res.second = &X86::VR256RegClass;
21395 else if (X86::VR512RegClass.hasType(VT))
21396 Res.second = &X86::VR512RegClass;
21402 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
21404 // Scaling factors are not free at all.
21405 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
21406 // will take 2 allocations in the out of order engine instead of 1
21407 // for plain addressing mode, i.e. inst (reg1).
21409 // vaddps (%rsi,%drx), %ymm0, %ymm1
21410 // Requires two allocations (one for the load, one for the computation)
21412 // vaddps (%rsi), %ymm0, %ymm1
21413 // Requires just 1 allocation, i.e., freeing allocations for other operations
21414 // and having less micro operations to execute.
21416 // For some X86 architectures, this is even worse because for instance for
21417 // stores, the complex addressing mode forces the instruction to use the
21418 // "load" ports instead of the dedicated "store" port.
21419 // E.g., on Haswell:
21420 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
21421 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
21422 if (isLegalAddressingMode(AM, Ty))
21423 // Scale represents reg2 * scale, thus account for 1
21424 // as soon as we use a second register.
21425 return AM.Scale != 0;