1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit bounday. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
177 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
178 unsigned IdxVal, SelectionDAG &DAG,
180 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
181 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
184 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
185 /// instructions. This is used because creating CONCAT_VECTOR nodes of
186 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
187 /// large BUILD_VECTORS.
188 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
195 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
196 unsigned NumElems, SelectionDAG &DAG,
198 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
199 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
202 // FIXME: This should stop caching the target machine as soon as
203 // we can remove resetOperationActions et al.
204 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
205 : TargetLowering(TM) {
206 Subtarget = &TM.getSubtarget<X86Subtarget>();
207 X86ScalarSSEf64 = Subtarget->hasSSE2();
208 X86ScalarSSEf32 = Subtarget->hasSSE1();
209 TD = getDataLayout();
211 resetOperationActions();
214 void X86TargetLowering::resetOperationActions() {
215 const TargetMachine &TM = getTargetMachine();
216 static bool FirstTimeThrough = true;
218 // If none of the target options have changed, then we don't need to reset the
219 // operation actions.
220 if (!FirstTimeThrough && TO == TM.Options) return;
222 if (!FirstTimeThrough) {
223 // Reinitialize the actions.
225 FirstTimeThrough = false;
230 // Set up the TargetLowering object.
231 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
233 // X86 is weird, it always uses i8 for shift amounts and setcc results.
234 setBooleanContents(ZeroOrOneBooleanContent);
235 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
236 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
238 // For 64-bit since we have so many registers use the ILP scheduler, for
239 // 32-bit code use the register pressure specific scheduling.
240 // For Atom, always use ILP scheduling.
241 if (Subtarget->isAtom())
242 setSchedulingPreference(Sched::ILP);
243 else if (Subtarget->is64Bit())
244 setSchedulingPreference(Sched::ILP);
246 setSchedulingPreference(Sched::RegPressure);
247 const X86RegisterInfo *RegInfo =
248 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
249 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
251 // Bypass expensive divides on Atom when compiling with O2
252 if (TM.getOptLevel() >= CodeGenOpt::Default) {
253 if (Subtarget->hasSlowDivide32())
254 addBypassSlowDiv(32, 8);
255 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
256 addBypassSlowDiv(64, 16);
259 if (Subtarget->isTargetKnownWindowsMSVC()) {
260 // Setup Windows compiler runtime calls.
261 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
262 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
263 setLibcallName(RTLIB::SREM_I64, "_allrem");
264 setLibcallName(RTLIB::UREM_I64, "_aullrem");
265 setLibcallName(RTLIB::MUL_I64, "_allmul");
266 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
270 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
272 // The _ftol2 runtime function has an unusual calling conv, which
273 // is modeled by a special pseudo-instruction.
274 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
276 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
277 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
280 if (Subtarget->isTargetDarwin()) {
281 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
282 setUseUnderscoreSetJmp(false);
283 setUseUnderscoreLongJmp(false);
284 } else if (Subtarget->isTargetWindowsGNU()) {
285 // MS runtime is weird: it exports _setjmp, but longjmp!
286 setUseUnderscoreSetJmp(true);
287 setUseUnderscoreLongJmp(false);
289 setUseUnderscoreSetJmp(true);
290 setUseUnderscoreLongJmp(true);
293 // Set up the register classes.
294 addRegisterClass(MVT::i8, &X86::GR8RegClass);
295 addRegisterClass(MVT::i16, &X86::GR16RegClass);
296 addRegisterClass(MVT::i32, &X86::GR32RegClass);
297 if (Subtarget->is64Bit())
298 addRegisterClass(MVT::i64, &X86::GR64RegClass);
300 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
302 // We don't accept any truncstore of integer registers.
303 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
304 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
305 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
306 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
307 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
308 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
310 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
312 // SETOEQ and SETUNE require checking two conditions.
313 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
314 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
315 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
317 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
318 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
320 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
322 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
324 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
328 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
329 } else if (!TM.Options.UseSoftFloat) {
330 // We have an algorithm for SSE2->double, and we turn this into a
331 // 64-bit FILD followed by conditional FADD for other targets.
332 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
333 // We have an algorithm for SSE2, and we turn this into a 64-bit
334 // FILD for other targets.
335 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
338 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
340 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
343 if (!TM.Options.UseSoftFloat) {
344 // SSE has no i16 to fp conversion, only i32
345 if (X86ScalarSSEf32) {
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
347 // f32 and f64 cases are Legal, f80 case is not
348 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
358 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
359 // are Legal, f80 is custom lowered.
360 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
363 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
365 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
366 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
368 if (X86ScalarSSEf32) {
369 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
370 // f32 and f64 cases are Legal, f80 case is not
371 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
374 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
377 // Handle FP_TO_UINT by promoting the destination to a larger signed
379 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
381 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
383 if (Subtarget->is64Bit()) {
384 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
385 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
386 } else if (!TM.Options.UseSoftFloat) {
387 // Since AVX is a superset of SSE3, only check for SSE here.
388 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
389 // Expand FP_TO_UINT into a select.
390 // FIXME: We would like to use a Custom expander here eventually to do
391 // the optimal thing for SSE vs. the default expansion in the legalizer.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
394 // With SSE3 we can use fisttpll to convert to a signed i64; without
395 // SSE, we're stuck with a fistpll.
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
399 if (isTargetFTOL()) {
400 // Use the _ftol2 runtime function, which has a pseudo-instruction
401 // to handle its weird calling convention.
402 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
405 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
406 if (!X86ScalarSSEf64) {
407 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
408 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
409 if (Subtarget->is64Bit()) {
410 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
411 // Without SSE, i64->f64 goes through memory.
412 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
416 // Scalar integer divide and remainder are lowered to use operations that
417 // produce two results, to match the available instructions. This exposes
418 // the two-result form to trivial CSE, which is able to combine x/y and x%y
419 // into a single instruction.
421 // Scalar integer multiply-high is also lowered to use two-result
422 // operations, to match the available instructions. However, plain multiply
423 // (low) operations are left as Legal, as there are single-result
424 // instructions for this in x86. Using the two-result multiply instructions
425 // when both high and low results are needed must be arranged by dagcombine.
426 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
428 setOperationAction(ISD::MULHS, VT, Expand);
429 setOperationAction(ISD::MULHU, VT, Expand);
430 setOperationAction(ISD::SDIV, VT, Expand);
431 setOperationAction(ISD::UDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UREM, VT, Expand);
435 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
436 setOperationAction(ISD::ADDC, VT, Custom);
437 setOperationAction(ISD::ADDE, VT, Custom);
438 setOperationAction(ISD::SUBC, VT, Custom);
439 setOperationAction(ISD::SUBE, VT, Custom);
442 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
443 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
444 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
446 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
449 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
450 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
457 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
458 if (Subtarget->is64Bit())
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
463 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
464 setOperationAction(ISD::FREM , MVT::f32 , Expand);
465 setOperationAction(ISD::FREM , MVT::f64 , Expand);
466 setOperationAction(ISD::FREM , MVT::f80 , Expand);
467 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
469 // Promote the i8 variants and force them on up to i32 which has a shorter
471 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
472 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
473 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
474 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
475 if (Subtarget->hasBMI()) {
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
481 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
482 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
483 if (Subtarget->is64Bit())
484 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
487 if (Subtarget->hasLZCNT()) {
488 // When promoting the i8 variants, force them to i32 for a shorter
490 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
491 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
493 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
494 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
496 if (Subtarget->is64Bit())
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
499 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
500 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
501 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
505 if (Subtarget->is64Bit()) {
506 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
507 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
511 // Special handling for half-precision floating point conversions.
512 // If we don't have F16C support, then lower half float conversions
513 // into library calls.
514 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
515 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
516 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
519 // There's never any support for operations beyond MVT::f32.
520 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
521 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
522 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
525 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
527 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
528 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
530 if (Subtarget->hasPOPCNT()) {
531 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
533 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
534 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
535 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
536 if (Subtarget->is64Bit())
537 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
540 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
542 if (!Subtarget->hasMOVBE())
543 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
545 // These should be promoted to a larger select which is supported.
546 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
547 // X86 wants to expand cmov itself.
548 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
549 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
550 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
552 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
553 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
555 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
556 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
558 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
559 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
560 if (Subtarget->is64Bit()) {
561 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
564 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
565 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
566 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
567 // support continuation, user-level threading, and etc.. As a result, no
568 // other SjLj exception interfaces are implemented and please don't build
569 // your own exception handling based on them.
570 // LLVM/Clang supports zero-cost DWARF exception handling.
571 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
572 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
575 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
576 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
577 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
578 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
579 if (Subtarget->is64Bit())
580 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
581 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
582 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
583 if (Subtarget->is64Bit()) {
584 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
585 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
586 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
587 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
588 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
590 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
591 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
592 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
593 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
596 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
597 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
600 if (Subtarget->hasSSE1())
601 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
603 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
605 // Expand certain atomics
606 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
608 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
609 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
610 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
613 if (Subtarget->hasCmpxchg16b()) {
614 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
617 // FIXME - use subtarget debug flags
618 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
619 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
620 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
623 if (Subtarget->is64Bit()) {
624 setExceptionPointerRegister(X86::RAX);
625 setExceptionSelectorRegister(X86::RDX);
627 setExceptionPointerRegister(X86::EAX);
628 setExceptionSelectorRegister(X86::EDX);
630 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
631 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
633 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
634 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
636 setOperationAction(ISD::TRAP, MVT::Other, Legal);
637 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
639 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
640 setOperationAction(ISD::VASTART , MVT::Other, Custom);
641 setOperationAction(ISD::VAEND , MVT::Other, Expand);
642 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
643 // TargetInfo::X86_64ABIBuiltinVaList
644 setOperationAction(ISD::VAARG , MVT::Other, Custom);
645 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
647 // TargetInfo::CharPtrBuiltinVaList
648 setOperationAction(ISD::VAARG , MVT::Other, Expand);
649 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
652 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
653 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
655 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
657 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
658 // f32 and f64 use SSE.
659 // Set up the FP register classes.
660 addRegisterClass(MVT::f32, &X86::FR32RegClass);
661 addRegisterClass(MVT::f64, &X86::FR64RegClass);
663 // Use ANDPD to simulate FABS.
664 setOperationAction(ISD::FABS , MVT::f64, Custom);
665 setOperationAction(ISD::FABS , MVT::f32, Custom);
667 // Use XORP to simulate FNEG.
668 setOperationAction(ISD::FNEG , MVT::f64, Custom);
669 setOperationAction(ISD::FNEG , MVT::f32, Custom);
671 // Use ANDPD and ORPD to simulate FCOPYSIGN.
672 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
673 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
675 // Lower this to FGETSIGNx86 plus an AND.
676 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
677 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
679 // We don't support sin/cos/fmod
680 setOperationAction(ISD::FSIN , MVT::f64, Expand);
681 setOperationAction(ISD::FCOS , MVT::f64, Expand);
682 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
683 setOperationAction(ISD::FSIN , MVT::f32, Expand);
684 setOperationAction(ISD::FCOS , MVT::f32, Expand);
685 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
687 // Expand FP immediates into loads from the stack, except for the special
689 addLegalFPImmediate(APFloat(+0.0)); // xorpd
690 addLegalFPImmediate(APFloat(+0.0f)); // xorps
691 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
692 // Use SSE for f32, x87 for f64.
693 // Set up the FP register classes.
694 addRegisterClass(MVT::f32, &X86::FR32RegClass);
695 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
697 // Use ANDPS to simulate FABS.
698 setOperationAction(ISD::FABS , MVT::f32, Custom);
700 // Use XORP to simulate FNEG.
701 setOperationAction(ISD::FNEG , MVT::f32, Custom);
703 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
705 // Use ANDPS and ORPS to simulate FCOPYSIGN.
706 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
707 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
709 // We don't support sin/cos/fmod
710 setOperationAction(ISD::FSIN , MVT::f32, Expand);
711 setOperationAction(ISD::FCOS , MVT::f32, Expand);
712 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
714 // Special cases we handle for FP constants.
715 addLegalFPImmediate(APFloat(+0.0f)); // xorps
716 addLegalFPImmediate(APFloat(+0.0)); // FLD0
717 addLegalFPImmediate(APFloat(+1.0)); // FLD1
718 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
719 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
721 if (!TM.Options.UnsafeFPMath) {
722 setOperationAction(ISD::FSIN , MVT::f64, Expand);
723 setOperationAction(ISD::FCOS , MVT::f64, Expand);
724 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
726 } else if (!TM.Options.UseSoftFloat) {
727 // f32 and f64 in x87.
728 // Set up the FP register classes.
729 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
730 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
732 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
733 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
734 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
735 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
737 if (!TM.Options.UnsafeFPMath) {
738 setOperationAction(ISD::FSIN , MVT::f64, Expand);
739 setOperationAction(ISD::FSIN , MVT::f32, Expand);
740 setOperationAction(ISD::FCOS , MVT::f64, Expand);
741 setOperationAction(ISD::FCOS , MVT::f32, Expand);
742 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
743 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
745 addLegalFPImmediate(APFloat(+0.0)); // FLD0
746 addLegalFPImmediate(APFloat(+1.0)); // FLD1
747 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
748 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
749 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
750 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
751 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
752 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
755 // We don't support FMA.
756 setOperationAction(ISD::FMA, MVT::f64, Expand);
757 setOperationAction(ISD::FMA, MVT::f32, Expand);
759 // Long double always uses X87.
760 if (!TM.Options.UseSoftFloat) {
761 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
762 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
763 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
765 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
766 addLegalFPImmediate(TmpFlt); // FLD0
768 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
771 APFloat TmpFlt2(+1.0);
772 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
774 addLegalFPImmediate(TmpFlt2); // FLD1
775 TmpFlt2.changeSign();
776 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
779 if (!TM.Options.UnsafeFPMath) {
780 setOperationAction(ISD::FSIN , MVT::f80, Expand);
781 setOperationAction(ISD::FCOS , MVT::f80, Expand);
782 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
785 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
786 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
787 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
788 setOperationAction(ISD::FRINT, MVT::f80, Expand);
789 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
790 setOperationAction(ISD::FMA, MVT::f80, Expand);
793 // Always use a library call for pow.
794 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
795 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
796 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
798 setOperationAction(ISD::FLOG, MVT::f80, Expand);
799 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
800 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
801 setOperationAction(ISD::FEXP, MVT::f80, Expand);
802 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
803 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
804 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
806 // First set operation action for all vector types to either promote
807 // (for widening) or expand (for scalarization). Then we will selectively
808 // turn on ones that can be effectively codegen'd.
809 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
810 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
811 MVT VT = (MVT::SimpleValueType)i;
812 setOperationAction(ISD::ADD , VT, Expand);
813 setOperationAction(ISD::SUB , VT, Expand);
814 setOperationAction(ISD::FADD, VT, Expand);
815 setOperationAction(ISD::FNEG, VT, Expand);
816 setOperationAction(ISD::FSUB, VT, Expand);
817 setOperationAction(ISD::MUL , VT, Expand);
818 setOperationAction(ISD::FMUL, VT, Expand);
819 setOperationAction(ISD::SDIV, VT, Expand);
820 setOperationAction(ISD::UDIV, VT, Expand);
821 setOperationAction(ISD::FDIV, VT, Expand);
822 setOperationAction(ISD::SREM, VT, Expand);
823 setOperationAction(ISD::UREM, VT, Expand);
824 setOperationAction(ISD::LOAD, VT, Expand);
825 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
826 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
827 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
828 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
829 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
830 setOperationAction(ISD::FABS, VT, Expand);
831 setOperationAction(ISD::FSIN, VT, Expand);
832 setOperationAction(ISD::FSINCOS, VT, Expand);
833 setOperationAction(ISD::FCOS, VT, Expand);
834 setOperationAction(ISD::FSINCOS, VT, Expand);
835 setOperationAction(ISD::FREM, VT, Expand);
836 setOperationAction(ISD::FMA, VT, Expand);
837 setOperationAction(ISD::FPOWI, VT, Expand);
838 setOperationAction(ISD::FSQRT, VT, Expand);
839 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
840 setOperationAction(ISD::FFLOOR, VT, Expand);
841 setOperationAction(ISD::FCEIL, VT, Expand);
842 setOperationAction(ISD::FTRUNC, VT, Expand);
843 setOperationAction(ISD::FRINT, VT, Expand);
844 setOperationAction(ISD::FNEARBYINT, VT, Expand);
845 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
846 setOperationAction(ISD::MULHS, VT, Expand);
847 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
848 setOperationAction(ISD::MULHU, VT, Expand);
849 setOperationAction(ISD::SDIVREM, VT, Expand);
850 setOperationAction(ISD::UDIVREM, VT, Expand);
851 setOperationAction(ISD::FPOW, VT, Expand);
852 setOperationAction(ISD::CTPOP, VT, Expand);
853 setOperationAction(ISD::CTTZ, VT, Expand);
854 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
855 setOperationAction(ISD::CTLZ, VT, Expand);
856 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
857 setOperationAction(ISD::SHL, VT, Expand);
858 setOperationAction(ISD::SRA, VT, Expand);
859 setOperationAction(ISD::SRL, VT, Expand);
860 setOperationAction(ISD::ROTL, VT, Expand);
861 setOperationAction(ISD::ROTR, VT, Expand);
862 setOperationAction(ISD::BSWAP, VT, Expand);
863 setOperationAction(ISD::SETCC, VT, Expand);
864 setOperationAction(ISD::FLOG, VT, Expand);
865 setOperationAction(ISD::FLOG2, VT, Expand);
866 setOperationAction(ISD::FLOG10, VT, Expand);
867 setOperationAction(ISD::FEXP, VT, Expand);
868 setOperationAction(ISD::FEXP2, VT, Expand);
869 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
870 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
871 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
872 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
873 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
874 setOperationAction(ISD::TRUNCATE, VT, Expand);
875 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
876 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
877 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
878 setOperationAction(ISD::VSELECT, VT, Expand);
879 setOperationAction(ISD::SELECT_CC, VT, Expand);
880 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
881 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
882 setTruncStoreAction(VT,
883 (MVT::SimpleValueType)InnerVT, Expand);
884 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
885 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
887 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
888 // we have to deal with them whether we ask for Expansion or not. Setting
889 // Expand causes its own optimisation problems though, so leave them legal.
890 if (VT.getVectorElementType() == MVT::i1)
891 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
894 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
895 // with -msoft-float, disable use of MMX as well.
896 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
897 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
898 // No operations on x86mmx supported, everything uses intrinsics.
901 // MMX-sized vectors (other than x86mmx) are expected to be expanded
902 // into smaller operations.
903 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
904 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
905 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
906 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
907 setOperationAction(ISD::AND, MVT::v8i8, Expand);
908 setOperationAction(ISD::AND, MVT::v4i16, Expand);
909 setOperationAction(ISD::AND, MVT::v2i32, Expand);
910 setOperationAction(ISD::AND, MVT::v1i64, Expand);
911 setOperationAction(ISD::OR, MVT::v8i8, Expand);
912 setOperationAction(ISD::OR, MVT::v4i16, Expand);
913 setOperationAction(ISD::OR, MVT::v2i32, Expand);
914 setOperationAction(ISD::OR, MVT::v1i64, Expand);
915 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
916 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
917 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
918 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
921 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
922 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
923 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
924 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
925 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
926 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
927 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
930 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
931 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
933 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
934 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
936 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
937 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
938 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
939 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
940 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
941 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
942 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
943 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
944 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
945 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
946 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
947 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
948 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
951 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
952 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
954 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
955 // registers cannot be used even for integer operations.
956 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
957 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
958 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
959 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
961 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
962 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
963 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
964 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
965 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
966 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
967 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
968 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
969 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
970 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
971 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
972 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
973 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
974 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
975 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
976 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
977 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
978 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
979 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
980 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
981 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
982 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
984 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
985 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
986 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
987 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
989 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
990 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
993 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
995 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
996 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
997 MVT VT = (MVT::SimpleValueType)i;
998 // Do not attempt to custom lower non-power-of-2 vectors
999 if (!isPowerOf2_32(VT.getVectorNumElements()))
1001 // Do not attempt to custom lower non-128-bit vectors
1002 if (!VT.is128BitVector())
1004 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1005 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1006 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1009 // We support custom legalizing of sext and anyext loads for specific
1010 // memory vector types which we can load as a scalar (or sequence of
1011 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1012 // loads these must work with a single scalar load.
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1014 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1015 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1023 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1024 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1025 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1026 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1027 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1028 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1030 if (Subtarget->is64Bit()) {
1031 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1032 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1035 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1036 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1037 MVT VT = (MVT::SimpleValueType)i;
1039 // Do not attempt to promote non-128-bit vectors
1040 if (!VT.is128BitVector())
1043 setOperationAction(ISD::AND, VT, Promote);
1044 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1045 setOperationAction(ISD::OR, VT, Promote);
1046 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1047 setOperationAction(ISD::XOR, VT, Promote);
1048 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1049 setOperationAction(ISD::LOAD, VT, Promote);
1050 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1051 setOperationAction(ISD::SELECT, VT, Promote);
1052 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1055 // Custom lower v2i64 and v2f64 selects.
1056 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1057 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1058 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1059 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1061 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1062 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1065 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1066 // As there is no 64-bit GPR available, we need build a special custom
1067 // sequence to convert from v2i32 to v2f32.
1068 if (!Subtarget->is64Bit())
1069 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1071 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1072 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1074 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1076 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1077 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1078 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1081 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1082 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1085 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1087 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1088 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1089 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1090 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1091 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1093 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1098 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1101 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1102 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1104 // FIXME: Do we need to handle scalar-to-vector here?
1105 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1107 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1110 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1111 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1112 // There is no BLENDI for byte vectors. We don't need to custom lower
1113 // some vselects for now.
1114 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1116 // SSE41 brings specific instructions for doing vector sign extend even in
1117 // cases where we don't have SRA.
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1119 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1120 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1122 // i8 and i16 vectors are custom because the source register and source
1123 // source memory operand types are not the same width. f32 vectors are
1124 // custom since the immediate controlling the insert encodes additional
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1128 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1129 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1133 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1134 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1136 // FIXME: these should be Legal, but that's only for the case where
1137 // the index is constant. For now custom expand to deal with that.
1138 if (Subtarget->is64Bit()) {
1139 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1144 if (Subtarget->hasSSE2()) {
1145 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1146 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1148 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1149 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1151 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1152 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1154 // In the customized shift lowering, the legal cases in AVX2 will be
1156 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1157 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1159 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1160 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1162 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1165 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1166 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1171 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1173 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1174 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1175 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1177 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1188 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1190 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1201 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1203 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1204 // even though v8i16 is a legal type.
1205 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1206 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1207 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1209 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1210 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1211 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1213 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1214 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1216 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1218 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1219 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1221 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1225 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1229 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1230 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1233 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1234 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1238 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1239 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1243 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1245 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1246 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1248 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1249 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1251 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1252 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1254 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1255 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1256 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1257 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1258 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1259 setOperationAction(ISD::FMA, MVT::f32, Legal);
1260 setOperationAction(ISD::FMA, MVT::f64, Legal);
1263 if (Subtarget->hasInt256()) {
1264 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1265 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1266 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1267 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1269 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1270 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1271 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1272 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1274 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1275 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1276 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1277 // Don't lower v32i8 because there is no 128-bit byte mul
1279 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1280 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1281 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1282 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1284 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1285 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1287 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1288 // when we have a 256bit-wide blend with immediate.
1289 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1291 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1292 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1293 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1294 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1296 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1297 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1298 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1299 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1301 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1302 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1303 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1304 // Don't lower v32i8 because there is no 128-bit byte mul
1307 // In the customized shift lowering, the legal cases in AVX2 will be
1309 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1310 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1312 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1313 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1315 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1317 // Custom lower several nodes for 256-bit types.
1318 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1319 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1320 MVT VT = (MVT::SimpleValueType)i;
1322 // Extract subvector is special because the value type
1323 // (result) is 128-bit but the source is 256-bit wide.
1324 if (VT.is128BitVector())
1325 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1327 // Do not attempt to custom lower other non-256-bit vectors
1328 if (!VT.is256BitVector())
1331 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1332 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1333 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1334 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1335 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1336 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1337 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1340 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1341 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1342 MVT VT = (MVT::SimpleValueType)i;
1344 // Do not attempt to promote non-256-bit vectors
1345 if (!VT.is256BitVector())
1348 setOperationAction(ISD::AND, VT, Promote);
1349 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1350 setOperationAction(ISD::OR, VT, Promote);
1351 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1352 setOperationAction(ISD::XOR, VT, Promote);
1353 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1354 setOperationAction(ISD::LOAD, VT, Promote);
1355 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1356 setOperationAction(ISD::SELECT, VT, Promote);
1357 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1361 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1362 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1363 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1364 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1365 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1367 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1368 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1369 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1371 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1372 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1373 setOperationAction(ISD::XOR, MVT::i1, Legal);
1374 setOperationAction(ISD::OR, MVT::i1, Legal);
1375 setOperationAction(ISD::AND, MVT::i1, Legal);
1376 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1377 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1378 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1379 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1383 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1384 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1385 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1386 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1390 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1391 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1392 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1393 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1396 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1399 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1400 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1401 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1402 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1403 if (Subtarget->is64Bit()) {
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1406 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1407 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1410 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1411 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1412 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1415 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1563 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1566 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1567 // of this type with custom code.
1568 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1569 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1570 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1574 // We want to custom lower some of our intrinsics.
1575 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1577 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1578 if (!Subtarget->is64Bit())
1579 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1581 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1582 // handle type legalization for these operations here.
1584 // FIXME: We really should do custom legalization for addition and
1585 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1586 // than generic legalization for 64-bit multiplication-with-overflow, though.
1587 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1588 // Add/Sub/Mul with overflow operations are custom lowered.
1590 setOperationAction(ISD::SADDO, VT, Custom);
1591 setOperationAction(ISD::UADDO, VT, Custom);
1592 setOperationAction(ISD::SSUBO, VT, Custom);
1593 setOperationAction(ISD::USUBO, VT, Custom);
1594 setOperationAction(ISD::SMULO, VT, Custom);
1595 setOperationAction(ISD::UMULO, VT, Custom);
1599 if (!Subtarget->is64Bit()) {
1600 // These libcalls are not available in 32-bit.
1601 setLibcallName(RTLIB::SHL_I128, nullptr);
1602 setLibcallName(RTLIB::SRL_I128, nullptr);
1603 setLibcallName(RTLIB::SRA_I128, nullptr);
1606 // Combine sin / cos into one node or libcall if possible.
1607 if (Subtarget->hasSinCos()) {
1608 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1609 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1610 if (Subtarget->isTargetDarwin()) {
1611 // For MacOSX, we don't want to the normal expansion of a libcall to
1612 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1614 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1615 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1619 if (Subtarget->isTargetWin64()) {
1620 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1621 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1622 setOperationAction(ISD::SREM, MVT::i128, Custom);
1623 setOperationAction(ISD::UREM, MVT::i128, Custom);
1624 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1628 // We have target-specific dag combine patterns for the following nodes:
1629 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1630 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1631 setTargetDAGCombine(ISD::VSELECT);
1632 setTargetDAGCombine(ISD::SELECT);
1633 setTargetDAGCombine(ISD::SHL);
1634 setTargetDAGCombine(ISD::SRA);
1635 setTargetDAGCombine(ISD::SRL);
1636 setTargetDAGCombine(ISD::OR);
1637 setTargetDAGCombine(ISD::AND);
1638 setTargetDAGCombine(ISD::ADD);
1639 setTargetDAGCombine(ISD::FADD);
1640 setTargetDAGCombine(ISD::FSUB);
1641 setTargetDAGCombine(ISD::FMA);
1642 setTargetDAGCombine(ISD::SUB);
1643 setTargetDAGCombine(ISD::LOAD);
1644 setTargetDAGCombine(ISD::STORE);
1645 setTargetDAGCombine(ISD::ZERO_EXTEND);
1646 setTargetDAGCombine(ISD::ANY_EXTEND);
1647 setTargetDAGCombine(ISD::SIGN_EXTEND);
1648 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1649 setTargetDAGCombine(ISD::TRUNCATE);
1650 setTargetDAGCombine(ISD::SINT_TO_FP);
1651 setTargetDAGCombine(ISD::SETCC);
1652 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1653 setTargetDAGCombine(ISD::BUILD_VECTOR);
1654 if (Subtarget->is64Bit())
1655 setTargetDAGCombine(ISD::MUL);
1656 setTargetDAGCombine(ISD::XOR);
1658 computeRegisterProperties();
1660 // On Darwin, -Os means optimize for size without hurting performance,
1661 // do not reduce the limit.
1662 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1663 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1664 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1665 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1666 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1667 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 setPrefLoopAlignment(4); // 2^4 bytes.
1670 // Predictable cmov don't hurt on atom because it's in-order.
1671 PredictableSelectIsExpensive = !Subtarget->isAtom();
1673 setPrefFunctionAlignment(4); // 2^4 bytes.
1675 verifyIntrinsicTables();
1678 // This has so far only been implemented for 64-bit MachO.
1679 bool X86TargetLowering::useLoadStackGuardNode() const {
1680 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1681 Subtarget->is64Bit();
1684 TargetLoweringBase::LegalizeTypeAction
1685 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1686 if (ExperimentalVectorWideningLegalization &&
1687 VT.getVectorNumElements() != 1 &&
1688 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1689 return TypeWidenVector;
1691 return TargetLoweringBase::getPreferredVectorAction(VT);
1694 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1696 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1698 const unsigned NumElts = VT.getVectorNumElements();
1699 const EVT EltVT = VT.getVectorElementType();
1700 if (VT.is512BitVector()) {
1701 if (Subtarget->hasAVX512())
1702 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1703 EltVT == MVT::f32 || EltVT == MVT::f64)
1705 case 8: return MVT::v8i1;
1706 case 16: return MVT::v16i1;
1708 if (Subtarget->hasBWI())
1709 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1711 case 32: return MVT::v32i1;
1712 case 64: return MVT::v64i1;
1716 if (VT.is256BitVector() || VT.is128BitVector()) {
1717 if (Subtarget->hasVLX())
1718 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1719 EltVT == MVT::f32 || EltVT == MVT::f64)
1721 case 2: return MVT::v2i1;
1722 case 4: return MVT::v4i1;
1723 case 8: return MVT::v8i1;
1725 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1726 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1728 case 8: return MVT::v8i1;
1729 case 16: return MVT::v16i1;
1730 case 32: return MVT::v32i1;
1734 return VT.changeVectorElementTypeToInteger();
1737 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1738 /// the desired ByVal argument alignment.
1739 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1742 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1743 if (VTy->getBitWidth() == 128)
1745 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1746 unsigned EltAlign = 0;
1747 getMaxByValAlign(ATy->getElementType(), EltAlign);
1748 if (EltAlign > MaxAlign)
1749 MaxAlign = EltAlign;
1750 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1751 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1752 unsigned EltAlign = 0;
1753 getMaxByValAlign(STy->getElementType(i), EltAlign);
1754 if (EltAlign > MaxAlign)
1755 MaxAlign = EltAlign;
1762 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1763 /// function arguments in the caller parameter area. For X86, aggregates
1764 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1765 /// are at 4-byte boundaries.
1766 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1767 if (Subtarget->is64Bit()) {
1768 // Max of 8 and alignment of type.
1769 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1776 if (Subtarget->hasSSE1())
1777 getMaxByValAlign(Ty, Align);
1781 /// getOptimalMemOpType - Returns the target specific optimal type for load
1782 /// and store operations as a result of memset, memcpy, and memmove
1783 /// lowering. If DstAlign is zero that means it's safe to destination
1784 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1785 /// means there isn't a need to check it against alignment requirement,
1786 /// probably because the source does not need to be loaded. If 'IsMemset' is
1787 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1788 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1789 /// source is constant so it does not need to be loaded.
1790 /// It returns EVT::Other if the type should be determined using generic
1791 /// target-independent logic.
1793 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1794 unsigned DstAlign, unsigned SrcAlign,
1795 bool IsMemset, bool ZeroMemset,
1797 MachineFunction &MF) const {
1798 const Function *F = MF.getFunction();
1799 if ((!IsMemset || ZeroMemset) &&
1800 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1801 Attribute::NoImplicitFloat)) {
1803 (Subtarget->isUnalignedMemAccessFast() ||
1804 ((DstAlign == 0 || DstAlign >= 16) &&
1805 (SrcAlign == 0 || SrcAlign >= 16)))) {
1807 if (Subtarget->hasInt256())
1809 if (Subtarget->hasFp256())
1812 if (Subtarget->hasSSE2())
1814 if (Subtarget->hasSSE1())
1816 } else if (!MemcpyStrSrc && Size >= 8 &&
1817 !Subtarget->is64Bit() &&
1818 Subtarget->hasSSE2()) {
1819 // Do not use f64 to lower memcpy if source is string constant. It's
1820 // better to use i32 to avoid the loads.
1824 if (Subtarget->is64Bit() && Size >= 8)
1829 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1831 return X86ScalarSSEf32;
1832 else if (VT == MVT::f64)
1833 return X86ScalarSSEf64;
1838 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1843 *Fast = Subtarget->isUnalignedMemAccessFast();
1847 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1848 /// current function. The returned value is a member of the
1849 /// MachineJumpTableInfo::JTEntryKind enum.
1850 unsigned X86TargetLowering::getJumpTableEncoding() const {
1851 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1853 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1854 Subtarget->isPICStyleGOT())
1855 return MachineJumpTableInfo::EK_Custom32;
1857 // Otherwise, use the normal jump table encoding heuristics.
1858 return TargetLowering::getJumpTableEncoding();
1862 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1863 const MachineBasicBlock *MBB,
1864 unsigned uid,MCContext &Ctx) const{
1865 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1866 Subtarget->isPICStyleGOT());
1867 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1869 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1870 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1873 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1875 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1876 SelectionDAG &DAG) const {
1877 if (!Subtarget->is64Bit())
1878 // This doesn't have SDLoc associated with it, but is not really the
1879 // same as a Register.
1880 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1884 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1885 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1887 const MCExpr *X86TargetLowering::
1888 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1889 MCContext &Ctx) const {
1890 // X86-64 uses RIP relative addressing based on the jump table label.
1891 if (Subtarget->isPICStyleRIPRel())
1892 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1894 // Otherwise, the reference is relative to the PIC base.
1895 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1898 // FIXME: Why this routine is here? Move to RegInfo!
1899 std::pair<const TargetRegisterClass*, uint8_t>
1900 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1901 const TargetRegisterClass *RRC = nullptr;
1903 switch (VT.SimpleTy) {
1905 return TargetLowering::findRepresentativeClass(VT);
1906 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1907 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1910 RRC = &X86::VR64RegClass;
1912 case MVT::f32: case MVT::f64:
1913 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1914 case MVT::v4f32: case MVT::v2f64:
1915 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1917 RRC = &X86::VR128RegClass;
1920 return std::make_pair(RRC, Cost);
1923 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1924 unsigned &Offset) const {
1925 if (!Subtarget->isTargetLinux())
1928 if (Subtarget->is64Bit()) {
1929 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1931 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1943 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1944 unsigned DestAS) const {
1945 assert(SrcAS != DestAS && "Expected different address spaces!");
1947 return SrcAS < 256 && DestAS < 256;
1950 //===----------------------------------------------------------------------===//
1951 // Return Value Calling Convention Implementation
1952 //===----------------------------------------------------------------------===//
1954 #include "X86GenCallingConv.inc"
1957 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1958 MachineFunction &MF, bool isVarArg,
1959 const SmallVectorImpl<ISD::OutputArg> &Outs,
1960 LLVMContext &Context) const {
1961 SmallVector<CCValAssign, 16> RVLocs;
1962 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1963 return CCInfo.CheckReturn(Outs, RetCC_X86);
1966 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1967 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1972 X86TargetLowering::LowerReturn(SDValue Chain,
1973 CallingConv::ID CallConv, bool isVarArg,
1974 const SmallVectorImpl<ISD::OutputArg> &Outs,
1975 const SmallVectorImpl<SDValue> &OutVals,
1976 SDLoc dl, SelectionDAG &DAG) const {
1977 MachineFunction &MF = DAG.getMachineFunction();
1978 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1980 SmallVector<CCValAssign, 16> RVLocs;
1981 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1982 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1985 SmallVector<SDValue, 6> RetOps;
1986 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1987 // Operand #1 = Bytes To Pop
1988 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1991 // Copy the result values into the output registers.
1992 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1993 CCValAssign &VA = RVLocs[i];
1994 assert(VA.isRegLoc() && "Can only return in registers!");
1995 SDValue ValToCopy = OutVals[i];
1996 EVT ValVT = ValToCopy.getValueType();
1998 // Promote values to the appropriate types
1999 if (VA.getLocInfo() == CCValAssign::SExt)
2000 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2001 else if (VA.getLocInfo() == CCValAssign::ZExt)
2002 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::AExt)
2004 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::BCvt)
2006 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2008 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2009 "Unexpected FP-extend for return value.");
2011 // If this is x86-64, and we disabled SSE, we can't return FP values,
2012 // or SSE or MMX vectors.
2013 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2014 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2015 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2016 report_fatal_error("SSE register return with SSE disabled");
2018 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2019 // llvm-gcc has never done it right and no one has noticed, so this
2020 // should be OK for now.
2021 if (ValVT == MVT::f64 &&
2022 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2023 report_fatal_error("SSE2 register return with SSE2 disabled");
2025 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2026 // the RET instruction and handled by the FP Stackifier.
2027 if (VA.getLocReg() == X86::FP0 ||
2028 VA.getLocReg() == X86::FP1) {
2029 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2030 // change the value to the FP stack register class.
2031 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2032 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2033 RetOps.push_back(ValToCopy);
2034 // Don't emit a copytoreg.
2038 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2039 // which is returned in RAX / RDX.
2040 if (Subtarget->is64Bit()) {
2041 if (ValVT == MVT::x86mmx) {
2042 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2043 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2044 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2046 // If we don't have SSE2 available, convert to v4f32 so the generated
2047 // register is legal.
2048 if (!Subtarget->hasSSE2())
2049 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2054 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2055 Flag = Chain.getValue(1);
2056 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2059 // The x86-64 ABIs require that for returning structs by value we copy
2060 // the sret argument into %rax/%eax (depending on ABI) for the return.
2061 // Win32 requires us to put the sret argument to %eax as well.
2062 // We saved the argument into a virtual register in the entry block,
2063 // so now we copy the value out and into %rax/%eax.
2064 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2065 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2066 MachineFunction &MF = DAG.getMachineFunction();
2067 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2068 unsigned Reg = FuncInfo->getSRetReturnReg();
2070 "SRetReturnReg should have been set in LowerFormalArguments().");
2071 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2074 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2075 X86::RAX : X86::EAX;
2076 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2077 Flag = Chain.getValue(1);
2079 // RAX/EAX now acts like a return value.
2080 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2083 RetOps[0] = Chain; // Update chain.
2085 // Add the flag if we have it.
2087 RetOps.push_back(Flag);
2089 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2092 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2093 if (N->getNumValues() != 1)
2095 if (!N->hasNUsesOfValue(1, 0))
2098 SDValue TCChain = Chain;
2099 SDNode *Copy = *N->use_begin();
2100 if (Copy->getOpcode() == ISD::CopyToReg) {
2101 // If the copy has a glue operand, we conservatively assume it isn't safe to
2102 // perform a tail call.
2103 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2105 TCChain = Copy->getOperand(0);
2106 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2109 bool HasRet = false;
2110 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2112 if (UI->getOpcode() != X86ISD::RET_FLAG)
2114 // If we are returning more than one value, we can definitely
2115 // not make a tail call see PR19530
2116 if (UI->getNumOperands() > 4)
2118 if (UI->getNumOperands() == 4 &&
2119 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2132 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2133 ISD::NodeType ExtendKind) const {
2135 // TODO: Is this also valid on 32-bit?
2136 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2137 ReturnMVT = MVT::i8;
2139 ReturnMVT = MVT::i32;
2141 EVT MinVT = getRegisterType(Context, ReturnMVT);
2142 return VT.bitsLT(MinVT) ? MinVT : VT;
2145 /// LowerCallResult - Lower the result values of a call into the
2146 /// appropriate copies out of appropriate physical registers.
2149 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2150 CallingConv::ID CallConv, bool isVarArg,
2151 const SmallVectorImpl<ISD::InputArg> &Ins,
2152 SDLoc dl, SelectionDAG &DAG,
2153 SmallVectorImpl<SDValue> &InVals) const {
2155 // Assign locations to each value returned by this call.
2156 SmallVector<CCValAssign, 16> RVLocs;
2157 bool Is64Bit = Subtarget->is64Bit();
2158 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2160 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2162 // Copy all of the result registers out of their specified physreg.
2163 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2164 CCValAssign &VA = RVLocs[i];
2165 EVT CopyVT = VA.getValVT();
2167 // If this is x86-64, and we disabled SSE, we can't return FP values
2168 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2169 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2170 report_fatal_error("SSE register return with SSE disabled");
2173 // If we prefer to use the value in xmm registers, copy it out as f80 and
2174 // use a truncate to move it from fp stack reg to xmm reg.
2175 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2176 isScalarFPTypeInSSEReg(VA.getValVT()))
2179 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2180 CopyVT, InFlag).getValue(1);
2181 SDValue Val = Chain.getValue(0);
2183 if (CopyVT != VA.getValVT())
2184 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2185 // This truncation won't change the value.
2186 DAG.getIntPtrConstant(1));
2188 InFlag = Chain.getValue(2);
2189 InVals.push_back(Val);
2195 //===----------------------------------------------------------------------===//
2196 // C & StdCall & Fast Calling Convention implementation
2197 //===----------------------------------------------------------------------===//
2198 // StdCall calling convention seems to be standard for many Windows' API
2199 // routines and around. It differs from C calling convention just a little:
2200 // callee should clean up the stack, not caller. Symbols should be also
2201 // decorated in some fancy way :) It doesn't support any vector arguments.
2202 // For info on fast calling convention see Fast Calling Convention (tail call)
2203 // implementation LowerX86_32FastCCCallTo.
2205 /// CallIsStructReturn - Determines whether a call uses struct return
2207 enum StructReturnType {
2212 static StructReturnType
2213 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2215 return NotStructReturn;
2217 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2218 if (!Flags.isSRet())
2219 return NotStructReturn;
2220 if (Flags.isInReg())
2221 return RegStructReturn;
2222 return StackStructReturn;
2225 /// ArgsAreStructReturn - Determines whether a function uses struct
2226 /// return semantics.
2227 static StructReturnType
2228 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2230 return NotStructReturn;
2232 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2233 if (!Flags.isSRet())
2234 return NotStructReturn;
2235 if (Flags.isInReg())
2236 return RegStructReturn;
2237 return StackStructReturn;
2240 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2241 /// by "Src" to address "Dst" with size and alignment information specified by
2242 /// the specific parameter attribute. The copy will be passed as a byval
2243 /// function parameter.
2245 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2246 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2248 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2250 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2251 /*isVolatile*/false, /*AlwaysInline=*/true,
2252 MachinePointerInfo(), MachinePointerInfo());
2255 /// IsTailCallConvention - Return true if the calling convention is one that
2256 /// supports tail call optimization.
2257 static bool IsTailCallConvention(CallingConv::ID CC) {
2258 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2259 CC == CallingConv::HiPE);
2262 /// \brief Return true if the calling convention is a C calling convention.
2263 static bool IsCCallConvention(CallingConv::ID CC) {
2264 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2265 CC == CallingConv::X86_64_SysV);
2268 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2269 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2273 CallingConv::ID CalleeCC = CS.getCallingConv();
2274 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2280 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2281 /// a tailcall target by changing its ABI.
2282 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2283 bool GuaranteedTailCallOpt) {
2284 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2288 X86TargetLowering::LowerMemArgument(SDValue Chain,
2289 CallingConv::ID CallConv,
2290 const SmallVectorImpl<ISD::InputArg> &Ins,
2291 SDLoc dl, SelectionDAG &DAG,
2292 const CCValAssign &VA,
2293 MachineFrameInfo *MFI,
2295 // Create the nodes corresponding to a load from this parameter slot.
2296 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2297 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2298 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2299 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2302 // If value is passed by pointer we have address passed instead of the value
2304 if (VA.getLocInfo() == CCValAssign::Indirect)
2305 ValVT = VA.getLocVT();
2307 ValVT = VA.getValVT();
2309 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2310 // changed with more analysis.
2311 // In case of tail call optimization mark all arguments mutable. Since they
2312 // could be overwritten by lowering of arguments in case of a tail call.
2313 if (Flags.isByVal()) {
2314 unsigned Bytes = Flags.getByValSize();
2315 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2316 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2317 return DAG.getFrameIndex(FI, getPointerTy());
2319 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2320 VA.getLocMemOffset(), isImmutable);
2321 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2322 return DAG.getLoad(ValVT, dl, Chain, FIN,
2323 MachinePointerInfo::getFixedStack(FI),
2324 false, false, false, 0);
2328 // FIXME: Get this from tablegen.
2329 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2330 const X86Subtarget *Subtarget) {
2331 assert(Subtarget->is64Bit());
2333 if (Subtarget->isCallingConvWin64(CallConv)) {
2334 static const MCPhysReg GPR64ArgRegsWin64[] = {
2335 X86::RCX, X86::RDX, X86::R8, X86::R9
2337 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2340 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2341 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2343 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2346 // FIXME: Get this from tablegen.
2347 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2348 CallingConv::ID CallConv,
2349 const X86Subtarget *Subtarget) {
2350 assert(Subtarget->is64Bit());
2351 if (Subtarget->isCallingConvWin64(CallConv)) {
2352 // The XMM registers which might contain var arg parameters are shadowed
2353 // in their paired GPR. So we only need to save the GPR to their home
2355 // TODO: __vectorcall will change this.
2359 const Function *Fn = MF.getFunction();
2360 bool NoImplicitFloatOps = Fn->getAttributes().
2361 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2362 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2363 "SSE register cannot be used when SSE is disabled!");
2364 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2365 !Subtarget->hasSSE1())
2366 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2370 static const MCPhysReg XMMArgRegs64Bit[] = {
2371 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2372 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2374 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2378 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2379 CallingConv::ID CallConv,
2381 const SmallVectorImpl<ISD::InputArg> &Ins,
2384 SmallVectorImpl<SDValue> &InVals)
2386 MachineFunction &MF = DAG.getMachineFunction();
2387 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2389 const Function* Fn = MF.getFunction();
2390 if (Fn->hasExternalLinkage() &&
2391 Subtarget->isTargetCygMing() &&
2392 Fn->getName() == "main")
2393 FuncInfo->setForceFramePointer(true);
2395 MachineFrameInfo *MFI = MF.getFrameInfo();
2396 bool Is64Bit = Subtarget->is64Bit();
2397 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2399 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2400 "Var args not supported with calling convention fastcc, ghc or hipe");
2402 // Assign locations to all of the incoming arguments.
2403 SmallVector<CCValAssign, 16> ArgLocs;
2404 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2406 // Allocate shadow area for Win64
2408 CCInfo.AllocateStack(32, 8);
2410 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2412 unsigned LastVal = ~0U;
2414 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2415 CCValAssign &VA = ArgLocs[i];
2416 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2418 assert(VA.getValNo() != LastVal &&
2419 "Don't support value assigned to multiple locs yet");
2421 LastVal = VA.getValNo();
2423 if (VA.isRegLoc()) {
2424 EVT RegVT = VA.getLocVT();
2425 const TargetRegisterClass *RC;
2426 if (RegVT == MVT::i32)
2427 RC = &X86::GR32RegClass;
2428 else if (Is64Bit && RegVT == MVT::i64)
2429 RC = &X86::GR64RegClass;
2430 else if (RegVT == MVT::f32)
2431 RC = &X86::FR32RegClass;
2432 else if (RegVT == MVT::f64)
2433 RC = &X86::FR64RegClass;
2434 else if (RegVT.is512BitVector())
2435 RC = &X86::VR512RegClass;
2436 else if (RegVT.is256BitVector())
2437 RC = &X86::VR256RegClass;
2438 else if (RegVT.is128BitVector())
2439 RC = &X86::VR128RegClass;
2440 else if (RegVT == MVT::x86mmx)
2441 RC = &X86::VR64RegClass;
2442 else if (RegVT == MVT::i1)
2443 RC = &X86::VK1RegClass;
2444 else if (RegVT == MVT::v8i1)
2445 RC = &X86::VK8RegClass;
2446 else if (RegVT == MVT::v16i1)
2447 RC = &X86::VK16RegClass;
2448 else if (RegVT == MVT::v32i1)
2449 RC = &X86::VK32RegClass;
2450 else if (RegVT == MVT::v64i1)
2451 RC = &X86::VK64RegClass;
2453 llvm_unreachable("Unknown argument type!");
2455 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2456 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2458 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2459 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2461 if (VA.getLocInfo() == CCValAssign::SExt)
2462 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2463 DAG.getValueType(VA.getValVT()));
2464 else if (VA.getLocInfo() == CCValAssign::ZExt)
2465 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2466 DAG.getValueType(VA.getValVT()));
2467 else if (VA.getLocInfo() == CCValAssign::BCvt)
2468 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2470 if (VA.isExtInLoc()) {
2471 // Handle MMX values passed in XMM regs.
2472 if (RegVT.isVector())
2473 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2475 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2478 assert(VA.isMemLoc());
2479 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2482 // If value is passed via pointer - do a load.
2483 if (VA.getLocInfo() == CCValAssign::Indirect)
2484 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2485 MachinePointerInfo(), false, false, false, 0);
2487 InVals.push_back(ArgValue);
2490 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2491 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2492 // The x86-64 ABIs require that for returning structs by value we copy
2493 // the sret argument into %rax/%eax (depending on ABI) for the return.
2494 // Win32 requires us to put the sret argument to %eax as well.
2495 // Save the argument into a virtual register so that we can access it
2496 // from the return points.
2497 if (Ins[i].Flags.isSRet()) {
2498 unsigned Reg = FuncInfo->getSRetReturnReg();
2500 MVT PtrTy = getPointerTy();
2501 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2502 FuncInfo->setSRetReturnReg(Reg);
2504 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2505 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2511 unsigned StackSize = CCInfo.getNextStackOffset();
2512 // Align stack specially for tail calls.
2513 if (FuncIsMadeTailCallSafe(CallConv,
2514 MF.getTarget().Options.GuaranteedTailCallOpt))
2515 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2517 // If the function takes variable number of arguments, make a frame index for
2518 // the start of the first vararg value... for expansion of llvm.va_start. We
2519 // can skip this if there are no va_start calls.
2520 if (MFI->hasVAStart() &&
2521 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2522 CallConv != CallingConv::X86_ThisCall))) {
2523 FuncInfo->setVarArgsFrameIndex(
2524 MFI->CreateFixedObject(1, StackSize, true));
2527 // 64-bit calling conventions support varargs and register parameters, so we
2528 // have to do extra work to spill them in the prologue or forward them to
2530 if (Is64Bit && isVarArg &&
2531 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2532 // Find the first unallocated argument registers.
2533 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2534 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2535 unsigned NumIntRegs =
2536 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2537 unsigned NumXMMRegs =
2538 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2539 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2540 "SSE register cannot be used when SSE is disabled!");
2542 // Gather all the live in physical registers.
2543 SmallVector<SDValue, 6> LiveGPRs;
2544 SmallVector<SDValue, 8> LiveXMMRegs;
2546 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2547 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2549 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2551 if (!ArgXMMs.empty()) {
2552 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2553 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2554 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2555 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2556 LiveXMMRegs.push_back(
2557 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2561 // Store them to the va_list returned by va_start.
2562 if (MFI->hasVAStart()) {
2564 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2565 // Get to the caller-allocated home save location. Add 8 to account
2566 // for the return address.
2567 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2568 FuncInfo->setRegSaveFrameIndex(
2569 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2570 // Fixup to set vararg frame on shadow area (4 x i64).
2572 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2574 // For X86-64, if there are vararg parameters that are passed via
2575 // registers, then we must store them to their spots on the stack so
2576 // they may be loaded by deferencing the result of va_next.
2577 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2578 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2579 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2580 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2583 // Store the integer parameter registers.
2584 SmallVector<SDValue, 8> MemOps;
2585 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2587 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2588 for (SDValue Val : LiveGPRs) {
2589 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2590 DAG.getIntPtrConstant(Offset));
2592 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2593 MachinePointerInfo::getFixedStack(
2594 FuncInfo->getRegSaveFrameIndex(), Offset),
2596 MemOps.push_back(Store);
2600 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2601 // Now store the XMM (fp + vector) parameter registers.
2602 SmallVector<SDValue, 12> SaveXMMOps;
2603 SaveXMMOps.push_back(Chain);
2604 SaveXMMOps.push_back(ALVal);
2605 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2606 FuncInfo->getRegSaveFrameIndex()));
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getVarArgsFPOffset()));
2609 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2611 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2612 MVT::Other, SaveXMMOps));
2615 if (!MemOps.empty())
2616 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2618 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2619 // to the liveout set on a musttail call.
2620 assert(MFI->hasMustTailInVarArgFunc());
2621 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2622 typedef X86MachineFunctionInfo::Forward Forward;
2624 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2626 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2627 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2628 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2631 if (!ArgXMMs.empty()) {
2633 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2634 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2635 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2637 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2639 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2640 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2642 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2648 // Some CCs need callee pop.
2649 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2650 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2651 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2653 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2654 // If this is an sret function, the return should pop the hidden pointer.
2655 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2656 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2657 argsAreStructReturn(Ins) == StackStructReturn)
2658 FuncInfo->setBytesToPopOnReturn(4);
2662 // RegSaveFrameIndex is X86-64 only.
2663 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2664 if (CallConv == CallingConv::X86_FastCall ||
2665 CallConv == CallingConv::X86_ThisCall)
2666 // fastcc functions can't have varargs.
2667 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2670 FuncInfo->setArgumentStackSize(StackSize);
2676 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2677 SDValue StackPtr, SDValue Arg,
2678 SDLoc dl, SelectionDAG &DAG,
2679 const CCValAssign &VA,
2680 ISD::ArgFlagsTy Flags) const {
2681 unsigned LocMemOffset = VA.getLocMemOffset();
2682 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2683 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2684 if (Flags.isByVal())
2685 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2687 return DAG.getStore(Chain, dl, Arg, PtrOff,
2688 MachinePointerInfo::getStack(LocMemOffset),
2692 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2693 /// optimization is performed and it is required.
2695 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2696 SDValue &OutRetAddr, SDValue Chain,
2697 bool IsTailCall, bool Is64Bit,
2698 int FPDiff, SDLoc dl) const {
2699 // Adjust the Return address stack slot.
2700 EVT VT = getPointerTy();
2701 OutRetAddr = getReturnAddressFrameIndex(DAG);
2703 // Load the "old" Return address.
2704 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2705 false, false, false, 0);
2706 return SDValue(OutRetAddr.getNode(), 1);
2709 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2710 /// optimization is performed and it is required (FPDiff!=0).
2711 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2712 SDValue Chain, SDValue RetAddrFrIdx,
2713 EVT PtrVT, unsigned SlotSize,
2714 int FPDiff, SDLoc dl) {
2715 // Store the return address to the appropriate stack slot.
2716 if (!FPDiff) return Chain;
2717 // Calculate the new stack slot for the return address.
2718 int NewReturnAddrFI =
2719 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2721 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2722 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2723 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2729 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2730 SmallVectorImpl<SDValue> &InVals) const {
2731 SelectionDAG &DAG = CLI.DAG;
2733 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2734 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2735 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2736 SDValue Chain = CLI.Chain;
2737 SDValue Callee = CLI.Callee;
2738 CallingConv::ID CallConv = CLI.CallConv;
2739 bool &isTailCall = CLI.IsTailCall;
2740 bool isVarArg = CLI.IsVarArg;
2742 MachineFunction &MF = DAG.getMachineFunction();
2743 bool Is64Bit = Subtarget->is64Bit();
2744 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2745 StructReturnType SR = callIsStructReturn(Outs);
2746 bool IsSibcall = false;
2747 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2749 if (MF.getTarget().Options.DisableTailCalls)
2752 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2754 // Force this to be a tail call. The verifier rules are enough to ensure
2755 // that we can lower this successfully without moving the return address
2758 } else if (isTailCall) {
2759 // Check if it's really possible to do a tail call.
2760 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2761 isVarArg, SR != NotStructReturn,
2762 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2763 Outs, OutVals, Ins, DAG);
2765 // Sibcalls are automatically detected tailcalls which do not require
2767 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2774 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2775 "Var args not supported with calling convention fastcc, ghc or hipe");
2777 // Analyze operands of the call, assigning locations to each operand.
2778 SmallVector<CCValAssign, 16> ArgLocs;
2779 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2781 // Allocate shadow area for Win64
2783 CCInfo.AllocateStack(32, 8);
2785 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2787 // Get a count of how many bytes are to be pushed on the stack.
2788 unsigned NumBytes = CCInfo.getNextStackOffset();
2790 // This is a sibcall. The memory operands are available in caller's
2791 // own caller's stack.
2793 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2794 IsTailCallConvention(CallConv))
2795 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2798 if (isTailCall && !IsSibcall && !IsMustTail) {
2799 // Lower arguments at fp - stackoffset + fpdiff.
2800 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2802 FPDiff = NumBytesCallerPushed - NumBytes;
2804 // Set the delta of movement of the returnaddr stackslot.
2805 // But only set if delta is greater than previous delta.
2806 if (FPDiff < X86Info->getTCReturnAddrDelta())
2807 X86Info->setTCReturnAddrDelta(FPDiff);
2810 unsigned NumBytesToPush = NumBytes;
2811 unsigned NumBytesToPop = NumBytes;
2813 // If we have an inalloca argument, all stack space has already been allocated
2814 // for us and be right at the top of the stack. We don't support multiple
2815 // arguments passed in memory when using inalloca.
2816 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2818 if (!ArgLocs.back().isMemLoc())
2819 report_fatal_error("cannot use inalloca attribute on a register "
2821 if (ArgLocs.back().getLocMemOffset() != 0)
2822 report_fatal_error("any parameter with the inalloca attribute must be "
2823 "the only memory argument");
2827 Chain = DAG.getCALLSEQ_START(
2828 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2830 SDValue RetAddrFrIdx;
2831 // Load return address for tail calls.
2832 if (isTailCall && FPDiff)
2833 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2834 Is64Bit, FPDiff, dl);
2836 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2837 SmallVector<SDValue, 8> MemOpChains;
2840 // Walk the register/memloc assignments, inserting copies/loads. In the case
2841 // of tail call optimization arguments are handle later.
2842 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2843 DAG.getSubtarget().getRegisterInfo());
2844 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2845 // Skip inalloca arguments, they have already been written.
2846 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2847 if (Flags.isInAlloca())
2850 CCValAssign &VA = ArgLocs[i];
2851 EVT RegVT = VA.getLocVT();
2852 SDValue Arg = OutVals[i];
2853 bool isByVal = Flags.isByVal();
2855 // Promote the value if needed.
2856 switch (VA.getLocInfo()) {
2857 default: llvm_unreachable("Unknown loc info!");
2858 case CCValAssign::Full: break;
2859 case CCValAssign::SExt:
2860 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2862 case CCValAssign::ZExt:
2863 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2865 case CCValAssign::AExt:
2866 if (RegVT.is128BitVector()) {
2867 // Special case: passing MMX values in XMM registers.
2868 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2869 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2870 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2872 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2874 case CCValAssign::BCvt:
2875 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2877 case CCValAssign::Indirect: {
2878 // Store the argument.
2879 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2880 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2881 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2882 MachinePointerInfo::getFixedStack(FI),
2889 if (VA.isRegLoc()) {
2890 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2891 if (isVarArg && IsWin64) {
2892 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2893 // shadow reg if callee is a varargs function.
2894 unsigned ShadowReg = 0;
2895 switch (VA.getLocReg()) {
2896 case X86::XMM0: ShadowReg = X86::RCX; break;
2897 case X86::XMM1: ShadowReg = X86::RDX; break;
2898 case X86::XMM2: ShadowReg = X86::R8; break;
2899 case X86::XMM3: ShadowReg = X86::R9; break;
2902 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2904 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2905 assert(VA.isMemLoc());
2906 if (!StackPtr.getNode())
2907 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2909 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2910 dl, DAG, VA, Flags));
2914 if (!MemOpChains.empty())
2915 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2917 if (Subtarget->isPICStyleGOT()) {
2918 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2921 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2922 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2924 // If we are tail calling and generating PIC/GOT style code load the
2925 // address of the callee into ECX. The value in ecx is used as target of
2926 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2927 // for tail calls on PIC/GOT architectures. Normally we would just put the
2928 // address of GOT into ebx and then call target@PLT. But for tail calls
2929 // ebx would be restored (since ebx is callee saved) before jumping to the
2932 // Note: The actual moving to ECX is done further down.
2933 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2934 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2935 !G->getGlobal()->hasProtectedVisibility())
2936 Callee = LowerGlobalAddress(Callee, DAG);
2937 else if (isa<ExternalSymbolSDNode>(Callee))
2938 Callee = LowerExternalSymbol(Callee, DAG);
2942 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2943 // From AMD64 ABI document:
2944 // For calls that may call functions that use varargs or stdargs
2945 // (prototype-less calls or calls to functions containing ellipsis (...) in
2946 // the declaration) %al is used as hidden argument to specify the number
2947 // of SSE registers used. The contents of %al do not need to match exactly
2948 // the number of registers, but must be an ubound on the number of SSE
2949 // registers used and is in the range 0 - 8 inclusive.
2951 // Count the number of XMM registers allocated.
2952 static const MCPhysReg XMMArgRegs[] = {
2953 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2954 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2956 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2957 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2958 && "SSE registers cannot be used when SSE is disabled");
2960 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2961 DAG.getConstant(NumXMMRegs, MVT::i8)));
2964 if (Is64Bit && isVarArg && IsMustTail) {
2965 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2966 for (const auto &F : Forwards) {
2967 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2968 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2972 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2973 // don't need this because the eligibility check rejects calls that require
2974 // shuffling arguments passed in memory.
2975 if (!IsSibcall && isTailCall) {
2976 // Force all the incoming stack arguments to be loaded from the stack
2977 // before any new outgoing arguments are stored to the stack, because the
2978 // outgoing stack slots may alias the incoming argument stack slots, and
2979 // the alias isn't otherwise explicit. This is slightly more conservative
2980 // than necessary, because it means that each store effectively depends
2981 // on every argument instead of just those arguments it would clobber.
2982 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2984 SmallVector<SDValue, 8> MemOpChains2;
2987 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2988 CCValAssign &VA = ArgLocs[i];
2991 assert(VA.isMemLoc());
2992 SDValue Arg = OutVals[i];
2993 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2994 // Skip inalloca arguments. They don't require any work.
2995 if (Flags.isInAlloca())
2997 // Create frame index.
2998 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2999 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3000 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3001 FIN = DAG.getFrameIndex(FI, getPointerTy());
3003 if (Flags.isByVal()) {
3004 // Copy relative to framepointer.
3005 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3006 if (!StackPtr.getNode())
3007 StackPtr = DAG.getCopyFromReg(Chain, dl,
3008 RegInfo->getStackRegister(),
3010 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3012 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3016 // Store relative to framepointer.
3017 MemOpChains2.push_back(
3018 DAG.getStore(ArgChain, dl, Arg, FIN,
3019 MachinePointerInfo::getFixedStack(FI),
3024 if (!MemOpChains2.empty())
3025 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3027 // Store the return address to the appropriate stack slot.
3028 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3029 getPointerTy(), RegInfo->getSlotSize(),
3033 // Build a sequence of copy-to-reg nodes chained together with token chain
3034 // and flag operands which copy the outgoing args into registers.
3036 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3037 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3038 RegsToPass[i].second, InFlag);
3039 InFlag = Chain.getValue(1);
3042 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3043 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3044 // In the 64-bit large code model, we have to make all calls
3045 // through a register, since the call instruction's 32-bit
3046 // pc-relative offset may not be large enough to hold the whole
3048 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3049 // If the callee is a GlobalAddress node (quite common, every direct call
3050 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3053 // We should use extra load for direct calls to dllimported functions in
3055 const GlobalValue *GV = G->getGlobal();
3056 if (!GV->hasDLLImportStorageClass()) {
3057 unsigned char OpFlags = 0;
3058 bool ExtraLoad = false;
3059 unsigned WrapperKind = ISD::DELETED_NODE;
3061 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3062 // external symbols most go through the PLT in PIC mode. If the symbol
3063 // has hidden or protected visibility, or if it is static or local, then
3064 // we don't need to use the PLT - we can directly call it.
3065 if (Subtarget->isTargetELF() &&
3066 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3067 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3068 OpFlags = X86II::MO_PLT;
3069 } else if (Subtarget->isPICStyleStubAny() &&
3070 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3071 (!Subtarget->getTargetTriple().isMacOSX() ||
3072 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3073 // PC-relative references to external symbols should go through $stub,
3074 // unless we're building with the leopard linker or later, which
3075 // automatically synthesizes these stubs.
3076 OpFlags = X86II::MO_DARWIN_STUB;
3077 } else if (Subtarget->isPICStyleRIPRel() &&
3078 isa<Function>(GV) &&
3079 cast<Function>(GV)->getAttributes().
3080 hasAttribute(AttributeSet::FunctionIndex,
3081 Attribute::NonLazyBind)) {
3082 // If the function is marked as non-lazy, generate an indirect call
3083 // which loads from the GOT directly. This avoids runtime overhead
3084 // at the cost of eager binding (and one extra byte of encoding).
3085 OpFlags = X86II::MO_GOTPCREL;
3086 WrapperKind = X86ISD::WrapperRIP;
3090 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3091 G->getOffset(), OpFlags);
3093 // Add a wrapper if needed.
3094 if (WrapperKind != ISD::DELETED_NODE)
3095 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3096 // Add extra indirection if needed.
3098 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3099 MachinePointerInfo::getGOT(),
3100 false, false, false, 0);
3102 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3103 unsigned char OpFlags = 0;
3105 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3106 // external symbols should go through the PLT.
3107 if (Subtarget->isTargetELF() &&
3108 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3109 OpFlags = X86II::MO_PLT;
3110 } else if (Subtarget->isPICStyleStubAny() &&
3111 (!Subtarget->getTargetTriple().isMacOSX() ||
3112 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3113 // PC-relative references to external symbols should go through $stub,
3114 // unless we're building with the leopard linker or later, which
3115 // automatically synthesizes these stubs.
3116 OpFlags = X86II::MO_DARWIN_STUB;
3119 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3121 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3122 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3123 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3126 // Returns a chain & a flag for retval copy to use.
3127 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3128 SmallVector<SDValue, 8> Ops;
3130 if (!IsSibcall && isTailCall) {
3131 Chain = DAG.getCALLSEQ_END(Chain,
3132 DAG.getIntPtrConstant(NumBytesToPop, true),
3133 DAG.getIntPtrConstant(0, true), InFlag, dl);
3134 InFlag = Chain.getValue(1);
3137 Ops.push_back(Chain);
3138 Ops.push_back(Callee);
3141 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3143 // Add argument registers to the end of the list so that they are known live
3145 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3146 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3147 RegsToPass[i].second.getValueType()));
3149 // Add a register mask operand representing the call-preserved registers.
3150 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3151 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3152 assert(Mask && "Missing call preserved mask for calling convention");
3153 Ops.push_back(DAG.getRegisterMask(Mask));
3155 if (InFlag.getNode())
3156 Ops.push_back(InFlag);
3160 //// If this is the first return lowered for this function, add the regs
3161 //// to the liveout set for the function.
3162 // This isn't right, although it's probably harmless on x86; liveouts
3163 // should be computed from returns not tail calls. Consider a void
3164 // function making a tail call to a function returning int.
3165 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3168 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3169 InFlag = Chain.getValue(1);
3171 // Create the CALLSEQ_END node.
3172 unsigned NumBytesForCalleeToPop;
3173 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3174 DAG.getTarget().Options.GuaranteedTailCallOpt))
3175 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3176 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3177 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3178 SR == StackStructReturn)
3179 // If this is a call to a struct-return function, the callee
3180 // pops the hidden struct pointer, so we have to push it back.
3181 // This is common for Darwin/X86, Linux & Mingw32 targets.
3182 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3183 NumBytesForCalleeToPop = 4;
3185 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3187 // Returns a flag for retval copy to use.
3189 Chain = DAG.getCALLSEQ_END(Chain,
3190 DAG.getIntPtrConstant(NumBytesToPop, true),
3191 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3194 InFlag = Chain.getValue(1);
3197 // Handle result values, copying them out of physregs into vregs that we
3199 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3200 Ins, dl, DAG, InVals);
3203 //===----------------------------------------------------------------------===//
3204 // Fast Calling Convention (tail call) implementation
3205 //===----------------------------------------------------------------------===//
3207 // Like std call, callee cleans arguments, convention except that ECX is
3208 // reserved for storing the tail called function address. Only 2 registers are
3209 // free for argument passing (inreg). Tail call optimization is performed
3211 // * tailcallopt is enabled
3212 // * caller/callee are fastcc
3213 // On X86_64 architecture with GOT-style position independent code only local
3214 // (within module) calls are supported at the moment.
3215 // To keep the stack aligned according to platform abi the function
3216 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3217 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3218 // If a tail called function callee has more arguments than the caller the
3219 // caller needs to make sure that there is room to move the RETADDR to. This is
3220 // achieved by reserving an area the size of the argument delta right after the
3221 // original RETADDR, but before the saved framepointer or the spilled registers
3222 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3234 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3235 /// for a 16 byte align requirement.
3237 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3238 SelectionDAG& DAG) const {
3239 MachineFunction &MF = DAG.getMachineFunction();
3240 const TargetMachine &TM = MF.getTarget();
3241 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3242 TM.getSubtargetImpl()->getRegisterInfo());
3243 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3244 unsigned StackAlignment = TFI.getStackAlignment();
3245 uint64_t AlignMask = StackAlignment - 1;
3246 int64_t Offset = StackSize;
3247 unsigned SlotSize = RegInfo->getSlotSize();
3248 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3249 // Number smaller than 12 so just add the difference.
3250 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3252 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3253 Offset = ((~AlignMask) & Offset) + StackAlignment +
3254 (StackAlignment-SlotSize);
3259 /// MatchingStackOffset - Return true if the given stack call argument is
3260 /// already available in the same position (relatively) of the caller's
3261 /// incoming argument stack.
3263 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3264 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3265 const X86InstrInfo *TII) {
3266 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3268 if (Arg.getOpcode() == ISD::CopyFromReg) {
3269 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3270 if (!TargetRegisterInfo::isVirtualRegister(VR))
3272 MachineInstr *Def = MRI->getVRegDef(VR);
3275 if (!Flags.isByVal()) {
3276 if (!TII->isLoadFromStackSlot(Def, FI))
3279 unsigned Opcode = Def->getOpcode();
3280 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3281 Def->getOperand(1).isFI()) {
3282 FI = Def->getOperand(1).getIndex();
3283 Bytes = Flags.getByValSize();
3287 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3288 if (Flags.isByVal())
3289 // ByVal argument is passed in as a pointer but it's now being
3290 // dereferenced. e.g.
3291 // define @foo(%struct.X* %A) {
3292 // tail call @bar(%struct.X* byval %A)
3295 SDValue Ptr = Ld->getBasePtr();
3296 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3299 FI = FINode->getIndex();
3300 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3301 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3302 FI = FINode->getIndex();
3303 Bytes = Flags.getByValSize();
3307 assert(FI != INT_MAX);
3308 if (!MFI->isFixedObjectIndex(FI))
3310 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3313 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3314 /// for tail call optimization. Targets which want to do tail call
3315 /// optimization should implement this function.
3317 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3318 CallingConv::ID CalleeCC,
3320 bool isCalleeStructRet,
3321 bool isCallerStructRet,
3323 const SmallVectorImpl<ISD::OutputArg> &Outs,
3324 const SmallVectorImpl<SDValue> &OutVals,
3325 const SmallVectorImpl<ISD::InputArg> &Ins,
3326 SelectionDAG &DAG) const {
3327 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3330 // If -tailcallopt is specified, make fastcc functions tail-callable.
3331 const MachineFunction &MF = DAG.getMachineFunction();
3332 const Function *CallerF = MF.getFunction();
3334 // If the function return type is x86_fp80 and the callee return type is not,
3335 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3336 // perform a tailcall optimization here.
3337 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3340 CallingConv::ID CallerCC = CallerF->getCallingConv();
3341 bool CCMatch = CallerCC == CalleeCC;
3342 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3343 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3345 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3346 if (IsTailCallConvention(CalleeCC) && CCMatch)
3351 // Look for obvious safe cases to perform tail call optimization that do not
3352 // require ABI changes. This is what gcc calls sibcall.
3354 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3355 // emit a special epilogue.
3356 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3357 DAG.getSubtarget().getRegisterInfo());
3358 if (RegInfo->needsStackRealignment(MF))
3361 // Also avoid sibcall optimization if either caller or callee uses struct
3362 // return semantics.
3363 if (isCalleeStructRet || isCallerStructRet)
3366 // An stdcall/thiscall caller is expected to clean up its arguments; the
3367 // callee isn't going to do that.
3368 // FIXME: this is more restrictive than needed. We could produce a tailcall
3369 // when the stack adjustment matches. For example, with a thiscall that takes
3370 // only one argument.
3371 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3372 CallerCC == CallingConv::X86_ThisCall))
3375 // Do not sibcall optimize vararg calls unless all arguments are passed via
3377 if (isVarArg && !Outs.empty()) {
3379 // Optimizing for varargs on Win64 is unlikely to be safe without
3380 // additional testing.
3381 if (IsCalleeWin64 || IsCallerWin64)
3384 SmallVector<CCValAssign, 16> ArgLocs;
3385 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3388 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3389 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3390 if (!ArgLocs[i].isRegLoc())
3394 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3395 // stack. Therefore, if it's not used by the call it is not safe to optimize
3396 // this into a sibcall.
3397 bool Unused = false;
3398 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3405 SmallVector<CCValAssign, 16> RVLocs;
3406 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3408 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3409 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3410 CCValAssign &VA = RVLocs[i];
3411 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3416 // If the calling conventions do not match, then we'd better make sure the
3417 // results are returned in the same way as what the caller expects.
3419 SmallVector<CCValAssign, 16> RVLocs1;
3420 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3422 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3424 SmallVector<CCValAssign, 16> RVLocs2;
3425 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3427 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3429 if (RVLocs1.size() != RVLocs2.size())
3431 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3432 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3434 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3436 if (RVLocs1[i].isRegLoc()) {
3437 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3440 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3446 // If the callee takes no arguments then go on to check the results of the
3448 if (!Outs.empty()) {
3449 // Check if stack adjustment is needed. For now, do not do this if any
3450 // argument is passed on the stack.
3451 SmallVector<CCValAssign, 16> ArgLocs;
3452 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3455 // Allocate shadow area for Win64
3457 CCInfo.AllocateStack(32, 8);
3459 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3460 if (CCInfo.getNextStackOffset()) {
3461 MachineFunction &MF = DAG.getMachineFunction();
3462 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3465 // Check if the arguments are already laid out in the right way as
3466 // the caller's fixed stack objects.
3467 MachineFrameInfo *MFI = MF.getFrameInfo();
3468 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3469 const X86InstrInfo *TII =
3470 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3471 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3472 CCValAssign &VA = ArgLocs[i];
3473 SDValue Arg = OutVals[i];
3474 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3475 if (VA.getLocInfo() == CCValAssign::Indirect)
3477 if (!VA.isRegLoc()) {
3478 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3485 // If the tailcall address may be in a register, then make sure it's
3486 // possible to register allocate for it. In 32-bit, the call address can
3487 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3488 // callee-saved registers are restored. These happen to be the same
3489 // registers used to pass 'inreg' arguments so watch out for those.
3490 if (!Subtarget->is64Bit() &&
3491 ((!isa<GlobalAddressSDNode>(Callee) &&
3492 !isa<ExternalSymbolSDNode>(Callee)) ||
3493 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3494 unsigned NumInRegs = 0;
3495 // In PIC we need an extra register to formulate the address computation
3497 unsigned MaxInRegs =
3498 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3500 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3501 CCValAssign &VA = ArgLocs[i];
3504 unsigned Reg = VA.getLocReg();
3507 case X86::EAX: case X86::EDX: case X86::ECX:
3508 if (++NumInRegs == MaxInRegs)
3520 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3521 const TargetLibraryInfo *libInfo) const {
3522 return X86::createFastISel(funcInfo, libInfo);
3525 //===----------------------------------------------------------------------===//
3526 // Other Lowering Hooks
3527 //===----------------------------------------------------------------------===//
3529 static bool MayFoldLoad(SDValue Op) {
3530 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3533 static bool MayFoldIntoStore(SDValue Op) {
3534 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3537 static bool isTargetShuffle(unsigned Opcode) {
3539 default: return false;
3540 case X86ISD::BLENDI:
3541 case X86ISD::PSHUFB:
3542 case X86ISD::PSHUFD:
3543 case X86ISD::PSHUFHW:
3544 case X86ISD::PSHUFLW:
3546 case X86ISD::PALIGNR:
3547 case X86ISD::MOVLHPS:
3548 case X86ISD::MOVLHPD:
3549 case X86ISD::MOVHLPS:
3550 case X86ISD::MOVLPS:
3551 case X86ISD::MOVLPD:
3552 case X86ISD::MOVSHDUP:
3553 case X86ISD::MOVSLDUP:
3554 case X86ISD::MOVDDUP:
3557 case X86ISD::UNPCKL:
3558 case X86ISD::UNPCKH:
3559 case X86ISD::VPERMILPI:
3560 case X86ISD::VPERM2X128:
3561 case X86ISD::VPERMI:
3566 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3567 SDValue V1, SelectionDAG &DAG) {
3569 default: llvm_unreachable("Unknown x86 shuffle node");
3570 case X86ISD::MOVSHDUP:
3571 case X86ISD::MOVSLDUP:
3572 case X86ISD::MOVDDUP:
3573 return DAG.getNode(Opc, dl, VT, V1);
3577 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3578 SDValue V1, unsigned TargetMask,
3579 SelectionDAG &DAG) {
3581 default: llvm_unreachable("Unknown x86 shuffle node");
3582 case X86ISD::PSHUFD:
3583 case X86ISD::PSHUFHW:
3584 case X86ISD::PSHUFLW:
3585 case X86ISD::VPERMILPI:
3586 case X86ISD::VPERMI:
3587 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3591 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3592 SDValue V1, SDValue V2, unsigned TargetMask,
3593 SelectionDAG &DAG) {
3595 default: llvm_unreachable("Unknown x86 shuffle node");
3596 case X86ISD::PALIGNR:
3597 case X86ISD::VALIGN:
3599 case X86ISD::VPERM2X128:
3600 return DAG.getNode(Opc, dl, VT, V1, V2,
3601 DAG.getConstant(TargetMask, MVT::i8));
3605 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3606 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3608 default: llvm_unreachable("Unknown x86 shuffle node");
3609 case X86ISD::MOVLHPS:
3610 case X86ISD::MOVLHPD:
3611 case X86ISD::MOVHLPS:
3612 case X86ISD::MOVLPS:
3613 case X86ISD::MOVLPD:
3616 case X86ISD::UNPCKL:
3617 case X86ISD::UNPCKH:
3618 return DAG.getNode(Opc, dl, VT, V1, V2);
3622 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3623 MachineFunction &MF = DAG.getMachineFunction();
3624 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3625 DAG.getSubtarget().getRegisterInfo());
3626 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3627 int ReturnAddrIndex = FuncInfo->getRAIndex();
3629 if (ReturnAddrIndex == 0) {
3630 // Set up a frame object for the return address.
3631 unsigned SlotSize = RegInfo->getSlotSize();
3632 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3635 FuncInfo->setRAIndex(ReturnAddrIndex);
3638 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3641 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3642 bool hasSymbolicDisplacement) {
3643 // Offset should fit into 32 bit immediate field.
3644 if (!isInt<32>(Offset))
3647 // If we don't have a symbolic displacement - we don't have any extra
3649 if (!hasSymbolicDisplacement)
3652 // FIXME: Some tweaks might be needed for medium code model.
3653 if (M != CodeModel::Small && M != CodeModel::Kernel)
3656 // For small code model we assume that latest object is 16MB before end of 31
3657 // bits boundary. We may also accept pretty large negative constants knowing
3658 // that all objects are in the positive half of address space.
3659 if (M == CodeModel::Small && Offset < 16*1024*1024)
3662 // For kernel code model we know that all object resist in the negative half
3663 // of 32bits address space. We may not accept negative offsets, since they may
3664 // be just off and we may accept pretty large positive ones.
3665 if (M == CodeModel::Kernel && Offset > 0)
3671 /// isCalleePop - Determines whether the callee is required to pop its
3672 /// own arguments. Callee pop is necessary to support tail calls.
3673 bool X86::isCalleePop(CallingConv::ID CallingConv,
3674 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3675 switch (CallingConv) {
3678 case CallingConv::X86_StdCall:
3679 case CallingConv::X86_FastCall:
3680 case CallingConv::X86_ThisCall:
3682 case CallingConv::Fast:
3683 case CallingConv::GHC:
3684 case CallingConv::HiPE:
3691 /// \brief Return true if the condition is an unsigned comparison operation.
3692 static bool isX86CCUnsigned(unsigned X86CC) {
3694 default: llvm_unreachable("Invalid integer condition!");
3695 case X86::COND_E: return true;
3696 case X86::COND_G: return false;
3697 case X86::COND_GE: return false;
3698 case X86::COND_L: return false;
3699 case X86::COND_LE: return false;
3700 case X86::COND_NE: return true;
3701 case X86::COND_B: return true;
3702 case X86::COND_A: return true;
3703 case X86::COND_BE: return true;
3704 case X86::COND_AE: return true;
3706 llvm_unreachable("covered switch fell through?!");
3709 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3710 /// specific condition code, returning the condition code and the LHS/RHS of the
3711 /// comparison to make.
3712 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3713 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3715 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3716 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3717 // X > -1 -> X == 0, jump !sign.
3718 RHS = DAG.getConstant(0, RHS.getValueType());
3719 return X86::COND_NS;
3721 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3722 // X < 0 -> X == 0, jump on sign.
3725 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3727 RHS = DAG.getConstant(0, RHS.getValueType());
3728 return X86::COND_LE;
3732 switch (SetCCOpcode) {
3733 default: llvm_unreachable("Invalid integer condition!");
3734 case ISD::SETEQ: return X86::COND_E;
3735 case ISD::SETGT: return X86::COND_G;
3736 case ISD::SETGE: return X86::COND_GE;
3737 case ISD::SETLT: return X86::COND_L;
3738 case ISD::SETLE: return X86::COND_LE;
3739 case ISD::SETNE: return X86::COND_NE;
3740 case ISD::SETULT: return X86::COND_B;
3741 case ISD::SETUGT: return X86::COND_A;
3742 case ISD::SETULE: return X86::COND_BE;
3743 case ISD::SETUGE: return X86::COND_AE;
3747 // First determine if it is required or is profitable to flip the operands.
3749 // If LHS is a foldable load, but RHS is not, flip the condition.
3750 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3751 !ISD::isNON_EXTLoad(RHS.getNode())) {
3752 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3753 std::swap(LHS, RHS);
3756 switch (SetCCOpcode) {
3762 std::swap(LHS, RHS);
3766 // On a floating point condition, the flags are set as follows:
3768 // 0 | 0 | 0 | X > Y
3769 // 0 | 0 | 1 | X < Y
3770 // 1 | 0 | 0 | X == Y
3771 // 1 | 1 | 1 | unordered
3772 switch (SetCCOpcode) {
3773 default: llvm_unreachable("Condcode should be pre-legalized away");
3775 case ISD::SETEQ: return X86::COND_E;
3776 case ISD::SETOLT: // flipped
3778 case ISD::SETGT: return X86::COND_A;
3779 case ISD::SETOLE: // flipped
3781 case ISD::SETGE: return X86::COND_AE;
3782 case ISD::SETUGT: // flipped
3784 case ISD::SETLT: return X86::COND_B;
3785 case ISD::SETUGE: // flipped
3787 case ISD::SETLE: return X86::COND_BE;
3789 case ISD::SETNE: return X86::COND_NE;
3790 case ISD::SETUO: return X86::COND_P;
3791 case ISD::SETO: return X86::COND_NP;
3793 case ISD::SETUNE: return X86::COND_INVALID;
3797 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3798 /// code. Current x86 isa includes the following FP cmov instructions:
3799 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3800 static bool hasFPCMov(unsigned X86CC) {
3816 /// isFPImmLegal - Returns true if the target can instruction select the
3817 /// specified FP immediate natively. If false, the legalizer will
3818 /// materialize the FP immediate as a load from a constant pool.
3819 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3820 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3821 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3827 /// \brief Returns true if it is beneficial to convert a load of a constant
3828 /// to just the constant itself.
3829 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3831 assert(Ty->isIntegerTy());
3833 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3834 if (BitSize == 0 || BitSize > 64)
3839 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3840 /// the specified range (L, H].
3841 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3842 return (Val < 0) || (Val >= Low && Val < Hi);
3845 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3846 /// specified value.
3847 static bool isUndefOrEqual(int Val, int CmpVal) {
3848 return (Val < 0 || Val == CmpVal);
3851 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3852 /// from position Pos and ending in Pos+Size, falls within the specified
3853 /// sequential range (L, L+Pos]. or is undef.
3854 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3855 unsigned Pos, unsigned Size, int Low) {
3856 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3857 if (!isUndefOrEqual(Mask[i], Low))
3862 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3863 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3864 /// operand - by default will match for first operand.
3865 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3866 bool TestSecondOperand = false) {
3867 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3868 VT != MVT::v2f64 && VT != MVT::v2i64)
3871 unsigned NumElems = VT.getVectorNumElements();
3872 unsigned Lo = TestSecondOperand ? NumElems : 0;
3873 unsigned Hi = Lo + NumElems;
3875 for (unsigned i = 0; i < NumElems; ++i)
3876 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3882 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3883 /// is suitable for input to PSHUFHW.
3884 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3885 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3888 // Lower quadword copied in order or undef.
3889 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3892 // Upper quadword shuffled.
3893 for (unsigned i = 4; i != 8; ++i)
3894 if (!isUndefOrInRange(Mask[i], 4, 8))
3897 if (VT == MVT::v16i16) {
3898 // Lower quadword copied in order or undef.
3899 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3902 // Upper quadword shuffled.
3903 for (unsigned i = 12; i != 16; ++i)
3904 if (!isUndefOrInRange(Mask[i], 12, 16))
3911 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3912 /// is suitable for input to PSHUFLW.
3913 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3914 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3917 // Upper quadword copied in order.
3918 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3921 // Lower quadword shuffled.
3922 for (unsigned i = 0; i != 4; ++i)
3923 if (!isUndefOrInRange(Mask[i], 0, 4))
3926 if (VT == MVT::v16i16) {
3927 // Upper quadword copied in order.
3928 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3931 // Lower quadword shuffled.
3932 for (unsigned i = 8; i != 12; ++i)
3933 if (!isUndefOrInRange(Mask[i], 8, 12))
3940 /// \brief Return true if the mask specifies a shuffle of elements that is
3941 /// suitable for input to intralane (palignr) or interlane (valign) vector
3943 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3944 unsigned NumElts = VT.getVectorNumElements();
3945 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3946 unsigned NumLaneElts = NumElts/NumLanes;
3948 // Do not handle 64-bit element shuffles with palignr.
3949 if (NumLaneElts == 2)
3952 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3954 for (i = 0; i != NumLaneElts; ++i) {
3959 // Lane is all undef, go to next lane
3960 if (i == NumLaneElts)
3963 int Start = Mask[i+l];
3965 // Make sure its in this lane in one of the sources
3966 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3967 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3970 // If not lane 0, then we must match lane 0
3971 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3974 // Correct second source to be contiguous with first source
3975 if (Start >= (int)NumElts)
3976 Start -= NumElts - NumLaneElts;
3978 // Make sure we're shifting in the right direction.
3979 if (Start <= (int)(i+l))
3984 // Check the rest of the elements to see if they are consecutive.
3985 for (++i; i != NumLaneElts; ++i) {
3986 int Idx = Mask[i+l];
3988 // Make sure its in this lane
3989 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3990 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3993 // If not lane 0, then we must match lane 0
3994 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3997 if (Idx >= (int)NumElts)
3998 Idx -= NumElts - NumLaneElts;
4000 if (!isUndefOrEqual(Idx, Start+i))
4009 /// \brief Return true if the node specifies a shuffle of elements that is
4010 /// suitable for input to PALIGNR.
4011 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4012 const X86Subtarget *Subtarget) {
4013 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4014 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4015 VT.is512BitVector())
4016 // FIXME: Add AVX512BW.
4019 return isAlignrMask(Mask, VT, false);
4022 /// \brief Return true if the node specifies a shuffle of elements that is
4023 /// suitable for input to VALIGN.
4024 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4025 const X86Subtarget *Subtarget) {
4026 // FIXME: Add AVX512VL.
4027 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4029 return isAlignrMask(Mask, VT, true);
4032 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4033 /// the two vector operands have swapped position.
4034 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4035 unsigned NumElems) {
4036 for (unsigned i = 0; i != NumElems; ++i) {
4040 else if (idx < (int)NumElems)
4041 Mask[i] = idx + NumElems;
4043 Mask[i] = idx - NumElems;
4047 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4048 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4049 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4050 /// reverse of what x86 shuffles want.
4051 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4053 unsigned NumElems = VT.getVectorNumElements();
4054 unsigned NumLanes = VT.getSizeInBits()/128;
4055 unsigned NumLaneElems = NumElems/NumLanes;
4057 if (NumLaneElems != 2 && NumLaneElems != 4)
4060 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4061 bool symetricMaskRequired =
4062 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4064 // VSHUFPSY divides the resulting vector into 4 chunks.
4065 // The sources are also splitted into 4 chunks, and each destination
4066 // chunk must come from a different source chunk.
4068 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4069 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4071 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4072 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4074 // VSHUFPDY divides the resulting vector into 4 chunks.
4075 // The sources are also splitted into 4 chunks, and each destination
4076 // chunk must come from a different source chunk.
4078 // SRC1 => X3 X2 X1 X0
4079 // SRC2 => Y3 Y2 Y1 Y0
4081 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4083 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4084 unsigned HalfLaneElems = NumLaneElems/2;
4085 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4086 for (unsigned i = 0; i != NumLaneElems; ++i) {
4087 int Idx = Mask[i+l];
4088 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4089 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4091 // For VSHUFPSY, the mask of the second half must be the same as the
4092 // first but with the appropriate offsets. This works in the same way as
4093 // VPERMILPS works with masks.
4094 if (!symetricMaskRequired || Idx < 0)
4096 if (MaskVal[i] < 0) {
4097 MaskVal[i] = Idx - l;
4100 if ((signed)(Idx - l) != MaskVal[i])
4108 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4109 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4110 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4111 if (!VT.is128BitVector())
4114 unsigned NumElems = VT.getVectorNumElements();
4119 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4120 return isUndefOrEqual(Mask[0], 6) &&
4121 isUndefOrEqual(Mask[1], 7) &&
4122 isUndefOrEqual(Mask[2], 2) &&
4123 isUndefOrEqual(Mask[3], 3);
4126 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4127 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4129 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4130 if (!VT.is128BitVector())
4133 unsigned NumElems = VT.getVectorNumElements();
4138 return isUndefOrEqual(Mask[0], 2) &&
4139 isUndefOrEqual(Mask[1], 3) &&
4140 isUndefOrEqual(Mask[2], 2) &&
4141 isUndefOrEqual(Mask[3], 3);
4144 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4145 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4146 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4147 if (!VT.is128BitVector())
4150 unsigned NumElems = VT.getVectorNumElements();
4152 if (NumElems != 2 && NumElems != 4)
4155 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4156 if (!isUndefOrEqual(Mask[i], i + NumElems))
4159 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4160 if (!isUndefOrEqual(Mask[i], i))
4166 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4167 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4168 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4169 if (!VT.is128BitVector())
4172 unsigned NumElems = VT.getVectorNumElements();
4174 if (NumElems != 2 && NumElems != 4)
4177 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4178 if (!isUndefOrEqual(Mask[i], i))
4181 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4182 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4188 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4189 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4190 /// i. e: If all but one element come from the same vector.
4191 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4192 // TODO: Deal with AVX's VINSERTPS
4193 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4196 unsigned CorrectPosV1 = 0;
4197 unsigned CorrectPosV2 = 0;
4198 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4199 if (Mask[i] == -1) {
4207 else if (Mask[i] == i + 4)
4211 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4212 // We have 3 elements (undefs count as elements from any vector) from one
4213 // vector, and one from another.
4220 // Some special combinations that can be optimized.
4223 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4224 SelectionDAG &DAG) {
4225 MVT VT = SVOp->getSimpleValueType(0);
4228 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4231 ArrayRef<int> Mask = SVOp->getMask();
4233 // These are the special masks that may be optimized.
4234 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4235 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4236 bool MatchEvenMask = true;
4237 bool MatchOddMask = true;
4238 for (int i=0; i<8; ++i) {
4239 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4240 MatchEvenMask = false;
4241 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4242 MatchOddMask = false;
4245 if (!MatchEvenMask && !MatchOddMask)
4248 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4250 SDValue Op0 = SVOp->getOperand(0);
4251 SDValue Op1 = SVOp->getOperand(1);
4253 if (MatchEvenMask) {
4254 // Shift the second operand right to 32 bits.
4255 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4256 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4258 // Shift the first operand left to 32 bits.
4259 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4260 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4262 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4263 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4266 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4267 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4268 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4269 bool HasInt256, bool V2IsSplat = false) {
4271 assert(VT.getSizeInBits() >= 128 &&
4272 "Unsupported vector type for unpckl");
4274 unsigned NumElts = VT.getVectorNumElements();
4275 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4276 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4279 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4280 "Unsupported vector type for unpckh");
4282 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4283 unsigned NumLanes = VT.getSizeInBits()/128;
4284 unsigned NumLaneElts = NumElts/NumLanes;
4286 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4287 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4288 int BitI = Mask[l+i];
4289 int BitI1 = Mask[l+i+1];
4290 if (!isUndefOrEqual(BitI, j))
4293 if (!isUndefOrEqual(BitI1, NumElts))
4296 if (!isUndefOrEqual(BitI1, j + NumElts))
4305 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4306 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4307 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4308 bool HasInt256, bool V2IsSplat = false) {
4309 assert(VT.getSizeInBits() >= 128 &&
4310 "Unsupported vector type for unpckh");
4312 unsigned NumElts = VT.getVectorNumElements();
4313 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4314 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4317 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4318 "Unsupported vector type for unpckh");
4320 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4321 unsigned NumLanes = VT.getSizeInBits()/128;
4322 unsigned NumLaneElts = NumElts/NumLanes;
4324 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4325 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4326 int BitI = Mask[l+i];
4327 int BitI1 = Mask[l+i+1];
4328 if (!isUndefOrEqual(BitI, j))
4331 if (isUndefOrEqual(BitI1, NumElts))
4334 if (!isUndefOrEqual(BitI1, j+NumElts))
4342 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4343 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4345 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4346 unsigned NumElts = VT.getVectorNumElements();
4347 bool Is256BitVec = VT.is256BitVector();
4349 if (VT.is512BitVector())
4351 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4352 "Unsupported vector type for unpckh");
4354 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4355 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4358 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4359 // FIXME: Need a better way to get rid of this, there's no latency difference
4360 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4361 // the former later. We should also remove the "_undef" special mask.
4362 if (NumElts == 4 && Is256BitVec)
4365 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4366 // independently on 128-bit lanes.
4367 unsigned NumLanes = VT.getSizeInBits()/128;
4368 unsigned NumLaneElts = NumElts/NumLanes;
4370 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4371 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4372 int BitI = Mask[l+i];
4373 int BitI1 = Mask[l+i+1];
4375 if (!isUndefOrEqual(BitI, j))
4377 if (!isUndefOrEqual(BitI1, j))
4385 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4386 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4388 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4389 unsigned NumElts = VT.getVectorNumElements();
4391 if (VT.is512BitVector())
4394 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4395 "Unsupported vector type for unpckh");
4397 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4398 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4401 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4402 // independently on 128-bit lanes.
4403 unsigned NumLanes = VT.getSizeInBits()/128;
4404 unsigned NumLaneElts = NumElts/NumLanes;
4406 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4407 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4408 int BitI = Mask[l+i];
4409 int BitI1 = Mask[l+i+1];
4410 if (!isUndefOrEqual(BitI, j))
4412 if (!isUndefOrEqual(BitI1, j))
4419 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4420 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4421 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4422 if (!VT.is512BitVector())
4425 unsigned NumElts = VT.getVectorNumElements();
4426 unsigned HalfSize = NumElts/2;
4427 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4428 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4433 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4434 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4442 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4443 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4444 /// MOVSD, and MOVD, i.e. setting the lowest element.
4445 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4446 if (VT.getVectorElementType().getSizeInBits() < 32)
4448 if (!VT.is128BitVector())
4451 unsigned NumElts = VT.getVectorNumElements();
4453 if (!isUndefOrEqual(Mask[0], NumElts))
4456 for (unsigned i = 1; i != NumElts; ++i)
4457 if (!isUndefOrEqual(Mask[i], i))
4463 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4464 /// as permutations between 128-bit chunks or halves. As an example: this
4466 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4467 /// The first half comes from the second half of V1 and the second half from the
4468 /// the second half of V2.
4469 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4470 if (!HasFp256 || !VT.is256BitVector())
4473 // The shuffle result is divided into half A and half B. In total the two
4474 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4475 // B must come from C, D, E or F.
4476 unsigned HalfSize = VT.getVectorNumElements()/2;
4477 bool MatchA = false, MatchB = false;
4479 // Check if A comes from one of C, D, E, F.
4480 for (unsigned Half = 0; Half != 4; ++Half) {
4481 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4487 // Check if B comes from one of C, D, E, F.
4488 for (unsigned Half = 0; Half != 4; ++Half) {
4489 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4495 return MatchA && MatchB;
4498 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4499 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4500 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4501 MVT VT = SVOp->getSimpleValueType(0);
4503 unsigned HalfSize = VT.getVectorNumElements()/2;
4505 unsigned FstHalf = 0, SndHalf = 0;
4506 for (unsigned i = 0; i < HalfSize; ++i) {
4507 if (SVOp->getMaskElt(i) > 0) {
4508 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4512 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4513 if (SVOp->getMaskElt(i) > 0) {
4514 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4519 return (FstHalf | (SndHalf << 4));
4522 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4523 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4524 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4528 unsigned NumElts = VT.getVectorNumElements();
4530 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4531 for (unsigned i = 0; i != NumElts; ++i) {
4534 Imm8 |= Mask[i] << (i*2);
4539 unsigned LaneSize = 4;
4540 SmallVector<int, 4> MaskVal(LaneSize, -1);
4542 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4543 for (unsigned i = 0; i != LaneSize; ++i) {
4544 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4548 if (MaskVal[i] < 0) {
4549 MaskVal[i] = Mask[i+l] - l;
4550 Imm8 |= MaskVal[i] << (i*2);
4553 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4560 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4561 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4562 /// Note that VPERMIL mask matching is different depending whether theunderlying
4563 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4564 /// to the same elements of the low, but to the higher half of the source.
4565 /// In VPERMILPD the two lanes could be shuffled independently of each other
4566 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4567 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4568 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4569 if (VT.getSizeInBits() < 256 || EltSize < 32)
4571 bool symetricMaskRequired = (EltSize == 32);
4572 unsigned NumElts = VT.getVectorNumElements();
4574 unsigned NumLanes = VT.getSizeInBits()/128;
4575 unsigned LaneSize = NumElts/NumLanes;
4576 // 2 or 4 elements in one lane
4578 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4579 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4580 for (unsigned i = 0; i != LaneSize; ++i) {
4581 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4583 if (symetricMaskRequired) {
4584 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4585 ExpectedMaskVal[i] = Mask[i+l] - l;
4588 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4596 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4597 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4598 /// element of vector 2 and the other elements to come from vector 1 in order.
4599 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4600 bool V2IsSplat = false, bool V2IsUndef = false) {
4601 if (!VT.is128BitVector())
4604 unsigned NumOps = VT.getVectorNumElements();
4605 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4608 if (!isUndefOrEqual(Mask[0], 0))
4611 for (unsigned i = 1; i != NumOps; ++i)
4612 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4613 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4614 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4620 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4621 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4622 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4623 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4624 const X86Subtarget *Subtarget) {
4625 if (!Subtarget->hasSSE3())
4628 unsigned NumElems = VT.getVectorNumElements();
4630 if ((VT.is128BitVector() && NumElems != 4) ||
4631 (VT.is256BitVector() && NumElems != 8) ||
4632 (VT.is512BitVector() && NumElems != 16))
4635 // "i+1" is the value the indexed mask element must have
4636 for (unsigned i = 0; i != NumElems; i += 2)
4637 if (!isUndefOrEqual(Mask[i], i+1) ||
4638 !isUndefOrEqual(Mask[i+1], i+1))
4644 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4645 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4646 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4647 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4648 const X86Subtarget *Subtarget) {
4649 if (!Subtarget->hasSSE3())
4652 unsigned NumElems = VT.getVectorNumElements();
4654 if ((VT.is128BitVector() && NumElems != 4) ||
4655 (VT.is256BitVector() && NumElems != 8) ||
4656 (VT.is512BitVector() && NumElems != 16))
4659 // "i" is the value the indexed mask element must have
4660 for (unsigned i = 0; i != NumElems; i += 2)
4661 if (!isUndefOrEqual(Mask[i], i) ||
4662 !isUndefOrEqual(Mask[i+1], i))
4668 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4669 /// specifies a shuffle of elements that is suitable for input to 256-bit
4670 /// version of MOVDDUP.
4671 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4672 if (!HasFp256 || !VT.is256BitVector())
4675 unsigned NumElts = VT.getVectorNumElements();
4679 for (unsigned i = 0; i != NumElts/2; ++i)
4680 if (!isUndefOrEqual(Mask[i], 0))
4682 for (unsigned i = NumElts/2; i != NumElts; ++i)
4683 if (!isUndefOrEqual(Mask[i], NumElts/2))
4688 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4689 /// specifies a shuffle of elements that is suitable for input to 128-bit
4690 /// version of MOVDDUP.
4691 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4692 if (!VT.is128BitVector())
4695 unsigned e = VT.getVectorNumElements() / 2;
4696 for (unsigned i = 0; i != e; ++i)
4697 if (!isUndefOrEqual(Mask[i], i))
4699 for (unsigned i = 0; i != e; ++i)
4700 if (!isUndefOrEqual(Mask[e+i], i))
4705 /// isVEXTRACTIndex - Return true if the specified
4706 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4707 /// suitable for instruction that extract 128 or 256 bit vectors
4708 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4709 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4710 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4713 // The index should be aligned on a vecWidth-bit boundary.
4715 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4717 MVT VT = N->getSimpleValueType(0);
4718 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4719 bool Result = (Index * ElSize) % vecWidth == 0;
4724 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4725 /// operand specifies a subvector insert that is suitable for input to
4726 /// insertion of 128 or 256-bit subvectors
4727 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4728 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4729 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4731 // The index should be aligned on a vecWidth-bit boundary.
4733 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4735 MVT VT = N->getSimpleValueType(0);
4736 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4737 bool Result = (Index * ElSize) % vecWidth == 0;
4742 bool X86::isVINSERT128Index(SDNode *N) {
4743 return isVINSERTIndex(N, 128);
4746 bool X86::isVINSERT256Index(SDNode *N) {
4747 return isVINSERTIndex(N, 256);
4750 bool X86::isVEXTRACT128Index(SDNode *N) {
4751 return isVEXTRACTIndex(N, 128);
4754 bool X86::isVEXTRACT256Index(SDNode *N) {
4755 return isVEXTRACTIndex(N, 256);
4758 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4759 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4760 /// Handles 128-bit and 256-bit.
4761 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4762 MVT VT = N->getSimpleValueType(0);
4764 assert((VT.getSizeInBits() >= 128) &&
4765 "Unsupported vector type for PSHUF/SHUFP");
4767 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4768 // independently on 128-bit lanes.
4769 unsigned NumElts = VT.getVectorNumElements();
4770 unsigned NumLanes = VT.getSizeInBits()/128;
4771 unsigned NumLaneElts = NumElts/NumLanes;
4773 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4774 "Only supports 2, 4 or 8 elements per lane");
4776 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4778 for (unsigned i = 0; i != NumElts; ++i) {
4779 int Elt = N->getMaskElt(i);
4780 if (Elt < 0) continue;
4781 Elt &= NumLaneElts - 1;
4782 unsigned ShAmt = (i << Shift) % 8;
4783 Mask |= Elt << ShAmt;
4789 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4790 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4791 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4792 MVT VT = N->getSimpleValueType(0);
4794 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4795 "Unsupported vector type for PSHUFHW");
4797 unsigned NumElts = VT.getVectorNumElements();
4800 for (unsigned l = 0; l != NumElts; l += 8) {
4801 // 8 nodes per lane, but we only care about the last 4.
4802 for (unsigned i = 0; i < 4; ++i) {
4803 int Elt = N->getMaskElt(l+i+4);
4804 if (Elt < 0) continue;
4805 Elt &= 0x3; // only 2-bits.
4806 Mask |= Elt << (i * 2);
4813 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4814 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4815 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4816 MVT VT = N->getSimpleValueType(0);
4818 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4819 "Unsupported vector type for PSHUFHW");
4821 unsigned NumElts = VT.getVectorNumElements();
4824 for (unsigned l = 0; l != NumElts; l += 8) {
4825 // 8 nodes per lane, but we only care about the first 4.
4826 for (unsigned i = 0; i < 4; ++i) {
4827 int Elt = N->getMaskElt(l+i);
4828 if (Elt < 0) continue;
4829 Elt &= 0x3; // only 2-bits
4830 Mask |= Elt << (i * 2);
4837 /// \brief Return the appropriate immediate to shuffle the specified
4838 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4839 /// VALIGN (if Interlane is true) instructions.
4840 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4842 MVT VT = SVOp->getSimpleValueType(0);
4843 unsigned EltSize = InterLane ? 1 :
4844 VT.getVectorElementType().getSizeInBits() >> 3;
4846 unsigned NumElts = VT.getVectorNumElements();
4847 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4848 unsigned NumLaneElts = NumElts/NumLanes;
4852 for (i = 0; i != NumElts; ++i) {
4853 Val = SVOp->getMaskElt(i);
4857 if (Val >= (int)NumElts)
4858 Val -= NumElts - NumLaneElts;
4860 assert(Val - i > 0 && "PALIGNR imm should be positive");
4861 return (Val - i) * EltSize;
4864 /// \brief Return the appropriate immediate to shuffle the specified
4865 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4866 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4867 return getShuffleAlignrImmediate(SVOp, false);
4870 /// \brief Return the appropriate immediate to shuffle the specified
4871 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4872 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4873 return getShuffleAlignrImmediate(SVOp, true);
4877 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4878 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4879 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4880 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4883 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4885 MVT VecVT = N->getOperand(0).getSimpleValueType();
4886 MVT ElVT = VecVT.getVectorElementType();
4888 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4889 return Index / NumElemsPerChunk;
4892 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4893 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4894 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4895 llvm_unreachable("Illegal insert subvector for VINSERT");
4898 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4900 MVT VecVT = N->getSimpleValueType(0);
4901 MVT ElVT = VecVT.getVectorElementType();
4903 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4904 return Index / NumElemsPerChunk;
4907 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4909 /// and VINSERTI128 instructions.
4910 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 128);
4914 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4915 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4916 /// and VINSERTI64x4 instructions.
4917 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4918 return getExtractVEXTRACTImmediate(N, 256);
4921 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4923 /// and VINSERTI128 instructions.
4924 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 128);
4928 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4929 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4930 /// and VINSERTI64x4 instructions.
4931 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4932 return getInsertVINSERTImmediate(N, 256);
4935 /// isZero - Returns true if Elt is a constant integer zero
4936 static bool isZero(SDValue V) {
4937 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4938 return C && C->isNullValue();
4941 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4943 bool X86::isZeroNode(SDValue Elt) {
4946 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4947 return CFP->getValueAPF().isPosZero();
4951 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4952 /// match movhlps. The lower half elements should come from upper half of
4953 /// V1 (and in order), and the upper half elements should come from the upper
4954 /// half of V2 (and in order).
4955 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4956 if (!VT.is128BitVector())
4958 if (VT.getVectorNumElements() != 4)
4960 for (unsigned i = 0, e = 2; i != e; ++i)
4961 if (!isUndefOrEqual(Mask[i], i+2))
4963 for (unsigned i = 2; i != 4; ++i)
4964 if (!isUndefOrEqual(Mask[i], i+4))
4969 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4970 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4972 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4973 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4975 N = N->getOperand(0).getNode();
4976 if (!ISD::isNON_EXTLoad(N))
4979 *LD = cast<LoadSDNode>(N);
4983 // Test whether the given value is a vector value which will be legalized
4985 static bool WillBeConstantPoolLoad(SDNode *N) {
4986 if (N->getOpcode() != ISD::BUILD_VECTOR)
4989 // Check for any non-constant elements.
4990 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4991 switch (N->getOperand(i).getNode()->getOpcode()) {
4993 case ISD::ConstantFP:
5000 // Vectors of all-zeros and all-ones are materialized with special
5001 // instructions rather than being loaded.
5002 return !ISD::isBuildVectorAllZeros(N) &&
5003 !ISD::isBuildVectorAllOnes(N);
5006 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5007 /// match movlp{s|d}. The lower half elements should come from lower half of
5008 /// V1 (and in order), and the upper half elements should come from the upper
5009 /// half of V2 (and in order). And since V1 will become the source of the
5010 /// MOVLP, it must be either a vector load or a scalar load to vector.
5011 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5012 ArrayRef<int> Mask, MVT VT) {
5013 if (!VT.is128BitVector())
5016 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5018 // Is V2 is a vector load, don't do this transformation. We will try to use
5019 // load folding shufps op.
5020 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5023 unsigned NumElems = VT.getVectorNumElements();
5025 if (NumElems != 2 && NumElems != 4)
5027 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5028 if (!isUndefOrEqual(Mask[i], i))
5030 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5031 if (!isUndefOrEqual(Mask[i], i+NumElems))
5036 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5037 /// to an zero vector.
5038 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5039 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5040 SDValue V1 = N->getOperand(0);
5041 SDValue V2 = N->getOperand(1);
5042 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5043 for (unsigned i = 0; i != NumElems; ++i) {
5044 int Idx = N->getMaskElt(i);
5045 if (Idx >= (int)NumElems) {
5046 unsigned Opc = V2.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5052 } else if (Idx >= 0) {
5053 unsigned Opc = V1.getOpcode();
5054 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5056 if (Opc != ISD::BUILD_VECTOR ||
5057 !X86::isZeroNode(V1.getOperand(Idx)))
5064 /// getZeroVector - Returns a vector of specified type with all zero elements.
5066 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5067 SelectionDAG &DAG, SDLoc dl) {
5068 assert(VT.isVector() && "Expected a vector type");
5070 // Always build SSE zero vectors as <4 x i32> bitcasted
5071 // to their dest type. This ensures they get CSE'd.
5073 if (VT.is128BitVector()) { // SSE
5074 if (Subtarget->hasSSE2()) { // SSE2
5075 SDValue Cst = DAG.getConstant(0, MVT::i32);
5076 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5078 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5081 } else if (VT.is256BitVector()) { // AVX
5082 if (Subtarget->hasInt256()) { // AVX2
5083 SDValue Cst = DAG.getConstant(0, MVT::i32);
5084 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5085 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5087 // 256-bit logic and arithmetic instructions in AVX are all
5088 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5089 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5090 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5093 } else if (VT.is512BitVector()) { // AVX-512
5094 SDValue Cst = DAG.getConstant(0, MVT::i32);
5095 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5096 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5097 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5098 } else if (VT.getScalarType() == MVT::i1) {
5099 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5100 SDValue Cst = DAG.getConstant(0, MVT::i1);
5101 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5102 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5104 llvm_unreachable("Unexpected vector type");
5106 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5109 /// getOnesVector - Returns a vector of specified type with all bits set.
5110 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5111 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5112 /// Then bitcast to their original type, ensuring they get CSE'd.
5113 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5115 assert(VT.isVector() && "Expected a vector type");
5117 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5119 if (VT.is256BitVector()) {
5120 if (HasInt256) { // AVX2
5121 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5124 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5125 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5127 } else if (VT.is128BitVector()) {
5128 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5130 llvm_unreachable("Unexpected vector type");
5132 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5135 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5136 /// that point to V2 points to its first element.
5137 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5138 for (unsigned i = 0; i != NumElems; ++i) {
5139 if (Mask[i] > (int)NumElems) {
5145 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5146 /// operation of specified width.
5147 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5149 unsigned NumElems = VT.getVectorNumElements();
5150 SmallVector<int, 8> Mask;
5151 Mask.push_back(NumElems);
5152 for (unsigned i = 1; i != NumElems; ++i)
5154 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5157 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5158 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5160 unsigned NumElems = VT.getVectorNumElements();
5161 SmallVector<int, 8> Mask;
5162 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5164 Mask.push_back(i + NumElems);
5166 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5169 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5170 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5172 unsigned NumElems = VT.getVectorNumElements();
5173 SmallVector<int, 8> Mask;
5174 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5175 Mask.push_back(i + Half);
5176 Mask.push_back(i + NumElems + Half);
5178 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5181 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5182 // a generic shuffle instruction because the target has no such instructions.
5183 // Generate shuffles which repeat i16 and i8 several times until they can be
5184 // represented by v4f32 and then be manipulated by target suported shuffles.
5185 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5186 MVT VT = V.getSimpleValueType();
5187 int NumElems = VT.getVectorNumElements();
5190 while (NumElems > 4) {
5191 if (EltNo < NumElems/2) {
5192 V = getUnpackl(DAG, dl, VT, V, V);
5194 V = getUnpackh(DAG, dl, VT, V, V);
5195 EltNo -= NumElems/2;
5202 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5203 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5204 MVT VT = V.getSimpleValueType();
5207 if (VT.is128BitVector()) {
5208 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5209 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5210 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5212 } else if (VT.is256BitVector()) {
5213 // To use VPERMILPS to splat scalars, the second half of indicies must
5214 // refer to the higher part, which is a duplication of the lower one,
5215 // because VPERMILPS can only handle in-lane permutations.
5216 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5217 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5219 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5220 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5223 llvm_unreachable("Vector size not supported");
5225 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5228 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5229 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5230 MVT SrcVT = SV->getSimpleValueType(0);
5231 SDValue V1 = SV->getOperand(0);
5234 int EltNo = SV->getSplatIndex();
5235 int NumElems = SrcVT.getVectorNumElements();
5236 bool Is256BitVec = SrcVT.is256BitVector();
5238 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5239 "Unknown how to promote splat for type");
5241 // Extract the 128-bit part containing the splat element and update
5242 // the splat element index when it refers to the higher register.
5244 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5245 if (EltNo >= NumElems/2)
5246 EltNo -= NumElems/2;
5249 // All i16 and i8 vector types can't be used directly by a generic shuffle
5250 // instruction because the target has no such instruction. Generate shuffles
5251 // which repeat i16 and i8 several times until they fit in i32, and then can
5252 // be manipulated by target suported shuffles.
5253 MVT EltVT = SrcVT.getVectorElementType();
5254 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5255 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5257 // Recreate the 256-bit vector and place the same 128-bit vector
5258 // into the low and high part. This is necessary because we want
5259 // to use VPERM* to shuffle the vectors
5261 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5264 return getLegalSplat(DAG, V1, EltNo);
5267 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5268 /// vector of zero or undef vector. This produces a shuffle where the low
5269 /// element of V2 is swizzled into the zero/undef vector, landing at element
5270 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5271 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5273 const X86Subtarget *Subtarget,
5274 SelectionDAG &DAG) {
5275 MVT VT = V2.getSimpleValueType();
5277 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5278 unsigned NumElems = VT.getVectorNumElements();
5279 SmallVector<int, 16> MaskVec;
5280 for (unsigned i = 0; i != NumElems; ++i)
5281 // If this is the insertion idx, put the low elt of V2 here.
5282 MaskVec.push_back(i == Idx ? NumElems : i);
5283 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5286 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5287 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5288 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5289 /// shuffles which use a single input multiple times, and in those cases it will
5290 /// adjust the mask to only have indices within that single input.
5291 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5292 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5293 unsigned NumElems = VT.getVectorNumElements();
5297 bool IsFakeUnary = false;
5298 switch(N->getOpcode()) {
5299 case X86ISD::BLENDI:
5300 ImmN = N->getOperand(N->getNumOperands()-1);
5301 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5304 ImmN = N->getOperand(N->getNumOperands()-1);
5305 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5306 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 case X86ISD::UNPCKH:
5309 DecodeUNPCKHMask(VT, Mask);
5310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 case X86ISD::UNPCKL:
5313 DecodeUNPCKLMask(VT, Mask);
5314 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5316 case X86ISD::MOVHLPS:
5317 DecodeMOVHLPSMask(NumElems, Mask);
5318 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5320 case X86ISD::MOVLHPS:
5321 DecodeMOVLHPSMask(NumElems, Mask);
5322 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5324 case X86ISD::PALIGNR:
5325 ImmN = N->getOperand(N->getNumOperands()-1);
5326 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5328 case X86ISD::PSHUFD:
5329 case X86ISD::VPERMILPI:
5330 ImmN = N->getOperand(N->getNumOperands()-1);
5331 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5334 case X86ISD::PSHUFHW:
5335 ImmN = N->getOperand(N->getNumOperands()-1);
5336 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5339 case X86ISD::PSHUFLW:
5340 ImmN = N->getOperand(N->getNumOperands()-1);
5341 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5344 case X86ISD::PSHUFB: {
5346 SDValue MaskNode = N->getOperand(1);
5347 while (MaskNode->getOpcode() == ISD::BITCAST)
5348 MaskNode = MaskNode->getOperand(0);
5350 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5351 // If we have a build-vector, then things are easy.
5352 EVT VT = MaskNode.getValueType();
5353 assert(VT.isVector() &&
5354 "Can't produce a non-vector with a build_vector!");
5355 if (!VT.isInteger())
5358 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5360 SmallVector<uint64_t, 32> RawMask;
5361 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5362 SDValue Op = MaskNode->getOperand(i);
5363 if (Op->getOpcode() == ISD::UNDEF) {
5364 RawMask.push_back((uint64_t)SM_SentinelUndef);
5367 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5370 APInt MaskElement = CN->getAPIntValue();
5372 // We now have to decode the element which could be any integer size and
5373 // extract each byte of it.
5374 for (int j = 0; j < NumBytesPerElement; ++j) {
5375 // Note that this is x86 and so always little endian: the low byte is
5376 // the first byte of the mask.
5377 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5378 MaskElement = MaskElement.lshr(8);
5381 DecodePSHUFBMask(RawMask, Mask);
5385 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5389 SDValue Ptr = MaskLoad->getBasePtr();
5390 if (Ptr->getOpcode() == X86ISD::Wrapper)
5391 Ptr = Ptr->getOperand(0);
5393 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5394 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5397 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5398 // FIXME: Support AVX-512 here.
5399 Type *Ty = C->getType();
5400 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5401 Ty->getVectorNumElements() != 32))
5404 DecodePSHUFBMask(C, Mask);
5410 case X86ISD::VPERMI:
5411 ImmN = N->getOperand(N->getNumOperands()-1);
5412 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5416 case X86ISD::MOVSD: {
5417 // The index 0 always comes from the first element of the second source,
5418 // this is why MOVSS and MOVSD are used in the first place. The other
5419 // elements come from the other positions of the first source vector
5420 Mask.push_back(NumElems);
5421 for (unsigned i = 1; i != NumElems; ++i) {
5426 case X86ISD::VPERM2X128:
5427 ImmN = N->getOperand(N->getNumOperands()-1);
5428 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5429 if (Mask.empty()) return false;
5431 case X86ISD::MOVSLDUP:
5432 DecodeMOVSLDUPMask(VT, Mask);
5434 case X86ISD::MOVSHDUP:
5435 DecodeMOVSHDUPMask(VT, Mask);
5437 case X86ISD::MOVDDUP:
5438 case X86ISD::MOVLHPD:
5439 case X86ISD::MOVLPD:
5440 case X86ISD::MOVLPS:
5441 // Not yet implemented
5443 default: llvm_unreachable("unknown target shuffle node");
5446 // If we have a fake unary shuffle, the shuffle mask is spread across two
5447 // inputs that are actually the same node. Re-map the mask to always point
5448 // into the first input.
5451 if (M >= (int)Mask.size())
5457 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5458 /// element of the result of the vector shuffle.
5459 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5462 return SDValue(); // Limit search depth.
5464 SDValue V = SDValue(N, 0);
5465 EVT VT = V.getValueType();
5466 unsigned Opcode = V.getOpcode();
5468 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5469 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5470 int Elt = SV->getMaskElt(Index);
5473 return DAG.getUNDEF(VT.getVectorElementType());
5475 unsigned NumElems = VT.getVectorNumElements();
5476 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5477 : SV->getOperand(1);
5478 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5481 // Recurse into target specific vector shuffles to find scalars.
5482 if (isTargetShuffle(Opcode)) {
5483 MVT ShufVT = V.getSimpleValueType();
5484 unsigned NumElems = ShufVT.getVectorNumElements();
5485 SmallVector<int, 16> ShuffleMask;
5488 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5491 int Elt = ShuffleMask[Index];
5493 return DAG.getUNDEF(ShufVT.getVectorElementType());
5495 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5497 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5501 // Actual nodes that may contain scalar elements
5502 if (Opcode == ISD::BITCAST) {
5503 V = V.getOperand(0);
5504 EVT SrcVT = V.getValueType();
5505 unsigned NumElems = VT.getVectorNumElements();
5507 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5511 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5512 return (Index == 0) ? V.getOperand(0)
5513 : DAG.getUNDEF(VT.getVectorElementType());
5515 if (V.getOpcode() == ISD::BUILD_VECTOR)
5516 return V.getOperand(Index);
5521 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5522 /// shuffle operation which come from a consecutively from a zero. The
5523 /// search can start in two different directions, from left or right.
5524 /// We count undefs as zeros until PreferredNum is reached.
5525 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5526 unsigned NumElems, bool ZerosFromLeft,
5528 unsigned PreferredNum = -1U) {
5529 unsigned NumZeros = 0;
5530 for (unsigned i = 0; i != NumElems; ++i) {
5531 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5532 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5536 if (X86::isZeroNode(Elt))
5538 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5539 NumZeros = std::min(NumZeros + 1, PreferredNum);
5547 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5548 /// correspond consecutively to elements from one of the vector operands,
5549 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5551 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5552 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5553 unsigned NumElems, unsigned &OpNum) {
5554 bool SeenV1 = false;
5555 bool SeenV2 = false;
5557 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5558 int Idx = SVOp->getMaskElt(i);
5559 // Ignore undef indicies
5563 if (Idx < (int)NumElems)
5568 // Only accept consecutive elements from the same vector
5569 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5573 OpNum = SeenV1 ? 0 : 1;
5577 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5578 /// logical left shift of a vector.
5579 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5580 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5582 SVOp->getSimpleValueType(0).getVectorNumElements();
5583 unsigned NumZeros = getNumOfConsecutiveZeros(
5584 SVOp, NumElems, false /* check zeros from right */, DAG,
5585 SVOp->getMaskElt(0));
5591 // Considering the elements in the mask that are not consecutive zeros,
5592 // check if they consecutively come from only one of the source vectors.
5594 // V1 = {X, A, B, C} 0
5596 // vector_shuffle V1, V2 <1, 2, 3, X>
5598 if (!isShuffleMaskConsecutive(SVOp,
5599 0, // Mask Start Index
5600 NumElems-NumZeros, // Mask End Index(exclusive)
5601 NumZeros, // Where to start looking in the src vector
5602 NumElems, // Number of elements in vector
5603 OpSrc)) // Which source operand ?
5608 ShVal = SVOp->getOperand(OpSrc);
5612 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5613 /// logical left shift of a vector.
5614 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5615 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5617 SVOp->getSimpleValueType(0).getVectorNumElements();
5618 unsigned NumZeros = getNumOfConsecutiveZeros(
5619 SVOp, NumElems, true /* check zeros from left */, DAG,
5620 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5626 // Considering the elements in the mask that are not consecutive zeros,
5627 // check if they consecutively come from only one of the source vectors.
5629 // 0 { A, B, X, X } = V2
5631 // vector_shuffle V1, V2 <X, X, 4, 5>
5633 if (!isShuffleMaskConsecutive(SVOp,
5634 NumZeros, // Mask Start Index
5635 NumElems, // Mask End Index(exclusive)
5636 0, // Where to start looking in the src vector
5637 NumElems, // Number of elements in vector
5638 OpSrc)) // Which source operand ?
5643 ShVal = SVOp->getOperand(OpSrc);
5647 /// isVectorShift - Returns true if the shuffle can be implemented as a
5648 /// logical left or right shift of a vector.
5649 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5650 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5651 // Although the logic below support any bitwidth size, there are no
5652 // shift instructions which handle more than 128-bit vectors.
5653 if (!SVOp->getSimpleValueType(0).is128BitVector())
5656 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5657 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5663 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5665 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5666 unsigned NumNonZero, unsigned NumZero,
5668 const X86Subtarget* Subtarget,
5669 const TargetLowering &TLI) {
5676 for (unsigned i = 0; i < 16; ++i) {
5677 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5678 if (ThisIsNonZero && First) {
5680 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5682 V = DAG.getUNDEF(MVT::v8i16);
5687 SDValue ThisElt, LastElt;
5688 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5689 if (LastIsNonZero) {
5690 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5691 MVT::i16, Op.getOperand(i-1));
5693 if (ThisIsNonZero) {
5694 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5695 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5696 ThisElt, DAG.getConstant(8, MVT::i8));
5698 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5702 if (ThisElt.getNode())
5703 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5704 DAG.getIntPtrConstant(i/2));
5708 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5711 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5713 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5714 unsigned NumNonZero, unsigned NumZero,
5716 const X86Subtarget* Subtarget,
5717 const TargetLowering &TLI) {
5724 for (unsigned i = 0; i < 8; ++i) {
5725 bool isNonZero = (NonZeros & (1 << i)) != 0;
5729 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5731 V = DAG.getUNDEF(MVT::v8i16);
5734 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5735 MVT::v8i16, V, Op.getOperand(i),
5736 DAG.getIntPtrConstant(i));
5743 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5744 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5745 const X86Subtarget *Subtarget,
5746 const TargetLowering &TLI) {
5747 // Find all zeroable elements.
5749 for (int i=0; i < 4; ++i) {
5750 SDValue Elt = Op->getOperand(i);
5751 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5753 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5754 [](bool M) { return !M; }) > 1 &&
5755 "We expect at least two non-zero elements!");
5757 // We only know how to deal with build_vector nodes where elements are either
5758 // zeroable or extract_vector_elt with constant index.
5759 SDValue FirstNonZero;
5760 for (int i=0; i < 4; ++i) {
5763 SDValue Elt = Op->getOperand(i);
5764 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5765 !isa<ConstantSDNode>(Elt.getOperand(1)))
5767 // Make sure that this node is extracting from a 128-bit vector.
5768 MVT VT = Elt.getOperand(0).getSimpleValueType();
5769 if (!VT.is128BitVector())
5771 if (!FirstNonZero.getNode())
5775 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5776 SDValue V1 = FirstNonZero.getOperand(0);
5777 MVT VT = V1.getSimpleValueType();
5779 // See if this build_vector can be lowered as a blend with zero.
5781 unsigned EltMaskIdx, EltIdx;
5783 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5784 if (Zeroable[EltIdx]) {
5785 // The zero vector will be on the right hand side.
5786 Mask[EltIdx] = EltIdx+4;
5790 Elt = Op->getOperand(EltIdx);
5791 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5792 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5793 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5795 Mask[EltIdx] = EltIdx;
5799 // Let the shuffle legalizer deal with blend operations.
5800 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5801 if (V1.getSimpleValueType() != VT)
5802 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5803 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5806 // See if we can lower this build_vector to a INSERTPS.
5807 if (!Subtarget->hasSSE41())
5810 SDValue V2 = Elt.getOperand(0);
5811 if (Elt == FirstNonZero)
5814 bool CanFold = true;
5815 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5819 SDValue Current = Op->getOperand(i);
5820 SDValue SrcVector = Current->getOperand(0);
5823 CanFold = SrcVector == V1 &&
5824 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5830 assert(V1.getNode() && "Expected at least two non-zero elements!");
5831 if (V1.getSimpleValueType() != MVT::v4f32)
5832 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5833 if (V2.getSimpleValueType() != MVT::v4f32)
5834 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5836 // Ok, we can emit an INSERTPS instruction.
5838 for (int i = 0; i < 4; ++i)
5842 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5843 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5844 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5845 DAG.getIntPtrConstant(InsertPSMask));
5846 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5849 /// getVShift - Return a vector logical shift node.
5851 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5852 unsigned NumBits, SelectionDAG &DAG,
5853 const TargetLowering &TLI, SDLoc dl) {
5854 assert(VT.is128BitVector() && "Unknown type for VShift");
5855 EVT ShVT = MVT::v2i64;
5856 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5857 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5858 return DAG.getNode(ISD::BITCAST, dl, VT,
5859 DAG.getNode(Opc, dl, ShVT, SrcOp,
5860 DAG.getConstant(NumBits,
5861 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5865 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5867 // Check if the scalar load can be widened into a vector load. And if
5868 // the address is "base + cst" see if the cst can be "absorbed" into
5869 // the shuffle mask.
5870 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5871 SDValue Ptr = LD->getBasePtr();
5872 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5874 EVT PVT = LD->getValueType(0);
5875 if (PVT != MVT::i32 && PVT != MVT::f32)
5880 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5881 FI = FINode->getIndex();
5883 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5884 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5885 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5886 Offset = Ptr.getConstantOperandVal(1);
5887 Ptr = Ptr.getOperand(0);
5892 // FIXME: 256-bit vector instructions don't require a strict alignment,
5893 // improve this code to support it better.
5894 unsigned RequiredAlign = VT.getSizeInBits()/8;
5895 SDValue Chain = LD->getChain();
5896 // Make sure the stack object alignment is at least 16 or 32.
5897 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5898 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5899 if (MFI->isFixedObjectIndex(FI)) {
5900 // Can't change the alignment. FIXME: It's possible to compute
5901 // the exact stack offset and reference FI + adjust offset instead.
5902 // If someone *really* cares about this. That's the way to implement it.
5905 MFI->setObjectAlignment(FI, RequiredAlign);
5909 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5910 // Ptr + (Offset & ~15).
5913 if ((Offset % RequiredAlign) & 3)
5915 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5917 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5918 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5920 int EltNo = (Offset - StartOffset) >> 2;
5921 unsigned NumElems = VT.getVectorNumElements();
5923 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5924 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5925 LD->getPointerInfo().getWithOffset(StartOffset),
5926 false, false, false, 0);
5928 SmallVector<int, 8> Mask;
5929 for (unsigned i = 0; i != NumElems; ++i)
5930 Mask.push_back(EltNo);
5932 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5938 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5939 /// vector of type 'VT', see if the elements can be replaced by a single large
5940 /// load which has the same value as a build_vector whose operands are 'elts'.
5942 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5944 /// FIXME: we'd also like to handle the case where the last elements are zero
5945 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5946 /// There's even a handy isZeroNode for that purpose.
5947 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5948 SDLoc &DL, SelectionDAG &DAG,
5949 bool isAfterLegalize) {
5950 EVT EltVT = VT.getVectorElementType();
5951 unsigned NumElems = Elts.size();
5953 LoadSDNode *LDBase = nullptr;
5954 unsigned LastLoadedElt = -1U;
5956 // For each element in the initializer, see if we've found a load or an undef.
5957 // If we don't find an initial load element, or later load elements are
5958 // non-consecutive, bail out.
5959 for (unsigned i = 0; i < NumElems; ++i) {
5960 SDValue Elt = Elts[i];
5962 if (!Elt.getNode() ||
5963 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5966 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5968 LDBase = cast<LoadSDNode>(Elt.getNode());
5972 if (Elt.getOpcode() == ISD::UNDEF)
5975 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5976 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5981 // If we have found an entire vector of loads and undefs, then return a large
5982 // load of the entire vector width starting at the base pointer. If we found
5983 // consecutive loads for the low half, generate a vzext_load node.
5984 if (LastLoadedElt == NumElems - 1) {
5986 if (isAfterLegalize &&
5987 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5990 SDValue NewLd = SDValue();
5992 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5993 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5994 LDBase->getPointerInfo(),
5995 LDBase->isVolatile(), LDBase->isNonTemporal(),
5996 LDBase->isInvariant(), 0);
5997 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5998 LDBase->getPointerInfo(),
5999 LDBase->isVolatile(), LDBase->isNonTemporal(),
6000 LDBase->isInvariant(), LDBase->getAlignment());
6002 if (LDBase->hasAnyUseOfValue(1)) {
6003 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6005 SDValue(NewLd.getNode(), 1));
6006 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6007 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6008 SDValue(NewLd.getNode(), 1));
6013 if (NumElems == 4 && LastLoadedElt == 1 &&
6014 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6015 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6016 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6018 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6019 LDBase->getPointerInfo(),
6020 LDBase->getAlignment(),
6021 false/*isVolatile*/, true/*ReadMem*/,
6024 // Make sure the newly-created LOAD is in the same position as LDBase in
6025 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6026 // update uses of LDBase's output chain to use the TokenFactor.
6027 if (LDBase->hasAnyUseOfValue(1)) {
6028 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6029 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6030 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6031 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6032 SDValue(ResNode.getNode(), 1));
6035 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6040 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6041 /// to generate a splat value for the following cases:
6042 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6043 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6044 /// a scalar load, or a constant.
6045 /// The VBROADCAST node is returned when a pattern is found,
6046 /// or SDValue() otherwise.
6047 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6048 SelectionDAG &DAG) {
6049 // VBROADCAST requires AVX.
6050 // TODO: Splats could be generated for non-AVX CPUs using SSE
6051 // instructions, but there's less potential gain for only 128-bit vectors.
6052 if (!Subtarget->hasAVX())
6055 MVT VT = Op.getSimpleValueType();
6058 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6059 "Unsupported vector type for broadcast.");
6064 switch (Op.getOpcode()) {
6066 // Unknown pattern found.
6069 case ISD::BUILD_VECTOR: {
6070 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6071 BitVector UndefElements;
6072 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6074 // We need a splat of a single value to use broadcast, and it doesn't
6075 // make any sense if the value is only in one element of the vector.
6076 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6080 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6081 Ld.getOpcode() == ISD::ConstantFP);
6083 // Make sure that all of the users of a non-constant load are from the
6084 // BUILD_VECTOR node.
6085 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6090 case ISD::VECTOR_SHUFFLE: {
6091 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6093 // Shuffles must have a splat mask where the first element is
6095 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6098 SDValue Sc = Op.getOperand(0);
6099 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6100 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6102 if (!Subtarget->hasInt256())
6105 // Use the register form of the broadcast instruction available on AVX2.
6106 if (VT.getSizeInBits() >= 256)
6107 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6108 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6111 Ld = Sc.getOperand(0);
6112 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6113 Ld.getOpcode() == ISD::ConstantFP);
6115 // The scalar_to_vector node and the suspected
6116 // load node must have exactly one user.
6117 // Constants may have multiple users.
6119 // AVX-512 has register version of the broadcast
6120 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6121 Ld.getValueType().getSizeInBits() >= 32;
6122 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6129 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6130 bool IsGE256 = (VT.getSizeInBits() >= 256);
6132 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6133 // instruction to save 8 or more bytes of constant pool data.
6134 // TODO: If multiple splats are generated to load the same constant,
6135 // it may be detrimental to overall size. There needs to be a way to detect
6136 // that condition to know if this is truly a size win.
6137 const Function *F = DAG.getMachineFunction().getFunction();
6138 bool OptForSize = F->getAttributes().
6139 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6141 // Handle broadcasting a single constant scalar from the constant pool
6143 // On Sandybridge (no AVX2), it is still better to load a constant vector
6144 // from the constant pool and not to broadcast it from a scalar.
6145 // But override that restriction when optimizing for size.
6146 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6147 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6148 EVT CVT = Ld.getValueType();
6149 assert(!CVT.isVector() && "Must not broadcast a vector type");
6151 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6152 // For size optimization, also splat v2f64 and v2i64, and for size opt
6153 // with AVX2, also splat i8 and i16.
6154 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6155 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6156 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6157 const Constant *C = nullptr;
6158 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6159 C = CI->getConstantIntValue();
6160 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6161 C = CF->getConstantFPValue();
6163 assert(C && "Invalid constant type");
6165 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6166 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6167 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6168 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6169 MachinePointerInfo::getConstantPool(),
6170 false, false, false, Alignment);
6172 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6176 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6178 // Handle AVX2 in-register broadcasts.
6179 if (!IsLoad && Subtarget->hasInt256() &&
6180 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6181 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6183 // The scalar source must be a normal load.
6187 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6188 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6190 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6191 // double since there is no vbroadcastsd xmm
6192 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6193 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6194 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6197 // Unsupported broadcast.
6201 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6202 /// underlying vector and index.
6204 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6206 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6208 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6209 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6212 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6214 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6216 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6217 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6220 // In this case the vector is the extract_subvector expression and the index
6221 // is 2, as specified by the shuffle.
6222 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6223 SDValue ShuffleVec = SVOp->getOperand(0);
6224 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6225 assert(ShuffleVecVT.getVectorElementType() ==
6226 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6228 int ShuffleIdx = SVOp->getMaskElt(Idx);
6229 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6230 ExtractedFromVec = ShuffleVec;
6236 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6237 MVT VT = Op.getSimpleValueType();
6239 // Skip if insert_vec_elt is not supported.
6240 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6241 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6245 unsigned NumElems = Op.getNumOperands();
6249 SmallVector<unsigned, 4> InsertIndices;
6250 SmallVector<int, 8> Mask(NumElems, -1);
6252 for (unsigned i = 0; i != NumElems; ++i) {
6253 unsigned Opc = Op.getOperand(i).getOpcode();
6255 if (Opc == ISD::UNDEF)
6258 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6259 // Quit if more than 1 elements need inserting.
6260 if (InsertIndices.size() > 1)
6263 InsertIndices.push_back(i);
6267 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6268 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6269 // Quit if non-constant index.
6270 if (!isa<ConstantSDNode>(ExtIdx))
6272 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6274 // Quit if extracted from vector of different type.
6275 if (ExtractedFromVec.getValueType() != VT)
6278 if (!VecIn1.getNode())
6279 VecIn1 = ExtractedFromVec;
6280 else if (VecIn1 != ExtractedFromVec) {
6281 if (!VecIn2.getNode())
6282 VecIn2 = ExtractedFromVec;
6283 else if (VecIn2 != ExtractedFromVec)
6284 // Quit if more than 2 vectors to shuffle
6288 if (ExtractedFromVec == VecIn1)
6290 else if (ExtractedFromVec == VecIn2)
6291 Mask[i] = Idx + NumElems;
6294 if (!VecIn1.getNode())
6297 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6298 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6299 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6300 unsigned Idx = InsertIndices[i];
6301 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6302 DAG.getIntPtrConstant(Idx));
6308 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6310 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6312 MVT VT = Op.getSimpleValueType();
6313 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6314 "Unexpected type in LowerBUILD_VECTORvXi1!");
6317 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6318 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6319 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6320 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6323 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6324 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6325 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6326 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6329 bool AllContants = true;
6330 uint64_t Immediate = 0;
6331 int NonConstIdx = -1;
6332 bool IsSplat = true;
6333 unsigned NumNonConsts = 0;
6334 unsigned NumConsts = 0;
6335 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6336 SDValue In = Op.getOperand(idx);
6337 if (In.getOpcode() == ISD::UNDEF)
6339 if (!isa<ConstantSDNode>(In)) {
6340 AllContants = false;
6346 if (cast<ConstantSDNode>(In)->getZExtValue())
6347 Immediate |= (1ULL << idx);
6349 if (In != Op.getOperand(0))
6354 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6355 DAG.getConstant(Immediate, MVT::i16));
6356 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6357 DAG.getIntPtrConstant(0));
6360 if (NumNonConsts == 1 && NonConstIdx != 0) {
6363 SDValue VecAsImm = DAG.getConstant(Immediate,
6364 MVT::getIntegerVT(VT.getSizeInBits()));
6365 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6368 DstVec = DAG.getUNDEF(VT);
6369 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6370 Op.getOperand(NonConstIdx),
6371 DAG.getIntPtrConstant(NonConstIdx));
6373 if (!IsSplat && (NonConstIdx != 0))
6374 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6375 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6378 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6379 DAG.getConstant(-1, SelectVT),
6380 DAG.getConstant(0, SelectVT));
6382 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6383 DAG.getConstant((Immediate | 1), SelectVT),
6384 DAG.getConstant(Immediate, SelectVT));
6385 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6388 /// \brief Return true if \p N implements a horizontal binop and return the
6389 /// operands for the horizontal binop into V0 and V1.
6391 /// This is a helper function of PerformBUILD_VECTORCombine.
6392 /// This function checks that the build_vector \p N in input implements a
6393 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6394 /// operation to match.
6395 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6396 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6397 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6400 /// This function only analyzes elements of \p N whose indices are
6401 /// in range [BaseIdx, LastIdx).
6402 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6404 unsigned BaseIdx, unsigned LastIdx,
6405 SDValue &V0, SDValue &V1) {
6406 EVT VT = N->getValueType(0);
6408 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6409 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6410 "Invalid Vector in input!");
6412 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6413 bool CanFold = true;
6414 unsigned ExpectedVExtractIdx = BaseIdx;
6415 unsigned NumElts = LastIdx - BaseIdx;
6416 V0 = DAG.getUNDEF(VT);
6417 V1 = DAG.getUNDEF(VT);
6419 // Check if N implements a horizontal binop.
6420 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6421 SDValue Op = N->getOperand(i + BaseIdx);
6424 if (Op->getOpcode() == ISD::UNDEF) {
6425 // Update the expected vector extract index.
6426 if (i * 2 == NumElts)
6427 ExpectedVExtractIdx = BaseIdx;
6428 ExpectedVExtractIdx += 2;
6432 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6437 SDValue Op0 = Op.getOperand(0);
6438 SDValue Op1 = Op.getOperand(1);
6440 // Try to match the following pattern:
6441 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6442 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6443 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6444 Op0.getOperand(0) == Op1.getOperand(0) &&
6445 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6446 isa<ConstantSDNode>(Op1.getOperand(1)));
6450 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6451 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6453 if (i * 2 < NumElts) {
6454 if (V0.getOpcode() == ISD::UNDEF)
6455 V0 = Op0.getOperand(0);
6457 if (V1.getOpcode() == ISD::UNDEF)
6458 V1 = Op0.getOperand(0);
6459 if (i * 2 == NumElts)
6460 ExpectedVExtractIdx = BaseIdx;
6463 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6464 if (I0 == ExpectedVExtractIdx)
6465 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6466 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6467 // Try to match the following dag sequence:
6468 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6469 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6473 ExpectedVExtractIdx += 2;
6479 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6480 /// a concat_vector.
6482 /// This is a helper function of PerformBUILD_VECTORCombine.
6483 /// This function expects two 256-bit vectors called V0 and V1.
6484 /// At first, each vector is split into two separate 128-bit vectors.
6485 /// Then, the resulting 128-bit vectors are used to implement two
6486 /// horizontal binary operations.
6488 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6490 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6491 /// the two new horizontal binop.
6492 /// When Mode is set, the first horizontal binop dag node would take as input
6493 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6494 /// horizontal binop dag node would take as input the lower 128-bit of V1
6495 /// and the upper 128-bit of V1.
6497 /// HADD V0_LO, V0_HI
6498 /// HADD V1_LO, V1_HI
6500 /// Otherwise, the first horizontal binop dag node takes as input the lower
6501 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6502 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6504 /// HADD V0_LO, V1_LO
6505 /// HADD V0_HI, V1_HI
6507 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6508 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6509 /// the upper 128-bits of the result.
6510 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6511 SDLoc DL, SelectionDAG &DAG,
6512 unsigned X86Opcode, bool Mode,
6513 bool isUndefLO, bool isUndefHI) {
6514 EVT VT = V0.getValueType();
6515 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6516 "Invalid nodes in input!");
6518 unsigned NumElts = VT.getVectorNumElements();
6519 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6520 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6521 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6522 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6523 EVT NewVT = V0_LO.getValueType();
6525 SDValue LO = DAG.getUNDEF(NewVT);
6526 SDValue HI = DAG.getUNDEF(NewVT);
6529 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6530 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6531 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6532 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6533 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6535 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6536 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6537 V1_LO->getOpcode() != ISD::UNDEF))
6538 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6540 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6541 V1_HI->getOpcode() != ISD::UNDEF))
6542 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6545 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6548 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6549 /// sequence of 'vadd + vsub + blendi'.
6550 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6551 const X86Subtarget *Subtarget) {
6553 EVT VT = BV->getValueType(0);
6554 unsigned NumElts = VT.getVectorNumElements();
6555 SDValue InVec0 = DAG.getUNDEF(VT);
6556 SDValue InVec1 = DAG.getUNDEF(VT);
6558 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6559 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6561 // Odd-numbered elements in the input build vector are obtained from
6562 // adding two integer/float elements.
6563 // Even-numbered elements in the input build vector are obtained from
6564 // subtracting two integer/float elements.
6565 unsigned ExpectedOpcode = ISD::FSUB;
6566 unsigned NextExpectedOpcode = ISD::FADD;
6567 bool AddFound = false;
6568 bool SubFound = false;
6570 for (unsigned i = 0, e = NumElts; i != e; i++) {
6571 SDValue Op = BV->getOperand(i);
6573 // Skip 'undef' values.
6574 unsigned Opcode = Op.getOpcode();
6575 if (Opcode == ISD::UNDEF) {
6576 std::swap(ExpectedOpcode, NextExpectedOpcode);
6580 // Early exit if we found an unexpected opcode.
6581 if (Opcode != ExpectedOpcode)
6584 SDValue Op0 = Op.getOperand(0);
6585 SDValue Op1 = Op.getOperand(1);
6587 // Try to match the following pattern:
6588 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6589 // Early exit if we cannot match that sequence.
6590 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6591 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6592 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6593 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6594 Op0.getOperand(1) != Op1.getOperand(1))
6597 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6601 // We found a valid add/sub node. Update the information accordingly.
6607 // Update InVec0 and InVec1.
6608 if (InVec0.getOpcode() == ISD::UNDEF)
6609 InVec0 = Op0.getOperand(0);
6610 if (InVec1.getOpcode() == ISD::UNDEF)
6611 InVec1 = Op1.getOperand(0);
6613 // Make sure that operands in input to each add/sub node always
6614 // come from a same pair of vectors.
6615 if (InVec0 != Op0.getOperand(0)) {
6616 if (ExpectedOpcode == ISD::FSUB)
6619 // FADD is commutable. Try to commute the operands
6620 // and then test again.
6621 std::swap(Op0, Op1);
6622 if (InVec0 != Op0.getOperand(0))
6626 if (InVec1 != Op1.getOperand(0))
6629 // Update the pair of expected opcodes.
6630 std::swap(ExpectedOpcode, NextExpectedOpcode);
6633 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6634 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6635 InVec1.getOpcode() != ISD::UNDEF)
6636 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6641 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6642 const X86Subtarget *Subtarget) {
6644 EVT VT = N->getValueType(0);
6645 unsigned NumElts = VT.getVectorNumElements();
6646 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6647 SDValue InVec0, InVec1;
6649 // Try to match an ADDSUB.
6650 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6651 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6652 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6653 if (Value.getNode())
6657 // Try to match horizontal ADD/SUB.
6658 unsigned NumUndefsLO = 0;
6659 unsigned NumUndefsHI = 0;
6660 unsigned Half = NumElts/2;
6662 // Count the number of UNDEF operands in the build_vector in input.
6663 for (unsigned i = 0, e = Half; i != e; ++i)
6664 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6667 for (unsigned i = Half, e = NumElts; i != e; ++i)
6668 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6671 // Early exit if this is either a build_vector of all UNDEFs or all the
6672 // operands but one are UNDEF.
6673 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6676 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6677 // Try to match an SSE3 float HADD/HSUB.
6678 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6679 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6681 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6682 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6683 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6684 // Try to match an SSSE3 integer HADD/HSUB.
6685 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6686 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6688 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6689 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6692 if (!Subtarget->hasAVX())
6695 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6696 // Try to match an AVX horizontal add/sub of packed single/double
6697 // precision floating point values from 256-bit vectors.
6698 SDValue InVec2, InVec3;
6699 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6700 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6701 ((InVec0.getOpcode() == ISD::UNDEF ||
6702 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6703 ((InVec1.getOpcode() == ISD::UNDEF ||
6704 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6705 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6707 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6708 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6709 ((InVec0.getOpcode() == ISD::UNDEF ||
6710 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6711 ((InVec1.getOpcode() == ISD::UNDEF ||
6712 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6713 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6714 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6715 // Try to match an AVX2 horizontal add/sub of signed integers.
6716 SDValue InVec2, InVec3;
6718 bool CanFold = true;
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6721 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6722 ((InVec0.getOpcode() == ISD::UNDEF ||
6723 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6724 ((InVec1.getOpcode() == ISD::UNDEF ||
6725 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6726 X86Opcode = X86ISD::HADD;
6727 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6728 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6729 ((InVec0.getOpcode() == ISD::UNDEF ||
6730 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6731 ((InVec1.getOpcode() == ISD::UNDEF ||
6732 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6733 X86Opcode = X86ISD::HSUB;
6738 // Fold this build_vector into a single horizontal add/sub.
6739 // Do this only if the target has AVX2.
6740 if (Subtarget->hasAVX2())
6741 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6743 // Do not try to expand this build_vector into a pair of horizontal
6744 // add/sub if we can emit a pair of scalar add/sub.
6745 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6748 // Convert this build_vector into a pair of horizontal binop followed by
6750 bool isUndefLO = NumUndefsLO == Half;
6751 bool isUndefHI = NumUndefsHI == Half;
6752 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6753 isUndefLO, isUndefHI);
6757 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6758 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6760 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6761 X86Opcode = X86ISD::HADD;
6762 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6763 X86Opcode = X86ISD::HSUB;
6764 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6765 X86Opcode = X86ISD::FHADD;
6766 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6767 X86Opcode = X86ISD::FHSUB;
6771 // Don't try to expand this build_vector into a pair of horizontal add/sub
6772 // if we can simply emit a pair of scalar add/sub.
6773 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6776 // Convert this build_vector into two horizontal add/sub followed by
6778 bool isUndefLO = NumUndefsLO == Half;
6779 bool isUndefHI = NumUndefsHI == Half;
6780 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6781 isUndefLO, isUndefHI);
6788 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6791 MVT VT = Op.getSimpleValueType();
6792 MVT ExtVT = VT.getVectorElementType();
6793 unsigned NumElems = Op.getNumOperands();
6795 // Generate vectors for predicate vectors.
6796 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6797 return LowerBUILD_VECTORvXi1(Op, DAG);
6799 // Vectors containing all zeros can be matched by pxor and xorps later
6800 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6801 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6802 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6803 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6806 return getZeroVector(VT, Subtarget, DAG, dl);
6809 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6810 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6811 // vpcmpeqd on 256-bit vectors.
6812 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6813 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6816 if (!VT.is512BitVector())
6817 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6820 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6821 if (Broadcast.getNode())
6824 unsigned EVTBits = ExtVT.getSizeInBits();
6826 unsigned NumZero = 0;
6827 unsigned NumNonZero = 0;
6828 unsigned NonZeros = 0;
6829 bool IsAllConstants = true;
6830 SmallSet<SDValue, 8> Values;
6831 for (unsigned i = 0; i < NumElems; ++i) {
6832 SDValue Elt = Op.getOperand(i);
6833 if (Elt.getOpcode() == ISD::UNDEF)
6836 if (Elt.getOpcode() != ISD::Constant &&
6837 Elt.getOpcode() != ISD::ConstantFP)
6838 IsAllConstants = false;
6839 if (X86::isZeroNode(Elt))
6842 NonZeros |= (1 << i);
6847 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6848 if (NumNonZero == 0)
6849 return DAG.getUNDEF(VT);
6851 // Special case for single non-zero, non-undef, element.
6852 if (NumNonZero == 1) {
6853 unsigned Idx = countTrailingZeros(NonZeros);
6854 SDValue Item = Op.getOperand(Idx);
6856 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6857 // the value are obviously zero, truncate the value to i32 and do the
6858 // insertion that way. Only do this if the value is non-constant or if the
6859 // value is a constant being inserted into element 0. It is cheaper to do
6860 // a constant pool load than it is to do a movd + shuffle.
6861 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6862 (!IsAllConstants || Idx == 0)) {
6863 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6865 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6866 EVT VecVT = MVT::v4i32;
6867 unsigned VecElts = 4;
6869 // Truncate the value (which may itself be a constant) to i32, and
6870 // convert it to a vector with movd (S2V+shuffle to zero extend).
6871 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6874 // If using the new shuffle lowering, just directly insert this.
6875 if (ExperimentalVectorShuffleLowering)
6877 ISD::BITCAST, dl, VT,
6878 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6880 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6882 // Now we have our 32-bit value zero extended in the low element of
6883 // a vector. If Idx != 0, swizzle it into place.
6885 SmallVector<int, 4> Mask;
6886 Mask.push_back(Idx);
6887 for (unsigned i = 1; i != VecElts; ++i)
6889 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6892 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6896 // If we have a constant or non-constant insertion into the low element of
6897 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6898 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6899 // depending on what the source datatype is.
6902 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6904 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6905 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6906 if (VT.is256BitVector() || VT.is512BitVector()) {
6907 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6908 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6909 Item, DAG.getIntPtrConstant(0));
6911 assert(VT.is128BitVector() && "Expected an SSE value type!");
6912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6914 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6917 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6918 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6919 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6920 if (VT.is256BitVector()) {
6921 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6922 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6924 assert(VT.is128BitVector() && "Expected an SSE value type!");
6925 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6927 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6931 // Is it a vector logical left shift?
6932 if (NumElems == 2 && Idx == 1 &&
6933 X86::isZeroNode(Op.getOperand(0)) &&
6934 !X86::isZeroNode(Op.getOperand(1))) {
6935 unsigned NumBits = VT.getSizeInBits();
6936 return getVShift(true, VT,
6937 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6938 VT, Op.getOperand(1)),
6939 NumBits/2, DAG, *this, dl);
6942 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6945 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6946 // is a non-constant being inserted into an element other than the low one,
6947 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6948 // movd/movss) to move this into the low element, then shuffle it into
6950 if (EVTBits == 32) {
6951 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6953 // If using the new shuffle lowering, just directly insert this.
6954 if (ExperimentalVectorShuffleLowering)
6955 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6957 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6958 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6959 SmallVector<int, 8> MaskVec;
6960 for (unsigned i = 0; i != NumElems; ++i)
6961 MaskVec.push_back(i == Idx ? 0 : 1);
6962 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6966 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6967 if (Values.size() == 1) {
6968 if (EVTBits == 32) {
6969 // Instead of a shuffle like this:
6970 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6971 // Check if it's possible to issue this instead.
6972 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6973 unsigned Idx = countTrailingZeros(NonZeros);
6974 SDValue Item = Op.getOperand(Idx);
6975 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6976 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6981 // A vector full of immediates; various special cases are already
6982 // handled, so this is best done with a single constant-pool load.
6986 // For AVX-length vectors, build the individual 128-bit pieces and use
6987 // shuffles to put them in place.
6988 if (VT.is256BitVector() || VT.is512BitVector()) {
6989 SmallVector<SDValue, 64> V;
6990 for (unsigned i = 0; i != NumElems; ++i)
6991 V.push_back(Op.getOperand(i));
6993 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6995 // Build both the lower and upper subvector.
6996 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6997 makeArrayRef(&V[0], NumElems/2));
6998 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6999 makeArrayRef(&V[NumElems / 2], NumElems/2));
7001 // Recreate the wider vector with the lower and upper part.
7002 if (VT.is256BitVector())
7003 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7004 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7007 // Let legalizer expand 2-wide build_vectors.
7008 if (EVTBits == 64) {
7009 if (NumNonZero == 1) {
7010 // One half is zero or undef.
7011 unsigned Idx = countTrailingZeros(NonZeros);
7012 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7013 Op.getOperand(Idx));
7014 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7019 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7020 if (EVTBits == 8 && NumElems == 16) {
7021 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7023 if (V.getNode()) return V;
7026 if (EVTBits == 16 && NumElems == 8) {
7027 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7029 if (V.getNode()) return V;
7032 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7033 if (EVTBits == 32 && NumElems == 4) {
7034 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7039 // If element VT is == 32 bits, turn it into a number of shuffles.
7040 SmallVector<SDValue, 8> V(NumElems);
7041 if (NumElems == 4 && NumZero > 0) {
7042 for (unsigned i = 0; i < 4; ++i) {
7043 bool isZero = !(NonZeros & (1 << i));
7045 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7047 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7050 for (unsigned i = 0; i < 2; ++i) {
7051 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7054 V[i] = V[i*2]; // Must be a zero vector.
7057 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7060 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7063 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7068 bool Reverse1 = (NonZeros & 0x3) == 2;
7069 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7073 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7074 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7076 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7079 if (Values.size() > 1 && VT.is128BitVector()) {
7080 // Check for a build vector of consecutive loads.
7081 for (unsigned i = 0; i < NumElems; ++i)
7082 V[i] = Op.getOperand(i);
7084 // Check for elements which are consecutive loads.
7085 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7089 // Check for a build vector from mostly shuffle plus few inserting.
7090 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7094 // For SSE 4.1, use insertps to put the high elements into the low element.
7095 if (getSubtarget()->hasSSE41()) {
7097 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7098 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7100 Result = DAG.getUNDEF(VT);
7102 for (unsigned i = 1; i < NumElems; ++i) {
7103 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7104 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7105 Op.getOperand(i), DAG.getIntPtrConstant(i));
7110 // Otherwise, expand into a number of unpckl*, start by extending each of
7111 // our (non-undef) elements to the full vector width with the element in the
7112 // bottom slot of the vector (which generates no code for SSE).
7113 for (unsigned i = 0; i < NumElems; ++i) {
7114 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7115 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7117 V[i] = DAG.getUNDEF(VT);
7120 // Next, we iteratively mix elements, e.g. for v4f32:
7121 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7122 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7123 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7124 unsigned EltStride = NumElems >> 1;
7125 while (EltStride != 0) {
7126 for (unsigned i = 0; i < EltStride; ++i) {
7127 // If V[i+EltStride] is undef and this is the first round of mixing,
7128 // then it is safe to just drop this shuffle: V[i] is already in the
7129 // right place, the one element (since it's the first round) being
7130 // inserted as undef can be dropped. This isn't safe for successive
7131 // rounds because they will permute elements within both vectors.
7132 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7133 EltStride == NumElems/2)
7136 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7145 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7146 // to create 256-bit vectors from two other 128-bit ones.
7147 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7149 MVT ResVT = Op.getSimpleValueType();
7151 assert((ResVT.is256BitVector() ||
7152 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7154 SDValue V1 = Op.getOperand(0);
7155 SDValue V2 = Op.getOperand(1);
7156 unsigned NumElems = ResVT.getVectorNumElements();
7157 if(ResVT.is256BitVector())
7158 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7160 if (Op.getNumOperands() == 4) {
7161 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7162 ResVT.getVectorNumElements()/2);
7163 SDValue V3 = Op.getOperand(2);
7164 SDValue V4 = Op.getOperand(3);
7165 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7166 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7168 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7171 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7172 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7173 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7174 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7175 Op.getNumOperands() == 4)));
7177 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7178 // from two other 128-bit ones.
7180 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7181 return LowerAVXCONCAT_VECTORS(Op, DAG);
7185 //===----------------------------------------------------------------------===//
7186 // Vector shuffle lowering
7188 // This is an experimental code path for lowering vector shuffles on x86. It is
7189 // designed to handle arbitrary vector shuffles and blends, gracefully
7190 // degrading performance as necessary. It works hard to recognize idiomatic
7191 // shuffles and lower them to optimal instruction patterns without leaving
7192 // a framework that allows reasonably efficient handling of all vector shuffle
7194 //===----------------------------------------------------------------------===//
7196 /// \brief Tiny helper function to identify a no-op mask.
7198 /// This is a somewhat boring predicate function. It checks whether the mask
7199 /// array input, which is assumed to be a single-input shuffle mask of the kind
7200 /// used by the X86 shuffle instructions (not a fully general
7201 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7202 /// in-place shuffle are 'no-op's.
7203 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7204 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7205 if (Mask[i] != -1 && Mask[i] != i)
7210 /// \brief Helper function to classify a mask as a single-input mask.
7212 /// This isn't a generic single-input test because in the vector shuffle
7213 /// lowering we canonicalize single inputs to be the first input operand. This
7214 /// means we can more quickly test for a single input by only checking whether
7215 /// an input from the second operand exists. We also assume that the size of
7216 /// mask corresponds to the size of the input vectors which isn't true in the
7217 /// fully general case.
7218 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7220 if (M >= (int)Mask.size())
7225 /// \brief Test whether there are elements crossing 128-bit lanes in this
7228 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7229 /// and we routinely test for these.
7230 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7231 int LaneSize = 128 / VT.getScalarSizeInBits();
7232 int Size = Mask.size();
7233 for (int i = 0; i < Size; ++i)
7234 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7239 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7241 /// This checks a shuffle mask to see if it is performing the same
7242 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7243 /// that it is also not lane-crossing. It may however involve a blend from the
7244 /// same lane of a second vector.
7246 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7247 /// non-trivial to compute in the face of undef lanes. The representation is
7248 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7249 /// entries from both V1 and V2 inputs to the wider mask.
7251 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7252 SmallVectorImpl<int> &RepeatedMask) {
7253 int LaneSize = 128 / VT.getScalarSizeInBits();
7254 RepeatedMask.resize(LaneSize, -1);
7255 int Size = Mask.size();
7256 for (int i = 0; i < Size; ++i) {
7259 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7260 // This entry crosses lanes, so there is no way to model this shuffle.
7263 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7264 if (RepeatedMask[i % LaneSize] == -1)
7265 // This is the first non-undef entry in this slot of a 128-bit lane.
7266 RepeatedMask[i % LaneSize] =
7267 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7268 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7269 // Found a mismatch with the repeated mask.
7275 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7276 // 2013 will allow us to use it as a non-type template parameter.
7279 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7281 /// See its documentation for details.
7282 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7283 if (Mask.size() != Args.size())
7285 for (int i = 0, e = Mask.size(); i < e; ++i) {
7286 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7287 if (Mask[i] != -1 && Mask[i] != *Args[i])
7295 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7298 /// This is a fast way to test a shuffle mask against a fixed pattern:
7300 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7302 /// It returns true if the mask is exactly as wide as the argument list, and
7303 /// each element of the mask is either -1 (signifying undef) or the value given
7304 /// in the argument.
7305 static const VariadicFunction1<
7306 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7308 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7310 /// This helper function produces an 8-bit shuffle immediate corresponding to
7311 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7312 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7315 /// NB: We rely heavily on "undef" masks preserving the input lane.
7316 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7317 SelectionDAG &DAG) {
7318 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7319 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7320 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7321 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7322 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7325 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7326 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7327 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7328 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7329 return DAG.getConstant(Imm, MVT::i8);
7332 /// \brief Try to emit a blend instruction for a shuffle.
7334 /// This doesn't do any checks for the availability of instructions for blending
7335 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7336 /// be matched in the backend with the type given. What it does check for is
7337 /// that the shuffle mask is in fact a blend.
7338 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7339 SDValue V2, ArrayRef<int> Mask,
7340 const X86Subtarget *Subtarget,
7341 SelectionDAG &DAG) {
7343 unsigned BlendMask = 0;
7344 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7345 if (Mask[i] >= Size) {
7346 if (Mask[i] != i + Size)
7347 return SDValue(); // Shuffled V2 input!
7348 BlendMask |= 1u << i;
7351 if (Mask[i] >= 0 && Mask[i] != i)
7352 return SDValue(); // Shuffled V1 input!
7354 switch (VT.SimpleTy) {
7359 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7360 DAG.getConstant(BlendMask, MVT::i8));
7364 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7368 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7369 // that instruction.
7370 if (Subtarget->hasAVX2()) {
7371 // Scale the blend by the number of 32-bit dwords per element.
7372 int Scale = VT.getScalarSizeInBits() / 32;
7374 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7375 if (Mask[i] >= Size)
7376 for (int j = 0; j < Scale; ++j)
7377 BlendMask |= 1u << (i * Scale + j);
7379 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7380 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7381 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7382 return DAG.getNode(ISD::BITCAST, DL, VT,
7383 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7384 DAG.getConstant(BlendMask, MVT::i8)));
7388 // For integer shuffles we need to expand the mask and cast the inputs to
7389 // v8i16s prior to blending.
7390 int Scale = 8 / VT.getVectorNumElements();
7392 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7393 if (Mask[i] >= Size)
7394 for (int j = 0; j < Scale; ++j)
7395 BlendMask |= 1u << (i * Scale + j);
7397 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7398 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7399 return DAG.getNode(ISD::BITCAST, DL, VT,
7400 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7401 DAG.getConstant(BlendMask, MVT::i8)));
7405 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7406 SmallVector<int, 8> RepeatedMask;
7407 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7408 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7409 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7411 for (int i = 0; i < 8; ++i)
7412 if (RepeatedMask[i] >= 16)
7413 BlendMask |= 1u << i;
7414 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7415 DAG.getConstant(BlendMask, MVT::i8));
7420 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7421 // Scale the blend by the number of bytes per element.
7422 int Scale = VT.getScalarSizeInBits() / 8;
7423 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7425 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7426 // mix of LLVM's code generator and the x86 backend. We tell the code
7427 // generator that boolean values in the elements of an x86 vector register
7428 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7429 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7430 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7431 // of the element (the remaining are ignored) and 0 in that high bit would
7432 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7433 // the LLVM model for boolean values in vector elements gets the relevant
7434 // bit set, it is set backwards and over constrained relative to x86's
7436 SDValue VSELECTMask[32];
7437 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7438 for (int j = 0; j < Scale; ++j)
7439 VSELECTMask[Scale * i + j] =
7440 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7441 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7443 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7444 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7446 ISD::BITCAST, DL, VT,
7447 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7448 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7453 llvm_unreachable("Not a supported integer vector type!");
7457 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7458 /// unblended shuffles followed by an unshuffled blend.
7460 /// This matches the extremely common pattern for handling combined
7461 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7463 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7467 SelectionDAG &DAG) {
7468 // Shuffle the input elements into the desired positions in V1 and V2 and
7469 // blend them together.
7470 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7471 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7472 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7473 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7474 if (Mask[i] >= 0 && Mask[i] < Size) {
7475 V1Mask[i] = Mask[i];
7477 } else if (Mask[i] >= Size) {
7478 V2Mask[i] = Mask[i] - Size;
7479 BlendMask[i] = i + Size;
7482 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7483 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7484 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7487 /// \brief Try to lower a vector shuffle as a byte rotation.
7489 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7490 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7491 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7492 /// try to generically lower a vector shuffle through such an pattern. It
7493 /// does not check for the profitability of lowering either as PALIGNR or
7494 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7495 /// This matches shuffle vectors that look like:
7497 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7499 /// Essentially it concatenates V1 and V2, shifts right by some number of
7500 /// elements, and takes the low elements as the result. Note that while this is
7501 /// specified as a *right shift* because x86 is little-endian, it is a *left
7502 /// rotate* of the vector lanes.
7504 /// Note that this only handles 128-bit vector widths currently.
7505 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7508 const X86Subtarget *Subtarget,
7509 SelectionDAG &DAG) {
7510 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7512 // We need to detect various ways of spelling a rotation:
7513 // [11, 12, 13, 14, 15, 0, 1, 2]
7514 // [-1, 12, 13, 14, -1, -1, 1, -1]
7515 // [-1, -1, -1, -1, -1, -1, 1, 2]
7516 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7517 // [-1, 4, 5, 6, -1, -1, 9, -1]
7518 // [-1, 4, 5, 6, -1, -1, -1, -1]
7521 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7524 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7526 // Based on the mod-Size value of this mask element determine where
7527 // a rotated vector would have started.
7528 int StartIdx = i - (Mask[i] % Size);
7530 // The identity rotation isn't interesting, stop.
7533 // If we found the tail of a vector the rotation must be the missing
7534 // front. If we found the head of a vector, it must be how much of the head.
7535 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7538 Rotation = CandidateRotation;
7539 else if (Rotation != CandidateRotation)
7540 // The rotations don't match, so we can't match this mask.
7543 // Compute which value this mask is pointing at.
7544 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7546 // Compute which of the two target values this index should be assigned to.
7547 // This reflects whether the high elements are remaining or the low elements
7549 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7551 // Either set up this value if we've not encountered it before, or check
7552 // that it remains consistent.
7555 else if (TargetV != MaskV)
7556 // This may be a rotation, but it pulls from the inputs in some
7557 // unsupported interleaving.
7561 // Check that we successfully analyzed the mask, and normalize the results.
7562 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7563 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7569 assert(VT.getSizeInBits() == 128 &&
7570 "Rotate-based lowering only supports 128-bit lowering!");
7571 assert(Mask.size() <= 16 &&
7572 "Can shuffle at most 16 bytes in a 128-bit vector!");
7574 // The actual rotate instruction rotates bytes, so we need to scale the
7575 // rotation based on how many bytes are in the vector.
7576 int Scale = 16 / Mask.size();
7578 // SSSE3 targets can use the palignr instruction
7579 if (Subtarget->hasSSSE3()) {
7580 // Cast the inputs to v16i8 to match PALIGNR.
7581 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7582 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7584 return DAG.getNode(ISD::BITCAST, DL, VT,
7585 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7586 DAG.getConstant(Rotation * Scale, MVT::i8)));
7589 // Default SSE2 implementation
7590 int LoByteShift = 16 - Rotation * Scale;
7591 int HiByteShift = Rotation * Scale;
7593 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7594 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7595 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7597 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7598 DAG.getConstant(8 * LoByteShift, MVT::i8));
7599 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7600 DAG.getConstant(8 * HiByteShift, MVT::i8));
7601 return DAG.getNode(ISD::BITCAST, DL, VT,
7602 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7605 /// \brief Compute whether each element of a shuffle is zeroable.
7607 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7608 /// Either it is an undef element in the shuffle mask, the element of the input
7609 /// referenced is undef, or the element of the input referenced is known to be
7610 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7611 /// as many lanes with this technique as possible to simplify the remaining
7613 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7614 SDValue V1, SDValue V2) {
7615 SmallBitVector Zeroable(Mask.size(), false);
7617 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7618 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7620 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7622 // Handle the easy cases.
7623 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7628 // If this is an index into a build_vector node, dig out the input value and
7630 SDValue V = M < Size ? V1 : V2;
7631 if (V.getOpcode() != ISD::BUILD_VECTOR)
7634 SDValue Input = V.getOperand(M % Size);
7635 // The UNDEF opcode check really should be dead code here, but not quite
7636 // worth asserting on (it isn't invalid, just unexpected).
7637 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7644 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7646 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7647 /// byte-shift instructions. The mask must consist of a shifted sequential
7648 /// shuffle from one of the input vectors and zeroable elements for the
7649 /// remaining 'shifted in' elements.
7651 /// Note that this only handles 128-bit vector widths currently.
7652 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7653 SDValue V2, ArrayRef<int> Mask,
7654 SelectionDAG &DAG) {
7655 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7657 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7659 int Size = Mask.size();
7660 int Scale = 16 / Size;
7662 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7663 ArrayRef<int> Mask) {
7664 for (int i = StartIndex; i < EndIndex; i++) {
7667 if (i + Base != Mask[i] - MaskOffset)
7673 for (int Shift = 1; Shift < Size; Shift++) {
7674 int ByteShift = Shift * Scale;
7676 // PSRLDQ : (little-endian) right byte shift
7677 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7678 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7679 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7680 bool ZeroableRight = true;
7681 for (int i = Size - Shift; i < Size; i++) {
7682 ZeroableRight &= Zeroable[i];
7685 if (ZeroableRight) {
7686 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7687 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7689 if (ValidShiftRight1 || ValidShiftRight2) {
7690 // Cast the inputs to v2i64 to match PSRLDQ.
7691 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7692 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7693 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7694 DAG.getConstant(ByteShift * 8, MVT::i8));
7695 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7699 // PSLLDQ : (little-endian) left byte shift
7700 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7701 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7702 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7703 bool ZeroableLeft = true;
7704 for (int i = 0; i < Shift; i++) {
7705 ZeroableLeft &= Zeroable[i];
7709 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7710 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7712 if (ValidShiftLeft1 || ValidShiftLeft2) {
7713 // Cast the inputs to v2i64 to match PSLLDQ.
7714 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7715 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7716 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7717 DAG.getConstant(ByteShift * 8, MVT::i8));
7718 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7726 /// \brief Lower a vector shuffle as a zero or any extension.
7728 /// Given a specific number of elements, element bit width, and extension
7729 /// stride, produce either a zero or any extension based on the available
7730 /// features of the subtarget.
7731 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7732 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7733 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7734 assert(Scale > 1 && "Need a scale to extend.");
7735 int EltBits = VT.getSizeInBits() / NumElements;
7736 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7737 "Only 8, 16, and 32 bit elements can be extended.");
7738 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7740 // Found a valid zext mask! Try various lowering strategies based on the
7741 // input type and available ISA extensions.
7742 if (Subtarget->hasSSE41()) {
7743 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7744 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7745 NumElements / Scale);
7746 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7747 return DAG.getNode(ISD::BITCAST, DL, VT,
7748 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7751 // For any extends we can cheat for larger element sizes and use shuffle
7752 // instructions that can fold with a load and/or copy.
7753 if (AnyExt && EltBits == 32) {
7754 int PSHUFDMask[4] = {0, -1, 1, -1};
7756 ISD::BITCAST, DL, VT,
7757 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7758 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7759 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7761 if (AnyExt && EltBits == 16 && Scale > 2) {
7762 int PSHUFDMask[4] = {0, -1, 0, -1};
7763 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7764 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7765 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7766 int PSHUFHWMask[4] = {1, -1, -1, -1};
7768 ISD::BITCAST, DL, VT,
7769 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7770 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7771 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7774 // If this would require more than 2 unpack instructions to expand, use
7775 // pshufb when available. We can only use more than 2 unpack instructions
7776 // when zero extending i8 elements which also makes it easier to use pshufb.
7777 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7778 assert(NumElements == 16 && "Unexpected byte vector width!");
7779 SDValue PSHUFBMask[16];
7780 for (int i = 0; i < 16; ++i)
7782 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7783 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7784 return DAG.getNode(ISD::BITCAST, DL, VT,
7785 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7786 DAG.getNode(ISD::BUILD_VECTOR, DL,
7787 MVT::v16i8, PSHUFBMask)));
7790 // Otherwise emit a sequence of unpacks.
7792 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7793 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7794 : getZeroVector(InputVT, Subtarget, DAG, DL);
7795 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7796 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7800 } while (Scale > 1);
7801 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7804 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7806 /// This routine will try to do everything in its power to cleverly lower
7807 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7808 /// check for the profitability of this lowering, it tries to aggressively
7809 /// match this pattern. It will use all of the micro-architectural details it
7810 /// can to emit an efficient lowering. It handles both blends with all-zero
7811 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7812 /// masking out later).
7814 /// The reason we have dedicated lowering for zext-style shuffles is that they
7815 /// are both incredibly common and often quite performance sensitive.
7816 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7817 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7818 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7819 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7821 int Bits = VT.getSizeInBits();
7822 int NumElements = Mask.size();
7824 // Define a helper function to check a particular ext-scale and lower to it if
7826 auto Lower = [&](int Scale) -> SDValue {
7829 for (int i = 0; i < NumElements; ++i) {
7831 continue; // Valid anywhere but doesn't tell us anything.
7832 if (i % Scale != 0) {
7833 // Each of the extend elements needs to be zeroable.
7837 // We no lorger are in the anyext case.
7842 // Each of the base elements needs to be consecutive indices into the
7843 // same input vector.
7844 SDValue V = Mask[i] < NumElements ? V1 : V2;
7847 else if (InputV != V)
7848 return SDValue(); // Flip-flopping inputs.
7850 if (Mask[i] % NumElements != i / Scale)
7851 return SDValue(); // Non-consecutive strided elemenst.
7854 // If we fail to find an input, we have a zero-shuffle which should always
7855 // have already been handled.
7856 // FIXME: Maybe handle this here in case during blending we end up with one?
7860 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7861 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7864 // The widest scale possible for extending is to a 64-bit integer.
7865 assert(Bits % 64 == 0 &&
7866 "The number of bits in a vector must be divisible by 64 on x86!");
7867 int NumExtElements = Bits / 64;
7869 // Each iteration, try extending the elements half as much, but into twice as
7871 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7872 assert(NumElements % NumExtElements == 0 &&
7873 "The input vector size must be divisble by the extended size.");
7874 if (SDValue V = Lower(NumElements / NumExtElements))
7878 // No viable ext lowering found.
7882 /// \brief Try to get a scalar value for a specific element of a vector.
7884 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7885 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7886 SelectionDAG &DAG) {
7887 MVT VT = V.getSimpleValueType();
7888 MVT EltVT = VT.getVectorElementType();
7889 while (V.getOpcode() == ISD::BITCAST)
7890 V = V.getOperand(0);
7891 // If the bitcasts shift the element size, we can't extract an equivalent
7893 MVT NewVT = V.getSimpleValueType();
7894 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7897 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7898 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7899 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7904 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7906 /// This is particularly important because the set of instructions varies
7907 /// significantly based on whether the operand is a load or not.
7908 static bool isShuffleFoldableLoad(SDValue V) {
7909 while (V.getOpcode() == ISD::BITCAST)
7910 V = V.getOperand(0);
7912 return ISD::isNON_EXTLoad(V.getNode());
7915 /// \brief Try to lower insertion of a single element into a zero vector.
7917 /// This is a common pattern that we have especially efficient patterns to lower
7918 /// across all subtarget feature sets.
7919 static SDValue lowerVectorShuffleAsElementInsertion(
7920 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7921 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7922 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7924 MVT EltVT = VT.getVectorElementType();
7926 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7927 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7929 bool IsV1Zeroable = true;
7930 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7931 if (i != V2Index && !Zeroable[i]) {
7932 IsV1Zeroable = false;
7936 // Check for a single input from a SCALAR_TO_VECTOR node.
7937 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7938 // all the smarts here sunk into that routine. However, the current
7939 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7940 // vector shuffle lowering is dead.
7941 if (SDValue V2S = getScalarValueForVectorElement(
7942 V2, Mask[V2Index] - Mask.size(), DAG)) {
7943 // We need to zext the scalar if it is smaller than an i32.
7944 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7945 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7946 // Using zext to expand a narrow element won't work for non-zero
7951 // Zero-extend directly to i32.
7953 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7955 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7956 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7957 EltVT == MVT::i16) {
7958 // Either not inserting from the low element of the input or the input
7959 // element size is too small to use VZEXT_MOVL to clear the high bits.
7963 if (!IsV1Zeroable) {
7964 // If V1 can't be treated as a zero vector we have fewer options to lower
7965 // this. We can't support integer vectors or non-zero targets cheaply, and
7966 // the V1 elements can't be permuted in any way.
7967 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7968 if (!VT.isFloatingPoint() || V2Index != 0)
7970 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7971 V1Mask[V2Index] = -1;
7972 if (!isNoopShuffleMask(V1Mask))
7974 // This is essentially a special case blend operation, but if we have
7975 // general purpose blend operations, they are always faster. Bail and let
7976 // the rest of the lowering handle these as blends.
7977 if (Subtarget->hasSSE41())
7980 // Otherwise, use MOVSD or MOVSS.
7981 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7982 "Only two types of floating point element types to handle!");
7983 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7987 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7989 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7992 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7993 // the desired position. Otherwise it is more efficient to do a vector
7994 // shift left. We know that we can do a vector shift left because all
7995 // the inputs are zero.
7996 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7997 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7998 V2Shuffle[V2Index] = 0;
7999 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8001 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8003 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8005 V2Index * EltVT.getSizeInBits(),
8006 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8007 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8013 /// \brief Try to lower broadcast of a single element.
8015 /// For convenience, this code also bundles all of the subtarget feature set
8016 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8017 /// a convenient way to factor it out.
8018 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8020 const X86Subtarget *Subtarget,
8021 SelectionDAG &DAG) {
8022 if (!Subtarget->hasAVX())
8024 if (VT.isInteger() && !Subtarget->hasAVX2())
8027 // Check that the mask is a broadcast.
8028 int BroadcastIdx = -1;
8030 if (M >= 0 && BroadcastIdx == -1)
8032 else if (M >= 0 && M != BroadcastIdx)
8035 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8036 "a sorted mask where the broadcast "
8039 // Go up the chain of (vector) values to try and find a scalar load that
8040 // we can combine with the broadcast.
8042 switch (V.getOpcode()) {
8043 case ISD::CONCAT_VECTORS: {
8044 int OperandSize = Mask.size() / V.getNumOperands();
8045 V = V.getOperand(BroadcastIdx / OperandSize);
8046 BroadcastIdx %= OperandSize;
8050 case ISD::INSERT_SUBVECTOR: {
8051 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8052 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8056 int BeginIdx = (int)ConstantIdx->getZExtValue();
8058 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8059 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8060 BroadcastIdx -= BeginIdx;
8071 // Check if this is a broadcast of a scalar. We special case lowering
8072 // for scalars so that we can more effectively fold with loads.
8073 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8074 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8075 V = V.getOperand(BroadcastIdx);
8077 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8079 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8081 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8082 // We can't broadcast from a vector register w/o AVX2, and we can only
8083 // broadcast from the zero-element of a vector register.
8087 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8090 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8092 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8093 /// support for floating point shuffles but not integer shuffles. These
8094 /// instructions will incur a domain crossing penalty on some chips though so
8095 /// it is better to avoid lowering through this for integer vectors where
8097 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8098 const X86Subtarget *Subtarget,
8099 SelectionDAG &DAG) {
8101 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8102 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8103 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8104 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8105 ArrayRef<int> Mask = SVOp->getMask();
8106 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8108 if (isSingleInputShuffleMask(Mask)) {
8109 // Straight shuffle of a single input vector. Simulate this by using the
8110 // single input as both of the "inputs" to this instruction..
8111 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8113 if (Subtarget->hasAVX()) {
8114 // If we have AVX, we can use VPERMILPS which will allow folding a load
8115 // into the shuffle.
8116 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8117 DAG.getConstant(SHUFPDMask, MVT::i8));
8120 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8121 DAG.getConstant(SHUFPDMask, MVT::i8));
8123 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8124 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8126 // Use dedicated unpack instructions for masks that match their pattern.
8127 if (isShuffleEquivalent(Mask, 0, 2))
8128 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8129 if (isShuffleEquivalent(Mask, 1, 3))
8130 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8132 // If we have a single input, insert that into V1 if we can do so cheaply.
8133 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8134 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8135 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8137 // Try inverting the insertion since for v2 masks it is easy to do and we
8138 // can't reliably sort the mask one way or the other.
8139 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8140 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8141 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8142 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8146 // Try to use one of the special instruction patterns to handle two common
8147 // blend patterns if a zero-blend above didn't work.
8148 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8149 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8150 // We can either use a special instruction to load over the low double or
8151 // to move just the low double.
8153 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8155 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8157 if (Subtarget->hasSSE41())
8158 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8162 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8163 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8164 DAG.getConstant(SHUFPDMask, MVT::i8));
8167 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8169 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8170 /// the integer unit to minimize domain crossing penalties. However, for blends
8171 /// it falls back to the floating point shuffle operation with appropriate bit
8173 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8174 const X86Subtarget *Subtarget,
8175 SelectionDAG &DAG) {
8177 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8178 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8179 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8180 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8181 ArrayRef<int> Mask = SVOp->getMask();
8182 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8184 if (isSingleInputShuffleMask(Mask)) {
8185 // Check for being able to broadcast a single element.
8186 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8187 Mask, Subtarget, DAG))
8190 // Straight shuffle of a single input vector. For everything from SSE2
8191 // onward this has a single fast instruction with no scary immediates.
8192 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8193 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8194 int WidenedMask[4] = {
8195 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8196 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8198 ISD::BITCAST, DL, MVT::v2i64,
8199 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8200 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8203 // If we have a single input from V2 insert that into V1 if we can do so
8205 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8206 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8207 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8209 // Try inverting the insertion since for v2 masks it is easy to do and we
8210 // can't reliably sort the mask one way or the other.
8211 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8212 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8213 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8214 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8218 // Use dedicated unpack instructions for masks that match their pattern.
8219 if (isShuffleEquivalent(Mask, 0, 2))
8220 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8221 if (isShuffleEquivalent(Mask, 1, 3))
8222 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8224 if (Subtarget->hasSSE41())
8225 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8229 // Try to use byte shift instructions.
8230 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8231 DL, MVT::v2i64, V1, V2, Mask, DAG))
8234 // Try to use byte rotation instructions.
8235 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8236 if (Subtarget->hasSSSE3())
8237 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8238 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8241 // We implement this with SHUFPD which is pretty lame because it will likely
8242 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8243 // However, all the alternatives are still more cycles and newer chips don't
8244 // have this problem. It would be really nice if x86 had better shuffles here.
8245 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8246 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8247 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8248 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8251 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8253 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8254 /// It makes no assumptions about whether this is the *best* lowering, it simply
8256 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8257 ArrayRef<int> Mask, SDValue V1,
8258 SDValue V2, SelectionDAG &DAG) {
8259 SDValue LowV = V1, HighV = V2;
8260 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8263 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8265 if (NumV2Elements == 1) {
8267 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8270 // Compute the index adjacent to V2Index and in the same half by toggling
8272 int V2AdjIndex = V2Index ^ 1;
8274 if (Mask[V2AdjIndex] == -1) {
8275 // Handles all the cases where we have a single V2 element and an undef.
8276 // This will only ever happen in the high lanes because we commute the
8277 // vector otherwise.
8279 std::swap(LowV, HighV);
8280 NewMask[V2Index] -= 4;
8282 // Handle the case where the V2 element ends up adjacent to a V1 element.
8283 // To make this work, blend them together as the first step.
8284 int V1Index = V2AdjIndex;
8285 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8286 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8287 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8289 // Now proceed to reconstruct the final blend as we have the necessary
8290 // high or low half formed.
8297 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8298 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8300 } else if (NumV2Elements == 2) {
8301 if (Mask[0] < 4 && Mask[1] < 4) {
8302 // Handle the easy case where we have V1 in the low lanes and V2 in the
8306 } else if (Mask[2] < 4 && Mask[3] < 4) {
8307 // We also handle the reversed case because this utility may get called
8308 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8309 // arrange things in the right direction.
8315 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8316 // trying to place elements directly, just blend them and set up the final
8317 // shuffle to place them.
8319 // The first two blend mask elements are for V1, the second two are for
8321 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8322 Mask[2] < 4 ? Mask[2] : Mask[3],
8323 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8324 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8325 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8326 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8328 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8331 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8332 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8333 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8334 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8337 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8338 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8341 /// \brief Lower 4-lane 32-bit floating point shuffles.
8343 /// Uses instructions exclusively from the floating point unit to minimize
8344 /// domain crossing penalties, as these are sufficient to implement all v4f32
8346 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8347 const X86Subtarget *Subtarget,
8348 SelectionDAG &DAG) {
8350 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8351 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8352 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8353 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8354 ArrayRef<int> Mask = SVOp->getMask();
8355 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8358 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8360 if (NumV2Elements == 0) {
8361 // Check for being able to broadcast a single element.
8362 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8363 Mask, Subtarget, DAG))
8366 if (Subtarget->hasAVX()) {
8367 // If we have AVX, we can use VPERMILPS which will allow folding a load
8368 // into the shuffle.
8369 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8370 getV4X86ShuffleImm8ForMask(Mask, DAG));
8373 // Otherwise, use a straight shuffle of a single input vector. We pass the
8374 // input vector to both operands to simulate this with a SHUFPS.
8375 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8376 getV4X86ShuffleImm8ForMask(Mask, DAG));
8379 // Use dedicated unpack instructions for masks that match their pattern.
8380 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8381 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8382 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8383 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8385 // There are special ways we can lower some single-element blends. However, we
8386 // have custom ways we can lower more complex single-element blends below that
8387 // we defer to if both this and BLENDPS fail to match, so restrict this to
8388 // when the V2 input is targeting element 0 of the mask -- that is the fast
8390 if (NumV2Elements == 1 && Mask[0] >= 4)
8391 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8392 Mask, Subtarget, DAG))
8395 if (Subtarget->hasSSE41())
8396 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8400 // Check for whether we can use INSERTPS to perform the blend. We only use
8401 // INSERTPS when the V1 elements are already in the correct locations
8402 // because otherwise we can just always use two SHUFPS instructions which
8403 // are much smaller to encode than a SHUFPS and an INSERTPS.
8404 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8406 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8409 // When using INSERTPS we can zero any lane of the destination. Collect
8410 // the zero inputs into a mask and drop them from the lanes of V1 which
8411 // actually need to be present as inputs to the INSERTPS.
8412 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8414 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8415 bool InsertNeedsShuffle = false;
8417 for (int i = 0; i < 4; ++i)
8421 } else if (Mask[i] != i) {
8422 InsertNeedsShuffle = true;
8427 // We don't want to use INSERTPS or other insertion techniques if it will
8428 // require shuffling anyways.
8429 if (!InsertNeedsShuffle) {
8430 // If all of V1 is zeroable, replace it with undef.
8431 if ((ZMask | 1 << V2Index) == 0xF)
8432 V1 = DAG.getUNDEF(MVT::v4f32);
8434 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8435 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8437 // Insert the V2 element into the desired position.
8438 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8439 DAG.getConstant(InsertPSMask, MVT::i8));
8443 // Otherwise fall back to a SHUFPS lowering strategy.
8444 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8447 /// \brief Lower 4-lane i32 vector shuffles.
8449 /// We try to handle these with integer-domain shuffles where we can, but for
8450 /// blends we use the floating point domain blend instructions.
8451 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8452 const X86Subtarget *Subtarget,
8453 SelectionDAG &DAG) {
8455 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8456 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8457 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8459 ArrayRef<int> Mask = SVOp->getMask();
8460 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8462 // Whenever we can lower this as a zext, that instruction is strictly faster
8463 // than any alternative. It also allows us to fold memory operands into the
8464 // shuffle in many cases.
8465 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8466 Mask, Subtarget, DAG))
8470 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8472 if (NumV2Elements == 0) {
8473 // Check for being able to broadcast a single element.
8474 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8475 Mask, Subtarget, DAG))
8478 // Straight shuffle of a single input vector. For everything from SSE2
8479 // onward this has a single fast instruction with no scary immediates.
8480 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8481 // but we aren't actually going to use the UNPCK instruction because doing
8482 // so prevents folding a load into this instruction or making a copy.
8483 const int UnpackLoMask[] = {0, 0, 1, 1};
8484 const int UnpackHiMask[] = {2, 2, 3, 3};
8485 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8486 Mask = UnpackLoMask;
8487 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8488 Mask = UnpackHiMask;
8490 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8491 getV4X86ShuffleImm8ForMask(Mask, DAG));
8494 // There are special ways we can lower some single-element blends.
8495 if (NumV2Elements == 1)
8496 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8497 Mask, Subtarget, DAG))
8500 // Use dedicated unpack instructions for masks that match their pattern.
8501 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8502 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8503 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8504 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8506 if (Subtarget->hasSSE41())
8507 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8511 // Try to use byte shift instructions.
8512 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8513 DL, MVT::v4i32, V1, V2, Mask, DAG))
8516 // Try to use byte rotation instructions.
8517 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8518 if (Subtarget->hasSSSE3())
8519 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8520 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8523 // We implement this with SHUFPS because it can blend from two vectors.
8524 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8525 // up the inputs, bypassing domain shift penalties that we would encur if we
8526 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8528 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8529 DAG.getVectorShuffle(
8531 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8532 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8535 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8536 /// shuffle lowering, and the most complex part.
8538 /// The lowering strategy is to try to form pairs of input lanes which are
8539 /// targeted at the same half of the final vector, and then use a dword shuffle
8540 /// to place them onto the right half, and finally unpack the paired lanes into
8541 /// their final position.
8543 /// The exact breakdown of how to form these dword pairs and align them on the
8544 /// correct sides is really tricky. See the comments within the function for
8545 /// more of the details.
8546 static SDValue lowerV8I16SingleInputVectorShuffle(
8547 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8548 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8549 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8550 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8551 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8553 SmallVector<int, 4> LoInputs;
8554 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8555 [](int M) { return M >= 0; });
8556 std::sort(LoInputs.begin(), LoInputs.end());
8557 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8558 SmallVector<int, 4> HiInputs;
8559 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8560 [](int M) { return M >= 0; });
8561 std::sort(HiInputs.begin(), HiInputs.end());
8562 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8564 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8565 int NumHToL = LoInputs.size() - NumLToL;
8567 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8568 int NumHToH = HiInputs.size() - NumLToH;
8569 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8570 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8571 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8572 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8574 // Check for being able to broadcast a single element.
8575 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8576 Mask, Subtarget, DAG))
8579 // Use dedicated unpack instructions for masks that match their pattern.
8580 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8581 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8582 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8583 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8585 // Try to use byte shift instructions.
8586 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8587 DL, MVT::v8i16, V, V, Mask, DAG))
8590 // Try to use byte rotation instructions.
8591 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8592 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8595 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8596 // such inputs we can swap two of the dwords across the half mark and end up
8597 // with <=2 inputs to each half in each half. Once there, we can fall through
8598 // to the generic code below. For example:
8600 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8601 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8603 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8604 // and an existing 2-into-2 on the other half. In this case we may have to
8605 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8606 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8607 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8608 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8609 // half than the one we target for fixing) will be fixed when we re-enter this
8610 // path. We will also combine away any sequence of PSHUFD instructions that
8611 // result into a single instruction. Here is an example of the tricky case:
8613 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8614 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8616 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8618 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8619 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8621 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8622 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8624 // The result is fine to be handled by the generic logic.
8625 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8626 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8627 int AOffset, int BOffset) {
8628 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8629 "Must call this with A having 3 or 1 inputs from the A half.");
8630 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8631 "Must call this with B having 1 or 3 inputs from the B half.");
8632 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8633 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8635 // Compute the index of dword with only one word among the three inputs in
8636 // a half by taking the sum of the half with three inputs and subtracting
8637 // the sum of the actual three inputs. The difference is the remaining
8640 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8641 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8642 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8643 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8644 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8645 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8646 int TripleNonInputIdx =
8647 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8648 TripleDWord = TripleNonInputIdx / 2;
8650 // We use xor with one to compute the adjacent DWord to whichever one the
8652 OneInputDWord = (OneInput / 2) ^ 1;
8654 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8655 // and BToA inputs. If there is also such a problem with the BToB and AToB
8656 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8657 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8658 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8659 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8660 // Compute how many inputs will be flipped by swapping these DWords. We
8662 // to balance this to ensure we don't form a 3-1 shuffle in the other
8664 int NumFlippedAToBInputs =
8665 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8666 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8667 int NumFlippedBToBInputs =
8668 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8669 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8670 if ((NumFlippedAToBInputs == 1 &&
8671 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8672 (NumFlippedBToBInputs == 1 &&
8673 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8674 // We choose whether to fix the A half or B half based on whether that
8675 // half has zero flipped inputs. At zero, we may not be able to fix it
8676 // with that half. We also bias towards fixing the B half because that
8677 // will more commonly be the high half, and we have to bias one way.
8678 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8679 ArrayRef<int> Inputs) {
8680 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8681 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8682 PinnedIdx ^ 1) != Inputs.end();
8683 // Determine whether the free index is in the flipped dword or the
8684 // unflipped dword based on where the pinned index is. We use this bit
8685 // in an xor to conditionally select the adjacent dword.
8686 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8687 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8688 FixFreeIdx) != Inputs.end();
8689 if (IsFixIdxInput == IsFixFreeIdxInput)
8691 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8692 FixFreeIdx) != Inputs.end();
8693 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8694 "We need to be changing the number of flipped inputs!");
8695 int PSHUFHalfMask[] = {0, 1, 2, 3};
8696 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8697 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8699 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8702 if (M != -1 && M == FixIdx)
8704 else if (M != -1 && M == FixFreeIdx)
8707 if (NumFlippedBToBInputs != 0) {
8709 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8710 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8712 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8714 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8715 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8720 int PSHUFDMask[] = {0, 1, 2, 3};
8721 PSHUFDMask[ADWord] = BDWord;
8722 PSHUFDMask[BDWord] = ADWord;
8723 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8724 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8725 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8726 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8728 // Adjust the mask to match the new locations of A and B.
8730 if (M != -1 && M/2 == ADWord)
8731 M = 2 * BDWord + M % 2;
8732 else if (M != -1 && M/2 == BDWord)
8733 M = 2 * ADWord + M % 2;
8735 // Recurse back into this routine to re-compute state now that this isn't
8736 // a 3 and 1 problem.
8737 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8740 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8741 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8742 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8743 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8745 // At this point there are at most two inputs to the low and high halves from
8746 // each half. That means the inputs can always be grouped into dwords and
8747 // those dwords can then be moved to the correct half with a dword shuffle.
8748 // We use at most one low and one high word shuffle to collect these paired
8749 // inputs into dwords, and finally a dword shuffle to place them.
8750 int PSHUFLMask[4] = {-1, -1, -1, -1};
8751 int PSHUFHMask[4] = {-1, -1, -1, -1};
8752 int PSHUFDMask[4] = {-1, -1, -1, -1};
8754 // First fix the masks for all the inputs that are staying in their
8755 // original halves. This will then dictate the targets of the cross-half
8757 auto fixInPlaceInputs =
8758 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8759 MutableArrayRef<int> SourceHalfMask,
8760 MutableArrayRef<int> HalfMask, int HalfOffset) {
8761 if (InPlaceInputs.empty())
8763 if (InPlaceInputs.size() == 1) {
8764 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8765 InPlaceInputs[0] - HalfOffset;
8766 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8769 if (IncomingInputs.empty()) {
8770 // Just fix all of the in place inputs.
8771 for (int Input : InPlaceInputs) {
8772 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8773 PSHUFDMask[Input / 2] = Input / 2;
8778 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8779 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8780 InPlaceInputs[0] - HalfOffset;
8781 // Put the second input next to the first so that they are packed into
8782 // a dword. We find the adjacent index by toggling the low bit.
8783 int AdjIndex = InPlaceInputs[0] ^ 1;
8784 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8785 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8786 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8788 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8789 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8791 // Now gather the cross-half inputs and place them into a free dword of
8792 // their target half.
8793 // FIXME: This operation could almost certainly be simplified dramatically to
8794 // look more like the 3-1 fixing operation.
8795 auto moveInputsToRightHalf = [&PSHUFDMask](
8796 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8797 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8798 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8800 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8801 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8803 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8805 int LowWord = Word & ~1;
8806 int HighWord = Word | 1;
8807 return isWordClobbered(SourceHalfMask, LowWord) ||
8808 isWordClobbered(SourceHalfMask, HighWord);
8811 if (IncomingInputs.empty())
8814 if (ExistingInputs.empty()) {
8815 // Map any dwords with inputs from them into the right half.
8816 for (int Input : IncomingInputs) {
8817 // If the source half mask maps over the inputs, turn those into
8818 // swaps and use the swapped lane.
8819 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8820 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8821 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8822 Input - SourceOffset;
8823 // We have to swap the uses in our half mask in one sweep.
8824 for (int &M : HalfMask)
8825 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8827 else if (M == Input)
8828 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8830 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8831 Input - SourceOffset &&
8832 "Previous placement doesn't match!");
8834 // Note that this correctly re-maps both when we do a swap and when
8835 // we observe the other side of the swap above. We rely on that to
8836 // avoid swapping the members of the input list directly.
8837 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8840 // Map the input's dword into the correct half.
8841 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8842 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8844 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8846 "Previous placement doesn't match!");
8849 // And just directly shift any other-half mask elements to be same-half
8850 // as we will have mirrored the dword containing the element into the
8851 // same position within that half.
8852 for (int &M : HalfMask)
8853 if (M >= SourceOffset && M < SourceOffset + 4) {
8854 M = M - SourceOffset + DestOffset;
8855 assert(M >= 0 && "This should never wrap below zero!");
8860 // Ensure we have the input in a viable dword of its current half. This
8861 // is particularly tricky because the original position may be clobbered
8862 // by inputs being moved and *staying* in that half.
8863 if (IncomingInputs.size() == 1) {
8864 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8865 int InputFixed = std::find(std::begin(SourceHalfMask),
8866 std::end(SourceHalfMask), -1) -
8867 std::begin(SourceHalfMask) + SourceOffset;
8868 SourceHalfMask[InputFixed - SourceOffset] =
8869 IncomingInputs[0] - SourceOffset;
8870 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8872 IncomingInputs[0] = InputFixed;
8874 } else if (IncomingInputs.size() == 2) {
8875 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8876 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8877 // We have two non-adjacent or clobbered inputs we need to extract from
8878 // the source half. To do this, we need to map them into some adjacent
8879 // dword slot in the source mask.
8880 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8881 IncomingInputs[1] - SourceOffset};
8883 // If there is a free slot in the source half mask adjacent to one of
8884 // the inputs, place the other input in it. We use (Index XOR 1) to
8885 // compute an adjacent index.
8886 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8887 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8888 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8889 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8890 InputsFixed[1] = InputsFixed[0] ^ 1;
8891 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8892 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8893 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8894 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8895 InputsFixed[0] = InputsFixed[1] ^ 1;
8896 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8897 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8898 // The two inputs are in the same DWord but it is clobbered and the
8899 // adjacent DWord isn't used at all. Move both inputs to the free
8901 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8902 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8903 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8904 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8906 // The only way we hit this point is if there is no clobbering
8907 // (because there are no off-half inputs to this half) and there is no
8908 // free slot adjacent to one of the inputs. In this case, we have to
8909 // swap an input with a non-input.
8910 for (int i = 0; i < 4; ++i)
8911 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8912 "We can't handle any clobbers here!");
8913 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8914 "Cannot have adjacent inputs here!");
8916 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8917 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8919 // We also have to update the final source mask in this case because
8920 // it may need to undo the above swap.
8921 for (int &M : FinalSourceHalfMask)
8922 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8923 M = InputsFixed[1] + SourceOffset;
8924 else if (M == InputsFixed[1] + SourceOffset)
8925 M = (InputsFixed[0] ^ 1) + SourceOffset;
8927 InputsFixed[1] = InputsFixed[0] ^ 1;
8930 // Point everything at the fixed inputs.
8931 for (int &M : HalfMask)
8932 if (M == IncomingInputs[0])
8933 M = InputsFixed[0] + SourceOffset;
8934 else if (M == IncomingInputs[1])
8935 M = InputsFixed[1] + SourceOffset;
8937 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8938 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8941 llvm_unreachable("Unhandled input size!");
8944 // Now hoist the DWord down to the right half.
8945 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8946 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8947 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8948 for (int &M : HalfMask)
8949 for (int Input : IncomingInputs)
8951 M = FreeDWord * 2 + Input % 2;
8953 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8954 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8955 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8956 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8958 // Now enact all the shuffles we've computed to move the inputs into their
8960 if (!isNoopShuffleMask(PSHUFLMask))
8961 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8962 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8963 if (!isNoopShuffleMask(PSHUFHMask))
8964 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8965 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8966 if (!isNoopShuffleMask(PSHUFDMask))
8967 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8968 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8969 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8970 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8972 // At this point, each half should contain all its inputs, and we can then
8973 // just shuffle them into their final position.
8974 assert(std::count_if(LoMask.begin(), LoMask.end(),
8975 [](int M) { return M >= 4; }) == 0 &&
8976 "Failed to lift all the high half inputs to the low mask!");
8977 assert(std::count_if(HiMask.begin(), HiMask.end(),
8978 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8979 "Failed to lift all the low half inputs to the high mask!");
8981 // Do a half shuffle for the low mask.
8982 if (!isNoopShuffleMask(LoMask))
8983 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8984 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8986 // Do a half shuffle with the high mask after shifting its values down.
8987 for (int &M : HiMask)
8990 if (!isNoopShuffleMask(HiMask))
8991 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8992 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8997 /// \brief Detect whether the mask pattern should be lowered through
9000 /// This essentially tests whether viewing the mask as an interleaving of two
9001 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9002 /// lowering it through interleaving is a significantly better strategy.
9003 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9004 int NumEvenInputs[2] = {0, 0};
9005 int NumOddInputs[2] = {0, 0};
9006 int NumLoInputs[2] = {0, 0};
9007 int NumHiInputs[2] = {0, 0};
9008 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9012 int InputIdx = Mask[i] >= Size;
9015 ++NumLoInputs[InputIdx];
9017 ++NumHiInputs[InputIdx];
9020 ++NumEvenInputs[InputIdx];
9022 ++NumOddInputs[InputIdx];
9025 // The minimum number of cross-input results for both the interleaved and
9026 // split cases. If interleaving results in fewer cross-input results, return
9028 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9029 NumEvenInputs[0] + NumOddInputs[1]);
9030 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9031 NumLoInputs[0] + NumHiInputs[1]);
9032 return InterleavedCrosses < SplitCrosses;
9035 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9037 /// This strategy only works when the inputs from each vector fit into a single
9038 /// half of that vector, and generally there are not so many inputs as to leave
9039 /// the in-place shuffles required highly constrained (and thus expensive). It
9040 /// shifts all the inputs into a single side of both input vectors and then
9041 /// uses an unpack to interleave these inputs in a single vector. At that
9042 /// point, we will fall back on the generic single input shuffle lowering.
9043 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9045 MutableArrayRef<int> Mask,
9046 const X86Subtarget *Subtarget,
9047 SelectionDAG &DAG) {
9048 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9049 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9050 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9051 for (int i = 0; i < 8; ++i)
9052 if (Mask[i] >= 0 && Mask[i] < 4)
9053 LoV1Inputs.push_back(i);
9054 else if (Mask[i] >= 4 && Mask[i] < 8)
9055 HiV1Inputs.push_back(i);
9056 else if (Mask[i] >= 8 && Mask[i] < 12)
9057 LoV2Inputs.push_back(i);
9058 else if (Mask[i] >= 12)
9059 HiV2Inputs.push_back(i);
9061 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9062 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9065 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9066 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9067 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9069 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9070 HiV1Inputs.size() + HiV2Inputs.size();
9072 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9073 ArrayRef<int> HiInputs, bool MoveToLo,
9075 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9076 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9077 if (BadInputs.empty())
9080 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9081 int MoveOffset = MoveToLo ? 0 : 4;
9083 if (GoodInputs.empty()) {
9084 for (int BadInput : BadInputs) {
9085 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9086 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9089 if (GoodInputs.size() == 2) {
9090 // If the low inputs are spread across two dwords, pack them into
9092 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9093 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9094 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9095 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9097 // Otherwise pin the good inputs.
9098 for (int GoodInput : GoodInputs)
9099 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9102 if (BadInputs.size() == 2) {
9103 // If we have two bad inputs then there may be either one or two good
9104 // inputs fixed in place. Find a fixed input, and then find the *other*
9105 // two adjacent indices by using modular arithmetic.
9107 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9108 [](int M) { return M >= 0; }) -
9109 std::begin(MoveMask);
9111 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9112 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9113 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9114 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9115 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9116 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9117 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9119 assert(BadInputs.size() == 1 && "All sizes handled");
9120 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9121 std::end(MoveMask), -1) -
9122 std::begin(MoveMask);
9123 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9124 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9128 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9131 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9133 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9136 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9137 // cross-half traffic in the final shuffle.
9139 // Munge the mask to be a single-input mask after the unpack merges the
9143 M = 2 * (M % 4) + (M / 8);
9145 return DAG.getVectorShuffle(
9146 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9147 DL, MVT::v8i16, V1, V2),
9148 DAG.getUNDEF(MVT::v8i16), Mask);
9151 /// \brief Generic lowering of 8-lane i16 shuffles.
9153 /// This handles both single-input shuffles and combined shuffle/blends with
9154 /// two inputs. The single input shuffles are immediately delegated to
9155 /// a dedicated lowering routine.
9157 /// The blends are lowered in one of three fundamental ways. If there are few
9158 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9159 /// of the input is significantly cheaper when lowered as an interleaving of
9160 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9161 /// halves of the inputs separately (making them have relatively few inputs)
9162 /// and then concatenate them.
9163 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9164 const X86Subtarget *Subtarget,
9165 SelectionDAG &DAG) {
9167 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9168 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9169 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9170 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9171 ArrayRef<int> OrigMask = SVOp->getMask();
9172 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9173 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9174 MutableArrayRef<int> Mask(MaskStorage);
9176 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9178 // Whenever we can lower this as a zext, that instruction is strictly faster
9179 // than any alternative.
9180 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9181 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9184 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9185 auto isV2 = [](int M) { return M >= 8; };
9187 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9188 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9190 if (NumV2Inputs == 0)
9191 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9193 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9194 "to be V1-input shuffles.");
9196 // There are special ways we can lower some single-element blends.
9197 if (NumV2Inputs == 1)
9198 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9199 Mask, Subtarget, DAG))
9202 // Use dedicated unpack instructions for masks that match their pattern.
9203 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9204 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9205 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9206 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9208 if (Subtarget->hasSSE41())
9209 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9213 // Try to use byte shift instructions.
9214 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9215 DL, MVT::v8i16, V1, V2, Mask, DAG))
9218 // Try to use byte rotation instructions.
9219 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9220 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9223 if (NumV1Inputs + NumV2Inputs <= 4)
9224 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9226 // Check whether an interleaving lowering is likely to be more efficient.
9227 // This isn't perfect but it is a strong heuristic that tends to work well on
9228 // the kinds of shuffles that show up in practice.
9230 // FIXME: Handle 1x, 2x, and 4x interleaving.
9231 if (shouldLowerAsInterleaving(Mask)) {
9232 // FIXME: Figure out whether we should pack these into the low or high
9235 int EMask[8], OMask[8];
9236 for (int i = 0; i < 4; ++i) {
9237 EMask[i] = Mask[2*i];
9238 OMask[i] = Mask[2*i + 1];
9243 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9244 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9246 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9249 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9250 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9252 for (int i = 0; i < 4; ++i) {
9253 LoBlendMask[i] = Mask[i];
9254 HiBlendMask[i] = Mask[i + 4];
9257 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9258 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9259 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9260 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9262 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9263 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9266 /// \brief Check whether a compaction lowering can be done by dropping even
9267 /// elements and compute how many times even elements must be dropped.
9269 /// This handles shuffles which take every Nth element where N is a power of
9270 /// two. Example shuffle masks:
9272 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9273 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9274 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9275 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9276 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9277 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9279 /// Any of these lanes can of course be undef.
9281 /// This routine only supports N <= 3.
9282 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9285 /// \returns N above, or the number of times even elements must be dropped if
9286 /// there is such a number. Otherwise returns zero.
9287 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9288 // Figure out whether we're looping over two inputs or just one.
9289 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9291 // The modulus for the shuffle vector entries is based on whether this is
9292 // a single input or not.
9293 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9294 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9295 "We should only be called with masks with a power-of-2 size!");
9297 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9299 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9300 // and 2^3 simultaneously. This is because we may have ambiguity with
9301 // partially undef inputs.
9302 bool ViableForN[3] = {true, true, true};
9304 for (int i = 0, e = Mask.size(); i < e; ++i) {
9305 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9310 bool IsAnyViable = false;
9311 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9312 if (ViableForN[j]) {
9315 // The shuffle mask must be equal to (i * 2^N) % M.
9316 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9319 ViableForN[j] = false;
9321 // Early exit if we exhaust the possible powers of two.
9326 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9330 // Return 0 as there is no viable power of two.
9334 /// \brief Generic lowering of v16i8 shuffles.
9336 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9337 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9338 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9339 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9341 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9342 const X86Subtarget *Subtarget,
9343 SelectionDAG &DAG) {
9345 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9346 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9347 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9348 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9349 ArrayRef<int> OrigMask = SVOp->getMask();
9350 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9352 // Try to use byte shift instructions.
9353 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9354 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9357 // Try to use byte rotation instructions.
9358 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9359 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9362 // Try to use a zext lowering.
9363 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9364 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9367 int MaskStorage[16] = {
9368 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9369 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9370 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9371 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9372 MutableArrayRef<int> Mask(MaskStorage);
9373 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9374 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9377 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9379 // For single-input shuffles, there are some nicer lowering tricks we can use.
9380 if (NumV2Elements == 0) {
9381 // Check for being able to broadcast a single element.
9382 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9383 Mask, Subtarget, DAG))
9386 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9387 // Notably, this handles splat and partial-splat shuffles more efficiently.
9388 // However, it only makes sense if the pre-duplication shuffle simplifies
9389 // things significantly. Currently, this means we need to be able to
9390 // express the pre-duplication shuffle as an i16 shuffle.
9392 // FIXME: We should check for other patterns which can be widened into an
9393 // i16 shuffle as well.
9394 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9395 for (int i = 0; i < 16; i += 2)
9396 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9401 auto tryToWidenViaDuplication = [&]() -> SDValue {
9402 if (!canWidenViaDuplication(Mask))
9404 SmallVector<int, 4> LoInputs;
9405 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9406 [](int M) { return M >= 0 && M < 8; });
9407 std::sort(LoInputs.begin(), LoInputs.end());
9408 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9410 SmallVector<int, 4> HiInputs;
9411 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9412 [](int M) { return M >= 8; });
9413 std::sort(HiInputs.begin(), HiInputs.end());
9414 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9417 bool TargetLo = LoInputs.size() >= HiInputs.size();
9418 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9419 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9421 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9422 SmallDenseMap<int, int, 8> LaneMap;
9423 for (int I : InPlaceInputs) {
9424 PreDupI16Shuffle[I/2] = I/2;
9427 int j = TargetLo ? 0 : 4, je = j + 4;
9428 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9429 // Check if j is already a shuffle of this input. This happens when
9430 // there are two adjacent bytes after we move the low one.
9431 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9432 // If we haven't yet mapped the input, search for a slot into which
9434 while (j < je && PreDupI16Shuffle[j] != -1)
9438 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9441 // Map this input with the i16 shuffle.
9442 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9445 // Update the lane map based on the mapping we ended up with.
9446 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9449 ISD::BITCAST, DL, MVT::v16i8,
9450 DAG.getVectorShuffle(MVT::v8i16, DL,
9451 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9452 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9454 // Unpack the bytes to form the i16s that will be shuffled into place.
9455 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9456 MVT::v16i8, V1, V1);
9458 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9459 for (int i = 0; i < 16; ++i)
9460 if (Mask[i] != -1) {
9461 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9462 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9463 if (PostDupI16Shuffle[i / 2] == -1)
9464 PostDupI16Shuffle[i / 2] = MappedMask;
9466 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9467 "Conflicting entrties in the original shuffle!");
9470 ISD::BITCAST, DL, MVT::v16i8,
9471 DAG.getVectorShuffle(MVT::v8i16, DL,
9472 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9473 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9475 if (SDValue V = tryToWidenViaDuplication())
9479 // Check whether an interleaving lowering is likely to be more efficient.
9480 // This isn't perfect but it is a strong heuristic that tends to work well on
9481 // the kinds of shuffles that show up in practice.
9483 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9484 if (shouldLowerAsInterleaving(Mask)) {
9485 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9486 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9488 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9489 return (M >= 8 && M < 16) || M >= 24;
9491 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9492 -1, -1, -1, -1, -1, -1, -1, -1};
9493 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9494 -1, -1, -1, -1, -1, -1, -1, -1};
9495 bool UnpackLo = NumLoHalf >= NumHiHalf;
9496 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9497 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9498 for (int i = 0; i < 8; ++i) {
9499 TargetEMask[i] = Mask[2 * i];
9500 TargetOMask[i] = Mask[2 * i + 1];
9503 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9504 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9506 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9507 MVT::v16i8, Evens, Odds);
9510 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9511 // with PSHUFB. It is important to do this before we attempt to generate any
9512 // blends but after all of the single-input lowerings. If the single input
9513 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9514 // want to preserve that and we can DAG combine any longer sequences into
9515 // a PSHUFB in the end. But once we start blending from multiple inputs,
9516 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9517 // and there are *very* few patterns that would actually be faster than the
9518 // PSHUFB approach because of its ability to zero lanes.
9520 // FIXME: The only exceptions to the above are blends which are exact
9521 // interleavings with direct instructions supporting them. We currently don't
9522 // handle those well here.
9523 if (Subtarget->hasSSSE3()) {
9526 for (int i = 0; i < 16; ++i)
9527 if (Mask[i] == -1) {
9528 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9530 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9532 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9534 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9535 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9536 if (isSingleInputShuffleMask(Mask))
9537 return V1; // Single inputs are easy.
9539 // Otherwise, blend the two.
9540 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9541 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9542 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9545 // There are special ways we can lower some single-element blends.
9546 if (NumV2Elements == 1)
9547 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9548 Mask, Subtarget, DAG))
9551 // Check whether a compaction lowering can be done. This handles shuffles
9552 // which take every Nth element for some even N. See the helper function for
9555 // We special case these as they can be particularly efficiently handled with
9556 // the PACKUSB instruction on x86 and they show up in common patterns of
9557 // rearranging bytes to truncate wide elements.
9558 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9559 // NumEvenDrops is the power of two stride of the elements. Another way of
9560 // thinking about it is that we need to drop the even elements this many
9561 // times to get the original input.
9562 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9564 // First we need to zero all the dropped bytes.
9565 assert(NumEvenDrops <= 3 &&
9566 "No support for dropping even elements more than 3 times.");
9567 // We use the mask type to pick which bytes are preserved based on how many
9568 // elements are dropped.
9569 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9570 SDValue ByteClearMask =
9571 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9572 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9573 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9575 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9577 // Now pack things back together.
9578 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9579 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9580 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9581 for (int i = 1; i < NumEvenDrops; ++i) {
9582 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9583 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9589 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9590 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9591 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9592 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9594 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9595 MutableArrayRef<int> V1HalfBlendMask,
9596 MutableArrayRef<int> V2HalfBlendMask) {
9597 for (int i = 0; i < 8; ++i)
9598 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9599 V1HalfBlendMask[i] = HalfMask[i];
9601 } else if (HalfMask[i] >= 16) {
9602 V2HalfBlendMask[i] = HalfMask[i] - 16;
9603 HalfMask[i] = i + 8;
9606 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9607 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9609 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9611 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9612 MutableArrayRef<int> HiBlendMask) {
9614 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9615 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9617 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9618 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9619 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9620 [](int M) { return M >= 0 && M % 2 == 1; })) {
9621 // Use a mask to drop the high bytes.
9622 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9623 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9624 DAG.getConstant(0x00FF, MVT::v8i16));
9626 // This will be a single vector shuffle instead of a blend so nuke V2.
9627 V2 = DAG.getUNDEF(MVT::v8i16);
9629 // Squash the masks to point directly into V1.
9630 for (int &M : LoBlendMask)
9633 for (int &M : HiBlendMask)
9637 // Otherwise just unpack the low half of V into V1 and the high half into
9638 // V2 so that we can blend them as i16s.
9639 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9640 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9641 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9642 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9645 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9646 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9647 return std::make_pair(BlendedLo, BlendedHi);
9649 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9650 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9651 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9653 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9654 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9656 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9659 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9661 /// This routine breaks down the specific type of 128-bit shuffle and
9662 /// dispatches to the lowering routines accordingly.
9663 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9664 MVT VT, const X86Subtarget *Subtarget,
9665 SelectionDAG &DAG) {
9666 switch (VT.SimpleTy) {
9668 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9670 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9672 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9674 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9676 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9678 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9681 llvm_unreachable("Unimplemented!");
9685 /// \brief Helper function to test whether a shuffle mask could be
9686 /// simplified by widening the elements being shuffled.
9688 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9689 /// leaves it in an unspecified state.
9691 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9692 /// shuffle masks. The latter have the special property of a '-2' representing
9693 /// a zero-ed lane of a vector.
9694 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9695 SmallVectorImpl<int> &WidenedMask) {
9696 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9697 // If both elements are undef, its trivial.
9698 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9699 WidenedMask.push_back(SM_SentinelUndef);
9703 // Check for an undef mask and a mask value properly aligned to fit with
9704 // a pair of values. If we find such a case, use the non-undef mask's value.
9705 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9706 WidenedMask.push_back(Mask[i + 1] / 2);
9709 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9710 WidenedMask.push_back(Mask[i] / 2);
9714 // When zeroing, we need to spread the zeroing across both lanes to widen.
9715 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9716 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9717 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9718 WidenedMask.push_back(SM_SentinelZero);
9724 // Finally check if the two mask values are adjacent and aligned with
9726 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9727 WidenedMask.push_back(Mask[i] / 2);
9731 // Otherwise we can't safely widen the elements used in this shuffle.
9734 assert(WidenedMask.size() == Mask.size() / 2 &&
9735 "Incorrect size of mask after widening the elements!");
9740 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9742 /// This routine just extracts two subvectors, shuffles them independently, and
9743 /// then concatenates them back together. This should work effectively with all
9744 /// AVX vector shuffle types.
9745 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9746 SDValue V2, ArrayRef<int> Mask,
9747 SelectionDAG &DAG) {
9748 assert(VT.getSizeInBits() >= 256 &&
9749 "Only for 256-bit or wider vector shuffles!");
9750 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9751 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9753 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9754 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9756 int NumElements = VT.getVectorNumElements();
9757 int SplitNumElements = NumElements / 2;
9758 MVT ScalarVT = VT.getScalarType();
9759 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9761 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9762 DAG.getIntPtrConstant(0));
9763 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9764 DAG.getIntPtrConstant(SplitNumElements));
9765 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9766 DAG.getIntPtrConstant(0));
9767 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9768 DAG.getIntPtrConstant(SplitNumElements));
9770 // Now create two 4-way blends of these half-width vectors.
9771 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9772 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9773 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9774 for (int i = 0; i < SplitNumElements; ++i) {
9775 int M = HalfMask[i];
9776 if (M >= NumElements) {
9777 if (M >= NumElements + SplitNumElements)
9781 V2BlendMask.push_back(M - NumElements);
9782 V1BlendMask.push_back(-1);
9783 BlendMask.push_back(SplitNumElements + i);
9784 } else if (M >= 0) {
9785 if (M >= SplitNumElements)
9789 V2BlendMask.push_back(-1);
9790 V1BlendMask.push_back(M);
9791 BlendMask.push_back(i);
9793 V2BlendMask.push_back(-1);
9794 V1BlendMask.push_back(-1);
9795 BlendMask.push_back(-1);
9799 // Because the lowering happens after all combining takes place, we need to
9800 // manually combine these blend masks as much as possible so that we create
9801 // a minimal number of high-level vector shuffle nodes.
9803 // First try just blending the halves of V1 or V2.
9804 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9805 return DAG.getUNDEF(SplitVT);
9806 if (!UseLoV2 && !UseHiV2)
9807 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9808 if (!UseLoV1 && !UseHiV1)
9809 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9811 SDValue V1Blend, V2Blend;
9812 if (UseLoV1 && UseHiV1) {
9814 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9816 // We only use half of V1 so map the usage down into the final blend mask.
9817 V1Blend = UseLoV1 ? LoV1 : HiV1;
9818 for (int i = 0; i < SplitNumElements; ++i)
9819 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9820 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9822 if (UseLoV2 && UseHiV2) {
9824 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9826 // We only use half of V2 so map the usage down into the final blend mask.
9827 V2Blend = UseLoV2 ? LoV2 : HiV2;
9828 for (int i = 0; i < SplitNumElements; ++i)
9829 if (BlendMask[i] >= SplitNumElements)
9830 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9832 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9834 SDValue Lo = HalfBlend(LoMask);
9835 SDValue Hi = HalfBlend(HiMask);
9836 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9839 /// \brief Either split a vector in halves or decompose the shuffles and the
9842 /// This is provided as a good fallback for many lowerings of non-single-input
9843 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9844 /// between splitting the shuffle into 128-bit components and stitching those
9845 /// back together vs. extracting the single-input shuffles and blending those
9847 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9848 SDValue V2, ArrayRef<int> Mask,
9849 SelectionDAG &DAG) {
9850 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9851 "lower single-input shuffles as it "
9852 "could then recurse on itself.");
9853 int Size = Mask.size();
9855 // If this can be modeled as a broadcast of two elements followed by a blend,
9856 // prefer that lowering. This is especially important because broadcasts can
9857 // often fold with memory operands.
9858 auto DoBothBroadcast = [&] {
9859 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9862 if (V2BroadcastIdx == -1)
9863 V2BroadcastIdx = M - Size;
9864 else if (M - Size != V2BroadcastIdx)
9866 } else if (M >= 0) {
9867 if (V1BroadcastIdx == -1)
9869 else if (M != V1BroadcastIdx)
9874 if (DoBothBroadcast())
9875 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9878 // If the inputs all stem from a single 128-bit lane of each input, then we
9879 // split them rather than blending because the split will decompose to
9880 // unusually few instructions.
9881 int LaneCount = VT.getSizeInBits() / 128;
9882 int LaneSize = Size / LaneCount;
9883 SmallBitVector LaneInputs[2];
9884 LaneInputs[0].resize(LaneCount, false);
9885 LaneInputs[1].resize(LaneCount, false);
9886 for (int i = 0; i < Size; ++i)
9888 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9889 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9890 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9892 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9893 // that the decomposed single-input shuffles don't end up here.
9894 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9897 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9898 /// a permutation and blend of those lanes.
9900 /// This essentially blends the out-of-lane inputs to each lane into the lane
9901 /// from a permuted copy of the vector. This lowering strategy results in four
9902 /// instructions in the worst case for a single-input cross lane shuffle which
9903 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9904 /// of. Special cases for each particular shuffle pattern should be handled
9905 /// prior to trying this lowering.
9906 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9907 SDValue V1, SDValue V2,
9909 SelectionDAG &DAG) {
9910 // FIXME: This should probably be generalized for 512-bit vectors as well.
9911 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9912 int LaneSize = Mask.size() / 2;
9914 // If there are only inputs from one 128-bit lane, splitting will in fact be
9915 // less expensive. The flags track wether the given lane contains an element
9916 // that crosses to another lane.
9917 bool LaneCrossing[2] = {false, false};
9918 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9919 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9920 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9921 if (!LaneCrossing[0] || !LaneCrossing[1])
9922 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9924 if (isSingleInputShuffleMask(Mask)) {
9925 SmallVector<int, 32> FlippedBlendMask;
9926 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9927 FlippedBlendMask.push_back(
9928 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9930 : Mask[i] % LaneSize +
9931 (i / LaneSize) * LaneSize + Size));
9933 // Flip the vector, and blend the results which should now be in-lane. The
9934 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9935 // 5 for the high source. The value 3 selects the high half of source 2 and
9936 // the value 2 selects the low half of source 2. We only use source 2 to
9937 // allow folding it into a memory operand.
9938 unsigned PERMMask = 3 | 2 << 4;
9939 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9940 V1, DAG.getConstant(PERMMask, MVT::i8));
9941 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9944 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9945 // will be handled by the above logic and a blend of the results, much like
9946 // other patterns in AVX.
9947 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9950 /// \brief Handle lowering 2-lane 128-bit shuffles.
9951 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9952 SDValue V2, ArrayRef<int> Mask,
9953 const X86Subtarget *Subtarget,
9954 SelectionDAG &DAG) {
9955 // Blends are faster and handle all the non-lane-crossing cases.
9956 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9960 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9961 VT.getVectorNumElements() / 2);
9962 // Check for patterns which can be matched with a single insert of a 128-bit
9964 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9965 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9966 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9967 DAG.getIntPtrConstant(0));
9968 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9969 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9970 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9972 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9973 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9974 DAG.getIntPtrConstant(0));
9975 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9976 DAG.getIntPtrConstant(2));
9977 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9980 // Otherwise form a 128-bit permutation.
9981 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9982 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9983 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9984 DAG.getConstant(PermMask, MVT::i8));
9987 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9989 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9990 /// isn't available.
9991 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9992 const X86Subtarget *Subtarget,
9993 SelectionDAG &DAG) {
9995 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9996 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9998 ArrayRef<int> Mask = SVOp->getMask();
9999 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10001 SmallVector<int, 4> WidenedMask;
10002 if (canWidenShuffleElements(Mask, WidenedMask))
10003 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10006 if (isSingleInputShuffleMask(Mask)) {
10007 // Check for being able to broadcast a single element.
10008 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10009 Mask, Subtarget, DAG))
10012 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10013 // Non-half-crossing single input shuffles can be lowerid with an
10014 // interleaved permutation.
10015 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10016 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10017 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10018 DAG.getConstant(VPERMILPMask, MVT::i8));
10021 // With AVX2 we have direct support for this permutation.
10022 if (Subtarget->hasAVX2())
10023 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10024 getV4X86ShuffleImm8ForMask(Mask, DAG));
10026 // Otherwise, fall back.
10027 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10031 // X86 has dedicated unpack instructions that can handle specific blend
10032 // operations: UNPCKH and UNPCKL.
10033 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10034 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10035 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10036 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10038 // If we have a single input to the zero element, insert that into V1 if we
10039 // can do so cheaply.
10040 int NumV2Elements =
10041 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10042 if (NumV2Elements == 1 && Mask[0] >= 4)
10043 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10044 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10047 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10051 // Check if the blend happens to exactly fit that of SHUFPD.
10052 if ((Mask[0] == -1 || Mask[0] < 2) &&
10053 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10054 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10055 (Mask[3] == -1 || Mask[3] >= 6)) {
10056 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10057 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10058 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10059 DAG.getConstant(SHUFPDMask, MVT::i8));
10061 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10062 (Mask[1] == -1 || Mask[1] < 2) &&
10063 (Mask[2] == -1 || Mask[2] >= 6) &&
10064 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10065 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10066 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10067 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10068 DAG.getConstant(SHUFPDMask, MVT::i8));
10071 // If we have AVX2 then we always want to lower with a blend because an v4 we
10072 // can fully permute the elements.
10073 if (Subtarget->hasAVX2())
10074 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10077 // Otherwise fall back on generic lowering.
10078 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10081 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10083 /// This routine is only called when we have AVX2 and thus a reasonable
10084 /// instruction set for v4i64 shuffling..
10085 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10086 const X86Subtarget *Subtarget,
10087 SelectionDAG &DAG) {
10089 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10090 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10091 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10092 ArrayRef<int> Mask = SVOp->getMask();
10093 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10094 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10096 SmallVector<int, 4> WidenedMask;
10097 if (canWidenShuffleElements(Mask, WidenedMask))
10098 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10101 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10105 // Check for being able to broadcast a single element.
10106 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10107 Mask, Subtarget, DAG))
10110 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10111 // use lower latency instructions that will operate on both 128-bit lanes.
10112 SmallVector<int, 2> RepeatedMask;
10113 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10114 if (isSingleInputShuffleMask(Mask)) {
10115 int PSHUFDMask[] = {-1, -1, -1, -1};
10116 for (int i = 0; i < 2; ++i)
10117 if (RepeatedMask[i] >= 0) {
10118 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10119 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10121 return DAG.getNode(
10122 ISD::BITCAST, DL, MVT::v4i64,
10123 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10124 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10125 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10128 // Use dedicated unpack instructions for masks that match their pattern.
10129 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10130 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10131 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10132 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10135 // AVX2 provides a direct instruction for permuting a single input across
10137 if (isSingleInputShuffleMask(Mask))
10138 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10139 getV4X86ShuffleImm8ForMask(Mask, DAG));
10141 // Otherwise fall back on generic blend lowering.
10142 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10146 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10148 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10149 /// isn't available.
10150 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10151 const X86Subtarget *Subtarget,
10152 SelectionDAG &DAG) {
10154 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10155 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10156 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10157 ArrayRef<int> Mask = SVOp->getMask();
10158 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10160 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10164 // Check for being able to broadcast a single element.
10165 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10166 Mask, Subtarget, DAG))
10169 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10170 // options to efficiently lower the shuffle.
10171 SmallVector<int, 4> RepeatedMask;
10172 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10173 assert(RepeatedMask.size() == 4 &&
10174 "Repeated masks must be half the mask width!");
10175 if (isSingleInputShuffleMask(Mask))
10176 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10177 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10179 // Use dedicated unpack instructions for masks that match their pattern.
10180 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10181 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10182 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10183 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10185 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10186 // have already handled any direct blends. We also need to squash the
10187 // repeated mask into a simulated v4f32 mask.
10188 for (int i = 0; i < 4; ++i)
10189 if (RepeatedMask[i] >= 8)
10190 RepeatedMask[i] -= 4;
10191 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10194 // If we have a single input shuffle with different shuffle patterns in the
10195 // two 128-bit lanes use the variable mask to VPERMILPS.
10196 if (isSingleInputShuffleMask(Mask)) {
10197 SDValue VPermMask[8];
10198 for (int i = 0; i < 8; ++i)
10199 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10200 : DAG.getConstant(Mask[i], MVT::i32);
10201 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10202 return DAG.getNode(
10203 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10204 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10206 if (Subtarget->hasAVX2())
10207 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10208 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10209 DAG.getNode(ISD::BUILD_VECTOR, DL,
10210 MVT::v8i32, VPermMask)),
10213 // Otherwise, fall back.
10214 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10218 // If we have AVX2 then we always want to lower with a blend because at v8 we
10219 // can fully permute the elements.
10220 if (Subtarget->hasAVX2())
10221 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10224 // Otherwise fall back on generic lowering.
10225 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10228 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10230 /// This routine is only called when we have AVX2 and thus a reasonable
10231 /// instruction set for v8i32 shuffling..
10232 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10233 const X86Subtarget *Subtarget,
10234 SelectionDAG &DAG) {
10236 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10237 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10238 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10239 ArrayRef<int> Mask = SVOp->getMask();
10240 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10241 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10243 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10247 // Check for being able to broadcast a single element.
10248 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10249 Mask, Subtarget, DAG))
10252 // If the shuffle mask is repeated in each 128-bit lane we can use more
10253 // efficient instructions that mirror the shuffles across the two 128-bit
10255 SmallVector<int, 4> RepeatedMask;
10256 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10257 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10258 if (isSingleInputShuffleMask(Mask))
10259 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10260 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10262 // Use dedicated unpack instructions for masks that match their pattern.
10263 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10264 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10265 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10266 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10269 // If the shuffle patterns aren't repeated but it is a single input, directly
10270 // generate a cross-lane VPERMD instruction.
10271 if (isSingleInputShuffleMask(Mask)) {
10272 SDValue VPermMask[8];
10273 for (int i = 0; i < 8; ++i)
10274 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10275 : DAG.getConstant(Mask[i], MVT::i32);
10276 return DAG.getNode(
10277 X86ISD::VPERMV, DL, MVT::v8i32,
10278 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10281 // Otherwise fall back on generic blend lowering.
10282 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10286 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10288 /// This routine is only called when we have AVX2 and thus a reasonable
10289 /// instruction set for v16i16 shuffling..
10290 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10291 const X86Subtarget *Subtarget,
10292 SelectionDAG &DAG) {
10294 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10295 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10296 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10297 ArrayRef<int> Mask = SVOp->getMask();
10298 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10299 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10301 // Check for being able to broadcast a single element.
10302 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10303 Mask, Subtarget, DAG))
10306 // There are no generalized cross-lane shuffle operations available on i16
10308 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10309 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10312 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10316 // Use dedicated unpack instructions for masks that match their pattern.
10317 if (isShuffleEquivalent(Mask,
10318 // First 128-bit lane:
10319 0, 16, 1, 17, 2, 18, 3, 19,
10320 // Second 128-bit lane:
10321 8, 24, 9, 25, 10, 26, 11, 27))
10322 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10323 if (isShuffleEquivalent(Mask,
10324 // First 128-bit lane:
10325 4, 20, 5, 21, 6, 22, 7, 23,
10326 // Second 128-bit lane:
10327 12, 28, 13, 29, 14, 30, 15, 31))
10328 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10330 if (isSingleInputShuffleMask(Mask)) {
10331 SDValue PSHUFBMask[32];
10332 for (int i = 0; i < 16; ++i) {
10333 if (Mask[i] == -1) {
10334 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10338 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10339 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10340 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10341 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10343 return DAG.getNode(
10344 ISD::BITCAST, DL, MVT::v16i16,
10346 X86ISD::PSHUFB, DL, MVT::v32i8,
10347 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10348 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10351 // Otherwise fall back on generic lowering.
10352 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10355 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10357 /// This routine is only called when we have AVX2 and thus a reasonable
10358 /// instruction set for v32i8 shuffling..
10359 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10360 const X86Subtarget *Subtarget,
10361 SelectionDAG &DAG) {
10363 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10364 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10365 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10366 ArrayRef<int> Mask = SVOp->getMask();
10367 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10368 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10370 // Check for being able to broadcast a single element.
10371 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10372 Mask, Subtarget, DAG))
10375 // There are no generalized cross-lane shuffle operations available on i8
10377 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10378 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10381 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10385 // Use dedicated unpack instructions for masks that match their pattern.
10386 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10388 if (isShuffleEquivalent(
10390 // First 128-bit lane:
10391 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10392 // Second 128-bit lane:
10393 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10394 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10395 if (isShuffleEquivalent(
10397 // First 128-bit lane:
10398 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10399 // Second 128-bit lane:
10400 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10401 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10403 if (isSingleInputShuffleMask(Mask)) {
10404 SDValue PSHUFBMask[32];
10405 for (int i = 0; i < 32; ++i)
10408 ? DAG.getUNDEF(MVT::i8)
10409 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10411 return DAG.getNode(
10412 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10413 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10416 // Otherwise fall back on generic lowering.
10417 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10420 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10422 /// This routine either breaks down the specific type of a 256-bit x86 vector
10423 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10424 /// together based on the available instructions.
10425 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10426 MVT VT, const X86Subtarget *Subtarget,
10427 SelectionDAG &DAG) {
10429 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10430 ArrayRef<int> Mask = SVOp->getMask();
10432 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10433 // check for those subtargets here and avoid much of the subtarget querying in
10434 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10435 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10436 // floating point types there eventually, just immediately cast everything to
10437 // a float and operate entirely in that domain.
10438 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10439 int ElementBits = VT.getScalarSizeInBits();
10440 if (ElementBits < 32)
10441 // No floating point type available, decompose into 128-bit vectors.
10442 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10444 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10445 VT.getVectorNumElements());
10446 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10447 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10448 return DAG.getNode(ISD::BITCAST, DL, VT,
10449 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10452 switch (VT.SimpleTy) {
10454 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10456 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10458 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10460 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10462 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10464 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10467 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10471 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10472 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10473 const X86Subtarget *Subtarget,
10474 SelectionDAG &DAG) {
10476 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10477 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10478 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10479 ArrayRef<int> Mask = SVOp->getMask();
10480 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10482 // FIXME: Implement direct support for this type!
10483 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10486 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10487 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10488 const X86Subtarget *Subtarget,
10489 SelectionDAG &DAG) {
10491 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10492 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10493 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10494 ArrayRef<int> Mask = SVOp->getMask();
10495 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10497 // FIXME: Implement direct support for this type!
10498 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10501 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10502 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10503 const X86Subtarget *Subtarget,
10504 SelectionDAG &DAG) {
10506 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10507 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10508 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10509 ArrayRef<int> Mask = SVOp->getMask();
10510 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10512 // FIXME: Implement direct support for this type!
10513 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10516 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10517 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10518 const X86Subtarget *Subtarget,
10519 SelectionDAG &DAG) {
10521 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10522 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10523 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10524 ArrayRef<int> Mask = SVOp->getMask();
10525 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10527 // FIXME: Implement direct support for this type!
10528 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10531 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10532 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10533 const X86Subtarget *Subtarget,
10534 SelectionDAG &DAG) {
10536 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10537 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10538 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10539 ArrayRef<int> Mask = SVOp->getMask();
10540 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10541 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10543 // FIXME: Implement direct support for this type!
10544 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10547 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10548 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10549 const X86Subtarget *Subtarget,
10550 SelectionDAG &DAG) {
10552 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10553 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10554 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10555 ArrayRef<int> Mask = SVOp->getMask();
10556 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10557 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10559 // FIXME: Implement direct support for this type!
10560 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10563 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10565 /// This routine either breaks down the specific type of a 512-bit x86 vector
10566 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10567 /// together based on the available instructions.
10568 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10569 MVT VT, const X86Subtarget *Subtarget,
10570 SelectionDAG &DAG) {
10572 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10573 ArrayRef<int> Mask = SVOp->getMask();
10574 assert(Subtarget->hasAVX512() &&
10575 "Cannot lower 512-bit vectors w/ basic ISA!");
10577 // Check for being able to broadcast a single element.
10578 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10579 Mask, Subtarget, DAG))
10582 // Dispatch to each element type for lowering. If we don't have supprot for
10583 // specific element type shuffles at 512 bits, immediately split them and
10584 // lower them. Each lowering routine of a given type is allowed to assume that
10585 // the requisite ISA extensions for that element type are available.
10586 switch (VT.SimpleTy) {
10588 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10590 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10592 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10594 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10596 if (Subtarget->hasBWI())
10597 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10600 if (Subtarget->hasBWI())
10601 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10605 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10608 // Otherwise fall back on splitting.
10609 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10612 /// \brief Top-level lowering for x86 vector shuffles.
10614 /// This handles decomposition, canonicalization, and lowering of all x86
10615 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10616 /// above in helper routines. The canonicalization attempts to widen shuffles
10617 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10618 /// s.t. only one of the two inputs needs to be tested, etc.
10619 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10620 SelectionDAG &DAG) {
10621 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10622 ArrayRef<int> Mask = SVOp->getMask();
10623 SDValue V1 = Op.getOperand(0);
10624 SDValue V2 = Op.getOperand(1);
10625 MVT VT = Op.getSimpleValueType();
10626 int NumElements = VT.getVectorNumElements();
10629 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10631 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10632 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10633 if (V1IsUndef && V2IsUndef)
10634 return DAG.getUNDEF(VT);
10636 // When we create a shuffle node we put the UNDEF node to second operand,
10637 // but in some cases the first operand may be transformed to UNDEF.
10638 // In this case we should just commute the node.
10640 return DAG.getCommutedVectorShuffle(*SVOp);
10642 // Check for non-undef masks pointing at an undef vector and make the masks
10643 // undef as well. This makes it easier to match the shuffle based solely on
10647 if (M >= NumElements) {
10648 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10649 for (int &M : NewMask)
10650 if (M >= NumElements)
10652 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10655 // Try to collapse shuffles into using a vector type with fewer elements but
10656 // wider element types. We cap this to not form integers or floating point
10657 // elements wider than 64 bits, but it might be interesting to form i128
10658 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10659 SmallVector<int, 16> WidenedMask;
10660 if (VT.getScalarSizeInBits() < 64 &&
10661 canWidenShuffleElements(Mask, WidenedMask)) {
10662 MVT NewEltVT = VT.isFloatingPoint()
10663 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10664 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10665 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10666 // Make sure that the new vector type is legal. For example, v2f64 isn't
10668 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10669 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10670 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10671 return DAG.getNode(ISD::BITCAST, dl, VT,
10672 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10676 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10677 for (int M : SVOp->getMask())
10679 ++NumUndefElements;
10680 else if (M < NumElements)
10685 // Commute the shuffle as needed such that more elements come from V1 than
10686 // V2. This allows us to match the shuffle pattern strictly on how many
10687 // elements come from V1 without handling the symmetric cases.
10688 if (NumV2Elements > NumV1Elements)
10689 return DAG.getCommutedVectorShuffle(*SVOp);
10691 // When the number of V1 and V2 elements are the same, try to minimize the
10692 // number of uses of V2 in the low half of the vector. When that is tied,
10693 // ensure that the sum of indices for V1 is equal to or lower than the sum
10695 if (NumV1Elements == NumV2Elements) {
10696 int LowV1Elements = 0, LowV2Elements = 0;
10697 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10698 if (M >= NumElements)
10702 if (LowV2Elements > LowV1Elements) {
10703 return DAG.getCommutedVectorShuffle(*SVOp);
10704 } else if (LowV2Elements == LowV1Elements) {
10705 int SumV1Indices = 0, SumV2Indices = 0;
10706 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10707 if (SVOp->getMask()[i] >= NumElements)
10709 else if (SVOp->getMask()[i] >= 0)
10711 if (SumV2Indices < SumV1Indices)
10712 return DAG.getCommutedVectorShuffle(*SVOp);
10716 // For each vector width, delegate to a specialized lowering routine.
10717 if (VT.getSizeInBits() == 128)
10718 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10720 if (VT.getSizeInBits() == 256)
10721 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10723 // Force AVX-512 vectors to be scalarized for now.
10724 // FIXME: Implement AVX-512 support!
10725 if (VT.getSizeInBits() == 512)
10726 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10728 llvm_unreachable("Unimplemented!");
10732 //===----------------------------------------------------------------------===//
10733 // Legacy vector shuffle lowering
10735 // This code is the legacy code handling vector shuffles until the above
10736 // replaces its functionality and performance.
10737 //===----------------------------------------------------------------------===//
10739 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10740 bool hasInt256, unsigned *MaskOut = nullptr) {
10741 MVT EltVT = VT.getVectorElementType();
10743 // There is no blend with immediate in AVX-512.
10744 if (VT.is512BitVector())
10747 if (!hasSSE41 || EltVT == MVT::i8)
10749 if (!hasInt256 && VT == MVT::v16i16)
10752 unsigned MaskValue = 0;
10753 unsigned NumElems = VT.getVectorNumElements();
10754 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10755 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10756 unsigned NumElemsInLane = NumElems / NumLanes;
10758 // Blend for v16i16 should be symetric for the both lanes.
10759 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10761 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10762 int EltIdx = MaskVals[i];
10764 if ((EltIdx < 0 || EltIdx == (int)i) &&
10765 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10768 if (((unsigned)EltIdx == (i + NumElems)) &&
10769 (SndLaneEltIdx < 0 ||
10770 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10771 MaskValue |= (1 << i);
10777 *MaskOut = MaskValue;
10781 // Try to lower a shuffle node into a simple blend instruction.
10782 // This function assumes isBlendMask returns true for this
10783 // SuffleVectorSDNode
10784 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10785 unsigned MaskValue,
10786 const X86Subtarget *Subtarget,
10787 SelectionDAG &DAG) {
10788 MVT VT = SVOp->getSimpleValueType(0);
10789 MVT EltVT = VT.getVectorElementType();
10790 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10791 Subtarget->hasInt256() && "Trying to lower a "
10792 "VECTOR_SHUFFLE to a Blend but "
10793 "with the wrong mask"));
10794 SDValue V1 = SVOp->getOperand(0);
10795 SDValue V2 = SVOp->getOperand(1);
10797 unsigned NumElems = VT.getVectorNumElements();
10799 // Convert i32 vectors to floating point if it is not AVX2.
10800 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10802 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10803 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10805 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10806 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10809 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10810 DAG.getConstant(MaskValue, MVT::i32));
10811 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10814 /// In vector type \p VT, return true if the element at index \p InputIdx
10815 /// falls on a different 128-bit lane than \p OutputIdx.
10816 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10817 unsigned OutputIdx) {
10818 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10819 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10822 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10823 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10824 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10825 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10827 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10828 SelectionDAG &DAG) {
10829 MVT VT = V1.getSimpleValueType();
10830 assert(VT.is128BitVector() || VT.is256BitVector());
10832 MVT EltVT = VT.getVectorElementType();
10833 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10834 unsigned NumElts = VT.getVectorNumElements();
10836 SmallVector<SDValue, 32> PshufbMask;
10837 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10838 int InputIdx = MaskVals[OutputIdx];
10839 unsigned InputByteIdx;
10841 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10842 InputByteIdx = 0x80;
10844 // Cross lane is not allowed.
10845 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10847 InputByteIdx = InputIdx * EltSizeInBytes;
10848 // Index is an byte offset within the 128-bit lane.
10849 InputByteIdx &= 0xf;
10852 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10853 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10854 if (InputByteIdx != 0x80)
10859 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10861 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10862 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10863 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10866 // v8i16 shuffles - Prefer shuffles in the following order:
10867 // 1. [all] pshuflw, pshufhw, optional move
10868 // 2. [ssse3] 1 x pshufb
10869 // 3. [ssse3] 2 x pshufb + 1 x por
10870 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10872 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10873 SelectionDAG &DAG) {
10874 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10875 SDValue V1 = SVOp->getOperand(0);
10876 SDValue V2 = SVOp->getOperand(1);
10878 SmallVector<int, 8> MaskVals;
10880 // Determine if more than 1 of the words in each of the low and high quadwords
10881 // of the result come from the same quadword of one of the two inputs. Undef
10882 // mask values count as coming from any quadword, for better codegen.
10884 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10885 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10886 unsigned LoQuad[] = { 0, 0, 0, 0 };
10887 unsigned HiQuad[] = { 0, 0, 0, 0 };
10888 // Indices of quads used.
10889 std::bitset<4> InputQuads;
10890 for (unsigned i = 0; i < 8; ++i) {
10891 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10892 int EltIdx = SVOp->getMaskElt(i);
10893 MaskVals.push_back(EltIdx);
10901 ++Quad[EltIdx / 4];
10902 InputQuads.set(EltIdx / 4);
10905 int BestLoQuad = -1;
10906 unsigned MaxQuad = 1;
10907 for (unsigned i = 0; i < 4; ++i) {
10908 if (LoQuad[i] > MaxQuad) {
10910 MaxQuad = LoQuad[i];
10914 int BestHiQuad = -1;
10916 for (unsigned i = 0; i < 4; ++i) {
10917 if (HiQuad[i] > MaxQuad) {
10919 MaxQuad = HiQuad[i];
10923 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10924 // of the two input vectors, shuffle them into one input vector so only a
10925 // single pshufb instruction is necessary. If there are more than 2 input
10926 // quads, disable the next transformation since it does not help SSSE3.
10927 bool V1Used = InputQuads[0] || InputQuads[1];
10928 bool V2Used = InputQuads[2] || InputQuads[3];
10929 if (Subtarget->hasSSSE3()) {
10930 if (InputQuads.count() == 2 && V1Used && V2Used) {
10931 BestLoQuad = InputQuads[0] ? 0 : 1;
10932 BestHiQuad = InputQuads[2] ? 2 : 3;
10934 if (InputQuads.count() > 2) {
10940 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10941 // the shuffle mask. If a quad is scored as -1, that means that it contains
10942 // words from all 4 input quadwords.
10944 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10946 BestLoQuad < 0 ? 0 : BestLoQuad,
10947 BestHiQuad < 0 ? 1 : BestHiQuad
10949 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10950 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10951 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10952 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10954 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10955 // source words for the shuffle, to aid later transformations.
10956 bool AllWordsInNewV = true;
10957 bool InOrder[2] = { true, true };
10958 for (unsigned i = 0; i != 8; ++i) {
10959 int idx = MaskVals[i];
10961 InOrder[i/4] = false;
10962 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10964 AllWordsInNewV = false;
10968 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10969 if (AllWordsInNewV) {
10970 for (int i = 0; i != 8; ++i) {
10971 int idx = MaskVals[i];
10974 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10975 if ((idx != i) && idx < 4)
10977 if ((idx != i) && idx > 3)
10986 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10987 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10988 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10989 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10990 unsigned TargetMask = 0;
10991 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10992 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10993 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10994 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10995 getShufflePSHUFLWImmediate(SVOp);
10996 V1 = NewV.getOperand(0);
10997 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11001 // Promote splats to a larger type which usually leads to more efficient code.
11002 // FIXME: Is this true if pshufb is available?
11003 if (SVOp->isSplat())
11004 return PromoteSplat(SVOp, DAG);
11006 // If we have SSSE3, and all words of the result are from 1 input vector,
11007 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11008 // is present, fall back to case 4.
11009 if (Subtarget->hasSSSE3()) {
11010 SmallVector<SDValue,16> pshufbMask;
11012 // If we have elements from both input vectors, set the high bit of the
11013 // shuffle mask element to zero out elements that come from V2 in the V1
11014 // mask, and elements that come from V1 in the V2 mask, so that the two
11015 // results can be OR'd together.
11016 bool TwoInputs = V1Used && V2Used;
11017 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11019 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11021 // Calculate the shuffle mask for the second input, shuffle it, and
11022 // OR it with the first shuffled input.
11023 CommuteVectorShuffleMask(MaskVals, 8);
11024 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11025 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11026 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11029 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11030 // and update MaskVals with new element order.
11031 std::bitset<8> InOrder;
11032 if (BestLoQuad >= 0) {
11033 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11034 for (int i = 0; i != 4; ++i) {
11035 int idx = MaskVals[i];
11038 } else if ((idx / 4) == BestLoQuad) {
11039 MaskV[i] = idx & 3;
11043 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11046 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11047 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11048 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11049 NewV.getOperand(0),
11050 getShufflePSHUFLWImmediate(SVOp), DAG);
11054 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11055 // and update MaskVals with the new element order.
11056 if (BestHiQuad >= 0) {
11057 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11058 for (unsigned i = 4; i != 8; ++i) {
11059 int idx = MaskVals[i];
11062 } else if ((idx / 4) == BestHiQuad) {
11063 MaskV[i] = (idx & 3) + 4;
11067 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11070 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11071 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11072 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11073 NewV.getOperand(0),
11074 getShufflePSHUFHWImmediate(SVOp), DAG);
11078 // In case BestHi & BestLo were both -1, which means each quadword has a word
11079 // from each of the four input quadwords, calculate the InOrder bitvector now
11080 // before falling through to the insert/extract cleanup.
11081 if (BestLoQuad == -1 && BestHiQuad == -1) {
11083 for (int i = 0; i != 8; ++i)
11084 if (MaskVals[i] < 0 || MaskVals[i] == i)
11088 // The other elements are put in the right place using pextrw and pinsrw.
11089 for (unsigned i = 0; i != 8; ++i) {
11092 int EltIdx = MaskVals[i];
11095 SDValue ExtOp = (EltIdx < 8) ?
11096 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11097 DAG.getIntPtrConstant(EltIdx)) :
11098 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11099 DAG.getIntPtrConstant(EltIdx - 8));
11100 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11101 DAG.getIntPtrConstant(i));
11106 /// \brief v16i16 shuffles
11108 /// FIXME: We only support generation of a single pshufb currently. We can
11109 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11110 /// well (e.g 2 x pshufb + 1 x por).
11112 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11113 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11114 SDValue V1 = SVOp->getOperand(0);
11115 SDValue V2 = SVOp->getOperand(1);
11118 if (V2.getOpcode() != ISD::UNDEF)
11121 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11122 return getPSHUFB(MaskVals, V1, dl, DAG);
11125 // v16i8 shuffles - Prefer shuffles in the following order:
11126 // 1. [ssse3] 1 x pshufb
11127 // 2. [ssse3] 2 x pshufb + 1 x por
11128 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11129 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11130 const X86Subtarget* Subtarget,
11131 SelectionDAG &DAG) {
11132 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11133 SDValue V1 = SVOp->getOperand(0);
11134 SDValue V2 = SVOp->getOperand(1);
11136 ArrayRef<int> MaskVals = SVOp->getMask();
11138 // Promote splats to a larger type which usually leads to more efficient code.
11139 // FIXME: Is this true if pshufb is available?
11140 if (SVOp->isSplat())
11141 return PromoteSplat(SVOp, DAG);
11143 // If we have SSSE3, case 1 is generated when all result bytes come from
11144 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11145 // present, fall back to case 3.
11147 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11148 if (Subtarget->hasSSSE3()) {
11149 SmallVector<SDValue,16> pshufbMask;
11151 // If all result elements are from one input vector, then only translate
11152 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11154 // Otherwise, we have elements from both input vectors, and must zero out
11155 // elements that come from V2 in the first mask, and V1 in the second mask
11156 // so that we can OR them together.
11157 for (unsigned i = 0; i != 16; ++i) {
11158 int EltIdx = MaskVals[i];
11159 if (EltIdx < 0 || EltIdx >= 16)
11161 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11163 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11164 DAG.getNode(ISD::BUILD_VECTOR, dl,
11165 MVT::v16i8, pshufbMask));
11167 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11168 // the 2nd operand if it's undefined or zero.
11169 if (V2.getOpcode() == ISD::UNDEF ||
11170 ISD::isBuildVectorAllZeros(V2.getNode()))
11173 // Calculate the shuffle mask for the second input, shuffle it, and
11174 // OR it with the first shuffled input.
11175 pshufbMask.clear();
11176 for (unsigned i = 0; i != 16; ++i) {
11177 int EltIdx = MaskVals[i];
11178 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11179 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11181 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11182 DAG.getNode(ISD::BUILD_VECTOR, dl,
11183 MVT::v16i8, pshufbMask));
11184 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11187 // No SSSE3 - Calculate in place words and then fix all out of place words
11188 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11189 // the 16 different words that comprise the two doublequadword input vectors.
11190 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11191 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11193 for (int i = 0; i != 8; ++i) {
11194 int Elt0 = MaskVals[i*2];
11195 int Elt1 = MaskVals[i*2+1];
11197 // This word of the result is all undef, skip it.
11198 if (Elt0 < 0 && Elt1 < 0)
11201 // This word of the result is already in the correct place, skip it.
11202 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11205 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11206 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11209 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11210 // using a single extract together, load it and store it.
11211 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11212 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11213 DAG.getIntPtrConstant(Elt1 / 2));
11214 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11215 DAG.getIntPtrConstant(i));
11219 // If Elt1 is defined, extract it from the appropriate source. If the
11220 // source byte is not also odd, shift the extracted word left 8 bits
11221 // otherwise clear the bottom 8 bits if we need to do an or.
11223 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11224 DAG.getIntPtrConstant(Elt1 / 2));
11225 if ((Elt1 & 1) == 0)
11226 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11228 TLI.getShiftAmountTy(InsElt.getValueType())));
11229 else if (Elt0 >= 0)
11230 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11231 DAG.getConstant(0xFF00, MVT::i16));
11233 // If Elt0 is defined, extract it from the appropriate source. If the
11234 // source byte is not also even, shift the extracted word right 8 bits. If
11235 // Elt1 was also defined, OR the extracted values together before
11236 // inserting them in the result.
11238 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11239 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11240 if ((Elt0 & 1) != 0)
11241 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11243 TLI.getShiftAmountTy(InsElt0.getValueType())));
11244 else if (Elt1 >= 0)
11245 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11246 DAG.getConstant(0x00FF, MVT::i16));
11247 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11250 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11251 DAG.getIntPtrConstant(i));
11253 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11256 // v32i8 shuffles - Translate to VPSHUFB if possible.
11258 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11259 const X86Subtarget *Subtarget,
11260 SelectionDAG &DAG) {
11261 MVT VT = SVOp->getSimpleValueType(0);
11262 SDValue V1 = SVOp->getOperand(0);
11263 SDValue V2 = SVOp->getOperand(1);
11265 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11267 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11268 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11269 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11271 // VPSHUFB may be generated if
11272 // (1) one of input vector is undefined or zeroinitializer.
11273 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11274 // And (2) the mask indexes don't cross the 128-bit lane.
11275 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11276 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11279 if (V1IsAllZero && !V2IsAllZero) {
11280 CommuteVectorShuffleMask(MaskVals, 32);
11283 return getPSHUFB(MaskVals, V1, dl, DAG);
11286 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11287 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11288 /// done when every pair / quad of shuffle mask elements point to elements in
11289 /// the right sequence. e.g.
11290 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11292 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11293 SelectionDAG &DAG) {
11294 MVT VT = SVOp->getSimpleValueType(0);
11296 unsigned NumElems = VT.getVectorNumElements();
11299 switch (VT.SimpleTy) {
11300 default: llvm_unreachable("Unexpected!");
11303 return SDValue(SVOp, 0);
11304 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11305 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11306 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11307 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11308 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11309 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11312 SmallVector<int, 8> MaskVec;
11313 for (unsigned i = 0; i != NumElems; i += Scale) {
11315 for (unsigned j = 0; j != Scale; ++j) {
11316 int EltIdx = SVOp->getMaskElt(i+j);
11320 StartIdx = (EltIdx / Scale);
11321 if (EltIdx != (int)(StartIdx*Scale + j))
11324 MaskVec.push_back(StartIdx);
11327 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11328 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11329 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11332 /// getVZextMovL - Return a zero-extending vector move low node.
11334 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11335 SDValue SrcOp, SelectionDAG &DAG,
11336 const X86Subtarget *Subtarget, SDLoc dl) {
11337 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11338 LoadSDNode *LD = nullptr;
11339 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11340 LD = dyn_cast<LoadSDNode>(SrcOp);
11342 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11344 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11345 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11346 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11347 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11348 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11350 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11351 return DAG.getNode(ISD::BITCAST, dl, VT,
11352 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11353 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11355 SrcOp.getOperand(0)
11361 return DAG.getNode(ISD::BITCAST, dl, VT,
11362 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11363 DAG.getNode(ISD::BITCAST, dl,
11367 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11368 /// which could not be matched by any known target speficic shuffle
11370 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11372 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11373 if (NewOp.getNode())
11376 MVT VT = SVOp->getSimpleValueType(0);
11378 unsigned NumElems = VT.getVectorNumElements();
11379 unsigned NumLaneElems = NumElems / 2;
11382 MVT EltVT = VT.getVectorElementType();
11383 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11386 SmallVector<int, 16> Mask;
11387 for (unsigned l = 0; l < 2; ++l) {
11388 // Build a shuffle mask for the output, discovering on the fly which
11389 // input vectors to use as shuffle operands (recorded in InputUsed).
11390 // If building a suitable shuffle vector proves too hard, then bail
11391 // out with UseBuildVector set.
11392 bool UseBuildVector = false;
11393 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11394 unsigned LaneStart = l * NumLaneElems;
11395 for (unsigned i = 0; i != NumLaneElems; ++i) {
11396 // The mask element. This indexes into the input.
11397 int Idx = SVOp->getMaskElt(i+LaneStart);
11399 // the mask element does not index into any input vector.
11400 Mask.push_back(-1);
11404 // The input vector this mask element indexes into.
11405 int Input = Idx / NumLaneElems;
11407 // Turn the index into an offset from the start of the input vector.
11408 Idx -= Input * NumLaneElems;
11410 // Find or create a shuffle vector operand to hold this input.
11412 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11413 if (InputUsed[OpNo] == Input)
11414 // This input vector is already an operand.
11416 if (InputUsed[OpNo] < 0) {
11417 // Create a new operand for this input vector.
11418 InputUsed[OpNo] = Input;
11423 if (OpNo >= array_lengthof(InputUsed)) {
11424 // More than two input vectors used! Give up on trying to create a
11425 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11426 UseBuildVector = true;
11430 // Add the mask index for the new shuffle vector.
11431 Mask.push_back(Idx + OpNo * NumLaneElems);
11434 if (UseBuildVector) {
11435 SmallVector<SDValue, 16> SVOps;
11436 for (unsigned i = 0; i != NumLaneElems; ++i) {
11437 // The mask element. This indexes into the input.
11438 int Idx = SVOp->getMaskElt(i+LaneStart);
11440 SVOps.push_back(DAG.getUNDEF(EltVT));
11444 // The input vector this mask element indexes into.
11445 int Input = Idx / NumElems;
11447 // Turn the index into an offset from the start of the input vector.
11448 Idx -= Input * NumElems;
11450 // Extract the vector element by hand.
11451 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11452 SVOp->getOperand(Input),
11453 DAG.getIntPtrConstant(Idx)));
11456 // Construct the output using a BUILD_VECTOR.
11457 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11458 } else if (InputUsed[0] < 0) {
11459 // No input vectors were used! The result is undefined.
11460 Output[l] = DAG.getUNDEF(NVT);
11462 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11463 (InputUsed[0] % 2) * NumLaneElems,
11465 // If only one input was used, use an undefined vector for the other.
11466 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11467 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11468 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11469 // At least one input vector was used. Create a new shuffle vector.
11470 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11476 // Concatenate the result back
11477 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11480 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11481 /// 4 elements, and match them with several different shuffle types.
11483 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11484 SDValue V1 = SVOp->getOperand(0);
11485 SDValue V2 = SVOp->getOperand(1);
11487 MVT VT = SVOp->getSimpleValueType(0);
11489 assert(VT.is128BitVector() && "Unsupported vector size");
11491 std::pair<int, int> Locs[4];
11492 int Mask1[] = { -1, -1, -1, -1 };
11493 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11495 unsigned NumHi = 0;
11496 unsigned NumLo = 0;
11497 for (unsigned i = 0; i != 4; ++i) {
11498 int Idx = PermMask[i];
11500 Locs[i] = std::make_pair(-1, -1);
11502 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11504 Locs[i] = std::make_pair(0, NumLo);
11505 Mask1[NumLo] = Idx;
11508 Locs[i] = std::make_pair(1, NumHi);
11510 Mask1[2+NumHi] = Idx;
11516 if (NumLo <= 2 && NumHi <= 2) {
11517 // If no more than two elements come from either vector. This can be
11518 // implemented with two shuffles. First shuffle gather the elements.
11519 // The second shuffle, which takes the first shuffle as both of its
11520 // vector operands, put the elements into the right order.
11521 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11523 int Mask2[] = { -1, -1, -1, -1 };
11525 for (unsigned i = 0; i != 4; ++i)
11526 if (Locs[i].first != -1) {
11527 unsigned Idx = (i < 2) ? 0 : 4;
11528 Idx += Locs[i].first * 2 + Locs[i].second;
11532 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11535 if (NumLo == 3 || NumHi == 3) {
11536 // Otherwise, we must have three elements from one vector, call it X, and
11537 // one element from the other, call it Y. First, use a shufps to build an
11538 // intermediate vector with the one element from Y and the element from X
11539 // that will be in the same half in the final destination (the indexes don't
11540 // matter). Then, use a shufps to build the final vector, taking the half
11541 // containing the element from Y from the intermediate, and the other half
11544 // Normalize it so the 3 elements come from V1.
11545 CommuteVectorShuffleMask(PermMask, 4);
11549 // Find the element from V2.
11551 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11552 int Val = PermMask[HiIndex];
11559 Mask1[0] = PermMask[HiIndex];
11561 Mask1[2] = PermMask[HiIndex^1];
11563 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11565 if (HiIndex >= 2) {
11566 Mask1[0] = PermMask[0];
11567 Mask1[1] = PermMask[1];
11568 Mask1[2] = HiIndex & 1 ? 6 : 4;
11569 Mask1[3] = HiIndex & 1 ? 4 : 6;
11570 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11573 Mask1[0] = HiIndex & 1 ? 2 : 0;
11574 Mask1[1] = HiIndex & 1 ? 0 : 2;
11575 Mask1[2] = PermMask[2];
11576 Mask1[3] = PermMask[3];
11581 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11584 // Break it into (shuffle shuffle_hi, shuffle_lo).
11585 int LoMask[] = { -1, -1, -1, -1 };
11586 int HiMask[] = { -1, -1, -1, -1 };
11588 int *MaskPtr = LoMask;
11589 unsigned MaskIdx = 0;
11590 unsigned LoIdx = 0;
11591 unsigned HiIdx = 2;
11592 for (unsigned i = 0; i != 4; ++i) {
11599 int Idx = PermMask[i];
11601 Locs[i] = std::make_pair(-1, -1);
11602 } else if (Idx < 4) {
11603 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11604 MaskPtr[LoIdx] = Idx;
11607 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11608 MaskPtr[HiIdx] = Idx;
11613 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11614 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11615 int MaskOps[] = { -1, -1, -1, -1 };
11616 for (unsigned i = 0; i != 4; ++i)
11617 if (Locs[i].first != -1)
11618 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11619 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11622 static bool MayFoldVectorLoad(SDValue V) {
11623 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11624 V = V.getOperand(0);
11626 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11627 V = V.getOperand(0);
11628 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11629 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11630 // BUILD_VECTOR (load), undef
11631 V = V.getOperand(0);
11633 return MayFoldLoad(V);
11637 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11638 MVT VT = Op.getSimpleValueType();
11640 // Canonizalize to v2f64.
11641 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11642 return DAG.getNode(ISD::BITCAST, dl, VT,
11643 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11648 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11650 SDValue V1 = Op.getOperand(0);
11651 SDValue V2 = Op.getOperand(1);
11652 MVT VT = Op.getSimpleValueType();
11654 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11656 if (HasSSE2 && VT == MVT::v2f64)
11657 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11659 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11660 return DAG.getNode(ISD::BITCAST, dl, VT,
11661 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11662 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11663 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11667 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11668 SDValue V1 = Op.getOperand(0);
11669 SDValue V2 = Op.getOperand(1);
11670 MVT VT = Op.getSimpleValueType();
11672 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11673 "unsupported shuffle type");
11675 if (V2.getOpcode() == ISD::UNDEF)
11679 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11683 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11684 SDValue V1 = Op.getOperand(0);
11685 SDValue V2 = Op.getOperand(1);
11686 MVT VT = Op.getSimpleValueType();
11687 unsigned NumElems = VT.getVectorNumElements();
11689 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11690 // operand of these instructions is only memory, so check if there's a
11691 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11693 bool CanFoldLoad = false;
11695 // Trivial case, when V2 comes from a load.
11696 if (MayFoldVectorLoad(V2))
11697 CanFoldLoad = true;
11699 // When V1 is a load, it can be folded later into a store in isel, example:
11700 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11702 // (MOVLPSmr addr:$src1, VR128:$src2)
11703 // So, recognize this potential and also use MOVLPS or MOVLPD
11704 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11705 CanFoldLoad = true;
11707 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11709 if (HasSSE2 && NumElems == 2)
11710 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11713 // If we don't care about the second element, proceed to use movss.
11714 if (SVOp->getMaskElt(1) != -1)
11715 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11718 // movl and movlp will both match v2i64, but v2i64 is never matched by
11719 // movl earlier because we make it strict to avoid messing with the movlp load
11720 // folding logic (see the code above getMOVLP call). Match it here then,
11721 // this is horrible, but will stay like this until we move all shuffle
11722 // matching to x86 specific nodes. Note that for the 1st condition all
11723 // types are matched with movsd.
11725 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11726 // as to remove this logic from here, as much as possible
11727 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11728 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11729 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11732 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11734 // Invert the operand order and use SHUFPS to match it.
11735 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11736 getShuffleSHUFImmediate(SVOp), DAG);
11739 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11740 SelectionDAG &DAG) {
11742 MVT VT = Load->getSimpleValueType(0);
11743 MVT EVT = VT.getVectorElementType();
11744 SDValue Addr = Load->getOperand(1);
11745 SDValue NewAddr = DAG.getNode(
11746 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11747 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11750 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11751 DAG.getMachineFunction().getMachineMemOperand(
11752 Load->getMemOperand(), 0, EVT.getStoreSize()));
11756 // It is only safe to call this function if isINSERTPSMask is true for
11757 // this shufflevector mask.
11758 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11759 SelectionDAG &DAG) {
11760 // Generate an insertps instruction when inserting an f32 from memory onto a
11761 // v4f32 or when copying a member from one v4f32 to another.
11762 // We also use it for transferring i32 from one register to another,
11763 // since it simply copies the same bits.
11764 // If we're transferring an i32 from memory to a specific element in a
11765 // register, we output a generic DAG that will match the PINSRD
11767 MVT VT = SVOp->getSimpleValueType(0);
11768 MVT EVT = VT.getVectorElementType();
11769 SDValue V1 = SVOp->getOperand(0);
11770 SDValue V2 = SVOp->getOperand(1);
11771 auto Mask = SVOp->getMask();
11772 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11773 "unsupported vector type for insertps/pinsrd");
11775 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11776 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11777 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11781 unsigned DestIndex;
11785 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11788 // If we have 1 element from each vector, we have to check if we're
11789 // changing V1's element's place. If so, we're done. Otherwise, we
11790 // should assume we're changing V2's element's place and behave
11792 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11793 assert(DestIndex <= INT32_MAX && "truncated destination index");
11794 if (FromV1 == FromV2 &&
11795 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11799 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11802 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11803 "More than one element from V1 and from V2, or no elements from one "
11804 "of the vectors. This case should not have returned true from "
11809 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11812 // Get an index into the source vector in the range [0,4) (the mask is
11813 // in the range [0,8) because it can address V1 and V2)
11814 unsigned SrcIndex = Mask[DestIndex] % 4;
11815 if (MayFoldLoad(From)) {
11816 // Trivial case, when From comes from a load and is only used by the
11817 // shuffle. Make it use insertps from the vector that we need from that
11820 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11821 if (!NewLoad.getNode())
11824 if (EVT == MVT::f32) {
11825 // Create this as a scalar to vector to match the instruction pattern.
11826 SDValue LoadScalarToVector =
11827 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11828 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11829 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11831 } else { // EVT == MVT::i32
11832 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11833 // instruction, to match the PINSRD instruction, which loads an i32 to a
11834 // certain vector element.
11835 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11836 DAG.getConstant(DestIndex, MVT::i32));
11840 // Vector-element-to-vector
11841 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11842 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11845 // Reduce a vector shuffle to zext.
11846 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11847 SelectionDAG &DAG) {
11848 // PMOVZX is only available from SSE41.
11849 if (!Subtarget->hasSSE41())
11852 MVT VT = Op.getSimpleValueType();
11854 // Only AVX2 support 256-bit vector integer extending.
11855 if (!Subtarget->hasInt256() && VT.is256BitVector())
11858 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11860 SDValue V1 = Op.getOperand(0);
11861 SDValue V2 = Op.getOperand(1);
11862 unsigned NumElems = VT.getVectorNumElements();
11864 // Extending is an unary operation and the element type of the source vector
11865 // won't be equal to or larger than i64.
11866 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11867 VT.getVectorElementType() == MVT::i64)
11870 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11871 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11872 while ((1U << Shift) < NumElems) {
11873 if (SVOp->getMaskElt(1U << Shift) == 1)
11876 // The maximal ratio is 8, i.e. from i8 to i64.
11881 // Check the shuffle mask.
11882 unsigned Mask = (1U << Shift) - 1;
11883 for (unsigned i = 0; i != NumElems; ++i) {
11884 int EltIdx = SVOp->getMaskElt(i);
11885 if ((i & Mask) != 0 && EltIdx != -1)
11887 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11891 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11892 MVT NeVT = MVT::getIntegerVT(NBits);
11893 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11895 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11898 return DAG.getNode(ISD::BITCAST, DL, VT,
11899 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11902 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11903 SelectionDAG &DAG) {
11904 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11905 MVT VT = Op.getSimpleValueType();
11907 SDValue V1 = Op.getOperand(0);
11908 SDValue V2 = Op.getOperand(1);
11910 if (isZeroShuffle(SVOp))
11911 return getZeroVector(VT, Subtarget, DAG, dl);
11913 // Handle splat operations
11914 if (SVOp->isSplat()) {
11915 // Use vbroadcast whenever the splat comes from a foldable load
11916 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11917 if (Broadcast.getNode())
11921 // Check integer expanding shuffles.
11922 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11923 if (NewOp.getNode())
11926 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11928 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11929 VT == MVT::v32i8) {
11930 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11931 if (NewOp.getNode())
11932 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11933 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11934 // FIXME: Figure out a cleaner way to do this.
11935 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11936 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11937 if (NewOp.getNode()) {
11938 MVT NewVT = NewOp.getSimpleValueType();
11939 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11940 NewVT, true, false))
11941 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11944 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11945 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11946 if (NewOp.getNode()) {
11947 MVT NewVT = NewOp.getSimpleValueType();
11948 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11949 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11958 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11959 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11960 SDValue V1 = Op.getOperand(0);
11961 SDValue V2 = Op.getOperand(1);
11962 MVT VT = Op.getSimpleValueType();
11964 unsigned NumElems = VT.getVectorNumElements();
11965 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11966 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11967 bool V1IsSplat = false;
11968 bool V2IsSplat = false;
11969 bool HasSSE2 = Subtarget->hasSSE2();
11970 bool HasFp256 = Subtarget->hasFp256();
11971 bool HasInt256 = Subtarget->hasInt256();
11972 MachineFunction &MF = DAG.getMachineFunction();
11973 bool OptForSize = MF.getFunction()->getAttributes().
11974 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11976 // Check if we should use the experimental vector shuffle lowering. If so,
11977 // delegate completely to that code path.
11978 if (ExperimentalVectorShuffleLowering)
11979 return lowerVectorShuffle(Op, Subtarget, DAG);
11981 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11983 if (V1IsUndef && V2IsUndef)
11984 return DAG.getUNDEF(VT);
11986 // When we create a shuffle node we put the UNDEF node to second operand,
11987 // but in some cases the first operand may be transformed to UNDEF.
11988 // In this case we should just commute the node.
11990 return DAG.getCommutedVectorShuffle(*SVOp);
11992 // Vector shuffle lowering takes 3 steps:
11994 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11995 // narrowing and commutation of operands should be handled.
11996 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11998 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11999 // so the shuffle can be broken into other shuffles and the legalizer can
12000 // try the lowering again.
12002 // The general idea is that no vector_shuffle operation should be left to
12003 // be matched during isel, all of them must be converted to a target specific
12006 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12007 // narrowing and commutation of operands should be handled. The actual code
12008 // doesn't include all of those, work in progress...
12009 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12010 if (NewOp.getNode())
12013 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12015 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12016 // unpckh_undef). Only use pshufd if speed is more important than size.
12017 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12018 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12019 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12020 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12022 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12023 V2IsUndef && MayFoldVectorLoad(V1))
12024 return getMOVDDup(Op, dl, V1, DAG);
12026 if (isMOVHLPS_v_undef_Mask(M, VT))
12027 return getMOVHighToLow(Op, dl, DAG);
12029 // Use to match splats
12030 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12031 (VT == MVT::v2f64 || VT == MVT::v2i64))
12032 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12034 if (isPSHUFDMask(M, VT)) {
12035 // The actual implementation will match the mask in the if above and then
12036 // during isel it can match several different instructions, not only pshufd
12037 // as its name says, sad but true, emulate the behavior for now...
12038 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12039 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12041 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12043 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12044 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12046 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12047 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12050 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12054 if (isPALIGNRMask(M, VT, Subtarget))
12055 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12056 getShufflePALIGNRImmediate(SVOp),
12059 if (isVALIGNMask(M, VT, Subtarget))
12060 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12061 getShuffleVALIGNImmediate(SVOp),
12064 // Check if this can be converted into a logical shift.
12065 bool isLeft = false;
12066 unsigned ShAmt = 0;
12068 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12069 if (isShift && ShVal.hasOneUse()) {
12070 // If the shifted value has multiple uses, it may be cheaper to use
12071 // v_set0 + movlhps or movhlps, etc.
12072 MVT EltVT = VT.getVectorElementType();
12073 ShAmt *= EltVT.getSizeInBits();
12074 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12077 if (isMOVLMask(M, VT)) {
12078 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12079 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12080 if (!isMOVLPMask(M, VT)) {
12081 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12082 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12084 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12085 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12089 // FIXME: fold these into legal mask.
12090 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12091 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12093 if (isMOVHLPSMask(M, VT))
12094 return getMOVHighToLow(Op, dl, DAG);
12096 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12097 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12099 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12100 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12102 if (isMOVLPMask(M, VT))
12103 return getMOVLP(Op, dl, DAG, HasSSE2);
12105 if (ShouldXformToMOVHLPS(M, VT) ||
12106 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12107 return DAG.getCommutedVectorShuffle(*SVOp);
12110 // No better options. Use a vshldq / vsrldq.
12111 MVT EltVT = VT.getVectorElementType();
12112 ShAmt *= EltVT.getSizeInBits();
12113 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12116 bool Commuted = false;
12117 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12118 // 1,1,1,1 -> v8i16 though.
12119 BitVector UndefElements;
12120 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12121 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12123 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12124 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12127 // Canonicalize the splat or undef, if present, to be on the RHS.
12128 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12129 CommuteVectorShuffleMask(M, NumElems);
12131 std::swap(V1IsSplat, V2IsSplat);
12135 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12136 // Shuffling low element of v1 into undef, just return v1.
12139 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12140 // the instruction selector will not match, so get a canonical MOVL with
12141 // swapped operands to undo the commute.
12142 return getMOVL(DAG, dl, VT, V2, V1);
12145 if (isUNPCKLMask(M, VT, HasInt256))
12146 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12148 if (isUNPCKHMask(M, VT, HasInt256))
12149 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12152 // Normalize mask so all entries that point to V2 points to its first
12153 // element then try to match unpck{h|l} again. If match, return a
12154 // new vector_shuffle with the corrected mask.p
12155 SmallVector<int, 8> NewMask(M.begin(), M.end());
12156 NormalizeMask(NewMask, NumElems);
12157 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12158 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12159 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12160 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12164 // Commute is back and try unpck* again.
12165 // FIXME: this seems wrong.
12166 CommuteVectorShuffleMask(M, NumElems);
12168 std::swap(V1IsSplat, V2IsSplat);
12170 if (isUNPCKLMask(M, VT, HasInt256))
12171 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12173 if (isUNPCKHMask(M, VT, HasInt256))
12174 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12177 // Normalize the node to match x86 shuffle ops if needed
12178 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12179 return DAG.getCommutedVectorShuffle(*SVOp);
12181 // The checks below are all present in isShuffleMaskLegal, but they are
12182 // inlined here right now to enable us to directly emit target specific
12183 // nodes, and remove one by one until they don't return Op anymore.
12185 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12186 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12187 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12188 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12191 if (isPSHUFHWMask(M, VT, HasInt256))
12192 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12193 getShufflePSHUFHWImmediate(SVOp),
12196 if (isPSHUFLWMask(M, VT, HasInt256))
12197 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12198 getShufflePSHUFLWImmediate(SVOp),
12201 unsigned MaskValue;
12202 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12204 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12206 if (isSHUFPMask(M, VT))
12207 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12208 getShuffleSHUFImmediate(SVOp), DAG);
12210 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12211 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12212 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12213 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12215 //===--------------------------------------------------------------------===//
12216 // Generate target specific nodes for 128 or 256-bit shuffles only
12217 // supported in the AVX instruction set.
12220 // Handle VMOVDDUPY permutations
12221 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12222 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12224 // Handle VPERMILPS/D* permutations
12225 if (isVPERMILPMask(M, VT)) {
12226 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12227 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12228 getShuffleSHUFImmediate(SVOp), DAG);
12229 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12230 getShuffleSHUFImmediate(SVOp), DAG);
12234 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12235 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12236 Idx*(NumElems/2), DAG, dl);
12238 // Handle VPERM2F128/VPERM2I128 permutations
12239 if (isVPERM2X128Mask(M, VT, HasFp256))
12240 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12241 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12243 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12244 return getINSERTPS(SVOp, dl, DAG);
12247 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12248 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12250 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12251 VT.is512BitVector()) {
12252 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12253 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12254 SmallVector<SDValue, 16> permclMask;
12255 for (unsigned i = 0; i != NumElems; ++i) {
12256 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12259 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12261 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12262 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12263 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12264 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12265 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12268 //===--------------------------------------------------------------------===//
12269 // Since no target specific shuffle was selected for this generic one,
12270 // lower it into other known shuffles. FIXME: this isn't true yet, but
12271 // this is the plan.
12274 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12275 if (VT == MVT::v8i16) {
12276 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12277 if (NewOp.getNode())
12281 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12282 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12283 if (NewOp.getNode())
12287 if (VT == MVT::v16i8) {
12288 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12289 if (NewOp.getNode())
12293 if (VT == MVT::v32i8) {
12294 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12295 if (NewOp.getNode())
12299 // Handle all 128-bit wide vectors with 4 elements, and match them with
12300 // several different shuffle types.
12301 if (NumElems == 4 && VT.is128BitVector())
12302 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12304 // Handle general 256-bit shuffles
12305 if (VT.is256BitVector())
12306 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12311 // This function assumes its argument is a BUILD_VECTOR of constants or
12312 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12314 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12315 unsigned &MaskValue) {
12317 unsigned NumElems = BuildVector->getNumOperands();
12318 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12319 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12320 unsigned NumElemsInLane = NumElems / NumLanes;
12322 // Blend for v16i16 should be symetric for the both lanes.
12323 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12324 SDValue EltCond = BuildVector->getOperand(i);
12325 SDValue SndLaneEltCond =
12326 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12328 int Lane1Cond = -1, Lane2Cond = -1;
12329 if (isa<ConstantSDNode>(EltCond))
12330 Lane1Cond = !isZero(EltCond);
12331 if (isa<ConstantSDNode>(SndLaneEltCond))
12332 Lane2Cond = !isZero(SndLaneEltCond);
12334 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12335 // Lane1Cond != 0, means we want the first argument.
12336 // Lane1Cond == 0, means we want the second argument.
12337 // The encoding of this argument is 0 for the first argument, 1
12338 // for the second. Therefore, invert the condition.
12339 MaskValue |= !Lane1Cond << i;
12340 else if (Lane1Cond < 0)
12341 MaskValue |= !Lane2Cond << i;
12348 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12350 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12351 SelectionDAG &DAG) {
12352 SDValue Cond = Op.getOperand(0);
12353 SDValue LHS = Op.getOperand(1);
12354 SDValue RHS = Op.getOperand(2);
12356 MVT VT = Op.getSimpleValueType();
12357 MVT EltVT = VT.getVectorElementType();
12358 unsigned NumElems = VT.getVectorNumElements();
12360 // There is no blend with immediate in AVX-512.
12361 if (VT.is512BitVector())
12364 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12366 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12369 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12372 // Check the mask for BLEND and build the value.
12373 unsigned MaskValue = 0;
12374 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12377 // Convert i32 vectors to floating point if it is not AVX2.
12378 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12380 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12381 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12383 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12384 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12387 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12388 DAG.getConstant(MaskValue, MVT::i32));
12389 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12392 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12393 // A vselect where all conditions and data are constants can be optimized into
12394 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12395 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12396 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12397 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12400 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12401 if (BlendOp.getNode())
12404 // Some types for vselect were previously set to Expand, not Legal or
12405 // Custom. Return an empty SDValue so we fall-through to Expand, after
12406 // the Custom lowering phase.
12407 MVT VT = Op.getSimpleValueType();
12408 switch (VT.SimpleTy) {
12413 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12418 // We couldn't create a "Blend with immediate" node.
12419 // This node should still be legal, but we'll have to emit a blendv*
12424 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12425 MVT VT = Op.getSimpleValueType();
12428 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12431 if (VT.getSizeInBits() == 8) {
12432 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12433 Op.getOperand(0), Op.getOperand(1));
12434 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12435 DAG.getValueType(VT));
12436 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12439 if (VT.getSizeInBits() == 16) {
12440 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12441 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12443 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12444 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12445 DAG.getNode(ISD::BITCAST, dl,
12448 Op.getOperand(1)));
12449 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12450 Op.getOperand(0), Op.getOperand(1));
12451 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12452 DAG.getValueType(VT));
12453 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12456 if (VT == MVT::f32) {
12457 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12458 // the result back to FR32 register. It's only worth matching if the
12459 // result has a single use which is a store or a bitcast to i32. And in
12460 // the case of a store, it's not worth it if the index is a constant 0,
12461 // because a MOVSSmr can be used instead, which is smaller and faster.
12462 if (!Op.hasOneUse())
12464 SDNode *User = *Op.getNode()->use_begin();
12465 if ((User->getOpcode() != ISD::STORE ||
12466 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12467 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12468 (User->getOpcode() != ISD::BITCAST ||
12469 User->getValueType(0) != MVT::i32))
12471 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12472 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12475 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12478 if (VT == MVT::i32 || VT == MVT::i64) {
12479 // ExtractPS/pextrq works with constant index.
12480 if (isa<ConstantSDNode>(Op.getOperand(1)))
12486 /// Extract one bit from mask vector, like v16i1 or v8i1.
12487 /// AVX-512 feature.
12489 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12490 SDValue Vec = Op.getOperand(0);
12492 MVT VecVT = Vec.getSimpleValueType();
12493 SDValue Idx = Op.getOperand(1);
12494 MVT EltVT = Op.getSimpleValueType();
12496 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12498 // variable index can't be handled in mask registers,
12499 // extend vector to VR512
12500 if (!isa<ConstantSDNode>(Idx)) {
12501 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12502 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12503 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12504 ExtVT.getVectorElementType(), Ext, Idx);
12505 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12508 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12509 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12510 unsigned MaxSift = rc->getSize()*8 - 1;
12511 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12512 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12513 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12514 DAG.getConstant(MaxSift, MVT::i8));
12515 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12516 DAG.getIntPtrConstant(0));
12520 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12521 SelectionDAG &DAG) const {
12523 SDValue Vec = Op.getOperand(0);
12524 MVT VecVT = Vec.getSimpleValueType();
12525 SDValue Idx = Op.getOperand(1);
12527 if (Op.getSimpleValueType() == MVT::i1)
12528 return ExtractBitFromMaskVector(Op, DAG);
12530 if (!isa<ConstantSDNode>(Idx)) {
12531 if (VecVT.is512BitVector() ||
12532 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12533 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12536 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12537 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12538 MaskEltVT.getSizeInBits());
12540 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12541 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12542 getZeroVector(MaskVT, Subtarget, DAG, dl),
12543 Idx, DAG.getConstant(0, getPointerTy()));
12544 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12545 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12546 Perm, DAG.getConstant(0, getPointerTy()));
12551 // If this is a 256-bit vector result, first extract the 128-bit vector and
12552 // then extract the element from the 128-bit vector.
12553 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12555 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12556 // Get the 128-bit vector.
12557 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12558 MVT EltVT = VecVT.getVectorElementType();
12560 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12562 //if (IdxVal >= NumElems/2)
12563 // IdxVal -= NumElems/2;
12564 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12565 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12566 DAG.getConstant(IdxVal, MVT::i32));
12569 assert(VecVT.is128BitVector() && "Unexpected vector length");
12571 if (Subtarget->hasSSE41()) {
12572 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12577 MVT VT = Op.getSimpleValueType();
12578 // TODO: handle v16i8.
12579 if (VT.getSizeInBits() == 16) {
12580 SDValue Vec = Op.getOperand(0);
12581 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12583 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12584 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12585 DAG.getNode(ISD::BITCAST, dl,
12587 Op.getOperand(1)));
12588 // Transform it so it match pextrw which produces a 32-bit result.
12589 MVT EltVT = MVT::i32;
12590 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12591 Op.getOperand(0), Op.getOperand(1));
12592 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12593 DAG.getValueType(VT));
12594 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12597 if (VT.getSizeInBits() == 32) {
12598 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12602 // SHUFPS the element to the lowest double word, then movss.
12603 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12604 MVT VVT = Op.getOperand(0).getSimpleValueType();
12605 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12606 DAG.getUNDEF(VVT), Mask);
12607 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12608 DAG.getIntPtrConstant(0));
12611 if (VT.getSizeInBits() == 64) {
12612 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12613 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12614 // to match extract_elt for f64.
12615 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12619 // UNPCKHPD the element to the lowest double word, then movsd.
12620 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12621 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12622 int Mask[2] = { 1, -1 };
12623 MVT VVT = Op.getOperand(0).getSimpleValueType();
12624 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12625 DAG.getUNDEF(VVT), Mask);
12626 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12627 DAG.getIntPtrConstant(0));
12633 /// Insert one bit to mask vector, like v16i1 or v8i1.
12634 /// AVX-512 feature.
12636 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12638 SDValue Vec = Op.getOperand(0);
12639 SDValue Elt = Op.getOperand(1);
12640 SDValue Idx = Op.getOperand(2);
12641 MVT VecVT = Vec.getSimpleValueType();
12643 if (!isa<ConstantSDNode>(Idx)) {
12644 // Non constant index. Extend source and destination,
12645 // insert element and then truncate the result.
12646 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12647 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12648 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12649 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12650 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12651 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12654 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12655 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12656 if (Vec.getOpcode() == ISD::UNDEF)
12657 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12658 DAG.getConstant(IdxVal, MVT::i8));
12659 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12660 unsigned MaxSift = rc->getSize()*8 - 1;
12661 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12662 DAG.getConstant(MaxSift, MVT::i8));
12663 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12664 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12665 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12668 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12669 SelectionDAG &DAG) const {
12670 MVT VT = Op.getSimpleValueType();
12671 MVT EltVT = VT.getVectorElementType();
12673 if (EltVT == MVT::i1)
12674 return InsertBitToMaskVector(Op, DAG);
12677 SDValue N0 = Op.getOperand(0);
12678 SDValue N1 = Op.getOperand(1);
12679 SDValue N2 = Op.getOperand(2);
12680 if (!isa<ConstantSDNode>(N2))
12682 auto *N2C = cast<ConstantSDNode>(N2);
12683 unsigned IdxVal = N2C->getZExtValue();
12685 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12686 // into that, and then insert the subvector back into the result.
12687 if (VT.is256BitVector() || VT.is512BitVector()) {
12688 // Get the desired 128-bit vector half.
12689 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12691 // Insert the element into the desired half.
12692 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12693 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12695 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12696 DAG.getConstant(IdxIn128, MVT::i32));
12698 // Insert the changed part back to the 256-bit vector
12699 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12701 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12703 if (Subtarget->hasSSE41()) {
12704 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12706 if (VT == MVT::v8i16) {
12707 Opc = X86ISD::PINSRW;
12709 assert(VT == MVT::v16i8);
12710 Opc = X86ISD::PINSRB;
12713 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12715 if (N1.getValueType() != MVT::i32)
12716 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12717 if (N2.getValueType() != MVT::i32)
12718 N2 = DAG.getIntPtrConstant(IdxVal);
12719 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12722 if (EltVT == MVT::f32) {
12723 // Bits [7:6] of the constant are the source select. This will always be
12724 // zero here. The DAG Combiner may combine an extract_elt index into
12726 // bits. For example (insert (extract, 3), 2) could be matched by
12728 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12729 // Bits [5:4] of the constant are the destination select. This is the
12730 // value of the incoming immediate.
12731 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12732 // combine either bitwise AND or insert of float 0.0 to set these bits.
12733 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12734 // Create this as a scalar to vector..
12735 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12736 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12739 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12740 // PINSR* works with constant index.
12745 if (EltVT == MVT::i8)
12748 if (EltVT.getSizeInBits() == 16) {
12749 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12750 // as its second argument.
12751 if (N1.getValueType() != MVT::i32)
12752 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12753 if (N2.getValueType() != MVT::i32)
12754 N2 = DAG.getIntPtrConstant(IdxVal);
12755 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12760 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12762 MVT OpVT = Op.getSimpleValueType();
12764 // If this is a 256-bit vector result, first insert into a 128-bit
12765 // vector and then insert into the 256-bit vector.
12766 if (!OpVT.is128BitVector()) {
12767 // Insert into a 128-bit vector.
12768 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12769 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12770 OpVT.getVectorNumElements() / SizeFactor);
12772 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12774 // Insert the 128-bit vector.
12775 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12778 if (OpVT == MVT::v1i64 &&
12779 Op.getOperand(0).getValueType() == MVT::i64)
12780 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12782 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12783 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12784 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12785 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12788 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12789 // a simple subregister reference or explicit instructions to grab
12790 // upper bits of a vector.
12791 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12792 SelectionDAG &DAG) {
12794 SDValue In = Op.getOperand(0);
12795 SDValue Idx = Op.getOperand(1);
12796 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12797 MVT ResVT = Op.getSimpleValueType();
12798 MVT InVT = In.getSimpleValueType();
12800 if (Subtarget->hasFp256()) {
12801 if (ResVT.is128BitVector() &&
12802 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12803 isa<ConstantSDNode>(Idx)) {
12804 return Extract128BitVector(In, IdxVal, DAG, dl);
12806 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12807 isa<ConstantSDNode>(Idx)) {
12808 return Extract256BitVector(In, IdxVal, DAG, dl);
12814 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12815 // simple superregister reference or explicit instructions to insert
12816 // the upper bits of a vector.
12817 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12818 SelectionDAG &DAG) {
12819 if (Subtarget->hasFp256()) {
12820 SDLoc dl(Op.getNode());
12821 SDValue Vec = Op.getNode()->getOperand(0);
12822 SDValue SubVec = Op.getNode()->getOperand(1);
12823 SDValue Idx = Op.getNode()->getOperand(2);
12825 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12826 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12827 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12828 isa<ConstantSDNode>(Idx)) {
12829 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12830 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12833 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12834 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12835 isa<ConstantSDNode>(Idx)) {
12836 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12837 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12843 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12844 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12845 // one of the above mentioned nodes. It has to be wrapped because otherwise
12846 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12847 // be used to form addressing mode. These wrapped nodes will be selected
12850 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12851 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12853 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12854 // global base reg.
12855 unsigned char OpFlag = 0;
12856 unsigned WrapperKind = X86ISD::Wrapper;
12857 CodeModel::Model M = DAG.getTarget().getCodeModel();
12859 if (Subtarget->isPICStyleRIPRel() &&
12860 (M == CodeModel::Small || M == CodeModel::Kernel))
12861 WrapperKind = X86ISD::WrapperRIP;
12862 else if (Subtarget->isPICStyleGOT())
12863 OpFlag = X86II::MO_GOTOFF;
12864 else if (Subtarget->isPICStyleStubPIC())
12865 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12867 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12868 CP->getAlignment(),
12869 CP->getOffset(), OpFlag);
12871 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12872 // With PIC, the address is actually $g + Offset.
12874 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12875 DAG.getNode(X86ISD::GlobalBaseReg,
12876 SDLoc(), getPointerTy()),
12883 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12884 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12886 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12887 // global base reg.
12888 unsigned char OpFlag = 0;
12889 unsigned WrapperKind = X86ISD::Wrapper;
12890 CodeModel::Model M = DAG.getTarget().getCodeModel();
12892 if (Subtarget->isPICStyleRIPRel() &&
12893 (M == CodeModel::Small || M == CodeModel::Kernel))
12894 WrapperKind = X86ISD::WrapperRIP;
12895 else if (Subtarget->isPICStyleGOT())
12896 OpFlag = X86II::MO_GOTOFF;
12897 else if (Subtarget->isPICStyleStubPIC())
12898 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12900 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12903 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12905 // With PIC, the address is actually $g + Offset.
12907 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12908 DAG.getNode(X86ISD::GlobalBaseReg,
12909 SDLoc(), getPointerTy()),
12916 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12917 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12919 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12920 // global base reg.
12921 unsigned char OpFlag = 0;
12922 unsigned WrapperKind = X86ISD::Wrapper;
12923 CodeModel::Model M = DAG.getTarget().getCodeModel();
12925 if (Subtarget->isPICStyleRIPRel() &&
12926 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12927 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12928 OpFlag = X86II::MO_GOTPCREL;
12929 WrapperKind = X86ISD::WrapperRIP;
12930 } else if (Subtarget->isPICStyleGOT()) {
12931 OpFlag = X86II::MO_GOT;
12932 } else if (Subtarget->isPICStyleStubPIC()) {
12933 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12934 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12935 OpFlag = X86II::MO_DARWIN_NONLAZY;
12938 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12941 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12943 // With PIC, the address is actually $g + Offset.
12944 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12945 !Subtarget->is64Bit()) {
12946 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12947 DAG.getNode(X86ISD::GlobalBaseReg,
12948 SDLoc(), getPointerTy()),
12952 // For symbols that require a load from a stub to get the address, emit the
12954 if (isGlobalStubReference(OpFlag))
12955 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12956 MachinePointerInfo::getGOT(), false, false, false, 0);
12962 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12963 // Create the TargetBlockAddressAddress node.
12964 unsigned char OpFlags =
12965 Subtarget->ClassifyBlockAddressReference();
12966 CodeModel::Model M = DAG.getTarget().getCodeModel();
12967 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12968 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12970 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12973 if (Subtarget->isPICStyleRIPRel() &&
12974 (M == CodeModel::Small || M == CodeModel::Kernel))
12975 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12977 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12979 // With PIC, the address is actually $g + Offset.
12980 if (isGlobalRelativeToPICBase(OpFlags)) {
12981 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12982 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12990 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12991 int64_t Offset, SelectionDAG &DAG) const {
12992 // Create the TargetGlobalAddress node, folding in the constant
12993 // offset if it is legal.
12994 unsigned char OpFlags =
12995 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12996 CodeModel::Model M = DAG.getTarget().getCodeModel();
12998 if (OpFlags == X86II::MO_NO_FLAG &&
12999 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13000 // A direct static reference to a global.
13001 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13004 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13007 if (Subtarget->isPICStyleRIPRel() &&
13008 (M == CodeModel::Small || M == CodeModel::Kernel))
13009 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13011 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13013 // With PIC, the address is actually $g + Offset.
13014 if (isGlobalRelativeToPICBase(OpFlags)) {
13015 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13016 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13020 // For globals that require a load from a stub to get the address, emit the
13022 if (isGlobalStubReference(OpFlags))
13023 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13024 MachinePointerInfo::getGOT(), false, false, false, 0);
13026 // If there was a non-zero offset that we didn't fold, create an explicit
13027 // addition for it.
13029 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13030 DAG.getConstant(Offset, getPointerTy()));
13036 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13037 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13038 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13039 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13043 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13044 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13045 unsigned char OperandFlags, bool LocalDynamic = false) {
13046 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13047 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13049 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13050 GA->getValueType(0),
13054 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13058 SDValue Ops[] = { Chain, TGA, *InFlag };
13059 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13061 SDValue Ops[] = { Chain, TGA };
13062 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13065 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13066 MFI->setAdjustsStack(true);
13067 MFI->setHasCalls(true);
13069 SDValue Flag = Chain.getValue(1);
13070 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13073 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13075 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13078 SDLoc dl(GA); // ? function entry point might be better
13079 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13080 DAG.getNode(X86ISD::GlobalBaseReg,
13081 SDLoc(), PtrVT), InFlag);
13082 InFlag = Chain.getValue(1);
13084 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13087 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13089 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13091 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13092 X86::RAX, X86II::MO_TLSGD);
13095 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13101 // Get the start address of the TLS block for this module.
13102 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13103 .getInfo<X86MachineFunctionInfo>();
13104 MFI->incNumLocalDynamicTLSAccesses();
13108 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13109 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13112 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13113 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13114 InFlag = Chain.getValue(1);
13115 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13116 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13119 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13123 unsigned char OperandFlags = X86II::MO_DTPOFF;
13124 unsigned WrapperKind = X86ISD::Wrapper;
13125 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13126 GA->getValueType(0),
13127 GA->getOffset(), OperandFlags);
13128 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13130 // Add x@dtpoff with the base.
13131 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13134 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13135 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13136 const EVT PtrVT, TLSModel::Model model,
13137 bool is64Bit, bool isPIC) {
13140 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13141 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13142 is64Bit ? 257 : 256));
13144 SDValue ThreadPointer =
13145 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13146 MachinePointerInfo(Ptr), false, false, false, 0);
13148 unsigned char OperandFlags = 0;
13149 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13151 unsigned WrapperKind = X86ISD::Wrapper;
13152 if (model == TLSModel::LocalExec) {
13153 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13154 } else if (model == TLSModel::InitialExec) {
13156 OperandFlags = X86II::MO_GOTTPOFF;
13157 WrapperKind = X86ISD::WrapperRIP;
13159 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13162 llvm_unreachable("Unexpected model");
13165 // emit "addl x@ntpoff,%eax" (local exec)
13166 // or "addl x@indntpoff,%eax" (initial exec)
13167 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13169 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13170 GA->getOffset(), OperandFlags);
13171 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13173 if (model == TLSModel::InitialExec) {
13174 if (isPIC && !is64Bit) {
13175 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13176 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13180 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13181 MachinePointerInfo::getGOT(), false, false, false, 0);
13184 // The address of the thread local variable is the add of the thread
13185 // pointer with the offset of the variable.
13186 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13190 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13192 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13193 const GlobalValue *GV = GA->getGlobal();
13195 if (Subtarget->isTargetELF()) {
13196 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13199 case TLSModel::GeneralDynamic:
13200 if (Subtarget->is64Bit())
13201 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13202 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13203 case TLSModel::LocalDynamic:
13204 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13205 Subtarget->is64Bit());
13206 case TLSModel::InitialExec:
13207 case TLSModel::LocalExec:
13208 return LowerToTLSExecModel(
13209 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13210 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13212 llvm_unreachable("Unknown TLS model.");
13215 if (Subtarget->isTargetDarwin()) {
13216 // Darwin only has one model of TLS. Lower to that.
13217 unsigned char OpFlag = 0;
13218 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13219 X86ISD::WrapperRIP : X86ISD::Wrapper;
13221 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13222 // global base reg.
13223 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13224 !Subtarget->is64Bit();
13226 OpFlag = X86II::MO_TLVP_PIC_BASE;
13228 OpFlag = X86II::MO_TLVP;
13230 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13231 GA->getValueType(0),
13232 GA->getOffset(), OpFlag);
13233 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13235 // With PIC32, the address is actually $g + Offset.
13237 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13238 DAG.getNode(X86ISD::GlobalBaseReg,
13239 SDLoc(), getPointerTy()),
13242 // Lowering the machine isd will make sure everything is in the right
13244 SDValue Chain = DAG.getEntryNode();
13245 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13246 SDValue Args[] = { Chain, Offset };
13247 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13249 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13250 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13251 MFI->setAdjustsStack(true);
13253 // And our return value (tls address) is in the standard call return value
13255 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13256 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13257 Chain.getValue(1));
13260 if (Subtarget->isTargetKnownWindowsMSVC() ||
13261 Subtarget->isTargetWindowsGNU()) {
13262 // Just use the implicit TLS architecture
13263 // Need to generate someting similar to:
13264 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13266 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13267 // mov rcx, qword [rdx+rcx*8]
13268 // mov eax, .tls$:tlsvar
13269 // [rax+rcx] contains the address
13270 // Windows 64bit: gs:0x58
13271 // Windows 32bit: fs:__tls_array
13274 SDValue Chain = DAG.getEntryNode();
13276 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13277 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13278 // use its literal value of 0x2C.
13279 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13280 ? Type::getInt8PtrTy(*DAG.getContext(),
13282 : Type::getInt32PtrTy(*DAG.getContext(),
13286 Subtarget->is64Bit()
13287 ? DAG.getIntPtrConstant(0x58)
13288 : (Subtarget->isTargetWindowsGNU()
13289 ? DAG.getIntPtrConstant(0x2C)
13290 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13292 SDValue ThreadPointer =
13293 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13294 MachinePointerInfo(Ptr), false, false, false, 0);
13296 // Load the _tls_index variable
13297 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13298 if (Subtarget->is64Bit())
13299 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13300 IDX, MachinePointerInfo(), MVT::i32,
13301 false, false, false, 0);
13303 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13304 false, false, false, 0);
13306 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13308 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13310 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13311 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13312 false, false, false, 0);
13314 // Get the offset of start of .tls section
13315 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13316 GA->getValueType(0),
13317 GA->getOffset(), X86II::MO_SECREL);
13318 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13320 // The address of the thread local variable is the add of the thread
13321 // pointer with the offset of the variable.
13322 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13325 llvm_unreachable("TLS not implemented for this target.");
13328 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13329 /// and take a 2 x i32 value to shift plus a shift amount.
13330 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13331 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13332 MVT VT = Op.getSimpleValueType();
13333 unsigned VTBits = VT.getSizeInBits();
13335 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13336 SDValue ShOpLo = Op.getOperand(0);
13337 SDValue ShOpHi = Op.getOperand(1);
13338 SDValue ShAmt = Op.getOperand(2);
13339 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13340 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13342 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13343 DAG.getConstant(VTBits - 1, MVT::i8));
13344 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13345 DAG.getConstant(VTBits - 1, MVT::i8))
13346 : DAG.getConstant(0, VT);
13348 SDValue Tmp2, Tmp3;
13349 if (Op.getOpcode() == ISD::SHL_PARTS) {
13350 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13351 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13353 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13354 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13357 // If the shift amount is larger or equal than the width of a part we can't
13358 // rely on the results of shld/shrd. Insert a test and select the appropriate
13359 // values for large shift amounts.
13360 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13361 DAG.getConstant(VTBits, MVT::i8));
13362 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13363 AndNode, DAG.getConstant(0, MVT::i8));
13366 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13367 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13368 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13370 if (Op.getOpcode() == ISD::SHL_PARTS) {
13371 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13372 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13374 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13375 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13378 SDValue Ops[2] = { Lo, Hi };
13379 return DAG.getMergeValues(Ops, dl);
13382 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13383 SelectionDAG &DAG) const {
13384 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13387 if (SrcVT.isVector()) {
13388 if (SrcVT.getVectorElementType() == MVT::i1) {
13389 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13390 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13391 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13392 Op.getOperand(0)));
13397 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13398 "Unknown SINT_TO_FP to lower!");
13400 // These are really Legal; return the operand so the caller accepts it as
13402 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13404 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13405 Subtarget->is64Bit()) {
13409 unsigned Size = SrcVT.getSizeInBits()/8;
13410 MachineFunction &MF = DAG.getMachineFunction();
13411 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13412 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13413 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13415 MachinePointerInfo::getFixedStack(SSFI),
13417 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13420 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13422 SelectionDAG &DAG) const {
13426 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13428 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13430 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13432 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13434 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13435 MachineMemOperand *MMO;
13437 int SSFI = FI->getIndex();
13439 DAG.getMachineFunction()
13440 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13441 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13443 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13444 StackSlot = StackSlot.getOperand(1);
13446 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13447 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13449 Tys, Ops, SrcVT, MMO);
13452 Chain = Result.getValue(1);
13453 SDValue InFlag = Result.getValue(2);
13455 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13456 // shouldn't be necessary except that RFP cannot be live across
13457 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13458 MachineFunction &MF = DAG.getMachineFunction();
13459 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13460 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13461 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13462 Tys = DAG.getVTList(MVT::Other);
13464 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13466 MachineMemOperand *MMO =
13467 DAG.getMachineFunction()
13468 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13469 MachineMemOperand::MOStore, SSFISize, SSFISize);
13471 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13472 Ops, Op.getValueType(), MMO);
13473 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13474 MachinePointerInfo::getFixedStack(SSFI),
13475 false, false, false, 0);
13481 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13482 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13483 SelectionDAG &DAG) const {
13484 // This algorithm is not obvious. Here it is what we're trying to output:
13487 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13488 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13490 haddpd %xmm0, %xmm0
13492 pshufd $0x4e, %xmm0, %xmm1
13498 LLVMContext *Context = DAG.getContext();
13500 // Build some magic constants.
13501 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13502 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13503 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13505 SmallVector<Constant*,2> CV1;
13507 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13508 APInt(64, 0x4330000000000000ULL))));
13510 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13511 APInt(64, 0x4530000000000000ULL))));
13512 Constant *C1 = ConstantVector::get(CV1);
13513 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13515 // Load the 64-bit value into an XMM register.
13516 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13518 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13519 MachinePointerInfo::getConstantPool(),
13520 false, false, false, 16);
13521 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13522 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13525 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13526 MachinePointerInfo::getConstantPool(),
13527 false, false, false, 16);
13528 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13529 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13532 if (Subtarget->hasSSE3()) {
13533 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13534 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13536 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13537 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13539 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13540 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13544 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13545 DAG.getIntPtrConstant(0));
13548 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13549 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13550 SelectionDAG &DAG) const {
13552 // FP constant to bias correct the final result.
13553 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13556 // Load the 32-bit value into an XMM register.
13557 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13560 // Zero out the upper parts of the register.
13561 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13563 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13564 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13565 DAG.getIntPtrConstant(0));
13567 // Or the load with the bias.
13568 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13569 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13570 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13571 MVT::v2f64, Load)),
13572 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13573 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13574 MVT::v2f64, Bias)));
13575 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13576 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13577 DAG.getIntPtrConstant(0));
13579 // Subtract the bias.
13580 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13582 // Handle final rounding.
13583 EVT DestVT = Op.getValueType();
13585 if (DestVT.bitsLT(MVT::f64))
13586 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13587 DAG.getIntPtrConstant(0));
13588 if (DestVT.bitsGT(MVT::f64))
13589 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13591 // Handle final rounding.
13595 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13596 const X86Subtarget &Subtarget) {
13597 // The algorithm is the following:
13598 // #ifdef __SSE4_1__
13599 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13600 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13601 // (uint4) 0x53000000, 0xaa);
13603 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13604 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13606 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13607 // return (float4) lo + fhi;
13610 SDValue V = Op->getOperand(0);
13611 EVT VecIntVT = V.getValueType();
13612 bool Is128 = VecIntVT == MVT::v4i32;
13613 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13614 // If we convert to something else than the supported type, e.g., to v4f64,
13616 if (VecFloatVT != Op->getValueType(0))
13619 unsigned NumElts = VecIntVT.getVectorNumElements();
13620 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13621 "Unsupported custom type");
13622 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13624 // In the #idef/#else code, we have in common:
13625 // - The vector of constants:
13631 // Create the splat vector for 0x4b000000.
13632 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13633 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13634 CstLow, CstLow, CstLow, CstLow};
13635 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13636 makeArrayRef(&CstLowArray[0], NumElts));
13637 // Create the splat vector for 0x53000000.
13638 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13639 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13640 CstHigh, CstHigh, CstHigh, CstHigh};
13641 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13642 makeArrayRef(&CstHighArray[0], NumElts));
13644 // Create the right shift.
13645 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13646 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13647 CstShift, CstShift, CstShift, CstShift};
13648 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13649 makeArrayRef(&CstShiftArray[0], NumElts));
13650 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13653 if (Subtarget.hasSSE41()) {
13654 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13655 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13656 SDValue VecCstLowBitcast =
13657 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13658 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13659 // Low will be bitcasted right away, so do not bother bitcasting back to its
13661 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13662 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13663 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13664 // (uint4) 0x53000000, 0xaa);
13665 SDValue VecCstHighBitcast =
13666 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13667 SDValue VecShiftBitcast =
13668 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13669 // High will be bitcasted right away, so do not bother bitcasting back to
13670 // its original type.
13671 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13672 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13674 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13675 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13676 CstMask, CstMask, CstMask);
13677 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13678 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13679 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13681 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13682 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13685 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13686 SDValue CstFAdd = DAG.getConstantFP(
13687 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13688 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13689 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13690 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13691 makeArrayRef(&CstFAddArray[0], NumElts));
13693 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13694 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13696 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13697 // return (float4) lo + fhi;
13698 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13699 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13702 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13703 SelectionDAG &DAG) const {
13704 SDValue N0 = Op.getOperand(0);
13705 MVT SVT = N0.getSimpleValueType();
13708 switch (SVT.SimpleTy) {
13710 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13715 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13716 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13717 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13721 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13723 llvm_unreachable(nullptr);
13726 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13727 SelectionDAG &DAG) const {
13728 SDValue N0 = Op.getOperand(0);
13731 if (Op.getValueType().isVector())
13732 return lowerUINT_TO_FP_vec(Op, DAG);
13734 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13735 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13736 // the optimization here.
13737 if (DAG.SignBitIsZero(N0))
13738 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13740 MVT SrcVT = N0.getSimpleValueType();
13741 MVT DstVT = Op.getSimpleValueType();
13742 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13743 return LowerUINT_TO_FP_i64(Op, DAG);
13744 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13745 return LowerUINT_TO_FP_i32(Op, DAG);
13746 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13749 // Make a 64-bit buffer, and use it to build an FILD.
13750 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13751 if (SrcVT == MVT::i32) {
13752 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13753 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13754 getPointerTy(), StackSlot, WordOff);
13755 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13756 StackSlot, MachinePointerInfo(),
13758 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13759 OffsetSlot, MachinePointerInfo(),
13761 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13765 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13766 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13767 StackSlot, MachinePointerInfo(),
13769 // For i64 source, we need to add the appropriate power of 2 if the input
13770 // was negative. This is the same as the optimization in
13771 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13772 // we must be careful to do the computation in x87 extended precision, not
13773 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13774 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13775 MachineMemOperand *MMO =
13776 DAG.getMachineFunction()
13777 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13778 MachineMemOperand::MOLoad, 8, 8);
13780 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13781 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13782 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13785 APInt FF(32, 0x5F800000ULL);
13787 // Check whether the sign bit is set.
13788 SDValue SignSet = DAG.getSetCC(dl,
13789 getSetCCResultType(*DAG.getContext(), MVT::i64),
13790 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13793 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13794 SDValue FudgePtr = DAG.getConstantPool(
13795 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13798 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13799 SDValue Zero = DAG.getIntPtrConstant(0);
13800 SDValue Four = DAG.getIntPtrConstant(4);
13801 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13803 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13805 // Load the value out, extending it from f32 to f80.
13806 // FIXME: Avoid the extend by constructing the right constant pool?
13807 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13808 FudgePtr, MachinePointerInfo::getConstantPool(),
13809 MVT::f32, false, false, false, 4);
13810 // Extend everything to 80 bits to force it to be done on x87.
13811 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13812 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13815 std::pair<SDValue,SDValue>
13816 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13817 bool IsSigned, bool IsReplace) const {
13820 EVT DstTy = Op.getValueType();
13822 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13823 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13827 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13828 DstTy.getSimpleVT() >= MVT::i16 &&
13829 "Unknown FP_TO_INT to lower!");
13831 // These are really Legal.
13832 if (DstTy == MVT::i32 &&
13833 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13834 return std::make_pair(SDValue(), SDValue());
13835 if (Subtarget->is64Bit() &&
13836 DstTy == MVT::i64 &&
13837 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13838 return std::make_pair(SDValue(), SDValue());
13840 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13841 // stack slot, or into the FTOL runtime function.
13842 MachineFunction &MF = DAG.getMachineFunction();
13843 unsigned MemSize = DstTy.getSizeInBits()/8;
13844 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13845 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13848 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13849 Opc = X86ISD::WIN_FTOL;
13851 switch (DstTy.getSimpleVT().SimpleTy) {
13852 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13853 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13854 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13855 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13858 SDValue Chain = DAG.getEntryNode();
13859 SDValue Value = Op.getOperand(0);
13860 EVT TheVT = Op.getOperand(0).getValueType();
13861 // FIXME This causes a redundant load/store if the SSE-class value is already
13862 // in memory, such as if it is on the callstack.
13863 if (isScalarFPTypeInSSEReg(TheVT)) {
13864 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13865 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13866 MachinePointerInfo::getFixedStack(SSFI),
13868 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13870 Chain, StackSlot, DAG.getValueType(TheVT)
13873 MachineMemOperand *MMO =
13874 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13875 MachineMemOperand::MOLoad, MemSize, MemSize);
13876 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13877 Chain = Value.getValue(1);
13878 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13879 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13882 MachineMemOperand *MMO =
13883 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13884 MachineMemOperand::MOStore, MemSize, MemSize);
13886 if (Opc != X86ISD::WIN_FTOL) {
13887 // Build the FP_TO_INT*_IN_MEM
13888 SDValue Ops[] = { Chain, Value, StackSlot };
13889 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13891 return std::make_pair(FIST, StackSlot);
13893 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13894 DAG.getVTList(MVT::Other, MVT::Glue),
13896 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13897 MVT::i32, ftol.getValue(1));
13898 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13899 MVT::i32, eax.getValue(2));
13900 SDValue Ops[] = { eax, edx };
13901 SDValue pair = IsReplace
13902 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13903 : DAG.getMergeValues(Ops, DL);
13904 return std::make_pair(pair, SDValue());
13908 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13909 const X86Subtarget *Subtarget) {
13910 MVT VT = Op->getSimpleValueType(0);
13911 SDValue In = Op->getOperand(0);
13912 MVT InVT = In.getSimpleValueType();
13915 // Optimize vectors in AVX mode:
13918 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13919 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13920 // Concat upper and lower parts.
13923 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13924 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13925 // Concat upper and lower parts.
13928 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13929 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13930 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13933 if (Subtarget->hasInt256())
13934 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13936 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13937 SDValue Undef = DAG.getUNDEF(InVT);
13938 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13939 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13940 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13942 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13943 VT.getVectorNumElements()/2);
13945 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13946 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13948 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13951 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13952 SelectionDAG &DAG) {
13953 MVT VT = Op->getSimpleValueType(0);
13954 SDValue In = Op->getOperand(0);
13955 MVT InVT = In.getSimpleValueType();
13957 unsigned int NumElts = VT.getVectorNumElements();
13958 if (NumElts != 8 && NumElts != 16)
13961 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13962 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13964 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13965 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13966 // Now we have only mask extension
13967 assert(InVT.getVectorElementType() == MVT::i1);
13968 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13969 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13970 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13971 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13972 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13973 MachinePointerInfo::getConstantPool(),
13974 false, false, false, Alignment);
13976 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13977 if (VT.is512BitVector())
13979 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13982 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13983 SelectionDAG &DAG) {
13984 if (Subtarget->hasFp256()) {
13985 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13993 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13994 SelectionDAG &DAG) {
13996 MVT VT = Op.getSimpleValueType();
13997 SDValue In = Op.getOperand(0);
13998 MVT SVT = In.getSimpleValueType();
14000 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14001 return LowerZERO_EXTEND_AVX512(Op, DAG);
14003 if (Subtarget->hasFp256()) {
14004 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14009 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14010 VT.getVectorNumElements() != SVT.getVectorNumElements());
14014 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14016 MVT VT = Op.getSimpleValueType();
14017 SDValue In = Op.getOperand(0);
14018 MVT InVT = In.getSimpleValueType();
14020 if (VT == MVT::i1) {
14021 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14022 "Invalid scalar TRUNCATE operation");
14023 if (InVT.getSizeInBits() >= 32)
14025 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14026 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14028 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14029 "Invalid TRUNCATE operation");
14031 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14032 if (VT.getVectorElementType().getSizeInBits() >=8)
14033 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14035 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14036 unsigned NumElts = InVT.getVectorNumElements();
14037 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14038 if (InVT.getSizeInBits() < 512) {
14039 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14040 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14044 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14045 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14046 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14047 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14048 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14049 MachinePointerInfo::getConstantPool(),
14050 false, false, false, Alignment);
14051 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14052 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14053 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14056 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14057 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14058 if (Subtarget->hasInt256()) {
14059 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14060 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14061 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14063 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14064 DAG.getIntPtrConstant(0));
14067 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14068 DAG.getIntPtrConstant(0));
14069 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14070 DAG.getIntPtrConstant(2));
14071 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14072 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14073 static const int ShufMask[] = {0, 2, 4, 6};
14074 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14077 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14078 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14079 if (Subtarget->hasInt256()) {
14080 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14082 SmallVector<SDValue,32> pshufbMask;
14083 for (unsigned i = 0; i < 2; ++i) {
14084 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14085 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14086 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14087 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14088 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14089 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14090 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14091 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14092 for (unsigned j = 0; j < 8; ++j)
14093 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14095 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14096 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14097 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14099 static const int ShufMask[] = {0, 2, -1, -1};
14100 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14102 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14103 DAG.getIntPtrConstant(0));
14104 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14107 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14108 DAG.getIntPtrConstant(0));
14110 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14111 DAG.getIntPtrConstant(4));
14113 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14114 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14116 // The PSHUFB mask:
14117 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14118 -1, -1, -1, -1, -1, -1, -1, -1};
14120 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14121 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14122 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14124 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14125 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14127 // The MOVLHPS Mask:
14128 static const int ShufMask2[] = {0, 1, 4, 5};
14129 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14130 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14133 // Handle truncation of V256 to V128 using shuffles.
14134 if (!VT.is128BitVector() || !InVT.is256BitVector())
14137 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14139 unsigned NumElems = VT.getVectorNumElements();
14140 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14142 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14143 // Prepare truncation shuffle mask
14144 for (unsigned i = 0; i != NumElems; ++i)
14145 MaskVec[i] = i * 2;
14146 SDValue V = DAG.getVectorShuffle(NVT, DL,
14147 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14148 DAG.getUNDEF(NVT), &MaskVec[0]);
14149 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14150 DAG.getIntPtrConstant(0));
14153 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14154 SelectionDAG &DAG) const {
14155 assert(!Op.getSimpleValueType().isVector());
14157 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14158 /*IsSigned=*/ true, /*IsReplace=*/ false);
14159 SDValue FIST = Vals.first, StackSlot = Vals.second;
14160 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14161 if (!FIST.getNode()) return Op;
14163 if (StackSlot.getNode())
14164 // Load the result.
14165 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14166 FIST, StackSlot, MachinePointerInfo(),
14167 false, false, false, 0);
14169 // The node is the result.
14173 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14174 SelectionDAG &DAG) const {
14175 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14176 /*IsSigned=*/ false, /*IsReplace=*/ false);
14177 SDValue FIST = Vals.first, StackSlot = Vals.second;
14178 assert(FIST.getNode() && "Unexpected failure");
14180 if (StackSlot.getNode())
14181 // Load the result.
14182 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14183 FIST, StackSlot, MachinePointerInfo(),
14184 false, false, false, 0);
14186 // The node is the result.
14190 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14192 MVT VT = Op.getSimpleValueType();
14193 SDValue In = Op.getOperand(0);
14194 MVT SVT = In.getSimpleValueType();
14196 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14198 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14199 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14200 In, DAG.getUNDEF(SVT)));
14203 /// The only differences between FABS and FNEG are the mask and the logic op.
14204 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14205 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14206 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14207 "Wrong opcode for lowering FABS or FNEG.");
14209 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14211 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14212 // into an FNABS. We'll lower the FABS after that if it is still in use.
14214 for (SDNode *User : Op->uses())
14215 if (User->getOpcode() == ISD::FNEG)
14218 SDValue Op0 = Op.getOperand(0);
14219 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14222 MVT VT = Op.getSimpleValueType();
14223 // Assume scalar op for initialization; update for vector if needed.
14224 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14225 // generate a 16-byte vector constant and logic op even for the scalar case.
14226 // Using a 16-byte mask allows folding the load of the mask with
14227 // the logic op, so it can save (~4 bytes) on code size.
14229 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14230 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14231 // decide if we should generate a 16-byte constant mask when we only need 4 or
14232 // 8 bytes for the scalar case.
14233 if (VT.isVector()) {
14234 EltVT = VT.getVectorElementType();
14235 NumElts = VT.getVectorNumElements();
14238 unsigned EltBits = EltVT.getSizeInBits();
14239 LLVMContext *Context = DAG.getContext();
14240 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14242 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14243 Constant *C = ConstantInt::get(*Context, MaskElt);
14244 C = ConstantVector::getSplat(NumElts, C);
14245 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14246 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14247 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14248 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14249 MachinePointerInfo::getConstantPool(),
14250 false, false, false, Alignment);
14252 if (VT.isVector()) {
14253 // For a vector, cast operands to a vector type, perform the logic op,
14254 // and cast the result back to the original value type.
14255 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14256 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14257 SDValue Operand = IsFNABS ?
14258 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14259 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14260 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14261 return DAG.getNode(ISD::BITCAST, dl, VT,
14262 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14265 // If not vector, then scalar.
14266 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14267 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14268 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14271 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14272 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14273 LLVMContext *Context = DAG.getContext();
14274 SDValue Op0 = Op.getOperand(0);
14275 SDValue Op1 = Op.getOperand(1);
14277 MVT VT = Op.getSimpleValueType();
14278 MVT SrcVT = Op1.getSimpleValueType();
14280 // If second operand is smaller, extend it first.
14281 if (SrcVT.bitsLT(VT)) {
14282 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14285 // And if it is bigger, shrink it first.
14286 if (SrcVT.bitsGT(VT)) {
14287 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14291 // At this point the operands and the result should have the same
14292 // type, and that won't be f80 since that is not custom lowered.
14294 // First get the sign bit of second operand.
14295 SmallVector<Constant*,4> CV;
14296 if (SrcVT == MVT::f64) {
14297 const fltSemantics &Sem = APFloat::IEEEdouble;
14298 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14299 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14301 const fltSemantics &Sem = APFloat::IEEEsingle;
14302 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14303 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14304 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14305 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14307 Constant *C = ConstantVector::get(CV);
14308 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14309 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14310 MachinePointerInfo::getConstantPool(),
14311 false, false, false, 16);
14312 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14314 // Shift sign bit right or left if the two operands have different types.
14315 if (SrcVT.bitsGT(VT)) {
14316 // Op0 is MVT::f32, Op1 is MVT::f64.
14317 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14318 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14319 DAG.getConstant(32, MVT::i32));
14320 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14321 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14322 DAG.getIntPtrConstant(0));
14325 // Clear first operand sign bit.
14327 if (VT == MVT::f64) {
14328 const fltSemantics &Sem = APFloat::IEEEdouble;
14329 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14330 APInt(64, ~(1ULL << 63)))));
14331 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14333 const fltSemantics &Sem = APFloat::IEEEsingle;
14334 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14335 APInt(32, ~(1U << 31)))));
14336 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14337 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14338 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14340 C = ConstantVector::get(CV);
14341 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14342 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14343 MachinePointerInfo::getConstantPool(),
14344 false, false, false, 16);
14345 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14347 // Or the value with the sign bit.
14348 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14351 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14352 SDValue N0 = Op.getOperand(0);
14354 MVT VT = Op.getSimpleValueType();
14356 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14357 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14358 DAG.getConstant(1, VT));
14359 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14362 // Check whether an OR'd tree is PTEST-able.
14363 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14364 SelectionDAG &DAG) {
14365 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14367 if (!Subtarget->hasSSE41())
14370 if (!Op->hasOneUse())
14373 SDNode *N = Op.getNode();
14376 SmallVector<SDValue, 8> Opnds;
14377 DenseMap<SDValue, unsigned> VecInMap;
14378 SmallVector<SDValue, 8> VecIns;
14379 EVT VT = MVT::Other;
14381 // Recognize a special case where a vector is casted into wide integer to
14383 Opnds.push_back(N->getOperand(0));
14384 Opnds.push_back(N->getOperand(1));
14386 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14387 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14388 // BFS traverse all OR'd operands.
14389 if (I->getOpcode() == ISD::OR) {
14390 Opnds.push_back(I->getOperand(0));
14391 Opnds.push_back(I->getOperand(1));
14392 // Re-evaluate the number of nodes to be traversed.
14393 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14397 // Quit if a non-EXTRACT_VECTOR_ELT
14398 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14401 // Quit if without a constant index.
14402 SDValue Idx = I->getOperand(1);
14403 if (!isa<ConstantSDNode>(Idx))
14406 SDValue ExtractedFromVec = I->getOperand(0);
14407 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14408 if (M == VecInMap.end()) {
14409 VT = ExtractedFromVec.getValueType();
14410 // Quit if not 128/256-bit vector.
14411 if (!VT.is128BitVector() && !VT.is256BitVector())
14413 // Quit if not the same type.
14414 if (VecInMap.begin() != VecInMap.end() &&
14415 VT != VecInMap.begin()->first.getValueType())
14417 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14418 VecIns.push_back(ExtractedFromVec);
14420 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14423 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14424 "Not extracted from 128-/256-bit vector.");
14426 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14428 for (DenseMap<SDValue, unsigned>::const_iterator
14429 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14430 // Quit if not all elements are used.
14431 if (I->second != FullMask)
14435 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14437 // Cast all vectors into TestVT for PTEST.
14438 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14439 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14441 // If more than one full vectors are evaluated, OR them first before PTEST.
14442 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14443 // Each iteration will OR 2 nodes and append the result until there is only
14444 // 1 node left, i.e. the final OR'd value of all vectors.
14445 SDValue LHS = VecIns[Slot];
14446 SDValue RHS = VecIns[Slot + 1];
14447 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14450 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14451 VecIns.back(), VecIns.back());
14454 /// \brief return true if \c Op has a use that doesn't just read flags.
14455 static bool hasNonFlagsUse(SDValue Op) {
14456 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14458 SDNode *User = *UI;
14459 unsigned UOpNo = UI.getOperandNo();
14460 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14461 // Look pass truncate.
14462 UOpNo = User->use_begin().getOperandNo();
14463 User = *User->use_begin();
14466 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14467 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14473 /// Emit nodes that will be selected as "test Op0,Op0", or something
14475 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14476 SelectionDAG &DAG) const {
14477 if (Op.getValueType() == MVT::i1)
14478 // KORTEST instruction should be selected
14479 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14480 DAG.getConstant(0, Op.getValueType()));
14482 // CF and OF aren't always set the way we want. Determine which
14483 // of these we need.
14484 bool NeedCF = false;
14485 bool NeedOF = false;
14488 case X86::COND_A: case X86::COND_AE:
14489 case X86::COND_B: case X86::COND_BE:
14492 case X86::COND_G: case X86::COND_GE:
14493 case X86::COND_L: case X86::COND_LE:
14494 case X86::COND_O: case X86::COND_NO: {
14495 // Check if we really need to set the
14496 // Overflow flag. If NoSignedWrap is present
14497 // that is not actually needed.
14498 switch (Op->getOpcode()) {
14503 const BinaryWithFlagsSDNode *BinNode =
14504 cast<BinaryWithFlagsSDNode>(Op.getNode());
14505 if (BinNode->hasNoSignedWrap())
14515 // See if we can use the EFLAGS value from the operand instead of
14516 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14517 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14518 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14519 // Emit a CMP with 0, which is the TEST pattern.
14520 //if (Op.getValueType() == MVT::i1)
14521 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14522 // DAG.getConstant(0, MVT::i1));
14523 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14524 DAG.getConstant(0, Op.getValueType()));
14526 unsigned Opcode = 0;
14527 unsigned NumOperands = 0;
14529 // Truncate operations may prevent the merge of the SETCC instruction
14530 // and the arithmetic instruction before it. Attempt to truncate the operands
14531 // of the arithmetic instruction and use a reduced bit-width instruction.
14532 bool NeedTruncation = false;
14533 SDValue ArithOp = Op;
14534 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14535 SDValue Arith = Op->getOperand(0);
14536 // Both the trunc and the arithmetic op need to have one user each.
14537 if (Arith->hasOneUse())
14538 switch (Arith.getOpcode()) {
14545 NeedTruncation = true;
14551 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14552 // which may be the result of a CAST. We use the variable 'Op', which is the
14553 // non-casted variable when we check for possible users.
14554 switch (ArithOp.getOpcode()) {
14556 // Due to an isel shortcoming, be conservative if this add is likely to be
14557 // selected as part of a load-modify-store instruction. When the root node
14558 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14559 // uses of other nodes in the match, such as the ADD in this case. This
14560 // leads to the ADD being left around and reselected, with the result being
14561 // two adds in the output. Alas, even if none our users are stores, that
14562 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14563 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14564 // climbing the DAG back to the root, and it doesn't seem to be worth the
14566 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14567 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14568 if (UI->getOpcode() != ISD::CopyToReg &&
14569 UI->getOpcode() != ISD::SETCC &&
14570 UI->getOpcode() != ISD::STORE)
14573 if (ConstantSDNode *C =
14574 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14575 // An add of one will be selected as an INC.
14576 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14577 Opcode = X86ISD::INC;
14582 // An add of negative one (subtract of one) will be selected as a DEC.
14583 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14584 Opcode = X86ISD::DEC;
14590 // Otherwise use a regular EFLAGS-setting add.
14591 Opcode = X86ISD::ADD;
14596 // If we have a constant logical shift that's only used in a comparison
14597 // against zero turn it into an equivalent AND. This allows turning it into
14598 // a TEST instruction later.
14599 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14600 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14601 EVT VT = Op.getValueType();
14602 unsigned BitWidth = VT.getSizeInBits();
14603 unsigned ShAmt = Op->getConstantOperandVal(1);
14604 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14606 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14607 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14608 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14609 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14611 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14612 DAG.getConstant(Mask, VT));
14613 DAG.ReplaceAllUsesWith(Op, New);
14619 // If the primary and result isn't used, don't bother using X86ISD::AND,
14620 // because a TEST instruction will be better.
14621 if (!hasNonFlagsUse(Op))
14627 // Due to the ISEL shortcoming noted above, be conservative if this op is
14628 // likely to be selected as part of a load-modify-store instruction.
14629 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14630 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14631 if (UI->getOpcode() == ISD::STORE)
14634 // Otherwise use a regular EFLAGS-setting instruction.
14635 switch (ArithOp.getOpcode()) {
14636 default: llvm_unreachable("unexpected operator!");
14637 case ISD::SUB: Opcode = X86ISD::SUB; break;
14638 case ISD::XOR: Opcode = X86ISD::XOR; break;
14639 case ISD::AND: Opcode = X86ISD::AND; break;
14641 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14642 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14643 if (EFLAGS.getNode())
14646 Opcode = X86ISD::OR;
14660 return SDValue(Op.getNode(), 1);
14666 // If we found that truncation is beneficial, perform the truncation and
14668 if (NeedTruncation) {
14669 EVT VT = Op.getValueType();
14670 SDValue WideVal = Op->getOperand(0);
14671 EVT WideVT = WideVal.getValueType();
14672 unsigned ConvertedOp = 0;
14673 // Use a target machine opcode to prevent further DAGCombine
14674 // optimizations that may separate the arithmetic operations
14675 // from the setcc node.
14676 switch (WideVal.getOpcode()) {
14678 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14679 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14680 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14681 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14682 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14686 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14687 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14688 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14689 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14690 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14696 // Emit a CMP with 0, which is the TEST pattern.
14697 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14698 DAG.getConstant(0, Op.getValueType()));
14700 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14701 SmallVector<SDValue, 4> Ops;
14702 for (unsigned i = 0; i != NumOperands; ++i)
14703 Ops.push_back(Op.getOperand(i));
14705 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14706 DAG.ReplaceAllUsesWith(Op, New);
14707 return SDValue(New.getNode(), 1);
14710 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14712 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14713 SDLoc dl, SelectionDAG &DAG) const {
14714 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14715 if (C->getAPIntValue() == 0)
14716 return EmitTest(Op0, X86CC, dl, DAG);
14718 if (Op0.getValueType() == MVT::i1)
14719 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14722 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14723 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14724 // Do the comparison at i32 if it's smaller, besides the Atom case.
14725 // This avoids subregister aliasing issues. Keep the smaller reference
14726 // if we're optimizing for size, however, as that'll allow better folding
14727 // of memory operations.
14728 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14729 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14730 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14731 !Subtarget->isAtom()) {
14732 unsigned ExtendOp =
14733 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14734 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14735 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14737 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14738 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14739 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14741 return SDValue(Sub.getNode(), 1);
14743 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14746 /// Convert a comparison if required by the subtarget.
14747 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14748 SelectionDAG &DAG) const {
14749 // If the subtarget does not support the FUCOMI instruction, floating-point
14750 // comparisons have to be converted.
14751 if (Subtarget->hasCMov() ||
14752 Cmp.getOpcode() != X86ISD::CMP ||
14753 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14754 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14757 // The instruction selector will select an FUCOM instruction instead of
14758 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14759 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14760 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14762 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14763 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14764 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14765 DAG.getConstant(8, MVT::i8));
14766 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14767 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14770 /// The minimum architected relative accuracy is 2^-12. We need one
14771 /// Newton-Raphson step to have a good float result (24 bits of precision).
14772 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14773 DAGCombinerInfo &DCI,
14774 unsigned &RefinementSteps,
14775 bool &UseOneConstNR) const {
14776 // FIXME: We should use instruction latency models to calculate the cost of
14777 // each potential sequence, but this is very hard to do reliably because
14778 // at least Intel's Core* chips have variable timing based on the number of
14779 // significant digits in the divisor and/or sqrt operand.
14780 if (!Subtarget->useSqrtEst())
14783 EVT VT = Op.getValueType();
14785 // SSE1 has rsqrtss and rsqrtps.
14786 // TODO: Add support for AVX512 (v16f32).
14787 // It is likely not profitable to do this for f64 because a double-precision
14788 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14789 // instructions: convert to single, rsqrtss, convert back to double, refine
14790 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14791 // along with FMA, this could be a throughput win.
14792 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14793 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14794 RefinementSteps = 1;
14795 UseOneConstNR = false;
14796 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14801 /// The minimum architected relative accuracy is 2^-12. We need one
14802 /// Newton-Raphson step to have a good float result (24 bits of precision).
14803 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14804 DAGCombinerInfo &DCI,
14805 unsigned &RefinementSteps) const {
14806 // FIXME: We should use instruction latency models to calculate the cost of
14807 // each potential sequence, but this is very hard to do reliably because
14808 // at least Intel's Core* chips have variable timing based on the number of
14809 // significant digits in the divisor.
14810 if (!Subtarget->useReciprocalEst())
14813 EVT VT = Op.getValueType();
14815 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14816 // TODO: Add support for AVX512 (v16f32).
14817 // It is likely not profitable to do this for f64 because a double-precision
14818 // reciprocal estimate with refinement on x86 prior to FMA requires
14819 // 15 instructions: convert to single, rcpss, convert back to double, refine
14820 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14821 // along with FMA, this could be a throughput win.
14822 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14823 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14824 RefinementSteps = ReciprocalEstimateRefinementSteps;
14825 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14830 static bool isAllOnes(SDValue V) {
14831 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14832 return C && C->isAllOnesValue();
14835 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14836 /// if it's possible.
14837 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14838 SDLoc dl, SelectionDAG &DAG) const {
14839 SDValue Op0 = And.getOperand(0);
14840 SDValue Op1 = And.getOperand(1);
14841 if (Op0.getOpcode() == ISD::TRUNCATE)
14842 Op0 = Op0.getOperand(0);
14843 if (Op1.getOpcode() == ISD::TRUNCATE)
14844 Op1 = Op1.getOperand(0);
14847 if (Op1.getOpcode() == ISD::SHL)
14848 std::swap(Op0, Op1);
14849 if (Op0.getOpcode() == ISD::SHL) {
14850 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14851 if (And00C->getZExtValue() == 1) {
14852 // If we looked past a truncate, check that it's only truncating away
14854 unsigned BitWidth = Op0.getValueSizeInBits();
14855 unsigned AndBitWidth = And.getValueSizeInBits();
14856 if (BitWidth > AndBitWidth) {
14858 DAG.computeKnownBits(Op0, Zeros, Ones);
14859 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14863 RHS = Op0.getOperand(1);
14865 } else if (Op1.getOpcode() == ISD::Constant) {
14866 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14867 uint64_t AndRHSVal = AndRHS->getZExtValue();
14868 SDValue AndLHS = Op0;
14870 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14871 LHS = AndLHS.getOperand(0);
14872 RHS = AndLHS.getOperand(1);
14875 // Use BT if the immediate can't be encoded in a TEST instruction.
14876 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14878 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14882 if (LHS.getNode()) {
14883 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14884 // instruction. Since the shift amount is in-range-or-undefined, we know
14885 // that doing a bittest on the i32 value is ok. We extend to i32 because
14886 // the encoding for the i16 version is larger than the i32 version.
14887 // Also promote i16 to i32 for performance / code size reason.
14888 if (LHS.getValueType() == MVT::i8 ||
14889 LHS.getValueType() == MVT::i16)
14890 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14892 // If the operand types disagree, extend the shift amount to match. Since
14893 // BT ignores high bits (like shifts) we can use anyextend.
14894 if (LHS.getValueType() != RHS.getValueType())
14895 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14897 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14898 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14899 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14900 DAG.getConstant(Cond, MVT::i8), BT);
14906 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14908 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14913 // SSE Condition code mapping:
14922 switch (SetCCOpcode) {
14923 default: llvm_unreachable("Unexpected SETCC condition");
14925 case ISD::SETEQ: SSECC = 0; break;
14927 case ISD::SETGT: Swap = true; // Fallthrough
14929 case ISD::SETOLT: SSECC = 1; break;
14931 case ISD::SETGE: Swap = true; // Fallthrough
14933 case ISD::SETOLE: SSECC = 2; break;
14934 case ISD::SETUO: SSECC = 3; break;
14936 case ISD::SETNE: SSECC = 4; break;
14937 case ISD::SETULE: Swap = true; // Fallthrough
14938 case ISD::SETUGE: SSECC = 5; break;
14939 case ISD::SETULT: Swap = true; // Fallthrough
14940 case ISD::SETUGT: SSECC = 6; break;
14941 case ISD::SETO: SSECC = 7; break;
14943 case ISD::SETONE: SSECC = 8; break;
14946 std::swap(Op0, Op1);
14951 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14952 // ones, and then concatenate the result back.
14953 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14954 MVT VT = Op.getSimpleValueType();
14956 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14957 "Unsupported value type for operation");
14959 unsigned NumElems = VT.getVectorNumElements();
14961 SDValue CC = Op.getOperand(2);
14963 // Extract the LHS vectors
14964 SDValue LHS = Op.getOperand(0);
14965 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14966 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14968 // Extract the RHS vectors
14969 SDValue RHS = Op.getOperand(1);
14970 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14971 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14973 // Issue the operation on the smaller types and concatenate the result back
14974 MVT EltVT = VT.getVectorElementType();
14975 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14976 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14977 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14978 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14981 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14982 const X86Subtarget *Subtarget) {
14983 SDValue Op0 = Op.getOperand(0);
14984 SDValue Op1 = Op.getOperand(1);
14985 SDValue CC = Op.getOperand(2);
14986 MVT VT = Op.getSimpleValueType();
14989 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14990 Op.getValueType().getScalarType() == MVT::i1 &&
14991 "Cannot set masked compare for this operation");
14993 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14995 bool Unsigned = false;
14998 switch (SetCCOpcode) {
14999 default: llvm_unreachable("Unexpected SETCC condition");
15000 case ISD::SETNE: SSECC = 4; break;
15001 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15002 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15003 case ISD::SETLT: Swap = true; //fall-through
15004 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15005 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15006 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15007 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15008 case ISD::SETULE: Unsigned = true; //fall-through
15009 case ISD::SETLE: SSECC = 2; break;
15013 std::swap(Op0, Op1);
15015 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15016 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15017 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15018 DAG.getConstant(SSECC, MVT::i8));
15021 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15022 /// operand \p Op1. If non-trivial (for example because it's not constant)
15023 /// return an empty value.
15024 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15026 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15030 MVT VT = Op1.getSimpleValueType();
15031 MVT EVT = VT.getVectorElementType();
15032 unsigned n = VT.getVectorNumElements();
15033 SmallVector<SDValue, 8> ULTOp1;
15035 for (unsigned i = 0; i < n; ++i) {
15036 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15037 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15040 // Avoid underflow.
15041 APInt Val = Elt->getAPIntValue();
15045 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15048 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15051 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15052 SelectionDAG &DAG) {
15053 SDValue Op0 = Op.getOperand(0);
15054 SDValue Op1 = Op.getOperand(1);
15055 SDValue CC = Op.getOperand(2);
15056 MVT VT = Op.getSimpleValueType();
15057 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15058 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15063 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15064 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15067 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15068 unsigned Opc = X86ISD::CMPP;
15069 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15070 assert(VT.getVectorNumElements() <= 16);
15071 Opc = X86ISD::CMPM;
15073 // In the two special cases we can't handle, emit two comparisons.
15076 unsigned CombineOpc;
15077 if (SetCCOpcode == ISD::SETUEQ) {
15078 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15080 assert(SetCCOpcode == ISD::SETONE);
15081 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15084 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15085 DAG.getConstant(CC0, MVT::i8));
15086 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15087 DAG.getConstant(CC1, MVT::i8));
15088 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15090 // Handle all other FP comparisons here.
15091 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15092 DAG.getConstant(SSECC, MVT::i8));
15095 // Break 256-bit integer vector compare into smaller ones.
15096 if (VT.is256BitVector() && !Subtarget->hasInt256())
15097 return Lower256IntVSETCC(Op, DAG);
15099 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15100 EVT OpVT = Op1.getValueType();
15101 if (Subtarget->hasAVX512()) {
15102 if (Op1.getValueType().is512BitVector() ||
15103 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15104 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15105 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15107 // In AVX-512 architecture setcc returns mask with i1 elements,
15108 // But there is no compare instruction for i8 and i16 elements in KNL.
15109 // We are not talking about 512-bit operands in this case, these
15110 // types are illegal.
15112 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15113 OpVT.getVectorElementType().getSizeInBits() >= 8))
15114 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15115 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15118 // We are handling one of the integer comparisons here. Since SSE only has
15119 // GT and EQ comparisons for integer, swapping operands and multiple
15120 // operations may be required for some comparisons.
15122 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15123 bool Subus = false;
15125 switch (SetCCOpcode) {
15126 default: llvm_unreachable("Unexpected SETCC condition");
15127 case ISD::SETNE: Invert = true;
15128 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15129 case ISD::SETLT: Swap = true;
15130 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15131 case ISD::SETGE: Swap = true;
15132 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15133 Invert = true; break;
15134 case ISD::SETULT: Swap = true;
15135 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15136 FlipSigns = true; break;
15137 case ISD::SETUGE: Swap = true;
15138 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15139 FlipSigns = true; Invert = true; break;
15142 // Special case: Use min/max operations for SETULE/SETUGE
15143 MVT VET = VT.getVectorElementType();
15145 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15146 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15149 switch (SetCCOpcode) {
15151 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15152 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15155 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15158 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15159 if (!MinMax && hasSubus) {
15160 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15162 // t = psubus Op0, Op1
15163 // pcmpeq t, <0..0>
15164 switch (SetCCOpcode) {
15166 case ISD::SETULT: {
15167 // If the comparison is against a constant we can turn this into a
15168 // setule. With psubus, setule does not require a swap. This is
15169 // beneficial because the constant in the register is no longer
15170 // destructed as the destination so it can be hoisted out of a loop.
15171 // Only do this pre-AVX since vpcmp* is no longer destructive.
15172 if (Subtarget->hasAVX())
15174 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15175 if (ULEOp1.getNode()) {
15177 Subus = true; Invert = false; Swap = false;
15181 // Psubus is better than flip-sign because it requires no inversion.
15182 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15183 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15187 Opc = X86ISD::SUBUS;
15193 std::swap(Op0, Op1);
15195 // Check that the operation in question is available (most are plain SSE2,
15196 // but PCMPGTQ and PCMPEQQ have different requirements).
15197 if (VT == MVT::v2i64) {
15198 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15199 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15201 // First cast everything to the right type.
15202 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15203 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15205 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15206 // bits of the inputs before performing those operations. The lower
15207 // compare is always unsigned.
15210 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15212 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15213 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15214 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15215 Sign, Zero, Sign, Zero);
15217 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15218 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15220 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15221 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15222 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15224 // Create masks for only the low parts/high parts of the 64 bit integers.
15225 static const int MaskHi[] = { 1, 1, 3, 3 };
15226 static const int MaskLo[] = { 0, 0, 2, 2 };
15227 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15228 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15229 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15231 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15232 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15235 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15237 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15240 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15241 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15242 // pcmpeqd + pshufd + pand.
15243 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15245 // First cast everything to the right type.
15246 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15247 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15250 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15252 // Make sure the lower and upper halves are both all-ones.
15253 static const int Mask[] = { 1, 0, 3, 2 };
15254 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15255 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15258 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15260 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15264 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15265 // bits of the inputs before performing those operations.
15267 EVT EltVT = VT.getVectorElementType();
15268 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15269 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15270 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15273 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15275 // If the logical-not of the result is required, perform that now.
15277 Result = DAG.getNOT(dl, Result, VT);
15280 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15283 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15284 getZeroVector(VT, Subtarget, DAG, dl));
15289 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15291 MVT VT = Op.getSimpleValueType();
15293 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15295 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15296 && "SetCC type must be 8-bit or 1-bit integer");
15297 SDValue Op0 = Op.getOperand(0);
15298 SDValue Op1 = Op.getOperand(1);
15300 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15302 // Optimize to BT if possible.
15303 // Lower (X & (1 << N)) == 0 to BT(X, N).
15304 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15305 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15306 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15307 Op1.getOpcode() == ISD::Constant &&
15308 cast<ConstantSDNode>(Op1)->isNullValue() &&
15309 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15310 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15311 if (NewSetCC.getNode())
15315 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15317 if (Op1.getOpcode() == ISD::Constant &&
15318 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15319 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15320 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15322 // If the input is a setcc, then reuse the input setcc or use a new one with
15323 // the inverted condition.
15324 if (Op0.getOpcode() == X86ISD::SETCC) {
15325 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15326 bool Invert = (CC == ISD::SETNE) ^
15327 cast<ConstantSDNode>(Op1)->isNullValue();
15331 CCode = X86::GetOppositeBranchCondition(CCode);
15332 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15333 DAG.getConstant(CCode, MVT::i8),
15334 Op0.getOperand(1));
15336 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15340 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15341 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15342 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15344 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15345 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15348 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15349 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15350 if (X86CC == X86::COND_INVALID)
15353 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15354 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15355 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15356 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15358 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15362 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15363 static bool isX86LogicalCmp(SDValue Op) {
15364 unsigned Opc = Op.getNode()->getOpcode();
15365 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15366 Opc == X86ISD::SAHF)
15368 if (Op.getResNo() == 1 &&
15369 (Opc == X86ISD::ADD ||
15370 Opc == X86ISD::SUB ||
15371 Opc == X86ISD::ADC ||
15372 Opc == X86ISD::SBB ||
15373 Opc == X86ISD::SMUL ||
15374 Opc == X86ISD::UMUL ||
15375 Opc == X86ISD::INC ||
15376 Opc == X86ISD::DEC ||
15377 Opc == X86ISD::OR ||
15378 Opc == X86ISD::XOR ||
15379 Opc == X86ISD::AND))
15382 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15388 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15389 if (V.getOpcode() != ISD::TRUNCATE)
15392 SDValue VOp0 = V.getOperand(0);
15393 unsigned InBits = VOp0.getValueSizeInBits();
15394 unsigned Bits = V.getValueSizeInBits();
15395 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15398 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15399 bool addTest = true;
15400 SDValue Cond = Op.getOperand(0);
15401 SDValue Op1 = Op.getOperand(1);
15402 SDValue Op2 = Op.getOperand(2);
15404 EVT VT = Op1.getValueType();
15407 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15408 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15409 // sequence later on.
15410 if (Cond.getOpcode() == ISD::SETCC &&
15411 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15412 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15413 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15414 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15415 int SSECC = translateX86FSETCC(
15416 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15419 if (Subtarget->hasAVX512()) {
15420 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15421 DAG.getConstant(SSECC, MVT::i8));
15422 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15424 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15425 DAG.getConstant(SSECC, MVT::i8));
15426 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15427 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15428 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15432 if (Cond.getOpcode() == ISD::SETCC) {
15433 SDValue NewCond = LowerSETCC(Cond, DAG);
15434 if (NewCond.getNode())
15438 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15439 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15440 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15441 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15442 if (Cond.getOpcode() == X86ISD::SETCC &&
15443 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15444 isZero(Cond.getOperand(1).getOperand(1))) {
15445 SDValue Cmp = Cond.getOperand(1);
15447 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15449 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15450 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15451 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15453 SDValue CmpOp0 = Cmp.getOperand(0);
15454 // Apply further optimizations for special cases
15455 // (select (x != 0), -1, 0) -> neg & sbb
15456 // (select (x == 0), 0, -1) -> neg & sbb
15457 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15458 if (YC->isNullValue() &&
15459 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15460 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15461 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15462 DAG.getConstant(0, CmpOp0.getValueType()),
15464 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15465 DAG.getConstant(X86::COND_B, MVT::i8),
15466 SDValue(Neg.getNode(), 1));
15470 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15471 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15472 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15474 SDValue Res = // Res = 0 or -1.
15475 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15476 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15478 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15479 Res = DAG.getNOT(DL, Res, Res.getValueType());
15481 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15482 if (!N2C || !N2C->isNullValue())
15483 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15488 // Look past (and (setcc_carry (cmp ...)), 1).
15489 if (Cond.getOpcode() == ISD::AND &&
15490 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15491 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15492 if (C && C->getAPIntValue() == 1)
15493 Cond = Cond.getOperand(0);
15496 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15497 // setting operand in place of the X86ISD::SETCC.
15498 unsigned CondOpcode = Cond.getOpcode();
15499 if (CondOpcode == X86ISD::SETCC ||
15500 CondOpcode == X86ISD::SETCC_CARRY) {
15501 CC = Cond.getOperand(0);
15503 SDValue Cmp = Cond.getOperand(1);
15504 unsigned Opc = Cmp.getOpcode();
15505 MVT VT = Op.getSimpleValueType();
15507 bool IllegalFPCMov = false;
15508 if (VT.isFloatingPoint() && !VT.isVector() &&
15509 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15510 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15512 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15513 Opc == X86ISD::BT) { // FIXME
15517 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15518 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15519 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15520 Cond.getOperand(0).getValueType() != MVT::i8)) {
15521 SDValue LHS = Cond.getOperand(0);
15522 SDValue RHS = Cond.getOperand(1);
15523 unsigned X86Opcode;
15526 switch (CondOpcode) {
15527 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15528 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15529 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15530 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15531 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15532 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15533 default: llvm_unreachable("unexpected overflowing operator");
15535 if (CondOpcode == ISD::UMULO)
15536 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15539 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15541 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15543 if (CondOpcode == ISD::UMULO)
15544 Cond = X86Op.getValue(2);
15546 Cond = X86Op.getValue(1);
15548 CC = DAG.getConstant(X86Cond, MVT::i8);
15553 // Look pass the truncate if the high bits are known zero.
15554 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15555 Cond = Cond.getOperand(0);
15557 // We know the result of AND is compared against zero. Try to match
15559 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15560 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15561 if (NewSetCC.getNode()) {
15562 CC = NewSetCC.getOperand(0);
15563 Cond = NewSetCC.getOperand(1);
15570 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15571 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15574 // a < b ? -1 : 0 -> RES = ~setcc_carry
15575 // a < b ? 0 : -1 -> RES = setcc_carry
15576 // a >= b ? -1 : 0 -> RES = setcc_carry
15577 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15578 if (Cond.getOpcode() == X86ISD::SUB) {
15579 Cond = ConvertCmpIfNecessary(Cond, DAG);
15580 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15582 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15583 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15584 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15585 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15586 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15587 return DAG.getNOT(DL, Res, Res.getValueType());
15592 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15593 // widen the cmov and push the truncate through. This avoids introducing a new
15594 // branch during isel and doesn't add any extensions.
15595 if (Op.getValueType() == MVT::i8 &&
15596 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15597 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15598 if (T1.getValueType() == T2.getValueType() &&
15599 // Blacklist CopyFromReg to avoid partial register stalls.
15600 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15601 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15602 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15603 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15607 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15608 // condition is true.
15609 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15610 SDValue Ops[] = { Op2, Op1, CC, Cond };
15611 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15614 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15615 SelectionDAG &DAG) {
15616 MVT VT = Op->getSimpleValueType(0);
15617 SDValue In = Op->getOperand(0);
15618 MVT InVT = In.getSimpleValueType();
15619 MVT VTElt = VT.getVectorElementType();
15620 MVT InVTElt = InVT.getVectorElementType();
15624 if ((InVTElt == MVT::i1) &&
15625 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15626 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15628 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15629 VTElt.getSizeInBits() <= 16)) ||
15631 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15632 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15634 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15635 VTElt.getSizeInBits() >= 32))))
15636 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15638 unsigned int NumElts = VT.getVectorNumElements();
15640 if (NumElts != 8 && NumElts != 16)
15643 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15644 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15645 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15646 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15650 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15652 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15653 Constant *C = ConstantInt::get(*DAG.getContext(),
15654 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15656 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15657 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15658 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15659 MachinePointerInfo::getConstantPool(),
15660 false, false, false, Alignment);
15661 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15662 if (VT.is512BitVector())
15664 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15667 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15668 SelectionDAG &DAG) {
15669 MVT VT = Op->getSimpleValueType(0);
15670 SDValue In = Op->getOperand(0);
15671 MVT InVT = In.getSimpleValueType();
15674 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15675 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15677 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15678 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15679 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15682 if (Subtarget->hasInt256())
15683 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15685 // Optimize vectors in AVX mode
15686 // Sign extend v8i16 to v8i32 and
15689 // Divide input vector into two parts
15690 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15691 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15692 // concat the vectors to original VT
15694 unsigned NumElems = InVT.getVectorNumElements();
15695 SDValue Undef = DAG.getUNDEF(InVT);
15697 SmallVector<int,8> ShufMask1(NumElems, -1);
15698 for (unsigned i = 0; i != NumElems/2; ++i)
15701 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15703 SmallVector<int,8> ShufMask2(NumElems, -1);
15704 for (unsigned i = 0; i != NumElems/2; ++i)
15705 ShufMask2[i] = i + NumElems/2;
15707 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15709 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15710 VT.getVectorNumElements()/2);
15712 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15713 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15715 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15718 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15719 // may emit an illegal shuffle but the expansion is still better than scalar
15720 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15721 // we'll emit a shuffle and a arithmetic shift.
15722 // TODO: It is possible to support ZExt by zeroing the undef values during
15723 // the shuffle phase or after the shuffle.
15724 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15725 SelectionDAG &DAG) {
15726 MVT RegVT = Op.getSimpleValueType();
15727 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15728 assert(RegVT.isInteger() &&
15729 "We only custom lower integer vector sext loads.");
15731 // Nothing useful we can do without SSE2 shuffles.
15732 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15734 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15736 EVT MemVT = Ld->getMemoryVT();
15737 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15738 unsigned RegSz = RegVT.getSizeInBits();
15740 ISD::LoadExtType Ext = Ld->getExtensionType();
15742 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15743 && "Only anyext and sext are currently implemented.");
15744 assert(MemVT != RegVT && "Cannot extend to the same type");
15745 assert(MemVT.isVector() && "Must load a vector from memory");
15747 unsigned NumElems = RegVT.getVectorNumElements();
15748 unsigned MemSz = MemVT.getSizeInBits();
15749 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15751 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15752 // The only way in which we have a legal 256-bit vector result but not the
15753 // integer 256-bit operations needed to directly lower a sextload is if we
15754 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15755 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15756 // correctly legalized. We do this late to allow the canonical form of
15757 // sextload to persist throughout the rest of the DAG combiner -- it wants
15758 // to fold together any extensions it can, and so will fuse a sign_extend
15759 // of an sextload into a sextload targeting a wider value.
15761 if (MemSz == 128) {
15762 // Just switch this to a normal load.
15763 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15764 "it must be a legal 128-bit vector "
15766 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15767 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15768 Ld->isInvariant(), Ld->getAlignment());
15770 assert(MemSz < 128 &&
15771 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15772 // Do an sext load to a 128-bit vector type. We want to use the same
15773 // number of elements, but elements half as wide. This will end up being
15774 // recursively lowered by this routine, but will succeed as we definitely
15775 // have all the necessary features if we're using AVX1.
15777 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15778 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15780 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15781 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15782 Ld->isNonTemporal(), Ld->isInvariant(),
15783 Ld->getAlignment());
15786 // Replace chain users with the new chain.
15787 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15788 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15790 // Finally, do a normal sign-extend to the desired register.
15791 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15794 // All sizes must be a power of two.
15795 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15796 "Non-power-of-two elements are not custom lowered!");
15798 // Attempt to load the original value using scalar loads.
15799 // Find the largest scalar type that divides the total loaded size.
15800 MVT SclrLoadTy = MVT::i8;
15801 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15802 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15803 MVT Tp = (MVT::SimpleValueType)tp;
15804 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15809 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15810 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15812 SclrLoadTy = MVT::f64;
15814 // Calculate the number of scalar loads that we need to perform
15815 // in order to load our vector from memory.
15816 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15818 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15819 "Can only lower sext loads with a single scalar load!");
15821 unsigned loadRegZize = RegSz;
15822 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15825 // Represent our vector as a sequence of elements which are the
15826 // largest scalar that we can load.
15827 EVT LoadUnitVecVT = EVT::getVectorVT(
15828 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15830 // Represent the data using the same element type that is stored in
15831 // memory. In practice, we ''widen'' MemVT.
15833 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15834 loadRegZize / MemVT.getScalarType().getSizeInBits());
15836 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15837 "Invalid vector type");
15839 // We can't shuffle using an illegal type.
15840 assert(TLI.isTypeLegal(WideVecVT) &&
15841 "We only lower types that form legal widened vector types");
15843 SmallVector<SDValue, 8> Chains;
15844 SDValue Ptr = Ld->getBasePtr();
15845 SDValue Increment =
15846 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15847 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15849 for (unsigned i = 0; i < NumLoads; ++i) {
15850 // Perform a single load.
15851 SDValue ScalarLoad =
15852 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15853 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15854 Ld->getAlignment());
15855 Chains.push_back(ScalarLoad.getValue(1));
15856 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15857 // another round of DAGCombining.
15859 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15861 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15862 ScalarLoad, DAG.getIntPtrConstant(i));
15864 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15867 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15869 // Bitcast the loaded value to a vector of the original element type, in
15870 // the size of the target vector type.
15871 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15872 unsigned SizeRatio = RegSz / MemSz;
15874 if (Ext == ISD::SEXTLOAD) {
15875 // If we have SSE4.1, we can directly emit a VSEXT node.
15876 if (Subtarget->hasSSE41()) {
15877 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15878 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15882 // Otherwise we'll shuffle the small elements in the high bits of the
15883 // larger type and perform an arithmetic shift. If the shift is not legal
15884 // it's better to scalarize.
15885 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15886 "We can't implement a sext load without an arithmetic right shift!");
15888 // Redistribute the loaded elements into the different locations.
15889 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15890 for (unsigned i = 0; i != NumElems; ++i)
15891 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15893 SDValue Shuff = DAG.getVectorShuffle(
15894 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15896 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15898 // Build the arithmetic shift.
15899 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15900 MemVT.getVectorElementType().getSizeInBits();
15902 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15904 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15908 // Redistribute the loaded elements into the different locations.
15909 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15910 for (unsigned i = 0; i != NumElems; ++i)
15911 ShuffleVec[i * SizeRatio] = i;
15913 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15914 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15916 // Bitcast to the requested type.
15917 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15918 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15922 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15923 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15924 // from the AND / OR.
15925 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15926 Opc = Op.getOpcode();
15927 if (Opc != ISD::OR && Opc != ISD::AND)
15929 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15930 Op.getOperand(0).hasOneUse() &&
15931 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15932 Op.getOperand(1).hasOneUse());
15935 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15936 // 1 and that the SETCC node has a single use.
15937 static bool isXor1OfSetCC(SDValue Op) {
15938 if (Op.getOpcode() != ISD::XOR)
15940 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15941 if (N1C && N1C->getAPIntValue() == 1) {
15942 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15943 Op.getOperand(0).hasOneUse();
15948 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15949 bool addTest = true;
15950 SDValue Chain = Op.getOperand(0);
15951 SDValue Cond = Op.getOperand(1);
15952 SDValue Dest = Op.getOperand(2);
15955 bool Inverted = false;
15957 if (Cond.getOpcode() == ISD::SETCC) {
15958 // Check for setcc([su]{add,sub,mul}o == 0).
15959 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15960 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15961 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15962 Cond.getOperand(0).getResNo() == 1 &&
15963 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15964 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15965 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15966 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15967 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15968 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15970 Cond = Cond.getOperand(0);
15972 SDValue NewCond = LowerSETCC(Cond, DAG);
15973 if (NewCond.getNode())
15978 // FIXME: LowerXALUO doesn't handle these!!
15979 else if (Cond.getOpcode() == X86ISD::ADD ||
15980 Cond.getOpcode() == X86ISD::SUB ||
15981 Cond.getOpcode() == X86ISD::SMUL ||
15982 Cond.getOpcode() == X86ISD::UMUL)
15983 Cond = LowerXALUO(Cond, DAG);
15986 // Look pass (and (setcc_carry (cmp ...)), 1).
15987 if (Cond.getOpcode() == ISD::AND &&
15988 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15989 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15990 if (C && C->getAPIntValue() == 1)
15991 Cond = Cond.getOperand(0);
15994 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15995 // setting operand in place of the X86ISD::SETCC.
15996 unsigned CondOpcode = Cond.getOpcode();
15997 if (CondOpcode == X86ISD::SETCC ||
15998 CondOpcode == X86ISD::SETCC_CARRY) {
15999 CC = Cond.getOperand(0);
16001 SDValue Cmp = Cond.getOperand(1);
16002 unsigned Opc = Cmp.getOpcode();
16003 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16004 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16008 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16012 // These can only come from an arithmetic instruction with overflow,
16013 // e.g. SADDO, UADDO.
16014 Cond = Cond.getNode()->getOperand(1);
16020 CondOpcode = Cond.getOpcode();
16021 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16022 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16023 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16024 Cond.getOperand(0).getValueType() != MVT::i8)) {
16025 SDValue LHS = Cond.getOperand(0);
16026 SDValue RHS = Cond.getOperand(1);
16027 unsigned X86Opcode;
16030 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16031 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16033 switch (CondOpcode) {
16034 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16036 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16038 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16041 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16042 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16044 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16046 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16049 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16050 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16051 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16052 default: llvm_unreachable("unexpected overflowing operator");
16055 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16056 if (CondOpcode == ISD::UMULO)
16057 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16060 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16062 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16064 if (CondOpcode == ISD::UMULO)
16065 Cond = X86Op.getValue(2);
16067 Cond = X86Op.getValue(1);
16069 CC = DAG.getConstant(X86Cond, MVT::i8);
16073 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16074 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16075 if (CondOpc == ISD::OR) {
16076 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16077 // two branches instead of an explicit OR instruction with a
16079 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16080 isX86LogicalCmp(Cmp)) {
16081 CC = Cond.getOperand(0).getOperand(0);
16082 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16083 Chain, Dest, CC, Cmp);
16084 CC = Cond.getOperand(1).getOperand(0);
16088 } else { // ISD::AND
16089 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16090 // two branches instead of an explicit AND instruction with a
16091 // separate test. However, we only do this if this block doesn't
16092 // have a fall-through edge, because this requires an explicit
16093 // jmp when the condition is false.
16094 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16095 isX86LogicalCmp(Cmp) &&
16096 Op.getNode()->hasOneUse()) {
16097 X86::CondCode CCode =
16098 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16099 CCode = X86::GetOppositeBranchCondition(CCode);
16100 CC = DAG.getConstant(CCode, MVT::i8);
16101 SDNode *User = *Op.getNode()->use_begin();
16102 // Look for an unconditional branch following this conditional branch.
16103 // We need this because we need to reverse the successors in order
16104 // to implement FCMP_OEQ.
16105 if (User->getOpcode() == ISD::BR) {
16106 SDValue FalseBB = User->getOperand(1);
16108 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16109 assert(NewBR == User);
16113 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16114 Chain, Dest, CC, Cmp);
16115 X86::CondCode CCode =
16116 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16117 CCode = X86::GetOppositeBranchCondition(CCode);
16118 CC = DAG.getConstant(CCode, MVT::i8);
16124 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16125 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16126 // It should be transformed during dag combiner except when the condition
16127 // is set by a arithmetics with overflow node.
16128 X86::CondCode CCode =
16129 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16130 CCode = X86::GetOppositeBranchCondition(CCode);
16131 CC = DAG.getConstant(CCode, MVT::i8);
16132 Cond = Cond.getOperand(0).getOperand(1);
16134 } else if (Cond.getOpcode() == ISD::SETCC &&
16135 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16136 // For FCMP_OEQ, we can emit
16137 // two branches instead of an explicit AND instruction with a
16138 // separate test. However, we only do this if this block doesn't
16139 // have a fall-through edge, because this requires an explicit
16140 // jmp when the condition is false.
16141 if (Op.getNode()->hasOneUse()) {
16142 SDNode *User = *Op.getNode()->use_begin();
16143 // Look for an unconditional branch following this conditional branch.
16144 // We need this because we need to reverse the successors in order
16145 // to implement FCMP_OEQ.
16146 if (User->getOpcode() == ISD::BR) {
16147 SDValue FalseBB = User->getOperand(1);
16149 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16150 assert(NewBR == User);
16154 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16155 Cond.getOperand(0), Cond.getOperand(1));
16156 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16157 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16158 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16159 Chain, Dest, CC, Cmp);
16160 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16165 } else if (Cond.getOpcode() == ISD::SETCC &&
16166 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16167 // For FCMP_UNE, we can emit
16168 // two branches instead of an explicit AND instruction with a
16169 // separate test. However, we only do this if this block doesn't
16170 // have a fall-through edge, because this requires an explicit
16171 // jmp when the condition is false.
16172 if (Op.getNode()->hasOneUse()) {
16173 SDNode *User = *Op.getNode()->use_begin();
16174 // Look for an unconditional branch following this conditional branch.
16175 // We need this because we need to reverse the successors in order
16176 // to implement FCMP_UNE.
16177 if (User->getOpcode() == ISD::BR) {
16178 SDValue FalseBB = User->getOperand(1);
16180 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16181 assert(NewBR == User);
16184 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16185 Cond.getOperand(0), Cond.getOperand(1));
16186 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16187 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16188 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16189 Chain, Dest, CC, Cmp);
16190 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16200 // Look pass the truncate if the high bits are known zero.
16201 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16202 Cond = Cond.getOperand(0);
16204 // We know the result of AND is compared against zero. Try to match
16206 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16207 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16208 if (NewSetCC.getNode()) {
16209 CC = NewSetCC.getOperand(0);
16210 Cond = NewSetCC.getOperand(1);
16217 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16218 CC = DAG.getConstant(X86Cond, MVT::i8);
16219 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16221 Cond = ConvertCmpIfNecessary(Cond, DAG);
16222 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16223 Chain, Dest, CC, Cond);
16226 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16227 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16228 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16229 // that the guard pages used by the OS virtual memory manager are allocated in
16230 // correct sequence.
16232 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16233 SelectionDAG &DAG) const {
16234 MachineFunction &MF = DAG.getMachineFunction();
16235 bool SplitStack = MF.shouldSplitStack();
16236 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16241 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16242 SDNode* Node = Op.getNode();
16244 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16245 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16246 " not tell us which reg is the stack pointer!");
16247 EVT VT = Node->getValueType(0);
16248 SDValue Tmp1 = SDValue(Node, 0);
16249 SDValue Tmp2 = SDValue(Node, 1);
16250 SDValue Tmp3 = Node->getOperand(2);
16251 SDValue Chain = Tmp1.getOperand(0);
16253 // Chain the dynamic stack allocation so that it doesn't modify the stack
16254 // pointer when other instructions are using the stack.
16255 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16258 SDValue Size = Tmp2.getOperand(1);
16259 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16260 Chain = SP.getValue(1);
16261 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16262 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16263 unsigned StackAlign = TFI.getStackAlignment();
16264 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16265 if (Align > StackAlign)
16266 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16267 DAG.getConstant(-(uint64_t)Align, VT));
16268 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16270 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16271 DAG.getIntPtrConstant(0, true), SDValue(),
16274 SDValue Ops[2] = { Tmp1, Tmp2 };
16275 return DAG.getMergeValues(Ops, dl);
16279 SDValue Chain = Op.getOperand(0);
16280 SDValue Size = Op.getOperand(1);
16281 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16282 EVT VT = Op.getNode()->getValueType(0);
16284 bool Is64Bit = Subtarget->is64Bit();
16285 EVT SPTy = getPointerTy();
16288 MachineRegisterInfo &MRI = MF.getRegInfo();
16291 // The 64 bit implementation of segmented stacks needs to clobber both r10
16292 // r11. This makes it impossible to use it along with nested parameters.
16293 const Function *F = MF.getFunction();
16295 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16297 if (I->hasNestAttr())
16298 report_fatal_error("Cannot use segmented stacks with functions that "
16299 "have nested arguments.");
16302 const TargetRegisterClass *AddrRegClass =
16303 getRegClassFor(getPointerTy());
16304 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16305 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16306 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16307 DAG.getRegister(Vreg, SPTy));
16308 SDValue Ops1[2] = { Value, Chain };
16309 return DAG.getMergeValues(Ops1, dl);
16312 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16314 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16315 Flag = Chain.getValue(1);
16316 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16318 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16320 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16321 DAG.getSubtarget().getRegisterInfo());
16322 unsigned SPReg = RegInfo->getStackRegister();
16323 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16324 Chain = SP.getValue(1);
16327 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16328 DAG.getConstant(-(uint64_t)Align, VT));
16329 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16332 SDValue Ops1[2] = { SP, Chain };
16333 return DAG.getMergeValues(Ops1, dl);
16337 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16338 MachineFunction &MF = DAG.getMachineFunction();
16339 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16341 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16344 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16345 // vastart just stores the address of the VarArgsFrameIndex slot into the
16346 // memory location argument.
16347 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16349 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16350 MachinePointerInfo(SV), false, false, 0);
16354 // gp_offset (0 - 6 * 8)
16355 // fp_offset (48 - 48 + 8 * 16)
16356 // overflow_arg_area (point to parameters coming in memory).
16358 SmallVector<SDValue, 8> MemOps;
16359 SDValue FIN = Op.getOperand(1);
16361 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16362 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16364 FIN, MachinePointerInfo(SV), false, false, 0);
16365 MemOps.push_back(Store);
16368 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16369 FIN, DAG.getIntPtrConstant(4));
16370 Store = DAG.getStore(Op.getOperand(0), DL,
16371 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16373 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16374 MemOps.push_back(Store);
16376 // Store ptr to overflow_arg_area
16377 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16378 FIN, DAG.getIntPtrConstant(4));
16379 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16381 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16382 MachinePointerInfo(SV, 8),
16384 MemOps.push_back(Store);
16386 // Store ptr to reg_save_area.
16387 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16388 FIN, DAG.getIntPtrConstant(8));
16389 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16391 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16392 MachinePointerInfo(SV, 16), false, false, 0);
16393 MemOps.push_back(Store);
16394 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16397 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16398 assert(Subtarget->is64Bit() &&
16399 "LowerVAARG only handles 64-bit va_arg!");
16400 assert((Subtarget->isTargetLinux() ||
16401 Subtarget->isTargetDarwin()) &&
16402 "Unhandled target in LowerVAARG");
16403 assert(Op.getNode()->getNumOperands() == 4);
16404 SDValue Chain = Op.getOperand(0);
16405 SDValue SrcPtr = Op.getOperand(1);
16406 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16407 unsigned Align = Op.getConstantOperandVal(3);
16410 EVT ArgVT = Op.getNode()->getValueType(0);
16411 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16412 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16415 // Decide which area this value should be read from.
16416 // TODO: Implement the AMD64 ABI in its entirety. This simple
16417 // selection mechanism works only for the basic types.
16418 if (ArgVT == MVT::f80) {
16419 llvm_unreachable("va_arg for f80 not yet implemented");
16420 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16421 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16422 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16423 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16425 llvm_unreachable("Unhandled argument type in LowerVAARG");
16428 if (ArgMode == 2) {
16429 // Sanity Check: Make sure using fp_offset makes sense.
16430 assert(!DAG.getTarget().Options.UseSoftFloat &&
16431 !(DAG.getMachineFunction()
16432 .getFunction()->getAttributes()
16433 .hasAttribute(AttributeSet::FunctionIndex,
16434 Attribute::NoImplicitFloat)) &&
16435 Subtarget->hasSSE1());
16438 // Insert VAARG_64 node into the DAG
16439 // VAARG_64 returns two values: Variable Argument Address, Chain
16440 SmallVector<SDValue, 11> InstOps;
16441 InstOps.push_back(Chain);
16442 InstOps.push_back(SrcPtr);
16443 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16444 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16445 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16446 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16447 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16448 VTs, InstOps, MVT::i64,
16449 MachinePointerInfo(SV),
16451 /*Volatile=*/false,
16453 /*WriteMem=*/true);
16454 Chain = VAARG.getValue(1);
16456 // Load the next argument and return it
16457 return DAG.getLoad(ArgVT, dl,
16460 MachinePointerInfo(),
16461 false, false, false, 0);
16464 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16465 SelectionDAG &DAG) {
16466 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16467 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16468 SDValue Chain = Op.getOperand(0);
16469 SDValue DstPtr = Op.getOperand(1);
16470 SDValue SrcPtr = Op.getOperand(2);
16471 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16472 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16475 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16476 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16478 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16481 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16482 // amount is a constant. Takes immediate version of shift as input.
16483 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16484 SDValue SrcOp, uint64_t ShiftAmt,
16485 SelectionDAG &DAG) {
16486 MVT ElementType = VT.getVectorElementType();
16488 // Fold this packed shift into its first operand if ShiftAmt is 0.
16492 // Check for ShiftAmt >= element width
16493 if (ShiftAmt >= ElementType.getSizeInBits()) {
16494 if (Opc == X86ISD::VSRAI)
16495 ShiftAmt = ElementType.getSizeInBits() - 1;
16497 return DAG.getConstant(0, VT);
16500 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16501 && "Unknown target vector shift-by-constant node");
16503 // Fold this packed vector shift into a build vector if SrcOp is a
16504 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16505 if (VT == SrcOp.getSimpleValueType() &&
16506 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16507 SmallVector<SDValue, 8> Elts;
16508 unsigned NumElts = SrcOp->getNumOperands();
16509 ConstantSDNode *ND;
16512 default: llvm_unreachable(nullptr);
16513 case X86ISD::VSHLI:
16514 for (unsigned i=0; i!=NumElts; ++i) {
16515 SDValue CurrentOp = SrcOp->getOperand(i);
16516 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16517 Elts.push_back(CurrentOp);
16520 ND = cast<ConstantSDNode>(CurrentOp);
16521 const APInt &C = ND->getAPIntValue();
16522 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16525 case X86ISD::VSRLI:
16526 for (unsigned i=0; i!=NumElts; ++i) {
16527 SDValue CurrentOp = SrcOp->getOperand(i);
16528 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16529 Elts.push_back(CurrentOp);
16532 ND = cast<ConstantSDNode>(CurrentOp);
16533 const APInt &C = ND->getAPIntValue();
16534 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16537 case X86ISD::VSRAI:
16538 for (unsigned i=0; i!=NumElts; ++i) {
16539 SDValue CurrentOp = SrcOp->getOperand(i);
16540 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16541 Elts.push_back(CurrentOp);
16544 ND = cast<ConstantSDNode>(CurrentOp);
16545 const APInt &C = ND->getAPIntValue();
16546 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16551 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16554 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16557 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16558 // may or may not be a constant. Takes immediate version of shift as input.
16559 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16560 SDValue SrcOp, SDValue ShAmt,
16561 SelectionDAG &DAG) {
16562 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16564 // Catch shift-by-constant.
16565 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16566 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16567 CShAmt->getZExtValue(), DAG);
16569 // Change opcode to non-immediate version
16571 default: llvm_unreachable("Unknown target vector shift node");
16572 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16573 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16574 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16577 // Need to build a vector containing shift amount
16578 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16581 ShOps[1] = DAG.getConstant(0, MVT::i32);
16582 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16583 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16585 // The return type has to be a 128-bit type with the same element
16586 // type as the input type.
16587 MVT EltVT = VT.getVectorElementType();
16588 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16590 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16591 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16594 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16595 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16596 /// necessary casting for \p Mask when lowering masking intrinsics.
16597 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16598 SDValue PreservedSrc,
16599 const X86Subtarget *Subtarget,
16600 SelectionDAG &DAG) {
16601 EVT VT = Op.getValueType();
16602 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16603 MVT::i1, VT.getVectorNumElements());
16604 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16605 Mask.getValueType().getSizeInBits());
16608 assert(MaskVT.isSimple() && "invalid mask type");
16610 if (isAllOnes(Mask))
16613 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16614 // are extracted by EXTRACT_SUBVECTOR.
16615 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16616 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16617 DAG.getIntPtrConstant(0));
16619 switch (Op.getOpcode()) {
16621 case X86ISD::PCMPEQM:
16622 case X86ISD::PCMPGTM:
16624 case X86ISD::CMPMU:
16625 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16627 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16628 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16629 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16632 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16634 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16635 case Intrinsic::x86_fma_vfmadd_ps:
16636 case Intrinsic::x86_fma_vfmadd_pd:
16637 case Intrinsic::x86_fma_vfmadd_ps_256:
16638 case Intrinsic::x86_fma_vfmadd_pd_256:
16639 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16640 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16641 return X86ISD::FMADD;
16642 case Intrinsic::x86_fma_vfmsub_ps:
16643 case Intrinsic::x86_fma_vfmsub_pd:
16644 case Intrinsic::x86_fma_vfmsub_ps_256:
16645 case Intrinsic::x86_fma_vfmsub_pd_256:
16646 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16647 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16648 return X86ISD::FMSUB;
16649 case Intrinsic::x86_fma_vfnmadd_ps:
16650 case Intrinsic::x86_fma_vfnmadd_pd:
16651 case Intrinsic::x86_fma_vfnmadd_ps_256:
16652 case Intrinsic::x86_fma_vfnmadd_pd_256:
16653 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16654 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16655 return X86ISD::FNMADD;
16656 case Intrinsic::x86_fma_vfnmsub_ps:
16657 case Intrinsic::x86_fma_vfnmsub_pd:
16658 case Intrinsic::x86_fma_vfnmsub_ps_256:
16659 case Intrinsic::x86_fma_vfnmsub_pd_256:
16660 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16661 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16662 return X86ISD::FNMSUB;
16663 case Intrinsic::x86_fma_vfmaddsub_ps:
16664 case Intrinsic::x86_fma_vfmaddsub_pd:
16665 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16666 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16667 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16668 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16669 return X86ISD::FMADDSUB;
16670 case Intrinsic::x86_fma_vfmsubadd_ps:
16671 case Intrinsic::x86_fma_vfmsubadd_pd:
16672 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16673 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16674 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16675 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16676 return X86ISD::FMSUBADD;
16680 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16681 SelectionDAG &DAG) {
16683 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16684 EVT VT = Op.getValueType();
16685 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16687 switch(IntrData->Type) {
16688 case INTR_TYPE_1OP:
16689 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16690 case INTR_TYPE_2OP:
16691 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16693 case INTR_TYPE_3OP:
16694 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16695 Op.getOperand(2), Op.getOperand(3));
16696 case INTR_TYPE_1OP_MASK_RM: {
16697 SDValue Src = Op.getOperand(1);
16698 SDValue Src0 = Op.getOperand(2);
16699 SDValue Mask = Op.getOperand(3);
16700 SDValue RoundingMode = Op.getOperand(4);
16701 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16703 Mask, Src0, Subtarget, DAG);
16707 case CMP_MASK_CC: {
16708 // Comparison intrinsics with masks.
16709 // Example of transformation:
16710 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16711 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16713 // (v8i1 (insert_subvector undef,
16714 // (v2i1 (and (PCMPEQM %a, %b),
16715 // (extract_subvector
16716 // (v8i1 (bitcast %mask)), 0))), 0))))
16717 EVT VT = Op.getOperand(1).getValueType();
16718 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16719 VT.getVectorNumElements());
16720 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16721 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16722 Mask.getValueType().getSizeInBits());
16724 if (IntrData->Type == CMP_MASK_CC) {
16725 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16726 Op.getOperand(2), Op.getOperand(3));
16728 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16729 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16732 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16733 DAG.getTargetConstant(0, MaskVT),
16735 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16736 DAG.getUNDEF(BitcastVT), CmpMask,
16737 DAG.getIntPtrConstant(0));
16738 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16740 case COMI: { // Comparison intrinsics
16741 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16742 SDValue LHS = Op.getOperand(1);
16743 SDValue RHS = Op.getOperand(2);
16744 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16745 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16746 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16747 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16748 DAG.getConstant(X86CC, MVT::i8), Cond);
16749 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16752 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16753 Op.getOperand(1), Op.getOperand(2), DAG);
16755 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16756 Op.getOperand(1), Op.getOperand(2), DAG),
16757 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);;
16764 default: return SDValue(); // Don't custom lower most intrinsics.
16766 // Arithmetic intrinsics.
16767 case Intrinsic::x86_sse2_pmulu_dq:
16768 case Intrinsic::x86_avx2_pmulu_dq:
16769 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16770 Op.getOperand(1), Op.getOperand(2));
16772 case Intrinsic::x86_sse41_pmuldq:
16773 case Intrinsic::x86_avx2_pmul_dq:
16774 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16775 Op.getOperand(1), Op.getOperand(2));
16777 case Intrinsic::x86_sse2_pmulhu_w:
16778 case Intrinsic::x86_avx2_pmulhu_w:
16779 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16780 Op.getOperand(1), Op.getOperand(2));
16782 case Intrinsic::x86_sse2_pmulh_w:
16783 case Intrinsic::x86_avx2_pmulh_w:
16784 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16785 Op.getOperand(1), Op.getOperand(2));
16787 // SSE/SSE2/AVX floating point max/min intrinsics.
16788 case Intrinsic::x86_sse_max_ps:
16789 case Intrinsic::x86_sse2_max_pd:
16790 case Intrinsic::x86_avx_max_ps_256:
16791 case Intrinsic::x86_avx_max_pd_256:
16792 case Intrinsic::x86_sse_min_ps:
16793 case Intrinsic::x86_sse2_min_pd:
16794 case Intrinsic::x86_avx_min_ps_256:
16795 case Intrinsic::x86_avx_min_pd_256: {
16798 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16799 case Intrinsic::x86_sse_max_ps:
16800 case Intrinsic::x86_sse2_max_pd:
16801 case Intrinsic::x86_avx_max_ps_256:
16802 case Intrinsic::x86_avx_max_pd_256:
16803 Opcode = X86ISD::FMAX;
16805 case Intrinsic::x86_sse_min_ps:
16806 case Intrinsic::x86_sse2_min_pd:
16807 case Intrinsic::x86_avx_min_ps_256:
16808 case Intrinsic::x86_avx_min_pd_256:
16809 Opcode = X86ISD::FMIN;
16812 return DAG.getNode(Opcode, dl, Op.getValueType(),
16813 Op.getOperand(1), Op.getOperand(2));
16816 // AVX2 variable shift intrinsics
16817 case Intrinsic::x86_avx2_psllv_d:
16818 case Intrinsic::x86_avx2_psllv_q:
16819 case Intrinsic::x86_avx2_psllv_d_256:
16820 case Intrinsic::x86_avx2_psllv_q_256:
16821 case Intrinsic::x86_avx2_psrlv_d:
16822 case Intrinsic::x86_avx2_psrlv_q:
16823 case Intrinsic::x86_avx2_psrlv_d_256:
16824 case Intrinsic::x86_avx2_psrlv_q_256:
16825 case Intrinsic::x86_avx2_psrav_d:
16826 case Intrinsic::x86_avx2_psrav_d_256: {
16829 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16830 case Intrinsic::x86_avx2_psllv_d:
16831 case Intrinsic::x86_avx2_psllv_q:
16832 case Intrinsic::x86_avx2_psllv_d_256:
16833 case Intrinsic::x86_avx2_psllv_q_256:
16836 case Intrinsic::x86_avx2_psrlv_d:
16837 case Intrinsic::x86_avx2_psrlv_q:
16838 case Intrinsic::x86_avx2_psrlv_d_256:
16839 case Intrinsic::x86_avx2_psrlv_q_256:
16842 case Intrinsic::x86_avx2_psrav_d:
16843 case Intrinsic::x86_avx2_psrav_d_256:
16847 return DAG.getNode(Opcode, dl, Op.getValueType(),
16848 Op.getOperand(1), Op.getOperand(2));
16851 case Intrinsic::x86_sse2_packssdw_128:
16852 case Intrinsic::x86_sse2_packsswb_128:
16853 case Intrinsic::x86_avx2_packssdw:
16854 case Intrinsic::x86_avx2_packsswb:
16855 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16856 Op.getOperand(1), Op.getOperand(2));
16858 case Intrinsic::x86_sse2_packuswb_128:
16859 case Intrinsic::x86_sse41_packusdw:
16860 case Intrinsic::x86_avx2_packuswb:
16861 case Intrinsic::x86_avx2_packusdw:
16862 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16863 Op.getOperand(1), Op.getOperand(2));
16865 case Intrinsic::x86_ssse3_pshuf_b_128:
16866 case Intrinsic::x86_avx2_pshuf_b:
16867 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16868 Op.getOperand(1), Op.getOperand(2));
16870 case Intrinsic::x86_sse2_pshuf_d:
16871 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16872 Op.getOperand(1), Op.getOperand(2));
16874 case Intrinsic::x86_sse2_pshufl_w:
16875 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16876 Op.getOperand(1), Op.getOperand(2));
16878 case Intrinsic::x86_sse2_pshufh_w:
16879 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16880 Op.getOperand(1), Op.getOperand(2));
16882 case Intrinsic::x86_ssse3_psign_b_128:
16883 case Intrinsic::x86_ssse3_psign_w_128:
16884 case Intrinsic::x86_ssse3_psign_d_128:
16885 case Intrinsic::x86_avx2_psign_b:
16886 case Intrinsic::x86_avx2_psign_w:
16887 case Intrinsic::x86_avx2_psign_d:
16888 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16889 Op.getOperand(1), Op.getOperand(2));
16891 case Intrinsic::x86_avx2_permd:
16892 case Intrinsic::x86_avx2_permps:
16893 // Operands intentionally swapped. Mask is last operand to intrinsic,
16894 // but second operand for node/instruction.
16895 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16896 Op.getOperand(2), Op.getOperand(1));
16898 case Intrinsic::x86_avx512_mask_valign_q_512:
16899 case Intrinsic::x86_avx512_mask_valign_d_512:
16900 // Vector source operands are swapped.
16901 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16902 Op.getValueType(), Op.getOperand(2),
16905 Op.getOperand(5), Op.getOperand(4),
16908 // ptest and testp intrinsics. The intrinsic these come from are designed to
16909 // return an integer value, not just an instruction so lower it to the ptest
16910 // or testp pattern and a setcc for the result.
16911 case Intrinsic::x86_sse41_ptestz:
16912 case Intrinsic::x86_sse41_ptestc:
16913 case Intrinsic::x86_sse41_ptestnzc:
16914 case Intrinsic::x86_avx_ptestz_256:
16915 case Intrinsic::x86_avx_ptestc_256:
16916 case Intrinsic::x86_avx_ptestnzc_256:
16917 case Intrinsic::x86_avx_vtestz_ps:
16918 case Intrinsic::x86_avx_vtestc_ps:
16919 case Intrinsic::x86_avx_vtestnzc_ps:
16920 case Intrinsic::x86_avx_vtestz_pd:
16921 case Intrinsic::x86_avx_vtestc_pd:
16922 case Intrinsic::x86_avx_vtestnzc_pd:
16923 case Intrinsic::x86_avx_vtestz_ps_256:
16924 case Intrinsic::x86_avx_vtestc_ps_256:
16925 case Intrinsic::x86_avx_vtestnzc_ps_256:
16926 case Intrinsic::x86_avx_vtestz_pd_256:
16927 case Intrinsic::x86_avx_vtestc_pd_256:
16928 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16929 bool IsTestPacked = false;
16932 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16933 case Intrinsic::x86_avx_vtestz_ps:
16934 case Intrinsic::x86_avx_vtestz_pd:
16935 case Intrinsic::x86_avx_vtestz_ps_256:
16936 case Intrinsic::x86_avx_vtestz_pd_256:
16937 IsTestPacked = true; // Fallthrough
16938 case Intrinsic::x86_sse41_ptestz:
16939 case Intrinsic::x86_avx_ptestz_256:
16941 X86CC = X86::COND_E;
16943 case Intrinsic::x86_avx_vtestc_ps:
16944 case Intrinsic::x86_avx_vtestc_pd:
16945 case Intrinsic::x86_avx_vtestc_ps_256:
16946 case Intrinsic::x86_avx_vtestc_pd_256:
16947 IsTestPacked = true; // Fallthrough
16948 case Intrinsic::x86_sse41_ptestc:
16949 case Intrinsic::x86_avx_ptestc_256:
16951 X86CC = X86::COND_B;
16953 case Intrinsic::x86_avx_vtestnzc_ps:
16954 case Intrinsic::x86_avx_vtestnzc_pd:
16955 case Intrinsic::x86_avx_vtestnzc_ps_256:
16956 case Intrinsic::x86_avx_vtestnzc_pd_256:
16957 IsTestPacked = true; // Fallthrough
16958 case Intrinsic::x86_sse41_ptestnzc:
16959 case Intrinsic::x86_avx_ptestnzc_256:
16961 X86CC = X86::COND_A;
16965 SDValue LHS = Op.getOperand(1);
16966 SDValue RHS = Op.getOperand(2);
16967 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16968 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16969 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16970 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16971 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16973 case Intrinsic::x86_avx512_kortestz_w:
16974 case Intrinsic::x86_avx512_kortestc_w: {
16975 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16976 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16977 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16978 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16979 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16980 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16981 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16984 case Intrinsic::x86_sse42_pcmpistria128:
16985 case Intrinsic::x86_sse42_pcmpestria128:
16986 case Intrinsic::x86_sse42_pcmpistric128:
16987 case Intrinsic::x86_sse42_pcmpestric128:
16988 case Intrinsic::x86_sse42_pcmpistrio128:
16989 case Intrinsic::x86_sse42_pcmpestrio128:
16990 case Intrinsic::x86_sse42_pcmpistris128:
16991 case Intrinsic::x86_sse42_pcmpestris128:
16992 case Intrinsic::x86_sse42_pcmpistriz128:
16993 case Intrinsic::x86_sse42_pcmpestriz128: {
16997 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16998 case Intrinsic::x86_sse42_pcmpistria128:
16999 Opcode = X86ISD::PCMPISTRI;
17000 X86CC = X86::COND_A;
17002 case Intrinsic::x86_sse42_pcmpestria128:
17003 Opcode = X86ISD::PCMPESTRI;
17004 X86CC = X86::COND_A;
17006 case Intrinsic::x86_sse42_pcmpistric128:
17007 Opcode = X86ISD::PCMPISTRI;
17008 X86CC = X86::COND_B;
17010 case Intrinsic::x86_sse42_pcmpestric128:
17011 Opcode = X86ISD::PCMPESTRI;
17012 X86CC = X86::COND_B;
17014 case Intrinsic::x86_sse42_pcmpistrio128:
17015 Opcode = X86ISD::PCMPISTRI;
17016 X86CC = X86::COND_O;
17018 case Intrinsic::x86_sse42_pcmpestrio128:
17019 Opcode = X86ISD::PCMPESTRI;
17020 X86CC = X86::COND_O;
17022 case Intrinsic::x86_sse42_pcmpistris128:
17023 Opcode = X86ISD::PCMPISTRI;
17024 X86CC = X86::COND_S;
17026 case Intrinsic::x86_sse42_pcmpestris128:
17027 Opcode = X86ISD::PCMPESTRI;
17028 X86CC = X86::COND_S;
17030 case Intrinsic::x86_sse42_pcmpistriz128:
17031 Opcode = X86ISD::PCMPISTRI;
17032 X86CC = X86::COND_E;
17034 case Intrinsic::x86_sse42_pcmpestriz128:
17035 Opcode = X86ISD::PCMPESTRI;
17036 X86CC = X86::COND_E;
17039 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17040 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17041 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17042 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17043 DAG.getConstant(X86CC, MVT::i8),
17044 SDValue(PCMP.getNode(), 1));
17045 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17048 case Intrinsic::x86_sse42_pcmpistri128:
17049 case Intrinsic::x86_sse42_pcmpestri128: {
17051 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17052 Opcode = X86ISD::PCMPISTRI;
17054 Opcode = X86ISD::PCMPESTRI;
17056 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17057 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17058 return DAG.getNode(Opcode, dl, VTs, NewOps);
17061 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17062 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17063 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17064 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17065 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17066 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17067 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17068 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17069 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17070 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17071 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17072 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17073 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17074 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17075 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17076 dl, Op.getValueType(),
17080 Op.getOperand(4), Op.getOperand(1),
17086 case Intrinsic::x86_fma_vfmadd_ps:
17087 case Intrinsic::x86_fma_vfmadd_pd:
17088 case Intrinsic::x86_fma_vfmsub_ps:
17089 case Intrinsic::x86_fma_vfmsub_pd:
17090 case Intrinsic::x86_fma_vfnmadd_ps:
17091 case Intrinsic::x86_fma_vfnmadd_pd:
17092 case Intrinsic::x86_fma_vfnmsub_ps:
17093 case Intrinsic::x86_fma_vfnmsub_pd:
17094 case Intrinsic::x86_fma_vfmaddsub_ps:
17095 case Intrinsic::x86_fma_vfmaddsub_pd:
17096 case Intrinsic::x86_fma_vfmsubadd_ps:
17097 case Intrinsic::x86_fma_vfmsubadd_pd:
17098 case Intrinsic::x86_fma_vfmadd_ps_256:
17099 case Intrinsic::x86_fma_vfmadd_pd_256:
17100 case Intrinsic::x86_fma_vfmsub_ps_256:
17101 case Intrinsic::x86_fma_vfmsub_pd_256:
17102 case Intrinsic::x86_fma_vfnmadd_ps_256:
17103 case Intrinsic::x86_fma_vfnmadd_pd_256:
17104 case Intrinsic::x86_fma_vfnmsub_ps_256:
17105 case Intrinsic::x86_fma_vfnmsub_pd_256:
17106 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17107 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17108 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17109 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17110 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17111 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17115 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17116 SDValue Src, SDValue Mask, SDValue Base,
17117 SDValue Index, SDValue ScaleOp, SDValue Chain,
17118 const X86Subtarget * Subtarget) {
17120 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17121 assert(C && "Invalid scale type");
17122 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17123 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17124 Index.getSimpleValueType().getVectorNumElements());
17126 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17128 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17130 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17131 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17132 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17133 SDValue Segment = DAG.getRegister(0, MVT::i32);
17134 if (Src.getOpcode() == ISD::UNDEF)
17135 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17136 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17137 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17138 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17139 return DAG.getMergeValues(RetOps, dl);
17142 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17143 SDValue Src, SDValue Mask, SDValue Base,
17144 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17146 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17147 assert(C && "Invalid scale type");
17148 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17149 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17150 SDValue Segment = DAG.getRegister(0, MVT::i32);
17151 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17152 Index.getSimpleValueType().getVectorNumElements());
17154 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17156 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17158 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17159 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17160 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17161 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17162 return SDValue(Res, 1);
17165 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17166 SDValue Mask, SDValue Base, SDValue Index,
17167 SDValue ScaleOp, SDValue Chain) {
17169 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17170 assert(C && "Invalid scale type");
17171 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17172 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17173 SDValue Segment = DAG.getRegister(0, MVT::i32);
17175 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17177 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17179 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17181 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17182 //SDVTList VTs = DAG.getVTList(MVT::Other);
17183 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17184 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17185 return SDValue(Res, 0);
17188 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17189 // read performance monitor counters (x86_rdpmc).
17190 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17191 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17192 SmallVectorImpl<SDValue> &Results) {
17193 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17194 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17197 // The ECX register is used to select the index of the performance counter
17199 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17201 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17203 // Reads the content of a 64-bit performance counter and returns it in the
17204 // registers EDX:EAX.
17205 if (Subtarget->is64Bit()) {
17206 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17207 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17210 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17211 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17214 Chain = HI.getValue(1);
17216 if (Subtarget->is64Bit()) {
17217 // The EAX register is loaded with the low-order 32 bits. The EDX register
17218 // is loaded with the supported high-order bits of the counter.
17219 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17220 DAG.getConstant(32, MVT::i8));
17221 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17222 Results.push_back(Chain);
17226 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17227 SDValue Ops[] = { LO, HI };
17228 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17229 Results.push_back(Pair);
17230 Results.push_back(Chain);
17233 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17234 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17235 // also used to custom lower READCYCLECOUNTER nodes.
17236 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17237 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17238 SmallVectorImpl<SDValue> &Results) {
17239 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17240 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17243 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17244 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17245 // and the EAX register is loaded with the low-order 32 bits.
17246 if (Subtarget->is64Bit()) {
17247 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17248 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17251 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17252 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17255 SDValue Chain = HI.getValue(1);
17257 if (Opcode == X86ISD::RDTSCP_DAG) {
17258 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17260 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17261 // the ECX register. Add 'ecx' explicitly to the chain.
17262 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17264 // Explicitly store the content of ECX at the location passed in input
17265 // to the 'rdtscp' intrinsic.
17266 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17267 MachinePointerInfo(), false, false, 0);
17270 if (Subtarget->is64Bit()) {
17271 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17272 // the EAX register is loaded with the low-order 32 bits.
17273 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17274 DAG.getConstant(32, MVT::i8));
17275 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17276 Results.push_back(Chain);
17280 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17281 SDValue Ops[] = { LO, HI };
17282 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17283 Results.push_back(Pair);
17284 Results.push_back(Chain);
17287 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17288 SelectionDAG &DAG) {
17289 SmallVector<SDValue, 2> Results;
17291 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17293 return DAG.getMergeValues(Results, DL);
17297 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17298 SelectionDAG &DAG) {
17299 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17301 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17306 switch(IntrData->Type) {
17308 llvm_unreachable("Unknown Intrinsic Type");
17312 // Emit the node with the right value type.
17313 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17314 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17316 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17317 // Otherwise return the value from Rand, which is always 0, casted to i32.
17318 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17319 DAG.getConstant(1, Op->getValueType(1)),
17320 DAG.getConstant(X86::COND_B, MVT::i32),
17321 SDValue(Result.getNode(), 1) };
17322 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17323 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17326 // Return { result, isValid, chain }.
17327 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17328 SDValue(Result.getNode(), 2));
17331 //gather(v1, mask, index, base, scale);
17332 SDValue Chain = Op.getOperand(0);
17333 SDValue Src = Op.getOperand(2);
17334 SDValue Base = Op.getOperand(3);
17335 SDValue Index = Op.getOperand(4);
17336 SDValue Mask = Op.getOperand(5);
17337 SDValue Scale = Op.getOperand(6);
17338 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17342 //scatter(base, mask, index, v1, scale);
17343 SDValue Chain = Op.getOperand(0);
17344 SDValue Base = Op.getOperand(2);
17345 SDValue Mask = Op.getOperand(3);
17346 SDValue Index = Op.getOperand(4);
17347 SDValue Src = Op.getOperand(5);
17348 SDValue Scale = Op.getOperand(6);
17349 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17352 SDValue Hint = Op.getOperand(6);
17354 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17355 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17356 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17357 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17358 SDValue Chain = Op.getOperand(0);
17359 SDValue Mask = Op.getOperand(2);
17360 SDValue Index = Op.getOperand(3);
17361 SDValue Base = Op.getOperand(4);
17362 SDValue Scale = Op.getOperand(5);
17363 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17365 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17367 SmallVector<SDValue, 2> Results;
17368 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17369 return DAG.getMergeValues(Results, dl);
17371 // Read Performance Monitoring Counters.
17373 SmallVector<SDValue, 2> Results;
17374 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17375 return DAG.getMergeValues(Results, dl);
17377 // XTEST intrinsics.
17379 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17380 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17381 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17382 DAG.getConstant(X86::COND_NE, MVT::i8),
17384 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17385 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17386 Ret, SDValue(InTrans.getNode(), 1));
17390 SmallVector<SDValue, 2> Results;
17391 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17392 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17393 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17394 DAG.getConstant(-1, MVT::i8));
17395 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17396 Op.getOperand(4), GenCF.getValue(1));
17397 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17398 Op.getOperand(5), MachinePointerInfo(),
17400 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17401 DAG.getConstant(X86::COND_B, MVT::i8),
17403 Results.push_back(SetCC);
17404 Results.push_back(Store);
17405 return DAG.getMergeValues(Results, dl);
17410 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17411 SelectionDAG &DAG) const {
17412 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17413 MFI->setReturnAddressIsTaken(true);
17415 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17418 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17420 EVT PtrVT = getPointerTy();
17423 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17424 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17425 DAG.getSubtarget().getRegisterInfo());
17426 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17427 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17428 DAG.getNode(ISD::ADD, dl, PtrVT,
17429 FrameAddr, Offset),
17430 MachinePointerInfo(), false, false, false, 0);
17433 // Just load the return address.
17434 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17435 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17436 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17439 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17440 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17441 MFI->setFrameAddressIsTaken(true);
17443 EVT VT = Op.getValueType();
17444 SDLoc dl(Op); // FIXME probably not meaningful
17445 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17446 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17447 DAG.getSubtarget().getRegisterInfo());
17448 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17449 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17450 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17451 "Invalid Frame Register!");
17452 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17454 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17455 MachinePointerInfo(),
17456 false, false, false, 0);
17460 // FIXME? Maybe this could be a TableGen attribute on some registers and
17461 // this table could be generated automatically from RegInfo.
17462 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17464 unsigned Reg = StringSwitch<unsigned>(RegName)
17465 .Case("esp", X86::ESP)
17466 .Case("rsp", X86::RSP)
17470 report_fatal_error("Invalid register name global variable");
17473 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17474 SelectionDAG &DAG) const {
17475 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17476 DAG.getSubtarget().getRegisterInfo());
17477 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17480 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17481 SDValue Chain = Op.getOperand(0);
17482 SDValue Offset = Op.getOperand(1);
17483 SDValue Handler = Op.getOperand(2);
17486 EVT PtrVT = getPointerTy();
17487 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17488 DAG.getSubtarget().getRegisterInfo());
17489 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17490 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17491 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17492 "Invalid Frame Register!");
17493 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17494 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17496 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17497 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17498 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17499 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17501 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17503 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17504 DAG.getRegister(StoreAddrReg, PtrVT));
17507 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17508 SelectionDAG &DAG) const {
17510 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17511 DAG.getVTList(MVT::i32, MVT::Other),
17512 Op.getOperand(0), Op.getOperand(1));
17515 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17516 SelectionDAG &DAG) const {
17518 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17519 Op.getOperand(0), Op.getOperand(1));
17522 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17523 return Op.getOperand(0);
17526 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17527 SelectionDAG &DAG) const {
17528 SDValue Root = Op.getOperand(0);
17529 SDValue Trmp = Op.getOperand(1); // trampoline
17530 SDValue FPtr = Op.getOperand(2); // nested function
17531 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17534 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17535 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17537 if (Subtarget->is64Bit()) {
17538 SDValue OutChains[6];
17540 // Large code-model.
17541 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17542 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17544 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17545 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17547 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17549 // Load the pointer to the nested function into R11.
17550 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17551 SDValue Addr = Trmp;
17552 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17553 Addr, MachinePointerInfo(TrmpAddr),
17556 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17557 DAG.getConstant(2, MVT::i64));
17558 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17559 MachinePointerInfo(TrmpAddr, 2),
17562 // Load the 'nest' parameter value into R10.
17563 // R10 is specified in X86CallingConv.td
17564 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17565 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17566 DAG.getConstant(10, MVT::i64));
17567 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17568 Addr, MachinePointerInfo(TrmpAddr, 10),
17571 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17572 DAG.getConstant(12, MVT::i64));
17573 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17574 MachinePointerInfo(TrmpAddr, 12),
17577 // Jump to the nested function.
17578 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17579 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17580 DAG.getConstant(20, MVT::i64));
17581 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17582 Addr, MachinePointerInfo(TrmpAddr, 20),
17585 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17586 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17587 DAG.getConstant(22, MVT::i64));
17588 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17589 MachinePointerInfo(TrmpAddr, 22),
17592 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17594 const Function *Func =
17595 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17596 CallingConv::ID CC = Func->getCallingConv();
17601 llvm_unreachable("Unsupported calling convention");
17602 case CallingConv::C:
17603 case CallingConv::X86_StdCall: {
17604 // Pass 'nest' parameter in ECX.
17605 // Must be kept in sync with X86CallingConv.td
17606 NestReg = X86::ECX;
17608 // Check that ECX wasn't needed by an 'inreg' parameter.
17609 FunctionType *FTy = Func->getFunctionType();
17610 const AttributeSet &Attrs = Func->getAttributes();
17612 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17613 unsigned InRegCount = 0;
17616 for (FunctionType::param_iterator I = FTy->param_begin(),
17617 E = FTy->param_end(); I != E; ++I, ++Idx)
17618 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17619 // FIXME: should only count parameters that are lowered to integers.
17620 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17622 if (InRegCount > 2) {
17623 report_fatal_error("Nest register in use - reduce number of inreg"
17629 case CallingConv::X86_FastCall:
17630 case CallingConv::X86_ThisCall:
17631 case CallingConv::Fast:
17632 // Pass 'nest' parameter in EAX.
17633 // Must be kept in sync with X86CallingConv.td
17634 NestReg = X86::EAX;
17638 SDValue OutChains[4];
17639 SDValue Addr, Disp;
17641 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17642 DAG.getConstant(10, MVT::i32));
17643 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17645 // This is storing the opcode for MOV32ri.
17646 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17647 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17648 OutChains[0] = DAG.getStore(Root, dl,
17649 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17650 Trmp, MachinePointerInfo(TrmpAddr),
17653 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17654 DAG.getConstant(1, MVT::i32));
17655 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17656 MachinePointerInfo(TrmpAddr, 1),
17659 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17660 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17661 DAG.getConstant(5, MVT::i32));
17662 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17663 MachinePointerInfo(TrmpAddr, 5),
17666 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17667 DAG.getConstant(6, MVT::i32));
17668 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17669 MachinePointerInfo(TrmpAddr, 6),
17672 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17676 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17677 SelectionDAG &DAG) const {
17679 The rounding mode is in bits 11:10 of FPSR, and has the following
17681 00 Round to nearest
17686 FLT_ROUNDS, on the other hand, expects the following:
17693 To perform the conversion, we do:
17694 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17697 MachineFunction &MF = DAG.getMachineFunction();
17698 const TargetMachine &TM = MF.getTarget();
17699 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17700 unsigned StackAlignment = TFI.getStackAlignment();
17701 MVT VT = Op.getSimpleValueType();
17704 // Save FP Control Word to stack slot
17705 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17706 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17708 MachineMemOperand *MMO =
17709 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17710 MachineMemOperand::MOStore, 2, 2);
17712 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17713 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17714 DAG.getVTList(MVT::Other),
17715 Ops, MVT::i16, MMO);
17717 // Load FP Control Word from stack slot
17718 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17719 MachinePointerInfo(), false, false, false, 0);
17721 // Transform as necessary
17723 DAG.getNode(ISD::SRL, DL, MVT::i16,
17724 DAG.getNode(ISD::AND, DL, MVT::i16,
17725 CWD, DAG.getConstant(0x800, MVT::i16)),
17726 DAG.getConstant(11, MVT::i8));
17728 DAG.getNode(ISD::SRL, DL, MVT::i16,
17729 DAG.getNode(ISD::AND, DL, MVT::i16,
17730 CWD, DAG.getConstant(0x400, MVT::i16)),
17731 DAG.getConstant(9, MVT::i8));
17734 DAG.getNode(ISD::AND, DL, MVT::i16,
17735 DAG.getNode(ISD::ADD, DL, MVT::i16,
17736 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17737 DAG.getConstant(1, MVT::i16)),
17738 DAG.getConstant(3, MVT::i16));
17740 return DAG.getNode((VT.getSizeInBits() < 16 ?
17741 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17744 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17745 MVT VT = Op.getSimpleValueType();
17747 unsigned NumBits = VT.getSizeInBits();
17750 Op = Op.getOperand(0);
17751 if (VT == MVT::i8) {
17752 // Zero extend to i32 since there is not an i8 bsr.
17754 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17757 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17758 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17759 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17761 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17764 DAG.getConstant(NumBits+NumBits-1, OpVT),
17765 DAG.getConstant(X86::COND_E, MVT::i8),
17768 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17770 // Finally xor with NumBits-1.
17771 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17774 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17778 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17779 MVT VT = Op.getSimpleValueType();
17781 unsigned NumBits = VT.getSizeInBits();
17784 Op = Op.getOperand(0);
17785 if (VT == MVT::i8) {
17786 // Zero extend to i32 since there is not an i8 bsr.
17788 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17791 // Issue a bsr (scan bits in reverse).
17792 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17793 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17795 // And xor with NumBits-1.
17796 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17799 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17803 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17804 MVT VT = Op.getSimpleValueType();
17805 unsigned NumBits = VT.getSizeInBits();
17807 Op = Op.getOperand(0);
17809 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17810 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17811 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17813 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17816 DAG.getConstant(NumBits, VT),
17817 DAG.getConstant(X86::COND_E, MVT::i8),
17820 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17823 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17824 // ones, and then concatenate the result back.
17825 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17826 MVT VT = Op.getSimpleValueType();
17828 assert(VT.is256BitVector() && VT.isInteger() &&
17829 "Unsupported value type for operation");
17831 unsigned NumElems = VT.getVectorNumElements();
17834 // Extract the LHS vectors
17835 SDValue LHS = Op.getOperand(0);
17836 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17837 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17839 // Extract the RHS vectors
17840 SDValue RHS = Op.getOperand(1);
17841 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17842 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17844 MVT EltVT = VT.getVectorElementType();
17845 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17847 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17848 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17849 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17852 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17853 assert(Op.getSimpleValueType().is256BitVector() &&
17854 Op.getSimpleValueType().isInteger() &&
17855 "Only handle AVX 256-bit vector integer operation");
17856 return Lower256IntArith(Op, DAG);
17859 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17860 assert(Op.getSimpleValueType().is256BitVector() &&
17861 Op.getSimpleValueType().isInteger() &&
17862 "Only handle AVX 256-bit vector integer operation");
17863 return Lower256IntArith(Op, DAG);
17866 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17867 SelectionDAG &DAG) {
17869 MVT VT = Op.getSimpleValueType();
17871 // Decompose 256-bit ops into smaller 128-bit ops.
17872 if (VT.is256BitVector() && !Subtarget->hasInt256())
17873 return Lower256IntArith(Op, DAG);
17875 SDValue A = Op.getOperand(0);
17876 SDValue B = Op.getOperand(1);
17878 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17879 if (VT == MVT::v4i32) {
17880 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17881 "Should not custom lower when pmuldq is available!");
17883 // Extract the odd parts.
17884 static const int UnpackMask[] = { 1, -1, 3, -1 };
17885 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17886 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17888 // Multiply the even parts.
17889 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17890 // Now multiply odd parts.
17891 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17893 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17894 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17896 // Merge the two vectors back together with a shuffle. This expands into 2
17898 static const int ShufMask[] = { 0, 4, 2, 6 };
17899 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17902 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17903 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17905 // Ahi = psrlqi(a, 32);
17906 // Bhi = psrlqi(b, 32);
17908 // AloBlo = pmuludq(a, b);
17909 // AloBhi = pmuludq(a, Bhi);
17910 // AhiBlo = pmuludq(Ahi, b);
17912 // AloBhi = psllqi(AloBhi, 32);
17913 // AhiBlo = psllqi(AhiBlo, 32);
17914 // return AloBlo + AloBhi + AhiBlo;
17916 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17917 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17919 // Bit cast to 32-bit vectors for MULUDQ
17920 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17921 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17922 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17923 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17924 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17925 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17927 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17928 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17929 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17931 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17932 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17934 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17935 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17938 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17939 assert(Subtarget->isTargetWin64() && "Unexpected target");
17940 EVT VT = Op.getValueType();
17941 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17942 "Unexpected return type for lowering");
17946 switch (Op->getOpcode()) {
17947 default: llvm_unreachable("Unexpected request for libcall!");
17948 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17949 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17950 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17951 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17952 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17953 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17957 SDValue InChain = DAG.getEntryNode();
17959 TargetLowering::ArgListTy Args;
17960 TargetLowering::ArgListEntry Entry;
17961 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17962 EVT ArgVT = Op->getOperand(i).getValueType();
17963 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17964 "Unexpected argument type for lowering");
17965 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17966 Entry.Node = StackPtr;
17967 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17969 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17970 Entry.Ty = PointerType::get(ArgTy,0);
17971 Entry.isSExt = false;
17972 Entry.isZExt = false;
17973 Args.push_back(Entry);
17976 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17979 TargetLowering::CallLoweringInfo CLI(DAG);
17980 CLI.setDebugLoc(dl).setChain(InChain)
17981 .setCallee(getLibcallCallingConv(LC),
17982 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17983 Callee, std::move(Args), 0)
17984 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17986 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17987 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17990 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17991 SelectionDAG &DAG) {
17992 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17993 EVT VT = Op0.getValueType();
17996 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17997 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17999 // PMULxD operations multiply each even value (starting at 0) of LHS with
18000 // the related value of RHS and produce a widen result.
18001 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18002 // => <2 x i64> <ae|cg>
18004 // In other word, to have all the results, we need to perform two PMULxD:
18005 // 1. one with the even values.
18006 // 2. one with the odd values.
18007 // To achieve #2, with need to place the odd values at an even position.
18009 // Place the odd value at an even position (basically, shift all values 1
18010 // step to the left):
18011 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18012 // <a|b|c|d> => <b|undef|d|undef>
18013 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18014 // <e|f|g|h> => <f|undef|h|undef>
18015 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18017 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18019 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18020 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18022 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18023 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18024 // => <2 x i64> <ae|cg>
18025 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18026 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18027 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18028 // => <2 x i64> <bf|dh>
18029 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18030 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18032 // Shuffle it back into the right order.
18033 SDValue Highs, Lows;
18034 if (VT == MVT::v8i32) {
18035 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18036 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18037 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18038 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18040 const int HighMask[] = {1, 5, 3, 7};
18041 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18042 const int LowMask[] = {0, 4, 2, 6};
18043 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18046 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18047 // unsigned multiply.
18048 if (IsSigned && !Subtarget->hasSSE41()) {
18050 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18051 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18052 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18053 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18054 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18056 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18057 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18060 // The first result of MUL_LOHI is actually the low value, followed by the
18062 SDValue Ops[] = {Lows, Highs};
18063 return DAG.getMergeValues(Ops, dl);
18066 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18067 const X86Subtarget *Subtarget) {
18068 MVT VT = Op.getSimpleValueType();
18070 SDValue R = Op.getOperand(0);
18071 SDValue Amt = Op.getOperand(1);
18073 // Optimize shl/srl/sra with constant shift amount.
18074 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18075 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18076 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18078 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18079 (Subtarget->hasInt256() &&
18080 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18081 (Subtarget->hasAVX512() &&
18082 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18083 if (Op.getOpcode() == ISD::SHL)
18084 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18086 if (Op.getOpcode() == ISD::SRL)
18087 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18089 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18090 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18094 if (VT == MVT::v16i8) {
18095 if (Op.getOpcode() == ISD::SHL) {
18096 // Make a large shift.
18097 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18098 MVT::v8i16, R, ShiftAmt,
18100 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18101 // Zero out the rightmost bits.
18102 SmallVector<SDValue, 16> V(16,
18103 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18105 return DAG.getNode(ISD::AND, dl, VT, SHL,
18106 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18108 if (Op.getOpcode() == ISD::SRL) {
18109 // Make a large shift.
18110 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18111 MVT::v8i16, R, ShiftAmt,
18113 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18114 // Zero out the leftmost bits.
18115 SmallVector<SDValue, 16> V(16,
18116 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18118 return DAG.getNode(ISD::AND, dl, VT, SRL,
18119 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18121 if (Op.getOpcode() == ISD::SRA) {
18122 if (ShiftAmt == 7) {
18123 // R s>> 7 === R s< 0
18124 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18125 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18128 // R s>> a === ((R u>> a) ^ m) - m
18129 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18130 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18132 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18133 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18134 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18137 llvm_unreachable("Unknown shift opcode.");
18140 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18141 if (Op.getOpcode() == ISD::SHL) {
18142 // Make a large shift.
18143 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18144 MVT::v16i16, R, ShiftAmt,
18146 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18147 // Zero out the rightmost bits.
18148 SmallVector<SDValue, 32> V(32,
18149 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18151 return DAG.getNode(ISD::AND, dl, VT, SHL,
18152 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18154 if (Op.getOpcode() == ISD::SRL) {
18155 // Make a large shift.
18156 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18157 MVT::v16i16, R, ShiftAmt,
18159 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18160 // Zero out the leftmost bits.
18161 SmallVector<SDValue, 32> V(32,
18162 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18164 return DAG.getNode(ISD::AND, dl, VT, SRL,
18165 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18167 if (Op.getOpcode() == ISD::SRA) {
18168 if (ShiftAmt == 7) {
18169 // R s>> 7 === R s< 0
18170 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18171 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18174 // R s>> a === ((R u>> a) ^ m) - m
18175 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18176 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18178 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18179 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18180 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18183 llvm_unreachable("Unknown shift opcode.");
18188 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18189 if (!Subtarget->is64Bit() &&
18190 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18191 Amt.getOpcode() == ISD::BITCAST &&
18192 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18193 Amt = Amt.getOperand(0);
18194 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18195 VT.getVectorNumElements();
18196 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18197 uint64_t ShiftAmt = 0;
18198 for (unsigned i = 0; i != Ratio; ++i) {
18199 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18203 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18205 // Check remaining shift amounts.
18206 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18207 uint64_t ShAmt = 0;
18208 for (unsigned j = 0; j != Ratio; ++j) {
18209 ConstantSDNode *C =
18210 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18214 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18216 if (ShAmt != ShiftAmt)
18219 switch (Op.getOpcode()) {
18221 llvm_unreachable("Unknown shift opcode!");
18223 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18226 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18229 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18237 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18238 const X86Subtarget* Subtarget) {
18239 MVT VT = Op.getSimpleValueType();
18241 SDValue R = Op.getOperand(0);
18242 SDValue Amt = Op.getOperand(1);
18244 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18245 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18246 (Subtarget->hasInt256() &&
18247 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18248 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18249 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18251 EVT EltVT = VT.getVectorElementType();
18253 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18254 unsigned NumElts = VT.getVectorNumElements();
18256 for (i = 0; i != NumElts; ++i) {
18257 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18261 for (j = i; j != NumElts; ++j) {
18262 SDValue Arg = Amt.getOperand(j);
18263 if (Arg.getOpcode() == ISD::UNDEF) continue;
18264 if (Arg != Amt.getOperand(i))
18267 if (i != NumElts && j == NumElts)
18268 BaseShAmt = Amt.getOperand(i);
18270 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18271 Amt = Amt.getOperand(0);
18272 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18273 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18274 SDValue InVec = Amt.getOperand(0);
18275 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18276 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18278 for (; i != NumElts; ++i) {
18279 SDValue Arg = InVec.getOperand(i);
18280 if (Arg.getOpcode() == ISD::UNDEF) continue;
18284 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18285 if (ConstantSDNode *C =
18286 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18287 unsigned SplatIdx =
18288 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18289 if (C->getZExtValue() == SplatIdx)
18290 BaseShAmt = InVec.getOperand(1);
18293 if (!BaseShAmt.getNode())
18294 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18295 DAG.getIntPtrConstant(0));
18299 if (BaseShAmt.getNode()) {
18300 if (EltVT.bitsGT(MVT::i32))
18301 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18302 else if (EltVT.bitsLT(MVT::i32))
18303 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18305 switch (Op.getOpcode()) {
18307 llvm_unreachable("Unknown shift opcode!");
18309 switch (VT.SimpleTy) {
18310 default: return SDValue();
18319 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18322 switch (VT.SimpleTy) {
18323 default: return SDValue();
18330 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18333 switch (VT.SimpleTy) {
18334 default: return SDValue();
18343 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18349 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18350 if (!Subtarget->is64Bit() &&
18351 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18352 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18353 Amt.getOpcode() == ISD::BITCAST &&
18354 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18355 Amt = Amt.getOperand(0);
18356 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18357 VT.getVectorNumElements();
18358 std::vector<SDValue> Vals(Ratio);
18359 for (unsigned i = 0; i != Ratio; ++i)
18360 Vals[i] = Amt.getOperand(i);
18361 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18362 for (unsigned j = 0; j != Ratio; ++j)
18363 if (Vals[j] != Amt.getOperand(i + j))
18366 switch (Op.getOpcode()) {
18368 llvm_unreachable("Unknown shift opcode!");
18370 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18372 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18374 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18381 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18382 SelectionDAG &DAG) {
18383 MVT VT = Op.getSimpleValueType();
18385 SDValue R = Op.getOperand(0);
18386 SDValue Amt = Op.getOperand(1);
18389 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18390 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18392 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18396 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18400 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18402 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18403 if (Subtarget->hasInt256()) {
18404 if (Op.getOpcode() == ISD::SRL &&
18405 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18406 VT == MVT::v4i64 || VT == MVT::v8i32))
18408 if (Op.getOpcode() == ISD::SHL &&
18409 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18410 VT == MVT::v4i64 || VT == MVT::v8i32))
18412 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18416 // If possible, lower this packed shift into a vector multiply instead of
18417 // expanding it into a sequence of scalar shifts.
18418 // Do this only if the vector shift count is a constant build_vector.
18419 if (Op.getOpcode() == ISD::SHL &&
18420 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18421 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18422 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18423 SmallVector<SDValue, 8> Elts;
18424 EVT SVT = VT.getScalarType();
18425 unsigned SVTBits = SVT.getSizeInBits();
18426 const APInt &One = APInt(SVTBits, 1);
18427 unsigned NumElems = VT.getVectorNumElements();
18429 for (unsigned i=0; i !=NumElems; ++i) {
18430 SDValue Op = Amt->getOperand(i);
18431 if (Op->getOpcode() == ISD::UNDEF) {
18432 Elts.push_back(Op);
18436 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18437 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18438 uint64_t ShAmt = C.getZExtValue();
18439 if (ShAmt >= SVTBits) {
18440 Elts.push_back(DAG.getUNDEF(SVT));
18443 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18445 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18446 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18449 // Lower SHL with variable shift amount.
18450 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18451 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18453 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18454 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18455 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18456 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18459 // If possible, lower this shift as a sequence of two shifts by
18460 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18462 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18464 // Could be rewritten as:
18465 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18467 // The advantage is that the two shifts from the example would be
18468 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18469 // the vector shift into four scalar shifts plus four pairs of vector
18471 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18472 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18473 unsigned TargetOpcode = X86ISD::MOVSS;
18474 bool CanBeSimplified;
18475 // The splat value for the first packed shift (the 'X' from the example).
18476 SDValue Amt1 = Amt->getOperand(0);
18477 // The splat value for the second packed shift (the 'Y' from the example).
18478 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18479 Amt->getOperand(2);
18481 // See if it is possible to replace this node with a sequence of
18482 // two shifts followed by a MOVSS/MOVSD
18483 if (VT == MVT::v4i32) {
18484 // Check if it is legal to use a MOVSS.
18485 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18486 Amt2 == Amt->getOperand(3);
18487 if (!CanBeSimplified) {
18488 // Otherwise, check if we can still simplify this node using a MOVSD.
18489 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18490 Amt->getOperand(2) == Amt->getOperand(3);
18491 TargetOpcode = X86ISD::MOVSD;
18492 Amt2 = Amt->getOperand(2);
18495 // Do similar checks for the case where the machine value type
18497 CanBeSimplified = Amt1 == Amt->getOperand(1);
18498 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18499 CanBeSimplified = Amt2 == Amt->getOperand(i);
18501 if (!CanBeSimplified) {
18502 TargetOpcode = X86ISD::MOVSD;
18503 CanBeSimplified = true;
18504 Amt2 = Amt->getOperand(4);
18505 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18506 CanBeSimplified = Amt1 == Amt->getOperand(i);
18507 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18508 CanBeSimplified = Amt2 == Amt->getOperand(j);
18512 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18513 isa<ConstantSDNode>(Amt2)) {
18514 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18515 EVT CastVT = MVT::v4i32;
18517 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18518 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18520 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18521 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18522 if (TargetOpcode == X86ISD::MOVSD)
18523 CastVT = MVT::v2i64;
18524 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18525 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18526 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18528 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18532 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18533 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18536 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18537 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18539 // Turn 'a' into a mask suitable for VSELECT
18540 SDValue VSelM = DAG.getConstant(0x80, VT);
18541 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18542 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18544 SDValue CM1 = DAG.getConstant(0x0f, VT);
18545 SDValue CM2 = DAG.getConstant(0x3f, VT);
18547 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18548 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18549 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18550 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18551 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18554 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18555 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18556 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18558 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18559 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18560 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18561 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18562 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18565 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18566 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18567 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18569 // return VSELECT(r, r+r, a);
18570 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18571 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18575 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18576 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18577 // solution better.
18578 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18579 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18581 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18582 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18583 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18584 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18585 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18588 // Decompose 256-bit shifts into smaller 128-bit shifts.
18589 if (VT.is256BitVector()) {
18590 unsigned NumElems = VT.getVectorNumElements();
18591 MVT EltVT = VT.getVectorElementType();
18592 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18594 // Extract the two vectors
18595 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18596 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18598 // Recreate the shift amount vectors
18599 SDValue Amt1, Amt2;
18600 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18601 // Constant shift amount
18602 SmallVector<SDValue, 4> Amt1Csts;
18603 SmallVector<SDValue, 4> Amt2Csts;
18604 for (unsigned i = 0; i != NumElems/2; ++i)
18605 Amt1Csts.push_back(Amt->getOperand(i));
18606 for (unsigned i = NumElems/2; i != NumElems; ++i)
18607 Amt2Csts.push_back(Amt->getOperand(i));
18609 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18610 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18612 // Variable shift amount
18613 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18614 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18617 // Issue new vector shifts for the smaller types
18618 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18619 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18621 // Concatenate the result back
18622 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18628 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18629 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18630 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18631 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18632 // has only one use.
18633 SDNode *N = Op.getNode();
18634 SDValue LHS = N->getOperand(0);
18635 SDValue RHS = N->getOperand(1);
18636 unsigned BaseOp = 0;
18639 switch (Op.getOpcode()) {
18640 default: llvm_unreachable("Unknown ovf instruction!");
18642 // A subtract of one will be selected as a INC. Note that INC doesn't
18643 // set CF, so we can't do this for UADDO.
18644 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18646 BaseOp = X86ISD::INC;
18647 Cond = X86::COND_O;
18650 BaseOp = X86ISD::ADD;
18651 Cond = X86::COND_O;
18654 BaseOp = X86ISD::ADD;
18655 Cond = X86::COND_B;
18658 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18659 // set CF, so we can't do this for USUBO.
18660 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18662 BaseOp = X86ISD::DEC;
18663 Cond = X86::COND_O;
18666 BaseOp = X86ISD::SUB;
18667 Cond = X86::COND_O;
18670 BaseOp = X86ISD::SUB;
18671 Cond = X86::COND_B;
18674 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18675 Cond = X86::COND_O;
18677 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18678 if (N->getValueType(0) == MVT::i8) {
18679 BaseOp = X86ISD::UMUL8;
18680 Cond = X86::COND_O;
18683 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18685 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18688 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18689 DAG.getConstant(X86::COND_O, MVT::i32),
18690 SDValue(Sum.getNode(), 2));
18692 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18696 // Also sets EFLAGS.
18697 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18698 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18701 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18702 DAG.getConstant(Cond, MVT::i32),
18703 SDValue(Sum.getNode(), 1));
18705 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18708 // Sign extension of the low part of vector elements. This may be used either
18709 // when sign extend instructions are not available or if the vector element
18710 // sizes already match the sign-extended size. If the vector elements are in
18711 // their pre-extended size and sign extend instructions are available, that will
18712 // be handled by LowerSIGN_EXTEND.
18713 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18714 SelectionDAG &DAG) const {
18716 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18717 MVT VT = Op.getSimpleValueType();
18719 if (!Subtarget->hasSSE2() || !VT.isVector())
18722 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18723 ExtraVT.getScalarType().getSizeInBits();
18725 switch (VT.SimpleTy) {
18726 default: return SDValue();
18729 if (!Subtarget->hasFp256())
18731 if (!Subtarget->hasInt256()) {
18732 // needs to be split
18733 unsigned NumElems = VT.getVectorNumElements();
18735 // Extract the LHS vectors
18736 SDValue LHS = Op.getOperand(0);
18737 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18738 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18740 MVT EltVT = VT.getVectorElementType();
18741 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18743 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18744 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18745 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18747 SDValue Extra = DAG.getValueType(ExtraVT);
18749 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18750 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18752 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18757 SDValue Op0 = Op.getOperand(0);
18759 // This is a sign extension of some low part of vector elements without
18760 // changing the size of the vector elements themselves:
18761 // Shift-Left + Shift-Right-Algebraic.
18762 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18764 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18770 /// Returns true if the operand type is exactly twice the native width, and
18771 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18772 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18773 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18774 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18775 const X86Subtarget &Subtarget =
18776 getTargetMachine().getSubtarget<X86Subtarget>();
18777 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18780 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18781 else if (OpWidth == 128)
18782 return Subtarget.hasCmpxchg16b();
18787 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18788 return needsCmpXchgNb(SI->getValueOperand()->getType());
18791 // Note: this turns large loads into lock cmpxchg8b/16b.
18792 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18793 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18794 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18795 return needsCmpXchgNb(PTy->getElementType());
18798 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18799 const X86Subtarget &Subtarget =
18800 getTargetMachine().getSubtarget<X86Subtarget>();
18801 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18802 const Type *MemType = AI->getType();
18804 // If the operand is too big, we must see if cmpxchg8/16b is available
18805 // and default to library calls otherwise.
18806 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18807 return needsCmpXchgNb(MemType);
18809 AtomicRMWInst::BinOp Op = AI->getOperation();
18812 llvm_unreachable("Unknown atomic operation");
18813 case AtomicRMWInst::Xchg:
18814 case AtomicRMWInst::Add:
18815 case AtomicRMWInst::Sub:
18816 // It's better to use xadd, xsub or xchg for these in all cases.
18818 case AtomicRMWInst::Or:
18819 case AtomicRMWInst::And:
18820 case AtomicRMWInst::Xor:
18821 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18822 // prefix to a normal instruction for these operations.
18823 return !AI->use_empty();
18824 case AtomicRMWInst::Nand:
18825 case AtomicRMWInst::Max:
18826 case AtomicRMWInst::Min:
18827 case AtomicRMWInst::UMax:
18828 case AtomicRMWInst::UMin:
18829 // These always require a non-trivial set of data operations on x86. We must
18830 // use a cmpxchg loop.
18835 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18836 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18837 // no-sse2). There isn't any reason to disable it if the target processor
18839 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18843 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18844 const X86Subtarget &Subtarget =
18845 getTargetMachine().getSubtarget<X86Subtarget>();
18846 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18847 const Type *MemType = AI->getType();
18848 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18849 // there is no benefit in turning such RMWs into loads, and it is actually
18850 // harmful as it introduces a mfence.
18851 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18854 auto Builder = IRBuilder<>(AI);
18855 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18856 auto SynchScope = AI->getSynchScope();
18857 // We must restrict the ordering to avoid generating loads with Release or
18858 // ReleaseAcquire orderings.
18859 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18860 auto Ptr = AI->getPointerOperand();
18862 // Before the load we need a fence. Here is an example lifted from
18863 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18866 // x.store(1, relaxed);
18867 // r1 = y.fetch_add(0, release);
18869 // y.fetch_add(42, acquire);
18870 // r2 = x.load(relaxed);
18871 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18872 // lowered to just a load without a fence. A mfence flushes the store buffer,
18873 // making the optimization clearly correct.
18874 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18875 // otherwise, we might be able to be more agressive on relaxed idempotent
18876 // rmw. In practice, they do not look useful, so we don't try to be
18877 // especially clever.
18878 if (SynchScope == SingleThread) {
18879 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18880 // the IR level, so we must wrap it in an intrinsic.
18882 } else if (hasMFENCE(Subtarget)) {
18883 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18884 Intrinsic::x86_sse2_mfence);
18885 Builder.CreateCall(MFence);
18887 // FIXME: it might make sense to use a locked operation here but on a
18888 // different cache-line to prevent cache-line bouncing. In practice it
18889 // is probably a small win, and x86 processors without mfence are rare
18890 // enough that we do not bother.
18894 // Finally we can emit the atomic load.
18895 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18896 AI->getType()->getPrimitiveSizeInBits());
18897 Loaded->setAtomic(Order, SynchScope);
18898 AI->replaceAllUsesWith(Loaded);
18899 AI->eraseFromParent();
18903 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18904 SelectionDAG &DAG) {
18906 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18907 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18908 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18909 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18911 // The only fence that needs an instruction is a sequentially-consistent
18912 // cross-thread fence.
18913 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18914 if (hasMFENCE(*Subtarget))
18915 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18917 SDValue Chain = Op.getOperand(0);
18918 SDValue Zero = DAG.getConstant(0, MVT::i32);
18920 DAG.getRegister(X86::ESP, MVT::i32), // Base
18921 DAG.getTargetConstant(1, MVT::i8), // Scale
18922 DAG.getRegister(0, MVT::i32), // Index
18923 DAG.getTargetConstant(0, MVT::i32), // Disp
18924 DAG.getRegister(0, MVT::i32), // Segment.
18928 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18929 return SDValue(Res, 0);
18932 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18933 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18936 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18937 SelectionDAG &DAG) {
18938 MVT T = Op.getSimpleValueType();
18942 switch(T.SimpleTy) {
18943 default: llvm_unreachable("Invalid value type!");
18944 case MVT::i8: Reg = X86::AL; size = 1; break;
18945 case MVT::i16: Reg = X86::AX; size = 2; break;
18946 case MVT::i32: Reg = X86::EAX; size = 4; break;
18948 assert(Subtarget->is64Bit() && "Node not type legal!");
18949 Reg = X86::RAX; size = 8;
18952 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18953 Op.getOperand(2), SDValue());
18954 SDValue Ops[] = { cpIn.getValue(0),
18957 DAG.getTargetConstant(size, MVT::i8),
18958 cpIn.getValue(1) };
18959 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18960 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18961 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18965 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18966 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18967 MVT::i32, cpOut.getValue(2));
18968 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18969 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18971 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18972 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18973 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18977 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18978 SelectionDAG &DAG) {
18979 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18980 MVT DstVT = Op.getSimpleValueType();
18982 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18983 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18984 if (DstVT != MVT::f64)
18985 // This conversion needs to be expanded.
18988 SDValue InVec = Op->getOperand(0);
18990 unsigned NumElts = SrcVT.getVectorNumElements();
18991 EVT SVT = SrcVT.getVectorElementType();
18993 // Widen the vector in input in the case of MVT::v2i32.
18994 // Example: from MVT::v2i32 to MVT::v4i32.
18995 SmallVector<SDValue, 16> Elts;
18996 for (unsigned i = 0, e = NumElts; i != e; ++i)
18997 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18998 DAG.getIntPtrConstant(i)));
19000 // Explicitly mark the extra elements as Undef.
19001 SDValue Undef = DAG.getUNDEF(SVT);
19002 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19003 Elts.push_back(Undef);
19005 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19006 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19007 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19008 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19009 DAG.getIntPtrConstant(0));
19012 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19013 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19014 assert((DstVT == MVT::i64 ||
19015 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19016 "Unexpected custom BITCAST");
19017 // i64 <=> MMX conversions are Legal.
19018 if (SrcVT==MVT::i64 && DstVT.isVector())
19020 if (DstVT==MVT::i64 && SrcVT.isVector())
19022 // MMX <=> MMX conversions are Legal.
19023 if (SrcVT.isVector() && DstVT.isVector())
19025 // All other conversions need to be expanded.
19029 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19030 SDNode *Node = Op.getNode();
19032 EVT T = Node->getValueType(0);
19033 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19034 DAG.getConstant(0, T), Node->getOperand(2));
19035 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19036 cast<AtomicSDNode>(Node)->getMemoryVT(),
19037 Node->getOperand(0),
19038 Node->getOperand(1), negOp,
19039 cast<AtomicSDNode>(Node)->getMemOperand(),
19040 cast<AtomicSDNode>(Node)->getOrdering(),
19041 cast<AtomicSDNode>(Node)->getSynchScope());
19044 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19045 SDNode *Node = Op.getNode();
19047 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19049 // Convert seq_cst store -> xchg
19050 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19051 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19052 // (The only way to get a 16-byte store is cmpxchg16b)
19053 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19054 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19055 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19056 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19057 cast<AtomicSDNode>(Node)->getMemoryVT(),
19058 Node->getOperand(0),
19059 Node->getOperand(1), Node->getOperand(2),
19060 cast<AtomicSDNode>(Node)->getMemOperand(),
19061 cast<AtomicSDNode>(Node)->getOrdering(),
19062 cast<AtomicSDNode>(Node)->getSynchScope());
19063 return Swap.getValue(1);
19065 // Other atomic stores have a simple pattern.
19069 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19070 EVT VT = Op.getNode()->getSimpleValueType(0);
19072 // Let legalize expand this if it isn't a legal type yet.
19073 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19076 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19079 bool ExtraOp = false;
19080 switch (Op.getOpcode()) {
19081 default: llvm_unreachable("Invalid code");
19082 case ISD::ADDC: Opc = X86ISD::ADD; break;
19083 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19084 case ISD::SUBC: Opc = X86ISD::SUB; break;
19085 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19089 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19091 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19092 Op.getOperand(1), Op.getOperand(2));
19095 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19096 SelectionDAG &DAG) {
19097 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19099 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19100 // which returns the values as { float, float } (in XMM0) or
19101 // { double, double } (which is returned in XMM0, XMM1).
19103 SDValue Arg = Op.getOperand(0);
19104 EVT ArgVT = Arg.getValueType();
19105 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19107 TargetLowering::ArgListTy Args;
19108 TargetLowering::ArgListEntry Entry;
19112 Entry.isSExt = false;
19113 Entry.isZExt = false;
19114 Args.push_back(Entry);
19116 bool isF64 = ArgVT == MVT::f64;
19117 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19118 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19119 // the results are returned via SRet in memory.
19120 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19122 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19124 Type *RetTy = isF64
19125 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19126 : (Type*)VectorType::get(ArgTy, 4);
19128 TargetLowering::CallLoweringInfo CLI(DAG);
19129 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19130 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19132 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19135 // Returned in xmm0 and xmm1.
19136 return CallResult.first;
19138 // Returned in bits 0:31 and 32:64 xmm0.
19139 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19140 CallResult.first, DAG.getIntPtrConstant(0));
19141 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19142 CallResult.first, DAG.getIntPtrConstant(1));
19143 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19144 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19147 /// LowerOperation - Provide custom lowering hooks for some operations.
19149 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19150 switch (Op.getOpcode()) {
19151 default: llvm_unreachable("Should not custom lower this!");
19152 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19153 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19154 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19155 return LowerCMP_SWAP(Op, Subtarget, DAG);
19156 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19157 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19158 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19159 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19160 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19161 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19162 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19163 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19164 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19165 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19166 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19167 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19168 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19169 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19170 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19171 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19172 case ISD::SHL_PARTS:
19173 case ISD::SRA_PARTS:
19174 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19175 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19176 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19177 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19178 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19179 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19180 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19181 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19182 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19183 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19184 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19186 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19187 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19188 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19189 case ISD::SETCC: return LowerSETCC(Op, DAG);
19190 case ISD::SELECT: return LowerSELECT(Op, DAG);
19191 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19192 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19193 case ISD::VASTART: return LowerVASTART(Op, DAG);
19194 case ISD::VAARG: return LowerVAARG(Op, DAG);
19195 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19196 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19197 case ISD::INTRINSIC_VOID:
19198 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19199 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19200 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19201 case ISD::FRAME_TO_ARGS_OFFSET:
19202 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19203 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19204 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19205 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19206 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19207 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19208 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19209 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19210 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19211 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19212 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19213 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19214 case ISD::UMUL_LOHI:
19215 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19218 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19224 case ISD::UMULO: return LowerXALUO(Op, DAG);
19225 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19226 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19230 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19231 case ISD::ADD: return LowerADD(Op, DAG);
19232 case ISD::SUB: return LowerSUB(Op, DAG);
19233 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19237 /// ReplaceNodeResults - Replace a node with an illegal result type
19238 /// with a new node built out of custom code.
19239 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19240 SmallVectorImpl<SDValue>&Results,
19241 SelectionDAG &DAG) const {
19243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19244 switch (N->getOpcode()) {
19246 llvm_unreachable("Do not know how to custom type legalize this operation!");
19247 case ISD::SIGN_EXTEND_INREG:
19252 // We don't want to expand or promote these.
19259 case ISD::UDIVREM: {
19260 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19261 Results.push_back(V);
19264 case ISD::FP_TO_SINT:
19265 case ISD::FP_TO_UINT: {
19266 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19268 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19271 std::pair<SDValue,SDValue> Vals =
19272 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19273 SDValue FIST = Vals.first, StackSlot = Vals.second;
19274 if (FIST.getNode()) {
19275 EVT VT = N->getValueType(0);
19276 // Return a load from the stack slot.
19277 if (StackSlot.getNode())
19278 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19279 MachinePointerInfo(),
19280 false, false, false, 0));
19282 Results.push_back(FIST);
19286 case ISD::UINT_TO_FP: {
19287 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19288 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19289 N->getValueType(0) != MVT::v2f32)
19291 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19293 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19295 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19296 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19297 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19298 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19299 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19300 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19303 case ISD::FP_ROUND: {
19304 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19306 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19307 Results.push_back(V);
19310 case ISD::INTRINSIC_W_CHAIN: {
19311 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19313 default : llvm_unreachable("Do not know how to custom type "
19314 "legalize this intrinsic operation!");
19315 case Intrinsic::x86_rdtsc:
19316 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19318 case Intrinsic::x86_rdtscp:
19319 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19321 case Intrinsic::x86_rdpmc:
19322 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19325 case ISD::READCYCLECOUNTER: {
19326 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19329 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19330 EVT T = N->getValueType(0);
19331 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19332 bool Regs64bit = T == MVT::i128;
19333 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19334 SDValue cpInL, cpInH;
19335 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19336 DAG.getConstant(0, HalfT));
19337 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19338 DAG.getConstant(1, HalfT));
19339 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19340 Regs64bit ? X86::RAX : X86::EAX,
19342 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19343 Regs64bit ? X86::RDX : X86::EDX,
19344 cpInH, cpInL.getValue(1));
19345 SDValue swapInL, swapInH;
19346 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19347 DAG.getConstant(0, HalfT));
19348 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19349 DAG.getConstant(1, HalfT));
19350 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19351 Regs64bit ? X86::RBX : X86::EBX,
19352 swapInL, cpInH.getValue(1));
19353 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19354 Regs64bit ? X86::RCX : X86::ECX,
19355 swapInH, swapInL.getValue(1));
19356 SDValue Ops[] = { swapInH.getValue(0),
19358 swapInH.getValue(1) };
19359 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19360 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19361 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19362 X86ISD::LCMPXCHG8_DAG;
19363 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19364 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19365 Regs64bit ? X86::RAX : X86::EAX,
19366 HalfT, Result.getValue(1));
19367 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19368 Regs64bit ? X86::RDX : X86::EDX,
19369 HalfT, cpOutL.getValue(2));
19370 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19372 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19373 MVT::i32, cpOutH.getValue(2));
19375 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19376 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19377 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19379 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19380 Results.push_back(Success);
19381 Results.push_back(EFLAGS.getValue(1));
19384 case ISD::ATOMIC_SWAP:
19385 case ISD::ATOMIC_LOAD_ADD:
19386 case ISD::ATOMIC_LOAD_SUB:
19387 case ISD::ATOMIC_LOAD_AND:
19388 case ISD::ATOMIC_LOAD_OR:
19389 case ISD::ATOMIC_LOAD_XOR:
19390 case ISD::ATOMIC_LOAD_NAND:
19391 case ISD::ATOMIC_LOAD_MIN:
19392 case ISD::ATOMIC_LOAD_MAX:
19393 case ISD::ATOMIC_LOAD_UMIN:
19394 case ISD::ATOMIC_LOAD_UMAX:
19395 case ISD::ATOMIC_LOAD: {
19396 // Delegate to generic TypeLegalization. Situations we can really handle
19397 // should have already been dealt with by AtomicExpandPass.cpp.
19400 case ISD::BITCAST: {
19401 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19402 EVT DstVT = N->getValueType(0);
19403 EVT SrcVT = N->getOperand(0)->getValueType(0);
19405 if (SrcVT != MVT::f64 ||
19406 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19409 unsigned NumElts = DstVT.getVectorNumElements();
19410 EVT SVT = DstVT.getVectorElementType();
19411 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19412 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19413 MVT::v2f64, N->getOperand(0));
19414 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19416 if (ExperimentalVectorWideningLegalization) {
19417 // If we are legalizing vectors by widening, we already have the desired
19418 // legal vector type, just return it.
19419 Results.push_back(ToVecInt);
19423 SmallVector<SDValue, 8> Elts;
19424 for (unsigned i = 0, e = NumElts; i != e; ++i)
19425 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19426 ToVecInt, DAG.getIntPtrConstant(i)));
19428 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19433 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19435 default: return nullptr;
19436 case X86ISD::BSF: return "X86ISD::BSF";
19437 case X86ISD::BSR: return "X86ISD::BSR";
19438 case X86ISD::SHLD: return "X86ISD::SHLD";
19439 case X86ISD::SHRD: return "X86ISD::SHRD";
19440 case X86ISD::FAND: return "X86ISD::FAND";
19441 case X86ISD::FANDN: return "X86ISD::FANDN";
19442 case X86ISD::FOR: return "X86ISD::FOR";
19443 case X86ISD::FXOR: return "X86ISD::FXOR";
19444 case X86ISD::FSRL: return "X86ISD::FSRL";
19445 case X86ISD::FILD: return "X86ISD::FILD";
19446 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19447 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19448 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19449 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19450 case X86ISD::FLD: return "X86ISD::FLD";
19451 case X86ISD::FST: return "X86ISD::FST";
19452 case X86ISD::CALL: return "X86ISD::CALL";
19453 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19454 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19455 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19456 case X86ISD::BT: return "X86ISD::BT";
19457 case X86ISD::CMP: return "X86ISD::CMP";
19458 case X86ISD::COMI: return "X86ISD::COMI";
19459 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19460 case X86ISD::CMPM: return "X86ISD::CMPM";
19461 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19462 case X86ISD::SETCC: return "X86ISD::SETCC";
19463 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19464 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19465 case X86ISD::CMOV: return "X86ISD::CMOV";
19466 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19467 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19468 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19469 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19470 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19471 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19472 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19473 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19474 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19475 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19476 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19477 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19478 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19479 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19480 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19481 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19482 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19483 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19484 case X86ISD::HADD: return "X86ISD::HADD";
19485 case X86ISD::HSUB: return "X86ISD::HSUB";
19486 case X86ISD::FHADD: return "X86ISD::FHADD";
19487 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19488 case X86ISD::UMAX: return "X86ISD::UMAX";
19489 case X86ISD::UMIN: return "X86ISD::UMIN";
19490 case X86ISD::SMAX: return "X86ISD::SMAX";
19491 case X86ISD::SMIN: return "X86ISD::SMIN";
19492 case X86ISD::FMAX: return "X86ISD::FMAX";
19493 case X86ISD::FMIN: return "X86ISD::FMIN";
19494 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19495 case X86ISD::FMINC: return "X86ISD::FMINC";
19496 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19497 case X86ISD::FRCP: return "X86ISD::FRCP";
19498 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19499 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19500 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19501 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19502 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19503 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19504 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19505 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19506 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19507 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19508 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19509 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19510 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19511 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19512 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19513 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19514 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19515 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19516 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19517 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19518 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19519 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19520 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19521 case X86ISD::VSHL: return "X86ISD::VSHL";
19522 case X86ISD::VSRL: return "X86ISD::VSRL";
19523 case X86ISD::VSRA: return "X86ISD::VSRA";
19524 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19525 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19526 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19527 case X86ISD::CMPP: return "X86ISD::CMPP";
19528 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19529 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19530 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19531 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19532 case X86ISD::ADD: return "X86ISD::ADD";
19533 case X86ISD::SUB: return "X86ISD::SUB";
19534 case X86ISD::ADC: return "X86ISD::ADC";
19535 case X86ISD::SBB: return "X86ISD::SBB";
19536 case X86ISD::SMUL: return "X86ISD::SMUL";
19537 case X86ISD::UMUL: return "X86ISD::UMUL";
19538 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19539 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19540 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19541 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19542 case X86ISD::INC: return "X86ISD::INC";
19543 case X86ISD::DEC: return "X86ISD::DEC";
19544 case X86ISD::OR: return "X86ISD::OR";
19545 case X86ISD::XOR: return "X86ISD::XOR";
19546 case X86ISD::AND: return "X86ISD::AND";
19547 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19548 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19549 case X86ISD::PTEST: return "X86ISD::PTEST";
19550 case X86ISD::TESTP: return "X86ISD::TESTP";
19551 case X86ISD::TESTM: return "X86ISD::TESTM";
19552 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19553 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19554 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19555 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19556 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19557 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19558 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19559 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19560 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19561 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19562 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19563 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19564 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19565 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19566 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19567 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19568 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19569 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19570 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19571 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19572 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19573 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19574 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19575 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19576 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19577 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19578 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19579 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19580 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19581 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19582 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19583 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19584 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19585 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19586 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19587 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19588 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19589 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19590 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19591 case X86ISD::SAHF: return "X86ISD::SAHF";
19592 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19593 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19594 case X86ISD::FMADD: return "X86ISD::FMADD";
19595 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19596 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19597 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19598 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19599 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19600 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19601 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19602 case X86ISD::XTEST: return "X86ISD::XTEST";
19606 // isLegalAddressingMode - Return true if the addressing mode represented
19607 // by AM is legal for this target, for a load/store of the specified type.
19608 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19610 // X86 supports extremely general addressing modes.
19611 CodeModel::Model M = getTargetMachine().getCodeModel();
19612 Reloc::Model R = getTargetMachine().getRelocationModel();
19614 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19615 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19620 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19622 // If a reference to this global requires an extra load, we can't fold it.
19623 if (isGlobalStubReference(GVFlags))
19626 // If BaseGV requires a register for the PIC base, we cannot also have a
19627 // BaseReg specified.
19628 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19631 // If lower 4G is not available, then we must use rip-relative addressing.
19632 if ((M != CodeModel::Small || R != Reloc::Static) &&
19633 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19637 switch (AM.Scale) {
19643 // These scales always work.
19648 // These scales are formed with basereg+scalereg. Only accept if there is
19653 default: // Other stuff never works.
19660 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19661 unsigned Bits = Ty->getScalarSizeInBits();
19663 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19664 // particularly cheaper than those without.
19668 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19669 // variable shifts just as cheap as scalar ones.
19670 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19673 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19674 // fully general vector.
19678 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19679 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19681 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19682 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19683 return NumBits1 > NumBits2;
19686 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19687 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19690 if (!isTypeLegal(EVT::getEVT(Ty1)))
19693 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19695 // Assuming the caller doesn't have a zeroext or signext return parameter,
19696 // truncation all the way down to i1 is valid.
19700 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19701 return isInt<32>(Imm);
19704 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19705 // Can also use sub to handle negated immediates.
19706 return isInt<32>(Imm);
19709 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19710 if (!VT1.isInteger() || !VT2.isInteger())
19712 unsigned NumBits1 = VT1.getSizeInBits();
19713 unsigned NumBits2 = VT2.getSizeInBits();
19714 return NumBits1 > NumBits2;
19717 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19718 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19719 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19722 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19723 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19724 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19727 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19728 EVT VT1 = Val.getValueType();
19729 if (isZExtFree(VT1, VT2))
19732 if (Val.getOpcode() != ISD::LOAD)
19735 if (!VT1.isSimple() || !VT1.isInteger() ||
19736 !VT2.isSimple() || !VT2.isInteger())
19739 switch (VT1.getSimpleVT().SimpleTy) {
19744 // X86 has 8, 16, and 32-bit zero-extending loads.
19752 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19753 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19756 VT = VT.getScalarType();
19758 if (!VT.isSimple())
19761 switch (VT.getSimpleVT().SimpleTy) {
19772 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19773 // i16 instructions are longer (0x66 prefix) and potentially slower.
19774 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19777 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19778 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19779 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19780 /// are assumed to be legal.
19782 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19784 if (!VT.isSimple())
19787 MVT SVT = VT.getSimpleVT();
19789 // Very little shuffling can be done for 64-bit vectors right now.
19790 if (VT.getSizeInBits() == 64)
19793 // If this is a single-input shuffle with no 128 bit lane crossings we can
19794 // lower it into pshufb.
19795 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19796 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19797 bool isLegal = true;
19798 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19799 if (M[I] >= (int)SVT.getVectorNumElements() ||
19800 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19809 // FIXME: blends, shifts.
19810 return (SVT.getVectorNumElements() == 2 ||
19811 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19812 isMOVLMask(M, SVT) ||
19813 isMOVHLPSMask(M, SVT) ||
19814 isSHUFPMask(M, SVT) ||
19815 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19816 isPSHUFDMask(M, SVT) ||
19817 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19818 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19819 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19820 isPALIGNRMask(M, SVT, Subtarget) ||
19821 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19822 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19823 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19824 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19825 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19826 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19830 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19832 if (!VT.isSimple())
19835 MVT SVT = VT.getSimpleVT();
19836 unsigned NumElts = SVT.getVectorNumElements();
19837 // FIXME: This collection of masks seems suspect.
19840 if (NumElts == 4 && SVT.is128BitVector()) {
19841 return (isMOVLMask(Mask, SVT) ||
19842 isCommutedMOVLMask(Mask, SVT, true) ||
19843 isSHUFPMask(Mask, SVT) ||
19844 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19845 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19846 Subtarget->hasInt256()));
19851 //===----------------------------------------------------------------------===//
19852 // X86 Scheduler Hooks
19853 //===----------------------------------------------------------------------===//
19855 /// Utility function to emit xbegin specifying the start of an RTM region.
19856 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19857 const TargetInstrInfo *TII) {
19858 DebugLoc DL = MI->getDebugLoc();
19860 const BasicBlock *BB = MBB->getBasicBlock();
19861 MachineFunction::iterator I = MBB;
19864 // For the v = xbegin(), we generate
19875 MachineBasicBlock *thisMBB = MBB;
19876 MachineFunction *MF = MBB->getParent();
19877 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19878 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19879 MF->insert(I, mainMBB);
19880 MF->insert(I, sinkMBB);
19882 // Transfer the remainder of BB and its successor edges to sinkMBB.
19883 sinkMBB->splice(sinkMBB->begin(), MBB,
19884 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19885 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19889 // # fallthrough to mainMBB
19890 // # abortion to sinkMBB
19891 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19892 thisMBB->addSuccessor(mainMBB);
19893 thisMBB->addSuccessor(sinkMBB);
19897 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19898 mainMBB->addSuccessor(sinkMBB);
19901 // EAX is live into the sinkMBB
19902 sinkMBB->addLiveIn(X86::EAX);
19903 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19904 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19907 MI->eraseFromParent();
19911 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19912 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19913 // in the .td file.
19914 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19915 const TargetInstrInfo *TII) {
19917 switch (MI->getOpcode()) {
19918 default: llvm_unreachable("illegal opcode!");
19919 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19920 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19921 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19922 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19923 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19924 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19925 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19926 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19929 DebugLoc dl = MI->getDebugLoc();
19930 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19932 unsigned NumArgs = MI->getNumOperands();
19933 for (unsigned i = 1; i < NumArgs; ++i) {
19934 MachineOperand &Op = MI->getOperand(i);
19935 if (!(Op.isReg() && Op.isImplicit()))
19936 MIB.addOperand(Op);
19938 if (MI->hasOneMemOperand())
19939 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19941 BuildMI(*BB, MI, dl,
19942 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19943 .addReg(X86::XMM0);
19945 MI->eraseFromParent();
19949 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19950 // defs in an instruction pattern
19951 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19952 const TargetInstrInfo *TII) {
19954 switch (MI->getOpcode()) {
19955 default: llvm_unreachable("illegal opcode!");
19956 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19957 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19958 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19959 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19960 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19961 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19962 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19963 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19966 DebugLoc dl = MI->getDebugLoc();
19967 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19969 unsigned NumArgs = MI->getNumOperands(); // remove the results
19970 for (unsigned i = 1; i < NumArgs; ++i) {
19971 MachineOperand &Op = MI->getOperand(i);
19972 if (!(Op.isReg() && Op.isImplicit()))
19973 MIB.addOperand(Op);
19975 if (MI->hasOneMemOperand())
19976 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19978 BuildMI(*BB, MI, dl,
19979 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19982 MI->eraseFromParent();
19986 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19987 const TargetInstrInfo *TII,
19988 const X86Subtarget* Subtarget) {
19989 DebugLoc dl = MI->getDebugLoc();
19991 // Address into RAX/EAX, other two args into ECX, EDX.
19992 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19993 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19994 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19995 for (int i = 0; i < X86::AddrNumOperands; ++i)
19996 MIB.addOperand(MI->getOperand(i));
19998 unsigned ValOps = X86::AddrNumOperands;
19999 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20000 .addReg(MI->getOperand(ValOps).getReg());
20001 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20002 .addReg(MI->getOperand(ValOps+1).getReg());
20004 // The instruction doesn't actually take any operands though.
20005 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20007 MI->eraseFromParent(); // The pseudo is gone now.
20011 MachineBasicBlock *
20012 X86TargetLowering::EmitVAARG64WithCustomInserter(
20014 MachineBasicBlock *MBB) const {
20015 // Emit va_arg instruction on X86-64.
20017 // Operands to this pseudo-instruction:
20018 // 0 ) Output : destination address (reg)
20019 // 1-5) Input : va_list address (addr, i64mem)
20020 // 6 ) ArgSize : Size (in bytes) of vararg type
20021 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20022 // 8 ) Align : Alignment of type
20023 // 9 ) EFLAGS (implicit-def)
20025 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20026 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20028 unsigned DestReg = MI->getOperand(0).getReg();
20029 MachineOperand &Base = MI->getOperand(1);
20030 MachineOperand &Scale = MI->getOperand(2);
20031 MachineOperand &Index = MI->getOperand(3);
20032 MachineOperand &Disp = MI->getOperand(4);
20033 MachineOperand &Segment = MI->getOperand(5);
20034 unsigned ArgSize = MI->getOperand(6).getImm();
20035 unsigned ArgMode = MI->getOperand(7).getImm();
20036 unsigned Align = MI->getOperand(8).getImm();
20038 // Memory Reference
20039 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20040 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20041 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20043 // Machine Information
20044 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20045 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20046 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20047 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20048 DebugLoc DL = MI->getDebugLoc();
20050 // struct va_list {
20053 // i64 overflow_area (address)
20054 // i64 reg_save_area (address)
20056 // sizeof(va_list) = 24
20057 // alignment(va_list) = 8
20059 unsigned TotalNumIntRegs = 6;
20060 unsigned TotalNumXMMRegs = 8;
20061 bool UseGPOffset = (ArgMode == 1);
20062 bool UseFPOffset = (ArgMode == 2);
20063 unsigned MaxOffset = TotalNumIntRegs * 8 +
20064 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20066 /* Align ArgSize to a multiple of 8 */
20067 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20068 bool NeedsAlign = (Align > 8);
20070 MachineBasicBlock *thisMBB = MBB;
20071 MachineBasicBlock *overflowMBB;
20072 MachineBasicBlock *offsetMBB;
20073 MachineBasicBlock *endMBB;
20075 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20076 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20077 unsigned OffsetReg = 0;
20079 if (!UseGPOffset && !UseFPOffset) {
20080 // If we only pull from the overflow region, we don't create a branch.
20081 // We don't need to alter control flow.
20082 OffsetDestReg = 0; // unused
20083 OverflowDestReg = DestReg;
20085 offsetMBB = nullptr;
20086 overflowMBB = thisMBB;
20089 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20090 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20091 // If not, pull from overflow_area. (branch to overflowMBB)
20096 // offsetMBB overflowMBB
20101 // Registers for the PHI in endMBB
20102 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20103 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20105 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20106 MachineFunction *MF = MBB->getParent();
20107 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20108 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20109 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20111 MachineFunction::iterator MBBIter = MBB;
20114 // Insert the new basic blocks
20115 MF->insert(MBBIter, offsetMBB);
20116 MF->insert(MBBIter, overflowMBB);
20117 MF->insert(MBBIter, endMBB);
20119 // Transfer the remainder of MBB and its successor edges to endMBB.
20120 endMBB->splice(endMBB->begin(), thisMBB,
20121 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20122 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20124 // Make offsetMBB and overflowMBB successors of thisMBB
20125 thisMBB->addSuccessor(offsetMBB);
20126 thisMBB->addSuccessor(overflowMBB);
20128 // endMBB is a successor of both offsetMBB and overflowMBB
20129 offsetMBB->addSuccessor(endMBB);
20130 overflowMBB->addSuccessor(endMBB);
20132 // Load the offset value into a register
20133 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20134 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20138 .addDisp(Disp, UseFPOffset ? 4 : 0)
20139 .addOperand(Segment)
20140 .setMemRefs(MMOBegin, MMOEnd);
20142 // Check if there is enough room left to pull this argument.
20143 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20145 .addImm(MaxOffset + 8 - ArgSizeA8);
20147 // Branch to "overflowMBB" if offset >= max
20148 // Fall through to "offsetMBB" otherwise
20149 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20150 .addMBB(overflowMBB);
20153 // In offsetMBB, emit code to use the reg_save_area.
20155 assert(OffsetReg != 0);
20157 // Read the reg_save_area address.
20158 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20159 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20164 .addOperand(Segment)
20165 .setMemRefs(MMOBegin, MMOEnd);
20167 // Zero-extend the offset
20168 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20169 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20172 .addImm(X86::sub_32bit);
20174 // Add the offset to the reg_save_area to get the final address.
20175 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20176 .addReg(OffsetReg64)
20177 .addReg(RegSaveReg);
20179 // Compute the offset for the next argument
20180 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20181 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20183 .addImm(UseFPOffset ? 16 : 8);
20185 // Store it back into the va_list.
20186 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20190 .addDisp(Disp, UseFPOffset ? 4 : 0)
20191 .addOperand(Segment)
20192 .addReg(NextOffsetReg)
20193 .setMemRefs(MMOBegin, MMOEnd);
20196 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20201 // Emit code to use overflow area
20204 // Load the overflow_area address into a register.
20205 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20206 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20211 .addOperand(Segment)
20212 .setMemRefs(MMOBegin, MMOEnd);
20214 // If we need to align it, do so. Otherwise, just copy the address
20215 // to OverflowDestReg.
20217 // Align the overflow address
20218 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20219 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20221 // aligned_addr = (addr + (align-1)) & ~(align-1)
20222 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20223 .addReg(OverflowAddrReg)
20226 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20228 .addImm(~(uint64_t)(Align-1));
20230 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20231 .addReg(OverflowAddrReg);
20234 // Compute the next overflow address after this argument.
20235 // (the overflow address should be kept 8-byte aligned)
20236 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20237 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20238 .addReg(OverflowDestReg)
20239 .addImm(ArgSizeA8);
20241 // Store the new overflow address.
20242 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20247 .addOperand(Segment)
20248 .addReg(NextAddrReg)
20249 .setMemRefs(MMOBegin, MMOEnd);
20251 // If we branched, emit the PHI to the front of endMBB.
20253 BuildMI(*endMBB, endMBB->begin(), DL,
20254 TII->get(X86::PHI), DestReg)
20255 .addReg(OffsetDestReg).addMBB(offsetMBB)
20256 .addReg(OverflowDestReg).addMBB(overflowMBB);
20259 // Erase the pseudo instruction
20260 MI->eraseFromParent();
20265 MachineBasicBlock *
20266 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20268 MachineBasicBlock *MBB) const {
20269 // Emit code to save XMM registers to the stack. The ABI says that the
20270 // number of registers to save is given in %al, so it's theoretically
20271 // possible to do an indirect jump trick to avoid saving all of them,
20272 // however this code takes a simpler approach and just executes all
20273 // of the stores if %al is non-zero. It's less code, and it's probably
20274 // easier on the hardware branch predictor, and stores aren't all that
20275 // expensive anyway.
20277 // Create the new basic blocks. One block contains all the XMM stores,
20278 // and one block is the final destination regardless of whether any
20279 // stores were performed.
20280 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20281 MachineFunction *F = MBB->getParent();
20282 MachineFunction::iterator MBBIter = MBB;
20284 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20285 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20286 F->insert(MBBIter, XMMSaveMBB);
20287 F->insert(MBBIter, EndMBB);
20289 // Transfer the remainder of MBB and its successor edges to EndMBB.
20290 EndMBB->splice(EndMBB->begin(), MBB,
20291 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20292 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20294 // The original block will now fall through to the XMM save block.
20295 MBB->addSuccessor(XMMSaveMBB);
20296 // The XMMSaveMBB will fall through to the end block.
20297 XMMSaveMBB->addSuccessor(EndMBB);
20299 // Now add the instructions.
20300 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20301 DebugLoc DL = MI->getDebugLoc();
20303 unsigned CountReg = MI->getOperand(0).getReg();
20304 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20305 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20307 if (!Subtarget->isTargetWin64()) {
20308 // If %al is 0, branch around the XMM save block.
20309 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20310 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20311 MBB->addSuccessor(EndMBB);
20314 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20315 // that was just emitted, but clearly shouldn't be "saved".
20316 assert((MI->getNumOperands() <= 3 ||
20317 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20318 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20319 && "Expected last argument to be EFLAGS");
20320 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20321 // In the XMM save block, save all the XMM argument registers.
20322 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20323 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20324 MachineMemOperand *MMO =
20325 F->getMachineMemOperand(
20326 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20327 MachineMemOperand::MOStore,
20328 /*Size=*/16, /*Align=*/16);
20329 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20330 .addFrameIndex(RegSaveFrameIndex)
20331 .addImm(/*Scale=*/1)
20332 .addReg(/*IndexReg=*/0)
20333 .addImm(/*Disp=*/Offset)
20334 .addReg(/*Segment=*/0)
20335 .addReg(MI->getOperand(i).getReg())
20336 .addMemOperand(MMO);
20339 MI->eraseFromParent(); // The pseudo instruction is gone now.
20344 // The EFLAGS operand of SelectItr might be missing a kill marker
20345 // because there were multiple uses of EFLAGS, and ISel didn't know
20346 // which to mark. Figure out whether SelectItr should have had a
20347 // kill marker, and set it if it should. Returns the correct kill
20349 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20350 MachineBasicBlock* BB,
20351 const TargetRegisterInfo* TRI) {
20352 // Scan forward through BB for a use/def of EFLAGS.
20353 MachineBasicBlock::iterator miI(std::next(SelectItr));
20354 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20355 const MachineInstr& mi = *miI;
20356 if (mi.readsRegister(X86::EFLAGS))
20358 if (mi.definesRegister(X86::EFLAGS))
20359 break; // Should have kill-flag - update below.
20362 // If we hit the end of the block, check whether EFLAGS is live into a
20364 if (miI == BB->end()) {
20365 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20366 sEnd = BB->succ_end();
20367 sItr != sEnd; ++sItr) {
20368 MachineBasicBlock* succ = *sItr;
20369 if (succ->isLiveIn(X86::EFLAGS))
20374 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20375 // out. SelectMI should have a kill flag on EFLAGS.
20376 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20380 MachineBasicBlock *
20381 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20382 MachineBasicBlock *BB) const {
20383 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20384 DebugLoc DL = MI->getDebugLoc();
20386 // To "insert" a SELECT_CC instruction, we actually have to insert the
20387 // diamond control-flow pattern. The incoming instruction knows the
20388 // destination vreg to set, the condition code register to branch on, the
20389 // true/false values to select between, and a branch opcode to use.
20390 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20391 MachineFunction::iterator It = BB;
20397 // cmpTY ccX, r1, r2
20399 // fallthrough --> copy0MBB
20400 MachineBasicBlock *thisMBB = BB;
20401 MachineFunction *F = BB->getParent();
20402 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20403 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20404 F->insert(It, copy0MBB);
20405 F->insert(It, sinkMBB);
20407 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20408 // live into the sink and copy blocks.
20409 const TargetRegisterInfo *TRI =
20410 BB->getParent()->getSubtarget().getRegisterInfo();
20411 if (!MI->killsRegister(X86::EFLAGS) &&
20412 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20413 copy0MBB->addLiveIn(X86::EFLAGS);
20414 sinkMBB->addLiveIn(X86::EFLAGS);
20417 // Transfer the remainder of BB and its successor edges to sinkMBB.
20418 sinkMBB->splice(sinkMBB->begin(), BB,
20419 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20420 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20422 // Add the true and fallthrough blocks as its successors.
20423 BB->addSuccessor(copy0MBB);
20424 BB->addSuccessor(sinkMBB);
20426 // Create the conditional branch instruction.
20428 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20429 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20432 // %FalseValue = ...
20433 // # fallthrough to sinkMBB
20434 copy0MBB->addSuccessor(sinkMBB);
20437 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20439 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20440 TII->get(X86::PHI), MI->getOperand(0).getReg())
20441 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20442 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20444 MI->eraseFromParent(); // The pseudo instruction is gone now.
20448 MachineBasicBlock *
20449 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20450 MachineBasicBlock *BB) const {
20451 MachineFunction *MF = BB->getParent();
20452 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20453 DebugLoc DL = MI->getDebugLoc();
20454 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20456 assert(MF->shouldSplitStack());
20458 const bool Is64Bit = Subtarget->is64Bit();
20459 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20461 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20462 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20465 // ... [Till the alloca]
20466 // If stacklet is not large enough, jump to mallocMBB
20469 // Allocate by subtracting from RSP
20470 // Jump to continueMBB
20473 // Allocate by call to runtime
20477 // [rest of original BB]
20480 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20481 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20482 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20484 MachineRegisterInfo &MRI = MF->getRegInfo();
20485 const TargetRegisterClass *AddrRegClass =
20486 getRegClassFor(getPointerTy());
20488 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20489 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20490 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20491 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20492 sizeVReg = MI->getOperand(1).getReg(),
20493 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20495 MachineFunction::iterator MBBIter = BB;
20498 MF->insert(MBBIter, bumpMBB);
20499 MF->insert(MBBIter, mallocMBB);
20500 MF->insert(MBBIter, continueMBB);
20502 continueMBB->splice(continueMBB->begin(), BB,
20503 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20504 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20506 // Add code to the main basic block to check if the stack limit has been hit,
20507 // and if so, jump to mallocMBB otherwise to bumpMBB.
20508 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20509 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20510 .addReg(tmpSPVReg).addReg(sizeVReg);
20511 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20512 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20513 .addReg(SPLimitVReg);
20514 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20516 // bumpMBB simply decreases the stack pointer, since we know the current
20517 // stacklet has enough space.
20518 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20519 .addReg(SPLimitVReg);
20520 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20521 .addReg(SPLimitVReg);
20522 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20524 // Calls into a routine in libgcc to allocate more space from the heap.
20525 const uint32_t *RegMask = MF->getTarget()
20526 .getSubtargetImpl()
20527 ->getRegisterInfo()
20528 ->getCallPreservedMask(CallingConv::C);
20530 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20532 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20533 .addExternalSymbol("__morestack_allocate_stack_space")
20534 .addRegMask(RegMask)
20535 .addReg(X86::RDI, RegState::Implicit)
20536 .addReg(X86::RAX, RegState::ImplicitDefine);
20537 } else if (Is64Bit) {
20538 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20540 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20541 .addExternalSymbol("__morestack_allocate_stack_space")
20542 .addRegMask(RegMask)
20543 .addReg(X86::EDI, RegState::Implicit)
20544 .addReg(X86::EAX, RegState::ImplicitDefine);
20546 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20548 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20549 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20550 .addExternalSymbol("__morestack_allocate_stack_space")
20551 .addRegMask(RegMask)
20552 .addReg(X86::EAX, RegState::ImplicitDefine);
20556 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20559 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20560 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20561 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20563 // Set up the CFG correctly.
20564 BB->addSuccessor(bumpMBB);
20565 BB->addSuccessor(mallocMBB);
20566 mallocMBB->addSuccessor(continueMBB);
20567 bumpMBB->addSuccessor(continueMBB);
20569 // Take care of the PHI nodes.
20570 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20571 MI->getOperand(0).getReg())
20572 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20573 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20575 // Delete the original pseudo instruction.
20576 MI->eraseFromParent();
20579 return continueMBB;
20582 MachineBasicBlock *
20583 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20584 MachineBasicBlock *BB) const {
20585 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20586 DebugLoc DL = MI->getDebugLoc();
20588 assert(!Subtarget->isTargetMacho());
20590 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20591 // non-trivial part is impdef of ESP.
20593 if (Subtarget->isTargetWin64()) {
20594 if (Subtarget->isTargetCygMing()) {
20595 // ___chkstk(Mingw64):
20596 // Clobbers R10, R11, RAX and EFLAGS.
20598 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20599 .addExternalSymbol("___chkstk")
20600 .addReg(X86::RAX, RegState::Implicit)
20601 .addReg(X86::RSP, RegState::Implicit)
20602 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20603 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20604 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20606 // __chkstk(MSVCRT): does not update stack pointer.
20607 // Clobbers R10, R11 and EFLAGS.
20608 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20609 .addExternalSymbol("__chkstk")
20610 .addReg(X86::RAX, RegState::Implicit)
20611 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20612 // RAX has the offset to be subtracted from RSP.
20613 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20618 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20619 Subtarget->isTargetWindowsItanium())
20623 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20624 .addExternalSymbol(StackProbeSymbol)
20625 .addReg(X86::EAX, RegState::Implicit)
20626 .addReg(X86::ESP, RegState::Implicit)
20627 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20628 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20629 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20632 MI->eraseFromParent(); // The pseudo instruction is gone now.
20636 MachineBasicBlock *
20637 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20638 MachineBasicBlock *BB) const {
20639 // This is pretty easy. We're taking the value that we received from
20640 // our load from the relocation, sticking it in either RDI (x86-64)
20641 // or EAX and doing an indirect call. The return value will then
20642 // be in the normal return register.
20643 MachineFunction *F = BB->getParent();
20644 const X86InstrInfo *TII =
20645 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20646 DebugLoc DL = MI->getDebugLoc();
20648 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20649 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20651 // Get a register mask for the lowered call.
20652 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20653 // proper register mask.
20654 const uint32_t *RegMask = F->getTarget()
20655 .getSubtargetImpl()
20656 ->getRegisterInfo()
20657 ->getCallPreservedMask(CallingConv::C);
20658 if (Subtarget->is64Bit()) {
20659 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20660 TII->get(X86::MOV64rm), X86::RDI)
20662 .addImm(0).addReg(0)
20663 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20664 MI->getOperand(3).getTargetFlags())
20666 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20667 addDirectMem(MIB, X86::RDI);
20668 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20669 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20670 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20671 TII->get(X86::MOV32rm), X86::EAX)
20673 .addImm(0).addReg(0)
20674 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20675 MI->getOperand(3).getTargetFlags())
20677 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20678 addDirectMem(MIB, X86::EAX);
20679 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20681 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20682 TII->get(X86::MOV32rm), X86::EAX)
20683 .addReg(TII->getGlobalBaseReg(F))
20684 .addImm(0).addReg(0)
20685 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20686 MI->getOperand(3).getTargetFlags())
20688 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20689 addDirectMem(MIB, X86::EAX);
20690 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20693 MI->eraseFromParent(); // The pseudo instruction is gone now.
20697 MachineBasicBlock *
20698 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20699 MachineBasicBlock *MBB) const {
20700 DebugLoc DL = MI->getDebugLoc();
20701 MachineFunction *MF = MBB->getParent();
20702 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20703 MachineRegisterInfo &MRI = MF->getRegInfo();
20705 const BasicBlock *BB = MBB->getBasicBlock();
20706 MachineFunction::iterator I = MBB;
20709 // Memory Reference
20710 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20711 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20714 unsigned MemOpndSlot = 0;
20716 unsigned CurOp = 0;
20718 DstReg = MI->getOperand(CurOp++).getReg();
20719 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20720 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20721 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20722 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20724 MemOpndSlot = CurOp;
20726 MVT PVT = getPointerTy();
20727 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20728 "Invalid Pointer Size!");
20730 // For v = setjmp(buf), we generate
20733 // buf[LabelOffset] = restoreMBB
20734 // SjLjSetup restoreMBB
20740 // v = phi(main, restore)
20745 MachineBasicBlock *thisMBB = MBB;
20746 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20747 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20748 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20749 MF->insert(I, mainMBB);
20750 MF->insert(I, sinkMBB);
20751 MF->push_back(restoreMBB);
20753 MachineInstrBuilder MIB;
20755 // Transfer the remainder of BB and its successor edges to sinkMBB.
20756 sinkMBB->splice(sinkMBB->begin(), MBB,
20757 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20758 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20761 unsigned PtrStoreOpc = 0;
20762 unsigned LabelReg = 0;
20763 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20764 Reloc::Model RM = MF->getTarget().getRelocationModel();
20765 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20766 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20768 // Prepare IP either in reg or imm.
20769 if (!UseImmLabel) {
20770 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20771 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20772 LabelReg = MRI.createVirtualRegister(PtrRC);
20773 if (Subtarget->is64Bit()) {
20774 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20778 .addMBB(restoreMBB)
20781 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20782 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20783 .addReg(XII->getGlobalBaseReg(MF))
20786 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20790 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20792 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20793 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20794 if (i == X86::AddrDisp)
20795 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20797 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20800 MIB.addReg(LabelReg);
20802 MIB.addMBB(restoreMBB);
20803 MIB.setMemRefs(MMOBegin, MMOEnd);
20805 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20806 .addMBB(restoreMBB);
20808 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20809 MF->getSubtarget().getRegisterInfo());
20810 MIB.addRegMask(RegInfo->getNoPreservedMask());
20811 thisMBB->addSuccessor(mainMBB);
20812 thisMBB->addSuccessor(restoreMBB);
20816 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20817 mainMBB->addSuccessor(sinkMBB);
20820 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20821 TII->get(X86::PHI), DstReg)
20822 .addReg(mainDstReg).addMBB(mainMBB)
20823 .addReg(restoreDstReg).addMBB(restoreMBB);
20826 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20827 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20828 restoreMBB->addSuccessor(sinkMBB);
20830 MI->eraseFromParent();
20834 MachineBasicBlock *
20835 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20836 MachineBasicBlock *MBB) const {
20837 DebugLoc DL = MI->getDebugLoc();
20838 MachineFunction *MF = MBB->getParent();
20839 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20840 MachineRegisterInfo &MRI = MF->getRegInfo();
20842 // Memory Reference
20843 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20844 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20846 MVT PVT = getPointerTy();
20847 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20848 "Invalid Pointer Size!");
20850 const TargetRegisterClass *RC =
20851 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20852 unsigned Tmp = MRI.createVirtualRegister(RC);
20853 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20854 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20855 MF->getSubtarget().getRegisterInfo());
20856 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20857 unsigned SP = RegInfo->getStackRegister();
20859 MachineInstrBuilder MIB;
20861 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20862 const int64_t SPOffset = 2 * PVT.getStoreSize();
20864 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20865 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20868 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20869 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20870 MIB.addOperand(MI->getOperand(i));
20871 MIB.setMemRefs(MMOBegin, MMOEnd);
20873 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20874 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20875 if (i == X86::AddrDisp)
20876 MIB.addDisp(MI->getOperand(i), LabelOffset);
20878 MIB.addOperand(MI->getOperand(i));
20880 MIB.setMemRefs(MMOBegin, MMOEnd);
20882 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20883 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20884 if (i == X86::AddrDisp)
20885 MIB.addDisp(MI->getOperand(i), SPOffset);
20887 MIB.addOperand(MI->getOperand(i));
20889 MIB.setMemRefs(MMOBegin, MMOEnd);
20891 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20893 MI->eraseFromParent();
20897 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20898 // accumulator loops. Writing back to the accumulator allows the coalescer
20899 // to remove extra copies in the loop.
20900 MachineBasicBlock *
20901 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20902 MachineBasicBlock *MBB) const {
20903 MachineOperand &AddendOp = MI->getOperand(3);
20905 // Bail out early if the addend isn't a register - we can't switch these.
20906 if (!AddendOp.isReg())
20909 MachineFunction &MF = *MBB->getParent();
20910 MachineRegisterInfo &MRI = MF.getRegInfo();
20912 // Check whether the addend is defined by a PHI:
20913 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20914 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20915 if (!AddendDef.isPHI())
20918 // Look for the following pattern:
20920 // %addend = phi [%entry, 0], [%loop, %result]
20922 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20926 // %addend = phi [%entry, 0], [%loop, %result]
20928 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20930 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20931 assert(AddendDef.getOperand(i).isReg());
20932 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20933 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20934 if (&PHISrcInst == MI) {
20935 // Found a matching instruction.
20936 unsigned NewFMAOpc = 0;
20937 switch (MI->getOpcode()) {
20938 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20939 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20940 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20941 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20942 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20943 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20944 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20945 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20946 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20947 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20948 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20949 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20950 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20951 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20952 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20953 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20954 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20955 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20956 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20957 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20959 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20960 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20961 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20962 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20963 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20964 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20965 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20966 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20967 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20968 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20969 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20970 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20971 default: llvm_unreachable("Unrecognized FMA variant.");
20974 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20975 MachineInstrBuilder MIB =
20976 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20977 .addOperand(MI->getOperand(0))
20978 .addOperand(MI->getOperand(3))
20979 .addOperand(MI->getOperand(2))
20980 .addOperand(MI->getOperand(1));
20981 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20982 MI->eraseFromParent();
20989 MachineBasicBlock *
20990 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20991 MachineBasicBlock *BB) const {
20992 switch (MI->getOpcode()) {
20993 default: llvm_unreachable("Unexpected instr type to insert");
20994 case X86::TAILJMPd64:
20995 case X86::TAILJMPr64:
20996 case X86::TAILJMPm64:
20997 llvm_unreachable("TAILJMP64 would not be touched here.");
20998 case X86::TCRETURNdi64:
20999 case X86::TCRETURNri64:
21000 case X86::TCRETURNmi64:
21002 case X86::WIN_ALLOCA:
21003 return EmitLoweredWinAlloca(MI, BB);
21004 case X86::SEG_ALLOCA_32:
21005 case X86::SEG_ALLOCA_64:
21006 return EmitLoweredSegAlloca(MI, BB);
21007 case X86::TLSCall_32:
21008 case X86::TLSCall_64:
21009 return EmitLoweredTLSCall(MI, BB);
21010 case X86::CMOV_GR8:
21011 case X86::CMOV_FR32:
21012 case X86::CMOV_FR64:
21013 case X86::CMOV_V4F32:
21014 case X86::CMOV_V2F64:
21015 case X86::CMOV_V2I64:
21016 case X86::CMOV_V8F32:
21017 case X86::CMOV_V4F64:
21018 case X86::CMOV_V4I64:
21019 case X86::CMOV_V16F32:
21020 case X86::CMOV_V8F64:
21021 case X86::CMOV_V8I64:
21022 case X86::CMOV_GR16:
21023 case X86::CMOV_GR32:
21024 case X86::CMOV_RFP32:
21025 case X86::CMOV_RFP64:
21026 case X86::CMOV_RFP80:
21027 return EmitLoweredSelect(MI, BB);
21029 case X86::FP32_TO_INT16_IN_MEM:
21030 case X86::FP32_TO_INT32_IN_MEM:
21031 case X86::FP32_TO_INT64_IN_MEM:
21032 case X86::FP64_TO_INT16_IN_MEM:
21033 case X86::FP64_TO_INT32_IN_MEM:
21034 case X86::FP64_TO_INT64_IN_MEM:
21035 case X86::FP80_TO_INT16_IN_MEM:
21036 case X86::FP80_TO_INT32_IN_MEM:
21037 case X86::FP80_TO_INT64_IN_MEM: {
21038 MachineFunction *F = BB->getParent();
21039 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21040 DebugLoc DL = MI->getDebugLoc();
21042 // Change the floating point control register to use "round towards zero"
21043 // mode when truncating to an integer value.
21044 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21045 addFrameReference(BuildMI(*BB, MI, DL,
21046 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21048 // Load the old value of the high byte of the control word...
21050 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21051 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21054 // Set the high part to be round to zero...
21055 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21058 // Reload the modified control word now...
21059 addFrameReference(BuildMI(*BB, MI, DL,
21060 TII->get(X86::FLDCW16m)), CWFrameIdx);
21062 // Restore the memory image of control word to original value
21063 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21066 // Get the X86 opcode to use.
21068 switch (MI->getOpcode()) {
21069 default: llvm_unreachable("illegal opcode!");
21070 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21071 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21072 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21073 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21074 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21075 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21076 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21077 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21078 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21082 MachineOperand &Op = MI->getOperand(0);
21084 AM.BaseType = X86AddressMode::RegBase;
21085 AM.Base.Reg = Op.getReg();
21087 AM.BaseType = X86AddressMode::FrameIndexBase;
21088 AM.Base.FrameIndex = Op.getIndex();
21090 Op = MI->getOperand(1);
21092 AM.Scale = Op.getImm();
21093 Op = MI->getOperand(2);
21095 AM.IndexReg = Op.getImm();
21096 Op = MI->getOperand(3);
21097 if (Op.isGlobal()) {
21098 AM.GV = Op.getGlobal();
21100 AM.Disp = Op.getImm();
21102 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21103 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21105 // Reload the original control word now.
21106 addFrameReference(BuildMI(*BB, MI, DL,
21107 TII->get(X86::FLDCW16m)), CWFrameIdx);
21109 MI->eraseFromParent(); // The pseudo instruction is gone now.
21112 // String/text processing lowering.
21113 case X86::PCMPISTRM128REG:
21114 case X86::VPCMPISTRM128REG:
21115 case X86::PCMPISTRM128MEM:
21116 case X86::VPCMPISTRM128MEM:
21117 case X86::PCMPESTRM128REG:
21118 case X86::VPCMPESTRM128REG:
21119 case X86::PCMPESTRM128MEM:
21120 case X86::VPCMPESTRM128MEM:
21121 assert(Subtarget->hasSSE42() &&
21122 "Target must have SSE4.2 or AVX features enabled");
21123 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21125 // String/text processing lowering.
21126 case X86::PCMPISTRIREG:
21127 case X86::VPCMPISTRIREG:
21128 case X86::PCMPISTRIMEM:
21129 case X86::VPCMPISTRIMEM:
21130 case X86::PCMPESTRIREG:
21131 case X86::VPCMPESTRIREG:
21132 case X86::PCMPESTRIMEM:
21133 case X86::VPCMPESTRIMEM:
21134 assert(Subtarget->hasSSE42() &&
21135 "Target must have SSE4.2 or AVX features enabled");
21136 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21138 // Thread synchronization.
21140 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21145 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21147 case X86::VASTART_SAVE_XMM_REGS:
21148 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21150 case X86::VAARG_64:
21151 return EmitVAARG64WithCustomInserter(MI, BB);
21153 case X86::EH_SjLj_SetJmp32:
21154 case X86::EH_SjLj_SetJmp64:
21155 return emitEHSjLjSetJmp(MI, BB);
21157 case X86::EH_SjLj_LongJmp32:
21158 case X86::EH_SjLj_LongJmp64:
21159 return emitEHSjLjLongJmp(MI, BB);
21161 case TargetOpcode::STACKMAP:
21162 case TargetOpcode::PATCHPOINT:
21163 return emitPatchPoint(MI, BB);
21165 case X86::VFMADDPDr213r:
21166 case X86::VFMADDPSr213r:
21167 case X86::VFMADDSDr213r:
21168 case X86::VFMADDSSr213r:
21169 case X86::VFMSUBPDr213r:
21170 case X86::VFMSUBPSr213r:
21171 case X86::VFMSUBSDr213r:
21172 case X86::VFMSUBSSr213r:
21173 case X86::VFNMADDPDr213r:
21174 case X86::VFNMADDPSr213r:
21175 case X86::VFNMADDSDr213r:
21176 case X86::VFNMADDSSr213r:
21177 case X86::VFNMSUBPDr213r:
21178 case X86::VFNMSUBPSr213r:
21179 case X86::VFNMSUBSDr213r:
21180 case X86::VFNMSUBSSr213r:
21181 case X86::VFMADDSUBPDr213r:
21182 case X86::VFMADDSUBPSr213r:
21183 case X86::VFMSUBADDPDr213r:
21184 case X86::VFMSUBADDPSr213r:
21185 case X86::VFMADDPDr213rY:
21186 case X86::VFMADDPSr213rY:
21187 case X86::VFMSUBPDr213rY:
21188 case X86::VFMSUBPSr213rY:
21189 case X86::VFNMADDPDr213rY:
21190 case X86::VFNMADDPSr213rY:
21191 case X86::VFNMSUBPDr213rY:
21192 case X86::VFNMSUBPSr213rY:
21193 case X86::VFMADDSUBPDr213rY:
21194 case X86::VFMADDSUBPSr213rY:
21195 case X86::VFMSUBADDPDr213rY:
21196 case X86::VFMSUBADDPSr213rY:
21197 return emitFMA3Instr(MI, BB);
21201 //===----------------------------------------------------------------------===//
21202 // X86 Optimization Hooks
21203 //===----------------------------------------------------------------------===//
21205 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21208 const SelectionDAG &DAG,
21209 unsigned Depth) const {
21210 unsigned BitWidth = KnownZero.getBitWidth();
21211 unsigned Opc = Op.getOpcode();
21212 assert((Opc >= ISD::BUILTIN_OP_END ||
21213 Opc == ISD::INTRINSIC_WO_CHAIN ||
21214 Opc == ISD::INTRINSIC_W_CHAIN ||
21215 Opc == ISD::INTRINSIC_VOID) &&
21216 "Should use MaskedValueIsZero if you don't know whether Op"
21217 " is a target node!");
21219 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21233 // These nodes' second result is a boolean.
21234 if (Op.getResNo() == 0)
21237 case X86ISD::SETCC:
21238 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21240 case ISD::INTRINSIC_WO_CHAIN: {
21241 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21242 unsigned NumLoBits = 0;
21245 case Intrinsic::x86_sse_movmsk_ps:
21246 case Intrinsic::x86_avx_movmsk_ps_256:
21247 case Intrinsic::x86_sse2_movmsk_pd:
21248 case Intrinsic::x86_avx_movmsk_pd_256:
21249 case Intrinsic::x86_mmx_pmovmskb:
21250 case Intrinsic::x86_sse2_pmovmskb_128:
21251 case Intrinsic::x86_avx2_pmovmskb: {
21252 // High bits of movmskp{s|d}, pmovmskb are known zero.
21254 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21255 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21256 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21257 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21258 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21259 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21260 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21261 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21263 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21272 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21274 const SelectionDAG &,
21275 unsigned Depth) const {
21276 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21277 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21278 return Op.getValueType().getScalarType().getSizeInBits();
21284 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21285 /// node is a GlobalAddress + offset.
21286 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21287 const GlobalValue* &GA,
21288 int64_t &Offset) const {
21289 if (N->getOpcode() == X86ISD::Wrapper) {
21290 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21291 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21292 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21296 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21299 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21300 /// same as extracting the high 128-bit part of 256-bit vector and then
21301 /// inserting the result into the low part of a new 256-bit vector
21302 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21303 EVT VT = SVOp->getValueType(0);
21304 unsigned NumElems = VT.getVectorNumElements();
21306 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21307 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21308 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21309 SVOp->getMaskElt(j) >= 0)
21315 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21316 /// same as extracting the low 128-bit part of 256-bit vector and then
21317 /// inserting the result into the high part of a new 256-bit vector
21318 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21319 EVT VT = SVOp->getValueType(0);
21320 unsigned NumElems = VT.getVectorNumElements();
21322 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21323 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21324 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21325 SVOp->getMaskElt(j) >= 0)
21331 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21332 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21333 TargetLowering::DAGCombinerInfo &DCI,
21334 const X86Subtarget* Subtarget) {
21336 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21337 SDValue V1 = SVOp->getOperand(0);
21338 SDValue V2 = SVOp->getOperand(1);
21339 EVT VT = SVOp->getValueType(0);
21340 unsigned NumElems = VT.getVectorNumElements();
21342 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21343 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21347 // V UNDEF BUILD_VECTOR UNDEF
21349 // CONCAT_VECTOR CONCAT_VECTOR
21352 // RESULT: V + zero extended
21354 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21355 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21356 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21359 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21362 // To match the shuffle mask, the first half of the mask should
21363 // be exactly the first vector, and all the rest a splat with the
21364 // first element of the second one.
21365 for (unsigned i = 0; i != NumElems/2; ++i)
21366 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21367 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21370 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21371 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21372 if (Ld->hasNUsesOfValue(1, 0)) {
21373 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21374 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21376 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21378 Ld->getPointerInfo(),
21379 Ld->getAlignment(),
21380 false/*isVolatile*/, true/*ReadMem*/,
21381 false/*WriteMem*/);
21383 // Make sure the newly-created LOAD is in the same position as Ld in
21384 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21385 // and update uses of Ld's output chain to use the TokenFactor.
21386 if (Ld->hasAnyUseOfValue(1)) {
21387 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21388 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21389 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21390 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21391 SDValue(ResNode.getNode(), 1));
21394 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21398 // Emit a zeroed vector and insert the desired subvector on its
21400 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21401 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21402 return DCI.CombineTo(N, InsV);
21405 //===--------------------------------------------------------------------===//
21406 // Combine some shuffles into subvector extracts and inserts:
21409 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21410 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21411 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21412 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21413 return DCI.CombineTo(N, InsV);
21416 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21417 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21418 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21419 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21420 return DCI.CombineTo(N, InsV);
21426 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21429 /// This is the leaf of the recursive combinine below. When we have found some
21430 /// chain of single-use x86 shuffle instructions and accumulated the combined
21431 /// shuffle mask represented by them, this will try to pattern match that mask
21432 /// into either a single instruction if there is a special purpose instruction
21433 /// for this operation, or into a PSHUFB instruction which is a fully general
21434 /// instruction but should only be used to replace chains over a certain depth.
21435 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21436 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21437 TargetLowering::DAGCombinerInfo &DCI,
21438 const X86Subtarget *Subtarget) {
21439 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21441 // Find the operand that enters the chain. Note that multiple uses are OK
21442 // here, we're not going to remove the operand we find.
21443 SDValue Input = Op.getOperand(0);
21444 while (Input.getOpcode() == ISD::BITCAST)
21445 Input = Input.getOperand(0);
21447 MVT VT = Input.getSimpleValueType();
21448 MVT RootVT = Root.getSimpleValueType();
21451 // Just remove no-op shuffle masks.
21452 if (Mask.size() == 1) {
21453 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21458 // Use the float domain if the operand type is a floating point type.
21459 bool FloatDomain = VT.isFloatingPoint();
21461 // For floating point shuffles, we don't have free copies in the shuffle
21462 // instructions or the ability to load as part of the instruction, so
21463 // canonicalize their shuffles to UNPCK or MOV variants.
21465 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21466 // vectors because it can have a load folded into it that UNPCK cannot. This
21467 // doesn't preclude something switching to the shorter encoding post-RA.
21469 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21470 bool Lo = Mask.equals(0, 0);
21473 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21474 // is no slower than UNPCKLPD but has the option to fold the input operand
21475 // into even an unaligned memory load.
21476 if (Lo && Subtarget->hasSSE3()) {
21477 Shuffle = X86ISD::MOVDDUP;
21478 ShuffleVT = MVT::v2f64;
21480 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21481 // than the UNPCK variants.
21482 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21483 ShuffleVT = MVT::v4f32;
21485 if (Depth == 1 && Root->getOpcode() == Shuffle)
21486 return false; // Nothing to do!
21487 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21488 DCI.AddToWorklist(Op.getNode());
21489 if (Shuffle == X86ISD::MOVDDUP)
21490 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21492 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21493 DCI.AddToWorklist(Op.getNode());
21494 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21498 if (Subtarget->hasSSE3() &&
21499 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21500 bool Lo = Mask.equals(0, 0, 2, 2);
21501 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21502 MVT ShuffleVT = MVT::v4f32;
21503 if (Depth == 1 && Root->getOpcode() == Shuffle)
21504 return false; // Nothing to do!
21505 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21506 DCI.AddToWorklist(Op.getNode());
21507 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21508 DCI.AddToWorklist(Op.getNode());
21509 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21513 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21514 bool Lo = Mask.equals(0, 0, 1, 1);
21515 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21516 MVT ShuffleVT = MVT::v4f32;
21517 if (Depth == 1 && Root->getOpcode() == Shuffle)
21518 return false; // Nothing to do!
21519 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21520 DCI.AddToWorklist(Op.getNode());
21521 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21522 DCI.AddToWorklist(Op.getNode());
21523 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21529 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21530 // variants as none of these have single-instruction variants that are
21531 // superior to the UNPCK formulation.
21532 if (!FloatDomain &&
21533 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21534 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21535 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21536 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21538 bool Lo = Mask[0] == 0;
21539 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21540 if (Depth == 1 && Root->getOpcode() == Shuffle)
21541 return false; // Nothing to do!
21543 switch (Mask.size()) {
21545 ShuffleVT = MVT::v8i16;
21548 ShuffleVT = MVT::v16i8;
21551 llvm_unreachable("Impossible mask size!");
21553 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21554 DCI.AddToWorklist(Op.getNode());
21555 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21556 DCI.AddToWorklist(Op.getNode());
21557 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21562 // Don't try to re-form single instruction chains under any circumstances now
21563 // that we've done encoding canonicalization for them.
21567 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21568 // can replace them with a single PSHUFB instruction profitably. Intel's
21569 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21570 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21571 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21572 SmallVector<SDValue, 16> PSHUFBMask;
21573 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21574 int Ratio = 16 / Mask.size();
21575 for (unsigned i = 0; i < 16; ++i) {
21576 if (Mask[i / Ratio] == SM_SentinelUndef) {
21577 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21580 int M = Mask[i / Ratio] != SM_SentinelZero
21581 ? Ratio * Mask[i / Ratio] + i % Ratio
21583 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21585 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21586 DCI.AddToWorklist(Op.getNode());
21587 SDValue PSHUFBMaskOp =
21588 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21589 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21590 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21591 DCI.AddToWorklist(Op.getNode());
21592 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21597 // Failed to find any combines.
21601 /// \brief Fully generic combining of x86 shuffle instructions.
21603 /// This should be the last combine run over the x86 shuffle instructions. Once
21604 /// they have been fully optimized, this will recursively consider all chains
21605 /// of single-use shuffle instructions, build a generic model of the cumulative
21606 /// shuffle operation, and check for simpler instructions which implement this
21607 /// operation. We use this primarily for two purposes:
21609 /// 1) Collapse generic shuffles to specialized single instructions when
21610 /// equivalent. In most cases, this is just an encoding size win, but
21611 /// sometimes we will collapse multiple generic shuffles into a single
21612 /// special-purpose shuffle.
21613 /// 2) Look for sequences of shuffle instructions with 3 or more total
21614 /// instructions, and replace them with the slightly more expensive SSSE3
21615 /// PSHUFB instruction if available. We do this as the last combining step
21616 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21617 /// a suitable short sequence of other instructions. The PHUFB will either
21618 /// use a register or have to read from memory and so is slightly (but only
21619 /// slightly) more expensive than the other shuffle instructions.
21621 /// Because this is inherently a quadratic operation (for each shuffle in
21622 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21623 /// This should never be an issue in practice as the shuffle lowering doesn't
21624 /// produce sequences of more than 8 instructions.
21626 /// FIXME: We will currently miss some cases where the redundant shuffling
21627 /// would simplify under the threshold for PSHUFB formation because of
21628 /// combine-ordering. To fix this, we should do the redundant instruction
21629 /// combining in this recursive walk.
21630 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21631 ArrayRef<int> RootMask,
21632 int Depth, bool HasPSHUFB,
21634 TargetLowering::DAGCombinerInfo &DCI,
21635 const X86Subtarget *Subtarget) {
21636 // Bound the depth of our recursive combine because this is ultimately
21637 // quadratic in nature.
21641 // Directly rip through bitcasts to find the underlying operand.
21642 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21643 Op = Op.getOperand(0);
21645 MVT VT = Op.getSimpleValueType();
21646 if (!VT.isVector())
21647 return false; // Bail if we hit a non-vector.
21648 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21649 // version should be added.
21650 if (VT.getSizeInBits() != 128)
21653 assert(Root.getSimpleValueType().isVector() &&
21654 "Shuffles operate on vector types!");
21655 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21656 "Can only combine shuffles of the same vector register size.");
21658 if (!isTargetShuffle(Op.getOpcode()))
21660 SmallVector<int, 16> OpMask;
21662 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21663 // We only can combine unary shuffles which we can decode the mask for.
21664 if (!HaveMask || !IsUnary)
21667 assert(VT.getVectorNumElements() == OpMask.size() &&
21668 "Different mask size from vector size!");
21669 assert(((RootMask.size() > OpMask.size() &&
21670 RootMask.size() % OpMask.size() == 0) ||
21671 (OpMask.size() > RootMask.size() &&
21672 OpMask.size() % RootMask.size() == 0) ||
21673 OpMask.size() == RootMask.size()) &&
21674 "The smaller number of elements must divide the larger.");
21675 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21676 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21677 assert(((RootRatio == 1 && OpRatio == 1) ||
21678 (RootRatio == 1) != (OpRatio == 1)) &&
21679 "Must not have a ratio for both incoming and op masks!");
21681 SmallVector<int, 16> Mask;
21682 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21684 // Merge this shuffle operation's mask into our accumulated mask. Note that
21685 // this shuffle's mask will be the first applied to the input, followed by the
21686 // root mask to get us all the way to the root value arrangement. The reason
21687 // for this order is that we are recursing up the operation chain.
21688 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21689 int RootIdx = i / RootRatio;
21690 if (RootMask[RootIdx] < 0) {
21691 // This is a zero or undef lane, we're done.
21692 Mask.push_back(RootMask[RootIdx]);
21696 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21697 int OpIdx = RootMaskedIdx / OpRatio;
21698 if (OpMask[OpIdx] < 0) {
21699 // The incoming lanes are zero or undef, it doesn't matter which ones we
21701 Mask.push_back(OpMask[OpIdx]);
21705 // Ok, we have non-zero lanes, map them through.
21706 Mask.push_back(OpMask[OpIdx] * OpRatio +
21707 RootMaskedIdx % OpRatio);
21710 // See if we can recurse into the operand to combine more things.
21711 switch (Op.getOpcode()) {
21712 case X86ISD::PSHUFB:
21714 case X86ISD::PSHUFD:
21715 case X86ISD::PSHUFHW:
21716 case X86ISD::PSHUFLW:
21717 if (Op.getOperand(0).hasOneUse() &&
21718 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21719 HasPSHUFB, DAG, DCI, Subtarget))
21723 case X86ISD::UNPCKL:
21724 case X86ISD::UNPCKH:
21725 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21726 // We can't check for single use, we have to check that this shuffle is the only user.
21727 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21728 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21729 HasPSHUFB, DAG, DCI, Subtarget))
21734 // Minor canonicalization of the accumulated shuffle mask to make it easier
21735 // to match below. All this does is detect masks with squential pairs of
21736 // elements, and shrink them to the half-width mask. It does this in a loop
21737 // so it will reduce the size of the mask to the minimal width mask which
21738 // performs an equivalent shuffle.
21739 SmallVector<int, 16> WidenedMask;
21740 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21741 Mask = std::move(WidenedMask);
21742 WidenedMask.clear();
21745 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21749 /// \brief Get the PSHUF-style mask from PSHUF node.
21751 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21752 /// PSHUF-style masks that can be reused with such instructions.
21753 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21754 SmallVector<int, 4> Mask;
21756 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21760 switch (N.getOpcode()) {
21761 case X86ISD::PSHUFD:
21763 case X86ISD::PSHUFLW:
21766 case X86ISD::PSHUFHW:
21767 Mask.erase(Mask.begin(), Mask.begin() + 4);
21768 for (int &M : Mask)
21772 llvm_unreachable("No valid shuffle instruction found!");
21776 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21778 /// We walk up the chain and look for a combinable shuffle, skipping over
21779 /// shuffles that we could hoist this shuffle's transformation past without
21780 /// altering anything.
21782 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21784 TargetLowering::DAGCombinerInfo &DCI) {
21785 assert(N.getOpcode() == X86ISD::PSHUFD &&
21786 "Called with something other than an x86 128-bit half shuffle!");
21789 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21790 // of the shuffles in the chain so that we can form a fresh chain to replace
21792 SmallVector<SDValue, 8> Chain;
21793 SDValue V = N.getOperand(0);
21794 for (; V.hasOneUse(); V = V.getOperand(0)) {
21795 switch (V.getOpcode()) {
21797 return SDValue(); // Nothing combined!
21800 // Skip bitcasts as we always know the type for the target specific
21804 case X86ISD::PSHUFD:
21805 // Found another dword shuffle.
21808 case X86ISD::PSHUFLW:
21809 // Check that the low words (being shuffled) are the identity in the
21810 // dword shuffle, and the high words are self-contained.
21811 if (Mask[0] != 0 || Mask[1] != 1 ||
21812 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21815 Chain.push_back(V);
21818 case X86ISD::PSHUFHW:
21819 // Check that the high words (being shuffled) are the identity in the
21820 // dword shuffle, and the low words are self-contained.
21821 if (Mask[2] != 2 || Mask[3] != 3 ||
21822 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21825 Chain.push_back(V);
21828 case X86ISD::UNPCKL:
21829 case X86ISD::UNPCKH:
21830 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21831 // shuffle into a preceding word shuffle.
21832 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21835 // Search for a half-shuffle which we can combine with.
21836 unsigned CombineOp =
21837 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21838 if (V.getOperand(0) != V.getOperand(1) ||
21839 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21841 Chain.push_back(V);
21842 V = V.getOperand(0);
21844 switch (V.getOpcode()) {
21846 return SDValue(); // Nothing to combine.
21848 case X86ISD::PSHUFLW:
21849 case X86ISD::PSHUFHW:
21850 if (V.getOpcode() == CombineOp)
21853 Chain.push_back(V);
21857 V = V.getOperand(0);
21861 } while (V.hasOneUse());
21864 // Break out of the loop if we break out of the switch.
21868 if (!V.hasOneUse())
21869 // We fell out of the loop without finding a viable combining instruction.
21872 // Merge this node's mask and our incoming mask.
21873 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21874 for (int &M : Mask)
21876 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21877 getV4X86ShuffleImm8ForMask(Mask, DAG));
21879 // Rebuild the chain around this new shuffle.
21880 while (!Chain.empty()) {
21881 SDValue W = Chain.pop_back_val();
21883 if (V.getValueType() != W.getOperand(0).getValueType())
21884 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21886 switch (W.getOpcode()) {
21888 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21890 case X86ISD::UNPCKL:
21891 case X86ISD::UNPCKH:
21892 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21895 case X86ISD::PSHUFD:
21896 case X86ISD::PSHUFLW:
21897 case X86ISD::PSHUFHW:
21898 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21902 if (V.getValueType() != N.getValueType())
21903 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21905 // Return the new chain to replace N.
21909 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21911 /// We walk up the chain, skipping shuffles of the other half and looking
21912 /// through shuffles which switch halves trying to find a shuffle of the same
21913 /// pair of dwords.
21914 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21916 TargetLowering::DAGCombinerInfo &DCI) {
21918 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21919 "Called with something other than an x86 128-bit half shuffle!");
21921 unsigned CombineOpcode = N.getOpcode();
21923 // Walk up a single-use chain looking for a combinable shuffle.
21924 SDValue V = N.getOperand(0);
21925 for (; V.hasOneUse(); V = V.getOperand(0)) {
21926 switch (V.getOpcode()) {
21928 return false; // Nothing combined!
21931 // Skip bitcasts as we always know the type for the target specific
21935 case X86ISD::PSHUFLW:
21936 case X86ISD::PSHUFHW:
21937 if (V.getOpcode() == CombineOpcode)
21940 // Other-half shuffles are no-ops.
21943 // Break out of the loop if we break out of the switch.
21947 if (!V.hasOneUse())
21948 // We fell out of the loop without finding a viable combining instruction.
21951 // Combine away the bottom node as its shuffle will be accumulated into
21952 // a preceding shuffle.
21953 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21955 // Record the old value.
21958 // Merge this node's mask and our incoming mask (adjusted to account for all
21959 // the pshufd instructions encountered).
21960 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21961 for (int &M : Mask)
21963 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21964 getV4X86ShuffleImm8ForMask(Mask, DAG));
21966 // Check that the shuffles didn't cancel each other out. If not, we need to
21967 // combine to the new one.
21969 // Replace the combinable shuffle with the combined one, updating all users
21970 // so that we re-evaluate the chain here.
21971 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21976 /// \brief Try to combine x86 target specific shuffles.
21977 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21978 TargetLowering::DAGCombinerInfo &DCI,
21979 const X86Subtarget *Subtarget) {
21981 MVT VT = N.getSimpleValueType();
21982 SmallVector<int, 4> Mask;
21984 switch (N.getOpcode()) {
21985 case X86ISD::PSHUFD:
21986 case X86ISD::PSHUFLW:
21987 case X86ISD::PSHUFHW:
21988 Mask = getPSHUFShuffleMask(N);
21989 assert(Mask.size() == 4);
21995 // Nuke no-op shuffles that show up after combining.
21996 if (isNoopShuffleMask(Mask))
21997 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21999 // Look for simplifications involving one or two shuffle instructions.
22000 SDValue V = N.getOperand(0);
22001 switch (N.getOpcode()) {
22004 case X86ISD::PSHUFLW:
22005 case X86ISD::PSHUFHW:
22006 assert(VT == MVT::v8i16);
22009 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22010 return SDValue(); // We combined away this shuffle, so we're done.
22012 // See if this reduces to a PSHUFD which is no more expensive and can
22013 // combine with more operations. Note that it has to at least flip the
22014 // dwords as otherwise it would have been removed as a no-op.
22015 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22016 int DMask[] = {0, 1, 2, 3};
22017 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22018 DMask[DOffset + 0] = DOffset + 1;
22019 DMask[DOffset + 1] = DOffset + 0;
22020 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22021 DCI.AddToWorklist(V.getNode());
22022 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22023 getV4X86ShuffleImm8ForMask(DMask, DAG));
22024 DCI.AddToWorklist(V.getNode());
22025 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22028 // Look for shuffle patterns which can be implemented as a single unpack.
22029 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22030 // only works when we have a PSHUFD followed by two half-shuffles.
22031 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22032 (V.getOpcode() == X86ISD::PSHUFLW ||
22033 V.getOpcode() == X86ISD::PSHUFHW) &&
22034 V.getOpcode() != N.getOpcode() &&
22036 SDValue D = V.getOperand(0);
22037 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22038 D = D.getOperand(0);
22039 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22040 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22041 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22042 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22043 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22045 for (int i = 0; i < 4; ++i) {
22046 WordMask[i + NOffset] = Mask[i] + NOffset;
22047 WordMask[i + VOffset] = VMask[i] + VOffset;
22049 // Map the word mask through the DWord mask.
22051 for (int i = 0; i < 8; ++i)
22052 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22053 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22054 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22055 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22056 std::begin(UnpackLoMask)) ||
22057 std::equal(std::begin(MappedMask), std::end(MappedMask),
22058 std::begin(UnpackHiMask))) {
22059 // We can replace all three shuffles with an unpack.
22060 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22061 DCI.AddToWorklist(V.getNode());
22062 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22064 DL, MVT::v8i16, V, V);
22071 case X86ISD::PSHUFD:
22072 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22081 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22083 /// We combine this directly on the abstract vector shuffle nodes so it is
22084 /// easier to generically match. We also insert dummy vector shuffle nodes for
22085 /// the operands which explicitly discard the lanes which are unused by this
22086 /// operation to try to flow through the rest of the combiner the fact that
22087 /// they're unused.
22088 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22090 EVT VT = N->getValueType(0);
22092 // We only handle target-independent shuffles.
22093 // FIXME: It would be easy and harmless to use the target shuffle mask
22094 // extraction tool to support more.
22095 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22098 auto *SVN = cast<ShuffleVectorSDNode>(N);
22099 ArrayRef<int> Mask = SVN->getMask();
22100 SDValue V1 = N->getOperand(0);
22101 SDValue V2 = N->getOperand(1);
22103 // We require the first shuffle operand to be the SUB node, and the second to
22104 // be the ADD node.
22105 // FIXME: We should support the commuted patterns.
22106 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22109 // If there are other uses of these operations we can't fold them.
22110 if (!V1->hasOneUse() || !V2->hasOneUse())
22113 // Ensure that both operations have the same operands. Note that we can
22114 // commute the FADD operands.
22115 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22116 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22117 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22120 // We're looking for blends between FADD and FSUB nodes. We insist on these
22121 // nodes being lined up in a specific expected pattern.
22122 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22123 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22124 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22127 // Only specific types are legal at this point, assert so we notice if and
22128 // when these change.
22129 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22130 VT == MVT::v4f64) &&
22131 "Unknown vector type encountered!");
22133 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22136 /// PerformShuffleCombine - Performs several different shuffle combines.
22137 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22138 TargetLowering::DAGCombinerInfo &DCI,
22139 const X86Subtarget *Subtarget) {
22141 SDValue N0 = N->getOperand(0);
22142 SDValue N1 = N->getOperand(1);
22143 EVT VT = N->getValueType(0);
22145 // Don't create instructions with illegal types after legalize types has run.
22146 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22147 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22150 // If we have legalized the vector types, look for blends of FADD and FSUB
22151 // nodes that we can fuse into an ADDSUB node.
22152 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22153 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22156 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22157 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22158 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22159 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22161 // During Type Legalization, when promoting illegal vector types,
22162 // the backend might introduce new shuffle dag nodes and bitcasts.
22164 // This code performs the following transformation:
22165 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22166 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22168 // We do this only if both the bitcast and the BINOP dag nodes have
22169 // one use. Also, perform this transformation only if the new binary
22170 // operation is legal. This is to avoid introducing dag nodes that
22171 // potentially need to be further expanded (or custom lowered) into a
22172 // less optimal sequence of dag nodes.
22173 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22174 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22175 N0.getOpcode() == ISD::BITCAST) {
22176 SDValue BC0 = N0.getOperand(0);
22177 EVT SVT = BC0.getValueType();
22178 unsigned Opcode = BC0.getOpcode();
22179 unsigned NumElts = VT.getVectorNumElements();
22181 if (BC0.hasOneUse() && SVT.isVector() &&
22182 SVT.getVectorNumElements() * 2 == NumElts &&
22183 TLI.isOperationLegal(Opcode, VT)) {
22184 bool CanFold = false;
22196 unsigned SVTNumElts = SVT.getVectorNumElements();
22197 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22198 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22199 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22200 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22201 CanFold = SVOp->getMaskElt(i) < 0;
22204 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22205 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22206 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22207 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22212 // Only handle 128 wide vector from here on.
22213 if (!VT.is128BitVector())
22216 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22217 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22218 // consecutive, non-overlapping, and in the right order.
22219 SmallVector<SDValue, 16> Elts;
22220 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22221 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22223 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22227 if (isTargetShuffle(N->getOpcode())) {
22229 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22230 if (Shuffle.getNode())
22233 // Try recursively combining arbitrary sequences of x86 shuffle
22234 // instructions into higher-order shuffles. We do this after combining
22235 // specific PSHUF instruction sequences into their minimal form so that we
22236 // can evaluate how many specialized shuffle instructions are involved in
22237 // a particular chain.
22238 SmallVector<int, 1> NonceMask; // Just a placeholder.
22239 NonceMask.push_back(0);
22240 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22241 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22243 return SDValue(); // This routine will use CombineTo to replace N.
22249 /// PerformTruncateCombine - Converts truncate operation to
22250 /// a sequence of vector shuffle operations.
22251 /// It is possible when we truncate 256-bit vector to 128-bit vector
22252 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22253 TargetLowering::DAGCombinerInfo &DCI,
22254 const X86Subtarget *Subtarget) {
22258 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22259 /// specific shuffle of a load can be folded into a single element load.
22260 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22261 /// shuffles have been custom lowered so we need to handle those here.
22262 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22263 TargetLowering::DAGCombinerInfo &DCI) {
22264 if (DCI.isBeforeLegalizeOps())
22267 SDValue InVec = N->getOperand(0);
22268 SDValue EltNo = N->getOperand(1);
22270 if (!isa<ConstantSDNode>(EltNo))
22273 EVT OriginalVT = InVec.getValueType();
22275 if (InVec.getOpcode() == ISD::BITCAST) {
22276 // Don't duplicate a load with other uses.
22277 if (!InVec.hasOneUse())
22279 EVT BCVT = InVec.getOperand(0).getValueType();
22280 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22282 InVec = InVec.getOperand(0);
22285 EVT CurrentVT = InVec.getValueType();
22287 if (!isTargetShuffle(InVec.getOpcode()))
22290 // Don't duplicate a load with other uses.
22291 if (!InVec.hasOneUse())
22294 SmallVector<int, 16> ShuffleMask;
22296 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22297 ShuffleMask, UnaryShuffle))
22300 // Select the input vector, guarding against out of range extract vector.
22301 unsigned NumElems = CurrentVT.getVectorNumElements();
22302 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22303 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22304 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22305 : InVec.getOperand(1);
22307 // If inputs to shuffle are the same for both ops, then allow 2 uses
22308 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22310 if (LdNode.getOpcode() == ISD::BITCAST) {
22311 // Don't duplicate a load with other uses.
22312 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22315 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22316 LdNode = LdNode.getOperand(0);
22319 if (!ISD::isNormalLoad(LdNode.getNode()))
22322 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22324 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22327 EVT EltVT = N->getValueType(0);
22328 // If there's a bitcast before the shuffle, check if the load type and
22329 // alignment is valid.
22330 unsigned Align = LN0->getAlignment();
22331 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22332 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22333 EltVT.getTypeForEVT(*DAG.getContext()));
22335 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22338 // All checks match so transform back to vector_shuffle so that DAG combiner
22339 // can finish the job
22342 // Create shuffle node taking into account the case that its a unary shuffle
22343 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22344 : InVec.getOperand(1);
22345 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22346 InVec.getOperand(0), Shuffle,
22348 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22349 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22353 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22354 /// generation and convert it from being a bunch of shuffles and extracts
22355 /// to a simple store and scalar loads to extract the elements.
22356 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22357 TargetLowering::DAGCombinerInfo &DCI) {
22358 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22359 if (NewOp.getNode())
22362 SDValue InputVector = N->getOperand(0);
22364 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22365 // from mmx to v2i32 has a single usage.
22366 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22367 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22368 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22369 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22370 N->getValueType(0),
22371 InputVector.getNode()->getOperand(0));
22373 // Only operate on vectors of 4 elements, where the alternative shuffling
22374 // gets to be more expensive.
22375 if (InputVector.getValueType() != MVT::v4i32)
22378 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22379 // single use which is a sign-extend or zero-extend, and all elements are
22381 SmallVector<SDNode *, 4> Uses;
22382 unsigned ExtractedElements = 0;
22383 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22384 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22385 if (UI.getUse().getResNo() != InputVector.getResNo())
22388 SDNode *Extract = *UI;
22389 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22392 if (Extract->getValueType(0) != MVT::i32)
22394 if (!Extract->hasOneUse())
22396 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22397 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22399 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22402 // Record which element was extracted.
22403 ExtractedElements |=
22404 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22406 Uses.push_back(Extract);
22409 // If not all the elements were used, this may not be worthwhile.
22410 if (ExtractedElements != 15)
22413 // Ok, we've now decided to do the transformation.
22414 SDLoc dl(InputVector);
22416 // Store the value to a temporary stack slot.
22417 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22418 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22419 MachinePointerInfo(), false, false, 0);
22421 // Replace each use (extract) with a load of the appropriate element.
22422 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22423 UE = Uses.end(); UI != UE; ++UI) {
22424 SDNode *Extract = *UI;
22426 // cOMpute the element's address.
22427 SDValue Idx = Extract->getOperand(1);
22429 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22430 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22431 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22432 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22434 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22435 StackPtr, OffsetVal);
22437 // Load the scalar.
22438 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22439 ScalarAddr, MachinePointerInfo(),
22440 false, false, false, 0);
22442 // Replace the exact with the load.
22443 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22446 // The replacement was made in place; don't return anything.
22450 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22451 static std::pair<unsigned, bool>
22452 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22453 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22454 if (!VT.isVector())
22455 return std::make_pair(0, false);
22457 bool NeedSplit = false;
22458 switch (VT.getSimpleVT().SimpleTy) {
22459 default: return std::make_pair(0, false);
22463 if (!Subtarget->hasAVX2())
22465 if (!Subtarget->hasAVX())
22466 return std::make_pair(0, false);
22471 if (!Subtarget->hasSSE2())
22472 return std::make_pair(0, false);
22475 // SSE2 has only a small subset of the operations.
22476 bool hasUnsigned = Subtarget->hasSSE41() ||
22477 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22478 bool hasSigned = Subtarget->hasSSE41() ||
22479 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22481 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22484 // Check for x CC y ? x : y.
22485 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22486 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22491 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22494 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22497 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22500 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22502 // Check for x CC y ? y : x -- a min/max with reversed arms.
22503 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22504 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22509 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22512 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22515 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22518 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22522 return std::make_pair(Opc, NeedSplit);
22526 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22527 const X86Subtarget *Subtarget) {
22529 SDValue Cond = N->getOperand(0);
22530 SDValue LHS = N->getOperand(1);
22531 SDValue RHS = N->getOperand(2);
22533 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22534 SDValue CondSrc = Cond->getOperand(0);
22535 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22536 Cond = CondSrc->getOperand(0);
22539 MVT VT = N->getSimpleValueType(0);
22540 MVT EltVT = VT.getVectorElementType();
22541 unsigned NumElems = VT.getVectorNumElements();
22542 // There is no blend with immediate in AVX-512.
22543 if (VT.is512BitVector())
22546 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22548 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22551 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22554 // A vselect where all conditions and data are constants can be optimized into
22555 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22556 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22557 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22560 unsigned MaskValue = 0;
22561 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22564 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22565 for (unsigned i = 0; i < NumElems; ++i) {
22566 // Be sure we emit undef where we can.
22567 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22568 ShuffleMask[i] = -1;
22570 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22573 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22576 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22578 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22579 TargetLowering::DAGCombinerInfo &DCI,
22580 const X86Subtarget *Subtarget) {
22582 SDValue Cond = N->getOperand(0);
22583 // Get the LHS/RHS of the select.
22584 SDValue LHS = N->getOperand(1);
22585 SDValue RHS = N->getOperand(2);
22586 EVT VT = LHS.getValueType();
22587 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22589 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22590 // instructions match the semantics of the common C idiom x<y?x:y but not
22591 // x<=y?x:y, because of how they handle negative zero (which can be
22592 // ignored in unsafe-math mode).
22593 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22594 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22595 (Subtarget->hasSSE2() ||
22596 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22597 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22599 unsigned Opcode = 0;
22600 // Check for x CC y ? x : y.
22601 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22602 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22606 // Converting this to a min would handle NaNs incorrectly, and swapping
22607 // the operands would cause it to handle comparisons between positive
22608 // and negative zero incorrectly.
22609 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22610 if (!DAG.getTarget().Options.UnsafeFPMath &&
22611 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22613 std::swap(LHS, RHS);
22615 Opcode = X86ISD::FMIN;
22618 // Converting this to a min would handle comparisons between positive
22619 // and negative zero incorrectly.
22620 if (!DAG.getTarget().Options.UnsafeFPMath &&
22621 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22623 Opcode = X86ISD::FMIN;
22626 // Converting this to a min would handle both negative zeros and NaNs
22627 // incorrectly, but we can swap the operands to fix both.
22628 std::swap(LHS, RHS);
22632 Opcode = X86ISD::FMIN;
22636 // Converting this to a max would handle comparisons between positive
22637 // and negative zero incorrectly.
22638 if (!DAG.getTarget().Options.UnsafeFPMath &&
22639 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22641 Opcode = X86ISD::FMAX;
22644 // Converting this to a max would handle NaNs incorrectly, and swapping
22645 // the operands would cause it to handle comparisons between positive
22646 // and negative zero incorrectly.
22647 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22648 if (!DAG.getTarget().Options.UnsafeFPMath &&
22649 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22651 std::swap(LHS, RHS);
22653 Opcode = X86ISD::FMAX;
22656 // Converting this to a max would handle both negative zeros and NaNs
22657 // incorrectly, but we can swap the operands to fix both.
22658 std::swap(LHS, RHS);
22662 Opcode = X86ISD::FMAX;
22665 // Check for x CC y ? y : x -- a min/max with reversed arms.
22666 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22667 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22671 // Converting this to a min would handle comparisons between positive
22672 // and negative zero incorrectly, and swapping the operands would
22673 // cause it to handle NaNs incorrectly.
22674 if (!DAG.getTarget().Options.UnsafeFPMath &&
22675 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22676 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22678 std::swap(LHS, RHS);
22680 Opcode = X86ISD::FMIN;
22683 // Converting this to a min would handle NaNs incorrectly.
22684 if (!DAG.getTarget().Options.UnsafeFPMath &&
22685 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22687 Opcode = X86ISD::FMIN;
22690 // Converting this to a min would handle both negative zeros and NaNs
22691 // incorrectly, but we can swap the operands to fix both.
22692 std::swap(LHS, RHS);
22696 Opcode = X86ISD::FMIN;
22700 // Converting this to a max would handle NaNs incorrectly.
22701 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22703 Opcode = X86ISD::FMAX;
22706 // Converting this to a max would handle comparisons between positive
22707 // and negative zero incorrectly, and swapping the operands would
22708 // cause it to handle NaNs incorrectly.
22709 if (!DAG.getTarget().Options.UnsafeFPMath &&
22710 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22711 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22713 std::swap(LHS, RHS);
22715 Opcode = X86ISD::FMAX;
22718 // Converting this to a max would handle both negative zeros and NaNs
22719 // incorrectly, but we can swap the operands to fix both.
22720 std::swap(LHS, RHS);
22724 Opcode = X86ISD::FMAX;
22730 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22733 EVT CondVT = Cond.getValueType();
22734 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22735 CondVT.getVectorElementType() == MVT::i1) {
22736 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22737 // lowering on KNL. In this case we convert it to
22738 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22739 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22740 // Since SKX these selects have a proper lowering.
22741 EVT OpVT = LHS.getValueType();
22742 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22743 (OpVT.getVectorElementType() == MVT::i8 ||
22744 OpVT.getVectorElementType() == MVT::i16) &&
22745 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22746 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22747 DCI.AddToWorklist(Cond.getNode());
22748 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22751 // If this is a select between two integer constants, try to do some
22753 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22754 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22755 // Don't do this for crazy integer types.
22756 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22757 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22758 // so that TrueC (the true value) is larger than FalseC.
22759 bool NeedsCondInvert = false;
22761 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22762 // Efficiently invertible.
22763 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22764 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22765 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22766 NeedsCondInvert = true;
22767 std::swap(TrueC, FalseC);
22770 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22771 if (FalseC->getAPIntValue() == 0 &&
22772 TrueC->getAPIntValue().isPowerOf2()) {
22773 if (NeedsCondInvert) // Invert the condition if needed.
22774 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22775 DAG.getConstant(1, Cond.getValueType()));
22777 // Zero extend the condition if needed.
22778 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22780 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22781 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22782 DAG.getConstant(ShAmt, MVT::i8));
22785 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22786 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22787 if (NeedsCondInvert) // Invert the condition if needed.
22788 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22789 DAG.getConstant(1, Cond.getValueType()));
22791 // Zero extend the condition if needed.
22792 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22793 FalseC->getValueType(0), Cond);
22794 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22795 SDValue(FalseC, 0));
22798 // Optimize cases that will turn into an LEA instruction. This requires
22799 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22800 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22801 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22802 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22804 bool isFastMultiplier = false;
22806 switch ((unsigned char)Diff) {
22808 case 1: // result = add base, cond
22809 case 2: // result = lea base( , cond*2)
22810 case 3: // result = lea base(cond, cond*2)
22811 case 4: // result = lea base( , cond*4)
22812 case 5: // result = lea base(cond, cond*4)
22813 case 8: // result = lea base( , cond*8)
22814 case 9: // result = lea base(cond, cond*8)
22815 isFastMultiplier = true;
22820 if (isFastMultiplier) {
22821 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22822 if (NeedsCondInvert) // Invert the condition if needed.
22823 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22824 DAG.getConstant(1, Cond.getValueType()));
22826 // Zero extend the condition if needed.
22827 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22829 // Scale the condition by the difference.
22831 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22832 DAG.getConstant(Diff, Cond.getValueType()));
22834 // Add the base if non-zero.
22835 if (FalseC->getAPIntValue() != 0)
22836 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22837 SDValue(FalseC, 0));
22844 // Canonicalize max and min:
22845 // (x > y) ? x : y -> (x >= y) ? x : y
22846 // (x < y) ? x : y -> (x <= y) ? x : y
22847 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22848 // the need for an extra compare
22849 // against zero. e.g.
22850 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22852 // testl %edi, %edi
22854 // cmovgl %edi, %eax
22858 // cmovsl %eax, %edi
22859 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22860 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22861 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22862 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22867 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22868 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22869 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22870 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22875 // Early exit check
22876 if (!TLI.isTypeLegal(VT))
22879 // Match VSELECTs into subs with unsigned saturation.
22880 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22881 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22882 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22883 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22884 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22886 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22887 // left side invert the predicate to simplify logic below.
22889 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22891 CC = ISD::getSetCCInverse(CC, true);
22892 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22896 if (Other.getNode() && Other->getNumOperands() == 2 &&
22897 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22898 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22899 SDValue CondRHS = Cond->getOperand(1);
22901 // Look for a general sub with unsigned saturation first.
22902 // x >= y ? x-y : 0 --> subus x, y
22903 // x > y ? x-y : 0 --> subus x, y
22904 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22905 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22906 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22908 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22909 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22910 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22911 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22912 // If the RHS is a constant we have to reverse the const
22913 // canonicalization.
22914 // x > C-1 ? x+-C : 0 --> subus x, C
22915 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22916 CondRHSConst->getAPIntValue() ==
22917 (-OpRHSConst->getAPIntValue() - 1))
22918 return DAG.getNode(
22919 X86ISD::SUBUS, DL, VT, OpLHS,
22920 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22922 // Another special case: If C was a sign bit, the sub has been
22923 // canonicalized into a xor.
22924 // FIXME: Would it be better to use computeKnownBits to determine
22925 // whether it's safe to decanonicalize the xor?
22926 // x s< 0 ? x^C : 0 --> subus x, C
22927 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22928 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22929 OpRHSConst->getAPIntValue().isSignBit())
22930 // Note that we have to rebuild the RHS constant here to ensure we
22931 // don't rely on particular values of undef lanes.
22932 return DAG.getNode(
22933 X86ISD::SUBUS, DL, VT, OpLHS,
22934 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22939 // Try to match a min/max vector operation.
22940 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22941 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22942 unsigned Opc = ret.first;
22943 bool NeedSplit = ret.second;
22945 if (Opc && NeedSplit) {
22946 unsigned NumElems = VT.getVectorNumElements();
22947 // Extract the LHS vectors
22948 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22949 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22951 // Extract the RHS vectors
22952 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22953 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22955 // Create min/max for each subvector
22956 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22957 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22959 // Merge the result
22960 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22962 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22965 // Simplify vector selection if condition value type matches vselect
22967 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22968 assert(Cond.getValueType().isVector() &&
22969 "vector select expects a vector selector!");
22971 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22972 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22974 // Try invert the condition if true value is not all 1s and false value
22976 if (!TValIsAllOnes && !FValIsAllZeros &&
22977 // Check if the selector will be produced by CMPP*/PCMP*
22978 Cond.getOpcode() == ISD::SETCC &&
22979 // Check if SETCC has already been promoted
22980 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22981 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22982 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22984 if (TValIsAllZeros || FValIsAllOnes) {
22985 SDValue CC = Cond.getOperand(2);
22986 ISD::CondCode NewCC =
22987 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22988 Cond.getOperand(0).getValueType().isInteger());
22989 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22990 std::swap(LHS, RHS);
22991 TValIsAllOnes = FValIsAllOnes;
22992 FValIsAllZeros = TValIsAllZeros;
22996 if (TValIsAllOnes || FValIsAllZeros) {
22999 if (TValIsAllOnes && FValIsAllZeros)
23001 else if (TValIsAllOnes)
23002 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23003 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23004 else if (FValIsAllZeros)
23005 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23006 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23008 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23012 // Try to fold this VSELECT into a MOVSS/MOVSD
23013 if (N->getOpcode() == ISD::VSELECT &&
23014 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
23015 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
23016 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
23017 bool CanFold = false;
23018 unsigned NumElems = Cond.getNumOperands();
23022 if (isZero(Cond.getOperand(0))) {
23025 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
23026 // fold (vselect <0,-1> -> (movsd A, B)
23027 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
23028 CanFold = isAllOnes(Cond.getOperand(i));
23029 } else if (isAllOnes(Cond.getOperand(0))) {
23033 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
23034 // fold (vselect <-1,0> -> (movsd B, A)
23035 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
23036 CanFold = isZero(Cond.getOperand(i));
23040 if (VT == MVT::v4i32 || VT == MVT::v4f32)
23041 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
23042 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
23045 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
23046 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
23047 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
23048 // (v2i64 (bitcast B)))))
23050 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
23051 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
23052 // (v2f64 (bitcast B)))))
23054 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
23055 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
23056 // (v2i64 (bitcast A)))))
23058 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
23059 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
23060 // (v2f64 (bitcast A)))))
23062 CanFold = (isZero(Cond.getOperand(0)) &&
23063 isZero(Cond.getOperand(1)) &&
23064 isAllOnes(Cond.getOperand(2)) &&
23065 isAllOnes(Cond.getOperand(3)));
23067 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
23068 isAllOnes(Cond.getOperand(1)) &&
23069 isZero(Cond.getOperand(2)) &&
23070 isZero(Cond.getOperand(3))) {
23072 std::swap(LHS, RHS);
23076 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
23077 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
23078 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
23079 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
23081 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
23087 // If we know that this node is legal then we know that it is going to be
23088 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23089 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23090 // to simplify previous instructions.
23091 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23092 !DCI.isBeforeLegalize() &&
23093 // We explicitly check against v8i16 and v16i16 because, although
23094 // they're marked as Custom, they might only be legal when Cond is a
23095 // build_vector of constants. This will be taken care in a later
23097 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23098 VT != MVT::v8i16) &&
23099 // Don't optimize vector of constants. Those are handled by
23100 // the generic code and all the bits must be properly set for
23101 // the generic optimizer.
23102 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23103 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23105 // Don't optimize vector selects that map to mask-registers.
23109 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23110 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23112 APInt KnownZero, KnownOne;
23113 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23114 DCI.isBeforeLegalizeOps());
23115 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23116 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23118 // If we changed the computation somewhere in the DAG, this change
23119 // will affect all users of Cond.
23120 // Make sure it is fine and update all the nodes so that we do not
23121 // use the generic VSELECT anymore. Otherwise, we may perform
23122 // wrong optimizations as we messed up with the actual expectation
23123 // for the vector boolean values.
23124 if (Cond != TLO.Old) {
23125 // Check all uses of that condition operand to check whether it will be
23126 // consumed by non-BLEND instructions, which may depend on all bits are
23128 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23130 if (I->getOpcode() != ISD::VSELECT)
23131 // TODO: Add other opcodes eventually lowered into BLEND.
23134 // Update all the users of the condition, before committing the change,
23135 // so that the VSELECT optimizations that expect the correct vector
23136 // boolean value will not be triggered.
23137 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23139 DAG.ReplaceAllUsesOfValueWith(
23141 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23142 Cond, I->getOperand(1), I->getOperand(2)));
23143 DCI.CommitTargetLoweringOpt(TLO);
23146 // At this point, only Cond is changed. Change the condition
23147 // just for N to keep the opportunity to optimize all other
23148 // users their own way.
23149 DAG.ReplaceAllUsesOfValueWith(
23151 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23152 TLO.New, N->getOperand(1), N->getOperand(2)));
23157 // We should generate an X86ISD::BLENDI from a vselect if its argument
23158 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23159 // constants. This specific pattern gets generated when we split a
23160 // selector for a 512 bit vector in a machine without AVX512 (but with
23161 // 256-bit vectors), during legalization:
23163 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23165 // Iff we find this pattern and the build_vectors are built from
23166 // constants, we translate the vselect into a shuffle_vector that we
23167 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23168 if ((N->getOpcode() == ISD::VSELECT ||
23169 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23170 !DCI.isBeforeLegalize()) {
23171 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23172 if (Shuffle.getNode())
23179 // Check whether a boolean test is testing a boolean value generated by
23180 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23183 // Simplify the following patterns:
23184 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23185 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23186 // to (Op EFLAGS Cond)
23188 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23189 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23190 // to (Op EFLAGS !Cond)
23192 // where Op could be BRCOND or CMOV.
23194 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23195 // Quit if not CMP and SUB with its value result used.
23196 if (Cmp.getOpcode() != X86ISD::CMP &&
23197 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23200 // Quit if not used as a boolean value.
23201 if (CC != X86::COND_E && CC != X86::COND_NE)
23204 // Check CMP operands. One of them should be 0 or 1 and the other should be
23205 // an SetCC or extended from it.
23206 SDValue Op1 = Cmp.getOperand(0);
23207 SDValue Op2 = Cmp.getOperand(1);
23210 const ConstantSDNode* C = nullptr;
23211 bool needOppositeCond = (CC == X86::COND_E);
23212 bool checkAgainstTrue = false; // Is it a comparison against 1?
23214 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23216 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23218 else // Quit if all operands are not constants.
23221 if (C->getZExtValue() == 1) {
23222 needOppositeCond = !needOppositeCond;
23223 checkAgainstTrue = true;
23224 } else if (C->getZExtValue() != 0)
23225 // Quit if the constant is neither 0 or 1.
23228 bool truncatedToBoolWithAnd = false;
23229 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23230 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23231 SetCC.getOpcode() == ISD::TRUNCATE ||
23232 SetCC.getOpcode() == ISD::AND) {
23233 if (SetCC.getOpcode() == ISD::AND) {
23235 ConstantSDNode *CS;
23236 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23237 CS->getZExtValue() == 1)
23239 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23240 CS->getZExtValue() == 1)
23244 SetCC = SetCC.getOperand(OpIdx);
23245 truncatedToBoolWithAnd = true;
23247 SetCC = SetCC.getOperand(0);
23250 switch (SetCC.getOpcode()) {
23251 case X86ISD::SETCC_CARRY:
23252 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23253 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23254 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23255 // truncated to i1 using 'and'.
23256 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23258 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23259 "Invalid use of SETCC_CARRY!");
23261 case X86ISD::SETCC:
23262 // Set the condition code or opposite one if necessary.
23263 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23264 if (needOppositeCond)
23265 CC = X86::GetOppositeBranchCondition(CC);
23266 return SetCC.getOperand(1);
23267 case X86ISD::CMOV: {
23268 // Check whether false/true value has canonical one, i.e. 0 or 1.
23269 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23270 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23271 // Quit if true value is not a constant.
23274 // Quit if false value is not a constant.
23276 SDValue Op = SetCC.getOperand(0);
23277 // Skip 'zext' or 'trunc' node.
23278 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23279 Op.getOpcode() == ISD::TRUNCATE)
23280 Op = Op.getOperand(0);
23281 // A special case for rdrand/rdseed, where 0 is set if false cond is
23283 if ((Op.getOpcode() != X86ISD::RDRAND &&
23284 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23287 // Quit if false value is not the constant 0 or 1.
23288 bool FValIsFalse = true;
23289 if (FVal && FVal->getZExtValue() != 0) {
23290 if (FVal->getZExtValue() != 1)
23292 // If FVal is 1, opposite cond is needed.
23293 needOppositeCond = !needOppositeCond;
23294 FValIsFalse = false;
23296 // Quit if TVal is not the constant opposite of FVal.
23297 if (FValIsFalse && TVal->getZExtValue() != 1)
23299 if (!FValIsFalse && TVal->getZExtValue() != 0)
23301 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23302 if (needOppositeCond)
23303 CC = X86::GetOppositeBranchCondition(CC);
23304 return SetCC.getOperand(3);
23311 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23312 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23313 TargetLowering::DAGCombinerInfo &DCI,
23314 const X86Subtarget *Subtarget) {
23317 // If the flag operand isn't dead, don't touch this CMOV.
23318 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23321 SDValue FalseOp = N->getOperand(0);
23322 SDValue TrueOp = N->getOperand(1);
23323 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23324 SDValue Cond = N->getOperand(3);
23326 if (CC == X86::COND_E || CC == X86::COND_NE) {
23327 switch (Cond.getOpcode()) {
23331 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23332 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23333 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23339 Flags = checkBoolTestSetCCCombine(Cond, CC);
23340 if (Flags.getNode() &&
23341 // Extra check as FCMOV only supports a subset of X86 cond.
23342 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23343 SDValue Ops[] = { FalseOp, TrueOp,
23344 DAG.getConstant(CC, MVT::i8), Flags };
23345 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23348 // If this is a select between two integer constants, try to do some
23349 // optimizations. Note that the operands are ordered the opposite of SELECT
23351 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23352 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23353 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23354 // larger than FalseC (the false value).
23355 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23356 CC = X86::GetOppositeBranchCondition(CC);
23357 std::swap(TrueC, FalseC);
23358 std::swap(TrueOp, FalseOp);
23361 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23362 // This is efficient for any integer data type (including i8/i16) and
23364 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23365 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23366 DAG.getConstant(CC, MVT::i8), Cond);
23368 // Zero extend the condition if needed.
23369 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23371 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23372 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23373 DAG.getConstant(ShAmt, MVT::i8));
23374 if (N->getNumValues() == 2) // Dead flag value?
23375 return DCI.CombineTo(N, Cond, SDValue());
23379 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23380 // for any integer data type, including i8/i16.
23381 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23382 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23383 DAG.getConstant(CC, MVT::i8), Cond);
23385 // Zero extend the condition if needed.
23386 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23387 FalseC->getValueType(0), Cond);
23388 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23389 SDValue(FalseC, 0));
23391 if (N->getNumValues() == 2) // Dead flag value?
23392 return DCI.CombineTo(N, Cond, SDValue());
23396 // Optimize cases that will turn into an LEA instruction. This requires
23397 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23398 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23399 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23400 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23402 bool isFastMultiplier = false;
23404 switch ((unsigned char)Diff) {
23406 case 1: // result = add base, cond
23407 case 2: // result = lea base( , cond*2)
23408 case 3: // result = lea base(cond, cond*2)
23409 case 4: // result = lea base( , cond*4)
23410 case 5: // result = lea base(cond, cond*4)
23411 case 8: // result = lea base( , cond*8)
23412 case 9: // result = lea base(cond, cond*8)
23413 isFastMultiplier = true;
23418 if (isFastMultiplier) {
23419 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23420 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23421 DAG.getConstant(CC, MVT::i8), Cond);
23422 // Zero extend the condition if needed.
23423 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23425 // Scale the condition by the difference.
23427 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23428 DAG.getConstant(Diff, Cond.getValueType()));
23430 // Add the base if non-zero.
23431 if (FalseC->getAPIntValue() != 0)
23432 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23433 SDValue(FalseC, 0));
23434 if (N->getNumValues() == 2) // Dead flag value?
23435 return DCI.CombineTo(N, Cond, SDValue());
23442 // Handle these cases:
23443 // (select (x != c), e, c) -> select (x != c), e, x),
23444 // (select (x == c), c, e) -> select (x == c), x, e)
23445 // where the c is an integer constant, and the "select" is the combination
23446 // of CMOV and CMP.
23448 // The rationale for this change is that the conditional-move from a constant
23449 // needs two instructions, however, conditional-move from a register needs
23450 // only one instruction.
23452 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23453 // some instruction-combining opportunities. This opt needs to be
23454 // postponed as late as possible.
23456 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23457 // the DCI.xxxx conditions are provided to postpone the optimization as
23458 // late as possible.
23460 ConstantSDNode *CmpAgainst = nullptr;
23461 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23462 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23463 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23465 if (CC == X86::COND_NE &&
23466 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23467 CC = X86::GetOppositeBranchCondition(CC);
23468 std::swap(TrueOp, FalseOp);
23471 if (CC == X86::COND_E &&
23472 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23473 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23474 DAG.getConstant(CC, MVT::i8), Cond };
23475 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23483 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23484 const X86Subtarget *Subtarget) {
23485 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23487 default: return SDValue();
23488 // SSE/AVX/AVX2 blend intrinsics.
23489 case Intrinsic::x86_avx2_pblendvb:
23490 case Intrinsic::x86_avx2_pblendw:
23491 case Intrinsic::x86_avx2_pblendd_128:
23492 case Intrinsic::x86_avx2_pblendd_256:
23493 // Don't try to simplify this intrinsic if we don't have AVX2.
23494 if (!Subtarget->hasAVX2())
23497 case Intrinsic::x86_avx_blend_pd_256:
23498 case Intrinsic::x86_avx_blend_ps_256:
23499 case Intrinsic::x86_avx_blendv_pd_256:
23500 case Intrinsic::x86_avx_blendv_ps_256:
23501 // Don't try to simplify this intrinsic if we don't have AVX.
23502 if (!Subtarget->hasAVX())
23505 case Intrinsic::x86_sse41_pblendw:
23506 case Intrinsic::x86_sse41_blendpd:
23507 case Intrinsic::x86_sse41_blendps:
23508 case Intrinsic::x86_sse41_blendvps:
23509 case Intrinsic::x86_sse41_blendvpd:
23510 case Intrinsic::x86_sse41_pblendvb: {
23511 SDValue Op0 = N->getOperand(1);
23512 SDValue Op1 = N->getOperand(2);
23513 SDValue Mask = N->getOperand(3);
23515 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23516 if (!Subtarget->hasSSE41())
23519 // fold (blend A, A, Mask) -> A
23522 // fold (blend A, B, allZeros) -> A
23523 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23525 // fold (blend A, B, allOnes) -> B
23526 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23529 // Simplify the case where the mask is a constant i32 value.
23530 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23531 if (C->isNullValue())
23533 if (C->isAllOnesValue())
23540 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23541 case Intrinsic::x86_sse2_psrai_w:
23542 case Intrinsic::x86_sse2_psrai_d:
23543 case Intrinsic::x86_avx2_psrai_w:
23544 case Intrinsic::x86_avx2_psrai_d:
23545 case Intrinsic::x86_sse2_psra_w:
23546 case Intrinsic::x86_sse2_psra_d:
23547 case Intrinsic::x86_avx2_psra_w:
23548 case Intrinsic::x86_avx2_psra_d: {
23549 SDValue Op0 = N->getOperand(1);
23550 SDValue Op1 = N->getOperand(2);
23551 EVT VT = Op0.getValueType();
23552 assert(VT.isVector() && "Expected a vector type!");
23554 if (isa<BuildVectorSDNode>(Op1))
23555 Op1 = Op1.getOperand(0);
23557 if (!isa<ConstantSDNode>(Op1))
23560 EVT SVT = VT.getVectorElementType();
23561 unsigned SVTBits = SVT.getSizeInBits();
23563 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23564 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23565 uint64_t ShAmt = C.getZExtValue();
23567 // Don't try to convert this shift into a ISD::SRA if the shift
23568 // count is bigger than or equal to the element size.
23569 if (ShAmt >= SVTBits)
23572 // Trivial case: if the shift count is zero, then fold this
23573 // into the first operand.
23577 // Replace this packed shift intrinsic with a target independent
23579 SDValue Splat = DAG.getConstant(C, VT);
23580 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23585 /// PerformMulCombine - Optimize a single multiply with constant into two
23586 /// in order to implement it with two cheaper instructions, e.g.
23587 /// LEA + SHL, LEA + LEA.
23588 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23589 TargetLowering::DAGCombinerInfo &DCI) {
23590 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23593 EVT VT = N->getValueType(0);
23594 if (VT != MVT::i64)
23597 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23600 uint64_t MulAmt = C->getZExtValue();
23601 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23604 uint64_t MulAmt1 = 0;
23605 uint64_t MulAmt2 = 0;
23606 if ((MulAmt % 9) == 0) {
23608 MulAmt2 = MulAmt / 9;
23609 } else if ((MulAmt % 5) == 0) {
23611 MulAmt2 = MulAmt / 5;
23612 } else if ((MulAmt % 3) == 0) {
23614 MulAmt2 = MulAmt / 3;
23617 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23620 if (isPowerOf2_64(MulAmt2) &&
23621 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23622 // If second multiplifer is pow2, issue it first. We want the multiply by
23623 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23625 std::swap(MulAmt1, MulAmt2);
23628 if (isPowerOf2_64(MulAmt1))
23629 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23630 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23632 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23633 DAG.getConstant(MulAmt1, VT));
23635 if (isPowerOf2_64(MulAmt2))
23636 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23637 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23639 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23640 DAG.getConstant(MulAmt2, VT));
23642 // Do not add new nodes to DAG combiner worklist.
23643 DCI.CombineTo(N, NewMul, false);
23648 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23649 SDValue N0 = N->getOperand(0);
23650 SDValue N1 = N->getOperand(1);
23651 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23652 EVT VT = N0.getValueType();
23654 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23655 // since the result of setcc_c is all zero's or all ones.
23656 if (VT.isInteger() && !VT.isVector() &&
23657 N1C && N0.getOpcode() == ISD::AND &&
23658 N0.getOperand(1).getOpcode() == ISD::Constant) {
23659 SDValue N00 = N0.getOperand(0);
23660 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23661 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23662 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23663 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23664 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23665 APInt ShAmt = N1C->getAPIntValue();
23666 Mask = Mask.shl(ShAmt);
23668 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23669 N00, DAG.getConstant(Mask, VT));
23673 // Hardware support for vector shifts is sparse which makes us scalarize the
23674 // vector operations in many cases. Also, on sandybridge ADD is faster than
23676 // (shl V, 1) -> add V,V
23677 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23678 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23679 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23680 // We shift all of the values by one. In many cases we do not have
23681 // hardware support for this operation. This is better expressed as an ADD
23683 if (N1SplatC->getZExtValue() == 1)
23684 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23690 /// \brief Returns a vector of 0s if the node in input is a vector logical
23691 /// shift by a constant amount which is known to be bigger than or equal
23692 /// to the vector element size in bits.
23693 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23694 const X86Subtarget *Subtarget) {
23695 EVT VT = N->getValueType(0);
23697 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23698 (!Subtarget->hasInt256() ||
23699 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23702 SDValue Amt = N->getOperand(1);
23704 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23705 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23706 APInt ShiftAmt = AmtSplat->getAPIntValue();
23707 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23709 // SSE2/AVX2 logical shifts always return a vector of 0s
23710 // if the shift amount is bigger than or equal to
23711 // the element size. The constant shift amount will be
23712 // encoded as a 8-bit immediate.
23713 if (ShiftAmt.trunc(8).uge(MaxAmount))
23714 return getZeroVector(VT, Subtarget, DAG, DL);
23720 /// PerformShiftCombine - Combine shifts.
23721 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23722 TargetLowering::DAGCombinerInfo &DCI,
23723 const X86Subtarget *Subtarget) {
23724 if (N->getOpcode() == ISD::SHL) {
23725 SDValue V = PerformSHLCombine(N, DAG);
23726 if (V.getNode()) return V;
23729 if (N->getOpcode() != ISD::SRA) {
23730 // Try to fold this logical shift into a zero vector.
23731 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23732 if (V.getNode()) return V;
23738 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23739 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23740 // and friends. Likewise for OR -> CMPNEQSS.
23741 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23742 TargetLowering::DAGCombinerInfo &DCI,
23743 const X86Subtarget *Subtarget) {
23746 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23747 // we're requiring SSE2 for both.
23748 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23749 SDValue N0 = N->getOperand(0);
23750 SDValue N1 = N->getOperand(1);
23751 SDValue CMP0 = N0->getOperand(1);
23752 SDValue CMP1 = N1->getOperand(1);
23755 // The SETCCs should both refer to the same CMP.
23756 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23759 SDValue CMP00 = CMP0->getOperand(0);
23760 SDValue CMP01 = CMP0->getOperand(1);
23761 EVT VT = CMP00.getValueType();
23763 if (VT == MVT::f32 || VT == MVT::f64) {
23764 bool ExpectingFlags = false;
23765 // Check for any users that want flags:
23766 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23767 !ExpectingFlags && UI != UE; ++UI)
23768 switch (UI->getOpcode()) {
23773 ExpectingFlags = true;
23775 case ISD::CopyToReg:
23776 case ISD::SIGN_EXTEND:
23777 case ISD::ZERO_EXTEND:
23778 case ISD::ANY_EXTEND:
23782 if (!ExpectingFlags) {
23783 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23784 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23786 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23787 X86::CondCode tmp = cc0;
23792 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23793 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23794 // FIXME: need symbolic constants for these magic numbers.
23795 // See X86ATTInstPrinter.cpp:printSSECC().
23796 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23797 if (Subtarget->hasAVX512()) {
23798 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23799 CMP01, DAG.getConstant(x86cc, MVT::i8));
23800 if (N->getValueType(0) != MVT::i1)
23801 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23805 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23806 CMP00.getValueType(), CMP00, CMP01,
23807 DAG.getConstant(x86cc, MVT::i8));
23809 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23810 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23812 if (is64BitFP && !Subtarget->is64Bit()) {
23813 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23814 // 64-bit integer, since that's not a legal type. Since
23815 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23816 // bits, but can do this little dance to extract the lowest 32 bits
23817 // and work with those going forward.
23818 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23820 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23822 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23823 Vector32, DAG.getIntPtrConstant(0));
23827 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23828 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23829 DAG.getConstant(1, IntVT));
23830 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23831 return OneBitOfTruth;
23839 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23840 /// so it can be folded inside ANDNP.
23841 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23842 EVT VT = N->getValueType(0);
23844 // Match direct AllOnes for 128 and 256-bit vectors
23845 if (ISD::isBuildVectorAllOnes(N))
23848 // Look through a bit convert.
23849 if (N->getOpcode() == ISD::BITCAST)
23850 N = N->getOperand(0).getNode();
23852 // Sometimes the operand may come from a insert_subvector building a 256-bit
23854 if (VT.is256BitVector() &&
23855 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23856 SDValue V1 = N->getOperand(0);
23857 SDValue V2 = N->getOperand(1);
23859 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23860 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23861 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23862 ISD::isBuildVectorAllOnes(V2.getNode()))
23869 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23870 // register. In most cases we actually compare or select YMM-sized registers
23871 // and mixing the two types creates horrible code. This method optimizes
23872 // some of the transition sequences.
23873 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23874 TargetLowering::DAGCombinerInfo &DCI,
23875 const X86Subtarget *Subtarget) {
23876 EVT VT = N->getValueType(0);
23877 if (!VT.is256BitVector())
23880 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23881 N->getOpcode() == ISD::ZERO_EXTEND ||
23882 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23884 SDValue Narrow = N->getOperand(0);
23885 EVT NarrowVT = Narrow->getValueType(0);
23886 if (!NarrowVT.is128BitVector())
23889 if (Narrow->getOpcode() != ISD::XOR &&
23890 Narrow->getOpcode() != ISD::AND &&
23891 Narrow->getOpcode() != ISD::OR)
23894 SDValue N0 = Narrow->getOperand(0);
23895 SDValue N1 = Narrow->getOperand(1);
23898 // The Left side has to be a trunc.
23899 if (N0.getOpcode() != ISD::TRUNCATE)
23902 // The type of the truncated inputs.
23903 EVT WideVT = N0->getOperand(0)->getValueType(0);
23907 // The right side has to be a 'trunc' or a constant vector.
23908 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23909 ConstantSDNode *RHSConstSplat = nullptr;
23910 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23911 RHSConstSplat = RHSBV->getConstantSplatNode();
23912 if (!RHSTrunc && !RHSConstSplat)
23915 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23917 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23920 // Set N0 and N1 to hold the inputs to the new wide operation.
23921 N0 = N0->getOperand(0);
23922 if (RHSConstSplat) {
23923 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23924 SDValue(RHSConstSplat, 0));
23925 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23926 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23927 } else if (RHSTrunc) {
23928 N1 = N1->getOperand(0);
23931 // Generate the wide operation.
23932 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23933 unsigned Opcode = N->getOpcode();
23935 case ISD::ANY_EXTEND:
23937 case ISD::ZERO_EXTEND: {
23938 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23939 APInt Mask = APInt::getAllOnesValue(InBits);
23940 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23941 return DAG.getNode(ISD::AND, DL, VT,
23942 Op, DAG.getConstant(Mask, VT));
23944 case ISD::SIGN_EXTEND:
23945 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23946 Op, DAG.getValueType(NarrowVT));
23948 llvm_unreachable("Unexpected opcode");
23952 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23953 TargetLowering::DAGCombinerInfo &DCI,
23954 const X86Subtarget *Subtarget) {
23955 EVT VT = N->getValueType(0);
23956 if (DCI.isBeforeLegalizeOps())
23959 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23963 // Create BEXTR instructions
23964 // BEXTR is ((X >> imm) & (2**size-1))
23965 if (VT == MVT::i32 || VT == MVT::i64) {
23966 SDValue N0 = N->getOperand(0);
23967 SDValue N1 = N->getOperand(1);
23970 // Check for BEXTR.
23971 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23972 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23973 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23974 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23975 if (MaskNode && ShiftNode) {
23976 uint64_t Mask = MaskNode->getZExtValue();
23977 uint64_t Shift = ShiftNode->getZExtValue();
23978 if (isMask_64(Mask)) {
23979 uint64_t MaskSize = CountPopulation_64(Mask);
23980 if (Shift + MaskSize <= VT.getSizeInBits())
23981 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23982 DAG.getConstant(Shift | (MaskSize << 8), VT));
23990 // Want to form ANDNP nodes:
23991 // 1) In the hopes of then easily combining them with OR and AND nodes
23992 // to form PBLEND/PSIGN.
23993 // 2) To match ANDN packed intrinsics
23994 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23997 SDValue N0 = N->getOperand(0);
23998 SDValue N1 = N->getOperand(1);
24001 // Check LHS for vnot
24002 if (N0.getOpcode() == ISD::XOR &&
24003 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24004 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24005 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24007 // Check RHS for vnot
24008 if (N1.getOpcode() == ISD::XOR &&
24009 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24010 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24011 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24016 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24017 TargetLowering::DAGCombinerInfo &DCI,
24018 const X86Subtarget *Subtarget) {
24019 if (DCI.isBeforeLegalizeOps())
24022 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24026 SDValue N0 = N->getOperand(0);
24027 SDValue N1 = N->getOperand(1);
24028 EVT VT = N->getValueType(0);
24030 // look for psign/blend
24031 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24032 if (!Subtarget->hasSSSE3() ||
24033 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24036 // Canonicalize pandn to RHS
24037 if (N0.getOpcode() == X86ISD::ANDNP)
24039 // or (and (m, y), (pandn m, x))
24040 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24041 SDValue Mask = N1.getOperand(0);
24042 SDValue X = N1.getOperand(1);
24044 if (N0.getOperand(0) == Mask)
24045 Y = N0.getOperand(1);
24046 if (N0.getOperand(1) == Mask)
24047 Y = N0.getOperand(0);
24049 // Check to see if the mask appeared in both the AND and ANDNP and
24053 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24054 // Look through mask bitcast.
24055 if (Mask.getOpcode() == ISD::BITCAST)
24056 Mask = Mask.getOperand(0);
24057 if (X.getOpcode() == ISD::BITCAST)
24058 X = X.getOperand(0);
24059 if (Y.getOpcode() == ISD::BITCAST)
24060 Y = Y.getOperand(0);
24062 EVT MaskVT = Mask.getValueType();
24064 // Validate that the Mask operand is a vector sra node.
24065 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24066 // there is no psrai.b
24067 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24068 unsigned SraAmt = ~0;
24069 if (Mask.getOpcode() == ISD::SRA) {
24070 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24071 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24072 SraAmt = AmtConst->getZExtValue();
24073 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24074 SDValue SraC = Mask.getOperand(1);
24075 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24077 if ((SraAmt + 1) != EltBits)
24082 // Now we know we at least have a plendvb with the mask val. See if
24083 // we can form a psignb/w/d.
24084 // psign = x.type == y.type == mask.type && y = sub(0, x);
24085 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24086 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24087 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24088 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24089 "Unsupported VT for PSIGN");
24090 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24091 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24093 // PBLENDVB only available on SSE 4.1
24094 if (!Subtarget->hasSSE41())
24097 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24099 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24100 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24101 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24102 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24103 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24107 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24110 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24111 MachineFunction &MF = DAG.getMachineFunction();
24112 bool OptForSize = MF.getFunction()->getAttributes().
24113 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24115 // SHLD/SHRD instructions have lower register pressure, but on some
24116 // platforms they have higher latency than the equivalent
24117 // series of shifts/or that would otherwise be generated.
24118 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24119 // have higher latencies and we are not optimizing for size.
24120 if (!OptForSize && Subtarget->isSHLDSlow())
24123 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24125 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24127 if (!N0.hasOneUse() || !N1.hasOneUse())
24130 SDValue ShAmt0 = N0.getOperand(1);
24131 if (ShAmt0.getValueType() != MVT::i8)
24133 SDValue ShAmt1 = N1.getOperand(1);
24134 if (ShAmt1.getValueType() != MVT::i8)
24136 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24137 ShAmt0 = ShAmt0.getOperand(0);
24138 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24139 ShAmt1 = ShAmt1.getOperand(0);
24142 unsigned Opc = X86ISD::SHLD;
24143 SDValue Op0 = N0.getOperand(0);
24144 SDValue Op1 = N1.getOperand(0);
24145 if (ShAmt0.getOpcode() == ISD::SUB) {
24146 Opc = X86ISD::SHRD;
24147 std::swap(Op0, Op1);
24148 std::swap(ShAmt0, ShAmt1);
24151 unsigned Bits = VT.getSizeInBits();
24152 if (ShAmt1.getOpcode() == ISD::SUB) {
24153 SDValue Sum = ShAmt1.getOperand(0);
24154 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24155 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24156 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24157 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24158 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24159 return DAG.getNode(Opc, DL, VT,
24161 DAG.getNode(ISD::TRUNCATE, DL,
24164 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24165 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24167 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24168 return DAG.getNode(Opc, DL, VT,
24169 N0.getOperand(0), N1.getOperand(0),
24170 DAG.getNode(ISD::TRUNCATE, DL,
24177 // Generate NEG and CMOV for integer abs.
24178 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24179 EVT VT = N->getValueType(0);
24181 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24182 // 8-bit integer abs to NEG and CMOV.
24183 if (VT.isInteger() && VT.getSizeInBits() == 8)
24186 SDValue N0 = N->getOperand(0);
24187 SDValue N1 = N->getOperand(1);
24190 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24191 // and change it to SUB and CMOV.
24192 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24193 N0.getOpcode() == ISD::ADD &&
24194 N0.getOperand(1) == N1 &&
24195 N1.getOpcode() == ISD::SRA &&
24196 N1.getOperand(0) == N0.getOperand(0))
24197 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24198 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24199 // Generate SUB & CMOV.
24200 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24201 DAG.getConstant(0, VT), N0.getOperand(0));
24203 SDValue Ops[] = { N0.getOperand(0), Neg,
24204 DAG.getConstant(X86::COND_GE, MVT::i8),
24205 SDValue(Neg.getNode(), 1) };
24206 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24211 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24212 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24213 TargetLowering::DAGCombinerInfo &DCI,
24214 const X86Subtarget *Subtarget) {
24215 if (DCI.isBeforeLegalizeOps())
24218 if (Subtarget->hasCMov()) {
24219 SDValue RV = performIntegerAbsCombine(N, DAG);
24227 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24228 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24229 TargetLowering::DAGCombinerInfo &DCI,
24230 const X86Subtarget *Subtarget) {
24231 LoadSDNode *Ld = cast<LoadSDNode>(N);
24232 EVT RegVT = Ld->getValueType(0);
24233 EVT MemVT = Ld->getMemoryVT();
24235 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24237 // On Sandybridge unaligned 256bit loads are inefficient.
24238 ISD::LoadExtType Ext = Ld->getExtensionType();
24239 unsigned Alignment = Ld->getAlignment();
24240 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24241 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
24242 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24243 unsigned NumElems = RegVT.getVectorNumElements();
24247 SDValue Ptr = Ld->getBasePtr();
24248 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24250 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24252 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24253 Ld->getPointerInfo(), Ld->isVolatile(),
24254 Ld->isNonTemporal(), Ld->isInvariant(),
24256 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24257 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24258 Ld->getPointerInfo(), Ld->isVolatile(),
24259 Ld->isNonTemporal(), Ld->isInvariant(),
24260 std::min(16U, Alignment));
24261 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24263 Load2.getValue(1));
24265 SDValue NewVec = DAG.getUNDEF(RegVT);
24266 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24267 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24268 return DCI.CombineTo(N, NewVec, TF, true);
24274 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24275 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24276 const X86Subtarget *Subtarget) {
24277 StoreSDNode *St = cast<StoreSDNode>(N);
24278 EVT VT = St->getValue().getValueType();
24279 EVT StVT = St->getMemoryVT();
24281 SDValue StoredVal = St->getOperand(1);
24282 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24284 // If we are saving a concatenation of two XMM registers, perform two stores.
24285 // On Sandy Bridge, 256-bit memory operations are executed by two
24286 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
24287 // memory operation.
24288 unsigned Alignment = St->getAlignment();
24289 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24290 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
24291 StVT == VT && !IsAligned) {
24292 unsigned NumElems = VT.getVectorNumElements();
24296 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24297 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24299 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24300 SDValue Ptr0 = St->getBasePtr();
24301 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24303 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24304 St->getPointerInfo(), St->isVolatile(),
24305 St->isNonTemporal(), Alignment);
24306 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24307 St->getPointerInfo(), St->isVolatile(),
24308 St->isNonTemporal(),
24309 std::min(16U, Alignment));
24310 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24313 // Optimize trunc store (of multiple scalars) to shuffle and store.
24314 // First, pack all of the elements in one place. Next, store to memory
24315 // in fewer chunks.
24316 if (St->isTruncatingStore() && VT.isVector()) {
24317 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24318 unsigned NumElems = VT.getVectorNumElements();
24319 assert(StVT != VT && "Cannot truncate to the same type");
24320 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24321 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24323 // From, To sizes and ElemCount must be pow of two
24324 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24325 // We are going to use the original vector elt for storing.
24326 // Accumulated smaller vector elements must be a multiple of the store size.
24327 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24329 unsigned SizeRatio = FromSz / ToSz;
24331 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24333 // Create a type on which we perform the shuffle
24334 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24335 StVT.getScalarType(), NumElems*SizeRatio);
24337 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24339 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24340 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24341 for (unsigned i = 0; i != NumElems; ++i)
24342 ShuffleVec[i] = i * SizeRatio;
24344 // Can't shuffle using an illegal type.
24345 if (!TLI.isTypeLegal(WideVecVT))
24348 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24349 DAG.getUNDEF(WideVecVT),
24351 // At this point all of the data is stored at the bottom of the
24352 // register. We now need to save it to mem.
24354 // Find the largest store unit
24355 MVT StoreType = MVT::i8;
24356 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24357 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24358 MVT Tp = (MVT::SimpleValueType)tp;
24359 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24363 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24364 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24365 (64 <= NumElems * ToSz))
24366 StoreType = MVT::f64;
24368 // Bitcast the original vector into a vector of store-size units
24369 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24370 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24371 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24372 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24373 SmallVector<SDValue, 8> Chains;
24374 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24375 TLI.getPointerTy());
24376 SDValue Ptr = St->getBasePtr();
24378 // Perform one or more big stores into memory.
24379 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24380 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24381 StoreType, ShuffWide,
24382 DAG.getIntPtrConstant(i));
24383 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24384 St->getPointerInfo(), St->isVolatile(),
24385 St->isNonTemporal(), St->getAlignment());
24386 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24387 Chains.push_back(Ch);
24390 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24393 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24394 // the FP state in cases where an emms may be missing.
24395 // A preferable solution to the general problem is to figure out the right
24396 // places to insert EMMS. This qualifies as a quick hack.
24398 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24399 if (VT.getSizeInBits() != 64)
24402 const Function *F = DAG.getMachineFunction().getFunction();
24403 bool NoImplicitFloatOps = F->getAttributes().
24404 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24405 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24406 && Subtarget->hasSSE2();
24407 if ((VT.isVector() ||
24408 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24409 isa<LoadSDNode>(St->getValue()) &&
24410 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24411 St->getChain().hasOneUse() && !St->isVolatile()) {
24412 SDNode* LdVal = St->getValue().getNode();
24413 LoadSDNode *Ld = nullptr;
24414 int TokenFactorIndex = -1;
24415 SmallVector<SDValue, 8> Ops;
24416 SDNode* ChainVal = St->getChain().getNode();
24417 // Must be a store of a load. We currently handle two cases: the load
24418 // is a direct child, and it's under an intervening TokenFactor. It is
24419 // possible to dig deeper under nested TokenFactors.
24420 if (ChainVal == LdVal)
24421 Ld = cast<LoadSDNode>(St->getChain());
24422 else if (St->getValue().hasOneUse() &&
24423 ChainVal->getOpcode() == ISD::TokenFactor) {
24424 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24425 if (ChainVal->getOperand(i).getNode() == LdVal) {
24426 TokenFactorIndex = i;
24427 Ld = cast<LoadSDNode>(St->getValue());
24429 Ops.push_back(ChainVal->getOperand(i));
24433 if (!Ld || !ISD::isNormalLoad(Ld))
24436 // If this is not the MMX case, i.e. we are just turning i64 load/store
24437 // into f64 load/store, avoid the transformation if there are multiple
24438 // uses of the loaded value.
24439 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24444 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24445 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24447 if (Subtarget->is64Bit() || F64IsLegal) {
24448 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24449 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24450 Ld->getPointerInfo(), Ld->isVolatile(),
24451 Ld->isNonTemporal(), Ld->isInvariant(),
24452 Ld->getAlignment());
24453 SDValue NewChain = NewLd.getValue(1);
24454 if (TokenFactorIndex != -1) {
24455 Ops.push_back(NewChain);
24456 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24458 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24459 St->getPointerInfo(),
24460 St->isVolatile(), St->isNonTemporal(),
24461 St->getAlignment());
24464 // Otherwise, lower to two pairs of 32-bit loads / stores.
24465 SDValue LoAddr = Ld->getBasePtr();
24466 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24467 DAG.getConstant(4, MVT::i32));
24469 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24470 Ld->getPointerInfo(),
24471 Ld->isVolatile(), Ld->isNonTemporal(),
24472 Ld->isInvariant(), Ld->getAlignment());
24473 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24474 Ld->getPointerInfo().getWithOffset(4),
24475 Ld->isVolatile(), Ld->isNonTemporal(),
24477 MinAlign(Ld->getAlignment(), 4));
24479 SDValue NewChain = LoLd.getValue(1);
24480 if (TokenFactorIndex != -1) {
24481 Ops.push_back(LoLd);
24482 Ops.push_back(HiLd);
24483 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24486 LoAddr = St->getBasePtr();
24487 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24488 DAG.getConstant(4, MVT::i32));
24490 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24491 St->getPointerInfo(),
24492 St->isVolatile(), St->isNonTemporal(),
24493 St->getAlignment());
24494 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24495 St->getPointerInfo().getWithOffset(4),
24497 St->isNonTemporal(),
24498 MinAlign(St->getAlignment(), 4));
24499 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24504 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24505 /// and return the operands for the horizontal operation in LHS and RHS. A
24506 /// horizontal operation performs the binary operation on successive elements
24507 /// of its first operand, then on successive elements of its second operand,
24508 /// returning the resulting values in a vector. For example, if
24509 /// A = < float a0, float a1, float a2, float a3 >
24511 /// B = < float b0, float b1, float b2, float b3 >
24512 /// then the result of doing a horizontal operation on A and B is
24513 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24514 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24515 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24516 /// set to A, RHS to B, and the routine returns 'true'.
24517 /// Note that the binary operation should have the property that if one of the
24518 /// operands is UNDEF then the result is UNDEF.
24519 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24520 // Look for the following pattern: if
24521 // A = < float a0, float a1, float a2, float a3 >
24522 // B = < float b0, float b1, float b2, float b3 >
24524 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24525 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24526 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24527 // which is A horizontal-op B.
24529 // At least one of the operands should be a vector shuffle.
24530 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24531 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24534 MVT VT = LHS.getSimpleValueType();
24536 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24537 "Unsupported vector type for horizontal add/sub");
24539 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24540 // operate independently on 128-bit lanes.
24541 unsigned NumElts = VT.getVectorNumElements();
24542 unsigned NumLanes = VT.getSizeInBits()/128;
24543 unsigned NumLaneElts = NumElts / NumLanes;
24544 assert((NumLaneElts % 2 == 0) &&
24545 "Vector type should have an even number of elements in each lane");
24546 unsigned HalfLaneElts = NumLaneElts/2;
24548 // View LHS in the form
24549 // LHS = VECTOR_SHUFFLE A, B, LMask
24550 // If LHS is not a shuffle then pretend it is the shuffle
24551 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24552 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24555 SmallVector<int, 16> LMask(NumElts);
24556 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24557 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24558 A = LHS.getOperand(0);
24559 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24560 B = LHS.getOperand(1);
24561 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24562 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24564 if (LHS.getOpcode() != ISD::UNDEF)
24566 for (unsigned i = 0; i != NumElts; ++i)
24570 // Likewise, view RHS in the form
24571 // RHS = VECTOR_SHUFFLE C, D, RMask
24573 SmallVector<int, 16> RMask(NumElts);
24574 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24575 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24576 C = RHS.getOperand(0);
24577 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24578 D = RHS.getOperand(1);
24579 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24580 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24582 if (RHS.getOpcode() != ISD::UNDEF)
24584 for (unsigned i = 0; i != NumElts; ++i)
24588 // Check that the shuffles are both shuffling the same vectors.
24589 if (!(A == C && B == D) && !(A == D && B == C))
24592 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24593 if (!A.getNode() && !B.getNode())
24596 // If A and B occur in reverse order in RHS, then "swap" them (which means
24597 // rewriting the mask).
24599 CommuteVectorShuffleMask(RMask, NumElts);
24601 // At this point LHS and RHS are equivalent to
24602 // LHS = VECTOR_SHUFFLE A, B, LMask
24603 // RHS = VECTOR_SHUFFLE A, B, RMask
24604 // Check that the masks correspond to performing a horizontal operation.
24605 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24606 for (unsigned i = 0; i != NumLaneElts; ++i) {
24607 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24609 // Ignore any UNDEF components.
24610 if (LIdx < 0 || RIdx < 0 ||
24611 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24612 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24615 // Check that successive elements are being operated on. If not, this is
24616 // not a horizontal operation.
24617 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24618 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24619 if (!(LIdx == Index && RIdx == Index + 1) &&
24620 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24625 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24626 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24630 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24631 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24632 const X86Subtarget *Subtarget) {
24633 EVT VT = N->getValueType(0);
24634 SDValue LHS = N->getOperand(0);
24635 SDValue RHS = N->getOperand(1);
24637 // Try to synthesize horizontal adds from adds of shuffles.
24638 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24639 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24640 isHorizontalBinOp(LHS, RHS, true))
24641 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24645 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24646 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24647 const X86Subtarget *Subtarget) {
24648 EVT VT = N->getValueType(0);
24649 SDValue LHS = N->getOperand(0);
24650 SDValue RHS = N->getOperand(1);
24652 // Try to synthesize horizontal subs from subs of shuffles.
24653 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24654 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24655 isHorizontalBinOp(LHS, RHS, false))
24656 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24660 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24661 /// X86ISD::FXOR nodes.
24662 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24663 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24664 // F[X]OR(0.0, x) -> x
24665 // F[X]OR(x, 0.0) -> x
24666 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24667 if (C->getValueAPF().isPosZero())
24668 return N->getOperand(1);
24669 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24670 if (C->getValueAPF().isPosZero())
24671 return N->getOperand(0);
24675 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24676 /// X86ISD::FMAX nodes.
24677 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24678 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24680 // Only perform optimizations if UnsafeMath is used.
24681 if (!DAG.getTarget().Options.UnsafeFPMath)
24684 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24685 // into FMINC and FMAXC, which are Commutative operations.
24686 unsigned NewOp = 0;
24687 switch (N->getOpcode()) {
24688 default: llvm_unreachable("unknown opcode");
24689 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24690 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24693 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24694 N->getOperand(0), N->getOperand(1));
24697 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24698 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24699 // FAND(0.0, x) -> 0.0
24700 // FAND(x, 0.0) -> 0.0
24701 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24702 if (C->getValueAPF().isPosZero())
24703 return N->getOperand(0);
24704 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24705 if (C->getValueAPF().isPosZero())
24706 return N->getOperand(1);
24710 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24711 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24712 // FANDN(x, 0.0) -> 0.0
24713 // FANDN(0.0, x) -> x
24714 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24715 if (C->getValueAPF().isPosZero())
24716 return N->getOperand(1);
24717 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24718 if (C->getValueAPF().isPosZero())
24719 return N->getOperand(1);
24723 static SDValue PerformBTCombine(SDNode *N,
24725 TargetLowering::DAGCombinerInfo &DCI) {
24726 // BT ignores high bits in the bit index operand.
24727 SDValue Op1 = N->getOperand(1);
24728 if (Op1.hasOneUse()) {
24729 unsigned BitWidth = Op1.getValueSizeInBits();
24730 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24731 APInt KnownZero, KnownOne;
24732 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24733 !DCI.isBeforeLegalizeOps());
24734 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24735 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24736 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24737 DCI.CommitTargetLoweringOpt(TLO);
24742 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24743 SDValue Op = N->getOperand(0);
24744 if (Op.getOpcode() == ISD::BITCAST)
24745 Op = Op.getOperand(0);
24746 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24747 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24748 VT.getVectorElementType().getSizeInBits() ==
24749 OpVT.getVectorElementType().getSizeInBits()) {
24750 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24755 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24756 const X86Subtarget *Subtarget) {
24757 EVT VT = N->getValueType(0);
24758 if (!VT.isVector())
24761 SDValue N0 = N->getOperand(0);
24762 SDValue N1 = N->getOperand(1);
24763 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24766 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24767 // both SSE and AVX2 since there is no sign-extended shift right
24768 // operation on a vector with 64-bit elements.
24769 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24770 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24771 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24772 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24773 SDValue N00 = N0.getOperand(0);
24775 // EXTLOAD has a better solution on AVX2,
24776 // it may be replaced with X86ISD::VSEXT node.
24777 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24778 if (!ISD::isNormalLoad(N00.getNode()))
24781 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24782 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24784 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24790 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24791 TargetLowering::DAGCombinerInfo &DCI,
24792 const X86Subtarget *Subtarget) {
24793 SDValue N0 = N->getOperand(0);
24794 EVT VT = N->getValueType(0);
24796 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24797 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24798 // This exposes the sext to the sdivrem lowering, so that it directly extends
24799 // from AH (which we otherwise need to do contortions to access).
24800 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24801 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24803 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24804 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24805 N0.getOperand(0), N0.getOperand(1));
24806 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24807 return R.getValue(1);
24810 if (!DCI.isBeforeLegalizeOps())
24813 if (!Subtarget->hasFp256())
24816 if (VT.isVector() && VT.getSizeInBits() == 256) {
24817 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24825 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24826 const X86Subtarget* Subtarget) {
24828 EVT VT = N->getValueType(0);
24830 // Let legalize expand this if it isn't a legal type yet.
24831 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24834 EVT ScalarVT = VT.getScalarType();
24835 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24836 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24839 SDValue A = N->getOperand(0);
24840 SDValue B = N->getOperand(1);
24841 SDValue C = N->getOperand(2);
24843 bool NegA = (A.getOpcode() == ISD::FNEG);
24844 bool NegB = (B.getOpcode() == ISD::FNEG);
24845 bool NegC = (C.getOpcode() == ISD::FNEG);
24847 // Negative multiplication when NegA xor NegB
24848 bool NegMul = (NegA != NegB);
24850 A = A.getOperand(0);
24852 B = B.getOperand(0);
24854 C = C.getOperand(0);
24858 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24860 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24862 return DAG.getNode(Opcode, dl, VT, A, B, C);
24865 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24866 TargetLowering::DAGCombinerInfo &DCI,
24867 const X86Subtarget *Subtarget) {
24868 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24869 // (and (i32 x86isd::setcc_carry), 1)
24870 // This eliminates the zext. This transformation is necessary because
24871 // ISD::SETCC is always legalized to i8.
24873 SDValue N0 = N->getOperand(0);
24874 EVT VT = N->getValueType(0);
24876 if (N0.getOpcode() == ISD::AND &&
24878 N0.getOperand(0).hasOneUse()) {
24879 SDValue N00 = N0.getOperand(0);
24880 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24881 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24882 if (!C || C->getZExtValue() != 1)
24884 return DAG.getNode(ISD::AND, dl, VT,
24885 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24886 N00.getOperand(0), N00.getOperand(1)),
24887 DAG.getConstant(1, VT));
24891 if (N0.getOpcode() == ISD::TRUNCATE &&
24893 N0.getOperand(0).hasOneUse()) {
24894 SDValue N00 = N0.getOperand(0);
24895 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24896 return DAG.getNode(ISD::AND, dl, VT,
24897 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24898 N00.getOperand(0), N00.getOperand(1)),
24899 DAG.getConstant(1, VT));
24902 if (VT.is256BitVector()) {
24903 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24908 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24909 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24910 // This exposes the zext to the udivrem lowering, so that it directly extends
24911 // from AH (which we otherwise need to do contortions to access).
24912 if (N0.getOpcode() == ISD::UDIVREM &&
24913 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24914 (VT == MVT::i32 || VT == MVT::i64)) {
24915 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24916 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24917 N0.getOperand(0), N0.getOperand(1));
24918 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24919 return R.getValue(1);
24925 // Optimize x == -y --> x+y == 0
24926 // x != -y --> x+y != 0
24927 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24928 const X86Subtarget* Subtarget) {
24929 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24930 SDValue LHS = N->getOperand(0);
24931 SDValue RHS = N->getOperand(1);
24932 EVT VT = N->getValueType(0);
24935 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24936 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24937 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24938 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24939 LHS.getValueType(), RHS, LHS.getOperand(1));
24940 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24941 addV, DAG.getConstant(0, addV.getValueType()), CC);
24943 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24944 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24945 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24946 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24947 RHS.getValueType(), LHS, RHS.getOperand(1));
24948 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24949 addV, DAG.getConstant(0, addV.getValueType()), CC);
24952 if (VT.getScalarType() == MVT::i1) {
24953 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24954 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24955 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24956 if (!IsSEXT0 && !IsVZero0)
24958 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24959 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24960 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24962 if (!IsSEXT1 && !IsVZero1)
24965 if (IsSEXT0 && IsVZero1) {
24966 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24967 if (CC == ISD::SETEQ)
24968 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24969 return LHS.getOperand(0);
24971 if (IsSEXT1 && IsVZero0) {
24972 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24973 if (CC == ISD::SETEQ)
24974 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24975 return RHS.getOperand(0);
24982 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24983 const X86Subtarget *Subtarget) {
24985 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24986 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24987 "X86insertps is only defined for v4x32");
24989 SDValue Ld = N->getOperand(1);
24990 if (MayFoldLoad(Ld)) {
24991 // Extract the countS bits from the immediate so we can get the proper
24992 // address when narrowing the vector load to a specific element.
24993 // When the second source op is a memory address, interps doesn't use
24994 // countS and just gets an f32 from that address.
24995 unsigned DestIndex =
24996 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24997 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25001 // Create this as a scalar to vector to match the instruction pattern.
25002 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25003 // countS bits are ignored when loading from memory on insertps, which
25004 // means we don't need to explicitly set them to 0.
25005 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25006 LoadScalarToVector, N->getOperand(2));
25009 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25010 // as "sbb reg,reg", since it can be extended without zext and produces
25011 // an all-ones bit which is more useful than 0/1 in some cases.
25012 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25015 return DAG.getNode(ISD::AND, DL, VT,
25016 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25017 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25018 DAG.getConstant(1, VT));
25019 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25020 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25021 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25022 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25025 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25026 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25027 TargetLowering::DAGCombinerInfo &DCI,
25028 const X86Subtarget *Subtarget) {
25030 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25031 SDValue EFLAGS = N->getOperand(1);
25033 if (CC == X86::COND_A) {
25034 // Try to convert COND_A into COND_B in an attempt to facilitate
25035 // materializing "setb reg".
25037 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25038 // cannot take an immediate as its first operand.
25040 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25041 EFLAGS.getValueType().isInteger() &&
25042 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25043 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25044 EFLAGS.getNode()->getVTList(),
25045 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25046 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25047 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25051 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25052 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25054 if (CC == X86::COND_B)
25055 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25059 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25060 if (Flags.getNode()) {
25061 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25062 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25068 // Optimize branch condition evaluation.
25070 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25071 TargetLowering::DAGCombinerInfo &DCI,
25072 const X86Subtarget *Subtarget) {
25074 SDValue Chain = N->getOperand(0);
25075 SDValue Dest = N->getOperand(1);
25076 SDValue EFLAGS = N->getOperand(3);
25077 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25081 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25082 if (Flags.getNode()) {
25083 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25084 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25091 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25092 SelectionDAG &DAG) {
25093 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25094 // optimize away operation when it's from a constant.
25096 // The general transformation is:
25097 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25098 // AND(VECTOR_CMP(x,y), constant2)
25099 // constant2 = UNARYOP(constant)
25101 // Early exit if this isn't a vector operation, the operand of the
25102 // unary operation isn't a bitwise AND, or if the sizes of the operations
25103 // aren't the same.
25104 EVT VT = N->getValueType(0);
25105 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25106 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25107 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25110 // Now check that the other operand of the AND is a constant. We could
25111 // make the transformation for non-constant splats as well, but it's unclear
25112 // that would be a benefit as it would not eliminate any operations, just
25113 // perform one more step in scalar code before moving to the vector unit.
25114 if (BuildVectorSDNode *BV =
25115 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25116 // Bail out if the vector isn't a constant.
25117 if (!BV->isConstant())
25120 // Everything checks out. Build up the new and improved node.
25122 EVT IntVT = BV->getValueType(0);
25123 // Create a new constant of the appropriate type for the transformed
25125 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25126 // The AND node needs bitcasts to/from an integer vector type around it.
25127 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25128 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25129 N->getOperand(0)->getOperand(0), MaskConst);
25130 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25137 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25138 const X86TargetLowering *XTLI) {
25139 // First try to optimize away the conversion entirely when it's
25140 // conditionally from a constant. Vectors only.
25141 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25142 if (Res != SDValue())
25145 // Now move on to more general possibilities.
25146 SDValue Op0 = N->getOperand(0);
25147 EVT InVT = Op0->getValueType(0);
25149 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25150 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25152 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25153 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25154 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25157 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25158 // a 32-bit target where SSE doesn't support i64->FP operations.
25159 if (Op0.getOpcode() == ISD::LOAD) {
25160 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25161 EVT VT = Ld->getValueType(0);
25162 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25163 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25164 !XTLI->getSubtarget()->is64Bit() &&
25166 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25167 Ld->getChain(), Op0, DAG);
25168 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25175 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25176 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25177 X86TargetLowering::DAGCombinerInfo &DCI) {
25178 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25179 // the result is either zero or one (depending on the input carry bit).
25180 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25181 if (X86::isZeroNode(N->getOperand(0)) &&
25182 X86::isZeroNode(N->getOperand(1)) &&
25183 // We don't have a good way to replace an EFLAGS use, so only do this when
25185 SDValue(N, 1).use_empty()) {
25187 EVT VT = N->getValueType(0);
25188 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25189 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25190 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25191 DAG.getConstant(X86::COND_B,MVT::i8),
25193 DAG.getConstant(1, VT));
25194 return DCI.CombineTo(N, Res1, CarryOut);
25200 // fold (add Y, (sete X, 0)) -> adc 0, Y
25201 // (add Y, (setne X, 0)) -> sbb -1, Y
25202 // (sub (sete X, 0), Y) -> sbb 0, Y
25203 // (sub (setne X, 0), Y) -> adc -1, Y
25204 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25207 // Look through ZExts.
25208 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25209 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25212 SDValue SetCC = Ext.getOperand(0);
25213 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25216 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25217 if (CC != X86::COND_E && CC != X86::COND_NE)
25220 SDValue Cmp = SetCC.getOperand(1);
25221 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25222 !X86::isZeroNode(Cmp.getOperand(1)) ||
25223 !Cmp.getOperand(0).getValueType().isInteger())
25226 SDValue CmpOp0 = Cmp.getOperand(0);
25227 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25228 DAG.getConstant(1, CmpOp0.getValueType()));
25230 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25231 if (CC == X86::COND_NE)
25232 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25233 DL, OtherVal.getValueType(), OtherVal,
25234 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25235 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25236 DL, OtherVal.getValueType(), OtherVal,
25237 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25240 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25241 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25242 const X86Subtarget *Subtarget) {
25243 EVT VT = N->getValueType(0);
25244 SDValue Op0 = N->getOperand(0);
25245 SDValue Op1 = N->getOperand(1);
25247 // Try to synthesize horizontal adds from adds of shuffles.
25248 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25249 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25250 isHorizontalBinOp(Op0, Op1, true))
25251 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25253 return OptimizeConditionalInDecrement(N, DAG);
25256 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25257 const X86Subtarget *Subtarget) {
25258 SDValue Op0 = N->getOperand(0);
25259 SDValue Op1 = N->getOperand(1);
25261 // X86 can't encode an immediate LHS of a sub. See if we can push the
25262 // negation into a preceding instruction.
25263 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25264 // If the RHS of the sub is a XOR with one use and a constant, invert the
25265 // immediate. Then add one to the LHS of the sub so we can turn
25266 // X-Y -> X+~Y+1, saving one register.
25267 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25268 isa<ConstantSDNode>(Op1.getOperand(1))) {
25269 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25270 EVT VT = Op0.getValueType();
25271 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25273 DAG.getConstant(~XorC, VT));
25274 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25275 DAG.getConstant(C->getAPIntValue()+1, VT));
25279 // Try to synthesize horizontal adds from adds of shuffles.
25280 EVT VT = N->getValueType(0);
25281 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25282 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25283 isHorizontalBinOp(Op0, Op1, true))
25284 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25286 return OptimizeConditionalInDecrement(N, DAG);
25289 /// performVZEXTCombine - Performs build vector combines
25290 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25291 TargetLowering::DAGCombinerInfo &DCI,
25292 const X86Subtarget *Subtarget) {
25294 MVT VT = N->getSimpleValueType(0);
25295 SDValue Op = N->getOperand(0);
25296 MVT OpVT = Op.getSimpleValueType();
25297 MVT OpEltVT = OpVT.getVectorElementType();
25298 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25300 // (vzext (bitcast (vzext (x)) -> (vzext x)
25302 while (V.getOpcode() == ISD::BITCAST)
25303 V = V.getOperand(0);
25305 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25306 MVT InnerVT = V.getSimpleValueType();
25307 MVT InnerEltVT = InnerVT.getVectorElementType();
25309 // If the element sizes match exactly, we can just do one larger vzext. This
25310 // is always an exact type match as vzext operates on integer types.
25311 if (OpEltVT == InnerEltVT) {
25312 assert(OpVT == InnerVT && "Types must match for vzext!");
25313 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25316 // The only other way we can combine them is if only a single element of the
25317 // inner vzext is used in the input to the outer vzext.
25318 if (InnerEltVT.getSizeInBits() < InputBits)
25321 // In this case, the inner vzext is completely dead because we're going to
25322 // only look at bits inside of the low element. Just do the outer vzext on
25323 // a bitcast of the input to the inner.
25324 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25325 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25328 // Check if we can bypass extracting and re-inserting an element of an input
25329 // vector. Essentialy:
25330 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25331 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25332 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25333 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25334 SDValue ExtractedV = V.getOperand(0);
25335 SDValue OrigV = ExtractedV.getOperand(0);
25336 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25337 if (ExtractIdx->getZExtValue() == 0) {
25338 MVT OrigVT = OrigV.getSimpleValueType();
25339 // Extract a subvector if necessary...
25340 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25341 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25342 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25343 OrigVT.getVectorNumElements() / Ratio);
25344 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25345 DAG.getIntPtrConstant(0));
25347 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25348 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25355 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25356 DAGCombinerInfo &DCI) const {
25357 SelectionDAG &DAG = DCI.DAG;
25358 switch (N->getOpcode()) {
25360 case ISD::EXTRACT_VECTOR_ELT:
25361 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25364 case X86ISD::SHRUNKBLEND:
25365 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25366 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25367 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25368 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25369 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25370 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25373 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25374 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25375 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25376 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25377 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25378 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25379 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25380 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25381 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25383 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25385 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25386 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25387 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25388 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25389 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25390 case ISD::ANY_EXTEND:
25391 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25392 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25393 case ISD::SIGN_EXTEND_INREG:
25394 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25395 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25396 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25397 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25398 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25399 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25400 case X86ISD::SHUFP: // Handle all target specific shuffles
25401 case X86ISD::PALIGNR:
25402 case X86ISD::UNPCKH:
25403 case X86ISD::UNPCKL:
25404 case X86ISD::MOVHLPS:
25405 case X86ISD::MOVLHPS:
25406 case X86ISD::PSHUFB:
25407 case X86ISD::PSHUFD:
25408 case X86ISD::PSHUFHW:
25409 case X86ISD::PSHUFLW:
25410 case X86ISD::MOVSS:
25411 case X86ISD::MOVSD:
25412 case X86ISD::VPERMILPI:
25413 case X86ISD::VPERM2X128:
25414 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25415 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25416 case ISD::INTRINSIC_WO_CHAIN:
25417 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25418 case X86ISD::INSERTPS:
25419 return PerformINSERTPSCombine(N, DAG, Subtarget);
25420 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25426 /// isTypeDesirableForOp - Return true if the target has native support for
25427 /// the specified value type and it is 'desirable' to use the type for the
25428 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25429 /// instruction encodings are longer and some i16 instructions are slow.
25430 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25431 if (!isTypeLegal(VT))
25433 if (VT != MVT::i16)
25440 case ISD::SIGN_EXTEND:
25441 case ISD::ZERO_EXTEND:
25442 case ISD::ANY_EXTEND:
25455 /// IsDesirableToPromoteOp - This method query the target whether it is
25456 /// beneficial for dag combiner to promote the specified node. If true, it
25457 /// should return the desired promotion type by reference.
25458 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25459 EVT VT = Op.getValueType();
25460 if (VT != MVT::i16)
25463 bool Promote = false;
25464 bool Commute = false;
25465 switch (Op.getOpcode()) {
25468 LoadSDNode *LD = cast<LoadSDNode>(Op);
25469 // If the non-extending load has a single use and it's not live out, then it
25470 // might be folded.
25471 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25472 Op.hasOneUse()*/) {
25473 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25474 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25475 // The only case where we'd want to promote LOAD (rather then it being
25476 // promoted as an operand is when it's only use is liveout.
25477 if (UI->getOpcode() != ISD::CopyToReg)
25484 case ISD::SIGN_EXTEND:
25485 case ISD::ZERO_EXTEND:
25486 case ISD::ANY_EXTEND:
25491 SDValue N0 = Op.getOperand(0);
25492 // Look out for (store (shl (load), x)).
25493 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25506 SDValue N0 = Op.getOperand(0);
25507 SDValue N1 = Op.getOperand(1);
25508 if (!Commute && MayFoldLoad(N1))
25510 // Avoid disabling potential load folding opportunities.
25511 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25513 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25523 //===----------------------------------------------------------------------===//
25524 // X86 Inline Assembly Support
25525 //===----------------------------------------------------------------------===//
25528 // Helper to match a string separated by whitespace.
25529 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25530 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25532 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25533 StringRef piece(*args[i]);
25534 if (!s.startswith(piece)) // Check if the piece matches.
25537 s = s.substr(piece.size());
25538 StringRef::size_type pos = s.find_first_not_of(" \t");
25539 if (pos == 0) // We matched a prefix.
25547 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25550 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25552 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25553 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25554 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25555 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25557 if (AsmPieces.size() == 3)
25559 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25566 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25567 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25569 std::string AsmStr = IA->getAsmString();
25571 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25572 if (!Ty || Ty->getBitWidth() % 16 != 0)
25575 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25576 SmallVector<StringRef, 4> AsmPieces;
25577 SplitString(AsmStr, AsmPieces, ";\n");
25579 switch (AsmPieces.size()) {
25580 default: return false;
25582 // FIXME: this should verify that we are targeting a 486 or better. If not,
25583 // we will turn this bswap into something that will be lowered to logical
25584 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25585 // lower so don't worry about this.
25587 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25588 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25589 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25590 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25591 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25592 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25593 // No need to check constraints, nothing other than the equivalent of
25594 // "=r,0" would be valid here.
25595 return IntrinsicLowering::LowerToByteSwap(CI);
25598 // rorw $$8, ${0:w} --> llvm.bswap.i16
25599 if (CI->getType()->isIntegerTy(16) &&
25600 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25601 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25602 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25604 const std::string &ConstraintsStr = IA->getConstraintString();
25605 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25606 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25607 if (clobbersFlagRegisters(AsmPieces))
25608 return IntrinsicLowering::LowerToByteSwap(CI);
25612 if (CI->getType()->isIntegerTy(32) &&
25613 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25614 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25615 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25616 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25618 const std::string &ConstraintsStr = IA->getConstraintString();
25619 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25620 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25621 if (clobbersFlagRegisters(AsmPieces))
25622 return IntrinsicLowering::LowerToByteSwap(CI);
25625 if (CI->getType()->isIntegerTy(64)) {
25626 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25627 if (Constraints.size() >= 2 &&
25628 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25629 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25630 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25631 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25632 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25633 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25634 return IntrinsicLowering::LowerToByteSwap(CI);
25642 /// getConstraintType - Given a constraint letter, return the type of
25643 /// constraint it is for this target.
25644 X86TargetLowering::ConstraintType
25645 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25646 if (Constraint.size() == 1) {
25647 switch (Constraint[0]) {
25658 return C_RegisterClass;
25682 return TargetLowering::getConstraintType(Constraint);
25685 /// Examine constraint type and operand type and determine a weight value.
25686 /// This object must already have been set up with the operand type
25687 /// and the current alternative constraint selected.
25688 TargetLowering::ConstraintWeight
25689 X86TargetLowering::getSingleConstraintMatchWeight(
25690 AsmOperandInfo &info, const char *constraint) const {
25691 ConstraintWeight weight = CW_Invalid;
25692 Value *CallOperandVal = info.CallOperandVal;
25693 // If we don't have a value, we can't do a match,
25694 // but allow it at the lowest weight.
25695 if (!CallOperandVal)
25697 Type *type = CallOperandVal->getType();
25698 // Look at the constraint type.
25699 switch (*constraint) {
25701 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25712 if (CallOperandVal->getType()->isIntegerTy())
25713 weight = CW_SpecificReg;
25718 if (type->isFloatingPointTy())
25719 weight = CW_SpecificReg;
25722 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25723 weight = CW_SpecificReg;
25727 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25728 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25729 weight = CW_Register;
25732 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25733 if (C->getZExtValue() <= 31)
25734 weight = CW_Constant;
25738 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25739 if (C->getZExtValue() <= 63)
25740 weight = CW_Constant;
25744 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25745 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25746 weight = CW_Constant;
25750 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25751 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25752 weight = CW_Constant;
25756 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25757 if (C->getZExtValue() <= 3)
25758 weight = CW_Constant;
25762 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25763 if (C->getZExtValue() <= 0xff)
25764 weight = CW_Constant;
25769 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25770 weight = CW_Constant;
25774 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25775 if ((C->getSExtValue() >= -0x80000000LL) &&
25776 (C->getSExtValue() <= 0x7fffffffLL))
25777 weight = CW_Constant;
25781 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25782 if (C->getZExtValue() <= 0xffffffff)
25783 weight = CW_Constant;
25790 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25791 /// with another that has more specific requirements based on the type of the
25792 /// corresponding operand.
25793 const char *X86TargetLowering::
25794 LowerXConstraint(EVT ConstraintVT) const {
25795 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25796 // 'f' like normal targets.
25797 if (ConstraintVT.isFloatingPoint()) {
25798 if (Subtarget->hasSSE2())
25800 if (Subtarget->hasSSE1())
25804 return TargetLowering::LowerXConstraint(ConstraintVT);
25807 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25808 /// vector. If it is invalid, don't add anything to Ops.
25809 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25810 std::string &Constraint,
25811 std::vector<SDValue>&Ops,
25812 SelectionDAG &DAG) const {
25815 // Only support length 1 constraints for now.
25816 if (Constraint.length() > 1) return;
25818 char ConstraintLetter = Constraint[0];
25819 switch (ConstraintLetter) {
25822 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25823 if (C->getZExtValue() <= 31) {
25824 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25830 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25831 if (C->getZExtValue() <= 63) {
25832 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25838 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25839 if (isInt<8>(C->getSExtValue())) {
25840 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25846 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25847 if (C->getZExtValue() <= 255) {
25848 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25854 // 32-bit signed value
25855 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25856 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25857 C->getSExtValue())) {
25858 // Widen to 64 bits here to get it sign extended.
25859 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25862 // FIXME gcc accepts some relocatable values here too, but only in certain
25863 // memory models; it's complicated.
25868 // 32-bit unsigned value
25869 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25870 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25871 C->getZExtValue())) {
25872 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25876 // FIXME gcc accepts some relocatable values here too, but only in certain
25877 // memory models; it's complicated.
25881 // Literal immediates are always ok.
25882 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25883 // Widen to 64 bits here to get it sign extended.
25884 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25888 // In any sort of PIC mode addresses need to be computed at runtime by
25889 // adding in a register or some sort of table lookup. These can't
25890 // be used as immediates.
25891 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25894 // If we are in non-pic codegen mode, we allow the address of a global (with
25895 // an optional displacement) to be used with 'i'.
25896 GlobalAddressSDNode *GA = nullptr;
25897 int64_t Offset = 0;
25899 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25901 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25902 Offset += GA->getOffset();
25904 } else if (Op.getOpcode() == ISD::ADD) {
25905 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25906 Offset += C->getZExtValue();
25907 Op = Op.getOperand(0);
25910 } else if (Op.getOpcode() == ISD::SUB) {
25911 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25912 Offset += -C->getZExtValue();
25913 Op = Op.getOperand(0);
25918 // Otherwise, this isn't something we can handle, reject it.
25922 const GlobalValue *GV = GA->getGlobal();
25923 // If we require an extra load to get this address, as in PIC mode, we
25924 // can't accept it.
25925 if (isGlobalStubReference(
25926 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25929 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25930 GA->getValueType(0), Offset);
25935 if (Result.getNode()) {
25936 Ops.push_back(Result);
25939 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25942 std::pair<unsigned, const TargetRegisterClass*>
25943 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25945 // First, see if this is a constraint that directly corresponds to an LLVM
25947 if (Constraint.size() == 1) {
25948 // GCC Constraint Letters
25949 switch (Constraint[0]) {
25951 // TODO: Slight differences here in allocation order and leaving
25952 // RIP in the class. Do they matter any more here than they do
25953 // in the normal allocation?
25954 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25955 if (Subtarget->is64Bit()) {
25956 if (VT == MVT::i32 || VT == MVT::f32)
25957 return std::make_pair(0U, &X86::GR32RegClass);
25958 if (VT == MVT::i16)
25959 return std::make_pair(0U, &X86::GR16RegClass);
25960 if (VT == MVT::i8 || VT == MVT::i1)
25961 return std::make_pair(0U, &X86::GR8RegClass);
25962 if (VT == MVT::i64 || VT == MVT::f64)
25963 return std::make_pair(0U, &X86::GR64RegClass);
25966 // 32-bit fallthrough
25967 case 'Q': // Q_REGS
25968 if (VT == MVT::i32 || VT == MVT::f32)
25969 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25970 if (VT == MVT::i16)
25971 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25972 if (VT == MVT::i8 || VT == MVT::i1)
25973 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25974 if (VT == MVT::i64)
25975 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25977 case 'r': // GENERAL_REGS
25978 case 'l': // INDEX_REGS
25979 if (VT == MVT::i8 || VT == MVT::i1)
25980 return std::make_pair(0U, &X86::GR8RegClass);
25981 if (VT == MVT::i16)
25982 return std::make_pair(0U, &X86::GR16RegClass);
25983 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25984 return std::make_pair(0U, &X86::GR32RegClass);
25985 return std::make_pair(0U, &X86::GR64RegClass);
25986 case 'R': // LEGACY_REGS
25987 if (VT == MVT::i8 || VT == MVT::i1)
25988 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25989 if (VT == MVT::i16)
25990 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25991 if (VT == MVT::i32 || !Subtarget->is64Bit())
25992 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25993 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25994 case 'f': // FP Stack registers.
25995 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25996 // value to the correct fpstack register class.
25997 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25998 return std::make_pair(0U, &X86::RFP32RegClass);
25999 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26000 return std::make_pair(0U, &X86::RFP64RegClass);
26001 return std::make_pair(0U, &X86::RFP80RegClass);
26002 case 'y': // MMX_REGS if MMX allowed.
26003 if (!Subtarget->hasMMX()) break;
26004 return std::make_pair(0U, &X86::VR64RegClass);
26005 case 'Y': // SSE_REGS if SSE2 allowed
26006 if (!Subtarget->hasSSE2()) break;
26008 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26009 if (!Subtarget->hasSSE1()) break;
26011 switch (VT.SimpleTy) {
26013 // Scalar SSE types.
26016 return std::make_pair(0U, &X86::FR32RegClass);
26019 return std::make_pair(0U, &X86::FR64RegClass);
26027 return std::make_pair(0U, &X86::VR128RegClass);
26035 return std::make_pair(0U, &X86::VR256RegClass);
26040 return std::make_pair(0U, &X86::VR512RegClass);
26046 // Use the default implementation in TargetLowering to convert the register
26047 // constraint into a member of a register class.
26048 std::pair<unsigned, const TargetRegisterClass*> Res;
26049 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26051 // Not found as a standard register?
26053 // Map st(0) -> st(7) -> ST0
26054 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26055 tolower(Constraint[1]) == 's' &&
26056 tolower(Constraint[2]) == 't' &&
26057 Constraint[3] == '(' &&
26058 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26059 Constraint[5] == ')' &&
26060 Constraint[6] == '}') {
26062 Res.first = X86::FP0+Constraint[4]-'0';
26063 Res.second = &X86::RFP80RegClass;
26067 // GCC allows "st(0)" to be called just plain "st".
26068 if (StringRef("{st}").equals_lower(Constraint)) {
26069 Res.first = X86::FP0;
26070 Res.second = &X86::RFP80RegClass;
26075 if (StringRef("{flags}").equals_lower(Constraint)) {
26076 Res.first = X86::EFLAGS;
26077 Res.second = &X86::CCRRegClass;
26081 // 'A' means EAX + EDX.
26082 if (Constraint == "A") {
26083 Res.first = X86::EAX;
26084 Res.second = &X86::GR32_ADRegClass;
26090 // Otherwise, check to see if this is a register class of the wrong value
26091 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26092 // turn into {ax},{dx}.
26093 if (Res.second->hasType(VT))
26094 return Res; // Correct type already, nothing to do.
26096 // All of the single-register GCC register classes map their values onto
26097 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26098 // really want an 8-bit or 32-bit register, map to the appropriate register
26099 // class and return the appropriate register.
26100 if (Res.second == &X86::GR16RegClass) {
26101 if (VT == MVT::i8 || VT == MVT::i1) {
26102 unsigned DestReg = 0;
26103 switch (Res.first) {
26105 case X86::AX: DestReg = X86::AL; break;
26106 case X86::DX: DestReg = X86::DL; break;
26107 case X86::CX: DestReg = X86::CL; break;
26108 case X86::BX: DestReg = X86::BL; break;
26111 Res.first = DestReg;
26112 Res.second = &X86::GR8RegClass;
26114 } else if (VT == MVT::i32 || VT == MVT::f32) {
26115 unsigned DestReg = 0;
26116 switch (Res.first) {
26118 case X86::AX: DestReg = X86::EAX; break;
26119 case X86::DX: DestReg = X86::EDX; break;
26120 case X86::CX: DestReg = X86::ECX; break;
26121 case X86::BX: DestReg = X86::EBX; break;
26122 case X86::SI: DestReg = X86::ESI; break;
26123 case X86::DI: DestReg = X86::EDI; break;
26124 case X86::BP: DestReg = X86::EBP; break;
26125 case X86::SP: DestReg = X86::ESP; break;
26128 Res.first = DestReg;
26129 Res.second = &X86::GR32RegClass;
26131 } else if (VT == MVT::i64 || VT == MVT::f64) {
26132 unsigned DestReg = 0;
26133 switch (Res.first) {
26135 case X86::AX: DestReg = X86::RAX; break;
26136 case X86::DX: DestReg = X86::RDX; break;
26137 case X86::CX: DestReg = X86::RCX; break;
26138 case X86::BX: DestReg = X86::RBX; break;
26139 case X86::SI: DestReg = X86::RSI; break;
26140 case X86::DI: DestReg = X86::RDI; break;
26141 case X86::BP: DestReg = X86::RBP; break;
26142 case X86::SP: DestReg = X86::RSP; break;
26145 Res.first = DestReg;
26146 Res.second = &X86::GR64RegClass;
26149 } else if (Res.second == &X86::FR32RegClass ||
26150 Res.second == &X86::FR64RegClass ||
26151 Res.second == &X86::VR128RegClass ||
26152 Res.second == &X86::VR256RegClass ||
26153 Res.second == &X86::FR32XRegClass ||
26154 Res.second == &X86::FR64XRegClass ||
26155 Res.second == &X86::VR128XRegClass ||
26156 Res.second == &X86::VR256XRegClass ||
26157 Res.second == &X86::VR512RegClass) {
26158 // Handle references to XMM physical registers that got mapped into the
26159 // wrong class. This can happen with constraints like {xmm0} where the
26160 // target independent register mapper will just pick the first match it can
26161 // find, ignoring the required type.
26163 if (VT == MVT::f32 || VT == MVT::i32)
26164 Res.second = &X86::FR32RegClass;
26165 else if (VT == MVT::f64 || VT == MVT::i64)
26166 Res.second = &X86::FR64RegClass;
26167 else if (X86::VR128RegClass.hasType(VT))
26168 Res.second = &X86::VR128RegClass;
26169 else if (X86::VR256RegClass.hasType(VT))
26170 Res.second = &X86::VR256RegClass;
26171 else if (X86::VR512RegClass.hasType(VT))
26172 Res.second = &X86::VR512RegClass;
26178 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26180 // Scaling factors are not free at all.
26181 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26182 // will take 2 allocations in the out of order engine instead of 1
26183 // for plain addressing mode, i.e. inst (reg1).
26185 // vaddps (%rsi,%drx), %ymm0, %ymm1
26186 // Requires two allocations (one for the load, one for the computation)
26188 // vaddps (%rsi), %ymm0, %ymm1
26189 // Requires just 1 allocation, i.e., freeing allocations for other operations
26190 // and having less micro operations to execute.
26192 // For some X86 architectures, this is even worse because for instance for
26193 // stores, the complex addressing mode forces the instruction to use the
26194 // "load" ports instead of the dedicated "store" port.
26195 // E.g., on Haswell:
26196 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26197 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26198 if (isLegalAddressingMode(AM, Ty))
26199 // Scale represents reg2 * scale, thus account for 1
26200 // as soon as we use a second register.
26201 return AM.Scale != 0;
26205 bool X86TargetLowering::isTargetFTOL() const {
26206 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();