1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit bounday. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
177 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
178 unsigned IdxVal, SelectionDAG &DAG,
180 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
181 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
184 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
185 /// instructions. This is used because creating CONCAT_VECTOR nodes of
186 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
187 /// large BUILD_VECTORS.
188 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
195 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
196 unsigned NumElems, SelectionDAG &DAG,
198 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
199 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
202 // FIXME: This should stop caching the target machine as soon as
203 // we can remove resetOperationActions et al.
204 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
205 : TargetLowering(TM) {
206 Subtarget = &TM.getSubtarget<X86Subtarget>();
207 X86ScalarSSEf64 = Subtarget->hasSSE2();
208 X86ScalarSSEf32 = Subtarget->hasSSE1();
209 TD = getDataLayout();
211 resetOperationActions();
214 void X86TargetLowering::resetOperationActions() {
215 const TargetMachine &TM = getTargetMachine();
216 static bool FirstTimeThrough = true;
218 // If none of the target options have changed, then we don't need to reset the
219 // operation actions.
220 if (!FirstTimeThrough && TO == TM.Options) return;
222 if (!FirstTimeThrough) {
223 // Reinitialize the actions.
225 FirstTimeThrough = false;
230 // Set up the TargetLowering object.
231 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
233 // X86 is weird, it always uses i8 for shift amounts and setcc results.
234 setBooleanContents(ZeroOrOneBooleanContent);
235 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
236 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
238 // For 64-bit since we have so many registers use the ILP scheduler, for
239 // 32-bit code use the register pressure specific scheduling.
240 // For Atom, always use ILP scheduling.
241 if (Subtarget->isAtom())
242 setSchedulingPreference(Sched::ILP);
243 else if (Subtarget->is64Bit())
244 setSchedulingPreference(Sched::ILP);
246 setSchedulingPreference(Sched::RegPressure);
247 const X86RegisterInfo *RegInfo =
248 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
249 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
251 // Bypass expensive divides on Atom when compiling with O2
252 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
253 addBypassSlowDiv(32, 8);
254 if (Subtarget->is64Bit())
255 addBypassSlowDiv(64, 16);
258 if (Subtarget->isTargetKnownWindowsMSVC()) {
259 // Setup Windows compiler runtime calls.
260 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
261 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
262 setLibcallName(RTLIB::SREM_I64, "_allrem");
263 setLibcallName(RTLIB::UREM_I64, "_aullrem");
264 setLibcallName(RTLIB::MUL_I64, "_allmul");
265 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
266 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
271 // The _ftol2 runtime function has an unusual calling conv, which
272 // is modeled by a special pseudo-instruction.
273 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
274 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
276 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
279 if (Subtarget->isTargetDarwin()) {
280 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
281 setUseUnderscoreSetJmp(false);
282 setUseUnderscoreLongJmp(false);
283 } else if (Subtarget->isTargetWindowsGNU()) {
284 // MS runtime is weird: it exports _setjmp, but longjmp!
285 setUseUnderscoreSetJmp(true);
286 setUseUnderscoreLongJmp(false);
288 setUseUnderscoreSetJmp(true);
289 setUseUnderscoreLongJmp(true);
292 // Set up the register classes.
293 addRegisterClass(MVT::i8, &X86::GR8RegClass);
294 addRegisterClass(MVT::i16, &X86::GR16RegClass);
295 addRegisterClass(MVT::i32, &X86::GR32RegClass);
296 if (Subtarget->is64Bit())
297 addRegisterClass(MVT::i64, &X86::GR64RegClass);
299 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
301 // We don't accept any truncstore of integer registers.
302 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
303 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
304 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
305 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
306 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
307 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
309 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
311 // SETOEQ and SETUNE require checking two conditions.
312 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
313 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
314 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
315 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
317 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
319 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
321 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
322 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
325 if (Subtarget->is64Bit()) {
326 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 } else if (!TM.Options.UseSoftFloat) {
329 // We have an algorithm for SSE2->double, and we turn this into a
330 // 64-bit FILD followed by conditional FADD for other targets.
331 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
332 // We have an algorithm for SSE2, and we turn this into a 64-bit
333 // FILD for other targets.
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
337 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
339 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
342 if (!TM.Options.UseSoftFloat) {
343 // SSE has no i16 to fp conversion, only i32
344 if (X86ScalarSSEf32) {
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
346 // f32 and f64 cases are Legal, f80 case is not
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
357 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
358 // are Legal, f80 is custom lowered.
359 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
360 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
362 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
364 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
367 if (X86ScalarSSEf32) {
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
369 // f32 and f64 cases are Legal, f80 case is not
370 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
376 // Handle FP_TO_UINT by promoting the destination to a larger signed
378 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
379 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
382 if (Subtarget->is64Bit()) {
383 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
384 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
385 } else if (!TM.Options.UseSoftFloat) {
386 // Since AVX is a superset of SSE3, only check for SSE here.
387 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
388 // Expand FP_TO_UINT into a select.
389 // FIXME: We would like to use a Custom expander here eventually to do
390 // the optimal thing for SSE vs. the default expansion in the legalizer.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
393 // With SSE3 we can use fisttpll to convert to a signed i64; without
394 // SSE, we're stuck with a fistpll.
395 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
398 if (isTargetFTOL()) {
399 // Use the _ftol2 runtime function, which has a pseudo-instruction
400 // to handle its weird calling convention.
401 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
404 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
405 if (!X86ScalarSSEf64) {
406 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
407 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
408 if (Subtarget->is64Bit()) {
409 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
410 // Without SSE, i64->f64 goes through memory.
411 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
415 // Scalar integer divide and remainder are lowered to use operations that
416 // produce two results, to match the available instructions. This exposes
417 // the two-result form to trivial CSE, which is able to combine x/y and x%y
418 // into a single instruction.
420 // Scalar integer multiply-high is also lowered to use two-result
421 // operations, to match the available instructions. However, plain multiply
422 // (low) operations are left as Legal, as there are single-result
423 // instructions for this in x86. Using the two-result multiply instructions
424 // when both high and low results are needed must be arranged by dagcombine.
425 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
427 setOperationAction(ISD::MULHS, VT, Expand);
428 setOperationAction(ISD::MULHU, VT, Expand);
429 setOperationAction(ISD::SDIV, VT, Expand);
430 setOperationAction(ISD::UDIV, VT, Expand);
431 setOperationAction(ISD::SREM, VT, Expand);
432 setOperationAction(ISD::UREM, VT, Expand);
434 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
435 setOperationAction(ISD::ADDC, VT, Custom);
436 setOperationAction(ISD::ADDE, VT, Custom);
437 setOperationAction(ISD::SUBC, VT, Custom);
438 setOperationAction(ISD::SUBE, VT, Custom);
441 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
442 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
443 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
444 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
445 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
446 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
449 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
457 if (Subtarget->is64Bit())
458 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
462 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
463 setOperationAction(ISD::FREM , MVT::f32 , Expand);
464 setOperationAction(ISD::FREM , MVT::f64 , Expand);
465 setOperationAction(ISD::FREM , MVT::f80 , Expand);
466 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
468 // Promote the i8 variants and force them on up to i32 which has a shorter
470 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
471 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
473 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
474 if (Subtarget->hasBMI()) {
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
477 if (Subtarget->is64Bit())
478 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
480 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
481 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
482 if (Subtarget->is64Bit())
483 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
486 if (Subtarget->hasLZCNT()) {
487 // When promoting the i8 variants, force them to i32 for a shorter
489 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
490 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
492 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
494 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
495 if (Subtarget->is64Bit())
496 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
498 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
499 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
500 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
504 if (Subtarget->is64Bit()) {
505 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
510 // Special handling for half-precision floating point conversions.
511 // If we don't have F16C support, then lower half float conversions
512 // into library calls.
513 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
514 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
515 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
518 // There's never any support for operations beyond MVT::f32.
519 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
520 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
521 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
522 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
524 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
525 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
527 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
529 if (Subtarget->hasPOPCNT()) {
530 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
532 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
533 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
534 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
535 if (Subtarget->is64Bit())
536 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
539 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
541 if (!Subtarget->hasMOVBE())
542 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
544 // These should be promoted to a larger select which is supported.
545 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
546 // X86 wants to expand cmov itself.
547 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
548 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
549 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
550 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
552 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
553 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
555 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
556 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
558 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
559 if (Subtarget->is64Bit()) {
560 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
563 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
564 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
565 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
566 // support continuation, user-level threading, and etc.. As a result, no
567 // other SjLj exception interfaces are implemented and please don't build
568 // your own exception handling based on them.
569 // LLVM/Clang supports zero-cost DWARF exception handling.
570 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
571 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
574 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
575 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
576 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
577 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
578 if (Subtarget->is64Bit())
579 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
580 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
581 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
582 if (Subtarget->is64Bit()) {
583 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
584 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
585 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
586 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
587 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
589 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
590 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
593 if (Subtarget->is64Bit()) {
594 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
595 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
596 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
599 if (Subtarget->hasSSE1())
600 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
602 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
604 // Expand certain atomics
605 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
607 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
608 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
609 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
612 if (Subtarget->hasCmpxchg16b()) {
613 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
616 // FIXME - use subtarget debug flags
617 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
618 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
619 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
622 if (Subtarget->is64Bit()) {
623 setExceptionPointerRegister(X86::RAX);
624 setExceptionSelectorRegister(X86::RDX);
626 setExceptionPointerRegister(X86::EAX);
627 setExceptionSelectorRegister(X86::EDX);
629 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
630 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
632 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
633 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
635 setOperationAction(ISD::TRAP, MVT::Other, Legal);
636 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
638 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
639 setOperationAction(ISD::VASTART , MVT::Other, Custom);
640 setOperationAction(ISD::VAEND , MVT::Other, Expand);
641 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
642 // TargetInfo::X86_64ABIBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Custom);
644 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
646 // TargetInfo::CharPtrBuiltinVaList
647 setOperationAction(ISD::VAARG , MVT::Other, Expand);
648 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
651 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
652 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
654 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
656 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
657 // f32 and f64 use SSE.
658 // Set up the FP register classes.
659 addRegisterClass(MVT::f32, &X86::FR32RegClass);
660 addRegisterClass(MVT::f64, &X86::FR64RegClass);
662 // Use ANDPD to simulate FABS.
663 setOperationAction(ISD::FABS , MVT::f64, Custom);
664 setOperationAction(ISD::FABS , MVT::f32, Custom);
666 // Use XORP to simulate FNEG.
667 setOperationAction(ISD::FNEG , MVT::f64, Custom);
668 setOperationAction(ISD::FNEG , MVT::f32, Custom);
670 // Use ANDPD and ORPD to simulate FCOPYSIGN.
671 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
672 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
674 // Lower this to FGETSIGNx86 plus an AND.
675 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
676 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
678 // We don't support sin/cos/fmod
679 setOperationAction(ISD::FSIN , MVT::f64, Expand);
680 setOperationAction(ISD::FCOS , MVT::f64, Expand);
681 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
682 setOperationAction(ISD::FSIN , MVT::f32, Expand);
683 setOperationAction(ISD::FCOS , MVT::f32, Expand);
684 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
686 // Expand FP immediates into loads from the stack, except for the special
688 addLegalFPImmediate(APFloat(+0.0)); // xorpd
689 addLegalFPImmediate(APFloat(+0.0f)); // xorps
690 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
691 // Use SSE for f32, x87 for f64.
692 // Set up the FP register classes.
693 addRegisterClass(MVT::f32, &X86::FR32RegClass);
694 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
696 // Use ANDPS to simulate FABS.
697 setOperationAction(ISD::FABS , MVT::f32, Custom);
699 // Use XORP to simulate FNEG.
700 setOperationAction(ISD::FNEG , MVT::f32, Custom);
702 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
704 // Use ANDPS and ORPS to simulate FCOPYSIGN.
705 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
706 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
708 // We don't support sin/cos/fmod
709 setOperationAction(ISD::FSIN , MVT::f32, Expand);
710 setOperationAction(ISD::FCOS , MVT::f32, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
713 // Special cases we handle for FP constants.
714 addLegalFPImmediate(APFloat(+0.0f)); // xorps
715 addLegalFPImmediate(APFloat(+0.0)); // FLD0
716 addLegalFPImmediate(APFloat(+1.0)); // FLD1
717 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
718 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
720 if (!TM.Options.UnsafeFPMath) {
721 setOperationAction(ISD::FSIN , MVT::f64, Expand);
722 setOperationAction(ISD::FCOS , MVT::f64, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
725 } else if (!TM.Options.UseSoftFloat) {
726 // f32 and f64 in x87.
727 // Set up the FP register classes.
728 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
729 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
731 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
732 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
733 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
734 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
736 if (!TM.Options.UnsafeFPMath) {
737 setOperationAction(ISD::FSIN , MVT::f64, Expand);
738 setOperationAction(ISD::FSIN , MVT::f32, Expand);
739 setOperationAction(ISD::FCOS , MVT::f64, Expand);
740 setOperationAction(ISD::FCOS , MVT::f32, Expand);
741 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
742 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
744 addLegalFPImmediate(APFloat(+0.0)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
748 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
749 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
750 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
751 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
754 // We don't support FMA.
755 setOperationAction(ISD::FMA, MVT::f64, Expand);
756 setOperationAction(ISD::FMA, MVT::f32, Expand);
758 // Long double always uses X87.
759 if (!TM.Options.UseSoftFloat) {
760 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
761 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
762 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
764 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
765 addLegalFPImmediate(TmpFlt); // FLD0
767 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
770 APFloat TmpFlt2(+1.0);
771 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
773 addLegalFPImmediate(TmpFlt2); // FLD1
774 TmpFlt2.changeSign();
775 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
778 if (!TM.Options.UnsafeFPMath) {
779 setOperationAction(ISD::FSIN , MVT::f80, Expand);
780 setOperationAction(ISD::FCOS , MVT::f80, Expand);
781 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
784 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
785 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
786 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
787 setOperationAction(ISD::FRINT, MVT::f80, Expand);
788 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
789 setOperationAction(ISD::FMA, MVT::f80, Expand);
792 // Always use a library call for pow.
793 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
794 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
795 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
797 setOperationAction(ISD::FLOG, MVT::f80, Expand);
798 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
799 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
800 setOperationAction(ISD::FEXP, MVT::f80, Expand);
801 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
802 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
803 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
805 // First set operation action for all vector types to either promote
806 // (for widening) or expand (for scalarization). Then we will selectively
807 // turn on ones that can be effectively codegen'd.
808 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
809 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
810 MVT VT = (MVT::SimpleValueType)i;
811 setOperationAction(ISD::ADD , VT, Expand);
812 setOperationAction(ISD::SUB , VT, Expand);
813 setOperationAction(ISD::FADD, VT, Expand);
814 setOperationAction(ISD::FNEG, VT, Expand);
815 setOperationAction(ISD::FSUB, VT, Expand);
816 setOperationAction(ISD::MUL , VT, Expand);
817 setOperationAction(ISD::FMUL, VT, Expand);
818 setOperationAction(ISD::SDIV, VT, Expand);
819 setOperationAction(ISD::UDIV, VT, Expand);
820 setOperationAction(ISD::FDIV, VT, Expand);
821 setOperationAction(ISD::SREM, VT, Expand);
822 setOperationAction(ISD::UREM, VT, Expand);
823 setOperationAction(ISD::LOAD, VT, Expand);
824 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
825 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
826 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
827 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
828 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
829 setOperationAction(ISD::FABS, VT, Expand);
830 setOperationAction(ISD::FSIN, VT, Expand);
831 setOperationAction(ISD::FSINCOS, VT, Expand);
832 setOperationAction(ISD::FCOS, VT, Expand);
833 setOperationAction(ISD::FSINCOS, VT, Expand);
834 setOperationAction(ISD::FREM, VT, Expand);
835 setOperationAction(ISD::FMA, VT, Expand);
836 setOperationAction(ISD::FPOWI, VT, Expand);
837 setOperationAction(ISD::FSQRT, VT, Expand);
838 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
839 setOperationAction(ISD::FFLOOR, VT, Expand);
840 setOperationAction(ISD::FCEIL, VT, Expand);
841 setOperationAction(ISD::FTRUNC, VT, Expand);
842 setOperationAction(ISD::FRINT, VT, Expand);
843 setOperationAction(ISD::FNEARBYINT, VT, Expand);
844 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
845 setOperationAction(ISD::MULHS, VT, Expand);
846 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
847 setOperationAction(ISD::MULHU, VT, Expand);
848 setOperationAction(ISD::SDIVREM, VT, Expand);
849 setOperationAction(ISD::UDIVREM, VT, Expand);
850 setOperationAction(ISD::FPOW, VT, Expand);
851 setOperationAction(ISD::CTPOP, VT, Expand);
852 setOperationAction(ISD::CTTZ, VT, Expand);
853 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
854 setOperationAction(ISD::CTLZ, VT, Expand);
855 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
856 setOperationAction(ISD::SHL, VT, Expand);
857 setOperationAction(ISD::SRA, VT, Expand);
858 setOperationAction(ISD::SRL, VT, Expand);
859 setOperationAction(ISD::ROTL, VT, Expand);
860 setOperationAction(ISD::ROTR, VT, Expand);
861 setOperationAction(ISD::BSWAP, VT, Expand);
862 setOperationAction(ISD::SETCC, VT, Expand);
863 setOperationAction(ISD::FLOG, VT, Expand);
864 setOperationAction(ISD::FLOG2, VT, Expand);
865 setOperationAction(ISD::FLOG10, VT, Expand);
866 setOperationAction(ISD::FEXP, VT, Expand);
867 setOperationAction(ISD::FEXP2, VT, Expand);
868 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
869 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
870 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
871 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
872 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
873 setOperationAction(ISD::TRUNCATE, VT, Expand);
874 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
875 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
876 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
877 setOperationAction(ISD::VSELECT, VT, Expand);
878 setOperationAction(ISD::SELECT_CC, VT, Expand);
879 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
880 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
881 setTruncStoreAction(VT,
882 (MVT::SimpleValueType)InnerVT, Expand);
883 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
884 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
886 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
887 // we have to deal with them whether we ask for Expansion or not. Setting
888 // Expand causes its own optimisation problems though, so leave them legal.
889 if (VT.getVectorElementType() == MVT::i1)
890 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
893 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
894 // with -msoft-float, disable use of MMX as well.
895 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
896 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
897 // No operations on x86mmx supported, everything uses intrinsics.
900 // MMX-sized vectors (other than x86mmx) are expected to be expanded
901 // into smaller operations.
902 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
903 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
904 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
905 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
906 setOperationAction(ISD::AND, MVT::v8i8, Expand);
907 setOperationAction(ISD::AND, MVT::v4i16, Expand);
908 setOperationAction(ISD::AND, MVT::v2i32, Expand);
909 setOperationAction(ISD::AND, MVT::v1i64, Expand);
910 setOperationAction(ISD::OR, MVT::v8i8, Expand);
911 setOperationAction(ISD::OR, MVT::v4i16, Expand);
912 setOperationAction(ISD::OR, MVT::v2i32, Expand);
913 setOperationAction(ISD::OR, MVT::v1i64, Expand);
914 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
921 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
922 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
923 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
924 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
925 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
926 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
927 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
930 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
932 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
933 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
935 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
936 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
937 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
938 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
939 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
940 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
941 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
942 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
943 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
944 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
945 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
946 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
947 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
950 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
951 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
953 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
954 // registers cannot be used even for integer operations.
955 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
956 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
957 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
958 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
960 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
961 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
962 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
963 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
964 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
965 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
966 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
967 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
968 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
969 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
970 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
971 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
972 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
973 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
974 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
975 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
976 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
977 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
978 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
979 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
980 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
981 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
983 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
984 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
985 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
986 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
988 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
989 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
994 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
995 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
996 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to custom lower non-power-of-2 vectors
998 if (!isPowerOf2_32(VT.getVectorNumElements()))
1000 // Do not attempt to custom lower non-128-bit vectors
1001 if (!VT.is128BitVector())
1003 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1004 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1008 // We support custom legalizing of sext and anyext loads for specific
1009 // memory vector types which we can load as a scalar (or sequence of
1010 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1011 // loads these must work with a single scalar load.
1012 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1014 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1022 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1023 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1024 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1025 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1026 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1027 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1029 if (Subtarget->is64Bit()) {
1030 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1031 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1034 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1035 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1036 MVT VT = (MVT::SimpleValueType)i;
1038 // Do not attempt to promote non-128-bit vectors
1039 if (!VT.is128BitVector())
1042 setOperationAction(ISD::AND, VT, Promote);
1043 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1044 setOperationAction(ISD::OR, VT, Promote);
1045 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1046 setOperationAction(ISD::XOR, VT, Promote);
1047 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1048 setOperationAction(ISD::LOAD, VT, Promote);
1049 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1050 setOperationAction(ISD::SELECT, VT, Promote);
1051 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1054 // Custom lower v2i64 and v2f64 selects.
1055 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1056 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1057 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1058 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1060 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1061 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1063 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1065 // As there is no 64-bit GPR available, we need build a special custom
1066 // sequence to convert from v2i32 to v2f32.
1067 if (!Subtarget->is64Bit())
1068 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1070 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1071 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1073 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1075 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1076 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1077 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1080 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1081 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1082 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1083 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1084 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1085 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1086 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1087 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1088 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1089 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1090 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1092 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1103 // FIXME: Do we need to handle scalar-to-vector here?
1104 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1106 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1107 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1110 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1111 // There is no BLENDI for byte vectors. We don't need to custom lower
1112 // some vselects for now.
1113 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1115 // SSE41 brings specific instructions for doing vector sign extend even in
1116 // cases where we don't have SRA.
1117 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1119 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1121 // i8 and i16 vectors are custom because the source register and source
1122 // source memory operand types are not the same width. f32 vectors are
1123 // custom since the immediate controlling the insert encodes additional
1125 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1128 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1133 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1135 // FIXME: these should be Legal, but that's only for the case where
1136 // the index is constant. For now custom expand to deal with that.
1137 if (Subtarget->is64Bit()) {
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1143 if (Subtarget->hasSSE2()) {
1144 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1145 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1147 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1148 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1150 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1151 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1153 // In the customized shift lowering, the legal cases in AVX2 will be
1155 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1156 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1158 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1159 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1161 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1164 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1165 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1172 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1173 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1174 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1176 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1187 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1189 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1200 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1202 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1203 // even though v8i16 is a legal type.
1204 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1205 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1206 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1208 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1209 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1210 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1212 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1213 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1215 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1217 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1218 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1220 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1223 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1224 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1226 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1229 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1231 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1233 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1235 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1238 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1240 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1242 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1243 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1245 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1246 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1248 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1249 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1251 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1253 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1254 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1255 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1256 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1257 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1258 setOperationAction(ISD::FMA, MVT::f32, Legal);
1259 setOperationAction(ISD::FMA, MVT::f64, Legal);
1262 if (Subtarget->hasInt256()) {
1263 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1264 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1265 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1266 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1268 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1269 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1270 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1271 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1273 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1274 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1275 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1276 // Don't lower v32i8 because there is no 128-bit byte mul
1278 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1279 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1280 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1281 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1283 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1284 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1286 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1287 // when we have a 256bit-wide blend with immediate.
1288 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1290 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1291 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1292 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1293 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1295 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1296 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1297 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1298 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1300 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1301 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1302 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1303 // Don't lower v32i8 because there is no 128-bit byte mul
1306 // In the customized shift lowering, the legal cases in AVX2 will be
1308 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1309 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1311 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1312 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1314 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1316 // Custom lower several nodes for 256-bit types.
1317 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1318 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1319 MVT VT = (MVT::SimpleValueType)i;
1321 // Extract subvector is special because the value type
1322 // (result) is 128-bit but the source is 256-bit wide.
1323 if (VT.is128BitVector())
1324 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1326 // Do not attempt to custom lower other non-256-bit vectors
1327 if (!VT.is256BitVector())
1330 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1331 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1334 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1335 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1336 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1339 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1340 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1341 MVT VT = (MVT::SimpleValueType)i;
1343 // Do not attempt to promote non-256-bit vectors
1344 if (!VT.is256BitVector())
1347 setOperationAction(ISD::AND, VT, Promote);
1348 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1349 setOperationAction(ISD::OR, VT, Promote);
1350 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1351 setOperationAction(ISD::XOR, VT, Promote);
1352 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1353 setOperationAction(ISD::LOAD, VT, Promote);
1354 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1355 setOperationAction(ISD::SELECT, VT, Promote);
1356 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1360 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1361 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1362 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1363 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1364 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1366 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1367 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1368 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1370 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1371 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1372 setOperationAction(ISD::XOR, MVT::i1, Legal);
1373 setOperationAction(ISD::OR, MVT::i1, Legal);
1374 setOperationAction(ISD::AND, MVT::i1, Legal);
1375 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1376 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1377 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1378 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1379 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1382 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1383 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1384 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1385 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1386 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1389 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1390 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1391 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1392 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1393 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1395 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1398 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1399 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1400 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1401 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1402 if (Subtarget->is64Bit()) {
1403 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1404 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1408 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1410 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1411 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1415 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1421 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1423 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1429 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1437 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1444 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1445 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1447 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1451 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1453 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1459 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1460 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1462 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1463 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1465 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1467 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1470 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1471 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1473 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1476 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1477 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1478 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1480 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1481 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1483 if (Subtarget->hasCDI()) {
1484 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1485 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1488 // Custom lower several nodes.
1489 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1490 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1491 MVT VT = (MVT::SimpleValueType)i;
1493 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1494 // Extract subvector is special because the value type
1495 // (result) is 256/128-bit but the source is 512-bit wide.
1496 if (VT.is128BitVector() || VT.is256BitVector())
1497 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1499 if (VT.getVectorElementType() == MVT::i1)
1500 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1502 // Do not attempt to custom lower other non-512-bit vectors
1503 if (!VT.is512BitVector())
1506 if ( EltSize >= 32) {
1507 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1508 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1509 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1510 setOperationAction(ISD::VSELECT, VT, Legal);
1511 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1512 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1513 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1516 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1517 MVT VT = (MVT::SimpleValueType)i;
1519 // Do not attempt to promote non-256-bit vectors
1520 if (!VT.is512BitVector())
1523 setOperationAction(ISD::SELECT, VT, Promote);
1524 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1528 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1529 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1530 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1532 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1533 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1535 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1536 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1537 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1538 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1540 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1541 const MVT VT = (MVT::SimpleValueType)i;
1543 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1545 // Do not attempt to promote non-256-bit vectors
1546 if (!VT.is512BitVector())
1549 if ( EltSize < 32) {
1550 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1551 setOperationAction(ISD::VSELECT, VT, Legal);
1556 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1557 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1558 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1560 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1561 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1562 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1598 if (!Subtarget->is64Bit()) {
1599 // These libcalls are not available in 32-bit.
1600 setLibcallName(RTLIB::SHL_I128, nullptr);
1601 setLibcallName(RTLIB::SRL_I128, nullptr);
1602 setLibcallName(RTLIB::SRA_I128, nullptr);
1605 // Combine sin / cos into one node or libcall if possible.
1606 if (Subtarget->hasSinCos()) {
1607 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1608 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1609 if (Subtarget->isTargetDarwin()) {
1610 // For MacOSX, we don't want to the normal expansion of a libcall to
1611 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1613 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1614 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1618 if (Subtarget->isTargetWin64()) {
1619 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1620 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1621 setOperationAction(ISD::SREM, MVT::i128, Custom);
1622 setOperationAction(ISD::UREM, MVT::i128, Custom);
1623 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1624 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1627 // We have target-specific dag combine patterns for the following nodes:
1628 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1629 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1630 setTargetDAGCombine(ISD::VSELECT);
1631 setTargetDAGCombine(ISD::SELECT);
1632 setTargetDAGCombine(ISD::SHL);
1633 setTargetDAGCombine(ISD::SRA);
1634 setTargetDAGCombine(ISD::SRL);
1635 setTargetDAGCombine(ISD::OR);
1636 setTargetDAGCombine(ISD::AND);
1637 setTargetDAGCombine(ISD::ADD);
1638 setTargetDAGCombine(ISD::FADD);
1639 setTargetDAGCombine(ISD::FSUB);
1640 setTargetDAGCombine(ISD::FMA);
1641 setTargetDAGCombine(ISD::SUB);
1642 setTargetDAGCombine(ISD::LOAD);
1643 setTargetDAGCombine(ISD::STORE);
1644 setTargetDAGCombine(ISD::ZERO_EXTEND);
1645 setTargetDAGCombine(ISD::ANY_EXTEND);
1646 setTargetDAGCombine(ISD::SIGN_EXTEND);
1647 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1648 setTargetDAGCombine(ISD::TRUNCATE);
1649 setTargetDAGCombine(ISD::SINT_TO_FP);
1650 setTargetDAGCombine(ISD::SETCC);
1651 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1652 setTargetDAGCombine(ISD::BUILD_VECTOR);
1653 if (Subtarget->is64Bit())
1654 setTargetDAGCombine(ISD::MUL);
1655 setTargetDAGCombine(ISD::XOR);
1657 computeRegisterProperties();
1659 // On Darwin, -Os means optimize for size without hurting performance,
1660 // do not reduce the limit.
1661 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1662 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1663 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1664 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1665 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1666 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1667 setPrefLoopAlignment(4); // 2^4 bytes.
1669 // Predictable cmov don't hurt on atom because it's in-order.
1670 PredictableSelectIsExpensive = !Subtarget->isAtom();
1672 setPrefFunctionAlignment(4); // 2^4 bytes.
1674 verifyIntrinsicTables();
1677 // This has so far only been implemented for 64-bit MachO.
1678 bool X86TargetLowering::useLoadStackGuardNode() const {
1679 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1680 Subtarget->is64Bit();
1683 TargetLoweringBase::LegalizeTypeAction
1684 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1685 if (ExperimentalVectorWideningLegalization &&
1686 VT.getVectorNumElements() != 1 &&
1687 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1688 return TypeWidenVector;
1690 return TargetLoweringBase::getPreferredVectorAction(VT);
1693 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1695 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1697 const unsigned NumElts = VT.getVectorNumElements();
1698 const EVT EltVT = VT.getVectorElementType();
1699 if (VT.is512BitVector()) {
1700 if (Subtarget->hasAVX512())
1701 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1702 EltVT == MVT::f32 || EltVT == MVT::f64)
1704 case 8: return MVT::v8i1;
1705 case 16: return MVT::v16i1;
1707 if (Subtarget->hasBWI())
1708 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1710 case 32: return MVT::v32i1;
1711 case 64: return MVT::v64i1;
1715 if (VT.is256BitVector() || VT.is128BitVector()) {
1716 if (Subtarget->hasVLX())
1717 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1718 EltVT == MVT::f32 || EltVT == MVT::f64)
1720 case 2: return MVT::v2i1;
1721 case 4: return MVT::v4i1;
1722 case 8: return MVT::v8i1;
1724 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1725 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1727 case 8: return MVT::v8i1;
1728 case 16: return MVT::v16i1;
1729 case 32: return MVT::v32i1;
1733 return VT.changeVectorElementTypeToInteger();
1736 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1737 /// the desired ByVal argument alignment.
1738 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1741 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1742 if (VTy->getBitWidth() == 128)
1744 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1745 unsigned EltAlign = 0;
1746 getMaxByValAlign(ATy->getElementType(), EltAlign);
1747 if (EltAlign > MaxAlign)
1748 MaxAlign = EltAlign;
1749 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1750 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1751 unsigned EltAlign = 0;
1752 getMaxByValAlign(STy->getElementType(i), EltAlign);
1753 if (EltAlign > MaxAlign)
1754 MaxAlign = EltAlign;
1761 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1762 /// function arguments in the caller parameter area. For X86, aggregates
1763 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1764 /// are at 4-byte boundaries.
1765 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1766 if (Subtarget->is64Bit()) {
1767 // Max of 8 and alignment of type.
1768 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1775 if (Subtarget->hasSSE1())
1776 getMaxByValAlign(Ty, Align);
1780 /// getOptimalMemOpType - Returns the target specific optimal type for load
1781 /// and store operations as a result of memset, memcpy, and memmove
1782 /// lowering. If DstAlign is zero that means it's safe to destination
1783 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1784 /// means there isn't a need to check it against alignment requirement,
1785 /// probably because the source does not need to be loaded. If 'IsMemset' is
1786 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1787 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1788 /// source is constant so it does not need to be loaded.
1789 /// It returns EVT::Other if the type should be determined using generic
1790 /// target-independent logic.
1792 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1793 unsigned DstAlign, unsigned SrcAlign,
1794 bool IsMemset, bool ZeroMemset,
1796 MachineFunction &MF) const {
1797 const Function *F = MF.getFunction();
1798 if ((!IsMemset || ZeroMemset) &&
1799 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1800 Attribute::NoImplicitFloat)) {
1802 (Subtarget->isUnalignedMemAccessFast() ||
1803 ((DstAlign == 0 || DstAlign >= 16) &&
1804 (SrcAlign == 0 || SrcAlign >= 16)))) {
1806 if (Subtarget->hasInt256())
1808 if (Subtarget->hasFp256())
1811 if (Subtarget->hasSSE2())
1813 if (Subtarget->hasSSE1())
1815 } else if (!MemcpyStrSrc && Size >= 8 &&
1816 !Subtarget->is64Bit() &&
1817 Subtarget->hasSSE2()) {
1818 // Do not use f64 to lower memcpy if source is string constant. It's
1819 // better to use i32 to avoid the loads.
1823 if (Subtarget->is64Bit() && Size >= 8)
1828 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1830 return X86ScalarSSEf32;
1831 else if (VT == MVT::f64)
1832 return X86ScalarSSEf64;
1837 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1842 *Fast = Subtarget->isUnalignedMemAccessFast();
1846 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1847 /// current function. The returned value is a member of the
1848 /// MachineJumpTableInfo::JTEntryKind enum.
1849 unsigned X86TargetLowering::getJumpTableEncoding() const {
1850 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1852 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1853 Subtarget->isPICStyleGOT())
1854 return MachineJumpTableInfo::EK_Custom32;
1856 // Otherwise, use the normal jump table encoding heuristics.
1857 return TargetLowering::getJumpTableEncoding();
1861 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1862 const MachineBasicBlock *MBB,
1863 unsigned uid,MCContext &Ctx) const{
1864 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1865 Subtarget->isPICStyleGOT());
1866 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1868 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1869 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1872 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1874 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1875 SelectionDAG &DAG) const {
1876 if (!Subtarget->is64Bit())
1877 // This doesn't have SDLoc associated with it, but is not really the
1878 // same as a Register.
1879 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1883 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1884 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1886 const MCExpr *X86TargetLowering::
1887 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1888 MCContext &Ctx) const {
1889 // X86-64 uses RIP relative addressing based on the jump table label.
1890 if (Subtarget->isPICStyleRIPRel())
1891 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1893 // Otherwise, the reference is relative to the PIC base.
1894 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1897 // FIXME: Why this routine is here? Move to RegInfo!
1898 std::pair<const TargetRegisterClass*, uint8_t>
1899 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1900 const TargetRegisterClass *RRC = nullptr;
1902 switch (VT.SimpleTy) {
1904 return TargetLowering::findRepresentativeClass(VT);
1905 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1906 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1909 RRC = &X86::VR64RegClass;
1911 case MVT::f32: case MVT::f64:
1912 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1913 case MVT::v4f32: case MVT::v2f64:
1914 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1916 RRC = &X86::VR128RegClass;
1919 return std::make_pair(RRC, Cost);
1922 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1923 unsigned &Offset) const {
1924 if (!Subtarget->isTargetLinux())
1927 if (Subtarget->is64Bit()) {
1928 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1930 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1942 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1943 unsigned DestAS) const {
1944 assert(SrcAS != DestAS && "Expected different address spaces!");
1946 return SrcAS < 256 && DestAS < 256;
1949 //===----------------------------------------------------------------------===//
1950 // Return Value Calling Convention Implementation
1951 //===----------------------------------------------------------------------===//
1953 #include "X86GenCallingConv.inc"
1956 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1957 MachineFunction &MF, bool isVarArg,
1958 const SmallVectorImpl<ISD::OutputArg> &Outs,
1959 LLVMContext &Context) const {
1960 SmallVector<CCValAssign, 16> RVLocs;
1961 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1962 return CCInfo.CheckReturn(Outs, RetCC_X86);
1965 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1966 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1971 X86TargetLowering::LowerReturn(SDValue Chain,
1972 CallingConv::ID CallConv, bool isVarArg,
1973 const SmallVectorImpl<ISD::OutputArg> &Outs,
1974 const SmallVectorImpl<SDValue> &OutVals,
1975 SDLoc dl, SelectionDAG &DAG) const {
1976 MachineFunction &MF = DAG.getMachineFunction();
1977 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1979 SmallVector<CCValAssign, 16> RVLocs;
1980 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1981 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1984 SmallVector<SDValue, 6> RetOps;
1985 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1986 // Operand #1 = Bytes To Pop
1987 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1990 // Copy the result values into the output registers.
1991 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1992 CCValAssign &VA = RVLocs[i];
1993 assert(VA.isRegLoc() && "Can only return in registers!");
1994 SDValue ValToCopy = OutVals[i];
1995 EVT ValVT = ValToCopy.getValueType();
1997 // Promote values to the appropriate types
1998 if (VA.getLocInfo() == CCValAssign::SExt)
1999 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2000 else if (VA.getLocInfo() == CCValAssign::ZExt)
2001 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2002 else if (VA.getLocInfo() == CCValAssign::AExt)
2003 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::BCvt)
2005 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2007 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2008 "Unexpected FP-extend for return value.");
2010 // If this is x86-64, and we disabled SSE, we can't return FP values,
2011 // or SSE or MMX vectors.
2012 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2013 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2014 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2015 report_fatal_error("SSE register return with SSE disabled");
2017 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2018 // llvm-gcc has never done it right and no one has noticed, so this
2019 // should be OK for now.
2020 if (ValVT == MVT::f64 &&
2021 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2022 report_fatal_error("SSE2 register return with SSE2 disabled");
2024 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2025 // the RET instruction and handled by the FP Stackifier.
2026 if (VA.getLocReg() == X86::FP0 ||
2027 VA.getLocReg() == X86::FP1) {
2028 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2029 // change the value to the FP stack register class.
2030 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2031 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2032 RetOps.push_back(ValToCopy);
2033 // Don't emit a copytoreg.
2037 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2038 // which is returned in RAX / RDX.
2039 if (Subtarget->is64Bit()) {
2040 if (ValVT == MVT::x86mmx) {
2041 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2042 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2043 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2045 // If we don't have SSE2 available, convert to v4f32 so the generated
2046 // register is legal.
2047 if (!Subtarget->hasSSE2())
2048 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2053 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2054 Flag = Chain.getValue(1);
2055 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2058 // The x86-64 ABIs require that for returning structs by value we copy
2059 // the sret argument into %rax/%eax (depending on ABI) for the return.
2060 // Win32 requires us to put the sret argument to %eax as well.
2061 // We saved the argument into a virtual register in the entry block,
2062 // so now we copy the value out and into %rax/%eax.
2063 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2064 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2065 MachineFunction &MF = DAG.getMachineFunction();
2066 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2067 unsigned Reg = FuncInfo->getSRetReturnReg();
2069 "SRetReturnReg should have been set in LowerFormalArguments().");
2070 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2073 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2074 X86::RAX : X86::EAX;
2075 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2076 Flag = Chain.getValue(1);
2078 // RAX/EAX now acts like a return value.
2079 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2082 RetOps[0] = Chain; // Update chain.
2084 // Add the flag if we have it.
2086 RetOps.push_back(Flag);
2088 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2091 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2092 if (N->getNumValues() != 1)
2094 if (!N->hasNUsesOfValue(1, 0))
2097 SDValue TCChain = Chain;
2098 SDNode *Copy = *N->use_begin();
2099 if (Copy->getOpcode() == ISD::CopyToReg) {
2100 // If the copy has a glue operand, we conservatively assume it isn't safe to
2101 // perform a tail call.
2102 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2104 TCChain = Copy->getOperand(0);
2105 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2108 bool HasRet = false;
2109 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2111 if (UI->getOpcode() != X86ISD::RET_FLAG)
2113 // If we are returning more than one value, we can definitely
2114 // not make a tail call see PR19530
2115 if (UI->getNumOperands() > 4)
2117 if (UI->getNumOperands() == 4 &&
2118 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2131 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2132 ISD::NodeType ExtendKind) const {
2134 // TODO: Is this also valid on 32-bit?
2135 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2136 ReturnMVT = MVT::i8;
2138 ReturnMVT = MVT::i32;
2140 EVT MinVT = getRegisterType(Context, ReturnMVT);
2141 return VT.bitsLT(MinVT) ? MinVT : VT;
2144 /// LowerCallResult - Lower the result values of a call into the
2145 /// appropriate copies out of appropriate physical registers.
2148 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2149 CallingConv::ID CallConv, bool isVarArg,
2150 const SmallVectorImpl<ISD::InputArg> &Ins,
2151 SDLoc dl, SelectionDAG &DAG,
2152 SmallVectorImpl<SDValue> &InVals) const {
2154 // Assign locations to each value returned by this call.
2155 SmallVector<CCValAssign, 16> RVLocs;
2156 bool Is64Bit = Subtarget->is64Bit();
2157 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2159 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2161 // Copy all of the result registers out of their specified physreg.
2162 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2163 CCValAssign &VA = RVLocs[i];
2164 EVT CopyVT = VA.getValVT();
2166 // If this is x86-64, and we disabled SSE, we can't return FP values
2167 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2168 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2169 report_fatal_error("SSE register return with SSE disabled");
2172 // If we prefer to use the value in xmm registers, copy it out as f80 and
2173 // use a truncate to move it from fp stack reg to xmm reg.
2174 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2175 isScalarFPTypeInSSEReg(VA.getValVT()))
2178 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2179 CopyVT, InFlag).getValue(1);
2180 SDValue Val = Chain.getValue(0);
2182 if (CopyVT != VA.getValVT())
2183 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2184 // This truncation won't change the value.
2185 DAG.getIntPtrConstant(1));
2187 InFlag = Chain.getValue(2);
2188 InVals.push_back(Val);
2194 //===----------------------------------------------------------------------===//
2195 // C & StdCall & Fast Calling Convention implementation
2196 //===----------------------------------------------------------------------===//
2197 // StdCall calling convention seems to be standard for many Windows' API
2198 // routines and around. It differs from C calling convention just a little:
2199 // callee should clean up the stack, not caller. Symbols should be also
2200 // decorated in some fancy way :) It doesn't support any vector arguments.
2201 // For info on fast calling convention see Fast Calling Convention (tail call)
2202 // implementation LowerX86_32FastCCCallTo.
2204 /// CallIsStructReturn - Determines whether a call uses struct return
2206 enum StructReturnType {
2211 static StructReturnType
2212 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2214 return NotStructReturn;
2216 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2217 if (!Flags.isSRet())
2218 return NotStructReturn;
2219 if (Flags.isInReg())
2220 return RegStructReturn;
2221 return StackStructReturn;
2224 /// ArgsAreStructReturn - Determines whether a function uses struct
2225 /// return semantics.
2226 static StructReturnType
2227 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2229 return NotStructReturn;
2231 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2232 if (!Flags.isSRet())
2233 return NotStructReturn;
2234 if (Flags.isInReg())
2235 return RegStructReturn;
2236 return StackStructReturn;
2239 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2240 /// by "Src" to address "Dst" with size and alignment information specified by
2241 /// the specific parameter attribute. The copy will be passed as a byval
2242 /// function parameter.
2244 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2245 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2247 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2249 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2250 /*isVolatile*/false, /*AlwaysInline=*/true,
2251 MachinePointerInfo(), MachinePointerInfo());
2254 /// IsTailCallConvention - Return true if the calling convention is one that
2255 /// supports tail call optimization.
2256 static bool IsTailCallConvention(CallingConv::ID CC) {
2257 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2258 CC == CallingConv::HiPE);
2261 /// \brief Return true if the calling convention is a C calling convention.
2262 static bool IsCCallConvention(CallingConv::ID CC) {
2263 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2264 CC == CallingConv::X86_64_SysV);
2267 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2268 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2272 CallingConv::ID CalleeCC = CS.getCallingConv();
2273 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2279 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2280 /// a tailcall target by changing its ABI.
2281 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2282 bool GuaranteedTailCallOpt) {
2283 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2287 X86TargetLowering::LowerMemArgument(SDValue Chain,
2288 CallingConv::ID CallConv,
2289 const SmallVectorImpl<ISD::InputArg> &Ins,
2290 SDLoc dl, SelectionDAG &DAG,
2291 const CCValAssign &VA,
2292 MachineFrameInfo *MFI,
2294 // Create the nodes corresponding to a load from this parameter slot.
2295 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2296 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2297 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2298 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2301 // If value is passed by pointer we have address passed instead of the value
2303 if (VA.getLocInfo() == CCValAssign::Indirect)
2304 ValVT = VA.getLocVT();
2306 ValVT = VA.getValVT();
2308 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2309 // changed with more analysis.
2310 // In case of tail call optimization mark all arguments mutable. Since they
2311 // could be overwritten by lowering of arguments in case of a tail call.
2312 if (Flags.isByVal()) {
2313 unsigned Bytes = Flags.getByValSize();
2314 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2315 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2316 return DAG.getFrameIndex(FI, getPointerTy());
2318 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2319 VA.getLocMemOffset(), isImmutable);
2320 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2321 return DAG.getLoad(ValVT, dl, Chain, FIN,
2322 MachinePointerInfo::getFixedStack(FI),
2323 false, false, false, 0);
2327 // FIXME: Get this from tablegen.
2328 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2329 const X86Subtarget *Subtarget) {
2330 assert(Subtarget->is64Bit());
2332 if (Subtarget->isCallingConvWin64(CallConv)) {
2333 static const MCPhysReg GPR64ArgRegsWin64[] = {
2334 X86::RCX, X86::RDX, X86::R8, X86::R9
2336 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2339 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2340 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2342 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2345 // FIXME: Get this from tablegen.
2346 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2347 CallingConv::ID CallConv,
2348 const X86Subtarget *Subtarget) {
2349 assert(Subtarget->is64Bit());
2350 if (Subtarget->isCallingConvWin64(CallConv)) {
2351 // The XMM registers which might contain var arg parameters are shadowed
2352 // in their paired GPR. So we only need to save the GPR to their home
2354 // TODO: __vectorcall will change this.
2358 const Function *Fn = MF.getFunction();
2359 bool NoImplicitFloatOps = Fn->getAttributes().
2360 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2361 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2362 "SSE register cannot be used when SSE is disabled!");
2363 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2364 !Subtarget->hasSSE1())
2365 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2369 static const MCPhysReg XMMArgRegs64Bit[] = {
2370 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2371 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2373 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2377 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2378 CallingConv::ID CallConv,
2380 const SmallVectorImpl<ISD::InputArg> &Ins,
2383 SmallVectorImpl<SDValue> &InVals)
2385 MachineFunction &MF = DAG.getMachineFunction();
2386 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2388 const Function* Fn = MF.getFunction();
2389 if (Fn->hasExternalLinkage() &&
2390 Subtarget->isTargetCygMing() &&
2391 Fn->getName() == "main")
2392 FuncInfo->setForceFramePointer(true);
2394 MachineFrameInfo *MFI = MF.getFrameInfo();
2395 bool Is64Bit = Subtarget->is64Bit();
2396 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2398 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2399 "Var args not supported with calling convention fastcc, ghc or hipe");
2401 // Assign locations to all of the incoming arguments.
2402 SmallVector<CCValAssign, 16> ArgLocs;
2403 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2405 // Allocate shadow area for Win64
2407 CCInfo.AllocateStack(32, 8);
2409 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2411 unsigned LastVal = ~0U;
2413 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2414 CCValAssign &VA = ArgLocs[i];
2415 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2417 assert(VA.getValNo() != LastVal &&
2418 "Don't support value assigned to multiple locs yet");
2420 LastVal = VA.getValNo();
2422 if (VA.isRegLoc()) {
2423 EVT RegVT = VA.getLocVT();
2424 const TargetRegisterClass *RC;
2425 if (RegVT == MVT::i32)
2426 RC = &X86::GR32RegClass;
2427 else if (Is64Bit && RegVT == MVT::i64)
2428 RC = &X86::GR64RegClass;
2429 else if (RegVT == MVT::f32)
2430 RC = &X86::FR32RegClass;
2431 else if (RegVT == MVT::f64)
2432 RC = &X86::FR64RegClass;
2433 else if (RegVT.is512BitVector())
2434 RC = &X86::VR512RegClass;
2435 else if (RegVT.is256BitVector())
2436 RC = &X86::VR256RegClass;
2437 else if (RegVT.is128BitVector())
2438 RC = &X86::VR128RegClass;
2439 else if (RegVT == MVT::x86mmx)
2440 RC = &X86::VR64RegClass;
2441 else if (RegVT == MVT::i1)
2442 RC = &X86::VK1RegClass;
2443 else if (RegVT == MVT::v8i1)
2444 RC = &X86::VK8RegClass;
2445 else if (RegVT == MVT::v16i1)
2446 RC = &X86::VK16RegClass;
2447 else if (RegVT == MVT::v32i1)
2448 RC = &X86::VK32RegClass;
2449 else if (RegVT == MVT::v64i1)
2450 RC = &X86::VK64RegClass;
2452 llvm_unreachable("Unknown argument type!");
2454 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2455 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2457 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2458 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2460 if (VA.getLocInfo() == CCValAssign::SExt)
2461 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2462 DAG.getValueType(VA.getValVT()));
2463 else if (VA.getLocInfo() == CCValAssign::ZExt)
2464 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::BCvt)
2467 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2469 if (VA.isExtInLoc()) {
2470 // Handle MMX values passed in XMM regs.
2471 if (RegVT.isVector())
2472 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2474 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2477 assert(VA.isMemLoc());
2478 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2481 // If value is passed via pointer - do a load.
2482 if (VA.getLocInfo() == CCValAssign::Indirect)
2483 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2484 MachinePointerInfo(), false, false, false, 0);
2486 InVals.push_back(ArgValue);
2489 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2490 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2491 // The x86-64 ABIs require that for returning structs by value we copy
2492 // the sret argument into %rax/%eax (depending on ABI) for the return.
2493 // Win32 requires us to put the sret argument to %eax as well.
2494 // Save the argument into a virtual register so that we can access it
2495 // from the return points.
2496 if (Ins[i].Flags.isSRet()) {
2497 unsigned Reg = FuncInfo->getSRetReturnReg();
2499 MVT PtrTy = getPointerTy();
2500 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2501 FuncInfo->setSRetReturnReg(Reg);
2503 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2504 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2510 unsigned StackSize = CCInfo.getNextStackOffset();
2511 // Align stack specially for tail calls.
2512 if (FuncIsMadeTailCallSafe(CallConv,
2513 MF.getTarget().Options.GuaranteedTailCallOpt))
2514 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2516 // If the function takes variable number of arguments, make a frame index for
2517 // the start of the first vararg value... for expansion of llvm.va_start. We
2518 // can skip this if there are no va_start calls.
2519 if (MFI->hasVAStart() &&
2520 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2521 CallConv != CallingConv::X86_ThisCall))) {
2522 FuncInfo->setVarArgsFrameIndex(
2523 MFI->CreateFixedObject(1, StackSize, true));
2526 // 64-bit calling conventions support varargs and register parameters, so we
2527 // have to do extra work to spill them in the prologue or forward them to
2529 if (Is64Bit && isVarArg &&
2530 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2531 // Find the first unallocated argument registers.
2532 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2533 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2534 unsigned NumIntRegs =
2535 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2536 unsigned NumXMMRegs =
2537 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2538 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2539 "SSE register cannot be used when SSE is disabled!");
2541 // Gather all the live in physical registers.
2542 SmallVector<SDValue, 6> LiveGPRs;
2543 SmallVector<SDValue, 8> LiveXMMRegs;
2545 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2546 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2548 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2550 if (!ArgXMMs.empty()) {
2551 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2552 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2553 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2554 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2555 LiveXMMRegs.push_back(
2556 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2560 // Store them to the va_list returned by va_start.
2561 if (MFI->hasVAStart()) {
2563 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2564 // Get to the caller-allocated home save location. Add 8 to account
2565 // for the return address.
2566 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2567 FuncInfo->setRegSaveFrameIndex(
2568 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2569 // Fixup to set vararg frame on shadow area (4 x i64).
2571 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2573 // For X86-64, if there are vararg parameters that are passed via
2574 // registers, then we must store them to their spots on the stack so
2575 // they may be loaded by deferencing the result of va_next.
2576 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2577 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2578 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2579 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2582 // Store the integer parameter registers.
2583 SmallVector<SDValue, 8> MemOps;
2584 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2586 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2587 for (SDValue Val : LiveGPRs) {
2588 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2589 DAG.getIntPtrConstant(Offset));
2591 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2592 MachinePointerInfo::getFixedStack(
2593 FuncInfo->getRegSaveFrameIndex(), Offset),
2595 MemOps.push_back(Store);
2599 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2600 // Now store the XMM (fp + vector) parameter registers.
2601 SmallVector<SDValue, 12> SaveXMMOps;
2602 SaveXMMOps.push_back(Chain);
2603 SaveXMMOps.push_back(ALVal);
2604 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2605 FuncInfo->getRegSaveFrameIndex()));
2606 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2607 FuncInfo->getVarArgsFPOffset()));
2608 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2610 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2611 MVT::Other, SaveXMMOps));
2614 if (!MemOps.empty())
2615 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2617 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2618 // to the liveout set on a musttail call.
2619 assert(MFI->hasMustTailInVarArgFunc());
2620 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2621 typedef X86MachineFunctionInfo::Forward Forward;
2623 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2625 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2626 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2627 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2630 if (!ArgXMMs.empty()) {
2632 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2633 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2634 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2636 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2638 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2639 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2641 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2647 // Some CCs need callee pop.
2648 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2649 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2650 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2652 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2653 // If this is an sret function, the return should pop the hidden pointer.
2654 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2655 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2656 argsAreStructReturn(Ins) == StackStructReturn)
2657 FuncInfo->setBytesToPopOnReturn(4);
2661 // RegSaveFrameIndex is X86-64 only.
2662 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2663 if (CallConv == CallingConv::X86_FastCall ||
2664 CallConv == CallingConv::X86_ThisCall)
2665 // fastcc functions can't have varargs.
2666 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2669 FuncInfo->setArgumentStackSize(StackSize);
2675 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2676 SDValue StackPtr, SDValue Arg,
2677 SDLoc dl, SelectionDAG &DAG,
2678 const CCValAssign &VA,
2679 ISD::ArgFlagsTy Flags) const {
2680 unsigned LocMemOffset = VA.getLocMemOffset();
2681 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2682 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2683 if (Flags.isByVal())
2684 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2686 return DAG.getStore(Chain, dl, Arg, PtrOff,
2687 MachinePointerInfo::getStack(LocMemOffset),
2691 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2692 /// optimization is performed and it is required.
2694 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2695 SDValue &OutRetAddr, SDValue Chain,
2696 bool IsTailCall, bool Is64Bit,
2697 int FPDiff, SDLoc dl) const {
2698 // Adjust the Return address stack slot.
2699 EVT VT = getPointerTy();
2700 OutRetAddr = getReturnAddressFrameIndex(DAG);
2702 // Load the "old" Return address.
2703 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2704 false, false, false, 0);
2705 return SDValue(OutRetAddr.getNode(), 1);
2708 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2709 /// optimization is performed and it is required (FPDiff!=0).
2710 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2711 SDValue Chain, SDValue RetAddrFrIdx,
2712 EVT PtrVT, unsigned SlotSize,
2713 int FPDiff, SDLoc dl) {
2714 // Store the return address to the appropriate stack slot.
2715 if (!FPDiff) return Chain;
2716 // Calculate the new stack slot for the return address.
2717 int NewReturnAddrFI =
2718 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2720 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2721 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2722 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2728 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2729 SmallVectorImpl<SDValue> &InVals) const {
2730 SelectionDAG &DAG = CLI.DAG;
2732 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2733 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2734 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2735 SDValue Chain = CLI.Chain;
2736 SDValue Callee = CLI.Callee;
2737 CallingConv::ID CallConv = CLI.CallConv;
2738 bool &isTailCall = CLI.IsTailCall;
2739 bool isVarArg = CLI.IsVarArg;
2741 MachineFunction &MF = DAG.getMachineFunction();
2742 bool Is64Bit = Subtarget->is64Bit();
2743 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2744 StructReturnType SR = callIsStructReturn(Outs);
2745 bool IsSibcall = false;
2746 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2748 if (MF.getTarget().Options.DisableTailCalls)
2751 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2753 // Force this to be a tail call. The verifier rules are enough to ensure
2754 // that we can lower this successfully without moving the return address
2757 } else if (isTailCall) {
2758 // Check if it's really possible to do a tail call.
2759 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2760 isVarArg, SR != NotStructReturn,
2761 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2762 Outs, OutVals, Ins, DAG);
2764 // Sibcalls are automatically detected tailcalls which do not require
2766 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2773 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2774 "Var args not supported with calling convention fastcc, ghc or hipe");
2776 // Analyze operands of the call, assigning locations to each operand.
2777 SmallVector<CCValAssign, 16> ArgLocs;
2778 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2780 // Allocate shadow area for Win64
2782 CCInfo.AllocateStack(32, 8);
2784 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2786 // Get a count of how many bytes are to be pushed on the stack.
2787 unsigned NumBytes = CCInfo.getNextStackOffset();
2789 // This is a sibcall. The memory operands are available in caller's
2790 // own caller's stack.
2792 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2793 IsTailCallConvention(CallConv))
2794 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2797 if (isTailCall && !IsSibcall && !IsMustTail) {
2798 // Lower arguments at fp - stackoffset + fpdiff.
2799 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2801 FPDiff = NumBytesCallerPushed - NumBytes;
2803 // Set the delta of movement of the returnaddr stackslot.
2804 // But only set if delta is greater than previous delta.
2805 if (FPDiff < X86Info->getTCReturnAddrDelta())
2806 X86Info->setTCReturnAddrDelta(FPDiff);
2809 unsigned NumBytesToPush = NumBytes;
2810 unsigned NumBytesToPop = NumBytes;
2812 // If we have an inalloca argument, all stack space has already been allocated
2813 // for us and be right at the top of the stack. We don't support multiple
2814 // arguments passed in memory when using inalloca.
2815 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2817 if (!ArgLocs.back().isMemLoc())
2818 report_fatal_error("cannot use inalloca attribute on a register "
2820 if (ArgLocs.back().getLocMemOffset() != 0)
2821 report_fatal_error("any parameter with the inalloca attribute must be "
2822 "the only memory argument");
2826 Chain = DAG.getCALLSEQ_START(
2827 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2829 SDValue RetAddrFrIdx;
2830 // Load return address for tail calls.
2831 if (isTailCall && FPDiff)
2832 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2833 Is64Bit, FPDiff, dl);
2835 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2836 SmallVector<SDValue, 8> MemOpChains;
2839 // Walk the register/memloc assignments, inserting copies/loads. In the case
2840 // of tail call optimization arguments are handle later.
2841 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2842 DAG.getSubtarget().getRegisterInfo());
2843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2844 // Skip inalloca arguments, they have already been written.
2845 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2846 if (Flags.isInAlloca())
2849 CCValAssign &VA = ArgLocs[i];
2850 EVT RegVT = VA.getLocVT();
2851 SDValue Arg = OutVals[i];
2852 bool isByVal = Flags.isByVal();
2854 // Promote the value if needed.
2855 switch (VA.getLocInfo()) {
2856 default: llvm_unreachable("Unknown loc info!");
2857 case CCValAssign::Full: break;
2858 case CCValAssign::SExt:
2859 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2861 case CCValAssign::ZExt:
2862 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::AExt:
2865 if (RegVT.is128BitVector()) {
2866 // Special case: passing MMX values in XMM registers.
2867 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2868 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2869 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2871 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2873 case CCValAssign::BCvt:
2874 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2876 case CCValAssign::Indirect: {
2877 // Store the argument.
2878 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2879 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2880 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2881 MachinePointerInfo::getFixedStack(FI),
2888 if (VA.isRegLoc()) {
2889 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2890 if (isVarArg && IsWin64) {
2891 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2892 // shadow reg if callee is a varargs function.
2893 unsigned ShadowReg = 0;
2894 switch (VA.getLocReg()) {
2895 case X86::XMM0: ShadowReg = X86::RCX; break;
2896 case X86::XMM1: ShadowReg = X86::RDX; break;
2897 case X86::XMM2: ShadowReg = X86::R8; break;
2898 case X86::XMM3: ShadowReg = X86::R9; break;
2901 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2903 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2904 assert(VA.isMemLoc());
2905 if (!StackPtr.getNode())
2906 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2908 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2909 dl, DAG, VA, Flags));
2913 if (!MemOpChains.empty())
2914 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2916 if (Subtarget->isPICStyleGOT()) {
2917 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2920 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2921 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2923 // If we are tail calling and generating PIC/GOT style code load the
2924 // address of the callee into ECX. The value in ecx is used as target of
2925 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2926 // for tail calls on PIC/GOT architectures. Normally we would just put the
2927 // address of GOT into ebx and then call target@PLT. But for tail calls
2928 // ebx would be restored (since ebx is callee saved) before jumping to the
2931 // Note: The actual moving to ECX is done further down.
2932 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2933 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2934 !G->getGlobal()->hasProtectedVisibility())
2935 Callee = LowerGlobalAddress(Callee, DAG);
2936 else if (isa<ExternalSymbolSDNode>(Callee))
2937 Callee = LowerExternalSymbol(Callee, DAG);
2941 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2942 // From AMD64 ABI document:
2943 // For calls that may call functions that use varargs or stdargs
2944 // (prototype-less calls or calls to functions containing ellipsis (...) in
2945 // the declaration) %al is used as hidden argument to specify the number
2946 // of SSE registers used. The contents of %al do not need to match exactly
2947 // the number of registers, but must be an ubound on the number of SSE
2948 // registers used and is in the range 0 - 8 inclusive.
2950 // Count the number of XMM registers allocated.
2951 static const MCPhysReg XMMArgRegs[] = {
2952 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2953 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2955 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2956 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2957 && "SSE registers cannot be used when SSE is disabled");
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2960 DAG.getConstant(NumXMMRegs, MVT::i8)));
2963 if (Is64Bit && isVarArg && IsMustTail) {
2964 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2965 for (const auto &F : Forwards) {
2966 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2967 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2971 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2972 // don't need this because the eligibility check rejects calls that require
2973 // shuffling arguments passed in memory.
2974 if (!IsSibcall && isTailCall) {
2975 // Force all the incoming stack arguments to be loaded from the stack
2976 // before any new outgoing arguments are stored to the stack, because the
2977 // outgoing stack slots may alias the incoming argument stack slots, and
2978 // the alias isn't otherwise explicit. This is slightly more conservative
2979 // than necessary, because it means that each store effectively depends
2980 // on every argument instead of just those arguments it would clobber.
2981 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2983 SmallVector<SDValue, 8> MemOpChains2;
2986 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2987 CCValAssign &VA = ArgLocs[i];
2990 assert(VA.isMemLoc());
2991 SDValue Arg = OutVals[i];
2992 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2993 // Skip inalloca arguments. They don't require any work.
2994 if (Flags.isInAlloca())
2996 // Create frame index.
2997 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2998 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2999 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3000 FIN = DAG.getFrameIndex(FI, getPointerTy());
3002 if (Flags.isByVal()) {
3003 // Copy relative to framepointer.
3004 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3005 if (!StackPtr.getNode())
3006 StackPtr = DAG.getCopyFromReg(Chain, dl,
3007 RegInfo->getStackRegister(),
3009 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3011 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3015 // Store relative to framepointer.
3016 MemOpChains2.push_back(
3017 DAG.getStore(ArgChain, dl, Arg, FIN,
3018 MachinePointerInfo::getFixedStack(FI),
3023 if (!MemOpChains2.empty())
3024 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3026 // Store the return address to the appropriate stack slot.
3027 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3028 getPointerTy(), RegInfo->getSlotSize(),
3032 // Build a sequence of copy-to-reg nodes chained together with token chain
3033 // and flag operands which copy the outgoing args into registers.
3035 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3036 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3037 RegsToPass[i].second, InFlag);
3038 InFlag = Chain.getValue(1);
3041 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3042 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3043 // In the 64-bit large code model, we have to make all calls
3044 // through a register, since the call instruction's 32-bit
3045 // pc-relative offset may not be large enough to hold the whole
3047 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3048 // If the callee is a GlobalAddress node (quite common, every direct call
3049 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3052 // We should use extra load for direct calls to dllimported functions in
3054 const GlobalValue *GV = G->getGlobal();
3055 if (!GV->hasDLLImportStorageClass()) {
3056 unsigned char OpFlags = 0;
3057 bool ExtraLoad = false;
3058 unsigned WrapperKind = ISD::DELETED_NODE;
3060 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3061 // external symbols most go through the PLT in PIC mode. If the symbol
3062 // has hidden or protected visibility, or if it is static or local, then
3063 // we don't need to use the PLT - we can directly call it.
3064 if (Subtarget->isTargetELF() &&
3065 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3066 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3067 OpFlags = X86II::MO_PLT;
3068 } else if (Subtarget->isPICStyleStubAny() &&
3069 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3070 (!Subtarget->getTargetTriple().isMacOSX() ||
3071 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3072 // PC-relative references to external symbols should go through $stub,
3073 // unless we're building with the leopard linker or later, which
3074 // automatically synthesizes these stubs.
3075 OpFlags = X86II::MO_DARWIN_STUB;
3076 } else if (Subtarget->isPICStyleRIPRel() &&
3077 isa<Function>(GV) &&
3078 cast<Function>(GV)->getAttributes().
3079 hasAttribute(AttributeSet::FunctionIndex,
3080 Attribute::NonLazyBind)) {
3081 // If the function is marked as non-lazy, generate an indirect call
3082 // which loads from the GOT directly. This avoids runtime overhead
3083 // at the cost of eager binding (and one extra byte of encoding).
3084 OpFlags = X86II::MO_GOTPCREL;
3085 WrapperKind = X86ISD::WrapperRIP;
3089 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3090 G->getOffset(), OpFlags);
3092 // Add a wrapper if needed.
3093 if (WrapperKind != ISD::DELETED_NODE)
3094 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3095 // Add extra indirection if needed.
3097 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3098 MachinePointerInfo::getGOT(),
3099 false, false, false, 0);
3101 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3102 unsigned char OpFlags = 0;
3104 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3105 // external symbols should go through the PLT.
3106 if (Subtarget->isTargetELF() &&
3107 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3108 OpFlags = X86II::MO_PLT;
3109 } else if (Subtarget->isPICStyleStubAny() &&
3110 (!Subtarget->getTargetTriple().isMacOSX() ||
3111 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3112 // PC-relative references to external symbols should go through $stub,
3113 // unless we're building with the leopard linker or later, which
3114 // automatically synthesizes these stubs.
3115 OpFlags = X86II::MO_DARWIN_STUB;
3118 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3120 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3121 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3122 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3125 // Returns a chain & a flag for retval copy to use.
3126 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3127 SmallVector<SDValue, 8> Ops;
3129 if (!IsSibcall && isTailCall) {
3130 Chain = DAG.getCALLSEQ_END(Chain,
3131 DAG.getIntPtrConstant(NumBytesToPop, true),
3132 DAG.getIntPtrConstant(0, true), InFlag, dl);
3133 InFlag = Chain.getValue(1);
3136 Ops.push_back(Chain);
3137 Ops.push_back(Callee);
3140 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3142 // Add argument registers to the end of the list so that they are known live
3144 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3145 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3146 RegsToPass[i].second.getValueType()));
3148 // Add a register mask operand representing the call-preserved registers.
3149 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3150 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3151 assert(Mask && "Missing call preserved mask for calling convention");
3152 Ops.push_back(DAG.getRegisterMask(Mask));
3154 if (InFlag.getNode())
3155 Ops.push_back(InFlag);
3159 //// If this is the first return lowered for this function, add the regs
3160 //// to the liveout set for the function.
3161 // This isn't right, although it's probably harmless on x86; liveouts
3162 // should be computed from returns not tail calls. Consider a void
3163 // function making a tail call to a function returning int.
3164 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3167 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3168 InFlag = Chain.getValue(1);
3170 // Create the CALLSEQ_END node.
3171 unsigned NumBytesForCalleeToPop;
3172 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3173 DAG.getTarget().Options.GuaranteedTailCallOpt))
3174 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3175 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3176 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3177 SR == StackStructReturn)
3178 // If this is a call to a struct-return function, the callee
3179 // pops the hidden struct pointer, so we have to push it back.
3180 // This is common for Darwin/X86, Linux & Mingw32 targets.
3181 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3182 NumBytesForCalleeToPop = 4;
3184 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3186 // Returns a flag for retval copy to use.
3188 Chain = DAG.getCALLSEQ_END(Chain,
3189 DAG.getIntPtrConstant(NumBytesToPop, true),
3190 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3193 InFlag = Chain.getValue(1);
3196 // Handle result values, copying them out of physregs into vregs that we
3198 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3199 Ins, dl, DAG, InVals);
3202 //===----------------------------------------------------------------------===//
3203 // Fast Calling Convention (tail call) implementation
3204 //===----------------------------------------------------------------------===//
3206 // Like std call, callee cleans arguments, convention except that ECX is
3207 // reserved for storing the tail called function address. Only 2 registers are
3208 // free for argument passing (inreg). Tail call optimization is performed
3210 // * tailcallopt is enabled
3211 // * caller/callee are fastcc
3212 // On X86_64 architecture with GOT-style position independent code only local
3213 // (within module) calls are supported at the moment.
3214 // To keep the stack aligned according to platform abi the function
3215 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3216 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3217 // If a tail called function callee has more arguments than the caller the
3218 // caller needs to make sure that there is room to move the RETADDR to. This is
3219 // achieved by reserving an area the size of the argument delta right after the
3220 // original RETADDR, but before the saved framepointer or the spilled registers
3221 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3233 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3234 /// for a 16 byte align requirement.
3236 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3237 SelectionDAG& DAG) const {
3238 MachineFunction &MF = DAG.getMachineFunction();
3239 const TargetMachine &TM = MF.getTarget();
3240 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3241 TM.getSubtargetImpl()->getRegisterInfo());
3242 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3243 unsigned StackAlignment = TFI.getStackAlignment();
3244 uint64_t AlignMask = StackAlignment - 1;
3245 int64_t Offset = StackSize;
3246 unsigned SlotSize = RegInfo->getSlotSize();
3247 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3248 // Number smaller than 12 so just add the difference.
3249 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3251 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3252 Offset = ((~AlignMask) & Offset) + StackAlignment +
3253 (StackAlignment-SlotSize);
3258 /// MatchingStackOffset - Return true if the given stack call argument is
3259 /// already available in the same position (relatively) of the caller's
3260 /// incoming argument stack.
3262 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3263 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3264 const X86InstrInfo *TII) {
3265 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3267 if (Arg.getOpcode() == ISD::CopyFromReg) {
3268 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3269 if (!TargetRegisterInfo::isVirtualRegister(VR))
3271 MachineInstr *Def = MRI->getVRegDef(VR);
3274 if (!Flags.isByVal()) {
3275 if (!TII->isLoadFromStackSlot(Def, FI))
3278 unsigned Opcode = Def->getOpcode();
3279 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3280 Def->getOperand(1).isFI()) {
3281 FI = Def->getOperand(1).getIndex();
3282 Bytes = Flags.getByValSize();
3286 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3287 if (Flags.isByVal())
3288 // ByVal argument is passed in as a pointer but it's now being
3289 // dereferenced. e.g.
3290 // define @foo(%struct.X* %A) {
3291 // tail call @bar(%struct.X* byval %A)
3294 SDValue Ptr = Ld->getBasePtr();
3295 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3298 FI = FINode->getIndex();
3299 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3300 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3301 FI = FINode->getIndex();
3302 Bytes = Flags.getByValSize();
3306 assert(FI != INT_MAX);
3307 if (!MFI->isFixedObjectIndex(FI))
3309 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3312 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3313 /// for tail call optimization. Targets which want to do tail call
3314 /// optimization should implement this function.
3316 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3317 CallingConv::ID CalleeCC,
3319 bool isCalleeStructRet,
3320 bool isCallerStructRet,
3322 const SmallVectorImpl<ISD::OutputArg> &Outs,
3323 const SmallVectorImpl<SDValue> &OutVals,
3324 const SmallVectorImpl<ISD::InputArg> &Ins,
3325 SelectionDAG &DAG) const {
3326 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3329 // If -tailcallopt is specified, make fastcc functions tail-callable.
3330 const MachineFunction &MF = DAG.getMachineFunction();
3331 const Function *CallerF = MF.getFunction();
3333 // If the function return type is x86_fp80 and the callee return type is not,
3334 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3335 // perform a tailcall optimization here.
3336 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3339 CallingConv::ID CallerCC = CallerF->getCallingConv();
3340 bool CCMatch = CallerCC == CalleeCC;
3341 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3342 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3344 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3345 if (IsTailCallConvention(CalleeCC) && CCMatch)
3350 // Look for obvious safe cases to perform tail call optimization that do not
3351 // require ABI changes. This is what gcc calls sibcall.
3353 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3354 // emit a special epilogue.
3355 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3356 DAG.getSubtarget().getRegisterInfo());
3357 if (RegInfo->needsStackRealignment(MF))
3360 // Also avoid sibcall optimization if either caller or callee uses struct
3361 // return semantics.
3362 if (isCalleeStructRet || isCallerStructRet)
3365 // An stdcall/thiscall caller is expected to clean up its arguments; the
3366 // callee isn't going to do that.
3367 // FIXME: this is more restrictive than needed. We could produce a tailcall
3368 // when the stack adjustment matches. For example, with a thiscall that takes
3369 // only one argument.
3370 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3371 CallerCC == CallingConv::X86_ThisCall))
3374 // Do not sibcall optimize vararg calls unless all arguments are passed via
3376 if (isVarArg && !Outs.empty()) {
3378 // Optimizing for varargs on Win64 is unlikely to be safe without
3379 // additional testing.
3380 if (IsCalleeWin64 || IsCallerWin64)
3383 SmallVector<CCValAssign, 16> ArgLocs;
3384 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3387 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3388 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3389 if (!ArgLocs[i].isRegLoc())
3393 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3394 // stack. Therefore, if it's not used by the call it is not safe to optimize
3395 // this into a sibcall.
3396 bool Unused = false;
3397 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3404 SmallVector<CCValAssign, 16> RVLocs;
3405 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3407 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3408 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3409 CCValAssign &VA = RVLocs[i];
3410 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3415 // If the calling conventions do not match, then we'd better make sure the
3416 // results are returned in the same way as what the caller expects.
3418 SmallVector<CCValAssign, 16> RVLocs1;
3419 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3421 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3423 SmallVector<CCValAssign, 16> RVLocs2;
3424 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3426 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3428 if (RVLocs1.size() != RVLocs2.size())
3430 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3431 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3433 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3435 if (RVLocs1[i].isRegLoc()) {
3436 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3439 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3445 // If the callee takes no arguments then go on to check the results of the
3447 if (!Outs.empty()) {
3448 // Check if stack adjustment is needed. For now, do not do this if any
3449 // argument is passed on the stack.
3450 SmallVector<CCValAssign, 16> ArgLocs;
3451 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3454 // Allocate shadow area for Win64
3456 CCInfo.AllocateStack(32, 8);
3458 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3459 if (CCInfo.getNextStackOffset()) {
3460 MachineFunction &MF = DAG.getMachineFunction();
3461 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3464 // Check if the arguments are already laid out in the right way as
3465 // the caller's fixed stack objects.
3466 MachineFrameInfo *MFI = MF.getFrameInfo();
3467 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3468 const X86InstrInfo *TII =
3469 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3470 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3471 CCValAssign &VA = ArgLocs[i];
3472 SDValue Arg = OutVals[i];
3473 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3474 if (VA.getLocInfo() == CCValAssign::Indirect)
3476 if (!VA.isRegLoc()) {
3477 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3484 // If the tailcall address may be in a register, then make sure it's
3485 // possible to register allocate for it. In 32-bit, the call address can
3486 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3487 // callee-saved registers are restored. These happen to be the same
3488 // registers used to pass 'inreg' arguments so watch out for those.
3489 if (!Subtarget->is64Bit() &&
3490 ((!isa<GlobalAddressSDNode>(Callee) &&
3491 !isa<ExternalSymbolSDNode>(Callee)) ||
3492 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3493 unsigned NumInRegs = 0;
3494 // In PIC we need an extra register to formulate the address computation
3496 unsigned MaxInRegs =
3497 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3499 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3500 CCValAssign &VA = ArgLocs[i];
3503 unsigned Reg = VA.getLocReg();
3506 case X86::EAX: case X86::EDX: case X86::ECX:
3507 if (++NumInRegs == MaxInRegs)
3519 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3520 const TargetLibraryInfo *libInfo) const {
3521 return X86::createFastISel(funcInfo, libInfo);
3524 //===----------------------------------------------------------------------===//
3525 // Other Lowering Hooks
3526 //===----------------------------------------------------------------------===//
3528 static bool MayFoldLoad(SDValue Op) {
3529 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3532 static bool MayFoldIntoStore(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3536 static bool isTargetShuffle(unsigned Opcode) {
3538 default: return false;
3539 case X86ISD::BLENDI:
3540 case X86ISD::PSHUFB:
3541 case X86ISD::PSHUFD:
3542 case X86ISD::PSHUFHW:
3543 case X86ISD::PSHUFLW:
3545 case X86ISD::PALIGNR:
3546 case X86ISD::MOVLHPS:
3547 case X86ISD::MOVLHPD:
3548 case X86ISD::MOVHLPS:
3549 case X86ISD::MOVLPS:
3550 case X86ISD::MOVLPD:
3551 case X86ISD::MOVSHDUP:
3552 case X86ISD::MOVSLDUP:
3553 case X86ISD::MOVDDUP:
3556 case X86ISD::UNPCKL:
3557 case X86ISD::UNPCKH:
3558 case X86ISD::VPERMILPI:
3559 case X86ISD::VPERM2X128:
3560 case X86ISD::VPERMI:
3565 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3566 SDValue V1, SelectionDAG &DAG) {
3568 default: llvm_unreachable("Unknown x86 shuffle node");
3569 case X86ISD::MOVSHDUP:
3570 case X86ISD::MOVSLDUP:
3571 case X86ISD::MOVDDUP:
3572 return DAG.getNode(Opc, dl, VT, V1);
3576 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3577 SDValue V1, unsigned TargetMask,
3578 SelectionDAG &DAG) {
3580 default: llvm_unreachable("Unknown x86 shuffle node");
3581 case X86ISD::PSHUFD:
3582 case X86ISD::PSHUFHW:
3583 case X86ISD::PSHUFLW:
3584 case X86ISD::VPERMILPI:
3585 case X86ISD::VPERMI:
3586 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3590 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3591 SDValue V1, SDValue V2, unsigned TargetMask,
3592 SelectionDAG &DAG) {
3594 default: llvm_unreachable("Unknown x86 shuffle node");
3595 case X86ISD::PALIGNR:
3596 case X86ISD::VALIGN:
3598 case X86ISD::VPERM2X128:
3599 return DAG.getNode(Opc, dl, VT, V1, V2,
3600 DAG.getConstant(TargetMask, MVT::i8));
3604 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3605 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3607 default: llvm_unreachable("Unknown x86 shuffle node");
3608 case X86ISD::MOVLHPS:
3609 case X86ISD::MOVLHPD:
3610 case X86ISD::MOVHLPS:
3611 case X86ISD::MOVLPS:
3612 case X86ISD::MOVLPD:
3615 case X86ISD::UNPCKL:
3616 case X86ISD::UNPCKH:
3617 return DAG.getNode(Opc, dl, VT, V1, V2);
3621 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3622 MachineFunction &MF = DAG.getMachineFunction();
3623 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3624 DAG.getSubtarget().getRegisterInfo());
3625 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3626 int ReturnAddrIndex = FuncInfo->getRAIndex();
3628 if (ReturnAddrIndex == 0) {
3629 // Set up a frame object for the return address.
3630 unsigned SlotSize = RegInfo->getSlotSize();
3631 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3634 FuncInfo->setRAIndex(ReturnAddrIndex);
3637 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3640 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3641 bool hasSymbolicDisplacement) {
3642 // Offset should fit into 32 bit immediate field.
3643 if (!isInt<32>(Offset))
3646 // If we don't have a symbolic displacement - we don't have any extra
3648 if (!hasSymbolicDisplacement)
3651 // FIXME: Some tweaks might be needed for medium code model.
3652 if (M != CodeModel::Small && M != CodeModel::Kernel)
3655 // For small code model we assume that latest object is 16MB before end of 31
3656 // bits boundary. We may also accept pretty large negative constants knowing
3657 // that all objects are in the positive half of address space.
3658 if (M == CodeModel::Small && Offset < 16*1024*1024)
3661 // For kernel code model we know that all object resist in the negative half
3662 // of 32bits address space. We may not accept negative offsets, since they may
3663 // be just off and we may accept pretty large positive ones.
3664 if (M == CodeModel::Kernel && Offset > 0)
3670 /// isCalleePop - Determines whether the callee is required to pop its
3671 /// own arguments. Callee pop is necessary to support tail calls.
3672 bool X86::isCalleePop(CallingConv::ID CallingConv,
3673 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3674 switch (CallingConv) {
3677 case CallingConv::X86_StdCall:
3678 case CallingConv::X86_FastCall:
3679 case CallingConv::X86_ThisCall:
3681 case CallingConv::Fast:
3682 case CallingConv::GHC:
3683 case CallingConv::HiPE:
3690 /// \brief Return true if the condition is an unsigned comparison operation.
3691 static bool isX86CCUnsigned(unsigned X86CC) {
3693 default: llvm_unreachable("Invalid integer condition!");
3694 case X86::COND_E: return true;
3695 case X86::COND_G: return false;
3696 case X86::COND_GE: return false;
3697 case X86::COND_L: return false;
3698 case X86::COND_LE: return false;
3699 case X86::COND_NE: return true;
3700 case X86::COND_B: return true;
3701 case X86::COND_A: return true;
3702 case X86::COND_BE: return true;
3703 case X86::COND_AE: return true;
3705 llvm_unreachable("covered switch fell through?!");
3708 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3709 /// specific condition code, returning the condition code and the LHS/RHS of the
3710 /// comparison to make.
3711 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3712 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3714 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3715 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3716 // X > -1 -> X == 0, jump !sign.
3717 RHS = DAG.getConstant(0, RHS.getValueType());
3718 return X86::COND_NS;
3720 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3721 // X < 0 -> X == 0, jump on sign.
3724 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3726 RHS = DAG.getConstant(0, RHS.getValueType());
3727 return X86::COND_LE;
3731 switch (SetCCOpcode) {
3732 default: llvm_unreachable("Invalid integer condition!");
3733 case ISD::SETEQ: return X86::COND_E;
3734 case ISD::SETGT: return X86::COND_G;
3735 case ISD::SETGE: return X86::COND_GE;
3736 case ISD::SETLT: return X86::COND_L;
3737 case ISD::SETLE: return X86::COND_LE;
3738 case ISD::SETNE: return X86::COND_NE;
3739 case ISD::SETULT: return X86::COND_B;
3740 case ISD::SETUGT: return X86::COND_A;
3741 case ISD::SETULE: return X86::COND_BE;
3742 case ISD::SETUGE: return X86::COND_AE;
3746 // First determine if it is required or is profitable to flip the operands.
3748 // If LHS is a foldable load, but RHS is not, flip the condition.
3749 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3750 !ISD::isNON_EXTLoad(RHS.getNode())) {
3751 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3752 std::swap(LHS, RHS);
3755 switch (SetCCOpcode) {
3761 std::swap(LHS, RHS);
3765 // On a floating point condition, the flags are set as follows:
3767 // 0 | 0 | 0 | X > Y
3768 // 0 | 0 | 1 | X < Y
3769 // 1 | 0 | 0 | X == Y
3770 // 1 | 1 | 1 | unordered
3771 switch (SetCCOpcode) {
3772 default: llvm_unreachable("Condcode should be pre-legalized away");
3774 case ISD::SETEQ: return X86::COND_E;
3775 case ISD::SETOLT: // flipped
3777 case ISD::SETGT: return X86::COND_A;
3778 case ISD::SETOLE: // flipped
3780 case ISD::SETGE: return X86::COND_AE;
3781 case ISD::SETUGT: // flipped
3783 case ISD::SETLT: return X86::COND_B;
3784 case ISD::SETUGE: // flipped
3786 case ISD::SETLE: return X86::COND_BE;
3788 case ISD::SETNE: return X86::COND_NE;
3789 case ISD::SETUO: return X86::COND_P;
3790 case ISD::SETO: return X86::COND_NP;
3792 case ISD::SETUNE: return X86::COND_INVALID;
3796 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3797 /// code. Current x86 isa includes the following FP cmov instructions:
3798 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3799 static bool hasFPCMov(unsigned X86CC) {
3815 /// isFPImmLegal - Returns true if the target can instruction select the
3816 /// specified FP immediate natively. If false, the legalizer will
3817 /// materialize the FP immediate as a load from a constant pool.
3818 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3819 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3820 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3826 /// \brief Returns true if it is beneficial to convert a load of a constant
3827 /// to just the constant itself.
3828 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3830 assert(Ty->isIntegerTy());
3832 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3833 if (BitSize == 0 || BitSize > 64)
3838 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3839 /// the specified range (L, H].
3840 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3841 return (Val < 0) || (Val >= Low && Val < Hi);
3844 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3845 /// specified value.
3846 static bool isUndefOrEqual(int Val, int CmpVal) {
3847 return (Val < 0 || Val == CmpVal);
3850 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3851 /// from position Pos and ending in Pos+Size, falls within the specified
3852 /// sequential range (L, L+Pos]. or is undef.
3853 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3854 unsigned Pos, unsigned Size, int Low) {
3855 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3856 if (!isUndefOrEqual(Mask[i], Low))
3861 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3862 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3863 /// operand - by default will match for first operand.
3864 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3865 bool TestSecondOperand = false) {
3866 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3867 VT != MVT::v2f64 && VT != MVT::v2i64)
3870 unsigned NumElems = VT.getVectorNumElements();
3871 unsigned Lo = TestSecondOperand ? NumElems : 0;
3872 unsigned Hi = Lo + NumElems;
3874 for (unsigned i = 0; i < NumElems; ++i)
3875 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3881 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3882 /// is suitable for input to PSHUFHW.
3883 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3884 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3887 // Lower quadword copied in order or undef.
3888 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3891 // Upper quadword shuffled.
3892 for (unsigned i = 4; i != 8; ++i)
3893 if (!isUndefOrInRange(Mask[i], 4, 8))
3896 if (VT == MVT::v16i16) {
3897 // Lower quadword copied in order or undef.
3898 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3901 // Upper quadword shuffled.
3902 for (unsigned i = 12; i != 16; ++i)
3903 if (!isUndefOrInRange(Mask[i], 12, 16))
3910 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3911 /// is suitable for input to PSHUFLW.
3912 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3913 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3916 // Upper quadword copied in order.
3917 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3920 // Lower quadword shuffled.
3921 for (unsigned i = 0; i != 4; ++i)
3922 if (!isUndefOrInRange(Mask[i], 0, 4))
3925 if (VT == MVT::v16i16) {
3926 // Upper quadword copied in order.
3927 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3930 // Lower quadword shuffled.
3931 for (unsigned i = 8; i != 12; ++i)
3932 if (!isUndefOrInRange(Mask[i], 8, 12))
3939 /// \brief Return true if the mask specifies a shuffle of elements that is
3940 /// suitable for input to intralane (palignr) or interlane (valign) vector
3942 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3943 unsigned NumElts = VT.getVectorNumElements();
3944 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3945 unsigned NumLaneElts = NumElts/NumLanes;
3947 // Do not handle 64-bit element shuffles with palignr.
3948 if (NumLaneElts == 2)
3951 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3953 for (i = 0; i != NumLaneElts; ++i) {
3958 // Lane is all undef, go to next lane
3959 if (i == NumLaneElts)
3962 int Start = Mask[i+l];
3964 // Make sure its in this lane in one of the sources
3965 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3966 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3969 // If not lane 0, then we must match lane 0
3970 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3973 // Correct second source to be contiguous with first source
3974 if (Start >= (int)NumElts)
3975 Start -= NumElts - NumLaneElts;
3977 // Make sure we're shifting in the right direction.
3978 if (Start <= (int)(i+l))
3983 // Check the rest of the elements to see if they are consecutive.
3984 for (++i; i != NumLaneElts; ++i) {
3985 int Idx = Mask[i+l];
3987 // Make sure its in this lane
3988 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3989 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3992 // If not lane 0, then we must match lane 0
3993 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3996 if (Idx >= (int)NumElts)
3997 Idx -= NumElts - NumLaneElts;
3999 if (!isUndefOrEqual(Idx, Start+i))
4008 /// \brief Return true if the node specifies a shuffle of elements that is
4009 /// suitable for input to PALIGNR.
4010 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4011 const X86Subtarget *Subtarget) {
4012 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4013 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4014 VT.is512BitVector())
4015 // FIXME: Add AVX512BW.
4018 return isAlignrMask(Mask, VT, false);
4021 /// \brief Return true if the node specifies a shuffle of elements that is
4022 /// suitable for input to VALIGN.
4023 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4024 const X86Subtarget *Subtarget) {
4025 // FIXME: Add AVX512VL.
4026 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4028 return isAlignrMask(Mask, VT, true);
4031 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4032 /// the two vector operands have swapped position.
4033 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4034 unsigned NumElems) {
4035 for (unsigned i = 0; i != NumElems; ++i) {
4039 else if (idx < (int)NumElems)
4040 Mask[i] = idx + NumElems;
4042 Mask[i] = idx - NumElems;
4046 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4047 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4048 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4049 /// reverse of what x86 shuffles want.
4050 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4052 unsigned NumElems = VT.getVectorNumElements();
4053 unsigned NumLanes = VT.getSizeInBits()/128;
4054 unsigned NumLaneElems = NumElems/NumLanes;
4056 if (NumLaneElems != 2 && NumLaneElems != 4)
4059 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4060 bool symetricMaskRequired =
4061 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4063 // VSHUFPSY divides the resulting vector into 4 chunks.
4064 // The sources are also splitted into 4 chunks, and each destination
4065 // chunk must come from a different source chunk.
4067 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4068 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4070 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4071 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4073 // VSHUFPDY divides the resulting vector into 4 chunks.
4074 // The sources are also splitted into 4 chunks, and each destination
4075 // chunk must come from a different source chunk.
4077 // SRC1 => X3 X2 X1 X0
4078 // SRC2 => Y3 Y2 Y1 Y0
4080 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4082 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4083 unsigned HalfLaneElems = NumLaneElems/2;
4084 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4085 for (unsigned i = 0; i != NumLaneElems; ++i) {
4086 int Idx = Mask[i+l];
4087 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4088 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4090 // For VSHUFPSY, the mask of the second half must be the same as the
4091 // first but with the appropriate offsets. This works in the same way as
4092 // VPERMILPS works with masks.
4093 if (!symetricMaskRequired || Idx < 0)
4095 if (MaskVal[i] < 0) {
4096 MaskVal[i] = Idx - l;
4099 if ((signed)(Idx - l) != MaskVal[i])
4107 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4108 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4109 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4110 if (!VT.is128BitVector())
4113 unsigned NumElems = VT.getVectorNumElements();
4118 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4119 return isUndefOrEqual(Mask[0], 6) &&
4120 isUndefOrEqual(Mask[1], 7) &&
4121 isUndefOrEqual(Mask[2], 2) &&
4122 isUndefOrEqual(Mask[3], 3);
4125 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4126 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4128 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4129 if (!VT.is128BitVector())
4132 unsigned NumElems = VT.getVectorNumElements();
4137 return isUndefOrEqual(Mask[0], 2) &&
4138 isUndefOrEqual(Mask[1], 3) &&
4139 isUndefOrEqual(Mask[2], 2) &&
4140 isUndefOrEqual(Mask[3], 3);
4143 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4144 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4145 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4146 if (!VT.is128BitVector())
4149 unsigned NumElems = VT.getVectorNumElements();
4151 if (NumElems != 2 && NumElems != 4)
4154 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4155 if (!isUndefOrEqual(Mask[i], i + NumElems))
4158 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4159 if (!isUndefOrEqual(Mask[i], i))
4165 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4166 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4167 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4168 if (!VT.is128BitVector())
4171 unsigned NumElems = VT.getVectorNumElements();
4173 if (NumElems != 2 && NumElems != 4)
4176 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4177 if (!isUndefOrEqual(Mask[i], i))
4180 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4181 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4187 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4188 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4189 /// i. e: If all but one element come from the same vector.
4190 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4191 // TODO: Deal with AVX's VINSERTPS
4192 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4195 unsigned CorrectPosV1 = 0;
4196 unsigned CorrectPosV2 = 0;
4197 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4198 if (Mask[i] == -1) {
4206 else if (Mask[i] == i + 4)
4210 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4211 // We have 3 elements (undefs count as elements from any vector) from one
4212 // vector, and one from another.
4219 // Some special combinations that can be optimized.
4222 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4223 SelectionDAG &DAG) {
4224 MVT VT = SVOp->getSimpleValueType(0);
4227 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4230 ArrayRef<int> Mask = SVOp->getMask();
4232 // These are the special masks that may be optimized.
4233 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4234 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4235 bool MatchEvenMask = true;
4236 bool MatchOddMask = true;
4237 for (int i=0; i<8; ++i) {
4238 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4239 MatchEvenMask = false;
4240 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4241 MatchOddMask = false;
4244 if (!MatchEvenMask && !MatchOddMask)
4247 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4249 SDValue Op0 = SVOp->getOperand(0);
4250 SDValue Op1 = SVOp->getOperand(1);
4252 if (MatchEvenMask) {
4253 // Shift the second operand right to 32 bits.
4254 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4255 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4257 // Shift the first operand left to 32 bits.
4258 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4259 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4261 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4262 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4265 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4266 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4267 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4268 bool HasInt256, bool V2IsSplat = false) {
4270 assert(VT.getSizeInBits() >= 128 &&
4271 "Unsupported vector type for unpckl");
4273 unsigned NumElts = VT.getVectorNumElements();
4274 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4275 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4278 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4279 "Unsupported vector type for unpckh");
4281 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4282 unsigned NumLanes = VT.getSizeInBits()/128;
4283 unsigned NumLaneElts = NumElts/NumLanes;
4285 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4286 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4287 int BitI = Mask[l+i];
4288 int BitI1 = Mask[l+i+1];
4289 if (!isUndefOrEqual(BitI, j))
4292 if (!isUndefOrEqual(BitI1, NumElts))
4295 if (!isUndefOrEqual(BitI1, j + NumElts))
4304 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4305 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4306 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4307 bool HasInt256, bool V2IsSplat = false) {
4308 assert(VT.getSizeInBits() >= 128 &&
4309 "Unsupported vector type for unpckh");
4311 unsigned NumElts = VT.getVectorNumElements();
4312 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4313 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4316 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4317 "Unsupported vector type for unpckh");
4319 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4320 unsigned NumLanes = VT.getSizeInBits()/128;
4321 unsigned NumLaneElts = NumElts/NumLanes;
4323 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4324 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4325 int BitI = Mask[l+i];
4326 int BitI1 = Mask[l+i+1];
4327 if (!isUndefOrEqual(BitI, j))
4330 if (isUndefOrEqual(BitI1, NumElts))
4333 if (!isUndefOrEqual(BitI1, j+NumElts))
4341 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4342 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4344 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4345 unsigned NumElts = VT.getVectorNumElements();
4346 bool Is256BitVec = VT.is256BitVector();
4348 if (VT.is512BitVector())
4350 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4351 "Unsupported vector type for unpckh");
4353 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4354 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4357 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4358 // FIXME: Need a better way to get rid of this, there's no latency difference
4359 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4360 // the former later. We should also remove the "_undef" special mask.
4361 if (NumElts == 4 && Is256BitVec)
4364 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4365 // independently on 128-bit lanes.
4366 unsigned NumLanes = VT.getSizeInBits()/128;
4367 unsigned NumLaneElts = NumElts/NumLanes;
4369 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4370 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4371 int BitI = Mask[l+i];
4372 int BitI1 = Mask[l+i+1];
4374 if (!isUndefOrEqual(BitI, j))
4376 if (!isUndefOrEqual(BitI1, j))
4384 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4385 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4387 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4388 unsigned NumElts = VT.getVectorNumElements();
4390 if (VT.is512BitVector())
4393 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4394 "Unsupported vector type for unpckh");
4396 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4397 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4400 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4401 // independently on 128-bit lanes.
4402 unsigned NumLanes = VT.getSizeInBits()/128;
4403 unsigned NumLaneElts = NumElts/NumLanes;
4405 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4406 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4407 int BitI = Mask[l+i];
4408 int BitI1 = Mask[l+i+1];
4409 if (!isUndefOrEqual(BitI, j))
4411 if (!isUndefOrEqual(BitI1, j))
4418 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4419 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4420 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4421 if (!VT.is512BitVector())
4424 unsigned NumElts = VT.getVectorNumElements();
4425 unsigned HalfSize = NumElts/2;
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4432 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4433 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4441 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4442 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4443 /// MOVSD, and MOVD, i.e. setting the lowest element.
4444 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4445 if (VT.getVectorElementType().getSizeInBits() < 32)
4447 if (!VT.is128BitVector())
4450 unsigned NumElts = VT.getVectorNumElements();
4452 if (!isUndefOrEqual(Mask[0], NumElts))
4455 for (unsigned i = 1; i != NumElts; ++i)
4456 if (!isUndefOrEqual(Mask[i], i))
4462 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4463 /// as permutations between 128-bit chunks or halves. As an example: this
4465 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4466 /// The first half comes from the second half of V1 and the second half from the
4467 /// the second half of V2.
4468 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4469 if (!HasFp256 || !VT.is256BitVector())
4472 // The shuffle result is divided into half A and half B. In total the two
4473 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4474 // B must come from C, D, E or F.
4475 unsigned HalfSize = VT.getVectorNumElements()/2;
4476 bool MatchA = false, MatchB = false;
4478 // Check if A comes from one of C, D, E, F.
4479 for (unsigned Half = 0; Half != 4; ++Half) {
4480 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4486 // Check if B comes from one of C, D, E, F.
4487 for (unsigned Half = 0; Half != 4; ++Half) {
4488 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4494 return MatchA && MatchB;
4497 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4498 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4499 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4500 MVT VT = SVOp->getSimpleValueType(0);
4502 unsigned HalfSize = VT.getVectorNumElements()/2;
4504 unsigned FstHalf = 0, SndHalf = 0;
4505 for (unsigned i = 0; i < HalfSize; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4511 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4512 if (SVOp->getMaskElt(i) > 0) {
4513 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4518 return (FstHalf | (SndHalf << 4));
4521 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4522 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4523 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4527 unsigned NumElts = VT.getVectorNumElements();
4529 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4530 for (unsigned i = 0; i != NumElts; ++i) {
4533 Imm8 |= Mask[i] << (i*2);
4538 unsigned LaneSize = 4;
4539 SmallVector<int, 4> MaskVal(LaneSize, -1);
4541 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4542 for (unsigned i = 0; i != LaneSize; ++i) {
4543 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4547 if (MaskVal[i] < 0) {
4548 MaskVal[i] = Mask[i+l] - l;
4549 Imm8 |= MaskVal[i] << (i*2);
4552 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4559 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4560 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4561 /// Note that VPERMIL mask matching is different depending whether theunderlying
4562 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4563 /// to the same elements of the low, but to the higher half of the source.
4564 /// In VPERMILPD the two lanes could be shuffled independently of each other
4565 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4566 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4567 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4568 if (VT.getSizeInBits() < 256 || EltSize < 32)
4570 bool symetricMaskRequired = (EltSize == 32);
4571 unsigned NumElts = VT.getVectorNumElements();
4573 unsigned NumLanes = VT.getSizeInBits()/128;
4574 unsigned LaneSize = NumElts/NumLanes;
4575 // 2 or 4 elements in one lane
4577 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4578 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4579 for (unsigned i = 0; i != LaneSize; ++i) {
4580 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4582 if (symetricMaskRequired) {
4583 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4584 ExpectedMaskVal[i] = Mask[i+l] - l;
4587 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4595 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4596 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4597 /// element of vector 2 and the other elements to come from vector 1 in order.
4598 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4599 bool V2IsSplat = false, bool V2IsUndef = false) {
4600 if (!VT.is128BitVector())
4603 unsigned NumOps = VT.getVectorNumElements();
4604 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4607 if (!isUndefOrEqual(Mask[0], 0))
4610 for (unsigned i = 1; i != NumOps; ++i)
4611 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4612 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4613 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4619 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4620 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4621 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4622 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4623 const X86Subtarget *Subtarget) {
4624 if (!Subtarget->hasSSE3())
4627 unsigned NumElems = VT.getVectorNumElements();
4629 if ((VT.is128BitVector() && NumElems != 4) ||
4630 (VT.is256BitVector() && NumElems != 8) ||
4631 (VT.is512BitVector() && NumElems != 16))
4634 // "i+1" is the value the indexed mask element must have
4635 for (unsigned i = 0; i != NumElems; i += 2)
4636 if (!isUndefOrEqual(Mask[i], i+1) ||
4637 !isUndefOrEqual(Mask[i+1], i+1))
4643 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4644 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4645 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4646 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4647 const X86Subtarget *Subtarget) {
4648 if (!Subtarget->hasSSE3())
4651 unsigned NumElems = VT.getVectorNumElements();
4653 if ((VT.is128BitVector() && NumElems != 4) ||
4654 (VT.is256BitVector() && NumElems != 8) ||
4655 (VT.is512BitVector() && NumElems != 16))
4658 // "i" is the value the indexed mask element must have
4659 for (unsigned i = 0; i != NumElems; i += 2)
4660 if (!isUndefOrEqual(Mask[i], i) ||
4661 !isUndefOrEqual(Mask[i+1], i))
4667 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4668 /// specifies a shuffle of elements that is suitable for input to 256-bit
4669 /// version of MOVDDUP.
4670 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4671 if (!HasFp256 || !VT.is256BitVector())
4674 unsigned NumElts = VT.getVectorNumElements();
4678 for (unsigned i = 0; i != NumElts/2; ++i)
4679 if (!isUndefOrEqual(Mask[i], 0))
4681 for (unsigned i = NumElts/2; i != NumElts; ++i)
4682 if (!isUndefOrEqual(Mask[i], NumElts/2))
4687 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4688 /// specifies a shuffle of elements that is suitable for input to 128-bit
4689 /// version of MOVDDUP.
4690 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4691 if (!VT.is128BitVector())
4694 unsigned e = VT.getVectorNumElements() / 2;
4695 for (unsigned i = 0; i != e; ++i)
4696 if (!isUndefOrEqual(Mask[i], i))
4698 for (unsigned i = 0; i != e; ++i)
4699 if (!isUndefOrEqual(Mask[e+i], i))
4704 /// isVEXTRACTIndex - Return true if the specified
4705 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4706 /// suitable for instruction that extract 128 or 256 bit vectors
4707 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4708 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4709 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4712 // The index should be aligned on a vecWidth-bit boundary.
4714 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4716 MVT VT = N->getSimpleValueType(0);
4717 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4718 bool Result = (Index * ElSize) % vecWidth == 0;
4723 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4724 /// operand specifies a subvector insert that is suitable for input to
4725 /// insertion of 128 or 256-bit subvectors
4726 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4727 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4728 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4730 // The index should be aligned on a vecWidth-bit boundary.
4732 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4734 MVT VT = N->getSimpleValueType(0);
4735 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4736 bool Result = (Index * ElSize) % vecWidth == 0;
4741 bool X86::isVINSERT128Index(SDNode *N) {
4742 return isVINSERTIndex(N, 128);
4745 bool X86::isVINSERT256Index(SDNode *N) {
4746 return isVINSERTIndex(N, 256);
4749 bool X86::isVEXTRACT128Index(SDNode *N) {
4750 return isVEXTRACTIndex(N, 128);
4753 bool X86::isVEXTRACT256Index(SDNode *N) {
4754 return isVEXTRACTIndex(N, 256);
4757 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4758 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4759 /// Handles 128-bit and 256-bit.
4760 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4761 MVT VT = N->getSimpleValueType(0);
4763 assert((VT.getSizeInBits() >= 128) &&
4764 "Unsupported vector type for PSHUF/SHUFP");
4766 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4767 // independently on 128-bit lanes.
4768 unsigned NumElts = VT.getVectorNumElements();
4769 unsigned NumLanes = VT.getSizeInBits()/128;
4770 unsigned NumLaneElts = NumElts/NumLanes;
4772 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4773 "Only supports 2, 4 or 8 elements per lane");
4775 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4777 for (unsigned i = 0; i != NumElts; ++i) {
4778 int Elt = N->getMaskElt(i);
4779 if (Elt < 0) continue;
4780 Elt &= NumLaneElts - 1;
4781 unsigned ShAmt = (i << Shift) % 8;
4782 Mask |= Elt << ShAmt;
4788 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4789 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4790 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4791 MVT VT = N->getSimpleValueType(0);
4793 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4794 "Unsupported vector type for PSHUFHW");
4796 unsigned NumElts = VT.getVectorNumElements();
4799 for (unsigned l = 0; l != NumElts; l += 8) {
4800 // 8 nodes per lane, but we only care about the last 4.
4801 for (unsigned i = 0; i < 4; ++i) {
4802 int Elt = N->getMaskElt(l+i+4);
4803 if (Elt < 0) continue;
4804 Elt &= 0x3; // only 2-bits.
4805 Mask |= Elt << (i * 2);
4812 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4813 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4814 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4815 MVT VT = N->getSimpleValueType(0);
4817 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4818 "Unsupported vector type for PSHUFHW");
4820 unsigned NumElts = VT.getVectorNumElements();
4823 for (unsigned l = 0; l != NumElts; l += 8) {
4824 // 8 nodes per lane, but we only care about the first 4.
4825 for (unsigned i = 0; i < 4; ++i) {
4826 int Elt = N->getMaskElt(l+i);
4827 if (Elt < 0) continue;
4828 Elt &= 0x3; // only 2-bits
4829 Mask |= Elt << (i * 2);
4836 /// \brief Return the appropriate immediate to shuffle the specified
4837 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4838 /// VALIGN (if Interlane is true) instructions.
4839 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4841 MVT VT = SVOp->getSimpleValueType(0);
4842 unsigned EltSize = InterLane ? 1 :
4843 VT.getVectorElementType().getSizeInBits() >> 3;
4845 unsigned NumElts = VT.getVectorNumElements();
4846 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4847 unsigned NumLaneElts = NumElts/NumLanes;
4851 for (i = 0; i != NumElts; ++i) {
4852 Val = SVOp->getMaskElt(i);
4856 if (Val >= (int)NumElts)
4857 Val -= NumElts - NumLaneElts;
4859 assert(Val - i > 0 && "PALIGNR imm should be positive");
4860 return (Val - i) * EltSize;
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4865 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, false);
4869 /// \brief Return the appropriate immediate to shuffle the specified
4870 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4871 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4872 return getShuffleAlignrImmediate(SVOp, true);
4876 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4877 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4878 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4879 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4882 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4884 MVT VecVT = N->getOperand(0).getSimpleValueType();
4885 MVT ElVT = VecVT.getVectorElementType();
4887 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4888 return Index / NumElemsPerChunk;
4891 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4892 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4893 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4894 llvm_unreachable("Illegal insert subvector for VINSERT");
4897 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4899 MVT VecVT = N->getSimpleValueType(0);
4900 MVT ElVT = VecVT.getVectorElementType();
4902 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4903 return Index / NumElemsPerChunk;
4906 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4907 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4908 /// and VINSERTI128 instructions.
4909 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4910 return getExtractVEXTRACTImmediate(N, 128);
4913 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4914 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4915 /// and VINSERTI64x4 instructions.
4916 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4917 return getExtractVEXTRACTImmediate(N, 256);
4920 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4921 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4922 /// and VINSERTI128 instructions.
4923 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4924 return getInsertVINSERTImmediate(N, 128);
4927 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4928 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4929 /// and VINSERTI64x4 instructions.
4930 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4931 return getInsertVINSERTImmediate(N, 256);
4934 /// isZero - Returns true if Elt is a constant integer zero
4935 static bool isZero(SDValue V) {
4936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4937 return C && C->isNullValue();
4940 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4942 bool X86::isZeroNode(SDValue Elt) {
4945 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4946 return CFP->getValueAPF().isPosZero();
4950 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4951 /// match movhlps. The lower half elements should come from upper half of
4952 /// V1 (and in order), and the upper half elements should come from the upper
4953 /// half of V2 (and in order).
4954 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4955 if (!VT.is128BitVector())
4957 if (VT.getVectorNumElements() != 4)
4959 for (unsigned i = 0, e = 2; i != e; ++i)
4960 if (!isUndefOrEqual(Mask[i], i+2))
4962 for (unsigned i = 2; i != 4; ++i)
4963 if (!isUndefOrEqual(Mask[i], i+4))
4968 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4969 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4971 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4972 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4974 N = N->getOperand(0).getNode();
4975 if (!ISD::isNON_EXTLoad(N))
4978 *LD = cast<LoadSDNode>(N);
4982 // Test whether the given value is a vector value which will be legalized
4984 static bool WillBeConstantPoolLoad(SDNode *N) {
4985 if (N->getOpcode() != ISD::BUILD_VECTOR)
4988 // Check for any non-constant elements.
4989 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4990 switch (N->getOperand(i).getNode()->getOpcode()) {
4992 case ISD::ConstantFP:
4999 // Vectors of all-zeros and all-ones are materialized with special
5000 // instructions rather than being loaded.
5001 return !ISD::isBuildVectorAllZeros(N) &&
5002 !ISD::isBuildVectorAllOnes(N);
5005 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5006 /// match movlp{s|d}. The lower half elements should come from lower half of
5007 /// V1 (and in order), and the upper half elements should come from the upper
5008 /// half of V2 (and in order). And since V1 will become the source of the
5009 /// MOVLP, it must be either a vector load or a scalar load to vector.
5010 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5011 ArrayRef<int> Mask, MVT VT) {
5012 if (!VT.is128BitVector())
5015 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5017 // Is V2 is a vector load, don't do this transformation. We will try to use
5018 // load folding shufps op.
5019 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5022 unsigned NumElems = VT.getVectorNumElements();
5024 if (NumElems != 2 && NumElems != 4)
5026 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5027 if (!isUndefOrEqual(Mask[i], i))
5029 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5030 if (!isUndefOrEqual(Mask[i], i+NumElems))
5035 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5036 /// to an zero vector.
5037 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5038 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5039 SDValue V1 = N->getOperand(0);
5040 SDValue V2 = N->getOperand(1);
5041 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5042 for (unsigned i = 0; i != NumElems; ++i) {
5043 int Idx = N->getMaskElt(i);
5044 if (Idx >= (int)NumElems) {
5045 unsigned Opc = V2.getOpcode();
5046 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5048 if (Opc != ISD::BUILD_VECTOR ||
5049 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5051 } else if (Idx >= 0) {
5052 unsigned Opc = V1.getOpcode();
5053 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5055 if (Opc != ISD::BUILD_VECTOR ||
5056 !X86::isZeroNode(V1.getOperand(Idx)))
5063 /// getZeroVector - Returns a vector of specified type with all zero elements.
5065 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5066 SelectionDAG &DAG, SDLoc dl) {
5067 assert(VT.isVector() && "Expected a vector type");
5069 // Always build SSE zero vectors as <4 x i32> bitcasted
5070 // to their dest type. This ensures they get CSE'd.
5072 if (VT.is128BitVector()) { // SSE
5073 if (Subtarget->hasSSE2()) { // SSE2
5074 SDValue Cst = DAG.getConstant(0, MVT::i32);
5075 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5077 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5080 } else if (VT.is256BitVector()) { // AVX
5081 if (Subtarget->hasInt256()) { // AVX2
5082 SDValue Cst = DAG.getConstant(0, MVT::i32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5086 // 256-bit logic and arithmetic instructions in AVX are all
5087 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5088 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5089 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5092 } else if (VT.is512BitVector()) { // AVX-512
5093 SDValue Cst = DAG.getConstant(0, MVT::i32);
5094 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5095 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5096 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5097 } else if (VT.getScalarType() == MVT::i1) {
5098 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5099 SDValue Cst = DAG.getConstant(0, MVT::i1);
5100 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5101 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5103 llvm_unreachable("Unexpected vector type");
5105 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5108 /// getOnesVector - Returns a vector of specified type with all bits set.
5109 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5110 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5111 /// Then bitcast to their original type, ensuring they get CSE'd.
5112 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5114 assert(VT.isVector() && "Expected a vector type");
5116 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5118 if (VT.is256BitVector()) {
5119 if (HasInt256) { // AVX2
5120 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5123 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5124 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5126 } else if (VT.is128BitVector()) {
5127 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5129 llvm_unreachable("Unexpected vector type");
5131 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5134 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5135 /// that point to V2 points to its first element.
5136 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5137 for (unsigned i = 0; i != NumElems; ++i) {
5138 if (Mask[i] > (int)NumElems) {
5144 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5145 /// operation of specified width.
5146 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5148 unsigned NumElems = VT.getVectorNumElements();
5149 SmallVector<int, 8> Mask;
5150 Mask.push_back(NumElems);
5151 for (unsigned i = 1; i != NumElems; ++i)
5153 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5156 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5157 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5159 unsigned NumElems = VT.getVectorNumElements();
5160 SmallVector<int, 8> Mask;
5161 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5163 Mask.push_back(i + NumElems);
5165 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5168 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5169 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5171 unsigned NumElems = VT.getVectorNumElements();
5172 SmallVector<int, 8> Mask;
5173 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5174 Mask.push_back(i + Half);
5175 Mask.push_back(i + NumElems + Half);
5177 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5180 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5181 // a generic shuffle instruction because the target has no such instructions.
5182 // Generate shuffles which repeat i16 and i8 several times until they can be
5183 // represented by v4f32 and then be manipulated by target suported shuffles.
5184 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5185 MVT VT = V.getSimpleValueType();
5186 int NumElems = VT.getVectorNumElements();
5189 while (NumElems > 4) {
5190 if (EltNo < NumElems/2) {
5191 V = getUnpackl(DAG, dl, VT, V, V);
5193 V = getUnpackh(DAG, dl, VT, V, V);
5194 EltNo -= NumElems/2;
5201 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5202 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5203 MVT VT = V.getSimpleValueType();
5206 if (VT.is128BitVector()) {
5207 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5208 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5209 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5211 } else if (VT.is256BitVector()) {
5212 // To use VPERMILPS to splat scalars, the second half of indicies must
5213 // refer to the higher part, which is a duplication of the lower one,
5214 // because VPERMILPS can only handle in-lane permutations.
5215 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5216 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5218 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5219 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5222 llvm_unreachable("Vector size not supported");
5224 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5227 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5228 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5229 MVT SrcVT = SV->getSimpleValueType(0);
5230 SDValue V1 = SV->getOperand(0);
5233 int EltNo = SV->getSplatIndex();
5234 int NumElems = SrcVT.getVectorNumElements();
5235 bool Is256BitVec = SrcVT.is256BitVector();
5237 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5238 "Unknown how to promote splat for type");
5240 // Extract the 128-bit part containing the splat element and update
5241 // the splat element index when it refers to the higher register.
5243 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5244 if (EltNo >= NumElems/2)
5245 EltNo -= NumElems/2;
5248 // All i16 and i8 vector types can't be used directly by a generic shuffle
5249 // instruction because the target has no such instruction. Generate shuffles
5250 // which repeat i16 and i8 several times until they fit in i32, and then can
5251 // be manipulated by target suported shuffles.
5252 MVT EltVT = SrcVT.getVectorElementType();
5253 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5254 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5256 // Recreate the 256-bit vector and place the same 128-bit vector
5257 // into the low and high part. This is necessary because we want
5258 // to use VPERM* to shuffle the vectors
5260 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5263 return getLegalSplat(DAG, V1, EltNo);
5266 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5267 /// vector of zero or undef vector. This produces a shuffle where the low
5268 /// element of V2 is swizzled into the zero/undef vector, landing at element
5269 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5270 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5272 const X86Subtarget *Subtarget,
5273 SelectionDAG &DAG) {
5274 MVT VT = V2.getSimpleValueType();
5276 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5277 unsigned NumElems = VT.getVectorNumElements();
5278 SmallVector<int, 16> MaskVec;
5279 for (unsigned i = 0; i != NumElems; ++i)
5280 // If this is the insertion idx, put the low elt of V2 here.
5281 MaskVec.push_back(i == Idx ? NumElems : i);
5282 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5285 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5286 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5287 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5288 /// shuffles which use a single input multiple times, and in those cases it will
5289 /// adjust the mask to only have indices within that single input.
5290 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5291 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5292 unsigned NumElems = VT.getVectorNumElements();
5296 bool IsFakeUnary = false;
5297 switch(N->getOpcode()) {
5298 case X86ISD::BLENDI:
5299 ImmN = N->getOperand(N->getNumOperands()-1);
5300 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5303 ImmN = N->getOperand(N->getNumOperands()-1);
5304 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5305 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5307 case X86ISD::UNPCKH:
5308 DecodeUNPCKHMask(VT, Mask);
5309 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5311 case X86ISD::UNPCKL:
5312 DecodeUNPCKLMask(VT, Mask);
5313 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5315 case X86ISD::MOVHLPS:
5316 DecodeMOVHLPSMask(NumElems, Mask);
5317 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5319 case X86ISD::MOVLHPS:
5320 DecodeMOVLHPSMask(NumElems, Mask);
5321 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5323 case X86ISD::PALIGNR:
5324 ImmN = N->getOperand(N->getNumOperands()-1);
5325 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFD:
5328 case X86ISD::VPERMILPI:
5329 ImmN = N->getOperand(N->getNumOperands()-1);
5330 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5333 case X86ISD::PSHUFHW:
5334 ImmN = N->getOperand(N->getNumOperands()-1);
5335 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5338 case X86ISD::PSHUFLW:
5339 ImmN = N->getOperand(N->getNumOperands()-1);
5340 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5343 case X86ISD::PSHUFB: {
5345 SDValue MaskNode = N->getOperand(1);
5346 while (MaskNode->getOpcode() == ISD::BITCAST)
5347 MaskNode = MaskNode->getOperand(0);
5349 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5350 // If we have a build-vector, then things are easy.
5351 EVT VT = MaskNode.getValueType();
5352 assert(VT.isVector() &&
5353 "Can't produce a non-vector with a build_vector!");
5354 if (!VT.isInteger())
5357 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5359 SmallVector<uint64_t, 32> RawMask;
5360 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5361 SDValue Op = MaskNode->getOperand(i);
5362 if (Op->getOpcode() == ISD::UNDEF) {
5363 RawMask.push_back((uint64_t)SM_SentinelUndef);
5366 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5369 APInt MaskElement = CN->getAPIntValue();
5371 // We now have to decode the element which could be any integer size and
5372 // extract each byte of it.
5373 for (int j = 0; j < NumBytesPerElement; ++j) {
5374 // Note that this is x86 and so always little endian: the low byte is
5375 // the first byte of the mask.
5376 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5377 MaskElement = MaskElement.lshr(8);
5380 DecodePSHUFBMask(RawMask, Mask);
5384 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5388 SDValue Ptr = MaskLoad->getBasePtr();
5389 if (Ptr->getOpcode() == X86ISD::Wrapper)
5390 Ptr = Ptr->getOperand(0);
5392 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5393 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5396 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5397 // FIXME: Support AVX-512 here.
5398 Type *Ty = C->getType();
5399 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5400 Ty->getVectorNumElements() != 32))
5403 DecodePSHUFBMask(C, Mask);
5409 case X86ISD::VPERMI:
5410 ImmN = N->getOperand(N->getNumOperands()-1);
5411 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5415 case X86ISD::MOVSD: {
5416 // The index 0 always comes from the first element of the second source,
5417 // this is why MOVSS and MOVSD are used in the first place. The other
5418 // elements come from the other positions of the first source vector
5419 Mask.push_back(NumElems);
5420 for (unsigned i = 1; i != NumElems; ++i) {
5425 case X86ISD::VPERM2X128:
5426 ImmN = N->getOperand(N->getNumOperands()-1);
5427 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5428 if (Mask.empty()) return false;
5430 case X86ISD::MOVSLDUP:
5431 DecodeMOVSLDUPMask(VT, Mask);
5433 case X86ISD::MOVSHDUP:
5434 DecodeMOVSHDUPMask(VT, Mask);
5436 case X86ISD::MOVDDUP:
5437 case X86ISD::MOVLHPD:
5438 case X86ISD::MOVLPD:
5439 case X86ISD::MOVLPS:
5440 // Not yet implemented
5442 default: llvm_unreachable("unknown target shuffle node");
5445 // If we have a fake unary shuffle, the shuffle mask is spread across two
5446 // inputs that are actually the same node. Re-map the mask to always point
5447 // into the first input.
5450 if (M >= (int)Mask.size())
5456 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5457 /// element of the result of the vector shuffle.
5458 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5461 return SDValue(); // Limit search depth.
5463 SDValue V = SDValue(N, 0);
5464 EVT VT = V.getValueType();
5465 unsigned Opcode = V.getOpcode();
5467 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5468 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5469 int Elt = SV->getMaskElt(Index);
5472 return DAG.getUNDEF(VT.getVectorElementType());
5474 unsigned NumElems = VT.getVectorNumElements();
5475 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5476 : SV->getOperand(1);
5477 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5480 // Recurse into target specific vector shuffles to find scalars.
5481 if (isTargetShuffle(Opcode)) {
5482 MVT ShufVT = V.getSimpleValueType();
5483 unsigned NumElems = ShufVT.getVectorNumElements();
5484 SmallVector<int, 16> ShuffleMask;
5487 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5490 int Elt = ShuffleMask[Index];
5492 return DAG.getUNDEF(ShufVT.getVectorElementType());
5494 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5496 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5500 // Actual nodes that may contain scalar elements
5501 if (Opcode == ISD::BITCAST) {
5502 V = V.getOperand(0);
5503 EVT SrcVT = V.getValueType();
5504 unsigned NumElems = VT.getVectorNumElements();
5506 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5510 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5511 return (Index == 0) ? V.getOperand(0)
5512 : DAG.getUNDEF(VT.getVectorElementType());
5514 if (V.getOpcode() == ISD::BUILD_VECTOR)
5515 return V.getOperand(Index);
5520 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5521 /// shuffle operation which come from a consecutively from a zero. The
5522 /// search can start in two different directions, from left or right.
5523 /// We count undefs as zeros until PreferredNum is reached.
5524 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5525 unsigned NumElems, bool ZerosFromLeft,
5527 unsigned PreferredNum = -1U) {
5528 unsigned NumZeros = 0;
5529 for (unsigned i = 0; i != NumElems; ++i) {
5530 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5531 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5535 if (X86::isZeroNode(Elt))
5537 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5538 NumZeros = std::min(NumZeros + 1, PreferredNum);
5546 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5547 /// correspond consecutively to elements from one of the vector operands,
5548 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5550 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5551 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5552 unsigned NumElems, unsigned &OpNum) {
5553 bool SeenV1 = false;
5554 bool SeenV2 = false;
5556 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5557 int Idx = SVOp->getMaskElt(i);
5558 // Ignore undef indicies
5562 if (Idx < (int)NumElems)
5567 // Only accept consecutive elements from the same vector
5568 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5572 OpNum = SeenV1 ? 0 : 1;
5576 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5577 /// logical left shift of a vector.
5578 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5579 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5581 SVOp->getSimpleValueType(0).getVectorNumElements();
5582 unsigned NumZeros = getNumOfConsecutiveZeros(
5583 SVOp, NumElems, false /* check zeros from right */, DAG,
5584 SVOp->getMaskElt(0));
5590 // Considering the elements in the mask that are not consecutive zeros,
5591 // check if they consecutively come from only one of the source vectors.
5593 // V1 = {X, A, B, C} 0
5595 // vector_shuffle V1, V2 <1, 2, 3, X>
5597 if (!isShuffleMaskConsecutive(SVOp,
5598 0, // Mask Start Index
5599 NumElems-NumZeros, // Mask End Index(exclusive)
5600 NumZeros, // Where to start looking in the src vector
5601 NumElems, // Number of elements in vector
5602 OpSrc)) // Which source operand ?
5607 ShVal = SVOp->getOperand(OpSrc);
5611 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5612 /// logical left shift of a vector.
5613 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5614 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5616 SVOp->getSimpleValueType(0).getVectorNumElements();
5617 unsigned NumZeros = getNumOfConsecutiveZeros(
5618 SVOp, NumElems, true /* check zeros from left */, DAG,
5619 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5625 // Considering the elements in the mask that are not consecutive zeros,
5626 // check if they consecutively come from only one of the source vectors.
5628 // 0 { A, B, X, X } = V2
5630 // vector_shuffle V1, V2 <X, X, 4, 5>
5632 if (!isShuffleMaskConsecutive(SVOp,
5633 NumZeros, // Mask Start Index
5634 NumElems, // Mask End Index(exclusive)
5635 0, // Where to start looking in the src vector
5636 NumElems, // Number of elements in vector
5637 OpSrc)) // Which source operand ?
5642 ShVal = SVOp->getOperand(OpSrc);
5646 /// isVectorShift - Returns true if the shuffle can be implemented as a
5647 /// logical left or right shift of a vector.
5648 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5649 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5650 // Although the logic below support any bitwidth size, there are no
5651 // shift instructions which handle more than 128-bit vectors.
5652 if (!SVOp->getSimpleValueType(0).is128BitVector())
5655 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5656 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5662 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5664 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5665 unsigned NumNonZero, unsigned NumZero,
5667 const X86Subtarget* Subtarget,
5668 const TargetLowering &TLI) {
5675 for (unsigned i = 0; i < 16; ++i) {
5676 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5677 if (ThisIsNonZero && First) {
5679 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5681 V = DAG.getUNDEF(MVT::v8i16);
5686 SDValue ThisElt, LastElt;
5687 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5688 if (LastIsNonZero) {
5689 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5690 MVT::i16, Op.getOperand(i-1));
5692 if (ThisIsNonZero) {
5693 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5694 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5695 ThisElt, DAG.getConstant(8, MVT::i8));
5697 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5701 if (ThisElt.getNode())
5702 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5703 DAG.getIntPtrConstant(i/2));
5707 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5710 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5712 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5713 unsigned NumNonZero, unsigned NumZero,
5715 const X86Subtarget* Subtarget,
5716 const TargetLowering &TLI) {
5723 for (unsigned i = 0; i < 8; ++i) {
5724 bool isNonZero = (NonZeros & (1 << i)) != 0;
5728 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5730 V = DAG.getUNDEF(MVT::v8i16);
5733 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5734 MVT::v8i16, V, Op.getOperand(i),
5735 DAG.getIntPtrConstant(i));
5742 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5743 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5744 unsigned NonZeros, unsigned NumNonZero,
5745 unsigned NumZero, SelectionDAG &DAG,
5746 const X86Subtarget *Subtarget,
5747 const TargetLowering &TLI) {
5748 // We know there's at least one non-zero element
5749 unsigned FirstNonZeroIdx = 0;
5750 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5751 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5752 X86::isZeroNode(FirstNonZero)) {
5754 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5757 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5758 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5761 SDValue V = FirstNonZero.getOperand(0);
5762 MVT VVT = V.getSimpleValueType();
5763 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5766 unsigned FirstNonZeroDst =
5767 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5768 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5769 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5770 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5772 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5773 SDValue Elem = Op.getOperand(Idx);
5774 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5777 // TODO: What else can be here? Deal with it.
5778 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5781 // TODO: Some optimizations are still possible here
5782 // ex: Getting one element from a vector, and the rest from another.
5783 if (Elem.getOperand(0) != V)
5786 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5789 else if (IncorrectIdx == -1U) {
5793 // There was already one element with an incorrect index.
5794 // We can't optimize this case to an insertps.
5798 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5800 EVT VT = Op.getSimpleValueType();
5801 unsigned ElementMoveMask = 0;
5802 if (IncorrectIdx == -1U)
5803 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5805 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5807 SDValue InsertpsMask =
5808 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5809 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5815 /// getVShift - Return a vector logical shift node.
5817 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5818 unsigned NumBits, SelectionDAG &DAG,
5819 const TargetLowering &TLI, SDLoc dl) {
5820 assert(VT.is128BitVector() && "Unknown type for VShift");
5821 EVT ShVT = MVT::v2i64;
5822 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5823 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5824 return DAG.getNode(ISD::BITCAST, dl, VT,
5825 DAG.getNode(Opc, dl, ShVT, SrcOp,
5826 DAG.getConstant(NumBits,
5827 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5831 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5833 // Check if the scalar load can be widened into a vector load. And if
5834 // the address is "base + cst" see if the cst can be "absorbed" into
5835 // the shuffle mask.
5836 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5837 SDValue Ptr = LD->getBasePtr();
5838 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5840 EVT PVT = LD->getValueType(0);
5841 if (PVT != MVT::i32 && PVT != MVT::f32)
5846 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5847 FI = FINode->getIndex();
5849 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5850 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5851 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5852 Offset = Ptr.getConstantOperandVal(1);
5853 Ptr = Ptr.getOperand(0);
5858 // FIXME: 256-bit vector instructions don't require a strict alignment,
5859 // improve this code to support it better.
5860 unsigned RequiredAlign = VT.getSizeInBits()/8;
5861 SDValue Chain = LD->getChain();
5862 // Make sure the stack object alignment is at least 16 or 32.
5863 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5864 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5865 if (MFI->isFixedObjectIndex(FI)) {
5866 // Can't change the alignment. FIXME: It's possible to compute
5867 // the exact stack offset and reference FI + adjust offset instead.
5868 // If someone *really* cares about this. That's the way to implement it.
5871 MFI->setObjectAlignment(FI, RequiredAlign);
5875 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5876 // Ptr + (Offset & ~15).
5879 if ((Offset % RequiredAlign) & 3)
5881 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5883 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5884 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5886 int EltNo = (Offset - StartOffset) >> 2;
5887 unsigned NumElems = VT.getVectorNumElements();
5889 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5890 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5891 LD->getPointerInfo().getWithOffset(StartOffset),
5892 false, false, false, 0);
5894 SmallVector<int, 8> Mask;
5895 for (unsigned i = 0; i != NumElems; ++i)
5896 Mask.push_back(EltNo);
5898 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5904 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5905 /// vector of type 'VT', see if the elements can be replaced by a single large
5906 /// load which has the same value as a build_vector whose operands are 'elts'.
5908 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5910 /// FIXME: we'd also like to handle the case where the last elements are zero
5911 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5912 /// There's even a handy isZeroNode for that purpose.
5913 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5914 SDLoc &DL, SelectionDAG &DAG,
5915 bool isAfterLegalize) {
5916 EVT EltVT = VT.getVectorElementType();
5917 unsigned NumElems = Elts.size();
5919 LoadSDNode *LDBase = nullptr;
5920 unsigned LastLoadedElt = -1U;
5922 // For each element in the initializer, see if we've found a load or an undef.
5923 // If we don't find an initial load element, or later load elements are
5924 // non-consecutive, bail out.
5925 for (unsigned i = 0; i < NumElems; ++i) {
5926 SDValue Elt = Elts[i];
5928 if (!Elt.getNode() ||
5929 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5932 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5934 LDBase = cast<LoadSDNode>(Elt.getNode());
5938 if (Elt.getOpcode() == ISD::UNDEF)
5941 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5942 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5947 // If we have found an entire vector of loads and undefs, then return a large
5948 // load of the entire vector width starting at the base pointer. If we found
5949 // consecutive loads for the low half, generate a vzext_load node.
5950 if (LastLoadedElt == NumElems - 1) {
5952 if (isAfterLegalize &&
5953 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5956 SDValue NewLd = SDValue();
5958 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5959 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5960 LDBase->getPointerInfo(),
5961 LDBase->isVolatile(), LDBase->isNonTemporal(),
5962 LDBase->isInvariant(), 0);
5963 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5964 LDBase->getPointerInfo(),
5965 LDBase->isVolatile(), LDBase->isNonTemporal(),
5966 LDBase->isInvariant(), LDBase->getAlignment());
5968 if (LDBase->hasAnyUseOfValue(1)) {
5969 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5971 SDValue(NewLd.getNode(), 1));
5972 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5973 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5974 SDValue(NewLd.getNode(), 1));
5979 if (NumElems == 4 && LastLoadedElt == 1 &&
5980 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5981 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5982 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5984 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5985 LDBase->getPointerInfo(),
5986 LDBase->getAlignment(),
5987 false/*isVolatile*/, true/*ReadMem*/,
5990 // Make sure the newly-created LOAD is in the same position as LDBase in
5991 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5992 // update uses of LDBase's output chain to use the TokenFactor.
5993 if (LDBase->hasAnyUseOfValue(1)) {
5994 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5995 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5996 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5997 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5998 SDValue(ResNode.getNode(), 1));
6001 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6006 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6007 /// to generate a splat value for the following cases:
6008 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6009 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6010 /// a scalar load, or a constant.
6011 /// The VBROADCAST node is returned when a pattern is found,
6012 /// or SDValue() otherwise.
6013 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6014 SelectionDAG &DAG) {
6015 // VBROADCAST requires AVX.
6016 // TODO: Splats could be generated for non-AVX CPUs using SSE
6017 // instructions, but there's less potential gain for only 128-bit vectors.
6018 if (!Subtarget->hasAVX())
6021 MVT VT = Op.getSimpleValueType();
6024 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6025 "Unsupported vector type for broadcast.");
6030 switch (Op.getOpcode()) {
6032 // Unknown pattern found.
6035 case ISD::BUILD_VECTOR: {
6036 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6037 BitVector UndefElements;
6038 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6040 // We need a splat of a single value to use broadcast, and it doesn't
6041 // make any sense if the value is only in one element of the vector.
6042 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6046 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6047 Ld.getOpcode() == ISD::ConstantFP);
6049 // Make sure that all of the users of a non-constant load are from the
6050 // BUILD_VECTOR node.
6051 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6056 case ISD::VECTOR_SHUFFLE: {
6057 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6059 // Shuffles must have a splat mask where the first element is
6061 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6064 SDValue Sc = Op.getOperand(0);
6065 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6066 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6068 if (!Subtarget->hasInt256())
6071 // Use the register form of the broadcast instruction available on AVX2.
6072 if (VT.getSizeInBits() >= 256)
6073 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6074 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6077 Ld = Sc.getOperand(0);
6078 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6079 Ld.getOpcode() == ISD::ConstantFP);
6081 // The scalar_to_vector node and the suspected
6082 // load node must have exactly one user.
6083 // Constants may have multiple users.
6085 // AVX-512 has register version of the broadcast
6086 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6087 Ld.getValueType().getSizeInBits() >= 32;
6088 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6095 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6096 bool IsGE256 = (VT.getSizeInBits() >= 256);
6098 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6099 // instruction to save 8 or more bytes of constant pool data.
6100 // TODO: If multiple splats are generated to load the same constant,
6101 // it may be detrimental to overall size. There needs to be a way to detect
6102 // that condition to know if this is truly a size win.
6103 const Function *F = DAG.getMachineFunction().getFunction();
6104 bool OptForSize = F->getAttributes().
6105 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6107 // Handle broadcasting a single constant scalar from the constant pool
6109 // On Sandybridge (no AVX2), it is still better to load a constant vector
6110 // from the constant pool and not to broadcast it from a scalar.
6111 // But override that restriction when optimizing for size.
6112 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6113 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6114 EVT CVT = Ld.getValueType();
6115 assert(!CVT.isVector() && "Must not broadcast a vector type");
6117 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6118 // For size optimization, also splat v2f64 and v2i64, and for size opt
6119 // with AVX2, also splat i8 and i16.
6120 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6121 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6122 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6123 const Constant *C = nullptr;
6124 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6125 C = CI->getConstantIntValue();
6126 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6127 C = CF->getConstantFPValue();
6129 assert(C && "Invalid constant type");
6131 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6132 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6133 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6134 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6135 MachinePointerInfo::getConstantPool(),
6136 false, false, false, Alignment);
6138 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6142 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6144 // Handle AVX2 in-register broadcasts.
6145 if (!IsLoad && Subtarget->hasInt256() &&
6146 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6147 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6149 // The scalar source must be a normal load.
6153 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6154 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6156 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6157 // double since there is no vbroadcastsd xmm
6158 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6159 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6160 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6163 // Unsupported broadcast.
6167 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6168 /// underlying vector and index.
6170 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6172 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6174 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6175 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6178 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6180 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6182 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6183 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6186 // In this case the vector is the extract_subvector expression and the index
6187 // is 2, as specified by the shuffle.
6188 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6189 SDValue ShuffleVec = SVOp->getOperand(0);
6190 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6191 assert(ShuffleVecVT.getVectorElementType() ==
6192 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6194 int ShuffleIdx = SVOp->getMaskElt(Idx);
6195 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6196 ExtractedFromVec = ShuffleVec;
6202 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6203 MVT VT = Op.getSimpleValueType();
6205 // Skip if insert_vec_elt is not supported.
6206 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6207 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6211 unsigned NumElems = Op.getNumOperands();
6215 SmallVector<unsigned, 4> InsertIndices;
6216 SmallVector<int, 8> Mask(NumElems, -1);
6218 for (unsigned i = 0; i != NumElems; ++i) {
6219 unsigned Opc = Op.getOperand(i).getOpcode();
6221 if (Opc == ISD::UNDEF)
6224 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6225 // Quit if more than 1 elements need inserting.
6226 if (InsertIndices.size() > 1)
6229 InsertIndices.push_back(i);
6233 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6234 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6235 // Quit if non-constant index.
6236 if (!isa<ConstantSDNode>(ExtIdx))
6238 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6240 // Quit if extracted from vector of different type.
6241 if (ExtractedFromVec.getValueType() != VT)
6244 if (!VecIn1.getNode())
6245 VecIn1 = ExtractedFromVec;
6246 else if (VecIn1 != ExtractedFromVec) {
6247 if (!VecIn2.getNode())
6248 VecIn2 = ExtractedFromVec;
6249 else if (VecIn2 != ExtractedFromVec)
6250 // Quit if more than 2 vectors to shuffle
6254 if (ExtractedFromVec == VecIn1)
6256 else if (ExtractedFromVec == VecIn2)
6257 Mask[i] = Idx + NumElems;
6260 if (!VecIn1.getNode())
6263 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6264 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6265 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6266 unsigned Idx = InsertIndices[i];
6267 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6268 DAG.getIntPtrConstant(Idx));
6274 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6276 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6278 MVT VT = Op.getSimpleValueType();
6279 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6280 "Unexpected type in LowerBUILD_VECTORvXi1!");
6283 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6284 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6285 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6289 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6290 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6291 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6292 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6295 bool AllContants = true;
6296 uint64_t Immediate = 0;
6297 int NonConstIdx = -1;
6298 bool IsSplat = true;
6299 unsigned NumNonConsts = 0;
6300 unsigned NumConsts = 0;
6301 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6302 SDValue In = Op.getOperand(idx);
6303 if (In.getOpcode() == ISD::UNDEF)
6305 if (!isa<ConstantSDNode>(In)) {
6306 AllContants = false;
6312 if (cast<ConstantSDNode>(In)->getZExtValue())
6313 Immediate |= (1ULL << idx);
6315 if (In != Op.getOperand(0))
6320 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6321 DAG.getConstant(Immediate, MVT::i16));
6322 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6323 DAG.getIntPtrConstant(0));
6326 if (NumNonConsts == 1 && NonConstIdx != 0) {
6329 SDValue VecAsImm = DAG.getConstant(Immediate,
6330 MVT::getIntegerVT(VT.getSizeInBits()));
6331 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6334 DstVec = DAG.getUNDEF(VT);
6335 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6336 Op.getOperand(NonConstIdx),
6337 DAG.getIntPtrConstant(NonConstIdx));
6339 if (!IsSplat && (NonConstIdx != 0))
6340 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6341 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6344 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6345 DAG.getConstant(-1, SelectVT),
6346 DAG.getConstant(0, SelectVT));
6348 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6349 DAG.getConstant((Immediate | 1), SelectVT),
6350 DAG.getConstant(Immediate, SelectVT));
6351 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6354 /// \brief Return true if \p N implements a horizontal binop and return the
6355 /// operands for the horizontal binop into V0 and V1.
6357 /// This is a helper function of PerformBUILD_VECTORCombine.
6358 /// This function checks that the build_vector \p N in input implements a
6359 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6360 /// operation to match.
6361 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6362 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6363 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6366 /// This function only analyzes elements of \p N whose indices are
6367 /// in range [BaseIdx, LastIdx).
6368 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6370 unsigned BaseIdx, unsigned LastIdx,
6371 SDValue &V0, SDValue &V1) {
6372 EVT VT = N->getValueType(0);
6374 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6375 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6376 "Invalid Vector in input!");
6378 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6379 bool CanFold = true;
6380 unsigned ExpectedVExtractIdx = BaseIdx;
6381 unsigned NumElts = LastIdx - BaseIdx;
6382 V0 = DAG.getUNDEF(VT);
6383 V1 = DAG.getUNDEF(VT);
6385 // Check if N implements a horizontal binop.
6386 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6387 SDValue Op = N->getOperand(i + BaseIdx);
6390 if (Op->getOpcode() == ISD::UNDEF) {
6391 // Update the expected vector extract index.
6392 if (i * 2 == NumElts)
6393 ExpectedVExtractIdx = BaseIdx;
6394 ExpectedVExtractIdx += 2;
6398 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6403 SDValue Op0 = Op.getOperand(0);
6404 SDValue Op1 = Op.getOperand(1);
6406 // Try to match the following pattern:
6407 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6408 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6409 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6410 Op0.getOperand(0) == Op1.getOperand(0) &&
6411 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6412 isa<ConstantSDNode>(Op1.getOperand(1)));
6416 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6417 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6419 if (i * 2 < NumElts) {
6420 if (V0.getOpcode() == ISD::UNDEF)
6421 V0 = Op0.getOperand(0);
6423 if (V1.getOpcode() == ISD::UNDEF)
6424 V1 = Op0.getOperand(0);
6425 if (i * 2 == NumElts)
6426 ExpectedVExtractIdx = BaseIdx;
6429 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6430 if (I0 == ExpectedVExtractIdx)
6431 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6432 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6433 // Try to match the following dag sequence:
6434 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6435 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6439 ExpectedVExtractIdx += 2;
6445 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6446 /// a concat_vector.
6448 /// This is a helper function of PerformBUILD_VECTORCombine.
6449 /// This function expects two 256-bit vectors called V0 and V1.
6450 /// At first, each vector is split into two separate 128-bit vectors.
6451 /// Then, the resulting 128-bit vectors are used to implement two
6452 /// horizontal binary operations.
6454 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6456 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6457 /// the two new horizontal binop.
6458 /// When Mode is set, the first horizontal binop dag node would take as input
6459 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6460 /// horizontal binop dag node would take as input the lower 128-bit of V1
6461 /// and the upper 128-bit of V1.
6463 /// HADD V0_LO, V0_HI
6464 /// HADD V1_LO, V1_HI
6466 /// Otherwise, the first horizontal binop dag node takes as input the lower
6467 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6468 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6470 /// HADD V0_LO, V1_LO
6471 /// HADD V0_HI, V1_HI
6473 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6474 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6475 /// the upper 128-bits of the result.
6476 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6477 SDLoc DL, SelectionDAG &DAG,
6478 unsigned X86Opcode, bool Mode,
6479 bool isUndefLO, bool isUndefHI) {
6480 EVT VT = V0.getValueType();
6481 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6482 "Invalid nodes in input!");
6484 unsigned NumElts = VT.getVectorNumElements();
6485 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6486 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6487 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6488 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6489 EVT NewVT = V0_LO.getValueType();
6491 SDValue LO = DAG.getUNDEF(NewVT);
6492 SDValue HI = DAG.getUNDEF(NewVT);
6495 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6496 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6497 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6498 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6499 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6501 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6502 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6503 V1_LO->getOpcode() != ISD::UNDEF))
6504 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6506 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6507 V1_HI->getOpcode() != ISD::UNDEF))
6508 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6511 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6514 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6515 /// sequence of 'vadd + vsub + blendi'.
6516 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6517 const X86Subtarget *Subtarget) {
6519 EVT VT = BV->getValueType(0);
6520 unsigned NumElts = VT.getVectorNumElements();
6521 SDValue InVec0 = DAG.getUNDEF(VT);
6522 SDValue InVec1 = DAG.getUNDEF(VT);
6524 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6525 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6527 // Odd-numbered elements in the input build vector are obtained from
6528 // adding two integer/float elements.
6529 // Even-numbered elements in the input build vector are obtained from
6530 // subtracting two integer/float elements.
6531 unsigned ExpectedOpcode = ISD::FSUB;
6532 unsigned NextExpectedOpcode = ISD::FADD;
6533 bool AddFound = false;
6534 bool SubFound = false;
6536 for (unsigned i = 0, e = NumElts; i != e; i++) {
6537 SDValue Op = BV->getOperand(i);
6539 // Skip 'undef' values.
6540 unsigned Opcode = Op.getOpcode();
6541 if (Opcode == ISD::UNDEF) {
6542 std::swap(ExpectedOpcode, NextExpectedOpcode);
6546 // Early exit if we found an unexpected opcode.
6547 if (Opcode != ExpectedOpcode)
6550 SDValue Op0 = Op.getOperand(0);
6551 SDValue Op1 = Op.getOperand(1);
6553 // Try to match the following pattern:
6554 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6555 // Early exit if we cannot match that sequence.
6556 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6557 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6558 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6559 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6560 Op0.getOperand(1) != Op1.getOperand(1))
6563 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6567 // We found a valid add/sub node. Update the information accordingly.
6573 // Update InVec0 and InVec1.
6574 if (InVec0.getOpcode() == ISD::UNDEF)
6575 InVec0 = Op0.getOperand(0);
6576 if (InVec1.getOpcode() == ISD::UNDEF)
6577 InVec1 = Op1.getOperand(0);
6579 // Make sure that operands in input to each add/sub node always
6580 // come from a same pair of vectors.
6581 if (InVec0 != Op0.getOperand(0)) {
6582 if (ExpectedOpcode == ISD::FSUB)
6585 // FADD is commutable. Try to commute the operands
6586 // and then test again.
6587 std::swap(Op0, Op1);
6588 if (InVec0 != Op0.getOperand(0))
6592 if (InVec1 != Op1.getOperand(0))
6595 // Update the pair of expected opcodes.
6596 std::swap(ExpectedOpcode, NextExpectedOpcode);
6599 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6600 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6601 InVec1.getOpcode() != ISD::UNDEF)
6602 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6607 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6608 const X86Subtarget *Subtarget) {
6610 EVT VT = N->getValueType(0);
6611 unsigned NumElts = VT.getVectorNumElements();
6612 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6613 SDValue InVec0, InVec1;
6615 // Try to match an ADDSUB.
6616 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6617 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6618 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6619 if (Value.getNode())
6623 // Try to match horizontal ADD/SUB.
6624 unsigned NumUndefsLO = 0;
6625 unsigned NumUndefsHI = 0;
6626 unsigned Half = NumElts/2;
6628 // Count the number of UNDEF operands in the build_vector in input.
6629 for (unsigned i = 0, e = Half; i != e; ++i)
6630 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6633 for (unsigned i = Half, e = NumElts; i != e; ++i)
6634 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6637 // Early exit if this is either a build_vector of all UNDEFs or all the
6638 // operands but one are UNDEF.
6639 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6642 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6643 // Try to match an SSE3 float HADD/HSUB.
6644 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6645 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6647 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6648 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6649 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6650 // Try to match an SSSE3 integer HADD/HSUB.
6651 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6652 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6654 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6655 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6658 if (!Subtarget->hasAVX())
6661 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6662 // Try to match an AVX horizontal add/sub of packed single/double
6663 // precision floating point values from 256-bit vectors.
6664 SDValue InVec2, InVec3;
6665 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6666 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6667 ((InVec0.getOpcode() == ISD::UNDEF ||
6668 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6669 ((InVec1.getOpcode() == ISD::UNDEF ||
6670 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6671 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6673 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6674 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6675 ((InVec0.getOpcode() == ISD::UNDEF ||
6676 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6677 ((InVec1.getOpcode() == ISD::UNDEF ||
6678 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6679 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6680 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6681 // Try to match an AVX2 horizontal add/sub of signed integers.
6682 SDValue InVec2, InVec3;
6684 bool CanFold = true;
6686 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6687 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6688 ((InVec0.getOpcode() == ISD::UNDEF ||
6689 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6690 ((InVec1.getOpcode() == ISD::UNDEF ||
6691 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6692 X86Opcode = X86ISD::HADD;
6693 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6694 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6695 ((InVec0.getOpcode() == ISD::UNDEF ||
6696 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6697 ((InVec1.getOpcode() == ISD::UNDEF ||
6698 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6699 X86Opcode = X86ISD::HSUB;
6704 // Fold this build_vector into a single horizontal add/sub.
6705 // Do this only if the target has AVX2.
6706 if (Subtarget->hasAVX2())
6707 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6709 // Do not try to expand this build_vector into a pair of horizontal
6710 // add/sub if we can emit a pair of scalar add/sub.
6711 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6714 // Convert this build_vector into a pair of horizontal binop followed by
6716 bool isUndefLO = NumUndefsLO == Half;
6717 bool isUndefHI = NumUndefsHI == Half;
6718 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6719 isUndefLO, isUndefHI);
6723 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6724 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6726 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6727 X86Opcode = X86ISD::HADD;
6728 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6729 X86Opcode = X86ISD::HSUB;
6730 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6731 X86Opcode = X86ISD::FHADD;
6732 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6733 X86Opcode = X86ISD::FHSUB;
6737 // Don't try to expand this build_vector into a pair of horizontal add/sub
6738 // if we can simply emit a pair of scalar add/sub.
6739 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6742 // Convert this build_vector into two horizontal add/sub followed by
6744 bool isUndefLO = NumUndefsLO == Half;
6745 bool isUndefHI = NumUndefsHI == Half;
6746 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6747 isUndefLO, isUndefHI);
6754 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6757 MVT VT = Op.getSimpleValueType();
6758 MVT ExtVT = VT.getVectorElementType();
6759 unsigned NumElems = Op.getNumOperands();
6761 // Generate vectors for predicate vectors.
6762 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6763 return LowerBUILD_VECTORvXi1(Op, DAG);
6765 // Vectors containing all zeros can be matched by pxor and xorps later
6766 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6767 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6768 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6769 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6772 return getZeroVector(VT, Subtarget, DAG, dl);
6775 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6776 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6777 // vpcmpeqd on 256-bit vectors.
6778 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6779 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6782 if (!VT.is512BitVector())
6783 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6786 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6787 if (Broadcast.getNode())
6790 unsigned EVTBits = ExtVT.getSizeInBits();
6792 unsigned NumZero = 0;
6793 unsigned NumNonZero = 0;
6794 unsigned NonZeros = 0;
6795 bool IsAllConstants = true;
6796 SmallSet<SDValue, 8> Values;
6797 for (unsigned i = 0; i < NumElems; ++i) {
6798 SDValue Elt = Op.getOperand(i);
6799 if (Elt.getOpcode() == ISD::UNDEF)
6802 if (Elt.getOpcode() != ISD::Constant &&
6803 Elt.getOpcode() != ISD::ConstantFP)
6804 IsAllConstants = false;
6805 if (X86::isZeroNode(Elt))
6808 NonZeros |= (1 << i);
6813 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6814 if (NumNonZero == 0)
6815 return DAG.getUNDEF(VT);
6817 // Special case for single non-zero, non-undef, element.
6818 if (NumNonZero == 1) {
6819 unsigned Idx = countTrailingZeros(NonZeros);
6820 SDValue Item = Op.getOperand(Idx);
6822 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6823 // the value are obviously zero, truncate the value to i32 and do the
6824 // insertion that way. Only do this if the value is non-constant or if the
6825 // value is a constant being inserted into element 0. It is cheaper to do
6826 // a constant pool load than it is to do a movd + shuffle.
6827 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6828 (!IsAllConstants || Idx == 0)) {
6829 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6831 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6832 EVT VecVT = MVT::v4i32;
6833 unsigned VecElts = 4;
6835 // Truncate the value (which may itself be a constant) to i32, and
6836 // convert it to a vector with movd (S2V+shuffle to zero extend).
6837 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6838 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6840 // If using the new shuffle lowering, just directly insert this.
6841 if (ExperimentalVectorShuffleLowering)
6843 ISD::BITCAST, dl, VT,
6844 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6846 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6848 // Now we have our 32-bit value zero extended in the low element of
6849 // a vector. If Idx != 0, swizzle it into place.
6851 SmallVector<int, 4> Mask;
6852 Mask.push_back(Idx);
6853 for (unsigned i = 1; i != VecElts; ++i)
6855 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6858 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6862 // If we have a constant or non-constant insertion into the low element of
6863 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6864 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6865 // depending on what the source datatype is.
6868 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6870 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6871 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6872 if (VT.is256BitVector() || VT.is512BitVector()) {
6873 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6874 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6875 Item, DAG.getIntPtrConstant(0));
6877 assert(VT.is128BitVector() && "Expected an SSE value type!");
6878 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6879 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6880 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6883 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6884 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6885 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6886 if (VT.is256BitVector()) {
6887 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6888 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6890 assert(VT.is128BitVector() && "Expected an SSE value type!");
6891 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6893 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6897 // Is it a vector logical left shift?
6898 if (NumElems == 2 && Idx == 1 &&
6899 X86::isZeroNode(Op.getOperand(0)) &&
6900 !X86::isZeroNode(Op.getOperand(1))) {
6901 unsigned NumBits = VT.getSizeInBits();
6902 return getVShift(true, VT,
6903 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6904 VT, Op.getOperand(1)),
6905 NumBits/2, DAG, *this, dl);
6908 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6911 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6912 // is a non-constant being inserted into an element other than the low one,
6913 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6914 // movd/movss) to move this into the low element, then shuffle it into
6916 if (EVTBits == 32) {
6917 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6919 // If using the new shuffle lowering, just directly insert this.
6920 if (ExperimentalVectorShuffleLowering)
6921 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6923 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6924 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6925 SmallVector<int, 8> MaskVec;
6926 for (unsigned i = 0; i != NumElems; ++i)
6927 MaskVec.push_back(i == Idx ? 0 : 1);
6928 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6932 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6933 if (Values.size() == 1) {
6934 if (EVTBits == 32) {
6935 // Instead of a shuffle like this:
6936 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6937 // Check if it's possible to issue this instead.
6938 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6939 unsigned Idx = countTrailingZeros(NonZeros);
6940 SDValue Item = Op.getOperand(Idx);
6941 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6942 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6947 // A vector full of immediates; various special cases are already
6948 // handled, so this is best done with a single constant-pool load.
6952 // For AVX-length vectors, build the individual 128-bit pieces and use
6953 // shuffles to put them in place.
6954 if (VT.is256BitVector() || VT.is512BitVector()) {
6955 SmallVector<SDValue, 64> V;
6956 for (unsigned i = 0; i != NumElems; ++i)
6957 V.push_back(Op.getOperand(i));
6959 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6961 // Build both the lower and upper subvector.
6962 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6963 makeArrayRef(&V[0], NumElems/2));
6964 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6965 makeArrayRef(&V[NumElems / 2], NumElems/2));
6967 // Recreate the wider vector with the lower and upper part.
6968 if (VT.is256BitVector())
6969 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6970 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6973 // Let legalizer expand 2-wide build_vectors.
6974 if (EVTBits == 64) {
6975 if (NumNonZero == 1) {
6976 // One half is zero or undef.
6977 unsigned Idx = countTrailingZeros(NonZeros);
6978 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6979 Op.getOperand(Idx));
6980 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6985 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6986 if (EVTBits == 8 && NumElems == 16) {
6987 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6989 if (V.getNode()) return V;
6992 if (EVTBits == 16 && NumElems == 8) {
6993 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6995 if (V.getNode()) return V;
6998 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6999 if (EVTBits == 32 && NumElems == 4) {
7000 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
7001 NumZero, DAG, Subtarget, *this);
7006 // If element VT is == 32 bits, turn it into a number of shuffles.
7007 SmallVector<SDValue, 8> V(NumElems);
7008 if (NumElems == 4 && NumZero > 0) {
7009 for (unsigned i = 0; i < 4; ++i) {
7010 bool isZero = !(NonZeros & (1 << i));
7012 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7014 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7017 for (unsigned i = 0; i < 2; ++i) {
7018 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7021 V[i] = V[i*2]; // Must be a zero vector.
7024 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7027 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7030 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7035 bool Reverse1 = (NonZeros & 0x3) == 2;
7036 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7040 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7041 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7043 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7046 if (Values.size() > 1 && VT.is128BitVector()) {
7047 // Check for a build vector of consecutive loads.
7048 for (unsigned i = 0; i < NumElems; ++i)
7049 V[i] = Op.getOperand(i);
7051 // Check for elements which are consecutive loads.
7052 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7056 // Check for a build vector from mostly shuffle plus few inserting.
7057 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7061 // For SSE 4.1, use insertps to put the high elements into the low element.
7062 if (getSubtarget()->hasSSE41()) {
7064 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7065 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7067 Result = DAG.getUNDEF(VT);
7069 for (unsigned i = 1; i < NumElems; ++i) {
7070 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7071 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7072 Op.getOperand(i), DAG.getIntPtrConstant(i));
7077 // Otherwise, expand into a number of unpckl*, start by extending each of
7078 // our (non-undef) elements to the full vector width with the element in the
7079 // bottom slot of the vector (which generates no code for SSE).
7080 for (unsigned i = 0; i < NumElems; ++i) {
7081 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7082 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7084 V[i] = DAG.getUNDEF(VT);
7087 // Next, we iteratively mix elements, e.g. for v4f32:
7088 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7089 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7090 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7091 unsigned EltStride = NumElems >> 1;
7092 while (EltStride != 0) {
7093 for (unsigned i = 0; i < EltStride; ++i) {
7094 // If V[i+EltStride] is undef and this is the first round of mixing,
7095 // then it is safe to just drop this shuffle: V[i] is already in the
7096 // right place, the one element (since it's the first round) being
7097 // inserted as undef can be dropped. This isn't safe for successive
7098 // rounds because they will permute elements within both vectors.
7099 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7100 EltStride == NumElems/2)
7103 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7112 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7113 // to create 256-bit vectors from two other 128-bit ones.
7114 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7116 MVT ResVT = Op.getSimpleValueType();
7118 assert((ResVT.is256BitVector() ||
7119 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7121 SDValue V1 = Op.getOperand(0);
7122 SDValue V2 = Op.getOperand(1);
7123 unsigned NumElems = ResVT.getVectorNumElements();
7124 if(ResVT.is256BitVector())
7125 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7127 if (Op.getNumOperands() == 4) {
7128 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7129 ResVT.getVectorNumElements()/2);
7130 SDValue V3 = Op.getOperand(2);
7131 SDValue V4 = Op.getOperand(3);
7132 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7133 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7135 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7138 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7139 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7140 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7141 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7142 Op.getNumOperands() == 4)));
7144 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7145 // from two other 128-bit ones.
7147 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7148 return LowerAVXCONCAT_VECTORS(Op, DAG);
7152 //===----------------------------------------------------------------------===//
7153 // Vector shuffle lowering
7155 // This is an experimental code path for lowering vector shuffles on x86. It is
7156 // designed to handle arbitrary vector shuffles and blends, gracefully
7157 // degrading performance as necessary. It works hard to recognize idiomatic
7158 // shuffles and lower them to optimal instruction patterns without leaving
7159 // a framework that allows reasonably efficient handling of all vector shuffle
7161 //===----------------------------------------------------------------------===//
7163 /// \brief Tiny helper function to identify a no-op mask.
7165 /// This is a somewhat boring predicate function. It checks whether the mask
7166 /// array input, which is assumed to be a single-input shuffle mask of the kind
7167 /// used by the X86 shuffle instructions (not a fully general
7168 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7169 /// in-place shuffle are 'no-op's.
7170 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7171 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7172 if (Mask[i] != -1 && Mask[i] != i)
7177 /// \brief Helper function to classify a mask as a single-input mask.
7179 /// This isn't a generic single-input test because in the vector shuffle
7180 /// lowering we canonicalize single inputs to be the first input operand. This
7181 /// means we can more quickly test for a single input by only checking whether
7182 /// an input from the second operand exists. We also assume that the size of
7183 /// mask corresponds to the size of the input vectors which isn't true in the
7184 /// fully general case.
7185 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7187 if (M >= (int)Mask.size())
7192 /// \brief Test whether there are elements crossing 128-bit lanes in this
7195 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7196 /// and we routinely test for these.
7197 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7198 int LaneSize = 128 / VT.getScalarSizeInBits();
7199 int Size = Mask.size();
7200 for (int i = 0; i < Size; ++i)
7201 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7206 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7208 /// This checks a shuffle mask to see if it is performing the same
7209 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7210 /// that it is also not lane-crossing. It may however involve a blend from the
7211 /// same lane of a second vector.
7213 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7214 /// non-trivial to compute in the face of undef lanes. The representation is
7215 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7216 /// entries from both V1 and V2 inputs to the wider mask.
7218 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7219 SmallVectorImpl<int> &RepeatedMask) {
7220 int LaneSize = 128 / VT.getScalarSizeInBits();
7221 RepeatedMask.resize(LaneSize, -1);
7222 int Size = Mask.size();
7223 for (int i = 0; i < Size; ++i) {
7226 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7227 // This entry crosses lanes, so there is no way to model this shuffle.
7230 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7231 if (RepeatedMask[i % LaneSize] == -1)
7232 // This is the first non-undef entry in this slot of a 128-bit lane.
7233 RepeatedMask[i % LaneSize] =
7234 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7235 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7236 // Found a mismatch with the repeated mask.
7242 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7243 // 2013 will allow us to use it as a non-type template parameter.
7246 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7248 /// See its documentation for details.
7249 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7250 if (Mask.size() != Args.size())
7252 for (int i = 0, e = Mask.size(); i < e; ++i) {
7253 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7254 if (Mask[i] != -1 && Mask[i] != *Args[i])
7262 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7265 /// This is a fast way to test a shuffle mask against a fixed pattern:
7267 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7269 /// It returns true if the mask is exactly as wide as the argument list, and
7270 /// each element of the mask is either -1 (signifying undef) or the value given
7271 /// in the argument.
7272 static const VariadicFunction1<
7273 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7275 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7277 /// This helper function produces an 8-bit shuffle immediate corresponding to
7278 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7279 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7282 /// NB: We rely heavily on "undef" masks preserving the input lane.
7283 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7284 SelectionDAG &DAG) {
7285 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7286 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7287 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7288 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7289 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7292 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7293 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7294 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7295 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7296 return DAG.getConstant(Imm, MVT::i8);
7299 /// \brief Try to emit a blend instruction for a shuffle.
7301 /// This doesn't do any checks for the availability of instructions for blending
7302 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7303 /// be matched in the backend with the type given. What it does check for is
7304 /// that the shuffle mask is in fact a blend.
7305 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7306 SDValue V2, ArrayRef<int> Mask,
7307 const X86Subtarget *Subtarget,
7308 SelectionDAG &DAG) {
7310 unsigned BlendMask = 0;
7311 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7312 if (Mask[i] >= Size) {
7313 if (Mask[i] != i + Size)
7314 return SDValue(); // Shuffled V2 input!
7315 BlendMask |= 1u << i;
7318 if (Mask[i] >= 0 && Mask[i] != i)
7319 return SDValue(); // Shuffled V1 input!
7321 switch (VT.SimpleTy) {
7326 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7327 DAG.getConstant(BlendMask, MVT::i8));
7331 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7335 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7336 // that instruction.
7337 if (Subtarget->hasAVX2()) {
7338 // Scale the blend by the number of 32-bit dwords per element.
7339 int Scale = VT.getScalarSizeInBits() / 32;
7341 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7342 if (Mask[i] >= Size)
7343 for (int j = 0; j < Scale; ++j)
7344 BlendMask |= 1u << (i * Scale + j);
7346 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7347 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7348 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7349 return DAG.getNode(ISD::BITCAST, DL, VT,
7350 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7351 DAG.getConstant(BlendMask, MVT::i8)));
7355 // For integer shuffles we need to expand the mask and cast the inputs to
7356 // v8i16s prior to blending.
7357 int Scale = 8 / VT.getVectorNumElements();
7359 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7360 if (Mask[i] >= Size)
7361 for (int j = 0; j < Scale; ++j)
7362 BlendMask |= 1u << (i * Scale + j);
7364 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7365 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7366 return DAG.getNode(ISD::BITCAST, DL, VT,
7367 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7368 DAG.getConstant(BlendMask, MVT::i8)));
7372 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7373 SmallVector<int, 8> RepeatedMask;
7374 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7375 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7376 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7378 for (int i = 0; i < 8; ++i)
7379 if (RepeatedMask[i] >= 16)
7380 BlendMask |= 1u << i;
7381 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7382 DAG.getConstant(BlendMask, MVT::i8));
7387 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7388 // Scale the blend by the number of bytes per element.
7389 int Scale = VT.getScalarSizeInBits() / 8;
7390 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7392 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7393 // mix of LLVM's code generator and the x86 backend. We tell the code
7394 // generator that boolean values in the elements of an x86 vector register
7395 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7396 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7397 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7398 // of the element (the remaining are ignored) and 0 in that high bit would
7399 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7400 // the LLVM model for boolean values in vector elements gets the relevant
7401 // bit set, it is set backwards and over constrained relative to x86's
7403 SDValue VSELECTMask[32];
7404 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7405 for (int j = 0; j < Scale; ++j)
7406 VSELECTMask[Scale * i + j] =
7407 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7408 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7410 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7411 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7413 ISD::BITCAST, DL, VT,
7414 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7415 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7420 llvm_unreachable("Not a supported integer vector type!");
7424 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7425 /// unblended shuffles followed by an unshuffled blend.
7427 /// This matches the extremely common pattern for handling combined
7428 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7430 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7434 SelectionDAG &DAG) {
7435 // Shuffle the input elements into the desired positions in V1 and V2 and
7436 // blend them together.
7437 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7438 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7439 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7440 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7441 if (Mask[i] >= 0 && Mask[i] < Size) {
7442 V1Mask[i] = Mask[i];
7444 } else if (Mask[i] >= Size) {
7445 V2Mask[i] = Mask[i] - Size;
7446 BlendMask[i] = i + Size;
7449 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7450 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7451 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7454 /// \brief Try to lower a vector shuffle as a byte rotation.
7456 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7457 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7458 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7459 /// try to generically lower a vector shuffle through such an pattern. It
7460 /// does not check for the profitability of lowering either as PALIGNR or
7461 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7462 /// This matches shuffle vectors that look like:
7464 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7466 /// Essentially it concatenates V1 and V2, shifts right by some number of
7467 /// elements, and takes the low elements as the result. Note that while this is
7468 /// specified as a *right shift* because x86 is little-endian, it is a *left
7469 /// rotate* of the vector lanes.
7471 /// Note that this only handles 128-bit vector widths currently.
7472 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7475 const X86Subtarget *Subtarget,
7476 SelectionDAG &DAG) {
7477 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7479 // We need to detect various ways of spelling a rotation:
7480 // [11, 12, 13, 14, 15, 0, 1, 2]
7481 // [-1, 12, 13, 14, -1, -1, 1, -1]
7482 // [-1, -1, -1, -1, -1, -1, 1, 2]
7483 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7484 // [-1, 4, 5, 6, -1, -1, 9, -1]
7485 // [-1, 4, 5, 6, -1, -1, -1, -1]
7488 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7491 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7493 // Based on the mod-Size value of this mask element determine where
7494 // a rotated vector would have started.
7495 int StartIdx = i - (Mask[i] % Size);
7497 // The identity rotation isn't interesting, stop.
7500 // If we found the tail of a vector the rotation must be the missing
7501 // front. If we found the head of a vector, it must be how much of the head.
7502 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7505 Rotation = CandidateRotation;
7506 else if (Rotation != CandidateRotation)
7507 // The rotations don't match, so we can't match this mask.
7510 // Compute which value this mask is pointing at.
7511 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7513 // Compute which of the two target values this index should be assigned to.
7514 // This reflects whether the high elements are remaining or the low elements
7516 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7518 // Either set up this value if we've not encountered it before, or check
7519 // that it remains consistent.
7522 else if (TargetV != MaskV)
7523 // This may be a rotation, but it pulls from the inputs in some
7524 // unsupported interleaving.
7528 // Check that we successfully analyzed the mask, and normalize the results.
7529 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7530 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7536 assert(VT.getSizeInBits() == 128 &&
7537 "Rotate-based lowering only supports 128-bit lowering!");
7538 assert(Mask.size() <= 16 &&
7539 "Can shuffle at most 16 bytes in a 128-bit vector!");
7541 // The actual rotate instruction rotates bytes, so we need to scale the
7542 // rotation based on how many bytes are in the vector.
7543 int Scale = 16 / Mask.size();
7545 // SSSE3 targets can use the palignr instruction
7546 if (Subtarget->hasSSSE3()) {
7547 // Cast the inputs to v16i8 to match PALIGNR.
7548 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7549 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7551 return DAG.getNode(ISD::BITCAST, DL, VT,
7552 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7553 DAG.getConstant(Rotation * Scale, MVT::i8)));
7556 // Default SSE2 implementation
7557 int LoByteShift = 16 - Rotation * Scale;
7558 int HiByteShift = Rotation * Scale;
7560 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7561 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7562 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7564 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7565 DAG.getConstant(8 * LoByteShift, MVT::i8));
7566 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7567 DAG.getConstant(8 * HiByteShift, MVT::i8));
7568 return DAG.getNode(ISD::BITCAST, DL, VT,
7569 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7572 /// \brief Compute whether each element of a shuffle is zeroable.
7574 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7575 /// Either it is an undef element in the shuffle mask, the element of the input
7576 /// referenced is undef, or the element of the input referenced is known to be
7577 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7578 /// as many lanes with this technique as possible to simplify the remaining
7580 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7581 SDValue V1, SDValue V2) {
7582 SmallBitVector Zeroable(Mask.size(), false);
7584 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7585 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7587 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7589 // Handle the easy cases.
7590 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7595 // If this is an index into a build_vector node, dig out the input value and
7597 SDValue V = M < Size ? V1 : V2;
7598 if (V.getOpcode() != ISD::BUILD_VECTOR)
7601 SDValue Input = V.getOperand(M % Size);
7602 // The UNDEF opcode check really should be dead code here, but not quite
7603 // worth asserting on (it isn't invalid, just unexpected).
7604 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7611 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7613 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7614 /// byte-shift instructions. The mask must consist of a shifted sequential
7615 /// shuffle from one of the input vectors and zeroable elements for the
7616 /// remaining 'shifted in' elements.
7618 /// Note that this only handles 128-bit vector widths currently.
7619 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7620 SDValue V2, ArrayRef<int> Mask,
7621 SelectionDAG &DAG) {
7622 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7624 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7626 int Size = Mask.size();
7627 int Scale = 16 / Size;
7629 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7630 ArrayRef<int> Mask) {
7631 for (int i = StartIndex; i < EndIndex; i++) {
7634 if (i + Base != Mask[i] - MaskOffset)
7640 for (int Shift = 1; Shift < Size; Shift++) {
7641 int ByteShift = Shift * Scale;
7643 // PSRLDQ : (little-endian) right byte shift
7644 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7645 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7646 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7647 bool ZeroableRight = true;
7648 for (int i = Size - Shift; i < Size; i++) {
7649 ZeroableRight &= Zeroable[i];
7652 if (ZeroableRight) {
7653 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7654 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7656 if (ValidShiftRight1 || ValidShiftRight2) {
7657 // Cast the inputs to v2i64 to match PSRLDQ.
7658 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7659 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7660 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7661 DAG.getConstant(ByteShift * 8, MVT::i8));
7662 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7666 // PSLLDQ : (little-endian) left byte shift
7667 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7668 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7669 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7670 bool ZeroableLeft = true;
7671 for (int i = 0; i < Shift; i++) {
7672 ZeroableLeft &= Zeroable[i];
7676 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7677 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7679 if (ValidShiftLeft1 || ValidShiftLeft2) {
7680 // Cast the inputs to v2i64 to match PSLLDQ.
7681 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7682 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7683 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7684 DAG.getConstant(ByteShift * 8, MVT::i8));
7685 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7693 /// \brief Lower a vector shuffle as a zero or any extension.
7695 /// Given a specific number of elements, element bit width, and extension
7696 /// stride, produce either a zero or any extension based on the available
7697 /// features of the subtarget.
7698 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7699 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7700 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7701 assert(Scale > 1 && "Need a scale to extend.");
7702 int EltBits = VT.getSizeInBits() / NumElements;
7703 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7704 "Only 8, 16, and 32 bit elements can be extended.");
7705 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7707 // Found a valid zext mask! Try various lowering strategies based on the
7708 // input type and available ISA extensions.
7709 if (Subtarget->hasSSE41()) {
7710 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7711 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7712 NumElements / Scale);
7713 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7714 return DAG.getNode(ISD::BITCAST, DL, VT,
7715 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7718 // For any extends we can cheat for larger element sizes and use shuffle
7719 // instructions that can fold with a load and/or copy.
7720 if (AnyExt && EltBits == 32) {
7721 int PSHUFDMask[4] = {0, -1, 1, -1};
7723 ISD::BITCAST, DL, VT,
7724 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7725 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7726 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7728 if (AnyExt && EltBits == 16 && Scale > 2) {
7729 int PSHUFDMask[4] = {0, -1, 0, -1};
7730 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7731 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7732 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7733 int PSHUFHWMask[4] = {1, -1, -1, -1};
7735 ISD::BITCAST, DL, VT,
7736 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7737 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7738 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7741 // If this would require more than 2 unpack instructions to expand, use
7742 // pshufb when available. We can only use more than 2 unpack instructions
7743 // when zero extending i8 elements which also makes it easier to use pshufb.
7744 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7745 assert(NumElements == 16 && "Unexpected byte vector width!");
7746 SDValue PSHUFBMask[16];
7747 for (int i = 0; i < 16; ++i)
7749 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7750 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7751 return DAG.getNode(ISD::BITCAST, DL, VT,
7752 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7753 DAG.getNode(ISD::BUILD_VECTOR, DL,
7754 MVT::v16i8, PSHUFBMask)));
7757 // Otherwise emit a sequence of unpacks.
7759 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7760 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7761 : getZeroVector(InputVT, Subtarget, DAG, DL);
7762 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7763 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7767 } while (Scale > 1);
7768 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7771 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7773 /// This routine will try to do everything in its power to cleverly lower
7774 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7775 /// check for the profitability of this lowering, it tries to aggressively
7776 /// match this pattern. It will use all of the micro-architectural details it
7777 /// can to emit an efficient lowering. It handles both blends with all-zero
7778 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7779 /// masking out later).
7781 /// The reason we have dedicated lowering for zext-style shuffles is that they
7782 /// are both incredibly common and often quite performance sensitive.
7783 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7784 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7785 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7786 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7788 int Bits = VT.getSizeInBits();
7789 int NumElements = Mask.size();
7791 // Define a helper function to check a particular ext-scale and lower to it if
7793 auto Lower = [&](int Scale) -> SDValue {
7796 for (int i = 0; i < NumElements; ++i) {
7798 continue; // Valid anywhere but doesn't tell us anything.
7799 if (i % Scale != 0) {
7800 // Each of the extend elements needs to be zeroable.
7804 // We no lorger are in the anyext case.
7809 // Each of the base elements needs to be consecutive indices into the
7810 // same input vector.
7811 SDValue V = Mask[i] < NumElements ? V1 : V2;
7814 else if (InputV != V)
7815 return SDValue(); // Flip-flopping inputs.
7817 if (Mask[i] % NumElements != i / Scale)
7818 return SDValue(); // Non-consecutive strided elemenst.
7821 // If we fail to find an input, we have a zero-shuffle which should always
7822 // have already been handled.
7823 // FIXME: Maybe handle this here in case during blending we end up with one?
7827 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7828 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7831 // The widest scale possible for extending is to a 64-bit integer.
7832 assert(Bits % 64 == 0 &&
7833 "The number of bits in a vector must be divisible by 64 on x86!");
7834 int NumExtElements = Bits / 64;
7836 // Each iteration, try extending the elements half as much, but into twice as
7838 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7839 assert(NumElements % NumExtElements == 0 &&
7840 "The input vector size must be divisble by the extended size.");
7841 if (SDValue V = Lower(NumElements / NumExtElements))
7845 // No viable ext lowering found.
7849 /// \brief Try to get a scalar value for a specific element of a vector.
7851 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7852 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7853 SelectionDAG &DAG) {
7854 MVT VT = V.getSimpleValueType();
7855 MVT EltVT = VT.getVectorElementType();
7856 while (V.getOpcode() == ISD::BITCAST)
7857 V = V.getOperand(0);
7858 // If the bitcasts shift the element size, we can't extract an equivalent
7860 MVT NewVT = V.getSimpleValueType();
7861 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7864 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7865 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7866 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7871 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7873 /// This is particularly important because the set of instructions varies
7874 /// significantly based on whether the operand is a load or not.
7875 static bool isShuffleFoldableLoad(SDValue V) {
7876 while (V.getOpcode() == ISD::BITCAST)
7877 V = V.getOperand(0);
7879 return ISD::isNON_EXTLoad(V.getNode());
7882 /// \brief Try to lower insertion of a single element into a zero vector.
7884 /// This is a common pattern that we have especially efficient patterns to lower
7885 /// across all subtarget feature sets.
7886 static SDValue lowerVectorShuffleAsElementInsertion(
7887 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7888 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7889 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7891 MVT EltVT = VT.getVectorElementType();
7893 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7894 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7896 bool IsV1Zeroable = true;
7897 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7898 if (i != V2Index && !Zeroable[i]) {
7899 IsV1Zeroable = false;
7903 // Check for a single input from a SCALAR_TO_VECTOR node.
7904 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7905 // all the smarts here sunk into that routine. However, the current
7906 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7907 // vector shuffle lowering is dead.
7908 if (SDValue V2S = getScalarValueForVectorElement(
7909 V2, Mask[V2Index] - Mask.size(), DAG)) {
7910 // We need to zext the scalar if it is smaller than an i32.
7911 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7912 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7913 // Using zext to expand a narrow element won't work for non-zero
7918 // Zero-extend directly to i32.
7920 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7922 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7923 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7924 EltVT == MVT::i16) {
7925 // Either not inserting from the low element of the input or the input
7926 // element size is too small to use VZEXT_MOVL to clear the high bits.
7930 if (!IsV1Zeroable) {
7931 // If V1 can't be treated as a zero vector we have fewer options to lower
7932 // this. We can't support integer vectors or non-zero targets cheaply, and
7933 // the V1 elements can't be permuted in any way.
7934 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7935 if (!VT.isFloatingPoint() || V2Index != 0)
7937 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7938 V1Mask[V2Index] = -1;
7939 if (!isNoopShuffleMask(V1Mask))
7941 // This is essentially a special case blend operation, but if we have
7942 // general purpose blend operations, they are always faster. Bail and let
7943 // the rest of the lowering handle these as blends.
7944 if (Subtarget->hasSSE41())
7947 // Otherwise, use MOVSD or MOVSS.
7948 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7949 "Only two types of floating point element types to handle!");
7950 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7954 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7956 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7959 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7960 // the desired position. Otherwise it is more efficient to do a vector
7961 // shift left. We know that we can do a vector shift left because all
7962 // the inputs are zero.
7963 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7964 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7965 V2Shuffle[V2Index] = 0;
7966 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7968 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7970 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7972 V2Index * EltVT.getSizeInBits(),
7973 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7974 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7980 /// \brief Try to lower broadcast of a single element.
7982 /// For convenience, this code also bundles all of the subtarget feature set
7983 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7984 /// a convenient way to factor it out.
7985 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7987 const X86Subtarget *Subtarget,
7988 SelectionDAG &DAG) {
7989 if (!Subtarget->hasAVX())
7991 if (VT.isInteger() && !Subtarget->hasAVX2())
7994 // Check that the mask is a broadcast.
7995 int BroadcastIdx = -1;
7997 if (M >= 0 && BroadcastIdx == -1)
7999 else if (M >= 0 && M != BroadcastIdx)
8002 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8003 "a sorted mask where the broadcast "
8006 // Go up the chain of (vector) values to try and find a scalar load that
8007 // we can combine with the broadcast.
8009 switch (V.getOpcode()) {
8010 case ISD::CONCAT_VECTORS: {
8011 int OperandSize = Mask.size() / V.getNumOperands();
8012 V = V.getOperand(BroadcastIdx / OperandSize);
8013 BroadcastIdx %= OperandSize;
8017 case ISD::INSERT_SUBVECTOR: {
8018 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8019 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8023 int BeginIdx = (int)ConstantIdx->getZExtValue();
8025 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8026 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8027 BroadcastIdx -= BeginIdx;
8038 // Check if this is a broadcast of a scalar. We special case lowering
8039 // for scalars so that we can more effectively fold with loads.
8040 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8041 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8042 V = V.getOperand(BroadcastIdx);
8044 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8046 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8048 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8049 // We can't broadcast from a vector register w/o AVX2, and we can only
8050 // broadcast from the zero-element of a vector register.
8054 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8057 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8059 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8060 /// support for floating point shuffles but not integer shuffles. These
8061 /// instructions will incur a domain crossing penalty on some chips though so
8062 /// it is better to avoid lowering through this for integer vectors where
8064 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8065 const X86Subtarget *Subtarget,
8066 SelectionDAG &DAG) {
8068 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8069 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8070 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8071 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8072 ArrayRef<int> Mask = SVOp->getMask();
8073 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8075 if (isSingleInputShuffleMask(Mask)) {
8076 // Straight shuffle of a single input vector. Simulate this by using the
8077 // single input as both of the "inputs" to this instruction..
8078 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8080 if (Subtarget->hasAVX()) {
8081 // If we have AVX, we can use VPERMILPS which will allow folding a load
8082 // into the shuffle.
8083 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8084 DAG.getConstant(SHUFPDMask, MVT::i8));
8087 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8088 DAG.getConstant(SHUFPDMask, MVT::i8));
8090 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8091 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8093 // Use dedicated unpack instructions for masks that match their pattern.
8094 if (isShuffleEquivalent(Mask, 0, 2))
8095 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8096 if (isShuffleEquivalent(Mask, 1, 3))
8097 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8099 // If we have a single input, insert that into V1 if we can do so cheaply.
8100 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8101 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8102 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8104 // Try inverting the insertion since for v2 masks it is easy to do and we
8105 // can't reliably sort the mask one way or the other.
8106 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8107 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8108 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8109 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8113 // Try to use one of the special instruction patterns to handle two common
8114 // blend patterns if a zero-blend above didn't work.
8115 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8116 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8117 // We can either use a special instruction to load over the low double or
8118 // to move just the low double.
8120 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8122 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8124 if (Subtarget->hasSSE41())
8125 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8129 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8130 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8131 DAG.getConstant(SHUFPDMask, MVT::i8));
8134 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8136 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8137 /// the integer unit to minimize domain crossing penalties. However, for blends
8138 /// it falls back to the floating point shuffle operation with appropriate bit
8140 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8141 const X86Subtarget *Subtarget,
8142 SelectionDAG &DAG) {
8144 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8145 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8146 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8147 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8148 ArrayRef<int> Mask = SVOp->getMask();
8149 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8151 if (isSingleInputShuffleMask(Mask)) {
8152 // Check for being able to broadcast a single element.
8153 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8154 Mask, Subtarget, DAG))
8157 // Straight shuffle of a single input vector. For everything from SSE2
8158 // onward this has a single fast instruction with no scary immediates.
8159 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8160 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8161 int WidenedMask[4] = {
8162 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8163 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8165 ISD::BITCAST, DL, MVT::v2i64,
8166 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8167 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8170 // If we have a single input from V2 insert that into V1 if we can do so
8172 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8173 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8174 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8176 // Try inverting the insertion since for v2 masks it is easy to do and we
8177 // can't reliably sort the mask one way or the other.
8178 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8179 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8180 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8181 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8185 // Use dedicated unpack instructions for masks that match their pattern.
8186 if (isShuffleEquivalent(Mask, 0, 2))
8187 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8188 if (isShuffleEquivalent(Mask, 1, 3))
8189 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8191 if (Subtarget->hasSSE41())
8192 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8196 // Try to use byte shift instructions.
8197 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8198 DL, MVT::v2i64, V1, V2, Mask, DAG))
8201 // Try to use byte rotation instructions.
8202 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8203 if (Subtarget->hasSSSE3())
8204 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8205 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8208 // We implement this with SHUFPD which is pretty lame because it will likely
8209 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8210 // However, all the alternatives are still more cycles and newer chips don't
8211 // have this problem. It would be really nice if x86 had better shuffles here.
8212 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8213 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8214 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8215 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8218 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8220 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8221 /// It makes no assumptions about whether this is the *best* lowering, it simply
8223 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8224 ArrayRef<int> Mask, SDValue V1,
8225 SDValue V2, SelectionDAG &DAG) {
8226 SDValue LowV = V1, HighV = V2;
8227 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8230 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8232 if (NumV2Elements == 1) {
8234 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8237 // Compute the index adjacent to V2Index and in the same half by toggling
8239 int V2AdjIndex = V2Index ^ 1;
8241 if (Mask[V2AdjIndex] == -1) {
8242 // Handles all the cases where we have a single V2 element and an undef.
8243 // This will only ever happen in the high lanes because we commute the
8244 // vector otherwise.
8246 std::swap(LowV, HighV);
8247 NewMask[V2Index] -= 4;
8249 // Handle the case where the V2 element ends up adjacent to a V1 element.
8250 // To make this work, blend them together as the first step.
8251 int V1Index = V2AdjIndex;
8252 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8253 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8254 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8256 // Now proceed to reconstruct the final blend as we have the necessary
8257 // high or low half formed.
8264 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8265 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8267 } else if (NumV2Elements == 2) {
8268 if (Mask[0] < 4 && Mask[1] < 4) {
8269 // Handle the easy case where we have V1 in the low lanes and V2 in the
8273 } else if (Mask[2] < 4 && Mask[3] < 4) {
8274 // We also handle the reversed case because this utility may get called
8275 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8276 // arrange things in the right direction.
8282 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8283 // trying to place elements directly, just blend them and set up the final
8284 // shuffle to place them.
8286 // The first two blend mask elements are for V1, the second two are for
8288 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8289 Mask[2] < 4 ? Mask[2] : Mask[3],
8290 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8291 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8292 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8293 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8295 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8298 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8299 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8300 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8301 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8304 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8305 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8308 /// \brief Lower 4-lane 32-bit floating point shuffles.
8310 /// Uses instructions exclusively from the floating point unit to minimize
8311 /// domain crossing penalties, as these are sufficient to implement all v4f32
8313 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8314 const X86Subtarget *Subtarget,
8315 SelectionDAG &DAG) {
8317 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8318 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8319 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8320 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8321 ArrayRef<int> Mask = SVOp->getMask();
8322 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8325 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8327 if (NumV2Elements == 0) {
8328 // Check for being able to broadcast a single element.
8329 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8330 Mask, Subtarget, DAG))
8333 if (Subtarget->hasAVX()) {
8334 // If we have AVX, we can use VPERMILPS which will allow folding a load
8335 // into the shuffle.
8336 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8337 getV4X86ShuffleImm8ForMask(Mask, DAG));
8340 // Otherwise, use a straight shuffle of a single input vector. We pass the
8341 // input vector to both operands to simulate this with a SHUFPS.
8342 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8343 getV4X86ShuffleImm8ForMask(Mask, DAG));
8346 // Use dedicated unpack instructions for masks that match their pattern.
8347 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8348 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8349 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8350 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8352 // There are special ways we can lower some single-element blends. However, we
8353 // have custom ways we can lower more complex single-element blends below that
8354 // we defer to if both this and BLENDPS fail to match, so restrict this to
8355 // when the V2 input is targeting element 0 of the mask -- that is the fast
8357 if (NumV2Elements == 1 && Mask[0] >= 4)
8358 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8359 Mask, Subtarget, DAG))
8362 if (Subtarget->hasSSE41())
8363 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8367 // Check for whether we can use INSERTPS to perform the blend. We only use
8368 // INSERTPS when the V1 elements are already in the correct locations
8369 // because otherwise we can just always use two SHUFPS instructions which
8370 // are much smaller to encode than a SHUFPS and an INSERTPS.
8371 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8373 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8376 // When using INSERTPS we can zero any lane of the destination. Collect
8377 // the zero inputs into a mask and drop them from the lanes of V1 which
8378 // actually need to be present as inputs to the INSERTPS.
8379 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8381 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8382 bool InsertNeedsShuffle = false;
8384 for (int i = 0; i < 4; ++i)
8388 } else if (Mask[i] != i) {
8389 InsertNeedsShuffle = true;
8394 // We don't want to use INSERTPS or other insertion techniques if it will
8395 // require shuffling anyways.
8396 if (!InsertNeedsShuffle) {
8397 // If all of V1 is zeroable, replace it with undef.
8398 if ((ZMask | 1 << V2Index) == 0xF)
8399 V1 = DAG.getUNDEF(MVT::v4f32);
8401 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8402 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8404 // Insert the V2 element into the desired position.
8405 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8406 DAG.getConstant(InsertPSMask, MVT::i8));
8410 // Otherwise fall back to a SHUFPS lowering strategy.
8411 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8414 /// \brief Lower 4-lane i32 vector shuffles.
8416 /// We try to handle these with integer-domain shuffles where we can, but for
8417 /// blends we use the floating point domain blend instructions.
8418 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8419 const X86Subtarget *Subtarget,
8420 SelectionDAG &DAG) {
8422 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8423 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8424 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8425 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8426 ArrayRef<int> Mask = SVOp->getMask();
8427 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8429 // Whenever we can lower this as a zext, that instruction is strictly faster
8430 // than any alternative. It also allows us to fold memory operands into the
8431 // shuffle in many cases.
8432 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8433 Mask, Subtarget, DAG))
8437 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8439 if (NumV2Elements == 0) {
8440 // Check for being able to broadcast a single element.
8441 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8442 Mask, Subtarget, DAG))
8445 // Straight shuffle of a single input vector. For everything from SSE2
8446 // onward this has a single fast instruction with no scary immediates.
8447 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8448 // but we aren't actually going to use the UNPCK instruction because doing
8449 // so prevents folding a load into this instruction or making a copy.
8450 const int UnpackLoMask[] = {0, 0, 1, 1};
8451 const int UnpackHiMask[] = {2, 2, 3, 3};
8452 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8453 Mask = UnpackLoMask;
8454 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8455 Mask = UnpackHiMask;
8457 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8458 getV4X86ShuffleImm8ForMask(Mask, DAG));
8461 // There are special ways we can lower some single-element blends.
8462 if (NumV2Elements == 1)
8463 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8464 Mask, Subtarget, DAG))
8467 // Use dedicated unpack instructions for masks that match their pattern.
8468 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8469 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8470 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8471 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8473 if (Subtarget->hasSSE41())
8474 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8478 // Try to use byte shift instructions.
8479 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8480 DL, MVT::v4i32, V1, V2, Mask, DAG))
8483 // Try to use byte rotation instructions.
8484 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8485 if (Subtarget->hasSSSE3())
8486 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8487 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8490 // We implement this with SHUFPS because it can blend from two vectors.
8491 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8492 // up the inputs, bypassing domain shift penalties that we would encur if we
8493 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8495 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8496 DAG.getVectorShuffle(
8498 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8499 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8502 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8503 /// shuffle lowering, and the most complex part.
8505 /// The lowering strategy is to try to form pairs of input lanes which are
8506 /// targeted at the same half of the final vector, and then use a dword shuffle
8507 /// to place them onto the right half, and finally unpack the paired lanes into
8508 /// their final position.
8510 /// The exact breakdown of how to form these dword pairs and align them on the
8511 /// correct sides is really tricky. See the comments within the function for
8512 /// more of the details.
8513 static SDValue lowerV8I16SingleInputVectorShuffle(
8514 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8515 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8516 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8517 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8518 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8520 SmallVector<int, 4> LoInputs;
8521 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8522 [](int M) { return M >= 0; });
8523 std::sort(LoInputs.begin(), LoInputs.end());
8524 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8525 SmallVector<int, 4> HiInputs;
8526 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8527 [](int M) { return M >= 0; });
8528 std::sort(HiInputs.begin(), HiInputs.end());
8529 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8531 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8532 int NumHToL = LoInputs.size() - NumLToL;
8534 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8535 int NumHToH = HiInputs.size() - NumLToH;
8536 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8537 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8538 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8539 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8541 // Check for being able to broadcast a single element.
8542 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8543 Mask, Subtarget, DAG))
8546 // Use dedicated unpack instructions for masks that match their pattern.
8547 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8548 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8549 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8550 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8552 // Try to use byte shift instructions.
8553 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8554 DL, MVT::v8i16, V, V, Mask, DAG))
8557 // Try to use byte rotation instructions.
8558 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8559 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8562 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8563 // such inputs we can swap two of the dwords across the half mark and end up
8564 // with <=2 inputs to each half in each half. Once there, we can fall through
8565 // to the generic code below. For example:
8567 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8568 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8570 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8571 // and an existing 2-into-2 on the other half. In this case we may have to
8572 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8573 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8574 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8575 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8576 // half than the one we target for fixing) will be fixed when we re-enter this
8577 // path. We will also combine away any sequence of PSHUFD instructions that
8578 // result into a single instruction. Here is an example of the tricky case:
8580 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8581 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8583 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8585 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8586 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8588 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8589 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8591 // The result is fine to be handled by the generic logic.
8592 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8593 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8594 int AOffset, int BOffset) {
8595 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8596 "Must call this with A having 3 or 1 inputs from the A half.");
8597 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8598 "Must call this with B having 1 or 3 inputs from the B half.");
8599 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8600 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8602 // Compute the index of dword with only one word among the three inputs in
8603 // a half by taking the sum of the half with three inputs and subtracting
8604 // the sum of the actual three inputs. The difference is the remaining
8607 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8608 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8609 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8610 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8611 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8612 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8613 int TripleNonInputIdx =
8614 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8615 TripleDWord = TripleNonInputIdx / 2;
8617 // We use xor with one to compute the adjacent DWord to whichever one the
8619 OneInputDWord = (OneInput / 2) ^ 1;
8621 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8622 // and BToA inputs. If there is also such a problem with the BToB and AToB
8623 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8624 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8625 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8626 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8627 // Compute how many inputs will be flipped by swapping these DWords. We
8629 // to balance this to ensure we don't form a 3-1 shuffle in the other
8631 int NumFlippedAToBInputs =
8632 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8633 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8634 int NumFlippedBToBInputs =
8635 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8636 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8637 if ((NumFlippedAToBInputs == 1 &&
8638 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8639 (NumFlippedBToBInputs == 1 &&
8640 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8641 // We choose whether to fix the A half or B half based on whether that
8642 // half has zero flipped inputs. At zero, we may not be able to fix it
8643 // with that half. We also bias towards fixing the B half because that
8644 // will more commonly be the high half, and we have to bias one way.
8645 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8646 ArrayRef<int> Inputs) {
8647 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8648 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8649 PinnedIdx ^ 1) != Inputs.end();
8650 // Determine whether the free index is in the flipped dword or the
8651 // unflipped dword based on where the pinned index is. We use this bit
8652 // in an xor to conditionally select the adjacent dword.
8653 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8654 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8655 FixFreeIdx) != Inputs.end();
8656 if (IsFixIdxInput == IsFixFreeIdxInput)
8658 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8659 FixFreeIdx) != Inputs.end();
8660 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8661 "We need to be changing the number of flipped inputs!");
8662 int PSHUFHalfMask[] = {0, 1, 2, 3};
8663 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8664 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8666 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8669 if (M != -1 && M == FixIdx)
8671 else if (M != -1 && M == FixFreeIdx)
8674 if (NumFlippedBToBInputs != 0) {
8676 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8677 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8679 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8681 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8682 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8687 int PSHUFDMask[] = {0, 1, 2, 3};
8688 PSHUFDMask[ADWord] = BDWord;
8689 PSHUFDMask[BDWord] = ADWord;
8690 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8691 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8692 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8693 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8695 // Adjust the mask to match the new locations of A and B.
8697 if (M != -1 && M/2 == ADWord)
8698 M = 2 * BDWord + M % 2;
8699 else if (M != -1 && M/2 == BDWord)
8700 M = 2 * ADWord + M % 2;
8702 // Recurse back into this routine to re-compute state now that this isn't
8703 // a 3 and 1 problem.
8704 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8707 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8708 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8709 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8710 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8712 // At this point there are at most two inputs to the low and high halves from
8713 // each half. That means the inputs can always be grouped into dwords and
8714 // those dwords can then be moved to the correct half with a dword shuffle.
8715 // We use at most one low and one high word shuffle to collect these paired
8716 // inputs into dwords, and finally a dword shuffle to place them.
8717 int PSHUFLMask[4] = {-1, -1, -1, -1};
8718 int PSHUFHMask[4] = {-1, -1, -1, -1};
8719 int PSHUFDMask[4] = {-1, -1, -1, -1};
8721 // First fix the masks for all the inputs that are staying in their
8722 // original halves. This will then dictate the targets of the cross-half
8724 auto fixInPlaceInputs =
8725 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8726 MutableArrayRef<int> SourceHalfMask,
8727 MutableArrayRef<int> HalfMask, int HalfOffset) {
8728 if (InPlaceInputs.empty())
8730 if (InPlaceInputs.size() == 1) {
8731 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8732 InPlaceInputs[0] - HalfOffset;
8733 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8736 if (IncomingInputs.empty()) {
8737 // Just fix all of the in place inputs.
8738 for (int Input : InPlaceInputs) {
8739 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8740 PSHUFDMask[Input / 2] = Input / 2;
8745 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8746 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8747 InPlaceInputs[0] - HalfOffset;
8748 // Put the second input next to the first so that they are packed into
8749 // a dword. We find the adjacent index by toggling the low bit.
8750 int AdjIndex = InPlaceInputs[0] ^ 1;
8751 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8752 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8753 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8755 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8756 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8758 // Now gather the cross-half inputs and place them into a free dword of
8759 // their target half.
8760 // FIXME: This operation could almost certainly be simplified dramatically to
8761 // look more like the 3-1 fixing operation.
8762 auto moveInputsToRightHalf = [&PSHUFDMask](
8763 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8764 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8765 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8767 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8768 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8770 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8772 int LowWord = Word & ~1;
8773 int HighWord = Word | 1;
8774 return isWordClobbered(SourceHalfMask, LowWord) ||
8775 isWordClobbered(SourceHalfMask, HighWord);
8778 if (IncomingInputs.empty())
8781 if (ExistingInputs.empty()) {
8782 // Map any dwords with inputs from them into the right half.
8783 for (int Input : IncomingInputs) {
8784 // If the source half mask maps over the inputs, turn those into
8785 // swaps and use the swapped lane.
8786 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8787 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8788 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8789 Input - SourceOffset;
8790 // We have to swap the uses in our half mask in one sweep.
8791 for (int &M : HalfMask)
8792 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8794 else if (M == Input)
8795 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8797 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8798 Input - SourceOffset &&
8799 "Previous placement doesn't match!");
8801 // Note that this correctly re-maps both when we do a swap and when
8802 // we observe the other side of the swap above. We rely on that to
8803 // avoid swapping the members of the input list directly.
8804 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8807 // Map the input's dword into the correct half.
8808 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8809 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8811 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8813 "Previous placement doesn't match!");
8816 // And just directly shift any other-half mask elements to be same-half
8817 // as we will have mirrored the dword containing the element into the
8818 // same position within that half.
8819 for (int &M : HalfMask)
8820 if (M >= SourceOffset && M < SourceOffset + 4) {
8821 M = M - SourceOffset + DestOffset;
8822 assert(M >= 0 && "This should never wrap below zero!");
8827 // Ensure we have the input in a viable dword of its current half. This
8828 // is particularly tricky because the original position may be clobbered
8829 // by inputs being moved and *staying* in that half.
8830 if (IncomingInputs.size() == 1) {
8831 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8832 int InputFixed = std::find(std::begin(SourceHalfMask),
8833 std::end(SourceHalfMask), -1) -
8834 std::begin(SourceHalfMask) + SourceOffset;
8835 SourceHalfMask[InputFixed - SourceOffset] =
8836 IncomingInputs[0] - SourceOffset;
8837 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8839 IncomingInputs[0] = InputFixed;
8841 } else if (IncomingInputs.size() == 2) {
8842 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8843 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8844 // We have two non-adjacent or clobbered inputs we need to extract from
8845 // the source half. To do this, we need to map them into some adjacent
8846 // dword slot in the source mask.
8847 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8848 IncomingInputs[1] - SourceOffset};
8850 // If there is a free slot in the source half mask adjacent to one of
8851 // the inputs, place the other input in it. We use (Index XOR 1) to
8852 // compute an adjacent index.
8853 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8854 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8855 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8856 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8857 InputsFixed[1] = InputsFixed[0] ^ 1;
8858 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8859 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8860 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8861 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8862 InputsFixed[0] = InputsFixed[1] ^ 1;
8863 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8864 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8865 // The two inputs are in the same DWord but it is clobbered and the
8866 // adjacent DWord isn't used at all. Move both inputs to the free
8868 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8869 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8870 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8871 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8873 // The only way we hit this point is if there is no clobbering
8874 // (because there are no off-half inputs to this half) and there is no
8875 // free slot adjacent to one of the inputs. In this case, we have to
8876 // swap an input with a non-input.
8877 for (int i = 0; i < 4; ++i)
8878 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8879 "We can't handle any clobbers here!");
8880 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8881 "Cannot have adjacent inputs here!");
8883 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8884 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8886 // We also have to update the final source mask in this case because
8887 // it may need to undo the above swap.
8888 for (int &M : FinalSourceHalfMask)
8889 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8890 M = InputsFixed[1] + SourceOffset;
8891 else if (M == InputsFixed[1] + SourceOffset)
8892 M = (InputsFixed[0] ^ 1) + SourceOffset;
8894 InputsFixed[1] = InputsFixed[0] ^ 1;
8897 // Point everything at the fixed inputs.
8898 for (int &M : HalfMask)
8899 if (M == IncomingInputs[0])
8900 M = InputsFixed[0] + SourceOffset;
8901 else if (M == IncomingInputs[1])
8902 M = InputsFixed[1] + SourceOffset;
8904 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8905 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8908 llvm_unreachable("Unhandled input size!");
8911 // Now hoist the DWord down to the right half.
8912 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8913 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8914 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8915 for (int &M : HalfMask)
8916 for (int Input : IncomingInputs)
8918 M = FreeDWord * 2 + Input % 2;
8920 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8921 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8922 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8923 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8925 // Now enact all the shuffles we've computed to move the inputs into their
8927 if (!isNoopShuffleMask(PSHUFLMask))
8928 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8929 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8930 if (!isNoopShuffleMask(PSHUFHMask))
8931 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8932 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8933 if (!isNoopShuffleMask(PSHUFDMask))
8934 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8935 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8936 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8937 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8939 // At this point, each half should contain all its inputs, and we can then
8940 // just shuffle them into their final position.
8941 assert(std::count_if(LoMask.begin(), LoMask.end(),
8942 [](int M) { return M >= 4; }) == 0 &&
8943 "Failed to lift all the high half inputs to the low mask!");
8944 assert(std::count_if(HiMask.begin(), HiMask.end(),
8945 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8946 "Failed to lift all the low half inputs to the high mask!");
8948 // Do a half shuffle for the low mask.
8949 if (!isNoopShuffleMask(LoMask))
8950 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8951 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8953 // Do a half shuffle with the high mask after shifting its values down.
8954 for (int &M : HiMask)
8957 if (!isNoopShuffleMask(HiMask))
8958 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8959 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8964 /// \brief Detect whether the mask pattern should be lowered through
8967 /// This essentially tests whether viewing the mask as an interleaving of two
8968 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8969 /// lowering it through interleaving is a significantly better strategy.
8970 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8971 int NumEvenInputs[2] = {0, 0};
8972 int NumOddInputs[2] = {0, 0};
8973 int NumLoInputs[2] = {0, 0};
8974 int NumHiInputs[2] = {0, 0};
8975 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8979 int InputIdx = Mask[i] >= Size;
8982 ++NumLoInputs[InputIdx];
8984 ++NumHiInputs[InputIdx];
8987 ++NumEvenInputs[InputIdx];
8989 ++NumOddInputs[InputIdx];
8992 // The minimum number of cross-input results for both the interleaved and
8993 // split cases. If interleaving results in fewer cross-input results, return
8995 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8996 NumEvenInputs[0] + NumOddInputs[1]);
8997 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8998 NumLoInputs[0] + NumHiInputs[1]);
8999 return InterleavedCrosses < SplitCrosses;
9002 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9004 /// This strategy only works when the inputs from each vector fit into a single
9005 /// half of that vector, and generally there are not so many inputs as to leave
9006 /// the in-place shuffles required highly constrained (and thus expensive). It
9007 /// shifts all the inputs into a single side of both input vectors and then
9008 /// uses an unpack to interleave these inputs in a single vector. At that
9009 /// point, we will fall back on the generic single input shuffle lowering.
9010 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9012 MutableArrayRef<int> Mask,
9013 const X86Subtarget *Subtarget,
9014 SelectionDAG &DAG) {
9015 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9016 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9017 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9018 for (int i = 0; i < 8; ++i)
9019 if (Mask[i] >= 0 && Mask[i] < 4)
9020 LoV1Inputs.push_back(i);
9021 else if (Mask[i] >= 4 && Mask[i] < 8)
9022 HiV1Inputs.push_back(i);
9023 else if (Mask[i] >= 8 && Mask[i] < 12)
9024 LoV2Inputs.push_back(i);
9025 else if (Mask[i] >= 12)
9026 HiV2Inputs.push_back(i);
9028 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9029 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9032 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9033 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9034 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9036 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9037 HiV1Inputs.size() + HiV2Inputs.size();
9039 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9040 ArrayRef<int> HiInputs, bool MoveToLo,
9042 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9043 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9044 if (BadInputs.empty())
9047 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9048 int MoveOffset = MoveToLo ? 0 : 4;
9050 if (GoodInputs.empty()) {
9051 for (int BadInput : BadInputs) {
9052 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9053 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9056 if (GoodInputs.size() == 2) {
9057 // If the low inputs are spread across two dwords, pack them into
9059 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9060 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9061 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9062 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9064 // Otherwise pin the good inputs.
9065 for (int GoodInput : GoodInputs)
9066 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9069 if (BadInputs.size() == 2) {
9070 // If we have two bad inputs then there may be either one or two good
9071 // inputs fixed in place. Find a fixed input, and then find the *other*
9072 // two adjacent indices by using modular arithmetic.
9074 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9075 [](int M) { return M >= 0; }) -
9076 std::begin(MoveMask);
9078 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9079 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9080 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9081 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9082 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9083 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9084 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9086 assert(BadInputs.size() == 1 && "All sizes handled");
9087 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9088 std::end(MoveMask), -1) -
9089 std::begin(MoveMask);
9090 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9091 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9095 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9098 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9100 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9103 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9104 // cross-half traffic in the final shuffle.
9106 // Munge the mask to be a single-input mask after the unpack merges the
9110 M = 2 * (M % 4) + (M / 8);
9112 return DAG.getVectorShuffle(
9113 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9114 DL, MVT::v8i16, V1, V2),
9115 DAG.getUNDEF(MVT::v8i16), Mask);
9118 /// \brief Generic lowering of 8-lane i16 shuffles.
9120 /// This handles both single-input shuffles and combined shuffle/blends with
9121 /// two inputs. The single input shuffles are immediately delegated to
9122 /// a dedicated lowering routine.
9124 /// The blends are lowered in one of three fundamental ways. If there are few
9125 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9126 /// of the input is significantly cheaper when lowered as an interleaving of
9127 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9128 /// halves of the inputs separately (making them have relatively few inputs)
9129 /// and then concatenate them.
9130 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9131 const X86Subtarget *Subtarget,
9132 SelectionDAG &DAG) {
9134 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9135 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9136 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9137 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9138 ArrayRef<int> OrigMask = SVOp->getMask();
9139 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9140 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9141 MutableArrayRef<int> Mask(MaskStorage);
9143 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9145 // Whenever we can lower this as a zext, that instruction is strictly faster
9146 // than any alternative.
9147 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9148 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9151 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9152 auto isV2 = [](int M) { return M >= 8; };
9154 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9155 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9157 if (NumV2Inputs == 0)
9158 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9160 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9161 "to be V1-input shuffles.");
9163 // There are special ways we can lower some single-element blends.
9164 if (NumV2Inputs == 1)
9165 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9166 Mask, Subtarget, DAG))
9169 // Use dedicated unpack instructions for masks that match their pattern.
9170 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9171 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9172 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9173 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9175 if (Subtarget->hasSSE41())
9176 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9180 // Try to use byte shift instructions.
9181 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9182 DL, MVT::v8i16, V1, V2, Mask, DAG))
9185 // Try to use byte rotation instructions.
9186 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9187 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9190 if (NumV1Inputs + NumV2Inputs <= 4)
9191 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9193 // Check whether an interleaving lowering is likely to be more efficient.
9194 // This isn't perfect but it is a strong heuristic that tends to work well on
9195 // the kinds of shuffles that show up in practice.
9197 // FIXME: Handle 1x, 2x, and 4x interleaving.
9198 if (shouldLowerAsInterleaving(Mask)) {
9199 // FIXME: Figure out whether we should pack these into the low or high
9202 int EMask[8], OMask[8];
9203 for (int i = 0; i < 4; ++i) {
9204 EMask[i] = Mask[2*i];
9205 OMask[i] = Mask[2*i + 1];
9210 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9211 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9213 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9216 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9217 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9219 for (int i = 0; i < 4; ++i) {
9220 LoBlendMask[i] = Mask[i];
9221 HiBlendMask[i] = Mask[i + 4];
9224 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9225 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9226 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9227 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9229 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9230 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9233 /// \brief Check whether a compaction lowering can be done by dropping even
9234 /// elements and compute how many times even elements must be dropped.
9236 /// This handles shuffles which take every Nth element where N is a power of
9237 /// two. Example shuffle masks:
9239 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9240 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9241 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9242 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9243 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9244 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9246 /// Any of these lanes can of course be undef.
9248 /// This routine only supports N <= 3.
9249 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9252 /// \returns N above, or the number of times even elements must be dropped if
9253 /// there is such a number. Otherwise returns zero.
9254 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9255 // Figure out whether we're looping over two inputs or just one.
9256 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9258 // The modulus for the shuffle vector entries is based on whether this is
9259 // a single input or not.
9260 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9261 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9262 "We should only be called with masks with a power-of-2 size!");
9264 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9266 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9267 // and 2^3 simultaneously. This is because we may have ambiguity with
9268 // partially undef inputs.
9269 bool ViableForN[3] = {true, true, true};
9271 for (int i = 0, e = Mask.size(); i < e; ++i) {
9272 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9277 bool IsAnyViable = false;
9278 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9279 if (ViableForN[j]) {
9282 // The shuffle mask must be equal to (i * 2^N) % M.
9283 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9286 ViableForN[j] = false;
9288 // Early exit if we exhaust the possible powers of two.
9293 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9297 // Return 0 as there is no viable power of two.
9301 /// \brief Generic lowering of v16i8 shuffles.
9303 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9304 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9305 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9306 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9308 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9309 const X86Subtarget *Subtarget,
9310 SelectionDAG &DAG) {
9312 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9313 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9314 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9315 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9316 ArrayRef<int> OrigMask = SVOp->getMask();
9317 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9319 // Try to use byte shift instructions.
9320 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9321 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9324 // Try to use byte rotation instructions.
9325 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9326 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9329 // Try to use a zext lowering.
9330 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9331 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9334 int MaskStorage[16] = {
9335 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9336 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9337 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9338 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9339 MutableArrayRef<int> Mask(MaskStorage);
9340 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9341 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9344 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9346 // For single-input shuffles, there are some nicer lowering tricks we can use.
9347 if (NumV2Elements == 0) {
9348 // Check for being able to broadcast a single element.
9349 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9350 Mask, Subtarget, DAG))
9353 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9354 // Notably, this handles splat and partial-splat shuffles more efficiently.
9355 // However, it only makes sense if the pre-duplication shuffle simplifies
9356 // things significantly. Currently, this means we need to be able to
9357 // express the pre-duplication shuffle as an i16 shuffle.
9359 // FIXME: We should check for other patterns which can be widened into an
9360 // i16 shuffle as well.
9361 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9362 for (int i = 0; i < 16; i += 2)
9363 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9368 auto tryToWidenViaDuplication = [&]() -> SDValue {
9369 if (!canWidenViaDuplication(Mask))
9371 SmallVector<int, 4> LoInputs;
9372 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9373 [](int M) { return M >= 0 && M < 8; });
9374 std::sort(LoInputs.begin(), LoInputs.end());
9375 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9377 SmallVector<int, 4> HiInputs;
9378 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9379 [](int M) { return M >= 8; });
9380 std::sort(HiInputs.begin(), HiInputs.end());
9381 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9384 bool TargetLo = LoInputs.size() >= HiInputs.size();
9385 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9386 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9388 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9389 SmallDenseMap<int, int, 8> LaneMap;
9390 for (int I : InPlaceInputs) {
9391 PreDupI16Shuffle[I/2] = I/2;
9394 int j = TargetLo ? 0 : 4, je = j + 4;
9395 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9396 // Check if j is already a shuffle of this input. This happens when
9397 // there are two adjacent bytes after we move the low one.
9398 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9399 // If we haven't yet mapped the input, search for a slot into which
9401 while (j < je && PreDupI16Shuffle[j] != -1)
9405 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9408 // Map this input with the i16 shuffle.
9409 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9412 // Update the lane map based on the mapping we ended up with.
9413 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9416 ISD::BITCAST, DL, MVT::v16i8,
9417 DAG.getVectorShuffle(MVT::v8i16, DL,
9418 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9419 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9421 // Unpack the bytes to form the i16s that will be shuffled into place.
9422 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9423 MVT::v16i8, V1, V1);
9425 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9426 for (int i = 0; i < 16; ++i)
9427 if (Mask[i] != -1) {
9428 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9429 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9430 if (PostDupI16Shuffle[i / 2] == -1)
9431 PostDupI16Shuffle[i / 2] = MappedMask;
9433 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9434 "Conflicting entrties in the original shuffle!");
9437 ISD::BITCAST, DL, MVT::v16i8,
9438 DAG.getVectorShuffle(MVT::v8i16, DL,
9439 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9440 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9442 if (SDValue V = tryToWidenViaDuplication())
9446 // Check whether an interleaving lowering is likely to be more efficient.
9447 // This isn't perfect but it is a strong heuristic that tends to work well on
9448 // the kinds of shuffles that show up in practice.
9450 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9451 if (shouldLowerAsInterleaving(Mask)) {
9452 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9453 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9455 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9456 return (M >= 8 && M < 16) || M >= 24;
9458 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9459 -1, -1, -1, -1, -1, -1, -1, -1};
9460 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9461 -1, -1, -1, -1, -1, -1, -1, -1};
9462 bool UnpackLo = NumLoHalf >= NumHiHalf;
9463 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9464 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9465 for (int i = 0; i < 8; ++i) {
9466 TargetEMask[i] = Mask[2 * i];
9467 TargetOMask[i] = Mask[2 * i + 1];
9470 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9471 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9473 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9474 MVT::v16i8, Evens, Odds);
9477 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9478 // with PSHUFB. It is important to do this before we attempt to generate any
9479 // blends but after all of the single-input lowerings. If the single input
9480 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9481 // want to preserve that and we can DAG combine any longer sequences into
9482 // a PSHUFB in the end. But once we start blending from multiple inputs,
9483 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9484 // and there are *very* few patterns that would actually be faster than the
9485 // PSHUFB approach because of its ability to zero lanes.
9487 // FIXME: The only exceptions to the above are blends which are exact
9488 // interleavings with direct instructions supporting them. We currently don't
9489 // handle those well here.
9490 if (Subtarget->hasSSSE3()) {
9493 for (int i = 0; i < 16; ++i)
9494 if (Mask[i] == -1) {
9495 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9497 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9499 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9501 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9502 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9503 if (isSingleInputShuffleMask(Mask))
9504 return V1; // Single inputs are easy.
9506 // Otherwise, blend the two.
9507 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9508 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9509 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9512 // There are special ways we can lower some single-element blends.
9513 if (NumV2Elements == 1)
9514 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9515 Mask, Subtarget, DAG))
9518 // Check whether a compaction lowering can be done. This handles shuffles
9519 // which take every Nth element for some even N. See the helper function for
9522 // We special case these as they can be particularly efficiently handled with
9523 // the PACKUSB instruction on x86 and they show up in common patterns of
9524 // rearranging bytes to truncate wide elements.
9525 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9526 // NumEvenDrops is the power of two stride of the elements. Another way of
9527 // thinking about it is that we need to drop the even elements this many
9528 // times to get the original input.
9529 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9531 // First we need to zero all the dropped bytes.
9532 assert(NumEvenDrops <= 3 &&
9533 "No support for dropping even elements more than 3 times.");
9534 // We use the mask type to pick which bytes are preserved based on how many
9535 // elements are dropped.
9536 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9537 SDValue ByteClearMask =
9538 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9539 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9540 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9542 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9544 // Now pack things back together.
9545 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9546 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9547 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9548 for (int i = 1; i < NumEvenDrops; ++i) {
9549 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9550 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9556 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9557 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9558 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9559 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9561 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9562 MutableArrayRef<int> V1HalfBlendMask,
9563 MutableArrayRef<int> V2HalfBlendMask) {
9564 for (int i = 0; i < 8; ++i)
9565 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9566 V1HalfBlendMask[i] = HalfMask[i];
9568 } else if (HalfMask[i] >= 16) {
9569 V2HalfBlendMask[i] = HalfMask[i] - 16;
9570 HalfMask[i] = i + 8;
9573 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9574 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9576 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9578 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9579 MutableArrayRef<int> HiBlendMask) {
9581 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9582 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9584 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9585 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9586 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9587 [](int M) { return M >= 0 && M % 2 == 1; })) {
9588 // Use a mask to drop the high bytes.
9589 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9590 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9591 DAG.getConstant(0x00FF, MVT::v8i16));
9593 // This will be a single vector shuffle instead of a blend so nuke V2.
9594 V2 = DAG.getUNDEF(MVT::v8i16);
9596 // Squash the masks to point directly into V1.
9597 for (int &M : LoBlendMask)
9600 for (int &M : HiBlendMask)
9604 // Otherwise just unpack the low half of V into V1 and the high half into
9605 // V2 so that we can blend them as i16s.
9606 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9607 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9608 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9609 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9612 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9613 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9614 return std::make_pair(BlendedLo, BlendedHi);
9616 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9617 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9618 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9620 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9621 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9623 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9626 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9628 /// This routine breaks down the specific type of 128-bit shuffle and
9629 /// dispatches to the lowering routines accordingly.
9630 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9631 MVT VT, const X86Subtarget *Subtarget,
9632 SelectionDAG &DAG) {
9633 switch (VT.SimpleTy) {
9635 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9637 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9639 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9641 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9643 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9645 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9648 llvm_unreachable("Unimplemented!");
9652 /// \brief Helper function to test whether a shuffle mask could be
9653 /// simplified by widening the elements being shuffled.
9655 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9656 /// leaves it in an unspecified state.
9658 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9659 /// shuffle masks. The latter have the special property of a '-2' representing
9660 /// a zero-ed lane of a vector.
9661 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9662 SmallVectorImpl<int> &WidenedMask) {
9663 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9664 // If both elements are undef, its trivial.
9665 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9666 WidenedMask.push_back(SM_SentinelUndef);
9670 // Check for an undef mask and a mask value properly aligned to fit with
9671 // a pair of values. If we find such a case, use the non-undef mask's value.
9672 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9673 WidenedMask.push_back(Mask[i + 1] / 2);
9676 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9677 WidenedMask.push_back(Mask[i] / 2);
9681 // When zeroing, we need to spread the zeroing across both lanes to widen.
9682 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9683 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9684 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9685 WidenedMask.push_back(SM_SentinelZero);
9691 // Finally check if the two mask values are adjacent and aligned with
9693 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9694 WidenedMask.push_back(Mask[i] / 2);
9698 // Otherwise we can't safely widen the elements used in this shuffle.
9701 assert(WidenedMask.size() == Mask.size() / 2 &&
9702 "Incorrect size of mask after widening the elements!");
9707 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9709 /// This routine just extracts two subvectors, shuffles them independently, and
9710 /// then concatenates them back together. This should work effectively with all
9711 /// AVX vector shuffle types.
9712 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9713 SDValue V2, ArrayRef<int> Mask,
9714 SelectionDAG &DAG) {
9715 assert(VT.getSizeInBits() >= 256 &&
9716 "Only for 256-bit or wider vector shuffles!");
9717 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9718 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9720 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9721 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9723 int NumElements = VT.getVectorNumElements();
9724 int SplitNumElements = NumElements / 2;
9725 MVT ScalarVT = VT.getScalarType();
9726 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9728 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9729 DAG.getIntPtrConstant(0));
9730 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9731 DAG.getIntPtrConstant(SplitNumElements));
9732 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9733 DAG.getIntPtrConstant(0));
9734 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9735 DAG.getIntPtrConstant(SplitNumElements));
9737 // Now create two 4-way blends of these half-width vectors.
9738 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9739 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9740 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9741 for (int i = 0; i < SplitNumElements; ++i) {
9742 int M = HalfMask[i];
9743 if (M >= NumElements) {
9744 if (M >= NumElements + SplitNumElements)
9748 V2BlendMask.push_back(M - NumElements);
9749 V1BlendMask.push_back(-1);
9750 BlendMask.push_back(SplitNumElements + i);
9751 } else if (M >= 0) {
9752 if (M >= SplitNumElements)
9756 V2BlendMask.push_back(-1);
9757 V1BlendMask.push_back(M);
9758 BlendMask.push_back(i);
9760 V2BlendMask.push_back(-1);
9761 V1BlendMask.push_back(-1);
9762 BlendMask.push_back(-1);
9766 // Because the lowering happens after all combining takes place, we need to
9767 // manually combine these blend masks as much as possible so that we create
9768 // a minimal number of high-level vector shuffle nodes.
9770 // First try just blending the halves of V1 or V2.
9771 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9772 return DAG.getUNDEF(SplitVT);
9773 if (!UseLoV2 && !UseHiV2)
9774 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9775 if (!UseLoV1 && !UseHiV1)
9776 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9778 SDValue V1Blend, V2Blend;
9779 if (UseLoV1 && UseHiV1) {
9781 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9783 // We only use half of V1 so map the usage down into the final blend mask.
9784 V1Blend = UseLoV1 ? LoV1 : HiV1;
9785 for (int i = 0; i < SplitNumElements; ++i)
9786 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9787 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9789 if (UseLoV2 && UseHiV2) {
9791 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9793 // We only use half of V2 so map the usage down into the final blend mask.
9794 V2Blend = UseLoV2 ? LoV2 : HiV2;
9795 for (int i = 0; i < SplitNumElements; ++i)
9796 if (BlendMask[i] >= SplitNumElements)
9797 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9799 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9801 SDValue Lo = HalfBlend(LoMask);
9802 SDValue Hi = HalfBlend(HiMask);
9803 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9806 /// \brief Either split a vector in halves or decompose the shuffles and the
9809 /// This is provided as a good fallback for many lowerings of non-single-input
9810 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9811 /// between splitting the shuffle into 128-bit components and stitching those
9812 /// back together vs. extracting the single-input shuffles and blending those
9814 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9815 SDValue V2, ArrayRef<int> Mask,
9816 SelectionDAG &DAG) {
9817 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9818 "lower single-input shuffles as it "
9819 "could then recurse on itself.");
9820 int Size = Mask.size();
9822 // If this can be modeled as a broadcast of two elements followed by a blend,
9823 // prefer that lowering. This is especially important because broadcasts can
9824 // often fold with memory operands.
9825 auto DoBothBroadcast = [&] {
9826 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9829 if (V2BroadcastIdx == -1)
9830 V2BroadcastIdx = M - Size;
9831 else if (M - Size != V2BroadcastIdx)
9833 } else if (M >= 0) {
9834 if (V1BroadcastIdx == -1)
9836 else if (M != V1BroadcastIdx)
9841 if (DoBothBroadcast())
9842 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9845 // If the inputs all stem from a single 128-bit lane of each input, then we
9846 // split them rather than blending because the split will decompose to
9847 // unusually few instructions.
9848 int LaneCount = VT.getSizeInBits() / 128;
9849 int LaneSize = Size / LaneCount;
9850 SmallBitVector LaneInputs[2];
9851 LaneInputs[0].resize(LaneCount, false);
9852 LaneInputs[1].resize(LaneCount, false);
9853 for (int i = 0; i < Size; ++i)
9855 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9856 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9857 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9859 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9860 // that the decomposed single-input shuffles don't end up here.
9861 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9864 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9865 /// a permutation and blend of those lanes.
9867 /// This essentially blends the out-of-lane inputs to each lane into the lane
9868 /// from a permuted copy of the vector. This lowering strategy results in four
9869 /// instructions in the worst case for a single-input cross lane shuffle which
9870 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9871 /// of. Special cases for each particular shuffle pattern should be handled
9872 /// prior to trying this lowering.
9873 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9874 SDValue V1, SDValue V2,
9876 SelectionDAG &DAG) {
9877 // FIXME: This should probably be generalized for 512-bit vectors as well.
9878 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9879 int LaneSize = Mask.size() / 2;
9881 // If there are only inputs from one 128-bit lane, splitting will in fact be
9882 // less expensive. The flags track wether the given lane contains an element
9883 // that crosses to another lane.
9884 bool LaneCrossing[2] = {false, false};
9885 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9886 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9887 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9888 if (!LaneCrossing[0] || !LaneCrossing[1])
9889 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9891 if (isSingleInputShuffleMask(Mask)) {
9892 SmallVector<int, 32> FlippedBlendMask;
9893 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9894 FlippedBlendMask.push_back(
9895 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9897 : Mask[i] % LaneSize +
9898 (i / LaneSize) * LaneSize + Size));
9900 // Flip the vector, and blend the results which should now be in-lane. The
9901 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9902 // 5 for the high source. The value 3 selects the high half of source 2 and
9903 // the value 2 selects the low half of source 2. We only use source 2 to
9904 // allow folding it into a memory operand.
9905 unsigned PERMMask = 3 | 2 << 4;
9906 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9907 V1, DAG.getConstant(PERMMask, MVT::i8));
9908 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9911 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9912 // will be handled by the above logic and a blend of the results, much like
9913 // other patterns in AVX.
9914 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9917 /// \brief Handle lowering 2-lane 128-bit shuffles.
9918 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9919 SDValue V2, ArrayRef<int> Mask,
9920 const X86Subtarget *Subtarget,
9921 SelectionDAG &DAG) {
9922 // Blends are faster and handle all the non-lane-crossing cases.
9923 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9927 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9928 VT.getVectorNumElements() / 2);
9929 // Check for patterns which can be matched with a single insert of a 128-bit
9931 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9932 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9933 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9934 DAG.getIntPtrConstant(0));
9935 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9936 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9937 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9939 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9940 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9941 DAG.getIntPtrConstant(0));
9942 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9943 DAG.getIntPtrConstant(2));
9944 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9947 // Otherwise form a 128-bit permutation.
9948 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9949 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9950 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9951 DAG.getConstant(PermMask, MVT::i8));
9954 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9956 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9957 /// isn't available.
9958 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9959 const X86Subtarget *Subtarget,
9960 SelectionDAG &DAG) {
9962 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9963 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9964 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9965 ArrayRef<int> Mask = SVOp->getMask();
9966 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9968 SmallVector<int, 4> WidenedMask;
9969 if (canWidenShuffleElements(Mask, WidenedMask))
9970 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9973 if (isSingleInputShuffleMask(Mask)) {
9974 // Check for being able to broadcast a single element.
9975 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9976 Mask, Subtarget, DAG))
9979 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9980 // Non-half-crossing single input shuffles can be lowerid with an
9981 // interleaved permutation.
9982 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9983 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9984 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9985 DAG.getConstant(VPERMILPMask, MVT::i8));
9988 // With AVX2 we have direct support for this permutation.
9989 if (Subtarget->hasAVX2())
9990 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9991 getV4X86ShuffleImm8ForMask(Mask, DAG));
9993 // Otherwise, fall back.
9994 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9998 // X86 has dedicated unpack instructions that can handle specific blend
9999 // operations: UNPCKH and UNPCKL.
10000 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10001 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10002 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10003 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10005 // If we have a single input to the zero element, insert that into V1 if we
10006 // can do so cheaply.
10007 int NumV2Elements =
10008 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10009 if (NumV2Elements == 1 && Mask[0] >= 4)
10010 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10011 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10014 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10018 // Check if the blend happens to exactly fit that of SHUFPD.
10019 if ((Mask[0] == -1 || Mask[0] < 2) &&
10020 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10021 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10022 (Mask[3] == -1 || Mask[3] >= 6)) {
10023 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10024 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10025 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10026 DAG.getConstant(SHUFPDMask, MVT::i8));
10028 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10029 (Mask[1] == -1 || Mask[1] < 2) &&
10030 (Mask[2] == -1 || Mask[2] >= 6) &&
10031 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10032 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10033 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10034 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10035 DAG.getConstant(SHUFPDMask, MVT::i8));
10038 // If we have AVX2 then we always want to lower with a blend because an v4 we
10039 // can fully permute the elements.
10040 if (Subtarget->hasAVX2())
10041 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10044 // Otherwise fall back on generic lowering.
10045 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10048 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10050 /// This routine is only called when we have AVX2 and thus a reasonable
10051 /// instruction set for v4i64 shuffling..
10052 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10053 const X86Subtarget *Subtarget,
10054 SelectionDAG &DAG) {
10056 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10057 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10058 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10059 ArrayRef<int> Mask = SVOp->getMask();
10060 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10061 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10063 SmallVector<int, 4> WidenedMask;
10064 if (canWidenShuffleElements(Mask, WidenedMask))
10065 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10068 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10072 // Check for being able to broadcast a single element.
10073 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10074 Mask, Subtarget, DAG))
10077 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10078 // use lower latency instructions that will operate on both 128-bit lanes.
10079 SmallVector<int, 2> RepeatedMask;
10080 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10081 if (isSingleInputShuffleMask(Mask)) {
10082 int PSHUFDMask[] = {-1, -1, -1, -1};
10083 for (int i = 0; i < 2; ++i)
10084 if (RepeatedMask[i] >= 0) {
10085 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10086 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10088 return DAG.getNode(
10089 ISD::BITCAST, DL, MVT::v4i64,
10090 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10091 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10092 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10095 // Use dedicated unpack instructions for masks that match their pattern.
10096 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10097 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10098 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10099 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10102 // AVX2 provides a direct instruction for permuting a single input across
10104 if (isSingleInputShuffleMask(Mask))
10105 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10106 getV4X86ShuffleImm8ForMask(Mask, DAG));
10108 // Otherwise fall back on generic blend lowering.
10109 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10113 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10115 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10116 /// isn't available.
10117 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10118 const X86Subtarget *Subtarget,
10119 SelectionDAG &DAG) {
10121 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10122 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10123 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10124 ArrayRef<int> Mask = SVOp->getMask();
10125 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10127 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10131 // Check for being able to broadcast a single element.
10132 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10133 Mask, Subtarget, DAG))
10136 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10137 // options to efficiently lower the shuffle.
10138 SmallVector<int, 4> RepeatedMask;
10139 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10140 assert(RepeatedMask.size() == 4 &&
10141 "Repeated masks must be half the mask width!");
10142 if (isSingleInputShuffleMask(Mask))
10143 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10144 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10146 // Use dedicated unpack instructions for masks that match their pattern.
10147 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10148 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10149 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10150 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10152 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10153 // have already handled any direct blends. We also need to squash the
10154 // repeated mask into a simulated v4f32 mask.
10155 for (int i = 0; i < 4; ++i)
10156 if (RepeatedMask[i] >= 8)
10157 RepeatedMask[i] -= 4;
10158 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10161 // If we have a single input shuffle with different shuffle patterns in the
10162 // two 128-bit lanes use the variable mask to VPERMILPS.
10163 if (isSingleInputShuffleMask(Mask)) {
10164 SDValue VPermMask[8];
10165 for (int i = 0; i < 8; ++i)
10166 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10167 : DAG.getConstant(Mask[i], MVT::i32);
10168 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10169 return DAG.getNode(
10170 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10171 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10173 if (Subtarget->hasAVX2())
10174 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10175 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10176 DAG.getNode(ISD::BUILD_VECTOR, DL,
10177 MVT::v8i32, VPermMask)),
10180 // Otherwise, fall back.
10181 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10185 // If we have AVX2 then we always want to lower with a blend because at v8 we
10186 // can fully permute the elements.
10187 if (Subtarget->hasAVX2())
10188 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10191 // Otherwise fall back on generic lowering.
10192 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10195 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10197 /// This routine is only called when we have AVX2 and thus a reasonable
10198 /// instruction set for v8i32 shuffling..
10199 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10200 const X86Subtarget *Subtarget,
10201 SelectionDAG &DAG) {
10203 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10204 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10205 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10206 ArrayRef<int> Mask = SVOp->getMask();
10207 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10208 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10210 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10214 // Check for being able to broadcast a single element.
10215 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10216 Mask, Subtarget, DAG))
10219 // If the shuffle mask is repeated in each 128-bit lane we can use more
10220 // efficient instructions that mirror the shuffles across the two 128-bit
10222 SmallVector<int, 4> RepeatedMask;
10223 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10224 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10225 if (isSingleInputShuffleMask(Mask))
10226 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10227 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10229 // Use dedicated unpack instructions for masks that match their pattern.
10230 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10231 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10232 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10233 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10236 // If the shuffle patterns aren't repeated but it is a single input, directly
10237 // generate a cross-lane VPERMD instruction.
10238 if (isSingleInputShuffleMask(Mask)) {
10239 SDValue VPermMask[8];
10240 for (int i = 0; i < 8; ++i)
10241 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10242 : DAG.getConstant(Mask[i], MVT::i32);
10243 return DAG.getNode(
10244 X86ISD::VPERMV, DL, MVT::v8i32,
10245 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10248 // Otherwise fall back on generic blend lowering.
10249 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10253 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10255 /// This routine is only called when we have AVX2 and thus a reasonable
10256 /// instruction set for v16i16 shuffling..
10257 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10258 const X86Subtarget *Subtarget,
10259 SelectionDAG &DAG) {
10261 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10262 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10263 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10264 ArrayRef<int> Mask = SVOp->getMask();
10265 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10266 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10268 // Check for being able to broadcast a single element.
10269 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10270 Mask, Subtarget, DAG))
10273 // There are no generalized cross-lane shuffle operations available on i16
10275 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10276 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10279 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10283 // Use dedicated unpack instructions for masks that match their pattern.
10284 if (isShuffleEquivalent(Mask,
10285 // First 128-bit lane:
10286 0, 16, 1, 17, 2, 18, 3, 19,
10287 // Second 128-bit lane:
10288 8, 24, 9, 25, 10, 26, 11, 27))
10289 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10290 if (isShuffleEquivalent(Mask,
10291 // First 128-bit lane:
10292 4, 20, 5, 21, 6, 22, 7, 23,
10293 // Second 128-bit lane:
10294 12, 28, 13, 29, 14, 30, 15, 31))
10295 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10297 if (isSingleInputShuffleMask(Mask)) {
10298 SDValue PSHUFBMask[32];
10299 for (int i = 0; i < 16; ++i) {
10300 if (Mask[i] == -1) {
10301 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10305 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10306 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10307 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10308 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10310 return DAG.getNode(
10311 ISD::BITCAST, DL, MVT::v16i16,
10313 X86ISD::PSHUFB, DL, MVT::v32i8,
10314 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10315 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10318 // Otherwise fall back on generic lowering.
10319 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10322 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10324 /// This routine is only called when we have AVX2 and thus a reasonable
10325 /// instruction set for v32i8 shuffling..
10326 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10327 const X86Subtarget *Subtarget,
10328 SelectionDAG &DAG) {
10330 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10331 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10332 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10333 ArrayRef<int> Mask = SVOp->getMask();
10334 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10335 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10337 // Check for being able to broadcast a single element.
10338 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10339 Mask, Subtarget, DAG))
10342 // There are no generalized cross-lane shuffle operations available on i8
10344 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10345 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10348 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10352 // Use dedicated unpack instructions for masks that match their pattern.
10353 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10355 if (isShuffleEquivalent(
10357 // First 128-bit lane:
10358 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10359 // Second 128-bit lane:
10360 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10361 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10362 if (isShuffleEquivalent(
10364 // First 128-bit lane:
10365 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10366 // Second 128-bit lane:
10367 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10368 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10370 if (isSingleInputShuffleMask(Mask)) {
10371 SDValue PSHUFBMask[32];
10372 for (int i = 0; i < 32; ++i)
10375 ? DAG.getUNDEF(MVT::i8)
10376 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10378 return DAG.getNode(
10379 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10380 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10383 // Otherwise fall back on generic lowering.
10384 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10387 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10389 /// This routine either breaks down the specific type of a 256-bit x86 vector
10390 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10391 /// together based on the available instructions.
10392 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10393 MVT VT, const X86Subtarget *Subtarget,
10394 SelectionDAG &DAG) {
10396 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10397 ArrayRef<int> Mask = SVOp->getMask();
10399 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10400 // check for those subtargets here and avoid much of the subtarget querying in
10401 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10402 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10403 // floating point types there eventually, just immediately cast everything to
10404 // a float and operate entirely in that domain.
10405 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10406 int ElementBits = VT.getScalarSizeInBits();
10407 if (ElementBits < 32)
10408 // No floating point type available, decompose into 128-bit vectors.
10409 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10411 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10412 VT.getVectorNumElements());
10413 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10414 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10415 return DAG.getNode(ISD::BITCAST, DL, VT,
10416 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10419 switch (VT.SimpleTy) {
10421 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10423 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10425 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10427 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10429 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10431 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10434 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10438 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10439 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10440 const X86Subtarget *Subtarget,
10441 SelectionDAG &DAG) {
10443 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10444 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10445 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10446 ArrayRef<int> Mask = SVOp->getMask();
10447 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10449 // FIXME: Implement direct support for this type!
10450 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10453 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10454 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10455 const X86Subtarget *Subtarget,
10456 SelectionDAG &DAG) {
10458 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10459 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10460 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10461 ArrayRef<int> Mask = SVOp->getMask();
10462 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10464 // FIXME: Implement direct support for this type!
10465 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10468 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10469 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10470 const X86Subtarget *Subtarget,
10471 SelectionDAG &DAG) {
10473 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10474 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10476 ArrayRef<int> Mask = SVOp->getMask();
10477 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10479 // FIXME: Implement direct support for this type!
10480 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10483 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10484 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10485 const X86Subtarget *Subtarget,
10486 SelectionDAG &DAG) {
10488 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10489 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10490 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10491 ArrayRef<int> Mask = SVOp->getMask();
10492 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10494 // FIXME: Implement direct support for this type!
10495 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10498 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10499 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10500 const X86Subtarget *Subtarget,
10501 SelectionDAG &DAG) {
10503 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10504 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10505 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10506 ArrayRef<int> Mask = SVOp->getMask();
10507 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10508 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10510 // FIXME: Implement direct support for this type!
10511 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10514 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10515 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10516 const X86Subtarget *Subtarget,
10517 SelectionDAG &DAG) {
10519 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10520 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10521 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10522 ArrayRef<int> Mask = SVOp->getMask();
10523 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10524 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10526 // FIXME: Implement direct support for this type!
10527 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10530 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10532 /// This routine either breaks down the specific type of a 512-bit x86 vector
10533 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10534 /// together based on the available instructions.
10535 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10536 MVT VT, const X86Subtarget *Subtarget,
10537 SelectionDAG &DAG) {
10539 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10540 ArrayRef<int> Mask = SVOp->getMask();
10541 assert(Subtarget->hasAVX512() &&
10542 "Cannot lower 512-bit vectors w/ basic ISA!");
10544 // Check for being able to broadcast a single element.
10545 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10546 Mask, Subtarget, DAG))
10549 // Dispatch to each element type for lowering. If we don't have supprot for
10550 // specific element type shuffles at 512 bits, immediately split them and
10551 // lower them. Each lowering routine of a given type is allowed to assume that
10552 // the requisite ISA extensions for that element type are available.
10553 switch (VT.SimpleTy) {
10555 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10557 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10559 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10561 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10563 if (Subtarget->hasBWI())
10564 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10567 if (Subtarget->hasBWI())
10568 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10572 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10575 // Otherwise fall back on splitting.
10576 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10579 /// \brief Top-level lowering for x86 vector shuffles.
10581 /// This handles decomposition, canonicalization, and lowering of all x86
10582 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10583 /// above in helper routines. The canonicalization attempts to widen shuffles
10584 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10585 /// s.t. only one of the two inputs needs to be tested, etc.
10586 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10587 SelectionDAG &DAG) {
10588 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10589 ArrayRef<int> Mask = SVOp->getMask();
10590 SDValue V1 = Op.getOperand(0);
10591 SDValue V2 = Op.getOperand(1);
10592 MVT VT = Op.getSimpleValueType();
10593 int NumElements = VT.getVectorNumElements();
10596 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10598 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10599 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10600 if (V1IsUndef && V2IsUndef)
10601 return DAG.getUNDEF(VT);
10603 // When we create a shuffle node we put the UNDEF node to second operand,
10604 // but in some cases the first operand may be transformed to UNDEF.
10605 // In this case we should just commute the node.
10607 return DAG.getCommutedVectorShuffle(*SVOp);
10609 // Check for non-undef masks pointing at an undef vector and make the masks
10610 // undef as well. This makes it easier to match the shuffle based solely on
10614 if (M >= NumElements) {
10615 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10616 for (int &M : NewMask)
10617 if (M >= NumElements)
10619 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10622 // Try to collapse shuffles into using a vector type with fewer elements but
10623 // wider element types. We cap this to not form integers or floating point
10624 // elements wider than 64 bits, but it might be interesting to form i128
10625 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10626 SmallVector<int, 16> WidenedMask;
10627 if (VT.getScalarSizeInBits() < 64 &&
10628 canWidenShuffleElements(Mask, WidenedMask)) {
10629 MVT NewEltVT = VT.isFloatingPoint()
10630 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10631 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10632 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10633 // Make sure that the new vector type is legal. For example, v2f64 isn't
10635 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10636 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10637 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10638 return DAG.getNode(ISD::BITCAST, dl, VT,
10639 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10643 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10644 for (int M : SVOp->getMask())
10646 ++NumUndefElements;
10647 else if (M < NumElements)
10652 // Commute the shuffle as needed such that more elements come from V1 than
10653 // V2. This allows us to match the shuffle pattern strictly on how many
10654 // elements come from V1 without handling the symmetric cases.
10655 if (NumV2Elements > NumV1Elements)
10656 return DAG.getCommutedVectorShuffle(*SVOp);
10658 // When the number of V1 and V2 elements are the same, try to minimize the
10659 // number of uses of V2 in the low half of the vector. When that is tied,
10660 // ensure that the sum of indices for V1 is equal to or lower than the sum
10662 if (NumV1Elements == NumV2Elements) {
10663 int LowV1Elements = 0, LowV2Elements = 0;
10664 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10665 if (M >= NumElements)
10669 if (LowV2Elements > LowV1Elements) {
10670 return DAG.getCommutedVectorShuffle(*SVOp);
10671 } else if (LowV2Elements == LowV1Elements) {
10672 int SumV1Indices = 0, SumV2Indices = 0;
10673 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10674 if (SVOp->getMask()[i] >= NumElements)
10676 else if (SVOp->getMask()[i] >= 0)
10678 if (SumV2Indices < SumV1Indices)
10679 return DAG.getCommutedVectorShuffle(*SVOp);
10683 // For each vector width, delegate to a specialized lowering routine.
10684 if (VT.getSizeInBits() == 128)
10685 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10687 if (VT.getSizeInBits() == 256)
10688 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10690 // Force AVX-512 vectors to be scalarized for now.
10691 // FIXME: Implement AVX-512 support!
10692 if (VT.getSizeInBits() == 512)
10693 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10695 llvm_unreachable("Unimplemented!");
10699 //===----------------------------------------------------------------------===//
10700 // Legacy vector shuffle lowering
10702 // This code is the legacy code handling vector shuffles until the above
10703 // replaces its functionality and performance.
10704 //===----------------------------------------------------------------------===//
10706 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10707 bool hasInt256, unsigned *MaskOut = nullptr) {
10708 MVT EltVT = VT.getVectorElementType();
10710 // There is no blend with immediate in AVX-512.
10711 if (VT.is512BitVector())
10714 if (!hasSSE41 || EltVT == MVT::i8)
10716 if (!hasInt256 && VT == MVT::v16i16)
10719 unsigned MaskValue = 0;
10720 unsigned NumElems = VT.getVectorNumElements();
10721 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10722 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10723 unsigned NumElemsInLane = NumElems / NumLanes;
10725 // Blend for v16i16 should be symetric for the both lanes.
10726 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10728 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10729 int EltIdx = MaskVals[i];
10731 if ((EltIdx < 0 || EltIdx == (int)i) &&
10732 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10735 if (((unsigned)EltIdx == (i + NumElems)) &&
10736 (SndLaneEltIdx < 0 ||
10737 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10738 MaskValue |= (1 << i);
10744 *MaskOut = MaskValue;
10748 // Try to lower a shuffle node into a simple blend instruction.
10749 // This function assumes isBlendMask returns true for this
10750 // SuffleVectorSDNode
10751 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10752 unsigned MaskValue,
10753 const X86Subtarget *Subtarget,
10754 SelectionDAG &DAG) {
10755 MVT VT = SVOp->getSimpleValueType(0);
10756 MVT EltVT = VT.getVectorElementType();
10757 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10758 Subtarget->hasInt256() && "Trying to lower a "
10759 "VECTOR_SHUFFLE to a Blend but "
10760 "with the wrong mask"));
10761 SDValue V1 = SVOp->getOperand(0);
10762 SDValue V2 = SVOp->getOperand(1);
10764 unsigned NumElems = VT.getVectorNumElements();
10766 // Convert i32 vectors to floating point if it is not AVX2.
10767 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10769 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10770 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10772 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10773 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10776 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10777 DAG.getConstant(MaskValue, MVT::i32));
10778 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10781 /// In vector type \p VT, return true if the element at index \p InputIdx
10782 /// falls on a different 128-bit lane than \p OutputIdx.
10783 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10784 unsigned OutputIdx) {
10785 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10786 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10789 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10790 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10791 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10792 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10794 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10795 SelectionDAG &DAG) {
10796 MVT VT = V1.getSimpleValueType();
10797 assert(VT.is128BitVector() || VT.is256BitVector());
10799 MVT EltVT = VT.getVectorElementType();
10800 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10801 unsigned NumElts = VT.getVectorNumElements();
10803 SmallVector<SDValue, 32> PshufbMask;
10804 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10805 int InputIdx = MaskVals[OutputIdx];
10806 unsigned InputByteIdx;
10808 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10809 InputByteIdx = 0x80;
10811 // Cross lane is not allowed.
10812 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10814 InputByteIdx = InputIdx * EltSizeInBytes;
10815 // Index is an byte offset within the 128-bit lane.
10816 InputByteIdx &= 0xf;
10819 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10820 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10821 if (InputByteIdx != 0x80)
10826 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10828 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10829 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10830 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10833 // v8i16 shuffles - Prefer shuffles in the following order:
10834 // 1. [all] pshuflw, pshufhw, optional move
10835 // 2. [ssse3] 1 x pshufb
10836 // 3. [ssse3] 2 x pshufb + 1 x por
10837 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10839 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10840 SelectionDAG &DAG) {
10841 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10842 SDValue V1 = SVOp->getOperand(0);
10843 SDValue V2 = SVOp->getOperand(1);
10845 SmallVector<int, 8> MaskVals;
10847 // Determine if more than 1 of the words in each of the low and high quadwords
10848 // of the result come from the same quadword of one of the two inputs. Undef
10849 // mask values count as coming from any quadword, for better codegen.
10851 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10852 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10853 unsigned LoQuad[] = { 0, 0, 0, 0 };
10854 unsigned HiQuad[] = { 0, 0, 0, 0 };
10855 // Indices of quads used.
10856 std::bitset<4> InputQuads;
10857 for (unsigned i = 0; i < 8; ++i) {
10858 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10859 int EltIdx = SVOp->getMaskElt(i);
10860 MaskVals.push_back(EltIdx);
10868 ++Quad[EltIdx / 4];
10869 InputQuads.set(EltIdx / 4);
10872 int BestLoQuad = -1;
10873 unsigned MaxQuad = 1;
10874 for (unsigned i = 0; i < 4; ++i) {
10875 if (LoQuad[i] > MaxQuad) {
10877 MaxQuad = LoQuad[i];
10881 int BestHiQuad = -1;
10883 for (unsigned i = 0; i < 4; ++i) {
10884 if (HiQuad[i] > MaxQuad) {
10886 MaxQuad = HiQuad[i];
10890 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10891 // of the two input vectors, shuffle them into one input vector so only a
10892 // single pshufb instruction is necessary. If there are more than 2 input
10893 // quads, disable the next transformation since it does not help SSSE3.
10894 bool V1Used = InputQuads[0] || InputQuads[1];
10895 bool V2Used = InputQuads[2] || InputQuads[3];
10896 if (Subtarget->hasSSSE3()) {
10897 if (InputQuads.count() == 2 && V1Used && V2Used) {
10898 BestLoQuad = InputQuads[0] ? 0 : 1;
10899 BestHiQuad = InputQuads[2] ? 2 : 3;
10901 if (InputQuads.count() > 2) {
10907 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10908 // the shuffle mask. If a quad is scored as -1, that means that it contains
10909 // words from all 4 input quadwords.
10911 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10913 BestLoQuad < 0 ? 0 : BestLoQuad,
10914 BestHiQuad < 0 ? 1 : BestHiQuad
10916 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10917 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10918 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10919 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10921 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10922 // source words for the shuffle, to aid later transformations.
10923 bool AllWordsInNewV = true;
10924 bool InOrder[2] = { true, true };
10925 for (unsigned i = 0; i != 8; ++i) {
10926 int idx = MaskVals[i];
10928 InOrder[i/4] = false;
10929 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10931 AllWordsInNewV = false;
10935 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10936 if (AllWordsInNewV) {
10937 for (int i = 0; i != 8; ++i) {
10938 int idx = MaskVals[i];
10941 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10942 if ((idx != i) && idx < 4)
10944 if ((idx != i) && idx > 3)
10953 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10954 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10955 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10956 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10957 unsigned TargetMask = 0;
10958 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10959 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10960 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10961 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10962 getShufflePSHUFLWImmediate(SVOp);
10963 V1 = NewV.getOperand(0);
10964 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10968 // Promote splats to a larger type which usually leads to more efficient code.
10969 // FIXME: Is this true if pshufb is available?
10970 if (SVOp->isSplat())
10971 return PromoteSplat(SVOp, DAG);
10973 // If we have SSSE3, and all words of the result are from 1 input vector,
10974 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10975 // is present, fall back to case 4.
10976 if (Subtarget->hasSSSE3()) {
10977 SmallVector<SDValue,16> pshufbMask;
10979 // If we have elements from both input vectors, set the high bit of the
10980 // shuffle mask element to zero out elements that come from V2 in the V1
10981 // mask, and elements that come from V1 in the V2 mask, so that the two
10982 // results can be OR'd together.
10983 bool TwoInputs = V1Used && V2Used;
10984 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10986 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10988 // Calculate the shuffle mask for the second input, shuffle it, and
10989 // OR it with the first shuffled input.
10990 CommuteVectorShuffleMask(MaskVals, 8);
10991 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10992 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10993 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10996 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10997 // and update MaskVals with new element order.
10998 std::bitset<8> InOrder;
10999 if (BestLoQuad >= 0) {
11000 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11001 for (int i = 0; i != 4; ++i) {
11002 int idx = MaskVals[i];
11005 } else if ((idx / 4) == BestLoQuad) {
11006 MaskV[i] = idx & 3;
11010 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11013 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11014 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11015 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11016 NewV.getOperand(0),
11017 getShufflePSHUFLWImmediate(SVOp), DAG);
11021 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11022 // and update MaskVals with the new element order.
11023 if (BestHiQuad >= 0) {
11024 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11025 for (unsigned i = 4; i != 8; ++i) {
11026 int idx = MaskVals[i];
11029 } else if ((idx / 4) == BestHiQuad) {
11030 MaskV[i] = (idx & 3) + 4;
11034 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11037 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11038 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11039 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11040 NewV.getOperand(0),
11041 getShufflePSHUFHWImmediate(SVOp), DAG);
11045 // In case BestHi & BestLo were both -1, which means each quadword has a word
11046 // from each of the four input quadwords, calculate the InOrder bitvector now
11047 // before falling through to the insert/extract cleanup.
11048 if (BestLoQuad == -1 && BestHiQuad == -1) {
11050 for (int i = 0; i != 8; ++i)
11051 if (MaskVals[i] < 0 || MaskVals[i] == i)
11055 // The other elements are put in the right place using pextrw and pinsrw.
11056 for (unsigned i = 0; i != 8; ++i) {
11059 int EltIdx = MaskVals[i];
11062 SDValue ExtOp = (EltIdx < 8) ?
11063 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11064 DAG.getIntPtrConstant(EltIdx)) :
11065 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11066 DAG.getIntPtrConstant(EltIdx - 8));
11067 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11068 DAG.getIntPtrConstant(i));
11073 /// \brief v16i16 shuffles
11075 /// FIXME: We only support generation of a single pshufb currently. We can
11076 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11077 /// well (e.g 2 x pshufb + 1 x por).
11079 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11080 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11081 SDValue V1 = SVOp->getOperand(0);
11082 SDValue V2 = SVOp->getOperand(1);
11085 if (V2.getOpcode() != ISD::UNDEF)
11088 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11089 return getPSHUFB(MaskVals, V1, dl, DAG);
11092 // v16i8 shuffles - Prefer shuffles in the following order:
11093 // 1. [ssse3] 1 x pshufb
11094 // 2. [ssse3] 2 x pshufb + 1 x por
11095 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11096 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11097 const X86Subtarget* Subtarget,
11098 SelectionDAG &DAG) {
11099 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11100 SDValue V1 = SVOp->getOperand(0);
11101 SDValue V2 = SVOp->getOperand(1);
11103 ArrayRef<int> MaskVals = SVOp->getMask();
11105 // Promote splats to a larger type which usually leads to more efficient code.
11106 // FIXME: Is this true if pshufb is available?
11107 if (SVOp->isSplat())
11108 return PromoteSplat(SVOp, DAG);
11110 // If we have SSSE3, case 1 is generated when all result bytes come from
11111 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11112 // present, fall back to case 3.
11114 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11115 if (Subtarget->hasSSSE3()) {
11116 SmallVector<SDValue,16> pshufbMask;
11118 // If all result elements are from one input vector, then only translate
11119 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11121 // Otherwise, we have elements from both input vectors, and must zero out
11122 // elements that come from V2 in the first mask, and V1 in the second mask
11123 // so that we can OR them together.
11124 for (unsigned i = 0; i != 16; ++i) {
11125 int EltIdx = MaskVals[i];
11126 if (EltIdx < 0 || EltIdx >= 16)
11128 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11130 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11131 DAG.getNode(ISD::BUILD_VECTOR, dl,
11132 MVT::v16i8, pshufbMask));
11134 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11135 // the 2nd operand if it's undefined or zero.
11136 if (V2.getOpcode() == ISD::UNDEF ||
11137 ISD::isBuildVectorAllZeros(V2.getNode()))
11140 // Calculate the shuffle mask for the second input, shuffle it, and
11141 // OR it with the first shuffled input.
11142 pshufbMask.clear();
11143 for (unsigned i = 0; i != 16; ++i) {
11144 int EltIdx = MaskVals[i];
11145 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11146 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11148 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11149 DAG.getNode(ISD::BUILD_VECTOR, dl,
11150 MVT::v16i8, pshufbMask));
11151 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11154 // No SSSE3 - Calculate in place words and then fix all out of place words
11155 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11156 // the 16 different words that comprise the two doublequadword input vectors.
11157 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11158 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11160 for (int i = 0; i != 8; ++i) {
11161 int Elt0 = MaskVals[i*2];
11162 int Elt1 = MaskVals[i*2+1];
11164 // This word of the result is all undef, skip it.
11165 if (Elt0 < 0 && Elt1 < 0)
11168 // This word of the result is already in the correct place, skip it.
11169 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11172 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11173 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11176 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11177 // using a single extract together, load it and store it.
11178 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11179 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11180 DAG.getIntPtrConstant(Elt1 / 2));
11181 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11182 DAG.getIntPtrConstant(i));
11186 // If Elt1 is defined, extract it from the appropriate source. If the
11187 // source byte is not also odd, shift the extracted word left 8 bits
11188 // otherwise clear the bottom 8 bits if we need to do an or.
11190 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11191 DAG.getIntPtrConstant(Elt1 / 2));
11192 if ((Elt1 & 1) == 0)
11193 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11195 TLI.getShiftAmountTy(InsElt.getValueType())));
11196 else if (Elt0 >= 0)
11197 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11198 DAG.getConstant(0xFF00, MVT::i16));
11200 // If Elt0 is defined, extract it from the appropriate source. If the
11201 // source byte is not also even, shift the extracted word right 8 bits. If
11202 // Elt1 was also defined, OR the extracted values together before
11203 // inserting them in the result.
11205 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11206 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11207 if ((Elt0 & 1) != 0)
11208 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11210 TLI.getShiftAmountTy(InsElt0.getValueType())));
11211 else if (Elt1 >= 0)
11212 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11213 DAG.getConstant(0x00FF, MVT::i16));
11214 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11217 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11218 DAG.getIntPtrConstant(i));
11220 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11223 // v32i8 shuffles - Translate to VPSHUFB if possible.
11225 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11226 const X86Subtarget *Subtarget,
11227 SelectionDAG &DAG) {
11228 MVT VT = SVOp->getSimpleValueType(0);
11229 SDValue V1 = SVOp->getOperand(0);
11230 SDValue V2 = SVOp->getOperand(1);
11232 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11234 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11235 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11236 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11238 // VPSHUFB may be generated if
11239 // (1) one of input vector is undefined or zeroinitializer.
11240 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11241 // And (2) the mask indexes don't cross the 128-bit lane.
11242 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11243 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11246 if (V1IsAllZero && !V2IsAllZero) {
11247 CommuteVectorShuffleMask(MaskVals, 32);
11250 return getPSHUFB(MaskVals, V1, dl, DAG);
11253 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11254 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11255 /// done when every pair / quad of shuffle mask elements point to elements in
11256 /// the right sequence. e.g.
11257 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11259 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11260 SelectionDAG &DAG) {
11261 MVT VT = SVOp->getSimpleValueType(0);
11263 unsigned NumElems = VT.getVectorNumElements();
11266 switch (VT.SimpleTy) {
11267 default: llvm_unreachable("Unexpected!");
11270 return SDValue(SVOp, 0);
11271 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11272 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11273 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11274 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11275 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11276 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11279 SmallVector<int, 8> MaskVec;
11280 for (unsigned i = 0; i != NumElems; i += Scale) {
11282 for (unsigned j = 0; j != Scale; ++j) {
11283 int EltIdx = SVOp->getMaskElt(i+j);
11287 StartIdx = (EltIdx / Scale);
11288 if (EltIdx != (int)(StartIdx*Scale + j))
11291 MaskVec.push_back(StartIdx);
11294 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11295 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11296 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11299 /// getVZextMovL - Return a zero-extending vector move low node.
11301 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11302 SDValue SrcOp, SelectionDAG &DAG,
11303 const X86Subtarget *Subtarget, SDLoc dl) {
11304 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11305 LoadSDNode *LD = nullptr;
11306 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11307 LD = dyn_cast<LoadSDNode>(SrcOp);
11309 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11311 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11312 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11313 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11314 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11315 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11317 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11318 return DAG.getNode(ISD::BITCAST, dl, VT,
11319 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11320 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11322 SrcOp.getOperand(0)
11328 return DAG.getNode(ISD::BITCAST, dl, VT,
11329 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11330 DAG.getNode(ISD::BITCAST, dl,
11334 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11335 /// which could not be matched by any known target speficic shuffle
11337 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11339 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11340 if (NewOp.getNode())
11343 MVT VT = SVOp->getSimpleValueType(0);
11345 unsigned NumElems = VT.getVectorNumElements();
11346 unsigned NumLaneElems = NumElems / 2;
11349 MVT EltVT = VT.getVectorElementType();
11350 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11353 SmallVector<int, 16> Mask;
11354 for (unsigned l = 0; l < 2; ++l) {
11355 // Build a shuffle mask for the output, discovering on the fly which
11356 // input vectors to use as shuffle operands (recorded in InputUsed).
11357 // If building a suitable shuffle vector proves too hard, then bail
11358 // out with UseBuildVector set.
11359 bool UseBuildVector = false;
11360 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11361 unsigned LaneStart = l * NumLaneElems;
11362 for (unsigned i = 0; i != NumLaneElems; ++i) {
11363 // The mask element. This indexes into the input.
11364 int Idx = SVOp->getMaskElt(i+LaneStart);
11366 // the mask element does not index into any input vector.
11367 Mask.push_back(-1);
11371 // The input vector this mask element indexes into.
11372 int Input = Idx / NumLaneElems;
11374 // Turn the index into an offset from the start of the input vector.
11375 Idx -= Input * NumLaneElems;
11377 // Find or create a shuffle vector operand to hold this input.
11379 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11380 if (InputUsed[OpNo] == Input)
11381 // This input vector is already an operand.
11383 if (InputUsed[OpNo] < 0) {
11384 // Create a new operand for this input vector.
11385 InputUsed[OpNo] = Input;
11390 if (OpNo >= array_lengthof(InputUsed)) {
11391 // More than two input vectors used! Give up on trying to create a
11392 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11393 UseBuildVector = true;
11397 // Add the mask index for the new shuffle vector.
11398 Mask.push_back(Idx + OpNo * NumLaneElems);
11401 if (UseBuildVector) {
11402 SmallVector<SDValue, 16> SVOps;
11403 for (unsigned i = 0; i != NumLaneElems; ++i) {
11404 // The mask element. This indexes into the input.
11405 int Idx = SVOp->getMaskElt(i+LaneStart);
11407 SVOps.push_back(DAG.getUNDEF(EltVT));
11411 // The input vector this mask element indexes into.
11412 int Input = Idx / NumElems;
11414 // Turn the index into an offset from the start of the input vector.
11415 Idx -= Input * NumElems;
11417 // Extract the vector element by hand.
11418 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11419 SVOp->getOperand(Input),
11420 DAG.getIntPtrConstant(Idx)));
11423 // Construct the output using a BUILD_VECTOR.
11424 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11425 } else if (InputUsed[0] < 0) {
11426 // No input vectors were used! The result is undefined.
11427 Output[l] = DAG.getUNDEF(NVT);
11429 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11430 (InputUsed[0] % 2) * NumLaneElems,
11432 // If only one input was used, use an undefined vector for the other.
11433 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11434 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11435 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11436 // At least one input vector was used. Create a new shuffle vector.
11437 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11443 // Concatenate the result back
11444 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11447 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11448 /// 4 elements, and match them with several different shuffle types.
11450 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11451 SDValue V1 = SVOp->getOperand(0);
11452 SDValue V2 = SVOp->getOperand(1);
11454 MVT VT = SVOp->getSimpleValueType(0);
11456 assert(VT.is128BitVector() && "Unsupported vector size");
11458 std::pair<int, int> Locs[4];
11459 int Mask1[] = { -1, -1, -1, -1 };
11460 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11462 unsigned NumHi = 0;
11463 unsigned NumLo = 0;
11464 for (unsigned i = 0; i != 4; ++i) {
11465 int Idx = PermMask[i];
11467 Locs[i] = std::make_pair(-1, -1);
11469 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11471 Locs[i] = std::make_pair(0, NumLo);
11472 Mask1[NumLo] = Idx;
11475 Locs[i] = std::make_pair(1, NumHi);
11477 Mask1[2+NumHi] = Idx;
11483 if (NumLo <= 2 && NumHi <= 2) {
11484 // If no more than two elements come from either vector. This can be
11485 // implemented with two shuffles. First shuffle gather the elements.
11486 // The second shuffle, which takes the first shuffle as both of its
11487 // vector operands, put the elements into the right order.
11488 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11490 int Mask2[] = { -1, -1, -1, -1 };
11492 for (unsigned i = 0; i != 4; ++i)
11493 if (Locs[i].first != -1) {
11494 unsigned Idx = (i < 2) ? 0 : 4;
11495 Idx += Locs[i].first * 2 + Locs[i].second;
11499 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11502 if (NumLo == 3 || NumHi == 3) {
11503 // Otherwise, we must have three elements from one vector, call it X, and
11504 // one element from the other, call it Y. First, use a shufps to build an
11505 // intermediate vector with the one element from Y and the element from X
11506 // that will be in the same half in the final destination (the indexes don't
11507 // matter). Then, use a shufps to build the final vector, taking the half
11508 // containing the element from Y from the intermediate, and the other half
11511 // Normalize it so the 3 elements come from V1.
11512 CommuteVectorShuffleMask(PermMask, 4);
11516 // Find the element from V2.
11518 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11519 int Val = PermMask[HiIndex];
11526 Mask1[0] = PermMask[HiIndex];
11528 Mask1[2] = PermMask[HiIndex^1];
11530 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11532 if (HiIndex >= 2) {
11533 Mask1[0] = PermMask[0];
11534 Mask1[1] = PermMask[1];
11535 Mask1[2] = HiIndex & 1 ? 6 : 4;
11536 Mask1[3] = HiIndex & 1 ? 4 : 6;
11537 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11540 Mask1[0] = HiIndex & 1 ? 2 : 0;
11541 Mask1[1] = HiIndex & 1 ? 0 : 2;
11542 Mask1[2] = PermMask[2];
11543 Mask1[3] = PermMask[3];
11548 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11551 // Break it into (shuffle shuffle_hi, shuffle_lo).
11552 int LoMask[] = { -1, -1, -1, -1 };
11553 int HiMask[] = { -1, -1, -1, -1 };
11555 int *MaskPtr = LoMask;
11556 unsigned MaskIdx = 0;
11557 unsigned LoIdx = 0;
11558 unsigned HiIdx = 2;
11559 for (unsigned i = 0; i != 4; ++i) {
11566 int Idx = PermMask[i];
11568 Locs[i] = std::make_pair(-1, -1);
11569 } else if (Idx < 4) {
11570 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11571 MaskPtr[LoIdx] = Idx;
11574 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11575 MaskPtr[HiIdx] = Idx;
11580 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11581 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11582 int MaskOps[] = { -1, -1, -1, -1 };
11583 for (unsigned i = 0; i != 4; ++i)
11584 if (Locs[i].first != -1)
11585 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11586 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11589 static bool MayFoldVectorLoad(SDValue V) {
11590 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11591 V = V.getOperand(0);
11593 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11594 V = V.getOperand(0);
11595 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11596 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11597 // BUILD_VECTOR (load), undef
11598 V = V.getOperand(0);
11600 return MayFoldLoad(V);
11604 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11605 MVT VT = Op.getSimpleValueType();
11607 // Canonizalize to v2f64.
11608 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11609 return DAG.getNode(ISD::BITCAST, dl, VT,
11610 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11615 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11617 SDValue V1 = Op.getOperand(0);
11618 SDValue V2 = Op.getOperand(1);
11619 MVT VT = Op.getSimpleValueType();
11621 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11623 if (HasSSE2 && VT == MVT::v2f64)
11624 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11626 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11627 return DAG.getNode(ISD::BITCAST, dl, VT,
11628 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11629 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11630 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11634 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11635 SDValue V1 = Op.getOperand(0);
11636 SDValue V2 = Op.getOperand(1);
11637 MVT VT = Op.getSimpleValueType();
11639 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11640 "unsupported shuffle type");
11642 if (V2.getOpcode() == ISD::UNDEF)
11646 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11650 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11651 SDValue V1 = Op.getOperand(0);
11652 SDValue V2 = Op.getOperand(1);
11653 MVT VT = Op.getSimpleValueType();
11654 unsigned NumElems = VT.getVectorNumElements();
11656 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11657 // operand of these instructions is only memory, so check if there's a
11658 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11660 bool CanFoldLoad = false;
11662 // Trivial case, when V2 comes from a load.
11663 if (MayFoldVectorLoad(V2))
11664 CanFoldLoad = true;
11666 // When V1 is a load, it can be folded later into a store in isel, example:
11667 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11669 // (MOVLPSmr addr:$src1, VR128:$src2)
11670 // So, recognize this potential and also use MOVLPS or MOVLPD
11671 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11672 CanFoldLoad = true;
11674 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11676 if (HasSSE2 && NumElems == 2)
11677 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11680 // If we don't care about the second element, proceed to use movss.
11681 if (SVOp->getMaskElt(1) != -1)
11682 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11685 // movl and movlp will both match v2i64, but v2i64 is never matched by
11686 // movl earlier because we make it strict to avoid messing with the movlp load
11687 // folding logic (see the code above getMOVLP call). Match it here then,
11688 // this is horrible, but will stay like this until we move all shuffle
11689 // matching to x86 specific nodes. Note that for the 1st condition all
11690 // types are matched with movsd.
11692 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11693 // as to remove this logic from here, as much as possible
11694 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11695 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11696 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11699 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11701 // Invert the operand order and use SHUFPS to match it.
11702 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11703 getShuffleSHUFImmediate(SVOp), DAG);
11706 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11707 SelectionDAG &DAG) {
11709 MVT VT = Load->getSimpleValueType(0);
11710 MVT EVT = VT.getVectorElementType();
11711 SDValue Addr = Load->getOperand(1);
11712 SDValue NewAddr = DAG.getNode(
11713 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11714 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11717 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11718 DAG.getMachineFunction().getMachineMemOperand(
11719 Load->getMemOperand(), 0, EVT.getStoreSize()));
11723 // It is only safe to call this function if isINSERTPSMask is true for
11724 // this shufflevector mask.
11725 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11726 SelectionDAG &DAG) {
11727 // Generate an insertps instruction when inserting an f32 from memory onto a
11728 // v4f32 or when copying a member from one v4f32 to another.
11729 // We also use it for transferring i32 from one register to another,
11730 // since it simply copies the same bits.
11731 // If we're transferring an i32 from memory to a specific element in a
11732 // register, we output a generic DAG that will match the PINSRD
11734 MVT VT = SVOp->getSimpleValueType(0);
11735 MVT EVT = VT.getVectorElementType();
11736 SDValue V1 = SVOp->getOperand(0);
11737 SDValue V2 = SVOp->getOperand(1);
11738 auto Mask = SVOp->getMask();
11739 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11740 "unsupported vector type for insertps/pinsrd");
11742 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11743 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11744 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11748 unsigned DestIndex;
11752 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11755 // If we have 1 element from each vector, we have to check if we're
11756 // changing V1's element's place. If so, we're done. Otherwise, we
11757 // should assume we're changing V2's element's place and behave
11759 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11760 assert(DestIndex <= INT32_MAX && "truncated destination index");
11761 if (FromV1 == FromV2 &&
11762 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11766 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11769 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11770 "More than one element from V1 and from V2, or no elements from one "
11771 "of the vectors. This case should not have returned true from "
11776 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11779 // Get an index into the source vector in the range [0,4) (the mask is
11780 // in the range [0,8) because it can address V1 and V2)
11781 unsigned SrcIndex = Mask[DestIndex] % 4;
11782 if (MayFoldLoad(From)) {
11783 // Trivial case, when From comes from a load and is only used by the
11784 // shuffle. Make it use insertps from the vector that we need from that
11787 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11788 if (!NewLoad.getNode())
11791 if (EVT == MVT::f32) {
11792 // Create this as a scalar to vector to match the instruction pattern.
11793 SDValue LoadScalarToVector =
11794 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11795 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11796 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11798 } else { // EVT == MVT::i32
11799 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11800 // instruction, to match the PINSRD instruction, which loads an i32 to a
11801 // certain vector element.
11802 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11803 DAG.getConstant(DestIndex, MVT::i32));
11807 // Vector-element-to-vector
11808 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11809 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11812 // Reduce a vector shuffle to zext.
11813 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11814 SelectionDAG &DAG) {
11815 // PMOVZX is only available from SSE41.
11816 if (!Subtarget->hasSSE41())
11819 MVT VT = Op.getSimpleValueType();
11821 // Only AVX2 support 256-bit vector integer extending.
11822 if (!Subtarget->hasInt256() && VT.is256BitVector())
11825 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11827 SDValue V1 = Op.getOperand(0);
11828 SDValue V2 = Op.getOperand(1);
11829 unsigned NumElems = VT.getVectorNumElements();
11831 // Extending is an unary operation and the element type of the source vector
11832 // won't be equal to or larger than i64.
11833 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11834 VT.getVectorElementType() == MVT::i64)
11837 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11838 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11839 while ((1U << Shift) < NumElems) {
11840 if (SVOp->getMaskElt(1U << Shift) == 1)
11843 // The maximal ratio is 8, i.e. from i8 to i64.
11848 // Check the shuffle mask.
11849 unsigned Mask = (1U << Shift) - 1;
11850 for (unsigned i = 0; i != NumElems; ++i) {
11851 int EltIdx = SVOp->getMaskElt(i);
11852 if ((i & Mask) != 0 && EltIdx != -1)
11854 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11858 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11859 MVT NeVT = MVT::getIntegerVT(NBits);
11860 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11862 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11865 return DAG.getNode(ISD::BITCAST, DL, VT,
11866 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11869 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11870 SelectionDAG &DAG) {
11871 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11872 MVT VT = Op.getSimpleValueType();
11874 SDValue V1 = Op.getOperand(0);
11875 SDValue V2 = Op.getOperand(1);
11877 if (isZeroShuffle(SVOp))
11878 return getZeroVector(VT, Subtarget, DAG, dl);
11880 // Handle splat operations
11881 if (SVOp->isSplat()) {
11882 // Use vbroadcast whenever the splat comes from a foldable load
11883 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11884 if (Broadcast.getNode())
11888 // Check integer expanding shuffles.
11889 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11890 if (NewOp.getNode())
11893 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11895 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11896 VT == MVT::v32i8) {
11897 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11898 if (NewOp.getNode())
11899 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11900 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11901 // FIXME: Figure out a cleaner way to do this.
11902 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11903 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11904 if (NewOp.getNode()) {
11905 MVT NewVT = NewOp.getSimpleValueType();
11906 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11907 NewVT, true, false))
11908 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11911 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11912 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11913 if (NewOp.getNode()) {
11914 MVT NewVT = NewOp.getSimpleValueType();
11915 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11916 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11925 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11926 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11927 SDValue V1 = Op.getOperand(0);
11928 SDValue V2 = Op.getOperand(1);
11929 MVT VT = Op.getSimpleValueType();
11931 unsigned NumElems = VT.getVectorNumElements();
11932 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11933 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11934 bool V1IsSplat = false;
11935 bool V2IsSplat = false;
11936 bool HasSSE2 = Subtarget->hasSSE2();
11937 bool HasFp256 = Subtarget->hasFp256();
11938 bool HasInt256 = Subtarget->hasInt256();
11939 MachineFunction &MF = DAG.getMachineFunction();
11940 bool OptForSize = MF.getFunction()->getAttributes().
11941 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11943 // Check if we should use the experimental vector shuffle lowering. If so,
11944 // delegate completely to that code path.
11945 if (ExperimentalVectorShuffleLowering)
11946 return lowerVectorShuffle(Op, Subtarget, DAG);
11948 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11950 if (V1IsUndef && V2IsUndef)
11951 return DAG.getUNDEF(VT);
11953 // When we create a shuffle node we put the UNDEF node to second operand,
11954 // but in some cases the first operand may be transformed to UNDEF.
11955 // In this case we should just commute the node.
11957 return DAG.getCommutedVectorShuffle(*SVOp);
11959 // Vector shuffle lowering takes 3 steps:
11961 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11962 // narrowing and commutation of operands should be handled.
11963 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11965 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11966 // so the shuffle can be broken into other shuffles and the legalizer can
11967 // try the lowering again.
11969 // The general idea is that no vector_shuffle operation should be left to
11970 // be matched during isel, all of them must be converted to a target specific
11973 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11974 // narrowing and commutation of operands should be handled. The actual code
11975 // doesn't include all of those, work in progress...
11976 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11977 if (NewOp.getNode())
11980 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11982 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11983 // unpckh_undef). Only use pshufd if speed is more important than size.
11984 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11985 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11986 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11987 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11989 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11990 V2IsUndef && MayFoldVectorLoad(V1))
11991 return getMOVDDup(Op, dl, V1, DAG);
11993 if (isMOVHLPS_v_undef_Mask(M, VT))
11994 return getMOVHighToLow(Op, dl, DAG);
11996 // Use to match splats
11997 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11998 (VT == MVT::v2f64 || VT == MVT::v2i64))
11999 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12001 if (isPSHUFDMask(M, VT)) {
12002 // The actual implementation will match the mask in the if above and then
12003 // during isel it can match several different instructions, not only pshufd
12004 // as its name says, sad but true, emulate the behavior for now...
12005 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12006 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12008 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12010 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12011 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12013 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12014 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12017 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12021 if (isPALIGNRMask(M, VT, Subtarget))
12022 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12023 getShufflePALIGNRImmediate(SVOp),
12026 if (isVALIGNMask(M, VT, Subtarget))
12027 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12028 getShuffleVALIGNImmediate(SVOp),
12031 // Check if this can be converted into a logical shift.
12032 bool isLeft = false;
12033 unsigned ShAmt = 0;
12035 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12036 if (isShift && ShVal.hasOneUse()) {
12037 // If the shifted value has multiple uses, it may be cheaper to use
12038 // v_set0 + movlhps or movhlps, etc.
12039 MVT EltVT = VT.getVectorElementType();
12040 ShAmt *= EltVT.getSizeInBits();
12041 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12044 if (isMOVLMask(M, VT)) {
12045 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12046 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12047 if (!isMOVLPMask(M, VT)) {
12048 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12049 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12051 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12052 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12056 // FIXME: fold these into legal mask.
12057 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12058 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12060 if (isMOVHLPSMask(M, VT))
12061 return getMOVHighToLow(Op, dl, DAG);
12063 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12064 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12066 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12067 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12069 if (isMOVLPMask(M, VT))
12070 return getMOVLP(Op, dl, DAG, HasSSE2);
12072 if (ShouldXformToMOVHLPS(M, VT) ||
12073 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12074 return DAG.getCommutedVectorShuffle(*SVOp);
12077 // No better options. Use a vshldq / vsrldq.
12078 MVT EltVT = VT.getVectorElementType();
12079 ShAmt *= EltVT.getSizeInBits();
12080 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12083 bool Commuted = false;
12084 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12085 // 1,1,1,1 -> v8i16 though.
12086 BitVector UndefElements;
12087 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12088 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12090 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12091 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12094 // Canonicalize the splat or undef, if present, to be on the RHS.
12095 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12096 CommuteVectorShuffleMask(M, NumElems);
12098 std::swap(V1IsSplat, V2IsSplat);
12102 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12103 // Shuffling low element of v1 into undef, just return v1.
12106 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12107 // the instruction selector will not match, so get a canonical MOVL with
12108 // swapped operands to undo the commute.
12109 return getMOVL(DAG, dl, VT, V2, V1);
12112 if (isUNPCKLMask(M, VT, HasInt256))
12113 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12115 if (isUNPCKHMask(M, VT, HasInt256))
12116 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12119 // Normalize mask so all entries that point to V2 points to its first
12120 // element then try to match unpck{h|l} again. If match, return a
12121 // new vector_shuffle with the corrected mask.p
12122 SmallVector<int, 8> NewMask(M.begin(), M.end());
12123 NormalizeMask(NewMask, NumElems);
12124 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12125 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12126 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12127 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12131 // Commute is back and try unpck* again.
12132 // FIXME: this seems wrong.
12133 CommuteVectorShuffleMask(M, NumElems);
12135 std::swap(V1IsSplat, V2IsSplat);
12137 if (isUNPCKLMask(M, VT, HasInt256))
12138 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12140 if (isUNPCKHMask(M, VT, HasInt256))
12141 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12144 // Normalize the node to match x86 shuffle ops if needed
12145 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12146 return DAG.getCommutedVectorShuffle(*SVOp);
12148 // The checks below are all present in isShuffleMaskLegal, but they are
12149 // inlined here right now to enable us to directly emit target specific
12150 // nodes, and remove one by one until they don't return Op anymore.
12152 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12153 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12154 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12155 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12158 if (isPSHUFHWMask(M, VT, HasInt256))
12159 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12160 getShufflePSHUFHWImmediate(SVOp),
12163 if (isPSHUFLWMask(M, VT, HasInt256))
12164 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12165 getShufflePSHUFLWImmediate(SVOp),
12168 unsigned MaskValue;
12169 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12171 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12173 if (isSHUFPMask(M, VT))
12174 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12175 getShuffleSHUFImmediate(SVOp), DAG);
12177 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12178 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12179 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12180 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12182 //===--------------------------------------------------------------------===//
12183 // Generate target specific nodes for 128 or 256-bit shuffles only
12184 // supported in the AVX instruction set.
12187 // Handle VMOVDDUPY permutations
12188 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12189 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12191 // Handle VPERMILPS/D* permutations
12192 if (isVPERMILPMask(M, VT)) {
12193 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12194 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12195 getShuffleSHUFImmediate(SVOp), DAG);
12196 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12197 getShuffleSHUFImmediate(SVOp), DAG);
12201 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12202 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12203 Idx*(NumElems/2), DAG, dl);
12205 // Handle VPERM2F128/VPERM2I128 permutations
12206 if (isVPERM2X128Mask(M, VT, HasFp256))
12207 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12208 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12210 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12211 return getINSERTPS(SVOp, dl, DAG);
12214 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12215 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12217 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12218 VT.is512BitVector()) {
12219 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12220 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12221 SmallVector<SDValue, 16> permclMask;
12222 for (unsigned i = 0; i != NumElems; ++i) {
12223 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12226 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12228 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12229 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12230 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12231 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12232 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12235 //===--------------------------------------------------------------------===//
12236 // Since no target specific shuffle was selected for this generic one,
12237 // lower it into other known shuffles. FIXME: this isn't true yet, but
12238 // this is the plan.
12241 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12242 if (VT == MVT::v8i16) {
12243 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12244 if (NewOp.getNode())
12248 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12249 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12250 if (NewOp.getNode())
12254 if (VT == MVT::v16i8) {
12255 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12256 if (NewOp.getNode())
12260 if (VT == MVT::v32i8) {
12261 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12262 if (NewOp.getNode())
12266 // Handle all 128-bit wide vectors with 4 elements, and match them with
12267 // several different shuffle types.
12268 if (NumElems == 4 && VT.is128BitVector())
12269 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12271 // Handle general 256-bit shuffles
12272 if (VT.is256BitVector())
12273 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12278 // This function assumes its argument is a BUILD_VECTOR of constants or
12279 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12281 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12282 unsigned &MaskValue) {
12284 unsigned NumElems = BuildVector->getNumOperands();
12285 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12286 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12287 unsigned NumElemsInLane = NumElems / NumLanes;
12289 // Blend for v16i16 should be symetric for the both lanes.
12290 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12291 SDValue EltCond = BuildVector->getOperand(i);
12292 SDValue SndLaneEltCond =
12293 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12295 int Lane1Cond = -1, Lane2Cond = -1;
12296 if (isa<ConstantSDNode>(EltCond))
12297 Lane1Cond = !isZero(EltCond);
12298 if (isa<ConstantSDNode>(SndLaneEltCond))
12299 Lane2Cond = !isZero(SndLaneEltCond);
12301 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12302 // Lane1Cond != 0, means we want the first argument.
12303 // Lane1Cond == 0, means we want the second argument.
12304 // The encoding of this argument is 0 for the first argument, 1
12305 // for the second. Therefore, invert the condition.
12306 MaskValue |= !Lane1Cond << i;
12307 else if (Lane1Cond < 0)
12308 MaskValue |= !Lane2Cond << i;
12315 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12317 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12318 SelectionDAG &DAG) {
12319 SDValue Cond = Op.getOperand(0);
12320 SDValue LHS = Op.getOperand(1);
12321 SDValue RHS = Op.getOperand(2);
12323 MVT VT = Op.getSimpleValueType();
12324 MVT EltVT = VT.getVectorElementType();
12325 unsigned NumElems = VT.getVectorNumElements();
12327 // There is no blend with immediate in AVX-512.
12328 if (VT.is512BitVector())
12331 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12333 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12336 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12339 // Check the mask for BLEND and build the value.
12340 unsigned MaskValue = 0;
12341 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12344 // Convert i32 vectors to floating point if it is not AVX2.
12345 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12347 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12348 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12350 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12351 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12354 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12355 DAG.getConstant(MaskValue, MVT::i32));
12356 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12359 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12360 // A vselect where all conditions and data are constants can be optimized into
12361 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12362 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12363 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12364 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12367 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12368 if (BlendOp.getNode())
12371 // Some types for vselect were previously set to Expand, not Legal or
12372 // Custom. Return an empty SDValue so we fall-through to Expand, after
12373 // the Custom lowering phase.
12374 MVT VT = Op.getSimpleValueType();
12375 switch (VT.SimpleTy) {
12380 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12385 // We couldn't create a "Blend with immediate" node.
12386 // This node should still be legal, but we'll have to emit a blendv*
12391 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12392 MVT VT = Op.getSimpleValueType();
12395 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12398 if (VT.getSizeInBits() == 8) {
12399 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12400 Op.getOperand(0), Op.getOperand(1));
12401 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12402 DAG.getValueType(VT));
12403 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12406 if (VT.getSizeInBits() == 16) {
12407 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12408 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12410 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12411 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12412 DAG.getNode(ISD::BITCAST, dl,
12415 Op.getOperand(1)));
12416 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12417 Op.getOperand(0), Op.getOperand(1));
12418 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12419 DAG.getValueType(VT));
12420 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12423 if (VT == MVT::f32) {
12424 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12425 // the result back to FR32 register. It's only worth matching if the
12426 // result has a single use which is a store or a bitcast to i32. And in
12427 // the case of a store, it's not worth it if the index is a constant 0,
12428 // because a MOVSSmr can be used instead, which is smaller and faster.
12429 if (!Op.hasOneUse())
12431 SDNode *User = *Op.getNode()->use_begin();
12432 if ((User->getOpcode() != ISD::STORE ||
12433 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12434 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12435 (User->getOpcode() != ISD::BITCAST ||
12436 User->getValueType(0) != MVT::i32))
12438 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12439 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12442 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12445 if (VT == MVT::i32 || VT == MVT::i64) {
12446 // ExtractPS/pextrq works with constant index.
12447 if (isa<ConstantSDNode>(Op.getOperand(1)))
12453 /// Extract one bit from mask vector, like v16i1 or v8i1.
12454 /// AVX-512 feature.
12456 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12457 SDValue Vec = Op.getOperand(0);
12459 MVT VecVT = Vec.getSimpleValueType();
12460 SDValue Idx = Op.getOperand(1);
12461 MVT EltVT = Op.getSimpleValueType();
12463 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12465 // variable index can't be handled in mask registers,
12466 // extend vector to VR512
12467 if (!isa<ConstantSDNode>(Idx)) {
12468 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12469 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12470 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12471 ExtVT.getVectorElementType(), Ext, Idx);
12472 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12475 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12476 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12477 unsigned MaxSift = rc->getSize()*8 - 1;
12478 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12479 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12480 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12481 DAG.getConstant(MaxSift, MVT::i8));
12482 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12483 DAG.getIntPtrConstant(0));
12487 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12488 SelectionDAG &DAG) const {
12490 SDValue Vec = Op.getOperand(0);
12491 MVT VecVT = Vec.getSimpleValueType();
12492 SDValue Idx = Op.getOperand(1);
12494 if (Op.getSimpleValueType() == MVT::i1)
12495 return ExtractBitFromMaskVector(Op, DAG);
12497 if (!isa<ConstantSDNode>(Idx)) {
12498 if (VecVT.is512BitVector() ||
12499 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12500 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12503 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12504 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12505 MaskEltVT.getSizeInBits());
12507 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12508 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12509 getZeroVector(MaskVT, Subtarget, DAG, dl),
12510 Idx, DAG.getConstant(0, getPointerTy()));
12511 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12512 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12513 Perm, DAG.getConstant(0, getPointerTy()));
12518 // If this is a 256-bit vector result, first extract the 128-bit vector and
12519 // then extract the element from the 128-bit vector.
12520 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12522 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12523 // Get the 128-bit vector.
12524 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12525 MVT EltVT = VecVT.getVectorElementType();
12527 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12529 //if (IdxVal >= NumElems/2)
12530 // IdxVal -= NumElems/2;
12531 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12532 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12533 DAG.getConstant(IdxVal, MVT::i32));
12536 assert(VecVT.is128BitVector() && "Unexpected vector length");
12538 if (Subtarget->hasSSE41()) {
12539 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12544 MVT VT = Op.getSimpleValueType();
12545 // TODO: handle v16i8.
12546 if (VT.getSizeInBits() == 16) {
12547 SDValue Vec = Op.getOperand(0);
12548 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12550 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12551 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12552 DAG.getNode(ISD::BITCAST, dl,
12554 Op.getOperand(1)));
12555 // Transform it so it match pextrw which produces a 32-bit result.
12556 MVT EltVT = MVT::i32;
12557 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12558 Op.getOperand(0), Op.getOperand(1));
12559 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12560 DAG.getValueType(VT));
12561 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12564 if (VT.getSizeInBits() == 32) {
12565 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12569 // SHUFPS the element to the lowest double word, then movss.
12570 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12571 MVT VVT = Op.getOperand(0).getSimpleValueType();
12572 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12573 DAG.getUNDEF(VVT), Mask);
12574 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12575 DAG.getIntPtrConstant(0));
12578 if (VT.getSizeInBits() == 64) {
12579 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12580 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12581 // to match extract_elt for f64.
12582 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12586 // UNPCKHPD the element to the lowest double word, then movsd.
12587 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12588 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12589 int Mask[2] = { 1, -1 };
12590 MVT VVT = Op.getOperand(0).getSimpleValueType();
12591 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12592 DAG.getUNDEF(VVT), Mask);
12593 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12594 DAG.getIntPtrConstant(0));
12600 /// Insert one bit to mask vector, like v16i1 or v8i1.
12601 /// AVX-512 feature.
12603 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12605 SDValue Vec = Op.getOperand(0);
12606 SDValue Elt = Op.getOperand(1);
12607 SDValue Idx = Op.getOperand(2);
12608 MVT VecVT = Vec.getSimpleValueType();
12610 if (!isa<ConstantSDNode>(Idx)) {
12611 // Non constant index. Extend source and destination,
12612 // insert element and then truncate the result.
12613 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12614 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12615 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12616 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12617 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12618 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12621 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12622 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12623 if (Vec.getOpcode() == ISD::UNDEF)
12624 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12625 DAG.getConstant(IdxVal, MVT::i8));
12626 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12627 unsigned MaxSift = rc->getSize()*8 - 1;
12628 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12629 DAG.getConstant(MaxSift, MVT::i8));
12630 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12631 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12632 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12635 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12636 SelectionDAG &DAG) const {
12637 MVT VT = Op.getSimpleValueType();
12638 MVT EltVT = VT.getVectorElementType();
12640 if (EltVT == MVT::i1)
12641 return InsertBitToMaskVector(Op, DAG);
12644 SDValue N0 = Op.getOperand(0);
12645 SDValue N1 = Op.getOperand(1);
12646 SDValue N2 = Op.getOperand(2);
12647 if (!isa<ConstantSDNode>(N2))
12649 auto *N2C = cast<ConstantSDNode>(N2);
12650 unsigned IdxVal = N2C->getZExtValue();
12652 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12653 // into that, and then insert the subvector back into the result.
12654 if (VT.is256BitVector() || VT.is512BitVector()) {
12655 // Get the desired 128-bit vector half.
12656 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12658 // Insert the element into the desired half.
12659 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12660 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12662 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12663 DAG.getConstant(IdxIn128, MVT::i32));
12665 // Insert the changed part back to the 256-bit vector
12666 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12668 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12670 if (Subtarget->hasSSE41()) {
12671 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12673 if (VT == MVT::v8i16) {
12674 Opc = X86ISD::PINSRW;
12676 assert(VT == MVT::v16i8);
12677 Opc = X86ISD::PINSRB;
12680 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12682 if (N1.getValueType() != MVT::i32)
12683 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12684 if (N2.getValueType() != MVT::i32)
12685 N2 = DAG.getIntPtrConstant(IdxVal);
12686 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12689 if (EltVT == MVT::f32) {
12690 // Bits [7:6] of the constant are the source select. This will always be
12691 // zero here. The DAG Combiner may combine an extract_elt index into
12693 // bits. For example (insert (extract, 3), 2) could be matched by
12695 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12696 // Bits [5:4] of the constant are the destination select. This is the
12697 // value of the incoming immediate.
12698 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12699 // combine either bitwise AND or insert of float 0.0 to set these bits.
12700 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12701 // Create this as a scalar to vector..
12702 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12703 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12706 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12707 // PINSR* works with constant index.
12712 if (EltVT == MVT::i8)
12715 if (EltVT.getSizeInBits() == 16) {
12716 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12717 // as its second argument.
12718 if (N1.getValueType() != MVT::i32)
12719 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12720 if (N2.getValueType() != MVT::i32)
12721 N2 = DAG.getIntPtrConstant(IdxVal);
12722 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12727 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12729 MVT OpVT = Op.getSimpleValueType();
12731 // If this is a 256-bit vector result, first insert into a 128-bit
12732 // vector and then insert into the 256-bit vector.
12733 if (!OpVT.is128BitVector()) {
12734 // Insert into a 128-bit vector.
12735 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12736 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12737 OpVT.getVectorNumElements() / SizeFactor);
12739 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12741 // Insert the 128-bit vector.
12742 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12745 if (OpVT == MVT::v1i64 &&
12746 Op.getOperand(0).getValueType() == MVT::i64)
12747 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12749 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12750 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12751 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12752 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12755 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12756 // a simple subregister reference or explicit instructions to grab
12757 // upper bits of a vector.
12758 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12759 SelectionDAG &DAG) {
12761 SDValue In = Op.getOperand(0);
12762 SDValue Idx = Op.getOperand(1);
12763 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12764 MVT ResVT = Op.getSimpleValueType();
12765 MVT InVT = In.getSimpleValueType();
12767 if (Subtarget->hasFp256()) {
12768 if (ResVT.is128BitVector() &&
12769 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12770 isa<ConstantSDNode>(Idx)) {
12771 return Extract128BitVector(In, IdxVal, DAG, dl);
12773 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12774 isa<ConstantSDNode>(Idx)) {
12775 return Extract256BitVector(In, IdxVal, DAG, dl);
12781 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12782 // simple superregister reference or explicit instructions to insert
12783 // the upper bits of a vector.
12784 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12785 SelectionDAG &DAG) {
12786 if (Subtarget->hasFp256()) {
12787 SDLoc dl(Op.getNode());
12788 SDValue Vec = Op.getNode()->getOperand(0);
12789 SDValue SubVec = Op.getNode()->getOperand(1);
12790 SDValue Idx = Op.getNode()->getOperand(2);
12792 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12793 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12794 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12795 isa<ConstantSDNode>(Idx)) {
12796 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12797 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12800 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12801 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12802 isa<ConstantSDNode>(Idx)) {
12803 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12804 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12810 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12811 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12812 // one of the above mentioned nodes. It has to be wrapped because otherwise
12813 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12814 // be used to form addressing mode. These wrapped nodes will be selected
12817 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12818 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12820 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12821 // global base reg.
12822 unsigned char OpFlag = 0;
12823 unsigned WrapperKind = X86ISD::Wrapper;
12824 CodeModel::Model M = DAG.getTarget().getCodeModel();
12826 if (Subtarget->isPICStyleRIPRel() &&
12827 (M == CodeModel::Small || M == CodeModel::Kernel))
12828 WrapperKind = X86ISD::WrapperRIP;
12829 else if (Subtarget->isPICStyleGOT())
12830 OpFlag = X86II::MO_GOTOFF;
12831 else if (Subtarget->isPICStyleStubPIC())
12832 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12834 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12835 CP->getAlignment(),
12836 CP->getOffset(), OpFlag);
12838 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12839 // With PIC, the address is actually $g + Offset.
12841 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12842 DAG.getNode(X86ISD::GlobalBaseReg,
12843 SDLoc(), getPointerTy()),
12850 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12851 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12853 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12854 // global base reg.
12855 unsigned char OpFlag = 0;
12856 unsigned WrapperKind = X86ISD::Wrapper;
12857 CodeModel::Model M = DAG.getTarget().getCodeModel();
12859 if (Subtarget->isPICStyleRIPRel() &&
12860 (M == CodeModel::Small || M == CodeModel::Kernel))
12861 WrapperKind = X86ISD::WrapperRIP;
12862 else if (Subtarget->isPICStyleGOT())
12863 OpFlag = X86II::MO_GOTOFF;
12864 else if (Subtarget->isPICStyleStubPIC())
12865 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12867 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12870 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12872 // With PIC, the address is actually $g + Offset.
12874 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12875 DAG.getNode(X86ISD::GlobalBaseReg,
12876 SDLoc(), getPointerTy()),
12883 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12884 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12886 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12887 // global base reg.
12888 unsigned char OpFlag = 0;
12889 unsigned WrapperKind = X86ISD::Wrapper;
12890 CodeModel::Model M = DAG.getTarget().getCodeModel();
12892 if (Subtarget->isPICStyleRIPRel() &&
12893 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12894 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12895 OpFlag = X86II::MO_GOTPCREL;
12896 WrapperKind = X86ISD::WrapperRIP;
12897 } else if (Subtarget->isPICStyleGOT()) {
12898 OpFlag = X86II::MO_GOT;
12899 } else if (Subtarget->isPICStyleStubPIC()) {
12900 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12901 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12902 OpFlag = X86II::MO_DARWIN_NONLAZY;
12905 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12908 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12910 // With PIC, the address is actually $g + Offset.
12911 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12912 !Subtarget->is64Bit()) {
12913 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12914 DAG.getNode(X86ISD::GlobalBaseReg,
12915 SDLoc(), getPointerTy()),
12919 // For symbols that require a load from a stub to get the address, emit the
12921 if (isGlobalStubReference(OpFlag))
12922 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12923 MachinePointerInfo::getGOT(), false, false, false, 0);
12929 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12930 // Create the TargetBlockAddressAddress node.
12931 unsigned char OpFlags =
12932 Subtarget->ClassifyBlockAddressReference();
12933 CodeModel::Model M = DAG.getTarget().getCodeModel();
12934 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12935 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12937 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12940 if (Subtarget->isPICStyleRIPRel() &&
12941 (M == CodeModel::Small || M == CodeModel::Kernel))
12942 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12944 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12946 // With PIC, the address is actually $g + Offset.
12947 if (isGlobalRelativeToPICBase(OpFlags)) {
12948 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12949 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12957 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12958 int64_t Offset, SelectionDAG &DAG) const {
12959 // Create the TargetGlobalAddress node, folding in the constant
12960 // offset if it is legal.
12961 unsigned char OpFlags =
12962 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12963 CodeModel::Model M = DAG.getTarget().getCodeModel();
12965 if (OpFlags == X86II::MO_NO_FLAG &&
12966 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12967 // A direct static reference to a global.
12968 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12971 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12974 if (Subtarget->isPICStyleRIPRel() &&
12975 (M == CodeModel::Small || M == CodeModel::Kernel))
12976 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12978 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12980 // With PIC, the address is actually $g + Offset.
12981 if (isGlobalRelativeToPICBase(OpFlags)) {
12982 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12983 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12987 // For globals that require a load from a stub to get the address, emit the
12989 if (isGlobalStubReference(OpFlags))
12990 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12991 MachinePointerInfo::getGOT(), false, false, false, 0);
12993 // If there was a non-zero offset that we didn't fold, create an explicit
12994 // addition for it.
12996 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12997 DAG.getConstant(Offset, getPointerTy()));
13003 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13004 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13005 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13006 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13010 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13011 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13012 unsigned char OperandFlags, bool LocalDynamic = false) {
13013 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13014 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13016 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13017 GA->getValueType(0),
13021 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13025 SDValue Ops[] = { Chain, TGA, *InFlag };
13026 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13028 SDValue Ops[] = { Chain, TGA };
13029 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13032 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13033 MFI->setAdjustsStack(true);
13034 MFI->setHasCalls(true);
13036 SDValue Flag = Chain.getValue(1);
13037 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13040 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13042 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13045 SDLoc dl(GA); // ? function entry point might be better
13046 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13047 DAG.getNode(X86ISD::GlobalBaseReg,
13048 SDLoc(), PtrVT), InFlag);
13049 InFlag = Chain.getValue(1);
13051 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13054 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13056 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13058 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13059 X86::RAX, X86II::MO_TLSGD);
13062 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13068 // Get the start address of the TLS block for this module.
13069 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13070 .getInfo<X86MachineFunctionInfo>();
13071 MFI->incNumLocalDynamicTLSAccesses();
13075 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13076 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13079 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13080 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13081 InFlag = Chain.getValue(1);
13082 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13083 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13086 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13090 unsigned char OperandFlags = X86II::MO_DTPOFF;
13091 unsigned WrapperKind = X86ISD::Wrapper;
13092 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13093 GA->getValueType(0),
13094 GA->getOffset(), OperandFlags);
13095 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13097 // Add x@dtpoff with the base.
13098 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13101 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13102 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13103 const EVT PtrVT, TLSModel::Model model,
13104 bool is64Bit, bool isPIC) {
13107 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13108 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13109 is64Bit ? 257 : 256));
13111 SDValue ThreadPointer =
13112 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13113 MachinePointerInfo(Ptr), false, false, false, 0);
13115 unsigned char OperandFlags = 0;
13116 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13118 unsigned WrapperKind = X86ISD::Wrapper;
13119 if (model == TLSModel::LocalExec) {
13120 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13121 } else if (model == TLSModel::InitialExec) {
13123 OperandFlags = X86II::MO_GOTTPOFF;
13124 WrapperKind = X86ISD::WrapperRIP;
13126 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13129 llvm_unreachable("Unexpected model");
13132 // emit "addl x@ntpoff,%eax" (local exec)
13133 // or "addl x@indntpoff,%eax" (initial exec)
13134 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13136 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13137 GA->getOffset(), OperandFlags);
13138 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13140 if (model == TLSModel::InitialExec) {
13141 if (isPIC && !is64Bit) {
13142 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13143 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13147 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13148 MachinePointerInfo::getGOT(), false, false, false, 0);
13151 // The address of the thread local variable is the add of the thread
13152 // pointer with the offset of the variable.
13153 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13157 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13159 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13160 const GlobalValue *GV = GA->getGlobal();
13162 if (Subtarget->isTargetELF()) {
13163 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13166 case TLSModel::GeneralDynamic:
13167 if (Subtarget->is64Bit())
13168 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13169 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13170 case TLSModel::LocalDynamic:
13171 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13172 Subtarget->is64Bit());
13173 case TLSModel::InitialExec:
13174 case TLSModel::LocalExec:
13175 return LowerToTLSExecModel(
13176 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13177 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13179 llvm_unreachable("Unknown TLS model.");
13182 if (Subtarget->isTargetDarwin()) {
13183 // Darwin only has one model of TLS. Lower to that.
13184 unsigned char OpFlag = 0;
13185 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13186 X86ISD::WrapperRIP : X86ISD::Wrapper;
13188 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13189 // global base reg.
13190 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13191 !Subtarget->is64Bit();
13193 OpFlag = X86II::MO_TLVP_PIC_BASE;
13195 OpFlag = X86II::MO_TLVP;
13197 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13198 GA->getValueType(0),
13199 GA->getOffset(), OpFlag);
13200 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13202 // With PIC32, the address is actually $g + Offset.
13204 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13205 DAG.getNode(X86ISD::GlobalBaseReg,
13206 SDLoc(), getPointerTy()),
13209 // Lowering the machine isd will make sure everything is in the right
13211 SDValue Chain = DAG.getEntryNode();
13212 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13213 SDValue Args[] = { Chain, Offset };
13214 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13216 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13217 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13218 MFI->setAdjustsStack(true);
13220 // And our return value (tls address) is in the standard call return value
13222 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13223 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13224 Chain.getValue(1));
13227 if (Subtarget->isTargetKnownWindowsMSVC() ||
13228 Subtarget->isTargetWindowsGNU()) {
13229 // Just use the implicit TLS architecture
13230 // Need to generate someting similar to:
13231 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13233 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13234 // mov rcx, qword [rdx+rcx*8]
13235 // mov eax, .tls$:tlsvar
13236 // [rax+rcx] contains the address
13237 // Windows 64bit: gs:0x58
13238 // Windows 32bit: fs:__tls_array
13241 SDValue Chain = DAG.getEntryNode();
13243 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13244 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13245 // use its literal value of 0x2C.
13246 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13247 ? Type::getInt8PtrTy(*DAG.getContext(),
13249 : Type::getInt32PtrTy(*DAG.getContext(),
13253 Subtarget->is64Bit()
13254 ? DAG.getIntPtrConstant(0x58)
13255 : (Subtarget->isTargetWindowsGNU()
13256 ? DAG.getIntPtrConstant(0x2C)
13257 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13259 SDValue ThreadPointer =
13260 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13261 MachinePointerInfo(Ptr), false, false, false, 0);
13263 // Load the _tls_index variable
13264 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13265 if (Subtarget->is64Bit())
13266 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13267 IDX, MachinePointerInfo(), MVT::i32,
13268 false, false, false, 0);
13270 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13271 false, false, false, 0);
13273 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13275 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13277 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13278 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13279 false, false, false, 0);
13281 // Get the offset of start of .tls section
13282 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13283 GA->getValueType(0),
13284 GA->getOffset(), X86II::MO_SECREL);
13285 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13287 // The address of the thread local variable is the add of the thread
13288 // pointer with the offset of the variable.
13289 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13292 llvm_unreachable("TLS not implemented for this target.");
13295 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13296 /// and take a 2 x i32 value to shift plus a shift amount.
13297 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13298 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13299 MVT VT = Op.getSimpleValueType();
13300 unsigned VTBits = VT.getSizeInBits();
13302 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13303 SDValue ShOpLo = Op.getOperand(0);
13304 SDValue ShOpHi = Op.getOperand(1);
13305 SDValue ShAmt = Op.getOperand(2);
13306 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13307 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13309 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13310 DAG.getConstant(VTBits - 1, MVT::i8));
13311 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13312 DAG.getConstant(VTBits - 1, MVT::i8))
13313 : DAG.getConstant(0, VT);
13315 SDValue Tmp2, Tmp3;
13316 if (Op.getOpcode() == ISD::SHL_PARTS) {
13317 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13318 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13320 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13321 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13324 // If the shift amount is larger or equal than the width of a part we can't
13325 // rely on the results of shld/shrd. Insert a test and select the appropriate
13326 // values for large shift amounts.
13327 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13328 DAG.getConstant(VTBits, MVT::i8));
13329 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13330 AndNode, DAG.getConstant(0, MVT::i8));
13333 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13334 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13335 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13337 if (Op.getOpcode() == ISD::SHL_PARTS) {
13338 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13339 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13341 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13342 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13345 SDValue Ops[2] = { Lo, Hi };
13346 return DAG.getMergeValues(Ops, dl);
13349 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13350 SelectionDAG &DAG) const {
13351 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13354 if (SrcVT.isVector()) {
13355 if (SrcVT.getVectorElementType() == MVT::i1) {
13356 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13357 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13358 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13359 Op.getOperand(0)));
13364 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13365 "Unknown SINT_TO_FP to lower!");
13367 // These are really Legal; return the operand so the caller accepts it as
13369 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13371 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13372 Subtarget->is64Bit()) {
13376 unsigned Size = SrcVT.getSizeInBits()/8;
13377 MachineFunction &MF = DAG.getMachineFunction();
13378 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13379 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13380 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13382 MachinePointerInfo::getFixedStack(SSFI),
13384 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13387 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13389 SelectionDAG &DAG) const {
13393 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13395 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13397 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13399 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13401 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13402 MachineMemOperand *MMO;
13404 int SSFI = FI->getIndex();
13406 DAG.getMachineFunction()
13407 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13408 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13410 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13411 StackSlot = StackSlot.getOperand(1);
13413 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13414 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13416 Tys, Ops, SrcVT, MMO);
13419 Chain = Result.getValue(1);
13420 SDValue InFlag = Result.getValue(2);
13422 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13423 // shouldn't be necessary except that RFP cannot be live across
13424 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13425 MachineFunction &MF = DAG.getMachineFunction();
13426 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13427 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13428 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13429 Tys = DAG.getVTList(MVT::Other);
13431 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13433 MachineMemOperand *MMO =
13434 DAG.getMachineFunction()
13435 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13436 MachineMemOperand::MOStore, SSFISize, SSFISize);
13438 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13439 Ops, Op.getValueType(), MMO);
13440 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13441 MachinePointerInfo::getFixedStack(SSFI),
13442 false, false, false, 0);
13448 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13449 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13450 SelectionDAG &DAG) const {
13451 // This algorithm is not obvious. Here it is what we're trying to output:
13454 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13455 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13457 haddpd %xmm0, %xmm0
13459 pshufd $0x4e, %xmm0, %xmm1
13465 LLVMContext *Context = DAG.getContext();
13467 // Build some magic constants.
13468 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13469 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13470 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13472 SmallVector<Constant*,2> CV1;
13474 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13475 APInt(64, 0x4330000000000000ULL))));
13477 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13478 APInt(64, 0x4530000000000000ULL))));
13479 Constant *C1 = ConstantVector::get(CV1);
13480 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13482 // Load the 64-bit value into an XMM register.
13483 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13485 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13486 MachinePointerInfo::getConstantPool(),
13487 false, false, false, 16);
13488 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13489 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13492 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13493 MachinePointerInfo::getConstantPool(),
13494 false, false, false, 16);
13495 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13496 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13499 if (Subtarget->hasSSE3()) {
13500 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13501 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13503 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13504 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13506 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13507 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13511 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13512 DAG.getIntPtrConstant(0));
13515 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13516 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13517 SelectionDAG &DAG) const {
13519 // FP constant to bias correct the final result.
13520 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13523 // Load the 32-bit value into an XMM register.
13524 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13527 // Zero out the upper parts of the register.
13528 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13530 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13531 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13532 DAG.getIntPtrConstant(0));
13534 // Or the load with the bias.
13535 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13536 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13537 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13538 MVT::v2f64, Load)),
13539 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13540 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13541 MVT::v2f64, Bias)));
13542 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13543 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13544 DAG.getIntPtrConstant(0));
13546 // Subtract the bias.
13547 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13549 // Handle final rounding.
13550 EVT DestVT = Op.getValueType();
13552 if (DestVT.bitsLT(MVT::f64))
13553 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13554 DAG.getIntPtrConstant(0));
13555 if (DestVT.bitsGT(MVT::f64))
13556 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13558 // Handle final rounding.
13562 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13563 const X86Subtarget &Subtarget) {
13564 // The algorithm is the following:
13565 // #ifdef __SSE4_1__
13566 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13567 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13568 // (uint4) 0x53000000, 0xaa);
13570 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13571 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13573 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13574 // return (float4) lo + fhi;
13577 SDValue V = Op->getOperand(0);
13578 EVT VecIntVT = V.getValueType();
13579 bool Is128 = VecIntVT == MVT::v4i32;
13580 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13581 unsigned NumElts = VecIntVT.getVectorNumElements();
13582 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13583 "Unsupported custom type");
13584 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13586 // In the #idef/#else code, we have in common:
13587 // - The vector of constants:
13593 // Create the splat vector for 0x4b000000.
13594 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13595 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13596 CstLow, CstLow, CstLow, CstLow};
13597 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13598 makeArrayRef(&CstLowArray[0], NumElts));
13599 // Create the splat vector for 0x53000000.
13600 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13601 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13602 CstHigh, CstHigh, CstHigh, CstHigh};
13603 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13604 makeArrayRef(&CstHighArray[0], NumElts));
13606 // Create the right shift.
13607 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13608 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13609 CstShift, CstShift, CstShift, CstShift};
13610 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13611 makeArrayRef(&CstShiftArray[0], NumElts));
13612 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13615 if (Subtarget.hasSSE41()) {
13616 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13617 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13618 SDValue VecCstLowBitcast =
13619 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13620 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13621 // Low will be bitcasted right away, so do not bother bitcasting back to its
13623 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13624 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13625 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13626 // (uint4) 0x53000000, 0xaa);
13627 SDValue VecCstHighBitcast =
13628 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13629 SDValue VecShiftBitcast =
13630 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13631 // High will be bitcasted right away, so do not bother bitcasting back to
13632 // its original type.
13633 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13634 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13636 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13637 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13638 CstMask, CstMask, CstMask);
13639 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13640 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13641 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13643 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13644 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13647 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13648 SDValue CstFAdd = DAG.getConstantFP(
13649 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13650 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13651 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13652 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13653 makeArrayRef(&CstFAddArray[0], NumElts));
13655 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13656 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13658 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13659 // return (float4) lo + fhi;
13660 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13661 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13664 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13665 SelectionDAG &DAG) const {
13666 SDValue N0 = Op.getOperand(0);
13667 MVT SVT = N0.getSimpleValueType();
13670 switch (SVT.SimpleTy) {
13672 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13677 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13678 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13679 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13683 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13685 llvm_unreachable(nullptr);
13688 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13689 SelectionDAG &DAG) const {
13690 SDValue N0 = Op.getOperand(0);
13693 if (Op.getValueType().isVector())
13694 return lowerUINT_TO_FP_vec(Op, DAG);
13696 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13697 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13698 // the optimization here.
13699 if (DAG.SignBitIsZero(N0))
13700 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13702 MVT SrcVT = N0.getSimpleValueType();
13703 MVT DstVT = Op.getSimpleValueType();
13704 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13705 return LowerUINT_TO_FP_i64(Op, DAG);
13706 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13707 return LowerUINT_TO_FP_i32(Op, DAG);
13708 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13711 // Make a 64-bit buffer, and use it to build an FILD.
13712 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13713 if (SrcVT == MVT::i32) {
13714 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13715 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13716 getPointerTy(), StackSlot, WordOff);
13717 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13718 StackSlot, MachinePointerInfo(),
13720 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13721 OffsetSlot, MachinePointerInfo(),
13723 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13727 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13728 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13729 StackSlot, MachinePointerInfo(),
13731 // For i64 source, we need to add the appropriate power of 2 if the input
13732 // was negative. This is the same as the optimization in
13733 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13734 // we must be careful to do the computation in x87 extended precision, not
13735 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13736 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13737 MachineMemOperand *MMO =
13738 DAG.getMachineFunction()
13739 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13740 MachineMemOperand::MOLoad, 8, 8);
13742 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13743 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13744 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13747 APInt FF(32, 0x5F800000ULL);
13749 // Check whether the sign bit is set.
13750 SDValue SignSet = DAG.getSetCC(dl,
13751 getSetCCResultType(*DAG.getContext(), MVT::i64),
13752 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13755 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13756 SDValue FudgePtr = DAG.getConstantPool(
13757 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13760 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13761 SDValue Zero = DAG.getIntPtrConstant(0);
13762 SDValue Four = DAG.getIntPtrConstant(4);
13763 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13765 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13767 // Load the value out, extending it from f32 to f80.
13768 // FIXME: Avoid the extend by constructing the right constant pool?
13769 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13770 FudgePtr, MachinePointerInfo::getConstantPool(),
13771 MVT::f32, false, false, false, 4);
13772 // Extend everything to 80 bits to force it to be done on x87.
13773 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13774 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13777 std::pair<SDValue,SDValue>
13778 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13779 bool IsSigned, bool IsReplace) const {
13782 EVT DstTy = Op.getValueType();
13784 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13785 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13789 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13790 DstTy.getSimpleVT() >= MVT::i16 &&
13791 "Unknown FP_TO_INT to lower!");
13793 // These are really Legal.
13794 if (DstTy == MVT::i32 &&
13795 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13796 return std::make_pair(SDValue(), SDValue());
13797 if (Subtarget->is64Bit() &&
13798 DstTy == MVT::i64 &&
13799 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13800 return std::make_pair(SDValue(), SDValue());
13802 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13803 // stack slot, or into the FTOL runtime function.
13804 MachineFunction &MF = DAG.getMachineFunction();
13805 unsigned MemSize = DstTy.getSizeInBits()/8;
13806 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13807 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13810 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13811 Opc = X86ISD::WIN_FTOL;
13813 switch (DstTy.getSimpleVT().SimpleTy) {
13814 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13815 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13816 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13817 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13820 SDValue Chain = DAG.getEntryNode();
13821 SDValue Value = Op.getOperand(0);
13822 EVT TheVT = Op.getOperand(0).getValueType();
13823 // FIXME This causes a redundant load/store if the SSE-class value is already
13824 // in memory, such as if it is on the callstack.
13825 if (isScalarFPTypeInSSEReg(TheVT)) {
13826 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13827 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13828 MachinePointerInfo::getFixedStack(SSFI),
13830 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13832 Chain, StackSlot, DAG.getValueType(TheVT)
13835 MachineMemOperand *MMO =
13836 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13837 MachineMemOperand::MOLoad, MemSize, MemSize);
13838 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13839 Chain = Value.getValue(1);
13840 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13841 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13844 MachineMemOperand *MMO =
13845 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13846 MachineMemOperand::MOStore, MemSize, MemSize);
13848 if (Opc != X86ISD::WIN_FTOL) {
13849 // Build the FP_TO_INT*_IN_MEM
13850 SDValue Ops[] = { Chain, Value, StackSlot };
13851 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13853 return std::make_pair(FIST, StackSlot);
13855 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13856 DAG.getVTList(MVT::Other, MVT::Glue),
13858 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13859 MVT::i32, ftol.getValue(1));
13860 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13861 MVT::i32, eax.getValue(2));
13862 SDValue Ops[] = { eax, edx };
13863 SDValue pair = IsReplace
13864 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13865 : DAG.getMergeValues(Ops, DL);
13866 return std::make_pair(pair, SDValue());
13870 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13871 const X86Subtarget *Subtarget) {
13872 MVT VT = Op->getSimpleValueType(0);
13873 SDValue In = Op->getOperand(0);
13874 MVT InVT = In.getSimpleValueType();
13877 // Optimize vectors in AVX mode:
13880 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13881 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13882 // Concat upper and lower parts.
13885 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13886 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13887 // Concat upper and lower parts.
13890 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13891 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13892 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13895 if (Subtarget->hasInt256())
13896 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13898 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13899 SDValue Undef = DAG.getUNDEF(InVT);
13900 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13901 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13902 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13904 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13905 VT.getVectorNumElements()/2);
13907 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13908 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13910 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13913 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13914 SelectionDAG &DAG) {
13915 MVT VT = Op->getSimpleValueType(0);
13916 SDValue In = Op->getOperand(0);
13917 MVT InVT = In.getSimpleValueType();
13919 unsigned int NumElts = VT.getVectorNumElements();
13920 if (NumElts != 8 && NumElts != 16)
13923 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13924 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13926 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13927 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13928 // Now we have only mask extension
13929 assert(InVT.getVectorElementType() == MVT::i1);
13930 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13931 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13932 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13933 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13934 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13935 MachinePointerInfo::getConstantPool(),
13936 false, false, false, Alignment);
13938 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13939 if (VT.is512BitVector())
13941 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13944 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13945 SelectionDAG &DAG) {
13946 if (Subtarget->hasFp256()) {
13947 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13955 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13956 SelectionDAG &DAG) {
13958 MVT VT = Op.getSimpleValueType();
13959 SDValue In = Op.getOperand(0);
13960 MVT SVT = In.getSimpleValueType();
13962 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13963 return LowerZERO_EXTEND_AVX512(Op, DAG);
13965 if (Subtarget->hasFp256()) {
13966 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13971 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13972 VT.getVectorNumElements() != SVT.getVectorNumElements());
13976 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13978 MVT VT = Op.getSimpleValueType();
13979 SDValue In = Op.getOperand(0);
13980 MVT InVT = In.getSimpleValueType();
13982 if (VT == MVT::i1) {
13983 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13984 "Invalid scalar TRUNCATE operation");
13985 if (InVT.getSizeInBits() >= 32)
13987 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13988 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13990 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13991 "Invalid TRUNCATE operation");
13993 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13994 if (VT.getVectorElementType().getSizeInBits() >=8)
13995 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13997 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13998 unsigned NumElts = InVT.getVectorNumElements();
13999 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14000 if (InVT.getSizeInBits() < 512) {
14001 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14002 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14006 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14007 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14008 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14009 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14010 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14011 MachinePointerInfo::getConstantPool(),
14012 false, false, false, Alignment);
14013 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14014 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14015 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14018 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14019 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14020 if (Subtarget->hasInt256()) {
14021 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14022 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14023 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14025 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14026 DAG.getIntPtrConstant(0));
14029 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14030 DAG.getIntPtrConstant(0));
14031 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14032 DAG.getIntPtrConstant(2));
14033 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14034 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14035 static const int ShufMask[] = {0, 2, 4, 6};
14036 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14039 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14040 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14041 if (Subtarget->hasInt256()) {
14042 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14044 SmallVector<SDValue,32> pshufbMask;
14045 for (unsigned i = 0; i < 2; ++i) {
14046 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14047 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14048 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14049 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14050 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14051 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14052 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14053 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14054 for (unsigned j = 0; j < 8; ++j)
14055 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14057 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14058 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14059 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14061 static const int ShufMask[] = {0, 2, -1, -1};
14062 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14064 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14065 DAG.getIntPtrConstant(0));
14066 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14069 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14070 DAG.getIntPtrConstant(0));
14072 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14073 DAG.getIntPtrConstant(4));
14075 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14076 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14078 // The PSHUFB mask:
14079 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14080 -1, -1, -1, -1, -1, -1, -1, -1};
14082 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14083 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14084 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14086 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14087 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14089 // The MOVLHPS Mask:
14090 static const int ShufMask2[] = {0, 1, 4, 5};
14091 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14092 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14095 // Handle truncation of V256 to V128 using shuffles.
14096 if (!VT.is128BitVector() || !InVT.is256BitVector())
14099 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14101 unsigned NumElems = VT.getVectorNumElements();
14102 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14104 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14105 // Prepare truncation shuffle mask
14106 for (unsigned i = 0; i != NumElems; ++i)
14107 MaskVec[i] = i * 2;
14108 SDValue V = DAG.getVectorShuffle(NVT, DL,
14109 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14110 DAG.getUNDEF(NVT), &MaskVec[0]);
14111 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14112 DAG.getIntPtrConstant(0));
14115 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14116 SelectionDAG &DAG) const {
14117 assert(!Op.getSimpleValueType().isVector());
14119 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14120 /*IsSigned=*/ true, /*IsReplace=*/ false);
14121 SDValue FIST = Vals.first, StackSlot = Vals.second;
14122 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14123 if (!FIST.getNode()) return Op;
14125 if (StackSlot.getNode())
14126 // Load the result.
14127 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14128 FIST, StackSlot, MachinePointerInfo(),
14129 false, false, false, 0);
14131 // The node is the result.
14135 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14136 SelectionDAG &DAG) const {
14137 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14138 /*IsSigned=*/ false, /*IsReplace=*/ false);
14139 SDValue FIST = Vals.first, StackSlot = Vals.second;
14140 assert(FIST.getNode() && "Unexpected failure");
14142 if (StackSlot.getNode())
14143 // Load the result.
14144 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14145 FIST, StackSlot, MachinePointerInfo(),
14146 false, false, false, 0);
14148 // The node is the result.
14152 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14154 MVT VT = Op.getSimpleValueType();
14155 SDValue In = Op.getOperand(0);
14156 MVT SVT = In.getSimpleValueType();
14158 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14160 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14161 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14162 In, DAG.getUNDEF(SVT)));
14165 /// The only differences between FABS and FNEG are the mask and the logic op.
14166 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14167 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14168 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14169 "Wrong opcode for lowering FABS or FNEG.");
14171 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14173 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14174 // into an FNABS. We'll lower the FABS after that if it is still in use.
14176 for (SDNode *User : Op->uses())
14177 if (User->getOpcode() == ISD::FNEG)
14180 SDValue Op0 = Op.getOperand(0);
14181 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14184 MVT VT = Op.getSimpleValueType();
14185 // Assume scalar op for initialization; update for vector if needed.
14186 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14187 // generate a 16-byte vector constant and logic op even for the scalar case.
14188 // Using a 16-byte mask allows folding the load of the mask with
14189 // the logic op, so it can save (~4 bytes) on code size.
14191 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14192 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14193 // decide if we should generate a 16-byte constant mask when we only need 4 or
14194 // 8 bytes for the scalar case.
14195 if (VT.isVector()) {
14196 EltVT = VT.getVectorElementType();
14197 NumElts = VT.getVectorNumElements();
14200 unsigned EltBits = EltVT.getSizeInBits();
14201 LLVMContext *Context = DAG.getContext();
14202 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14204 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14205 Constant *C = ConstantInt::get(*Context, MaskElt);
14206 C = ConstantVector::getSplat(NumElts, C);
14207 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14208 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14209 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14210 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14211 MachinePointerInfo::getConstantPool(),
14212 false, false, false, Alignment);
14214 if (VT.isVector()) {
14215 // For a vector, cast operands to a vector type, perform the logic op,
14216 // and cast the result back to the original value type.
14217 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14218 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14219 SDValue Operand = IsFNABS ?
14220 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14221 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14222 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14223 return DAG.getNode(ISD::BITCAST, dl, VT,
14224 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14227 // If not vector, then scalar.
14228 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14229 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14230 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14233 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14234 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14235 LLVMContext *Context = DAG.getContext();
14236 SDValue Op0 = Op.getOperand(0);
14237 SDValue Op1 = Op.getOperand(1);
14239 MVT VT = Op.getSimpleValueType();
14240 MVT SrcVT = Op1.getSimpleValueType();
14242 // If second operand is smaller, extend it first.
14243 if (SrcVT.bitsLT(VT)) {
14244 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14247 // And if it is bigger, shrink it first.
14248 if (SrcVT.bitsGT(VT)) {
14249 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14253 // At this point the operands and the result should have the same
14254 // type, and that won't be f80 since that is not custom lowered.
14256 // First get the sign bit of second operand.
14257 SmallVector<Constant*,4> CV;
14258 if (SrcVT == MVT::f64) {
14259 const fltSemantics &Sem = APFloat::IEEEdouble;
14260 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14261 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14263 const fltSemantics &Sem = APFloat::IEEEsingle;
14264 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14265 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14266 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14267 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14269 Constant *C = ConstantVector::get(CV);
14270 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14271 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14272 MachinePointerInfo::getConstantPool(),
14273 false, false, false, 16);
14274 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14276 // Shift sign bit right or left if the two operands have different types.
14277 if (SrcVT.bitsGT(VT)) {
14278 // Op0 is MVT::f32, Op1 is MVT::f64.
14279 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14280 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14281 DAG.getConstant(32, MVT::i32));
14282 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14283 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14284 DAG.getIntPtrConstant(0));
14287 // Clear first operand sign bit.
14289 if (VT == MVT::f64) {
14290 const fltSemantics &Sem = APFloat::IEEEdouble;
14291 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14292 APInt(64, ~(1ULL << 63)))));
14293 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14295 const fltSemantics &Sem = APFloat::IEEEsingle;
14296 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14297 APInt(32, ~(1U << 31)))));
14298 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14299 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14300 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14302 C = ConstantVector::get(CV);
14303 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14304 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14305 MachinePointerInfo::getConstantPool(),
14306 false, false, false, 16);
14307 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14309 // Or the value with the sign bit.
14310 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14313 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14314 SDValue N0 = Op.getOperand(0);
14316 MVT VT = Op.getSimpleValueType();
14318 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14319 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14320 DAG.getConstant(1, VT));
14321 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14324 // Check whether an OR'd tree is PTEST-able.
14325 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14326 SelectionDAG &DAG) {
14327 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14329 if (!Subtarget->hasSSE41())
14332 if (!Op->hasOneUse())
14335 SDNode *N = Op.getNode();
14338 SmallVector<SDValue, 8> Opnds;
14339 DenseMap<SDValue, unsigned> VecInMap;
14340 SmallVector<SDValue, 8> VecIns;
14341 EVT VT = MVT::Other;
14343 // Recognize a special case where a vector is casted into wide integer to
14345 Opnds.push_back(N->getOperand(0));
14346 Opnds.push_back(N->getOperand(1));
14348 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14349 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14350 // BFS traverse all OR'd operands.
14351 if (I->getOpcode() == ISD::OR) {
14352 Opnds.push_back(I->getOperand(0));
14353 Opnds.push_back(I->getOperand(1));
14354 // Re-evaluate the number of nodes to be traversed.
14355 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14359 // Quit if a non-EXTRACT_VECTOR_ELT
14360 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14363 // Quit if without a constant index.
14364 SDValue Idx = I->getOperand(1);
14365 if (!isa<ConstantSDNode>(Idx))
14368 SDValue ExtractedFromVec = I->getOperand(0);
14369 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14370 if (M == VecInMap.end()) {
14371 VT = ExtractedFromVec.getValueType();
14372 // Quit if not 128/256-bit vector.
14373 if (!VT.is128BitVector() && !VT.is256BitVector())
14375 // Quit if not the same type.
14376 if (VecInMap.begin() != VecInMap.end() &&
14377 VT != VecInMap.begin()->first.getValueType())
14379 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14380 VecIns.push_back(ExtractedFromVec);
14382 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14385 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14386 "Not extracted from 128-/256-bit vector.");
14388 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14390 for (DenseMap<SDValue, unsigned>::const_iterator
14391 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14392 // Quit if not all elements are used.
14393 if (I->second != FullMask)
14397 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14399 // Cast all vectors into TestVT for PTEST.
14400 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14401 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14403 // If more than one full vectors are evaluated, OR them first before PTEST.
14404 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14405 // Each iteration will OR 2 nodes and append the result until there is only
14406 // 1 node left, i.e. the final OR'd value of all vectors.
14407 SDValue LHS = VecIns[Slot];
14408 SDValue RHS = VecIns[Slot + 1];
14409 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14412 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14413 VecIns.back(), VecIns.back());
14416 /// \brief return true if \c Op has a use that doesn't just read flags.
14417 static bool hasNonFlagsUse(SDValue Op) {
14418 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14420 SDNode *User = *UI;
14421 unsigned UOpNo = UI.getOperandNo();
14422 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14423 // Look pass truncate.
14424 UOpNo = User->use_begin().getOperandNo();
14425 User = *User->use_begin();
14428 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14429 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14435 /// Emit nodes that will be selected as "test Op0,Op0", or something
14437 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14438 SelectionDAG &DAG) const {
14439 if (Op.getValueType() == MVT::i1)
14440 // KORTEST instruction should be selected
14441 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14442 DAG.getConstant(0, Op.getValueType()));
14444 // CF and OF aren't always set the way we want. Determine which
14445 // of these we need.
14446 bool NeedCF = false;
14447 bool NeedOF = false;
14450 case X86::COND_A: case X86::COND_AE:
14451 case X86::COND_B: case X86::COND_BE:
14454 case X86::COND_G: case X86::COND_GE:
14455 case X86::COND_L: case X86::COND_LE:
14456 case X86::COND_O: case X86::COND_NO: {
14457 // Check if we really need to set the
14458 // Overflow flag. If NoSignedWrap is present
14459 // that is not actually needed.
14460 switch (Op->getOpcode()) {
14465 const BinaryWithFlagsSDNode *BinNode =
14466 cast<BinaryWithFlagsSDNode>(Op.getNode());
14467 if (BinNode->hasNoSignedWrap())
14477 // See if we can use the EFLAGS value from the operand instead of
14478 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14479 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14480 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14481 // Emit a CMP with 0, which is the TEST pattern.
14482 //if (Op.getValueType() == MVT::i1)
14483 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14484 // DAG.getConstant(0, MVT::i1));
14485 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14486 DAG.getConstant(0, Op.getValueType()));
14488 unsigned Opcode = 0;
14489 unsigned NumOperands = 0;
14491 // Truncate operations may prevent the merge of the SETCC instruction
14492 // and the arithmetic instruction before it. Attempt to truncate the operands
14493 // of the arithmetic instruction and use a reduced bit-width instruction.
14494 bool NeedTruncation = false;
14495 SDValue ArithOp = Op;
14496 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14497 SDValue Arith = Op->getOperand(0);
14498 // Both the trunc and the arithmetic op need to have one user each.
14499 if (Arith->hasOneUse())
14500 switch (Arith.getOpcode()) {
14507 NeedTruncation = true;
14513 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14514 // which may be the result of a CAST. We use the variable 'Op', which is the
14515 // non-casted variable when we check for possible users.
14516 switch (ArithOp.getOpcode()) {
14518 // Due to an isel shortcoming, be conservative if this add is likely to be
14519 // selected as part of a load-modify-store instruction. When the root node
14520 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14521 // uses of other nodes in the match, such as the ADD in this case. This
14522 // leads to the ADD being left around and reselected, with the result being
14523 // two adds in the output. Alas, even if none our users are stores, that
14524 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14525 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14526 // climbing the DAG back to the root, and it doesn't seem to be worth the
14528 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14529 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14530 if (UI->getOpcode() != ISD::CopyToReg &&
14531 UI->getOpcode() != ISD::SETCC &&
14532 UI->getOpcode() != ISD::STORE)
14535 if (ConstantSDNode *C =
14536 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14537 // An add of one will be selected as an INC.
14538 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14539 Opcode = X86ISD::INC;
14544 // An add of negative one (subtract of one) will be selected as a DEC.
14545 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14546 Opcode = X86ISD::DEC;
14552 // Otherwise use a regular EFLAGS-setting add.
14553 Opcode = X86ISD::ADD;
14558 // If we have a constant logical shift that's only used in a comparison
14559 // against zero turn it into an equivalent AND. This allows turning it into
14560 // a TEST instruction later.
14561 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14562 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14563 EVT VT = Op.getValueType();
14564 unsigned BitWidth = VT.getSizeInBits();
14565 unsigned ShAmt = Op->getConstantOperandVal(1);
14566 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14568 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14569 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14570 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14571 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14573 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14574 DAG.getConstant(Mask, VT));
14575 DAG.ReplaceAllUsesWith(Op, New);
14581 // If the primary and result isn't used, don't bother using X86ISD::AND,
14582 // because a TEST instruction will be better.
14583 if (!hasNonFlagsUse(Op))
14589 // Due to the ISEL shortcoming noted above, be conservative if this op is
14590 // likely to be selected as part of a load-modify-store instruction.
14591 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14592 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14593 if (UI->getOpcode() == ISD::STORE)
14596 // Otherwise use a regular EFLAGS-setting instruction.
14597 switch (ArithOp.getOpcode()) {
14598 default: llvm_unreachable("unexpected operator!");
14599 case ISD::SUB: Opcode = X86ISD::SUB; break;
14600 case ISD::XOR: Opcode = X86ISD::XOR; break;
14601 case ISD::AND: Opcode = X86ISD::AND; break;
14603 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14604 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14605 if (EFLAGS.getNode())
14608 Opcode = X86ISD::OR;
14622 return SDValue(Op.getNode(), 1);
14628 // If we found that truncation is beneficial, perform the truncation and
14630 if (NeedTruncation) {
14631 EVT VT = Op.getValueType();
14632 SDValue WideVal = Op->getOperand(0);
14633 EVT WideVT = WideVal.getValueType();
14634 unsigned ConvertedOp = 0;
14635 // Use a target machine opcode to prevent further DAGCombine
14636 // optimizations that may separate the arithmetic operations
14637 // from the setcc node.
14638 switch (WideVal.getOpcode()) {
14640 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14641 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14642 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14643 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14644 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14648 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14649 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14650 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14651 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14652 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14658 // Emit a CMP with 0, which is the TEST pattern.
14659 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14660 DAG.getConstant(0, Op.getValueType()));
14662 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14663 SmallVector<SDValue, 4> Ops;
14664 for (unsigned i = 0; i != NumOperands; ++i)
14665 Ops.push_back(Op.getOperand(i));
14667 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14668 DAG.ReplaceAllUsesWith(Op, New);
14669 return SDValue(New.getNode(), 1);
14672 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14674 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14675 SDLoc dl, SelectionDAG &DAG) const {
14676 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14677 if (C->getAPIntValue() == 0)
14678 return EmitTest(Op0, X86CC, dl, DAG);
14680 if (Op0.getValueType() == MVT::i1)
14681 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14684 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14685 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14686 // Do the comparison at i32 if it's smaller, besides the Atom case.
14687 // This avoids subregister aliasing issues. Keep the smaller reference
14688 // if we're optimizing for size, however, as that'll allow better folding
14689 // of memory operations.
14690 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14691 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14692 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14693 !Subtarget->isAtom()) {
14694 unsigned ExtendOp =
14695 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14696 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14697 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14699 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14700 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14701 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14703 return SDValue(Sub.getNode(), 1);
14705 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14708 /// Convert a comparison if required by the subtarget.
14709 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14710 SelectionDAG &DAG) const {
14711 // If the subtarget does not support the FUCOMI instruction, floating-point
14712 // comparisons have to be converted.
14713 if (Subtarget->hasCMov() ||
14714 Cmp.getOpcode() != X86ISD::CMP ||
14715 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14716 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14719 // The instruction selector will select an FUCOM instruction instead of
14720 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14721 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14722 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14724 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14725 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14726 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14727 DAG.getConstant(8, MVT::i8));
14728 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14729 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14732 /// The minimum architected relative accuracy is 2^-12. We need one
14733 /// Newton-Raphson step to have a good float result (24 bits of precision).
14734 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14735 DAGCombinerInfo &DCI,
14736 unsigned &RefinementSteps,
14737 bool &UseOneConstNR) const {
14738 // FIXME: We should use instruction latency models to calculate the cost of
14739 // each potential sequence, but this is very hard to do reliably because
14740 // at least Intel's Core* chips have variable timing based on the number of
14741 // significant digits in the divisor and/or sqrt operand.
14742 if (!Subtarget->useSqrtEst())
14745 EVT VT = Op.getValueType();
14747 // SSE1 has rsqrtss and rsqrtps.
14748 // TODO: Add support for AVX512 (v16f32).
14749 // It is likely not profitable to do this for f64 because a double-precision
14750 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14751 // instructions: convert to single, rsqrtss, convert back to double, refine
14752 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14753 // along with FMA, this could be a throughput win.
14754 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14755 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14756 RefinementSteps = 1;
14757 UseOneConstNR = false;
14758 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14763 /// The minimum architected relative accuracy is 2^-12. We need one
14764 /// Newton-Raphson step to have a good float result (24 bits of precision).
14765 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14766 DAGCombinerInfo &DCI,
14767 unsigned &RefinementSteps) const {
14768 // FIXME: We should use instruction latency models to calculate the cost of
14769 // each potential sequence, but this is very hard to do reliably because
14770 // at least Intel's Core* chips have variable timing based on the number of
14771 // significant digits in the divisor.
14772 if (!Subtarget->useReciprocalEst())
14775 EVT VT = Op.getValueType();
14777 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14778 // TODO: Add support for AVX512 (v16f32).
14779 // It is likely not profitable to do this for f64 because a double-precision
14780 // reciprocal estimate with refinement on x86 prior to FMA requires
14781 // 15 instructions: convert to single, rcpss, convert back to double, refine
14782 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14783 // along with FMA, this could be a throughput win.
14784 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14785 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14786 RefinementSteps = ReciprocalEstimateRefinementSteps;
14787 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14792 static bool isAllOnes(SDValue V) {
14793 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14794 return C && C->isAllOnesValue();
14797 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14798 /// if it's possible.
14799 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14800 SDLoc dl, SelectionDAG &DAG) const {
14801 SDValue Op0 = And.getOperand(0);
14802 SDValue Op1 = And.getOperand(1);
14803 if (Op0.getOpcode() == ISD::TRUNCATE)
14804 Op0 = Op0.getOperand(0);
14805 if (Op1.getOpcode() == ISD::TRUNCATE)
14806 Op1 = Op1.getOperand(0);
14809 if (Op1.getOpcode() == ISD::SHL)
14810 std::swap(Op0, Op1);
14811 if (Op0.getOpcode() == ISD::SHL) {
14812 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14813 if (And00C->getZExtValue() == 1) {
14814 // If we looked past a truncate, check that it's only truncating away
14816 unsigned BitWidth = Op0.getValueSizeInBits();
14817 unsigned AndBitWidth = And.getValueSizeInBits();
14818 if (BitWidth > AndBitWidth) {
14820 DAG.computeKnownBits(Op0, Zeros, Ones);
14821 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14825 RHS = Op0.getOperand(1);
14827 } else if (Op1.getOpcode() == ISD::Constant) {
14828 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14829 uint64_t AndRHSVal = AndRHS->getZExtValue();
14830 SDValue AndLHS = Op0;
14832 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14833 LHS = AndLHS.getOperand(0);
14834 RHS = AndLHS.getOperand(1);
14837 // Use BT if the immediate can't be encoded in a TEST instruction.
14838 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14840 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14844 if (LHS.getNode()) {
14845 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14846 // instruction. Since the shift amount is in-range-or-undefined, we know
14847 // that doing a bittest on the i32 value is ok. We extend to i32 because
14848 // the encoding for the i16 version is larger than the i32 version.
14849 // Also promote i16 to i32 for performance / code size reason.
14850 if (LHS.getValueType() == MVT::i8 ||
14851 LHS.getValueType() == MVT::i16)
14852 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14854 // If the operand types disagree, extend the shift amount to match. Since
14855 // BT ignores high bits (like shifts) we can use anyextend.
14856 if (LHS.getValueType() != RHS.getValueType())
14857 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14859 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14860 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14861 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14862 DAG.getConstant(Cond, MVT::i8), BT);
14868 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14870 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14875 // SSE Condition code mapping:
14884 switch (SetCCOpcode) {
14885 default: llvm_unreachable("Unexpected SETCC condition");
14887 case ISD::SETEQ: SSECC = 0; break;
14889 case ISD::SETGT: Swap = true; // Fallthrough
14891 case ISD::SETOLT: SSECC = 1; break;
14893 case ISD::SETGE: Swap = true; // Fallthrough
14895 case ISD::SETOLE: SSECC = 2; break;
14896 case ISD::SETUO: SSECC = 3; break;
14898 case ISD::SETNE: SSECC = 4; break;
14899 case ISD::SETULE: Swap = true; // Fallthrough
14900 case ISD::SETUGE: SSECC = 5; break;
14901 case ISD::SETULT: Swap = true; // Fallthrough
14902 case ISD::SETUGT: SSECC = 6; break;
14903 case ISD::SETO: SSECC = 7; break;
14905 case ISD::SETONE: SSECC = 8; break;
14908 std::swap(Op0, Op1);
14913 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14914 // ones, and then concatenate the result back.
14915 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14916 MVT VT = Op.getSimpleValueType();
14918 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14919 "Unsupported value type for operation");
14921 unsigned NumElems = VT.getVectorNumElements();
14923 SDValue CC = Op.getOperand(2);
14925 // Extract the LHS vectors
14926 SDValue LHS = Op.getOperand(0);
14927 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14928 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14930 // Extract the RHS vectors
14931 SDValue RHS = Op.getOperand(1);
14932 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14933 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14935 // Issue the operation on the smaller types and concatenate the result back
14936 MVT EltVT = VT.getVectorElementType();
14937 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14938 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14939 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14940 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14943 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14944 const X86Subtarget *Subtarget) {
14945 SDValue Op0 = Op.getOperand(0);
14946 SDValue Op1 = Op.getOperand(1);
14947 SDValue CC = Op.getOperand(2);
14948 MVT VT = Op.getSimpleValueType();
14951 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14952 Op.getValueType().getScalarType() == MVT::i1 &&
14953 "Cannot set masked compare for this operation");
14955 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14957 bool Unsigned = false;
14960 switch (SetCCOpcode) {
14961 default: llvm_unreachable("Unexpected SETCC condition");
14962 case ISD::SETNE: SSECC = 4; break;
14963 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14964 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14965 case ISD::SETLT: Swap = true; //fall-through
14966 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14967 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14968 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14969 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14970 case ISD::SETULE: Unsigned = true; //fall-through
14971 case ISD::SETLE: SSECC = 2; break;
14975 std::swap(Op0, Op1);
14977 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14978 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14979 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14980 DAG.getConstant(SSECC, MVT::i8));
14983 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14984 /// operand \p Op1. If non-trivial (for example because it's not constant)
14985 /// return an empty value.
14986 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14988 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14992 MVT VT = Op1.getSimpleValueType();
14993 MVT EVT = VT.getVectorElementType();
14994 unsigned n = VT.getVectorNumElements();
14995 SmallVector<SDValue, 8> ULTOp1;
14997 for (unsigned i = 0; i < n; ++i) {
14998 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14999 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15002 // Avoid underflow.
15003 APInt Val = Elt->getAPIntValue();
15007 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15010 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15013 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15014 SelectionDAG &DAG) {
15015 SDValue Op0 = Op.getOperand(0);
15016 SDValue Op1 = Op.getOperand(1);
15017 SDValue CC = Op.getOperand(2);
15018 MVT VT = Op.getSimpleValueType();
15019 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15020 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15025 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15026 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15029 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15030 unsigned Opc = X86ISD::CMPP;
15031 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15032 assert(VT.getVectorNumElements() <= 16);
15033 Opc = X86ISD::CMPM;
15035 // In the two special cases we can't handle, emit two comparisons.
15038 unsigned CombineOpc;
15039 if (SetCCOpcode == ISD::SETUEQ) {
15040 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15042 assert(SetCCOpcode == ISD::SETONE);
15043 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15046 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15047 DAG.getConstant(CC0, MVT::i8));
15048 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15049 DAG.getConstant(CC1, MVT::i8));
15050 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15052 // Handle all other FP comparisons here.
15053 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15054 DAG.getConstant(SSECC, MVT::i8));
15057 // Break 256-bit integer vector compare into smaller ones.
15058 if (VT.is256BitVector() && !Subtarget->hasInt256())
15059 return Lower256IntVSETCC(Op, DAG);
15061 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15062 EVT OpVT = Op1.getValueType();
15063 if (Subtarget->hasAVX512()) {
15064 if (Op1.getValueType().is512BitVector() ||
15065 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15066 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15067 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15069 // In AVX-512 architecture setcc returns mask with i1 elements,
15070 // But there is no compare instruction for i8 and i16 elements in KNL.
15071 // We are not talking about 512-bit operands in this case, these
15072 // types are illegal.
15074 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15075 OpVT.getVectorElementType().getSizeInBits() >= 8))
15076 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15077 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15080 // We are handling one of the integer comparisons here. Since SSE only has
15081 // GT and EQ comparisons for integer, swapping operands and multiple
15082 // operations may be required for some comparisons.
15084 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15085 bool Subus = false;
15087 switch (SetCCOpcode) {
15088 default: llvm_unreachable("Unexpected SETCC condition");
15089 case ISD::SETNE: Invert = true;
15090 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15091 case ISD::SETLT: Swap = true;
15092 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15093 case ISD::SETGE: Swap = true;
15094 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15095 Invert = true; break;
15096 case ISD::SETULT: Swap = true;
15097 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15098 FlipSigns = true; break;
15099 case ISD::SETUGE: Swap = true;
15100 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15101 FlipSigns = true; Invert = true; break;
15104 // Special case: Use min/max operations for SETULE/SETUGE
15105 MVT VET = VT.getVectorElementType();
15107 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15108 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15111 switch (SetCCOpcode) {
15113 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15114 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15117 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15120 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15121 if (!MinMax && hasSubus) {
15122 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15124 // t = psubus Op0, Op1
15125 // pcmpeq t, <0..0>
15126 switch (SetCCOpcode) {
15128 case ISD::SETULT: {
15129 // If the comparison is against a constant we can turn this into a
15130 // setule. With psubus, setule does not require a swap. This is
15131 // beneficial because the constant in the register is no longer
15132 // destructed as the destination so it can be hoisted out of a loop.
15133 // Only do this pre-AVX since vpcmp* is no longer destructive.
15134 if (Subtarget->hasAVX())
15136 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15137 if (ULEOp1.getNode()) {
15139 Subus = true; Invert = false; Swap = false;
15143 // Psubus is better than flip-sign because it requires no inversion.
15144 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15145 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15149 Opc = X86ISD::SUBUS;
15155 std::swap(Op0, Op1);
15157 // Check that the operation in question is available (most are plain SSE2,
15158 // but PCMPGTQ and PCMPEQQ have different requirements).
15159 if (VT == MVT::v2i64) {
15160 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15161 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15163 // First cast everything to the right type.
15164 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15165 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15167 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15168 // bits of the inputs before performing those operations. The lower
15169 // compare is always unsigned.
15172 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15174 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15175 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15176 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15177 Sign, Zero, Sign, Zero);
15179 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15180 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15182 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15183 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15184 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15186 // Create masks for only the low parts/high parts of the 64 bit integers.
15187 static const int MaskHi[] = { 1, 1, 3, 3 };
15188 static const int MaskLo[] = { 0, 0, 2, 2 };
15189 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15190 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15191 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15193 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15194 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15197 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15199 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15202 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15203 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15204 // pcmpeqd + pshufd + pand.
15205 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15207 // First cast everything to the right type.
15208 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15209 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15212 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15214 // Make sure the lower and upper halves are both all-ones.
15215 static const int Mask[] = { 1, 0, 3, 2 };
15216 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15217 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15220 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15222 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15226 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15227 // bits of the inputs before performing those operations.
15229 EVT EltVT = VT.getVectorElementType();
15230 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15231 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15232 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15235 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15237 // If the logical-not of the result is required, perform that now.
15239 Result = DAG.getNOT(dl, Result, VT);
15242 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15245 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15246 getZeroVector(VT, Subtarget, DAG, dl));
15251 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15253 MVT VT = Op.getSimpleValueType();
15255 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15257 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15258 && "SetCC type must be 8-bit or 1-bit integer");
15259 SDValue Op0 = Op.getOperand(0);
15260 SDValue Op1 = Op.getOperand(1);
15262 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15264 // Optimize to BT if possible.
15265 // Lower (X & (1 << N)) == 0 to BT(X, N).
15266 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15267 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15268 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15269 Op1.getOpcode() == ISD::Constant &&
15270 cast<ConstantSDNode>(Op1)->isNullValue() &&
15271 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15272 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15273 if (NewSetCC.getNode())
15277 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15279 if (Op1.getOpcode() == ISD::Constant &&
15280 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15281 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15282 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15284 // If the input is a setcc, then reuse the input setcc or use a new one with
15285 // the inverted condition.
15286 if (Op0.getOpcode() == X86ISD::SETCC) {
15287 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15288 bool Invert = (CC == ISD::SETNE) ^
15289 cast<ConstantSDNode>(Op1)->isNullValue();
15293 CCode = X86::GetOppositeBranchCondition(CCode);
15294 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15295 DAG.getConstant(CCode, MVT::i8),
15296 Op0.getOperand(1));
15298 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15302 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15303 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15304 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15306 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15307 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15310 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15311 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15312 if (X86CC == X86::COND_INVALID)
15315 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15316 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15317 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15318 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15320 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15324 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15325 static bool isX86LogicalCmp(SDValue Op) {
15326 unsigned Opc = Op.getNode()->getOpcode();
15327 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15328 Opc == X86ISD::SAHF)
15330 if (Op.getResNo() == 1 &&
15331 (Opc == X86ISD::ADD ||
15332 Opc == X86ISD::SUB ||
15333 Opc == X86ISD::ADC ||
15334 Opc == X86ISD::SBB ||
15335 Opc == X86ISD::SMUL ||
15336 Opc == X86ISD::UMUL ||
15337 Opc == X86ISD::INC ||
15338 Opc == X86ISD::DEC ||
15339 Opc == X86ISD::OR ||
15340 Opc == X86ISD::XOR ||
15341 Opc == X86ISD::AND))
15344 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15350 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15351 if (V.getOpcode() != ISD::TRUNCATE)
15354 SDValue VOp0 = V.getOperand(0);
15355 unsigned InBits = VOp0.getValueSizeInBits();
15356 unsigned Bits = V.getValueSizeInBits();
15357 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15360 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15361 bool addTest = true;
15362 SDValue Cond = Op.getOperand(0);
15363 SDValue Op1 = Op.getOperand(1);
15364 SDValue Op2 = Op.getOperand(2);
15366 EVT VT = Op1.getValueType();
15369 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15370 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15371 // sequence later on.
15372 if (Cond.getOpcode() == ISD::SETCC &&
15373 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15374 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15375 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15376 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15377 int SSECC = translateX86FSETCC(
15378 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15381 if (Subtarget->hasAVX512()) {
15382 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15383 DAG.getConstant(SSECC, MVT::i8));
15384 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15386 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15387 DAG.getConstant(SSECC, MVT::i8));
15388 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15389 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15390 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15394 if (Cond.getOpcode() == ISD::SETCC) {
15395 SDValue NewCond = LowerSETCC(Cond, DAG);
15396 if (NewCond.getNode())
15400 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15401 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15402 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15403 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15404 if (Cond.getOpcode() == X86ISD::SETCC &&
15405 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15406 isZero(Cond.getOperand(1).getOperand(1))) {
15407 SDValue Cmp = Cond.getOperand(1);
15409 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15411 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15412 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15413 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15415 SDValue CmpOp0 = Cmp.getOperand(0);
15416 // Apply further optimizations for special cases
15417 // (select (x != 0), -1, 0) -> neg & sbb
15418 // (select (x == 0), 0, -1) -> neg & sbb
15419 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15420 if (YC->isNullValue() &&
15421 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15422 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15423 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15424 DAG.getConstant(0, CmpOp0.getValueType()),
15426 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15427 DAG.getConstant(X86::COND_B, MVT::i8),
15428 SDValue(Neg.getNode(), 1));
15432 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15433 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15434 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15436 SDValue Res = // Res = 0 or -1.
15437 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15438 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15440 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15441 Res = DAG.getNOT(DL, Res, Res.getValueType());
15443 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15444 if (!N2C || !N2C->isNullValue())
15445 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15450 // Look past (and (setcc_carry (cmp ...)), 1).
15451 if (Cond.getOpcode() == ISD::AND &&
15452 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15453 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15454 if (C && C->getAPIntValue() == 1)
15455 Cond = Cond.getOperand(0);
15458 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15459 // setting operand in place of the X86ISD::SETCC.
15460 unsigned CondOpcode = Cond.getOpcode();
15461 if (CondOpcode == X86ISD::SETCC ||
15462 CondOpcode == X86ISD::SETCC_CARRY) {
15463 CC = Cond.getOperand(0);
15465 SDValue Cmp = Cond.getOperand(1);
15466 unsigned Opc = Cmp.getOpcode();
15467 MVT VT = Op.getSimpleValueType();
15469 bool IllegalFPCMov = false;
15470 if (VT.isFloatingPoint() && !VT.isVector() &&
15471 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15472 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15474 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15475 Opc == X86ISD::BT) { // FIXME
15479 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15480 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15481 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15482 Cond.getOperand(0).getValueType() != MVT::i8)) {
15483 SDValue LHS = Cond.getOperand(0);
15484 SDValue RHS = Cond.getOperand(1);
15485 unsigned X86Opcode;
15488 switch (CondOpcode) {
15489 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15490 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15491 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15492 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15493 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15494 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15495 default: llvm_unreachable("unexpected overflowing operator");
15497 if (CondOpcode == ISD::UMULO)
15498 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15501 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15503 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15505 if (CondOpcode == ISD::UMULO)
15506 Cond = X86Op.getValue(2);
15508 Cond = X86Op.getValue(1);
15510 CC = DAG.getConstant(X86Cond, MVT::i8);
15515 // Look pass the truncate if the high bits are known zero.
15516 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15517 Cond = Cond.getOperand(0);
15519 // We know the result of AND is compared against zero. Try to match
15521 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15522 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15523 if (NewSetCC.getNode()) {
15524 CC = NewSetCC.getOperand(0);
15525 Cond = NewSetCC.getOperand(1);
15532 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15533 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15536 // a < b ? -1 : 0 -> RES = ~setcc_carry
15537 // a < b ? 0 : -1 -> RES = setcc_carry
15538 // a >= b ? -1 : 0 -> RES = setcc_carry
15539 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15540 if (Cond.getOpcode() == X86ISD::SUB) {
15541 Cond = ConvertCmpIfNecessary(Cond, DAG);
15542 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15544 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15545 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15546 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15547 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15548 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15549 return DAG.getNOT(DL, Res, Res.getValueType());
15554 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15555 // widen the cmov and push the truncate through. This avoids introducing a new
15556 // branch during isel and doesn't add any extensions.
15557 if (Op.getValueType() == MVT::i8 &&
15558 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15559 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15560 if (T1.getValueType() == T2.getValueType() &&
15561 // Blacklist CopyFromReg to avoid partial register stalls.
15562 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15563 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15564 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15565 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15569 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15570 // condition is true.
15571 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15572 SDValue Ops[] = { Op2, Op1, CC, Cond };
15573 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15576 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15577 SelectionDAG &DAG) {
15578 MVT VT = Op->getSimpleValueType(0);
15579 SDValue In = Op->getOperand(0);
15580 MVT InVT = In.getSimpleValueType();
15581 MVT VTElt = VT.getVectorElementType();
15582 MVT InVTElt = InVT.getVectorElementType();
15586 if ((InVTElt == MVT::i1) &&
15587 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15588 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15590 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15591 VTElt.getSizeInBits() <= 16)) ||
15593 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15594 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15596 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15597 VTElt.getSizeInBits() >= 32))))
15598 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15600 unsigned int NumElts = VT.getVectorNumElements();
15602 if (NumElts != 8 && NumElts != 16)
15605 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15606 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15607 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15608 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15611 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15612 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15614 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15615 Constant *C = ConstantInt::get(*DAG.getContext(),
15616 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15618 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15619 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15620 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15621 MachinePointerInfo::getConstantPool(),
15622 false, false, false, Alignment);
15623 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15624 if (VT.is512BitVector())
15626 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15629 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15630 SelectionDAG &DAG) {
15631 MVT VT = Op->getSimpleValueType(0);
15632 SDValue In = Op->getOperand(0);
15633 MVT InVT = In.getSimpleValueType();
15636 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15637 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15639 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15640 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15641 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15644 if (Subtarget->hasInt256())
15645 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15647 // Optimize vectors in AVX mode
15648 // Sign extend v8i16 to v8i32 and
15651 // Divide input vector into two parts
15652 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15653 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15654 // concat the vectors to original VT
15656 unsigned NumElems = InVT.getVectorNumElements();
15657 SDValue Undef = DAG.getUNDEF(InVT);
15659 SmallVector<int,8> ShufMask1(NumElems, -1);
15660 for (unsigned i = 0; i != NumElems/2; ++i)
15663 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15665 SmallVector<int,8> ShufMask2(NumElems, -1);
15666 for (unsigned i = 0; i != NumElems/2; ++i)
15667 ShufMask2[i] = i + NumElems/2;
15669 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15671 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15672 VT.getVectorNumElements()/2);
15674 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15675 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15677 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15680 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15681 // may emit an illegal shuffle but the expansion is still better than scalar
15682 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15683 // we'll emit a shuffle and a arithmetic shift.
15684 // TODO: It is possible to support ZExt by zeroing the undef values during
15685 // the shuffle phase or after the shuffle.
15686 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15687 SelectionDAG &DAG) {
15688 MVT RegVT = Op.getSimpleValueType();
15689 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15690 assert(RegVT.isInteger() &&
15691 "We only custom lower integer vector sext loads.");
15693 // Nothing useful we can do without SSE2 shuffles.
15694 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15696 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15698 EVT MemVT = Ld->getMemoryVT();
15699 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15700 unsigned RegSz = RegVT.getSizeInBits();
15702 ISD::LoadExtType Ext = Ld->getExtensionType();
15704 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15705 && "Only anyext and sext are currently implemented.");
15706 assert(MemVT != RegVT && "Cannot extend to the same type");
15707 assert(MemVT.isVector() && "Must load a vector from memory");
15709 unsigned NumElems = RegVT.getVectorNumElements();
15710 unsigned MemSz = MemVT.getSizeInBits();
15711 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15713 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15714 // The only way in which we have a legal 256-bit vector result but not the
15715 // integer 256-bit operations needed to directly lower a sextload is if we
15716 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15717 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15718 // correctly legalized. We do this late to allow the canonical form of
15719 // sextload to persist throughout the rest of the DAG combiner -- it wants
15720 // to fold together any extensions it can, and so will fuse a sign_extend
15721 // of an sextload into a sextload targeting a wider value.
15723 if (MemSz == 128) {
15724 // Just switch this to a normal load.
15725 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15726 "it must be a legal 128-bit vector "
15728 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15729 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15730 Ld->isInvariant(), Ld->getAlignment());
15732 assert(MemSz < 128 &&
15733 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15734 // Do an sext load to a 128-bit vector type. We want to use the same
15735 // number of elements, but elements half as wide. This will end up being
15736 // recursively lowered by this routine, but will succeed as we definitely
15737 // have all the necessary features if we're using AVX1.
15739 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15740 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15742 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15743 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15744 Ld->isNonTemporal(), Ld->isInvariant(),
15745 Ld->getAlignment());
15748 // Replace chain users with the new chain.
15749 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15750 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15752 // Finally, do a normal sign-extend to the desired register.
15753 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15756 // All sizes must be a power of two.
15757 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15758 "Non-power-of-two elements are not custom lowered!");
15760 // Attempt to load the original value using scalar loads.
15761 // Find the largest scalar type that divides the total loaded size.
15762 MVT SclrLoadTy = MVT::i8;
15763 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15764 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15765 MVT Tp = (MVT::SimpleValueType)tp;
15766 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15771 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15772 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15774 SclrLoadTy = MVT::f64;
15776 // Calculate the number of scalar loads that we need to perform
15777 // in order to load our vector from memory.
15778 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15780 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15781 "Can only lower sext loads with a single scalar load!");
15783 unsigned loadRegZize = RegSz;
15784 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15787 // Represent our vector as a sequence of elements which are the
15788 // largest scalar that we can load.
15789 EVT LoadUnitVecVT = EVT::getVectorVT(
15790 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15792 // Represent the data using the same element type that is stored in
15793 // memory. In practice, we ''widen'' MemVT.
15795 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15796 loadRegZize / MemVT.getScalarType().getSizeInBits());
15798 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15799 "Invalid vector type");
15801 // We can't shuffle using an illegal type.
15802 assert(TLI.isTypeLegal(WideVecVT) &&
15803 "We only lower types that form legal widened vector types");
15805 SmallVector<SDValue, 8> Chains;
15806 SDValue Ptr = Ld->getBasePtr();
15807 SDValue Increment =
15808 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15809 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15811 for (unsigned i = 0; i < NumLoads; ++i) {
15812 // Perform a single load.
15813 SDValue ScalarLoad =
15814 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15815 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15816 Ld->getAlignment());
15817 Chains.push_back(ScalarLoad.getValue(1));
15818 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15819 // another round of DAGCombining.
15821 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15823 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15824 ScalarLoad, DAG.getIntPtrConstant(i));
15826 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15829 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15831 // Bitcast the loaded value to a vector of the original element type, in
15832 // the size of the target vector type.
15833 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15834 unsigned SizeRatio = RegSz / MemSz;
15836 if (Ext == ISD::SEXTLOAD) {
15837 // If we have SSE4.1, we can directly emit a VSEXT node.
15838 if (Subtarget->hasSSE41()) {
15839 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15840 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15844 // Otherwise we'll shuffle the small elements in the high bits of the
15845 // larger type and perform an arithmetic shift. If the shift is not legal
15846 // it's better to scalarize.
15847 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15848 "We can't implement a sext load without an arithmetic right shift!");
15850 // Redistribute the loaded elements into the different locations.
15851 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15852 for (unsigned i = 0; i != NumElems; ++i)
15853 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15855 SDValue Shuff = DAG.getVectorShuffle(
15856 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15858 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15860 // Build the arithmetic shift.
15861 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15862 MemVT.getVectorElementType().getSizeInBits();
15864 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15866 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15870 // Redistribute the loaded elements into the different locations.
15871 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15872 for (unsigned i = 0; i != NumElems; ++i)
15873 ShuffleVec[i * SizeRatio] = i;
15875 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15876 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15878 // Bitcast to the requested type.
15879 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15880 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15884 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15885 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15886 // from the AND / OR.
15887 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15888 Opc = Op.getOpcode();
15889 if (Opc != ISD::OR && Opc != ISD::AND)
15891 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15892 Op.getOperand(0).hasOneUse() &&
15893 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15894 Op.getOperand(1).hasOneUse());
15897 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15898 // 1 and that the SETCC node has a single use.
15899 static bool isXor1OfSetCC(SDValue Op) {
15900 if (Op.getOpcode() != ISD::XOR)
15902 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15903 if (N1C && N1C->getAPIntValue() == 1) {
15904 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15905 Op.getOperand(0).hasOneUse();
15910 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15911 bool addTest = true;
15912 SDValue Chain = Op.getOperand(0);
15913 SDValue Cond = Op.getOperand(1);
15914 SDValue Dest = Op.getOperand(2);
15917 bool Inverted = false;
15919 if (Cond.getOpcode() == ISD::SETCC) {
15920 // Check for setcc([su]{add,sub,mul}o == 0).
15921 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15922 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15923 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15924 Cond.getOperand(0).getResNo() == 1 &&
15925 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15926 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15927 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15928 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15929 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15930 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15932 Cond = Cond.getOperand(0);
15934 SDValue NewCond = LowerSETCC(Cond, DAG);
15935 if (NewCond.getNode())
15940 // FIXME: LowerXALUO doesn't handle these!!
15941 else if (Cond.getOpcode() == X86ISD::ADD ||
15942 Cond.getOpcode() == X86ISD::SUB ||
15943 Cond.getOpcode() == X86ISD::SMUL ||
15944 Cond.getOpcode() == X86ISD::UMUL)
15945 Cond = LowerXALUO(Cond, DAG);
15948 // Look pass (and (setcc_carry (cmp ...)), 1).
15949 if (Cond.getOpcode() == ISD::AND &&
15950 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15951 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15952 if (C && C->getAPIntValue() == 1)
15953 Cond = Cond.getOperand(0);
15956 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15957 // setting operand in place of the X86ISD::SETCC.
15958 unsigned CondOpcode = Cond.getOpcode();
15959 if (CondOpcode == X86ISD::SETCC ||
15960 CondOpcode == X86ISD::SETCC_CARRY) {
15961 CC = Cond.getOperand(0);
15963 SDValue Cmp = Cond.getOperand(1);
15964 unsigned Opc = Cmp.getOpcode();
15965 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15966 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15970 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15974 // These can only come from an arithmetic instruction with overflow,
15975 // e.g. SADDO, UADDO.
15976 Cond = Cond.getNode()->getOperand(1);
15982 CondOpcode = Cond.getOpcode();
15983 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15984 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15985 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15986 Cond.getOperand(0).getValueType() != MVT::i8)) {
15987 SDValue LHS = Cond.getOperand(0);
15988 SDValue RHS = Cond.getOperand(1);
15989 unsigned X86Opcode;
15992 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15993 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15995 switch (CondOpcode) {
15996 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15998 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16000 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16003 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16004 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16006 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16008 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16011 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16012 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16013 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16014 default: llvm_unreachable("unexpected overflowing operator");
16017 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16018 if (CondOpcode == ISD::UMULO)
16019 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16022 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16024 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16026 if (CondOpcode == ISD::UMULO)
16027 Cond = X86Op.getValue(2);
16029 Cond = X86Op.getValue(1);
16031 CC = DAG.getConstant(X86Cond, MVT::i8);
16035 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16036 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16037 if (CondOpc == ISD::OR) {
16038 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16039 // two branches instead of an explicit OR instruction with a
16041 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16042 isX86LogicalCmp(Cmp)) {
16043 CC = Cond.getOperand(0).getOperand(0);
16044 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16045 Chain, Dest, CC, Cmp);
16046 CC = Cond.getOperand(1).getOperand(0);
16050 } else { // ISD::AND
16051 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16052 // two branches instead of an explicit AND instruction with a
16053 // separate test. However, we only do this if this block doesn't
16054 // have a fall-through edge, because this requires an explicit
16055 // jmp when the condition is false.
16056 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16057 isX86LogicalCmp(Cmp) &&
16058 Op.getNode()->hasOneUse()) {
16059 X86::CondCode CCode =
16060 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16061 CCode = X86::GetOppositeBranchCondition(CCode);
16062 CC = DAG.getConstant(CCode, MVT::i8);
16063 SDNode *User = *Op.getNode()->use_begin();
16064 // Look for an unconditional branch following this conditional branch.
16065 // We need this because we need to reverse the successors in order
16066 // to implement FCMP_OEQ.
16067 if (User->getOpcode() == ISD::BR) {
16068 SDValue FalseBB = User->getOperand(1);
16070 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16071 assert(NewBR == User);
16075 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16076 Chain, Dest, CC, Cmp);
16077 X86::CondCode CCode =
16078 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16079 CCode = X86::GetOppositeBranchCondition(CCode);
16080 CC = DAG.getConstant(CCode, MVT::i8);
16086 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16087 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16088 // It should be transformed during dag combiner except when the condition
16089 // is set by a arithmetics with overflow node.
16090 X86::CondCode CCode =
16091 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16092 CCode = X86::GetOppositeBranchCondition(CCode);
16093 CC = DAG.getConstant(CCode, MVT::i8);
16094 Cond = Cond.getOperand(0).getOperand(1);
16096 } else if (Cond.getOpcode() == ISD::SETCC &&
16097 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16098 // For FCMP_OEQ, we can emit
16099 // two branches instead of an explicit AND instruction with a
16100 // separate test. However, we only do this if this block doesn't
16101 // have a fall-through edge, because this requires an explicit
16102 // jmp when the condition is false.
16103 if (Op.getNode()->hasOneUse()) {
16104 SDNode *User = *Op.getNode()->use_begin();
16105 // Look for an unconditional branch following this conditional branch.
16106 // We need this because we need to reverse the successors in order
16107 // to implement FCMP_OEQ.
16108 if (User->getOpcode() == ISD::BR) {
16109 SDValue FalseBB = User->getOperand(1);
16111 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16112 assert(NewBR == User);
16116 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16117 Cond.getOperand(0), Cond.getOperand(1));
16118 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16119 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16120 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16121 Chain, Dest, CC, Cmp);
16122 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16127 } else if (Cond.getOpcode() == ISD::SETCC &&
16128 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16129 // For FCMP_UNE, we can emit
16130 // two branches instead of an explicit AND instruction with a
16131 // separate test. However, we only do this if this block doesn't
16132 // have a fall-through edge, because this requires an explicit
16133 // jmp when the condition is false.
16134 if (Op.getNode()->hasOneUse()) {
16135 SDNode *User = *Op.getNode()->use_begin();
16136 // Look for an unconditional branch following this conditional branch.
16137 // We need this because we need to reverse the successors in order
16138 // to implement FCMP_UNE.
16139 if (User->getOpcode() == ISD::BR) {
16140 SDValue FalseBB = User->getOperand(1);
16142 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16143 assert(NewBR == User);
16146 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16147 Cond.getOperand(0), Cond.getOperand(1));
16148 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16149 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16150 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16151 Chain, Dest, CC, Cmp);
16152 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16162 // Look pass the truncate if the high bits are known zero.
16163 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16164 Cond = Cond.getOperand(0);
16166 // We know the result of AND is compared against zero. Try to match
16168 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16169 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16170 if (NewSetCC.getNode()) {
16171 CC = NewSetCC.getOperand(0);
16172 Cond = NewSetCC.getOperand(1);
16179 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16180 CC = DAG.getConstant(X86Cond, MVT::i8);
16181 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16183 Cond = ConvertCmpIfNecessary(Cond, DAG);
16184 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16185 Chain, Dest, CC, Cond);
16188 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16189 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16190 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16191 // that the guard pages used by the OS virtual memory manager are allocated in
16192 // correct sequence.
16194 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16195 SelectionDAG &DAG) const {
16196 MachineFunction &MF = DAG.getMachineFunction();
16197 bool SplitStack = MF.shouldSplitStack();
16198 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16203 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16204 SDNode* Node = Op.getNode();
16206 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16207 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16208 " not tell us which reg is the stack pointer!");
16209 EVT VT = Node->getValueType(0);
16210 SDValue Tmp1 = SDValue(Node, 0);
16211 SDValue Tmp2 = SDValue(Node, 1);
16212 SDValue Tmp3 = Node->getOperand(2);
16213 SDValue Chain = Tmp1.getOperand(0);
16215 // Chain the dynamic stack allocation so that it doesn't modify the stack
16216 // pointer when other instructions are using the stack.
16217 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16220 SDValue Size = Tmp2.getOperand(1);
16221 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16222 Chain = SP.getValue(1);
16223 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16224 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16225 unsigned StackAlign = TFI.getStackAlignment();
16226 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16227 if (Align > StackAlign)
16228 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16229 DAG.getConstant(-(uint64_t)Align, VT));
16230 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16232 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16233 DAG.getIntPtrConstant(0, true), SDValue(),
16236 SDValue Ops[2] = { Tmp1, Tmp2 };
16237 return DAG.getMergeValues(Ops, dl);
16241 SDValue Chain = Op.getOperand(0);
16242 SDValue Size = Op.getOperand(1);
16243 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16244 EVT VT = Op.getNode()->getValueType(0);
16246 bool Is64Bit = Subtarget->is64Bit();
16247 EVT SPTy = getPointerTy();
16250 MachineRegisterInfo &MRI = MF.getRegInfo();
16253 // The 64 bit implementation of segmented stacks needs to clobber both r10
16254 // r11. This makes it impossible to use it along with nested parameters.
16255 const Function *F = MF.getFunction();
16257 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16259 if (I->hasNestAttr())
16260 report_fatal_error("Cannot use segmented stacks with functions that "
16261 "have nested arguments.");
16264 const TargetRegisterClass *AddrRegClass =
16265 getRegClassFor(getPointerTy());
16266 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16267 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16268 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16269 DAG.getRegister(Vreg, SPTy));
16270 SDValue Ops1[2] = { Value, Chain };
16271 return DAG.getMergeValues(Ops1, dl);
16274 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16276 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16277 Flag = Chain.getValue(1);
16278 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16280 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16282 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16283 DAG.getSubtarget().getRegisterInfo());
16284 unsigned SPReg = RegInfo->getStackRegister();
16285 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16286 Chain = SP.getValue(1);
16289 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16290 DAG.getConstant(-(uint64_t)Align, VT));
16291 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16294 SDValue Ops1[2] = { SP, Chain };
16295 return DAG.getMergeValues(Ops1, dl);
16299 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16300 MachineFunction &MF = DAG.getMachineFunction();
16301 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16303 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16306 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16307 // vastart just stores the address of the VarArgsFrameIndex slot into the
16308 // memory location argument.
16309 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16311 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16312 MachinePointerInfo(SV), false, false, 0);
16316 // gp_offset (0 - 6 * 8)
16317 // fp_offset (48 - 48 + 8 * 16)
16318 // overflow_arg_area (point to parameters coming in memory).
16320 SmallVector<SDValue, 8> MemOps;
16321 SDValue FIN = Op.getOperand(1);
16323 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16324 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16326 FIN, MachinePointerInfo(SV), false, false, 0);
16327 MemOps.push_back(Store);
16330 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16331 FIN, DAG.getIntPtrConstant(4));
16332 Store = DAG.getStore(Op.getOperand(0), DL,
16333 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16335 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16336 MemOps.push_back(Store);
16338 // Store ptr to overflow_arg_area
16339 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16340 FIN, DAG.getIntPtrConstant(4));
16341 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16343 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16344 MachinePointerInfo(SV, 8),
16346 MemOps.push_back(Store);
16348 // Store ptr to reg_save_area.
16349 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16350 FIN, DAG.getIntPtrConstant(8));
16351 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16353 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16354 MachinePointerInfo(SV, 16), false, false, 0);
16355 MemOps.push_back(Store);
16356 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16359 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16360 assert(Subtarget->is64Bit() &&
16361 "LowerVAARG only handles 64-bit va_arg!");
16362 assert((Subtarget->isTargetLinux() ||
16363 Subtarget->isTargetDarwin()) &&
16364 "Unhandled target in LowerVAARG");
16365 assert(Op.getNode()->getNumOperands() == 4);
16366 SDValue Chain = Op.getOperand(0);
16367 SDValue SrcPtr = Op.getOperand(1);
16368 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16369 unsigned Align = Op.getConstantOperandVal(3);
16372 EVT ArgVT = Op.getNode()->getValueType(0);
16373 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16374 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16377 // Decide which area this value should be read from.
16378 // TODO: Implement the AMD64 ABI in its entirety. This simple
16379 // selection mechanism works only for the basic types.
16380 if (ArgVT == MVT::f80) {
16381 llvm_unreachable("va_arg for f80 not yet implemented");
16382 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16383 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16384 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16385 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16387 llvm_unreachable("Unhandled argument type in LowerVAARG");
16390 if (ArgMode == 2) {
16391 // Sanity Check: Make sure using fp_offset makes sense.
16392 assert(!DAG.getTarget().Options.UseSoftFloat &&
16393 !(DAG.getMachineFunction()
16394 .getFunction()->getAttributes()
16395 .hasAttribute(AttributeSet::FunctionIndex,
16396 Attribute::NoImplicitFloat)) &&
16397 Subtarget->hasSSE1());
16400 // Insert VAARG_64 node into the DAG
16401 // VAARG_64 returns two values: Variable Argument Address, Chain
16402 SmallVector<SDValue, 11> InstOps;
16403 InstOps.push_back(Chain);
16404 InstOps.push_back(SrcPtr);
16405 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16406 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16407 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16408 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16409 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16410 VTs, InstOps, MVT::i64,
16411 MachinePointerInfo(SV),
16413 /*Volatile=*/false,
16415 /*WriteMem=*/true);
16416 Chain = VAARG.getValue(1);
16418 // Load the next argument and return it
16419 return DAG.getLoad(ArgVT, dl,
16422 MachinePointerInfo(),
16423 false, false, false, 0);
16426 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16427 SelectionDAG &DAG) {
16428 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16429 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16430 SDValue Chain = Op.getOperand(0);
16431 SDValue DstPtr = Op.getOperand(1);
16432 SDValue SrcPtr = Op.getOperand(2);
16433 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16434 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16437 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16438 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16440 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16443 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16444 // amount is a constant. Takes immediate version of shift as input.
16445 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16446 SDValue SrcOp, uint64_t ShiftAmt,
16447 SelectionDAG &DAG) {
16448 MVT ElementType = VT.getVectorElementType();
16450 // Fold this packed shift into its first operand if ShiftAmt is 0.
16454 // Check for ShiftAmt >= element width
16455 if (ShiftAmt >= ElementType.getSizeInBits()) {
16456 if (Opc == X86ISD::VSRAI)
16457 ShiftAmt = ElementType.getSizeInBits() - 1;
16459 return DAG.getConstant(0, VT);
16462 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16463 && "Unknown target vector shift-by-constant node");
16465 // Fold this packed vector shift into a build vector if SrcOp is a
16466 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16467 if (VT == SrcOp.getSimpleValueType() &&
16468 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16469 SmallVector<SDValue, 8> Elts;
16470 unsigned NumElts = SrcOp->getNumOperands();
16471 ConstantSDNode *ND;
16474 default: llvm_unreachable(nullptr);
16475 case X86ISD::VSHLI:
16476 for (unsigned i=0; i!=NumElts; ++i) {
16477 SDValue CurrentOp = SrcOp->getOperand(i);
16478 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16479 Elts.push_back(CurrentOp);
16482 ND = cast<ConstantSDNode>(CurrentOp);
16483 const APInt &C = ND->getAPIntValue();
16484 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16487 case X86ISD::VSRLI:
16488 for (unsigned i=0; i!=NumElts; ++i) {
16489 SDValue CurrentOp = SrcOp->getOperand(i);
16490 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16491 Elts.push_back(CurrentOp);
16494 ND = cast<ConstantSDNode>(CurrentOp);
16495 const APInt &C = ND->getAPIntValue();
16496 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16499 case X86ISD::VSRAI:
16500 for (unsigned i=0; i!=NumElts; ++i) {
16501 SDValue CurrentOp = SrcOp->getOperand(i);
16502 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16503 Elts.push_back(CurrentOp);
16506 ND = cast<ConstantSDNode>(CurrentOp);
16507 const APInt &C = ND->getAPIntValue();
16508 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16513 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16516 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16519 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16520 // may or may not be a constant. Takes immediate version of shift as input.
16521 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16522 SDValue SrcOp, SDValue ShAmt,
16523 SelectionDAG &DAG) {
16524 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16526 // Catch shift-by-constant.
16527 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16528 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16529 CShAmt->getZExtValue(), DAG);
16531 // Change opcode to non-immediate version
16533 default: llvm_unreachable("Unknown target vector shift node");
16534 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16535 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16536 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16539 // Need to build a vector containing shift amount
16540 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16543 ShOps[1] = DAG.getConstant(0, MVT::i32);
16544 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16545 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16547 // The return type has to be a 128-bit type with the same element
16548 // type as the input type.
16549 MVT EltVT = VT.getVectorElementType();
16550 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16552 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16553 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16556 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16557 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16558 /// necessary casting for \p Mask when lowering masking intrinsics.
16559 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16560 SDValue PreservedSrc,
16561 const X86Subtarget *Subtarget,
16562 SelectionDAG &DAG) {
16563 EVT VT = Op.getValueType();
16564 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16565 MVT::i1, VT.getVectorNumElements());
16566 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16567 Mask.getValueType().getSizeInBits());
16570 assert(MaskVT.isSimple() && "invalid mask type");
16572 if (isAllOnes(Mask))
16575 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16576 // are extracted by EXTRACT_SUBVECTOR.
16577 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16578 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16579 DAG.getIntPtrConstant(0));
16581 switch (Op.getOpcode()) {
16583 case X86ISD::PCMPEQM:
16584 case X86ISD::PCMPGTM:
16586 case X86ISD::CMPMU:
16587 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16589 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16590 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16591 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16594 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16596 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16597 case Intrinsic::x86_fma_vfmadd_ps:
16598 case Intrinsic::x86_fma_vfmadd_pd:
16599 case Intrinsic::x86_fma_vfmadd_ps_256:
16600 case Intrinsic::x86_fma_vfmadd_pd_256:
16601 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16602 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16603 return X86ISD::FMADD;
16604 case Intrinsic::x86_fma_vfmsub_ps:
16605 case Intrinsic::x86_fma_vfmsub_pd:
16606 case Intrinsic::x86_fma_vfmsub_ps_256:
16607 case Intrinsic::x86_fma_vfmsub_pd_256:
16608 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16609 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16610 return X86ISD::FMSUB;
16611 case Intrinsic::x86_fma_vfnmadd_ps:
16612 case Intrinsic::x86_fma_vfnmadd_pd:
16613 case Intrinsic::x86_fma_vfnmadd_ps_256:
16614 case Intrinsic::x86_fma_vfnmadd_pd_256:
16615 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16616 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16617 return X86ISD::FNMADD;
16618 case Intrinsic::x86_fma_vfnmsub_ps:
16619 case Intrinsic::x86_fma_vfnmsub_pd:
16620 case Intrinsic::x86_fma_vfnmsub_ps_256:
16621 case Intrinsic::x86_fma_vfnmsub_pd_256:
16622 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16623 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16624 return X86ISD::FNMSUB;
16625 case Intrinsic::x86_fma_vfmaddsub_ps:
16626 case Intrinsic::x86_fma_vfmaddsub_pd:
16627 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16628 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16629 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16630 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16631 return X86ISD::FMADDSUB;
16632 case Intrinsic::x86_fma_vfmsubadd_ps:
16633 case Intrinsic::x86_fma_vfmsubadd_pd:
16634 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16635 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16636 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16637 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16638 return X86ISD::FMSUBADD;
16642 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16643 SelectionDAG &DAG) {
16645 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16646 EVT VT = Op.getValueType();
16647 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16649 switch(IntrData->Type) {
16650 case INTR_TYPE_1OP:
16651 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16652 case INTR_TYPE_2OP:
16653 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16655 case INTR_TYPE_3OP:
16656 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16657 Op.getOperand(2), Op.getOperand(3));
16658 case INTR_TYPE_1OP_MASK_RM: {
16659 SDValue Src = Op.getOperand(1);
16660 SDValue Src0 = Op.getOperand(2);
16661 SDValue Mask = Op.getOperand(3);
16662 SDValue RoundingMode = Op.getOperand(4);
16663 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16665 Mask, Src0, Subtarget, DAG);
16669 case CMP_MASK_CC: {
16670 // Comparison intrinsics with masks.
16671 // Example of transformation:
16672 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16673 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16675 // (v8i1 (insert_subvector undef,
16676 // (v2i1 (and (PCMPEQM %a, %b),
16677 // (extract_subvector
16678 // (v8i1 (bitcast %mask)), 0))), 0))))
16679 EVT VT = Op.getOperand(1).getValueType();
16680 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16681 VT.getVectorNumElements());
16682 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16683 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16684 Mask.getValueType().getSizeInBits());
16686 if (IntrData->Type == CMP_MASK_CC) {
16687 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16688 Op.getOperand(2), Op.getOperand(3));
16690 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16691 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16694 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16695 DAG.getTargetConstant(0, MaskVT),
16697 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16698 DAG.getUNDEF(BitcastVT), CmpMask,
16699 DAG.getIntPtrConstant(0));
16700 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16702 case COMI: { // Comparison intrinsics
16703 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16704 SDValue LHS = Op.getOperand(1);
16705 SDValue RHS = Op.getOperand(2);
16706 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16707 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16708 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16709 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16710 DAG.getConstant(X86CC, MVT::i8), Cond);
16711 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16714 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16715 Op.getOperand(1), Op.getOperand(2), DAG);
16717 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16718 Op.getOperand(1), Op.getOperand(2), DAG),
16719 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);;
16726 default: return SDValue(); // Don't custom lower most intrinsics.
16728 // Arithmetic intrinsics.
16729 case Intrinsic::x86_sse2_pmulu_dq:
16730 case Intrinsic::x86_avx2_pmulu_dq:
16731 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16732 Op.getOperand(1), Op.getOperand(2));
16734 case Intrinsic::x86_sse41_pmuldq:
16735 case Intrinsic::x86_avx2_pmul_dq:
16736 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16737 Op.getOperand(1), Op.getOperand(2));
16739 case Intrinsic::x86_sse2_pmulhu_w:
16740 case Intrinsic::x86_avx2_pmulhu_w:
16741 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16742 Op.getOperand(1), Op.getOperand(2));
16744 case Intrinsic::x86_sse2_pmulh_w:
16745 case Intrinsic::x86_avx2_pmulh_w:
16746 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16747 Op.getOperand(1), Op.getOperand(2));
16749 // SSE/SSE2/AVX floating point max/min intrinsics.
16750 case Intrinsic::x86_sse_max_ps:
16751 case Intrinsic::x86_sse2_max_pd:
16752 case Intrinsic::x86_avx_max_ps_256:
16753 case Intrinsic::x86_avx_max_pd_256:
16754 case Intrinsic::x86_sse_min_ps:
16755 case Intrinsic::x86_sse2_min_pd:
16756 case Intrinsic::x86_avx_min_ps_256:
16757 case Intrinsic::x86_avx_min_pd_256: {
16760 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16761 case Intrinsic::x86_sse_max_ps:
16762 case Intrinsic::x86_sse2_max_pd:
16763 case Intrinsic::x86_avx_max_ps_256:
16764 case Intrinsic::x86_avx_max_pd_256:
16765 Opcode = X86ISD::FMAX;
16767 case Intrinsic::x86_sse_min_ps:
16768 case Intrinsic::x86_sse2_min_pd:
16769 case Intrinsic::x86_avx_min_ps_256:
16770 case Intrinsic::x86_avx_min_pd_256:
16771 Opcode = X86ISD::FMIN;
16774 return DAG.getNode(Opcode, dl, Op.getValueType(),
16775 Op.getOperand(1), Op.getOperand(2));
16778 // AVX2 variable shift intrinsics
16779 case Intrinsic::x86_avx2_psllv_d:
16780 case Intrinsic::x86_avx2_psllv_q:
16781 case Intrinsic::x86_avx2_psllv_d_256:
16782 case Intrinsic::x86_avx2_psllv_q_256:
16783 case Intrinsic::x86_avx2_psrlv_d:
16784 case Intrinsic::x86_avx2_psrlv_q:
16785 case Intrinsic::x86_avx2_psrlv_d_256:
16786 case Intrinsic::x86_avx2_psrlv_q_256:
16787 case Intrinsic::x86_avx2_psrav_d:
16788 case Intrinsic::x86_avx2_psrav_d_256: {
16791 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16792 case Intrinsic::x86_avx2_psllv_d:
16793 case Intrinsic::x86_avx2_psllv_q:
16794 case Intrinsic::x86_avx2_psllv_d_256:
16795 case Intrinsic::x86_avx2_psllv_q_256:
16798 case Intrinsic::x86_avx2_psrlv_d:
16799 case Intrinsic::x86_avx2_psrlv_q:
16800 case Intrinsic::x86_avx2_psrlv_d_256:
16801 case Intrinsic::x86_avx2_psrlv_q_256:
16804 case Intrinsic::x86_avx2_psrav_d:
16805 case Intrinsic::x86_avx2_psrav_d_256:
16809 return DAG.getNode(Opcode, dl, Op.getValueType(),
16810 Op.getOperand(1), Op.getOperand(2));
16813 case Intrinsic::x86_sse2_packssdw_128:
16814 case Intrinsic::x86_sse2_packsswb_128:
16815 case Intrinsic::x86_avx2_packssdw:
16816 case Intrinsic::x86_avx2_packsswb:
16817 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16818 Op.getOperand(1), Op.getOperand(2));
16820 case Intrinsic::x86_sse2_packuswb_128:
16821 case Intrinsic::x86_sse41_packusdw:
16822 case Intrinsic::x86_avx2_packuswb:
16823 case Intrinsic::x86_avx2_packusdw:
16824 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16825 Op.getOperand(1), Op.getOperand(2));
16827 case Intrinsic::x86_ssse3_pshuf_b_128:
16828 case Intrinsic::x86_avx2_pshuf_b:
16829 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16830 Op.getOperand(1), Op.getOperand(2));
16832 case Intrinsic::x86_sse2_pshuf_d:
16833 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16834 Op.getOperand(1), Op.getOperand(2));
16836 case Intrinsic::x86_sse2_pshufl_w:
16837 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16838 Op.getOperand(1), Op.getOperand(2));
16840 case Intrinsic::x86_sse2_pshufh_w:
16841 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16842 Op.getOperand(1), Op.getOperand(2));
16844 case Intrinsic::x86_ssse3_psign_b_128:
16845 case Intrinsic::x86_ssse3_psign_w_128:
16846 case Intrinsic::x86_ssse3_psign_d_128:
16847 case Intrinsic::x86_avx2_psign_b:
16848 case Intrinsic::x86_avx2_psign_w:
16849 case Intrinsic::x86_avx2_psign_d:
16850 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16851 Op.getOperand(1), Op.getOperand(2));
16853 case Intrinsic::x86_avx2_permd:
16854 case Intrinsic::x86_avx2_permps:
16855 // Operands intentionally swapped. Mask is last operand to intrinsic,
16856 // but second operand for node/instruction.
16857 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16858 Op.getOperand(2), Op.getOperand(1));
16860 case Intrinsic::x86_avx512_mask_valign_q_512:
16861 case Intrinsic::x86_avx512_mask_valign_d_512:
16862 // Vector source operands are swapped.
16863 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16864 Op.getValueType(), Op.getOperand(2),
16867 Op.getOperand(5), Op.getOperand(4),
16870 // ptest and testp intrinsics. The intrinsic these come from are designed to
16871 // return an integer value, not just an instruction so lower it to the ptest
16872 // or testp pattern and a setcc for the result.
16873 case Intrinsic::x86_sse41_ptestz:
16874 case Intrinsic::x86_sse41_ptestc:
16875 case Intrinsic::x86_sse41_ptestnzc:
16876 case Intrinsic::x86_avx_ptestz_256:
16877 case Intrinsic::x86_avx_ptestc_256:
16878 case Intrinsic::x86_avx_ptestnzc_256:
16879 case Intrinsic::x86_avx_vtestz_ps:
16880 case Intrinsic::x86_avx_vtestc_ps:
16881 case Intrinsic::x86_avx_vtestnzc_ps:
16882 case Intrinsic::x86_avx_vtestz_pd:
16883 case Intrinsic::x86_avx_vtestc_pd:
16884 case Intrinsic::x86_avx_vtestnzc_pd:
16885 case Intrinsic::x86_avx_vtestz_ps_256:
16886 case Intrinsic::x86_avx_vtestc_ps_256:
16887 case Intrinsic::x86_avx_vtestnzc_ps_256:
16888 case Intrinsic::x86_avx_vtestz_pd_256:
16889 case Intrinsic::x86_avx_vtestc_pd_256:
16890 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16891 bool IsTestPacked = false;
16894 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16895 case Intrinsic::x86_avx_vtestz_ps:
16896 case Intrinsic::x86_avx_vtestz_pd:
16897 case Intrinsic::x86_avx_vtestz_ps_256:
16898 case Intrinsic::x86_avx_vtestz_pd_256:
16899 IsTestPacked = true; // Fallthrough
16900 case Intrinsic::x86_sse41_ptestz:
16901 case Intrinsic::x86_avx_ptestz_256:
16903 X86CC = X86::COND_E;
16905 case Intrinsic::x86_avx_vtestc_ps:
16906 case Intrinsic::x86_avx_vtestc_pd:
16907 case Intrinsic::x86_avx_vtestc_ps_256:
16908 case Intrinsic::x86_avx_vtestc_pd_256:
16909 IsTestPacked = true; // Fallthrough
16910 case Intrinsic::x86_sse41_ptestc:
16911 case Intrinsic::x86_avx_ptestc_256:
16913 X86CC = X86::COND_B;
16915 case Intrinsic::x86_avx_vtestnzc_ps:
16916 case Intrinsic::x86_avx_vtestnzc_pd:
16917 case Intrinsic::x86_avx_vtestnzc_ps_256:
16918 case Intrinsic::x86_avx_vtestnzc_pd_256:
16919 IsTestPacked = true; // Fallthrough
16920 case Intrinsic::x86_sse41_ptestnzc:
16921 case Intrinsic::x86_avx_ptestnzc_256:
16923 X86CC = X86::COND_A;
16927 SDValue LHS = Op.getOperand(1);
16928 SDValue RHS = Op.getOperand(2);
16929 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16930 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16931 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16932 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16933 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16935 case Intrinsic::x86_avx512_kortestz_w:
16936 case Intrinsic::x86_avx512_kortestc_w: {
16937 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16938 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16939 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16940 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16941 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16942 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16943 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16946 case Intrinsic::x86_sse42_pcmpistria128:
16947 case Intrinsic::x86_sse42_pcmpestria128:
16948 case Intrinsic::x86_sse42_pcmpistric128:
16949 case Intrinsic::x86_sse42_pcmpestric128:
16950 case Intrinsic::x86_sse42_pcmpistrio128:
16951 case Intrinsic::x86_sse42_pcmpestrio128:
16952 case Intrinsic::x86_sse42_pcmpistris128:
16953 case Intrinsic::x86_sse42_pcmpestris128:
16954 case Intrinsic::x86_sse42_pcmpistriz128:
16955 case Intrinsic::x86_sse42_pcmpestriz128: {
16959 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16960 case Intrinsic::x86_sse42_pcmpistria128:
16961 Opcode = X86ISD::PCMPISTRI;
16962 X86CC = X86::COND_A;
16964 case Intrinsic::x86_sse42_pcmpestria128:
16965 Opcode = X86ISD::PCMPESTRI;
16966 X86CC = X86::COND_A;
16968 case Intrinsic::x86_sse42_pcmpistric128:
16969 Opcode = X86ISD::PCMPISTRI;
16970 X86CC = X86::COND_B;
16972 case Intrinsic::x86_sse42_pcmpestric128:
16973 Opcode = X86ISD::PCMPESTRI;
16974 X86CC = X86::COND_B;
16976 case Intrinsic::x86_sse42_pcmpistrio128:
16977 Opcode = X86ISD::PCMPISTRI;
16978 X86CC = X86::COND_O;
16980 case Intrinsic::x86_sse42_pcmpestrio128:
16981 Opcode = X86ISD::PCMPESTRI;
16982 X86CC = X86::COND_O;
16984 case Intrinsic::x86_sse42_pcmpistris128:
16985 Opcode = X86ISD::PCMPISTRI;
16986 X86CC = X86::COND_S;
16988 case Intrinsic::x86_sse42_pcmpestris128:
16989 Opcode = X86ISD::PCMPESTRI;
16990 X86CC = X86::COND_S;
16992 case Intrinsic::x86_sse42_pcmpistriz128:
16993 Opcode = X86ISD::PCMPISTRI;
16994 X86CC = X86::COND_E;
16996 case Intrinsic::x86_sse42_pcmpestriz128:
16997 Opcode = X86ISD::PCMPESTRI;
16998 X86CC = X86::COND_E;
17001 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17002 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17003 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17004 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17005 DAG.getConstant(X86CC, MVT::i8),
17006 SDValue(PCMP.getNode(), 1));
17007 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17010 case Intrinsic::x86_sse42_pcmpistri128:
17011 case Intrinsic::x86_sse42_pcmpestri128: {
17013 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17014 Opcode = X86ISD::PCMPISTRI;
17016 Opcode = X86ISD::PCMPESTRI;
17018 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17019 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17020 return DAG.getNode(Opcode, dl, VTs, NewOps);
17023 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17024 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17025 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17026 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17027 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17028 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17029 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17030 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17031 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17032 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17033 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17034 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17035 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17036 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17037 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17038 dl, Op.getValueType(),
17042 Op.getOperand(4), Op.getOperand(1),
17048 case Intrinsic::x86_fma_vfmadd_ps:
17049 case Intrinsic::x86_fma_vfmadd_pd:
17050 case Intrinsic::x86_fma_vfmsub_ps:
17051 case Intrinsic::x86_fma_vfmsub_pd:
17052 case Intrinsic::x86_fma_vfnmadd_ps:
17053 case Intrinsic::x86_fma_vfnmadd_pd:
17054 case Intrinsic::x86_fma_vfnmsub_ps:
17055 case Intrinsic::x86_fma_vfnmsub_pd:
17056 case Intrinsic::x86_fma_vfmaddsub_ps:
17057 case Intrinsic::x86_fma_vfmaddsub_pd:
17058 case Intrinsic::x86_fma_vfmsubadd_ps:
17059 case Intrinsic::x86_fma_vfmsubadd_pd:
17060 case Intrinsic::x86_fma_vfmadd_ps_256:
17061 case Intrinsic::x86_fma_vfmadd_pd_256:
17062 case Intrinsic::x86_fma_vfmsub_ps_256:
17063 case Intrinsic::x86_fma_vfmsub_pd_256:
17064 case Intrinsic::x86_fma_vfnmadd_ps_256:
17065 case Intrinsic::x86_fma_vfnmadd_pd_256:
17066 case Intrinsic::x86_fma_vfnmsub_ps_256:
17067 case Intrinsic::x86_fma_vfnmsub_pd_256:
17068 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17069 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17070 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17071 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17072 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17073 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17077 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17078 SDValue Src, SDValue Mask, SDValue Base,
17079 SDValue Index, SDValue ScaleOp, SDValue Chain,
17080 const X86Subtarget * Subtarget) {
17082 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17083 assert(C && "Invalid scale type");
17084 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17085 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17086 Index.getSimpleValueType().getVectorNumElements());
17088 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17090 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17092 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17093 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17094 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17095 SDValue Segment = DAG.getRegister(0, MVT::i32);
17096 if (Src.getOpcode() == ISD::UNDEF)
17097 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17098 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17099 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17100 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17101 return DAG.getMergeValues(RetOps, dl);
17104 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17105 SDValue Src, SDValue Mask, SDValue Base,
17106 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17108 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17109 assert(C && "Invalid scale type");
17110 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17111 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17112 SDValue Segment = DAG.getRegister(0, MVT::i32);
17113 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17114 Index.getSimpleValueType().getVectorNumElements());
17116 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17118 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17120 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17121 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17122 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17123 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17124 return SDValue(Res, 1);
17127 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17128 SDValue Mask, SDValue Base, SDValue Index,
17129 SDValue ScaleOp, SDValue Chain) {
17131 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17132 assert(C && "Invalid scale type");
17133 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17134 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17135 SDValue Segment = DAG.getRegister(0, MVT::i32);
17137 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17139 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17141 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17143 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17144 //SDVTList VTs = DAG.getVTList(MVT::Other);
17145 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17146 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17147 return SDValue(Res, 0);
17150 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17151 // read performance monitor counters (x86_rdpmc).
17152 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17153 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17154 SmallVectorImpl<SDValue> &Results) {
17155 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17156 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17159 // The ECX register is used to select the index of the performance counter
17161 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17163 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17165 // Reads the content of a 64-bit performance counter and returns it in the
17166 // registers EDX:EAX.
17167 if (Subtarget->is64Bit()) {
17168 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17169 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17172 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17173 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17176 Chain = HI.getValue(1);
17178 if (Subtarget->is64Bit()) {
17179 // The EAX register is loaded with the low-order 32 bits. The EDX register
17180 // is loaded with the supported high-order bits of the counter.
17181 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17182 DAG.getConstant(32, MVT::i8));
17183 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17184 Results.push_back(Chain);
17188 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17189 SDValue Ops[] = { LO, HI };
17190 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17191 Results.push_back(Pair);
17192 Results.push_back(Chain);
17195 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17196 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17197 // also used to custom lower READCYCLECOUNTER nodes.
17198 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17199 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17200 SmallVectorImpl<SDValue> &Results) {
17201 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17202 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17205 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17206 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17207 // and the EAX register is loaded with the low-order 32 bits.
17208 if (Subtarget->is64Bit()) {
17209 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17210 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17213 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17214 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17217 SDValue Chain = HI.getValue(1);
17219 if (Opcode == X86ISD::RDTSCP_DAG) {
17220 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17222 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17223 // the ECX register. Add 'ecx' explicitly to the chain.
17224 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17226 // Explicitly store the content of ECX at the location passed in input
17227 // to the 'rdtscp' intrinsic.
17228 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17229 MachinePointerInfo(), false, false, 0);
17232 if (Subtarget->is64Bit()) {
17233 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17234 // the EAX register is loaded with the low-order 32 bits.
17235 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17236 DAG.getConstant(32, MVT::i8));
17237 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17238 Results.push_back(Chain);
17242 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17243 SDValue Ops[] = { LO, HI };
17244 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17245 Results.push_back(Pair);
17246 Results.push_back(Chain);
17249 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17250 SelectionDAG &DAG) {
17251 SmallVector<SDValue, 2> Results;
17253 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17255 return DAG.getMergeValues(Results, DL);
17259 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17260 SelectionDAG &DAG) {
17261 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17263 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17268 switch(IntrData->Type) {
17270 llvm_unreachable("Unknown Intrinsic Type");
17274 // Emit the node with the right value type.
17275 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17276 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17278 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17279 // Otherwise return the value from Rand, which is always 0, casted to i32.
17280 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17281 DAG.getConstant(1, Op->getValueType(1)),
17282 DAG.getConstant(X86::COND_B, MVT::i32),
17283 SDValue(Result.getNode(), 1) };
17284 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17285 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17288 // Return { result, isValid, chain }.
17289 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17290 SDValue(Result.getNode(), 2));
17293 //gather(v1, mask, index, base, scale);
17294 SDValue Chain = Op.getOperand(0);
17295 SDValue Src = Op.getOperand(2);
17296 SDValue Base = Op.getOperand(3);
17297 SDValue Index = Op.getOperand(4);
17298 SDValue Mask = Op.getOperand(5);
17299 SDValue Scale = Op.getOperand(6);
17300 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17304 //scatter(base, mask, index, v1, scale);
17305 SDValue Chain = Op.getOperand(0);
17306 SDValue Base = Op.getOperand(2);
17307 SDValue Mask = Op.getOperand(3);
17308 SDValue Index = Op.getOperand(4);
17309 SDValue Src = Op.getOperand(5);
17310 SDValue Scale = Op.getOperand(6);
17311 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17314 SDValue Hint = Op.getOperand(6);
17316 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17317 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17318 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17319 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17320 SDValue Chain = Op.getOperand(0);
17321 SDValue Mask = Op.getOperand(2);
17322 SDValue Index = Op.getOperand(3);
17323 SDValue Base = Op.getOperand(4);
17324 SDValue Scale = Op.getOperand(5);
17325 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17327 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17329 SmallVector<SDValue, 2> Results;
17330 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17331 return DAG.getMergeValues(Results, dl);
17333 // Read Performance Monitoring Counters.
17335 SmallVector<SDValue, 2> Results;
17336 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17337 return DAG.getMergeValues(Results, dl);
17339 // XTEST intrinsics.
17341 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17342 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17343 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17344 DAG.getConstant(X86::COND_NE, MVT::i8),
17346 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17347 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17348 Ret, SDValue(InTrans.getNode(), 1));
17352 SmallVector<SDValue, 2> Results;
17353 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17354 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17355 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17356 DAG.getConstant(-1, MVT::i8));
17357 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17358 Op.getOperand(4), GenCF.getValue(1));
17359 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17360 Op.getOperand(5), MachinePointerInfo(),
17362 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17363 DAG.getConstant(X86::COND_B, MVT::i8),
17365 Results.push_back(SetCC);
17366 Results.push_back(Store);
17367 return DAG.getMergeValues(Results, dl);
17372 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17373 SelectionDAG &DAG) const {
17374 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17375 MFI->setReturnAddressIsTaken(true);
17377 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17380 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17382 EVT PtrVT = getPointerTy();
17385 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17386 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17387 DAG.getSubtarget().getRegisterInfo());
17388 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17389 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17390 DAG.getNode(ISD::ADD, dl, PtrVT,
17391 FrameAddr, Offset),
17392 MachinePointerInfo(), false, false, false, 0);
17395 // Just load the return address.
17396 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17397 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17398 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17401 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17402 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17403 MFI->setFrameAddressIsTaken(true);
17405 EVT VT = Op.getValueType();
17406 SDLoc dl(Op); // FIXME probably not meaningful
17407 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17408 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17409 DAG.getSubtarget().getRegisterInfo());
17410 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17411 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17412 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17413 "Invalid Frame Register!");
17414 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17416 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17417 MachinePointerInfo(),
17418 false, false, false, 0);
17422 // FIXME? Maybe this could be a TableGen attribute on some registers and
17423 // this table could be generated automatically from RegInfo.
17424 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17426 unsigned Reg = StringSwitch<unsigned>(RegName)
17427 .Case("esp", X86::ESP)
17428 .Case("rsp", X86::RSP)
17432 report_fatal_error("Invalid register name global variable");
17435 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17436 SelectionDAG &DAG) const {
17437 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17438 DAG.getSubtarget().getRegisterInfo());
17439 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17442 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17443 SDValue Chain = Op.getOperand(0);
17444 SDValue Offset = Op.getOperand(1);
17445 SDValue Handler = Op.getOperand(2);
17448 EVT PtrVT = getPointerTy();
17449 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17450 DAG.getSubtarget().getRegisterInfo());
17451 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17452 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17453 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17454 "Invalid Frame Register!");
17455 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17456 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17458 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17459 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17460 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17461 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17463 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17465 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17466 DAG.getRegister(StoreAddrReg, PtrVT));
17469 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17470 SelectionDAG &DAG) const {
17472 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17473 DAG.getVTList(MVT::i32, MVT::Other),
17474 Op.getOperand(0), Op.getOperand(1));
17477 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17478 SelectionDAG &DAG) const {
17480 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17481 Op.getOperand(0), Op.getOperand(1));
17484 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17485 return Op.getOperand(0);
17488 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17489 SelectionDAG &DAG) const {
17490 SDValue Root = Op.getOperand(0);
17491 SDValue Trmp = Op.getOperand(1); // trampoline
17492 SDValue FPtr = Op.getOperand(2); // nested function
17493 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17496 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17497 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17499 if (Subtarget->is64Bit()) {
17500 SDValue OutChains[6];
17502 // Large code-model.
17503 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17504 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17506 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17507 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17509 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17511 // Load the pointer to the nested function into R11.
17512 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17513 SDValue Addr = Trmp;
17514 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17515 Addr, MachinePointerInfo(TrmpAddr),
17518 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17519 DAG.getConstant(2, MVT::i64));
17520 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17521 MachinePointerInfo(TrmpAddr, 2),
17524 // Load the 'nest' parameter value into R10.
17525 // R10 is specified in X86CallingConv.td
17526 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17527 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17528 DAG.getConstant(10, MVT::i64));
17529 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17530 Addr, MachinePointerInfo(TrmpAddr, 10),
17533 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17534 DAG.getConstant(12, MVT::i64));
17535 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17536 MachinePointerInfo(TrmpAddr, 12),
17539 // Jump to the nested function.
17540 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17541 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17542 DAG.getConstant(20, MVT::i64));
17543 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17544 Addr, MachinePointerInfo(TrmpAddr, 20),
17547 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17548 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17549 DAG.getConstant(22, MVT::i64));
17550 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17551 MachinePointerInfo(TrmpAddr, 22),
17554 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17556 const Function *Func =
17557 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17558 CallingConv::ID CC = Func->getCallingConv();
17563 llvm_unreachable("Unsupported calling convention");
17564 case CallingConv::C:
17565 case CallingConv::X86_StdCall: {
17566 // Pass 'nest' parameter in ECX.
17567 // Must be kept in sync with X86CallingConv.td
17568 NestReg = X86::ECX;
17570 // Check that ECX wasn't needed by an 'inreg' parameter.
17571 FunctionType *FTy = Func->getFunctionType();
17572 const AttributeSet &Attrs = Func->getAttributes();
17574 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17575 unsigned InRegCount = 0;
17578 for (FunctionType::param_iterator I = FTy->param_begin(),
17579 E = FTy->param_end(); I != E; ++I, ++Idx)
17580 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17581 // FIXME: should only count parameters that are lowered to integers.
17582 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17584 if (InRegCount > 2) {
17585 report_fatal_error("Nest register in use - reduce number of inreg"
17591 case CallingConv::X86_FastCall:
17592 case CallingConv::X86_ThisCall:
17593 case CallingConv::Fast:
17594 // Pass 'nest' parameter in EAX.
17595 // Must be kept in sync with X86CallingConv.td
17596 NestReg = X86::EAX;
17600 SDValue OutChains[4];
17601 SDValue Addr, Disp;
17603 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17604 DAG.getConstant(10, MVT::i32));
17605 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17607 // This is storing the opcode for MOV32ri.
17608 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17609 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17610 OutChains[0] = DAG.getStore(Root, dl,
17611 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17612 Trmp, MachinePointerInfo(TrmpAddr),
17615 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17616 DAG.getConstant(1, MVT::i32));
17617 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17618 MachinePointerInfo(TrmpAddr, 1),
17621 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17622 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17623 DAG.getConstant(5, MVT::i32));
17624 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17625 MachinePointerInfo(TrmpAddr, 5),
17628 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17629 DAG.getConstant(6, MVT::i32));
17630 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17631 MachinePointerInfo(TrmpAddr, 6),
17634 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17638 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17639 SelectionDAG &DAG) const {
17641 The rounding mode is in bits 11:10 of FPSR, and has the following
17643 00 Round to nearest
17648 FLT_ROUNDS, on the other hand, expects the following:
17655 To perform the conversion, we do:
17656 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17659 MachineFunction &MF = DAG.getMachineFunction();
17660 const TargetMachine &TM = MF.getTarget();
17661 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17662 unsigned StackAlignment = TFI.getStackAlignment();
17663 MVT VT = Op.getSimpleValueType();
17666 // Save FP Control Word to stack slot
17667 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17668 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17670 MachineMemOperand *MMO =
17671 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17672 MachineMemOperand::MOStore, 2, 2);
17674 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17675 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17676 DAG.getVTList(MVT::Other),
17677 Ops, MVT::i16, MMO);
17679 // Load FP Control Word from stack slot
17680 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17681 MachinePointerInfo(), false, false, false, 0);
17683 // Transform as necessary
17685 DAG.getNode(ISD::SRL, DL, MVT::i16,
17686 DAG.getNode(ISD::AND, DL, MVT::i16,
17687 CWD, DAG.getConstant(0x800, MVT::i16)),
17688 DAG.getConstant(11, MVT::i8));
17690 DAG.getNode(ISD::SRL, DL, MVT::i16,
17691 DAG.getNode(ISD::AND, DL, MVT::i16,
17692 CWD, DAG.getConstant(0x400, MVT::i16)),
17693 DAG.getConstant(9, MVT::i8));
17696 DAG.getNode(ISD::AND, DL, MVT::i16,
17697 DAG.getNode(ISD::ADD, DL, MVT::i16,
17698 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17699 DAG.getConstant(1, MVT::i16)),
17700 DAG.getConstant(3, MVT::i16));
17702 return DAG.getNode((VT.getSizeInBits() < 16 ?
17703 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17706 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17707 MVT VT = Op.getSimpleValueType();
17709 unsigned NumBits = VT.getSizeInBits();
17712 Op = Op.getOperand(0);
17713 if (VT == MVT::i8) {
17714 // Zero extend to i32 since there is not an i8 bsr.
17716 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17719 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17720 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17721 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17723 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17726 DAG.getConstant(NumBits+NumBits-1, OpVT),
17727 DAG.getConstant(X86::COND_E, MVT::i8),
17730 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17732 // Finally xor with NumBits-1.
17733 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17736 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17740 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17741 MVT VT = Op.getSimpleValueType();
17743 unsigned NumBits = VT.getSizeInBits();
17746 Op = Op.getOperand(0);
17747 if (VT == MVT::i8) {
17748 // Zero extend to i32 since there is not an i8 bsr.
17750 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17753 // Issue a bsr (scan bits in reverse).
17754 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17755 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17757 // And xor with NumBits-1.
17758 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17761 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17765 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17766 MVT VT = Op.getSimpleValueType();
17767 unsigned NumBits = VT.getSizeInBits();
17769 Op = Op.getOperand(0);
17771 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17772 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17773 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17775 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17778 DAG.getConstant(NumBits, VT),
17779 DAG.getConstant(X86::COND_E, MVT::i8),
17782 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17785 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17786 // ones, and then concatenate the result back.
17787 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17788 MVT VT = Op.getSimpleValueType();
17790 assert(VT.is256BitVector() && VT.isInteger() &&
17791 "Unsupported value type for operation");
17793 unsigned NumElems = VT.getVectorNumElements();
17796 // Extract the LHS vectors
17797 SDValue LHS = Op.getOperand(0);
17798 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17799 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17801 // Extract the RHS vectors
17802 SDValue RHS = Op.getOperand(1);
17803 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17804 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17806 MVT EltVT = VT.getVectorElementType();
17807 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17809 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17810 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17811 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17814 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17815 assert(Op.getSimpleValueType().is256BitVector() &&
17816 Op.getSimpleValueType().isInteger() &&
17817 "Only handle AVX 256-bit vector integer operation");
17818 return Lower256IntArith(Op, DAG);
17821 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17822 assert(Op.getSimpleValueType().is256BitVector() &&
17823 Op.getSimpleValueType().isInteger() &&
17824 "Only handle AVX 256-bit vector integer operation");
17825 return Lower256IntArith(Op, DAG);
17828 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17829 SelectionDAG &DAG) {
17831 MVT VT = Op.getSimpleValueType();
17833 // Decompose 256-bit ops into smaller 128-bit ops.
17834 if (VT.is256BitVector() && !Subtarget->hasInt256())
17835 return Lower256IntArith(Op, DAG);
17837 SDValue A = Op.getOperand(0);
17838 SDValue B = Op.getOperand(1);
17840 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17841 if (VT == MVT::v4i32) {
17842 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17843 "Should not custom lower when pmuldq is available!");
17845 // Extract the odd parts.
17846 static const int UnpackMask[] = { 1, -1, 3, -1 };
17847 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17848 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17850 // Multiply the even parts.
17851 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17852 // Now multiply odd parts.
17853 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17855 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17856 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17858 // Merge the two vectors back together with a shuffle. This expands into 2
17860 static const int ShufMask[] = { 0, 4, 2, 6 };
17861 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17864 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17865 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17867 // Ahi = psrlqi(a, 32);
17868 // Bhi = psrlqi(b, 32);
17870 // AloBlo = pmuludq(a, b);
17871 // AloBhi = pmuludq(a, Bhi);
17872 // AhiBlo = pmuludq(Ahi, b);
17874 // AloBhi = psllqi(AloBhi, 32);
17875 // AhiBlo = psllqi(AhiBlo, 32);
17876 // return AloBlo + AloBhi + AhiBlo;
17878 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17879 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17881 // Bit cast to 32-bit vectors for MULUDQ
17882 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17883 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17884 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17885 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17886 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17887 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17889 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17890 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17891 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17893 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17894 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17896 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17897 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17900 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17901 assert(Subtarget->isTargetWin64() && "Unexpected target");
17902 EVT VT = Op.getValueType();
17903 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17904 "Unexpected return type for lowering");
17908 switch (Op->getOpcode()) {
17909 default: llvm_unreachable("Unexpected request for libcall!");
17910 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17911 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17912 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17913 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17914 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17915 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17919 SDValue InChain = DAG.getEntryNode();
17921 TargetLowering::ArgListTy Args;
17922 TargetLowering::ArgListEntry Entry;
17923 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17924 EVT ArgVT = Op->getOperand(i).getValueType();
17925 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17926 "Unexpected argument type for lowering");
17927 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17928 Entry.Node = StackPtr;
17929 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17931 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17932 Entry.Ty = PointerType::get(ArgTy,0);
17933 Entry.isSExt = false;
17934 Entry.isZExt = false;
17935 Args.push_back(Entry);
17938 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17941 TargetLowering::CallLoweringInfo CLI(DAG);
17942 CLI.setDebugLoc(dl).setChain(InChain)
17943 .setCallee(getLibcallCallingConv(LC),
17944 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17945 Callee, std::move(Args), 0)
17946 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17948 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17949 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17952 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17953 SelectionDAG &DAG) {
17954 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17955 EVT VT = Op0.getValueType();
17958 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17959 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17961 // PMULxD operations multiply each even value (starting at 0) of LHS with
17962 // the related value of RHS and produce a widen result.
17963 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17964 // => <2 x i64> <ae|cg>
17966 // In other word, to have all the results, we need to perform two PMULxD:
17967 // 1. one with the even values.
17968 // 2. one with the odd values.
17969 // To achieve #2, with need to place the odd values at an even position.
17971 // Place the odd value at an even position (basically, shift all values 1
17972 // step to the left):
17973 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17974 // <a|b|c|d> => <b|undef|d|undef>
17975 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17976 // <e|f|g|h> => <f|undef|h|undef>
17977 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17979 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17981 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17982 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17984 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17985 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17986 // => <2 x i64> <ae|cg>
17987 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17988 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17989 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17990 // => <2 x i64> <bf|dh>
17991 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17992 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17994 // Shuffle it back into the right order.
17995 SDValue Highs, Lows;
17996 if (VT == MVT::v8i32) {
17997 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17998 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17999 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18000 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18002 const int HighMask[] = {1, 5, 3, 7};
18003 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18004 const int LowMask[] = {0, 4, 2, 6};
18005 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18008 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18009 // unsigned multiply.
18010 if (IsSigned && !Subtarget->hasSSE41()) {
18012 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18013 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18014 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18015 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18016 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18018 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18019 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18022 // The first result of MUL_LOHI is actually the low value, followed by the
18024 SDValue Ops[] = {Lows, Highs};
18025 return DAG.getMergeValues(Ops, dl);
18028 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18029 const X86Subtarget *Subtarget) {
18030 MVT VT = Op.getSimpleValueType();
18032 SDValue R = Op.getOperand(0);
18033 SDValue Amt = Op.getOperand(1);
18035 // Optimize shl/srl/sra with constant shift amount.
18036 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18037 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18038 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18040 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18041 (Subtarget->hasInt256() &&
18042 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18043 (Subtarget->hasAVX512() &&
18044 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18045 if (Op.getOpcode() == ISD::SHL)
18046 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18048 if (Op.getOpcode() == ISD::SRL)
18049 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18051 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18052 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18056 if (VT == MVT::v16i8) {
18057 if (Op.getOpcode() == ISD::SHL) {
18058 // Make a large shift.
18059 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18060 MVT::v8i16, R, ShiftAmt,
18062 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18063 // Zero out the rightmost bits.
18064 SmallVector<SDValue, 16> V(16,
18065 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18067 return DAG.getNode(ISD::AND, dl, VT, SHL,
18068 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18070 if (Op.getOpcode() == ISD::SRL) {
18071 // Make a large shift.
18072 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18073 MVT::v8i16, R, ShiftAmt,
18075 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18076 // Zero out the leftmost bits.
18077 SmallVector<SDValue, 16> V(16,
18078 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18080 return DAG.getNode(ISD::AND, dl, VT, SRL,
18081 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18083 if (Op.getOpcode() == ISD::SRA) {
18084 if (ShiftAmt == 7) {
18085 // R s>> 7 === R s< 0
18086 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18087 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18090 // R s>> a === ((R u>> a) ^ m) - m
18091 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18092 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18094 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18095 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18096 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18099 llvm_unreachable("Unknown shift opcode.");
18102 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18103 if (Op.getOpcode() == ISD::SHL) {
18104 // Make a large shift.
18105 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18106 MVT::v16i16, R, ShiftAmt,
18108 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18109 // Zero out the rightmost bits.
18110 SmallVector<SDValue, 32> V(32,
18111 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18113 return DAG.getNode(ISD::AND, dl, VT, SHL,
18114 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18116 if (Op.getOpcode() == ISD::SRL) {
18117 // Make a large shift.
18118 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18119 MVT::v16i16, R, ShiftAmt,
18121 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18122 // Zero out the leftmost bits.
18123 SmallVector<SDValue, 32> V(32,
18124 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18126 return DAG.getNode(ISD::AND, dl, VT, SRL,
18127 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18129 if (Op.getOpcode() == ISD::SRA) {
18130 if (ShiftAmt == 7) {
18131 // R s>> 7 === R s< 0
18132 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18133 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18136 // R s>> a === ((R u>> a) ^ m) - m
18137 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18138 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18140 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18141 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18142 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18145 llvm_unreachable("Unknown shift opcode.");
18150 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18151 if (!Subtarget->is64Bit() &&
18152 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18153 Amt.getOpcode() == ISD::BITCAST &&
18154 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18155 Amt = Amt.getOperand(0);
18156 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18157 VT.getVectorNumElements();
18158 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18159 uint64_t ShiftAmt = 0;
18160 for (unsigned i = 0; i != Ratio; ++i) {
18161 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18165 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18167 // Check remaining shift amounts.
18168 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18169 uint64_t ShAmt = 0;
18170 for (unsigned j = 0; j != Ratio; ++j) {
18171 ConstantSDNode *C =
18172 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18176 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18178 if (ShAmt != ShiftAmt)
18181 switch (Op.getOpcode()) {
18183 llvm_unreachable("Unknown shift opcode!");
18185 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18188 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18191 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18199 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18200 const X86Subtarget* Subtarget) {
18201 MVT VT = Op.getSimpleValueType();
18203 SDValue R = Op.getOperand(0);
18204 SDValue Amt = Op.getOperand(1);
18206 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18207 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18208 (Subtarget->hasInt256() &&
18209 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18210 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18211 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18213 EVT EltVT = VT.getVectorElementType();
18215 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18216 unsigned NumElts = VT.getVectorNumElements();
18218 for (i = 0; i != NumElts; ++i) {
18219 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18223 for (j = i; j != NumElts; ++j) {
18224 SDValue Arg = Amt.getOperand(j);
18225 if (Arg.getOpcode() == ISD::UNDEF) continue;
18226 if (Arg != Amt.getOperand(i))
18229 if (i != NumElts && j == NumElts)
18230 BaseShAmt = Amt.getOperand(i);
18232 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18233 Amt = Amt.getOperand(0);
18234 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18235 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18236 SDValue InVec = Amt.getOperand(0);
18237 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18238 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18240 for (; i != NumElts; ++i) {
18241 SDValue Arg = InVec.getOperand(i);
18242 if (Arg.getOpcode() == ISD::UNDEF) continue;
18246 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18247 if (ConstantSDNode *C =
18248 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18249 unsigned SplatIdx =
18250 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18251 if (C->getZExtValue() == SplatIdx)
18252 BaseShAmt = InVec.getOperand(1);
18255 if (!BaseShAmt.getNode())
18256 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18257 DAG.getIntPtrConstant(0));
18261 if (BaseShAmt.getNode()) {
18262 if (EltVT.bitsGT(MVT::i32))
18263 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18264 else if (EltVT.bitsLT(MVT::i32))
18265 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18267 switch (Op.getOpcode()) {
18269 llvm_unreachable("Unknown shift opcode!");
18271 switch (VT.SimpleTy) {
18272 default: return SDValue();
18281 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18284 switch (VT.SimpleTy) {
18285 default: return SDValue();
18292 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18295 switch (VT.SimpleTy) {
18296 default: return SDValue();
18305 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18311 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18312 if (!Subtarget->is64Bit() &&
18313 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18314 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18315 Amt.getOpcode() == ISD::BITCAST &&
18316 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18317 Amt = Amt.getOperand(0);
18318 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18319 VT.getVectorNumElements();
18320 std::vector<SDValue> Vals(Ratio);
18321 for (unsigned i = 0; i != Ratio; ++i)
18322 Vals[i] = Amt.getOperand(i);
18323 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18324 for (unsigned j = 0; j != Ratio; ++j)
18325 if (Vals[j] != Amt.getOperand(i + j))
18328 switch (Op.getOpcode()) {
18330 llvm_unreachable("Unknown shift opcode!");
18332 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18334 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18336 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18343 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18344 SelectionDAG &DAG) {
18345 MVT VT = Op.getSimpleValueType();
18347 SDValue R = Op.getOperand(0);
18348 SDValue Amt = Op.getOperand(1);
18351 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18352 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18354 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18358 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18362 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18364 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18365 if (Subtarget->hasInt256()) {
18366 if (Op.getOpcode() == ISD::SRL &&
18367 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18368 VT == MVT::v4i64 || VT == MVT::v8i32))
18370 if (Op.getOpcode() == ISD::SHL &&
18371 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18372 VT == MVT::v4i64 || VT == MVT::v8i32))
18374 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18378 // If possible, lower this packed shift into a vector multiply instead of
18379 // expanding it into a sequence of scalar shifts.
18380 // Do this only if the vector shift count is a constant build_vector.
18381 if (Op.getOpcode() == ISD::SHL &&
18382 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18383 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18384 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18385 SmallVector<SDValue, 8> Elts;
18386 EVT SVT = VT.getScalarType();
18387 unsigned SVTBits = SVT.getSizeInBits();
18388 const APInt &One = APInt(SVTBits, 1);
18389 unsigned NumElems = VT.getVectorNumElements();
18391 for (unsigned i=0; i !=NumElems; ++i) {
18392 SDValue Op = Amt->getOperand(i);
18393 if (Op->getOpcode() == ISD::UNDEF) {
18394 Elts.push_back(Op);
18398 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18399 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18400 uint64_t ShAmt = C.getZExtValue();
18401 if (ShAmt >= SVTBits) {
18402 Elts.push_back(DAG.getUNDEF(SVT));
18405 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18407 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18408 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18411 // Lower SHL with variable shift amount.
18412 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18413 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18415 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18416 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18417 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18418 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18421 // If possible, lower this shift as a sequence of two shifts by
18422 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18424 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18426 // Could be rewritten as:
18427 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18429 // The advantage is that the two shifts from the example would be
18430 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18431 // the vector shift into four scalar shifts plus four pairs of vector
18433 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18434 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18435 unsigned TargetOpcode = X86ISD::MOVSS;
18436 bool CanBeSimplified;
18437 // The splat value for the first packed shift (the 'X' from the example).
18438 SDValue Amt1 = Amt->getOperand(0);
18439 // The splat value for the second packed shift (the 'Y' from the example).
18440 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18441 Amt->getOperand(2);
18443 // See if it is possible to replace this node with a sequence of
18444 // two shifts followed by a MOVSS/MOVSD
18445 if (VT == MVT::v4i32) {
18446 // Check if it is legal to use a MOVSS.
18447 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18448 Amt2 == Amt->getOperand(3);
18449 if (!CanBeSimplified) {
18450 // Otherwise, check if we can still simplify this node using a MOVSD.
18451 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18452 Amt->getOperand(2) == Amt->getOperand(3);
18453 TargetOpcode = X86ISD::MOVSD;
18454 Amt2 = Amt->getOperand(2);
18457 // Do similar checks for the case where the machine value type
18459 CanBeSimplified = Amt1 == Amt->getOperand(1);
18460 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18461 CanBeSimplified = Amt2 == Amt->getOperand(i);
18463 if (!CanBeSimplified) {
18464 TargetOpcode = X86ISD::MOVSD;
18465 CanBeSimplified = true;
18466 Amt2 = Amt->getOperand(4);
18467 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18468 CanBeSimplified = Amt1 == Amt->getOperand(i);
18469 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18470 CanBeSimplified = Amt2 == Amt->getOperand(j);
18474 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18475 isa<ConstantSDNode>(Amt2)) {
18476 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18477 EVT CastVT = MVT::v4i32;
18479 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18480 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18482 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18483 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18484 if (TargetOpcode == X86ISD::MOVSD)
18485 CastVT = MVT::v2i64;
18486 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18487 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18488 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18490 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18494 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18495 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18498 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18499 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18501 // Turn 'a' into a mask suitable for VSELECT
18502 SDValue VSelM = DAG.getConstant(0x80, VT);
18503 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18504 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18506 SDValue CM1 = DAG.getConstant(0x0f, VT);
18507 SDValue CM2 = DAG.getConstant(0x3f, VT);
18509 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18510 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18511 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18512 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18513 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18516 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18517 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18518 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18520 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18521 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18522 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18523 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18524 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18527 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18528 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18529 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18531 // return VSELECT(r, r+r, a);
18532 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18533 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18537 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18538 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18539 // solution better.
18540 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18541 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18543 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18544 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18545 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18546 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18547 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18550 // Decompose 256-bit shifts into smaller 128-bit shifts.
18551 if (VT.is256BitVector()) {
18552 unsigned NumElems = VT.getVectorNumElements();
18553 MVT EltVT = VT.getVectorElementType();
18554 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18556 // Extract the two vectors
18557 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18558 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18560 // Recreate the shift amount vectors
18561 SDValue Amt1, Amt2;
18562 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18563 // Constant shift amount
18564 SmallVector<SDValue, 4> Amt1Csts;
18565 SmallVector<SDValue, 4> Amt2Csts;
18566 for (unsigned i = 0; i != NumElems/2; ++i)
18567 Amt1Csts.push_back(Amt->getOperand(i));
18568 for (unsigned i = NumElems/2; i != NumElems; ++i)
18569 Amt2Csts.push_back(Amt->getOperand(i));
18571 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18572 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18574 // Variable shift amount
18575 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18576 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18579 // Issue new vector shifts for the smaller types
18580 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18581 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18583 // Concatenate the result back
18584 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18590 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18591 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18592 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18593 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18594 // has only one use.
18595 SDNode *N = Op.getNode();
18596 SDValue LHS = N->getOperand(0);
18597 SDValue RHS = N->getOperand(1);
18598 unsigned BaseOp = 0;
18601 switch (Op.getOpcode()) {
18602 default: llvm_unreachable("Unknown ovf instruction!");
18604 // A subtract of one will be selected as a INC. Note that INC doesn't
18605 // set CF, so we can't do this for UADDO.
18606 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18608 BaseOp = X86ISD::INC;
18609 Cond = X86::COND_O;
18612 BaseOp = X86ISD::ADD;
18613 Cond = X86::COND_O;
18616 BaseOp = X86ISD::ADD;
18617 Cond = X86::COND_B;
18620 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18621 // set CF, so we can't do this for USUBO.
18622 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18624 BaseOp = X86ISD::DEC;
18625 Cond = X86::COND_O;
18628 BaseOp = X86ISD::SUB;
18629 Cond = X86::COND_O;
18632 BaseOp = X86ISD::SUB;
18633 Cond = X86::COND_B;
18636 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18637 Cond = X86::COND_O;
18639 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18640 if (N->getValueType(0) == MVT::i8) {
18641 BaseOp = X86ISD::UMUL8;
18642 Cond = X86::COND_O;
18645 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18647 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18650 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18651 DAG.getConstant(X86::COND_O, MVT::i32),
18652 SDValue(Sum.getNode(), 2));
18654 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18658 // Also sets EFLAGS.
18659 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18660 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18663 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18664 DAG.getConstant(Cond, MVT::i32),
18665 SDValue(Sum.getNode(), 1));
18667 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18670 // Sign extension of the low part of vector elements. This may be used either
18671 // when sign extend instructions are not available or if the vector element
18672 // sizes already match the sign-extended size. If the vector elements are in
18673 // their pre-extended size and sign extend instructions are available, that will
18674 // be handled by LowerSIGN_EXTEND.
18675 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18676 SelectionDAG &DAG) const {
18678 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18679 MVT VT = Op.getSimpleValueType();
18681 if (!Subtarget->hasSSE2() || !VT.isVector())
18684 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18685 ExtraVT.getScalarType().getSizeInBits();
18687 switch (VT.SimpleTy) {
18688 default: return SDValue();
18691 if (!Subtarget->hasFp256())
18693 if (!Subtarget->hasInt256()) {
18694 // needs to be split
18695 unsigned NumElems = VT.getVectorNumElements();
18697 // Extract the LHS vectors
18698 SDValue LHS = Op.getOperand(0);
18699 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18700 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18702 MVT EltVT = VT.getVectorElementType();
18703 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18705 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18706 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18707 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18709 SDValue Extra = DAG.getValueType(ExtraVT);
18711 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18712 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18714 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18719 SDValue Op0 = Op.getOperand(0);
18721 // This is a sign extension of some low part of vector elements without
18722 // changing the size of the vector elements themselves:
18723 // Shift-Left + Shift-Right-Algebraic.
18724 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18726 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18732 /// Returns true if the operand type is exactly twice the native width, and
18733 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18734 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18735 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18736 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18737 const X86Subtarget &Subtarget =
18738 getTargetMachine().getSubtarget<X86Subtarget>();
18739 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18742 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18743 else if (OpWidth == 128)
18744 return Subtarget.hasCmpxchg16b();
18749 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18750 return needsCmpXchgNb(SI->getValueOperand()->getType());
18753 // Note: this turns large loads into lock cmpxchg8b/16b.
18754 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18755 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18756 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18757 return needsCmpXchgNb(PTy->getElementType());
18760 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18761 const X86Subtarget &Subtarget =
18762 getTargetMachine().getSubtarget<X86Subtarget>();
18763 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18764 const Type *MemType = AI->getType();
18766 // If the operand is too big, we must see if cmpxchg8/16b is available
18767 // and default to library calls otherwise.
18768 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18769 return needsCmpXchgNb(MemType);
18771 AtomicRMWInst::BinOp Op = AI->getOperation();
18774 llvm_unreachable("Unknown atomic operation");
18775 case AtomicRMWInst::Xchg:
18776 case AtomicRMWInst::Add:
18777 case AtomicRMWInst::Sub:
18778 // It's better to use xadd, xsub or xchg for these in all cases.
18780 case AtomicRMWInst::Or:
18781 case AtomicRMWInst::And:
18782 case AtomicRMWInst::Xor:
18783 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18784 // prefix to a normal instruction for these operations.
18785 return !AI->use_empty();
18786 case AtomicRMWInst::Nand:
18787 case AtomicRMWInst::Max:
18788 case AtomicRMWInst::Min:
18789 case AtomicRMWInst::UMax:
18790 case AtomicRMWInst::UMin:
18791 // These always require a non-trivial set of data operations on x86. We must
18792 // use a cmpxchg loop.
18797 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18798 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18799 // no-sse2). There isn't any reason to disable it if the target processor
18801 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18805 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18806 const X86Subtarget &Subtarget =
18807 getTargetMachine().getSubtarget<X86Subtarget>();
18808 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18809 const Type *MemType = AI->getType();
18810 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18811 // there is no benefit in turning such RMWs into loads, and it is actually
18812 // harmful as it introduces a mfence.
18813 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18816 auto Builder = IRBuilder<>(AI);
18817 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18818 auto SynchScope = AI->getSynchScope();
18819 // We must restrict the ordering to avoid generating loads with Release or
18820 // ReleaseAcquire orderings.
18821 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18822 auto Ptr = AI->getPointerOperand();
18824 // Before the load we need a fence. Here is an example lifted from
18825 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18828 // x.store(1, relaxed);
18829 // r1 = y.fetch_add(0, release);
18831 // y.fetch_add(42, acquire);
18832 // r2 = x.load(relaxed);
18833 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18834 // lowered to just a load without a fence. A mfence flushes the store buffer,
18835 // making the optimization clearly correct.
18836 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18837 // otherwise, we might be able to be more agressive on relaxed idempotent
18838 // rmw. In practice, they do not look useful, so we don't try to be
18839 // especially clever.
18840 if (SynchScope == SingleThread) {
18841 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18842 // the IR level, so we must wrap it in an intrinsic.
18844 } else if (hasMFENCE(Subtarget)) {
18845 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18846 Intrinsic::x86_sse2_mfence);
18847 Builder.CreateCall(MFence);
18849 // FIXME: it might make sense to use a locked operation here but on a
18850 // different cache-line to prevent cache-line bouncing. In practice it
18851 // is probably a small win, and x86 processors without mfence are rare
18852 // enough that we do not bother.
18856 // Finally we can emit the atomic load.
18857 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18858 AI->getType()->getPrimitiveSizeInBits());
18859 Loaded->setAtomic(Order, SynchScope);
18860 AI->replaceAllUsesWith(Loaded);
18861 AI->eraseFromParent();
18865 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18866 SelectionDAG &DAG) {
18868 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18869 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18870 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18871 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18873 // The only fence that needs an instruction is a sequentially-consistent
18874 // cross-thread fence.
18875 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18876 if (hasMFENCE(*Subtarget))
18877 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18879 SDValue Chain = Op.getOperand(0);
18880 SDValue Zero = DAG.getConstant(0, MVT::i32);
18882 DAG.getRegister(X86::ESP, MVT::i32), // Base
18883 DAG.getTargetConstant(1, MVT::i8), // Scale
18884 DAG.getRegister(0, MVT::i32), // Index
18885 DAG.getTargetConstant(0, MVT::i32), // Disp
18886 DAG.getRegister(0, MVT::i32), // Segment.
18890 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18891 return SDValue(Res, 0);
18894 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18895 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18898 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18899 SelectionDAG &DAG) {
18900 MVT T = Op.getSimpleValueType();
18904 switch(T.SimpleTy) {
18905 default: llvm_unreachable("Invalid value type!");
18906 case MVT::i8: Reg = X86::AL; size = 1; break;
18907 case MVT::i16: Reg = X86::AX; size = 2; break;
18908 case MVT::i32: Reg = X86::EAX; size = 4; break;
18910 assert(Subtarget->is64Bit() && "Node not type legal!");
18911 Reg = X86::RAX; size = 8;
18914 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18915 Op.getOperand(2), SDValue());
18916 SDValue Ops[] = { cpIn.getValue(0),
18919 DAG.getTargetConstant(size, MVT::i8),
18920 cpIn.getValue(1) };
18921 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18922 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18923 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18927 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18928 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18929 MVT::i32, cpOut.getValue(2));
18930 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18931 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18933 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18934 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18935 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18939 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18940 SelectionDAG &DAG) {
18941 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18942 MVT DstVT = Op.getSimpleValueType();
18944 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18945 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18946 if (DstVT != MVT::f64)
18947 // This conversion needs to be expanded.
18950 SDValue InVec = Op->getOperand(0);
18952 unsigned NumElts = SrcVT.getVectorNumElements();
18953 EVT SVT = SrcVT.getVectorElementType();
18955 // Widen the vector in input in the case of MVT::v2i32.
18956 // Example: from MVT::v2i32 to MVT::v4i32.
18957 SmallVector<SDValue, 16> Elts;
18958 for (unsigned i = 0, e = NumElts; i != e; ++i)
18959 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18960 DAG.getIntPtrConstant(i)));
18962 // Explicitly mark the extra elements as Undef.
18963 SDValue Undef = DAG.getUNDEF(SVT);
18964 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18965 Elts.push_back(Undef);
18967 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18968 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18969 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18970 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18971 DAG.getIntPtrConstant(0));
18974 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18975 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18976 assert((DstVT == MVT::i64 ||
18977 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18978 "Unexpected custom BITCAST");
18979 // i64 <=> MMX conversions are Legal.
18980 if (SrcVT==MVT::i64 && DstVT.isVector())
18982 if (DstVT==MVT::i64 && SrcVT.isVector())
18984 // MMX <=> MMX conversions are Legal.
18985 if (SrcVT.isVector() && DstVT.isVector())
18987 // All other conversions need to be expanded.
18991 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18992 SDNode *Node = Op.getNode();
18994 EVT T = Node->getValueType(0);
18995 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18996 DAG.getConstant(0, T), Node->getOperand(2));
18997 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18998 cast<AtomicSDNode>(Node)->getMemoryVT(),
18999 Node->getOperand(0),
19000 Node->getOperand(1), negOp,
19001 cast<AtomicSDNode>(Node)->getMemOperand(),
19002 cast<AtomicSDNode>(Node)->getOrdering(),
19003 cast<AtomicSDNode>(Node)->getSynchScope());
19006 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19007 SDNode *Node = Op.getNode();
19009 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19011 // Convert seq_cst store -> xchg
19012 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19013 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19014 // (The only way to get a 16-byte store is cmpxchg16b)
19015 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19016 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19017 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19018 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19019 cast<AtomicSDNode>(Node)->getMemoryVT(),
19020 Node->getOperand(0),
19021 Node->getOperand(1), Node->getOperand(2),
19022 cast<AtomicSDNode>(Node)->getMemOperand(),
19023 cast<AtomicSDNode>(Node)->getOrdering(),
19024 cast<AtomicSDNode>(Node)->getSynchScope());
19025 return Swap.getValue(1);
19027 // Other atomic stores have a simple pattern.
19031 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19032 EVT VT = Op.getNode()->getSimpleValueType(0);
19034 // Let legalize expand this if it isn't a legal type yet.
19035 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19038 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19041 bool ExtraOp = false;
19042 switch (Op.getOpcode()) {
19043 default: llvm_unreachable("Invalid code");
19044 case ISD::ADDC: Opc = X86ISD::ADD; break;
19045 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19046 case ISD::SUBC: Opc = X86ISD::SUB; break;
19047 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19051 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19053 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19054 Op.getOperand(1), Op.getOperand(2));
19057 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19058 SelectionDAG &DAG) {
19059 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19061 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19062 // which returns the values as { float, float } (in XMM0) or
19063 // { double, double } (which is returned in XMM0, XMM1).
19065 SDValue Arg = Op.getOperand(0);
19066 EVT ArgVT = Arg.getValueType();
19067 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19069 TargetLowering::ArgListTy Args;
19070 TargetLowering::ArgListEntry Entry;
19074 Entry.isSExt = false;
19075 Entry.isZExt = false;
19076 Args.push_back(Entry);
19078 bool isF64 = ArgVT == MVT::f64;
19079 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19080 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19081 // the results are returned via SRet in memory.
19082 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19083 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19084 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19086 Type *RetTy = isF64
19087 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
19088 : (Type*)VectorType::get(ArgTy, 4);
19090 TargetLowering::CallLoweringInfo CLI(DAG);
19091 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19092 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19094 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19097 // Returned in xmm0 and xmm1.
19098 return CallResult.first;
19100 // Returned in bits 0:31 and 32:64 xmm0.
19101 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19102 CallResult.first, DAG.getIntPtrConstant(0));
19103 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19104 CallResult.first, DAG.getIntPtrConstant(1));
19105 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19106 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19109 /// LowerOperation - Provide custom lowering hooks for some operations.
19111 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19112 switch (Op.getOpcode()) {
19113 default: llvm_unreachable("Should not custom lower this!");
19114 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19115 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19116 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19117 return LowerCMP_SWAP(Op, Subtarget, DAG);
19118 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19119 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19120 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19121 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19122 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19123 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19124 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19125 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19126 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19127 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19128 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19129 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19130 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19131 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19132 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19133 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19134 case ISD::SHL_PARTS:
19135 case ISD::SRA_PARTS:
19136 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19137 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19138 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19139 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19140 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19141 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19142 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19143 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19144 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19145 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19146 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19148 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19149 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19150 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19151 case ISD::SETCC: return LowerSETCC(Op, DAG);
19152 case ISD::SELECT: return LowerSELECT(Op, DAG);
19153 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19154 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19155 case ISD::VASTART: return LowerVASTART(Op, DAG);
19156 case ISD::VAARG: return LowerVAARG(Op, DAG);
19157 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19158 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19159 case ISD::INTRINSIC_VOID:
19160 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19161 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19162 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19163 case ISD::FRAME_TO_ARGS_OFFSET:
19164 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19165 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19166 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19167 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19168 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19169 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19170 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19171 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19172 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19173 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19174 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19175 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19176 case ISD::UMUL_LOHI:
19177 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19180 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19186 case ISD::UMULO: return LowerXALUO(Op, DAG);
19187 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19188 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19192 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19193 case ISD::ADD: return LowerADD(Op, DAG);
19194 case ISD::SUB: return LowerSUB(Op, DAG);
19195 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19199 /// ReplaceNodeResults - Replace a node with an illegal result type
19200 /// with a new node built out of custom code.
19201 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19202 SmallVectorImpl<SDValue>&Results,
19203 SelectionDAG &DAG) const {
19205 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19206 switch (N->getOpcode()) {
19208 llvm_unreachable("Do not know how to custom type legalize this operation!");
19209 case ISD::SIGN_EXTEND_INREG:
19214 // We don't want to expand or promote these.
19221 case ISD::UDIVREM: {
19222 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19223 Results.push_back(V);
19226 case ISD::FP_TO_SINT:
19227 case ISD::FP_TO_UINT: {
19228 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19230 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19233 std::pair<SDValue,SDValue> Vals =
19234 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19235 SDValue FIST = Vals.first, StackSlot = Vals.second;
19236 if (FIST.getNode()) {
19237 EVT VT = N->getValueType(0);
19238 // Return a load from the stack slot.
19239 if (StackSlot.getNode())
19240 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19241 MachinePointerInfo(),
19242 false, false, false, 0));
19244 Results.push_back(FIST);
19248 case ISD::UINT_TO_FP: {
19249 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19250 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19251 N->getValueType(0) != MVT::v2f32)
19253 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19255 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19257 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19258 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19259 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19260 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19261 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19262 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19265 case ISD::FP_ROUND: {
19266 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19268 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19269 Results.push_back(V);
19272 case ISD::INTRINSIC_W_CHAIN: {
19273 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19275 default : llvm_unreachable("Do not know how to custom type "
19276 "legalize this intrinsic operation!");
19277 case Intrinsic::x86_rdtsc:
19278 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19280 case Intrinsic::x86_rdtscp:
19281 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19283 case Intrinsic::x86_rdpmc:
19284 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19287 case ISD::READCYCLECOUNTER: {
19288 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19291 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19292 EVT T = N->getValueType(0);
19293 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19294 bool Regs64bit = T == MVT::i128;
19295 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19296 SDValue cpInL, cpInH;
19297 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19298 DAG.getConstant(0, HalfT));
19299 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19300 DAG.getConstant(1, HalfT));
19301 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19302 Regs64bit ? X86::RAX : X86::EAX,
19304 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19305 Regs64bit ? X86::RDX : X86::EDX,
19306 cpInH, cpInL.getValue(1));
19307 SDValue swapInL, swapInH;
19308 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19309 DAG.getConstant(0, HalfT));
19310 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19311 DAG.getConstant(1, HalfT));
19312 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19313 Regs64bit ? X86::RBX : X86::EBX,
19314 swapInL, cpInH.getValue(1));
19315 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19316 Regs64bit ? X86::RCX : X86::ECX,
19317 swapInH, swapInL.getValue(1));
19318 SDValue Ops[] = { swapInH.getValue(0),
19320 swapInH.getValue(1) };
19321 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19322 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19323 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19324 X86ISD::LCMPXCHG8_DAG;
19325 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19326 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19327 Regs64bit ? X86::RAX : X86::EAX,
19328 HalfT, Result.getValue(1));
19329 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19330 Regs64bit ? X86::RDX : X86::EDX,
19331 HalfT, cpOutL.getValue(2));
19332 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19334 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19335 MVT::i32, cpOutH.getValue(2));
19337 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19338 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19339 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19341 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19342 Results.push_back(Success);
19343 Results.push_back(EFLAGS.getValue(1));
19346 case ISD::ATOMIC_SWAP:
19347 case ISD::ATOMIC_LOAD_ADD:
19348 case ISD::ATOMIC_LOAD_SUB:
19349 case ISD::ATOMIC_LOAD_AND:
19350 case ISD::ATOMIC_LOAD_OR:
19351 case ISD::ATOMIC_LOAD_XOR:
19352 case ISD::ATOMIC_LOAD_NAND:
19353 case ISD::ATOMIC_LOAD_MIN:
19354 case ISD::ATOMIC_LOAD_MAX:
19355 case ISD::ATOMIC_LOAD_UMIN:
19356 case ISD::ATOMIC_LOAD_UMAX:
19357 case ISD::ATOMIC_LOAD: {
19358 // Delegate to generic TypeLegalization. Situations we can really handle
19359 // should have already been dealt with by AtomicExpandPass.cpp.
19362 case ISD::BITCAST: {
19363 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19364 EVT DstVT = N->getValueType(0);
19365 EVT SrcVT = N->getOperand(0)->getValueType(0);
19367 if (SrcVT != MVT::f64 ||
19368 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19371 unsigned NumElts = DstVT.getVectorNumElements();
19372 EVT SVT = DstVT.getVectorElementType();
19373 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19374 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19375 MVT::v2f64, N->getOperand(0));
19376 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19378 if (ExperimentalVectorWideningLegalization) {
19379 // If we are legalizing vectors by widening, we already have the desired
19380 // legal vector type, just return it.
19381 Results.push_back(ToVecInt);
19385 SmallVector<SDValue, 8> Elts;
19386 for (unsigned i = 0, e = NumElts; i != e; ++i)
19387 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19388 ToVecInt, DAG.getIntPtrConstant(i)));
19390 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19395 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19397 default: return nullptr;
19398 case X86ISD::BSF: return "X86ISD::BSF";
19399 case X86ISD::BSR: return "X86ISD::BSR";
19400 case X86ISD::SHLD: return "X86ISD::SHLD";
19401 case X86ISD::SHRD: return "X86ISD::SHRD";
19402 case X86ISD::FAND: return "X86ISD::FAND";
19403 case X86ISD::FANDN: return "X86ISD::FANDN";
19404 case X86ISD::FOR: return "X86ISD::FOR";
19405 case X86ISD::FXOR: return "X86ISD::FXOR";
19406 case X86ISD::FSRL: return "X86ISD::FSRL";
19407 case X86ISD::FILD: return "X86ISD::FILD";
19408 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19409 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19410 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19411 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19412 case X86ISD::FLD: return "X86ISD::FLD";
19413 case X86ISD::FST: return "X86ISD::FST";
19414 case X86ISD::CALL: return "X86ISD::CALL";
19415 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19416 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19417 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19418 case X86ISD::BT: return "X86ISD::BT";
19419 case X86ISD::CMP: return "X86ISD::CMP";
19420 case X86ISD::COMI: return "X86ISD::COMI";
19421 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19422 case X86ISD::CMPM: return "X86ISD::CMPM";
19423 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19424 case X86ISD::SETCC: return "X86ISD::SETCC";
19425 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19426 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19427 case X86ISD::CMOV: return "X86ISD::CMOV";
19428 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19429 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19430 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19431 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19432 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19433 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19434 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19435 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19436 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19437 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19438 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19439 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19440 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19441 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19442 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19443 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19444 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19445 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19446 case X86ISD::HADD: return "X86ISD::HADD";
19447 case X86ISD::HSUB: return "X86ISD::HSUB";
19448 case X86ISD::FHADD: return "X86ISD::FHADD";
19449 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19450 case X86ISD::UMAX: return "X86ISD::UMAX";
19451 case X86ISD::UMIN: return "X86ISD::UMIN";
19452 case X86ISD::SMAX: return "X86ISD::SMAX";
19453 case X86ISD::SMIN: return "X86ISD::SMIN";
19454 case X86ISD::FMAX: return "X86ISD::FMAX";
19455 case X86ISD::FMIN: return "X86ISD::FMIN";
19456 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19457 case X86ISD::FMINC: return "X86ISD::FMINC";
19458 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19459 case X86ISD::FRCP: return "X86ISD::FRCP";
19460 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19461 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19462 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19463 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19464 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19465 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19466 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19467 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19468 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19469 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19470 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19471 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19472 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19473 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19474 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19475 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19476 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19477 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19478 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19479 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19480 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19481 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19482 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19483 case X86ISD::VSHL: return "X86ISD::VSHL";
19484 case X86ISD::VSRL: return "X86ISD::VSRL";
19485 case X86ISD::VSRA: return "X86ISD::VSRA";
19486 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19487 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19488 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19489 case X86ISD::CMPP: return "X86ISD::CMPP";
19490 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19491 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19492 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19493 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19494 case X86ISD::ADD: return "X86ISD::ADD";
19495 case X86ISD::SUB: return "X86ISD::SUB";
19496 case X86ISD::ADC: return "X86ISD::ADC";
19497 case X86ISD::SBB: return "X86ISD::SBB";
19498 case X86ISD::SMUL: return "X86ISD::SMUL";
19499 case X86ISD::UMUL: return "X86ISD::UMUL";
19500 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19501 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19502 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19503 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19504 case X86ISD::INC: return "X86ISD::INC";
19505 case X86ISD::DEC: return "X86ISD::DEC";
19506 case X86ISD::OR: return "X86ISD::OR";
19507 case X86ISD::XOR: return "X86ISD::XOR";
19508 case X86ISD::AND: return "X86ISD::AND";
19509 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19510 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19511 case X86ISD::PTEST: return "X86ISD::PTEST";
19512 case X86ISD::TESTP: return "X86ISD::TESTP";
19513 case X86ISD::TESTM: return "X86ISD::TESTM";
19514 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19515 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19516 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19517 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19518 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19519 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19520 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19521 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19522 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19523 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19524 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19525 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19526 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19527 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19528 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19529 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19530 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19531 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19532 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19533 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19534 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19535 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19536 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19537 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19538 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19539 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19540 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19541 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19542 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19543 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19544 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19545 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19546 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19547 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19548 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19549 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19550 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19551 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19552 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19553 case X86ISD::SAHF: return "X86ISD::SAHF";
19554 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19555 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19556 case X86ISD::FMADD: return "X86ISD::FMADD";
19557 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19558 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19559 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19560 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19561 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19562 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19563 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19564 case X86ISD::XTEST: return "X86ISD::XTEST";
19568 // isLegalAddressingMode - Return true if the addressing mode represented
19569 // by AM is legal for this target, for a load/store of the specified type.
19570 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19572 // X86 supports extremely general addressing modes.
19573 CodeModel::Model M = getTargetMachine().getCodeModel();
19574 Reloc::Model R = getTargetMachine().getRelocationModel();
19576 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19577 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19582 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19584 // If a reference to this global requires an extra load, we can't fold it.
19585 if (isGlobalStubReference(GVFlags))
19588 // If BaseGV requires a register for the PIC base, we cannot also have a
19589 // BaseReg specified.
19590 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19593 // If lower 4G is not available, then we must use rip-relative addressing.
19594 if ((M != CodeModel::Small || R != Reloc::Static) &&
19595 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19599 switch (AM.Scale) {
19605 // These scales always work.
19610 // These scales are formed with basereg+scalereg. Only accept if there is
19615 default: // Other stuff never works.
19622 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19623 unsigned Bits = Ty->getScalarSizeInBits();
19625 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19626 // particularly cheaper than those without.
19630 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19631 // variable shifts just as cheap as scalar ones.
19632 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19635 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19636 // fully general vector.
19640 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19641 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19643 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19644 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19645 return NumBits1 > NumBits2;
19648 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19649 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19652 if (!isTypeLegal(EVT::getEVT(Ty1)))
19655 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19657 // Assuming the caller doesn't have a zeroext or signext return parameter,
19658 // truncation all the way down to i1 is valid.
19662 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19663 return isInt<32>(Imm);
19666 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19667 // Can also use sub to handle negated immediates.
19668 return isInt<32>(Imm);
19671 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19672 if (!VT1.isInteger() || !VT2.isInteger())
19674 unsigned NumBits1 = VT1.getSizeInBits();
19675 unsigned NumBits2 = VT2.getSizeInBits();
19676 return NumBits1 > NumBits2;
19679 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19680 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19681 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19684 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19685 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19686 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19689 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19690 EVT VT1 = Val.getValueType();
19691 if (isZExtFree(VT1, VT2))
19694 if (Val.getOpcode() != ISD::LOAD)
19697 if (!VT1.isSimple() || !VT1.isInteger() ||
19698 !VT2.isSimple() || !VT2.isInteger())
19701 switch (VT1.getSimpleVT().SimpleTy) {
19706 // X86 has 8, 16, and 32-bit zero-extending loads.
19714 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19715 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19718 VT = VT.getScalarType();
19720 if (!VT.isSimple())
19723 switch (VT.getSimpleVT().SimpleTy) {
19734 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19735 // i16 instructions are longer (0x66 prefix) and potentially slower.
19736 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19739 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19740 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19741 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19742 /// are assumed to be legal.
19744 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19746 if (!VT.isSimple())
19749 MVT SVT = VT.getSimpleVT();
19751 // Very little shuffling can be done for 64-bit vectors right now.
19752 if (VT.getSizeInBits() == 64)
19755 // If this is a single-input shuffle with no 128 bit lane crossings we can
19756 // lower it into pshufb.
19757 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19758 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19759 bool isLegal = true;
19760 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19761 if (M[I] >= (int)SVT.getVectorNumElements() ||
19762 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19771 // FIXME: blends, shifts.
19772 return (SVT.getVectorNumElements() == 2 ||
19773 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19774 isMOVLMask(M, SVT) ||
19775 isMOVHLPSMask(M, SVT) ||
19776 isSHUFPMask(M, SVT) ||
19777 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19778 isPSHUFDMask(M, SVT) ||
19779 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19780 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19781 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19782 isPALIGNRMask(M, SVT, Subtarget) ||
19783 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19784 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19785 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19786 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19787 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19788 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19792 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19794 if (!VT.isSimple())
19797 MVT SVT = VT.getSimpleVT();
19798 unsigned NumElts = SVT.getVectorNumElements();
19799 // FIXME: This collection of masks seems suspect.
19802 if (NumElts == 4 && SVT.is128BitVector()) {
19803 return (isMOVLMask(Mask, SVT) ||
19804 isCommutedMOVLMask(Mask, SVT, true) ||
19805 isSHUFPMask(Mask, SVT) ||
19806 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19807 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19808 Subtarget->hasInt256()));
19813 //===----------------------------------------------------------------------===//
19814 // X86 Scheduler Hooks
19815 //===----------------------------------------------------------------------===//
19817 /// Utility function to emit xbegin specifying the start of an RTM region.
19818 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19819 const TargetInstrInfo *TII) {
19820 DebugLoc DL = MI->getDebugLoc();
19822 const BasicBlock *BB = MBB->getBasicBlock();
19823 MachineFunction::iterator I = MBB;
19826 // For the v = xbegin(), we generate
19837 MachineBasicBlock *thisMBB = MBB;
19838 MachineFunction *MF = MBB->getParent();
19839 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19840 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19841 MF->insert(I, mainMBB);
19842 MF->insert(I, sinkMBB);
19844 // Transfer the remainder of BB and its successor edges to sinkMBB.
19845 sinkMBB->splice(sinkMBB->begin(), MBB,
19846 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19847 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19851 // # fallthrough to mainMBB
19852 // # abortion to sinkMBB
19853 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19854 thisMBB->addSuccessor(mainMBB);
19855 thisMBB->addSuccessor(sinkMBB);
19859 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19860 mainMBB->addSuccessor(sinkMBB);
19863 // EAX is live into the sinkMBB
19864 sinkMBB->addLiveIn(X86::EAX);
19865 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19866 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19869 MI->eraseFromParent();
19873 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19874 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19875 // in the .td file.
19876 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19877 const TargetInstrInfo *TII) {
19879 switch (MI->getOpcode()) {
19880 default: llvm_unreachable("illegal opcode!");
19881 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19882 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19883 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19884 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19885 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19886 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19887 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19888 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19891 DebugLoc dl = MI->getDebugLoc();
19892 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19894 unsigned NumArgs = MI->getNumOperands();
19895 for (unsigned i = 1; i < NumArgs; ++i) {
19896 MachineOperand &Op = MI->getOperand(i);
19897 if (!(Op.isReg() && Op.isImplicit()))
19898 MIB.addOperand(Op);
19900 if (MI->hasOneMemOperand())
19901 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19903 BuildMI(*BB, MI, dl,
19904 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19905 .addReg(X86::XMM0);
19907 MI->eraseFromParent();
19911 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19912 // defs in an instruction pattern
19913 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19914 const TargetInstrInfo *TII) {
19916 switch (MI->getOpcode()) {
19917 default: llvm_unreachable("illegal opcode!");
19918 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19919 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19920 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19921 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19922 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19923 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19924 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19925 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19928 DebugLoc dl = MI->getDebugLoc();
19929 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19931 unsigned NumArgs = MI->getNumOperands(); // remove the results
19932 for (unsigned i = 1; i < NumArgs; ++i) {
19933 MachineOperand &Op = MI->getOperand(i);
19934 if (!(Op.isReg() && Op.isImplicit()))
19935 MIB.addOperand(Op);
19937 if (MI->hasOneMemOperand())
19938 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19940 BuildMI(*BB, MI, dl,
19941 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19944 MI->eraseFromParent();
19948 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19949 const TargetInstrInfo *TII,
19950 const X86Subtarget* Subtarget) {
19951 DebugLoc dl = MI->getDebugLoc();
19953 // Address into RAX/EAX, other two args into ECX, EDX.
19954 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19955 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19956 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19957 for (int i = 0; i < X86::AddrNumOperands; ++i)
19958 MIB.addOperand(MI->getOperand(i));
19960 unsigned ValOps = X86::AddrNumOperands;
19961 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19962 .addReg(MI->getOperand(ValOps).getReg());
19963 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19964 .addReg(MI->getOperand(ValOps+1).getReg());
19966 // The instruction doesn't actually take any operands though.
19967 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19969 MI->eraseFromParent(); // The pseudo is gone now.
19973 MachineBasicBlock *
19974 X86TargetLowering::EmitVAARG64WithCustomInserter(
19976 MachineBasicBlock *MBB) const {
19977 // Emit va_arg instruction on X86-64.
19979 // Operands to this pseudo-instruction:
19980 // 0 ) Output : destination address (reg)
19981 // 1-5) Input : va_list address (addr, i64mem)
19982 // 6 ) ArgSize : Size (in bytes) of vararg type
19983 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19984 // 8 ) Align : Alignment of type
19985 // 9 ) EFLAGS (implicit-def)
19987 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19988 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19990 unsigned DestReg = MI->getOperand(0).getReg();
19991 MachineOperand &Base = MI->getOperand(1);
19992 MachineOperand &Scale = MI->getOperand(2);
19993 MachineOperand &Index = MI->getOperand(3);
19994 MachineOperand &Disp = MI->getOperand(4);
19995 MachineOperand &Segment = MI->getOperand(5);
19996 unsigned ArgSize = MI->getOperand(6).getImm();
19997 unsigned ArgMode = MI->getOperand(7).getImm();
19998 unsigned Align = MI->getOperand(8).getImm();
20000 // Memory Reference
20001 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20002 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20003 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20005 // Machine Information
20006 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20007 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20008 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20009 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20010 DebugLoc DL = MI->getDebugLoc();
20012 // struct va_list {
20015 // i64 overflow_area (address)
20016 // i64 reg_save_area (address)
20018 // sizeof(va_list) = 24
20019 // alignment(va_list) = 8
20021 unsigned TotalNumIntRegs = 6;
20022 unsigned TotalNumXMMRegs = 8;
20023 bool UseGPOffset = (ArgMode == 1);
20024 bool UseFPOffset = (ArgMode == 2);
20025 unsigned MaxOffset = TotalNumIntRegs * 8 +
20026 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20028 /* Align ArgSize to a multiple of 8 */
20029 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20030 bool NeedsAlign = (Align > 8);
20032 MachineBasicBlock *thisMBB = MBB;
20033 MachineBasicBlock *overflowMBB;
20034 MachineBasicBlock *offsetMBB;
20035 MachineBasicBlock *endMBB;
20037 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20038 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20039 unsigned OffsetReg = 0;
20041 if (!UseGPOffset && !UseFPOffset) {
20042 // If we only pull from the overflow region, we don't create a branch.
20043 // We don't need to alter control flow.
20044 OffsetDestReg = 0; // unused
20045 OverflowDestReg = DestReg;
20047 offsetMBB = nullptr;
20048 overflowMBB = thisMBB;
20051 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20052 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20053 // If not, pull from overflow_area. (branch to overflowMBB)
20058 // offsetMBB overflowMBB
20063 // Registers for the PHI in endMBB
20064 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20065 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20067 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20068 MachineFunction *MF = MBB->getParent();
20069 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20070 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20071 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20073 MachineFunction::iterator MBBIter = MBB;
20076 // Insert the new basic blocks
20077 MF->insert(MBBIter, offsetMBB);
20078 MF->insert(MBBIter, overflowMBB);
20079 MF->insert(MBBIter, endMBB);
20081 // Transfer the remainder of MBB and its successor edges to endMBB.
20082 endMBB->splice(endMBB->begin(), thisMBB,
20083 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20084 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20086 // Make offsetMBB and overflowMBB successors of thisMBB
20087 thisMBB->addSuccessor(offsetMBB);
20088 thisMBB->addSuccessor(overflowMBB);
20090 // endMBB is a successor of both offsetMBB and overflowMBB
20091 offsetMBB->addSuccessor(endMBB);
20092 overflowMBB->addSuccessor(endMBB);
20094 // Load the offset value into a register
20095 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20096 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20100 .addDisp(Disp, UseFPOffset ? 4 : 0)
20101 .addOperand(Segment)
20102 .setMemRefs(MMOBegin, MMOEnd);
20104 // Check if there is enough room left to pull this argument.
20105 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20107 .addImm(MaxOffset + 8 - ArgSizeA8);
20109 // Branch to "overflowMBB" if offset >= max
20110 // Fall through to "offsetMBB" otherwise
20111 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20112 .addMBB(overflowMBB);
20115 // In offsetMBB, emit code to use the reg_save_area.
20117 assert(OffsetReg != 0);
20119 // Read the reg_save_area address.
20120 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20121 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20126 .addOperand(Segment)
20127 .setMemRefs(MMOBegin, MMOEnd);
20129 // Zero-extend the offset
20130 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20131 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20134 .addImm(X86::sub_32bit);
20136 // Add the offset to the reg_save_area to get the final address.
20137 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20138 .addReg(OffsetReg64)
20139 .addReg(RegSaveReg);
20141 // Compute the offset for the next argument
20142 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20143 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20145 .addImm(UseFPOffset ? 16 : 8);
20147 // Store it back into the va_list.
20148 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20152 .addDisp(Disp, UseFPOffset ? 4 : 0)
20153 .addOperand(Segment)
20154 .addReg(NextOffsetReg)
20155 .setMemRefs(MMOBegin, MMOEnd);
20158 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20163 // Emit code to use overflow area
20166 // Load the overflow_area address into a register.
20167 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20168 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20173 .addOperand(Segment)
20174 .setMemRefs(MMOBegin, MMOEnd);
20176 // If we need to align it, do so. Otherwise, just copy the address
20177 // to OverflowDestReg.
20179 // Align the overflow address
20180 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20181 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20183 // aligned_addr = (addr + (align-1)) & ~(align-1)
20184 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20185 .addReg(OverflowAddrReg)
20188 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20190 .addImm(~(uint64_t)(Align-1));
20192 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20193 .addReg(OverflowAddrReg);
20196 // Compute the next overflow address after this argument.
20197 // (the overflow address should be kept 8-byte aligned)
20198 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20199 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20200 .addReg(OverflowDestReg)
20201 .addImm(ArgSizeA8);
20203 // Store the new overflow address.
20204 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20209 .addOperand(Segment)
20210 .addReg(NextAddrReg)
20211 .setMemRefs(MMOBegin, MMOEnd);
20213 // If we branched, emit the PHI to the front of endMBB.
20215 BuildMI(*endMBB, endMBB->begin(), DL,
20216 TII->get(X86::PHI), DestReg)
20217 .addReg(OffsetDestReg).addMBB(offsetMBB)
20218 .addReg(OverflowDestReg).addMBB(overflowMBB);
20221 // Erase the pseudo instruction
20222 MI->eraseFromParent();
20227 MachineBasicBlock *
20228 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20230 MachineBasicBlock *MBB) const {
20231 // Emit code to save XMM registers to the stack. The ABI says that the
20232 // number of registers to save is given in %al, so it's theoretically
20233 // possible to do an indirect jump trick to avoid saving all of them,
20234 // however this code takes a simpler approach and just executes all
20235 // of the stores if %al is non-zero. It's less code, and it's probably
20236 // easier on the hardware branch predictor, and stores aren't all that
20237 // expensive anyway.
20239 // Create the new basic blocks. One block contains all the XMM stores,
20240 // and one block is the final destination regardless of whether any
20241 // stores were performed.
20242 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20243 MachineFunction *F = MBB->getParent();
20244 MachineFunction::iterator MBBIter = MBB;
20246 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20247 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20248 F->insert(MBBIter, XMMSaveMBB);
20249 F->insert(MBBIter, EndMBB);
20251 // Transfer the remainder of MBB and its successor edges to EndMBB.
20252 EndMBB->splice(EndMBB->begin(), MBB,
20253 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20254 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20256 // The original block will now fall through to the XMM save block.
20257 MBB->addSuccessor(XMMSaveMBB);
20258 // The XMMSaveMBB will fall through to the end block.
20259 XMMSaveMBB->addSuccessor(EndMBB);
20261 // Now add the instructions.
20262 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20263 DebugLoc DL = MI->getDebugLoc();
20265 unsigned CountReg = MI->getOperand(0).getReg();
20266 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20267 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20269 if (!Subtarget->isTargetWin64()) {
20270 // If %al is 0, branch around the XMM save block.
20271 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20272 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20273 MBB->addSuccessor(EndMBB);
20276 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20277 // that was just emitted, but clearly shouldn't be "saved".
20278 assert((MI->getNumOperands() <= 3 ||
20279 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20280 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20281 && "Expected last argument to be EFLAGS");
20282 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20283 // In the XMM save block, save all the XMM argument registers.
20284 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20285 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20286 MachineMemOperand *MMO =
20287 F->getMachineMemOperand(
20288 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20289 MachineMemOperand::MOStore,
20290 /*Size=*/16, /*Align=*/16);
20291 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20292 .addFrameIndex(RegSaveFrameIndex)
20293 .addImm(/*Scale=*/1)
20294 .addReg(/*IndexReg=*/0)
20295 .addImm(/*Disp=*/Offset)
20296 .addReg(/*Segment=*/0)
20297 .addReg(MI->getOperand(i).getReg())
20298 .addMemOperand(MMO);
20301 MI->eraseFromParent(); // The pseudo instruction is gone now.
20306 // The EFLAGS operand of SelectItr might be missing a kill marker
20307 // because there were multiple uses of EFLAGS, and ISel didn't know
20308 // which to mark. Figure out whether SelectItr should have had a
20309 // kill marker, and set it if it should. Returns the correct kill
20311 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20312 MachineBasicBlock* BB,
20313 const TargetRegisterInfo* TRI) {
20314 // Scan forward through BB for a use/def of EFLAGS.
20315 MachineBasicBlock::iterator miI(std::next(SelectItr));
20316 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20317 const MachineInstr& mi = *miI;
20318 if (mi.readsRegister(X86::EFLAGS))
20320 if (mi.definesRegister(X86::EFLAGS))
20321 break; // Should have kill-flag - update below.
20324 // If we hit the end of the block, check whether EFLAGS is live into a
20326 if (miI == BB->end()) {
20327 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20328 sEnd = BB->succ_end();
20329 sItr != sEnd; ++sItr) {
20330 MachineBasicBlock* succ = *sItr;
20331 if (succ->isLiveIn(X86::EFLAGS))
20336 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20337 // out. SelectMI should have a kill flag on EFLAGS.
20338 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20342 MachineBasicBlock *
20343 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20344 MachineBasicBlock *BB) const {
20345 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20346 DebugLoc DL = MI->getDebugLoc();
20348 // To "insert" a SELECT_CC instruction, we actually have to insert the
20349 // diamond control-flow pattern. The incoming instruction knows the
20350 // destination vreg to set, the condition code register to branch on, the
20351 // true/false values to select between, and a branch opcode to use.
20352 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20353 MachineFunction::iterator It = BB;
20359 // cmpTY ccX, r1, r2
20361 // fallthrough --> copy0MBB
20362 MachineBasicBlock *thisMBB = BB;
20363 MachineFunction *F = BB->getParent();
20364 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20365 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20366 F->insert(It, copy0MBB);
20367 F->insert(It, sinkMBB);
20369 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20370 // live into the sink and copy blocks.
20371 const TargetRegisterInfo *TRI =
20372 BB->getParent()->getSubtarget().getRegisterInfo();
20373 if (!MI->killsRegister(X86::EFLAGS) &&
20374 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20375 copy0MBB->addLiveIn(X86::EFLAGS);
20376 sinkMBB->addLiveIn(X86::EFLAGS);
20379 // Transfer the remainder of BB and its successor edges to sinkMBB.
20380 sinkMBB->splice(sinkMBB->begin(), BB,
20381 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20382 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20384 // Add the true and fallthrough blocks as its successors.
20385 BB->addSuccessor(copy0MBB);
20386 BB->addSuccessor(sinkMBB);
20388 // Create the conditional branch instruction.
20390 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20391 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20394 // %FalseValue = ...
20395 // # fallthrough to sinkMBB
20396 copy0MBB->addSuccessor(sinkMBB);
20399 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20401 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20402 TII->get(X86::PHI), MI->getOperand(0).getReg())
20403 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20404 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20406 MI->eraseFromParent(); // The pseudo instruction is gone now.
20410 MachineBasicBlock *
20411 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20412 MachineBasicBlock *BB) const {
20413 MachineFunction *MF = BB->getParent();
20414 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20415 DebugLoc DL = MI->getDebugLoc();
20416 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20418 assert(MF->shouldSplitStack());
20420 const bool Is64Bit = Subtarget->is64Bit();
20421 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20423 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20424 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20427 // ... [Till the alloca]
20428 // If stacklet is not large enough, jump to mallocMBB
20431 // Allocate by subtracting from RSP
20432 // Jump to continueMBB
20435 // Allocate by call to runtime
20439 // [rest of original BB]
20442 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20443 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20444 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20446 MachineRegisterInfo &MRI = MF->getRegInfo();
20447 const TargetRegisterClass *AddrRegClass =
20448 getRegClassFor(getPointerTy());
20450 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20451 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20452 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20453 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20454 sizeVReg = MI->getOperand(1).getReg(),
20455 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20457 MachineFunction::iterator MBBIter = BB;
20460 MF->insert(MBBIter, bumpMBB);
20461 MF->insert(MBBIter, mallocMBB);
20462 MF->insert(MBBIter, continueMBB);
20464 continueMBB->splice(continueMBB->begin(), BB,
20465 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20466 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20468 // Add code to the main basic block to check if the stack limit has been hit,
20469 // and if so, jump to mallocMBB otherwise to bumpMBB.
20470 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20471 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20472 .addReg(tmpSPVReg).addReg(sizeVReg);
20473 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20474 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20475 .addReg(SPLimitVReg);
20476 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20478 // bumpMBB simply decreases the stack pointer, since we know the current
20479 // stacklet has enough space.
20480 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20481 .addReg(SPLimitVReg);
20482 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20483 .addReg(SPLimitVReg);
20484 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20486 // Calls into a routine in libgcc to allocate more space from the heap.
20487 const uint32_t *RegMask = MF->getTarget()
20488 .getSubtargetImpl()
20489 ->getRegisterInfo()
20490 ->getCallPreservedMask(CallingConv::C);
20492 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20494 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20495 .addExternalSymbol("__morestack_allocate_stack_space")
20496 .addRegMask(RegMask)
20497 .addReg(X86::RDI, RegState::Implicit)
20498 .addReg(X86::RAX, RegState::ImplicitDefine);
20499 } else if (Is64Bit) {
20500 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20502 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20503 .addExternalSymbol("__morestack_allocate_stack_space")
20504 .addRegMask(RegMask)
20505 .addReg(X86::EDI, RegState::Implicit)
20506 .addReg(X86::EAX, RegState::ImplicitDefine);
20508 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20510 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20511 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20512 .addExternalSymbol("__morestack_allocate_stack_space")
20513 .addRegMask(RegMask)
20514 .addReg(X86::EAX, RegState::ImplicitDefine);
20518 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20521 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20522 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20523 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20525 // Set up the CFG correctly.
20526 BB->addSuccessor(bumpMBB);
20527 BB->addSuccessor(mallocMBB);
20528 mallocMBB->addSuccessor(continueMBB);
20529 bumpMBB->addSuccessor(continueMBB);
20531 // Take care of the PHI nodes.
20532 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20533 MI->getOperand(0).getReg())
20534 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20535 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20537 // Delete the original pseudo instruction.
20538 MI->eraseFromParent();
20541 return continueMBB;
20544 MachineBasicBlock *
20545 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20546 MachineBasicBlock *BB) const {
20547 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20548 DebugLoc DL = MI->getDebugLoc();
20550 assert(!Subtarget->isTargetMacho());
20552 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20553 // non-trivial part is impdef of ESP.
20555 if (Subtarget->isTargetWin64()) {
20556 if (Subtarget->isTargetCygMing()) {
20557 // ___chkstk(Mingw64):
20558 // Clobbers R10, R11, RAX and EFLAGS.
20560 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20561 .addExternalSymbol("___chkstk")
20562 .addReg(X86::RAX, RegState::Implicit)
20563 .addReg(X86::RSP, RegState::Implicit)
20564 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20565 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20566 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20568 // __chkstk(MSVCRT): does not update stack pointer.
20569 // Clobbers R10, R11 and EFLAGS.
20570 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20571 .addExternalSymbol("__chkstk")
20572 .addReg(X86::RAX, RegState::Implicit)
20573 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20574 // RAX has the offset to be subtracted from RSP.
20575 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20580 const char *StackProbeSymbol =
20581 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
20583 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20584 .addExternalSymbol(StackProbeSymbol)
20585 .addReg(X86::EAX, RegState::Implicit)
20586 .addReg(X86::ESP, RegState::Implicit)
20587 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20588 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20589 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20592 MI->eraseFromParent(); // The pseudo instruction is gone now.
20596 MachineBasicBlock *
20597 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20598 MachineBasicBlock *BB) const {
20599 // This is pretty easy. We're taking the value that we received from
20600 // our load from the relocation, sticking it in either RDI (x86-64)
20601 // or EAX and doing an indirect call. The return value will then
20602 // be in the normal return register.
20603 MachineFunction *F = BB->getParent();
20604 const X86InstrInfo *TII =
20605 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20606 DebugLoc DL = MI->getDebugLoc();
20608 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20609 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20611 // Get a register mask for the lowered call.
20612 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20613 // proper register mask.
20614 const uint32_t *RegMask = F->getTarget()
20615 .getSubtargetImpl()
20616 ->getRegisterInfo()
20617 ->getCallPreservedMask(CallingConv::C);
20618 if (Subtarget->is64Bit()) {
20619 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20620 TII->get(X86::MOV64rm), X86::RDI)
20622 .addImm(0).addReg(0)
20623 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20624 MI->getOperand(3).getTargetFlags())
20626 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20627 addDirectMem(MIB, X86::RDI);
20628 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20629 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20630 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20631 TII->get(X86::MOV32rm), X86::EAX)
20633 .addImm(0).addReg(0)
20634 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20635 MI->getOperand(3).getTargetFlags())
20637 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20638 addDirectMem(MIB, X86::EAX);
20639 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20641 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20642 TII->get(X86::MOV32rm), X86::EAX)
20643 .addReg(TII->getGlobalBaseReg(F))
20644 .addImm(0).addReg(0)
20645 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20646 MI->getOperand(3).getTargetFlags())
20648 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20649 addDirectMem(MIB, X86::EAX);
20650 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20653 MI->eraseFromParent(); // The pseudo instruction is gone now.
20657 MachineBasicBlock *
20658 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20659 MachineBasicBlock *MBB) const {
20660 DebugLoc DL = MI->getDebugLoc();
20661 MachineFunction *MF = MBB->getParent();
20662 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20663 MachineRegisterInfo &MRI = MF->getRegInfo();
20665 const BasicBlock *BB = MBB->getBasicBlock();
20666 MachineFunction::iterator I = MBB;
20669 // Memory Reference
20670 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20671 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20674 unsigned MemOpndSlot = 0;
20676 unsigned CurOp = 0;
20678 DstReg = MI->getOperand(CurOp++).getReg();
20679 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20680 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20681 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20682 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20684 MemOpndSlot = CurOp;
20686 MVT PVT = getPointerTy();
20687 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20688 "Invalid Pointer Size!");
20690 // For v = setjmp(buf), we generate
20693 // buf[LabelOffset] = restoreMBB
20694 // SjLjSetup restoreMBB
20700 // v = phi(main, restore)
20705 MachineBasicBlock *thisMBB = MBB;
20706 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20707 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20708 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20709 MF->insert(I, mainMBB);
20710 MF->insert(I, sinkMBB);
20711 MF->push_back(restoreMBB);
20713 MachineInstrBuilder MIB;
20715 // Transfer the remainder of BB and its successor edges to sinkMBB.
20716 sinkMBB->splice(sinkMBB->begin(), MBB,
20717 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20718 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20721 unsigned PtrStoreOpc = 0;
20722 unsigned LabelReg = 0;
20723 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20724 Reloc::Model RM = MF->getTarget().getRelocationModel();
20725 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20726 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20728 // Prepare IP either in reg or imm.
20729 if (!UseImmLabel) {
20730 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20731 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20732 LabelReg = MRI.createVirtualRegister(PtrRC);
20733 if (Subtarget->is64Bit()) {
20734 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20738 .addMBB(restoreMBB)
20741 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20742 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20743 .addReg(XII->getGlobalBaseReg(MF))
20746 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20750 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20752 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20753 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20754 if (i == X86::AddrDisp)
20755 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20757 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20760 MIB.addReg(LabelReg);
20762 MIB.addMBB(restoreMBB);
20763 MIB.setMemRefs(MMOBegin, MMOEnd);
20765 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20766 .addMBB(restoreMBB);
20768 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20769 MF->getSubtarget().getRegisterInfo());
20770 MIB.addRegMask(RegInfo->getNoPreservedMask());
20771 thisMBB->addSuccessor(mainMBB);
20772 thisMBB->addSuccessor(restoreMBB);
20776 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20777 mainMBB->addSuccessor(sinkMBB);
20780 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20781 TII->get(X86::PHI), DstReg)
20782 .addReg(mainDstReg).addMBB(mainMBB)
20783 .addReg(restoreDstReg).addMBB(restoreMBB);
20786 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20787 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20788 restoreMBB->addSuccessor(sinkMBB);
20790 MI->eraseFromParent();
20794 MachineBasicBlock *
20795 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20796 MachineBasicBlock *MBB) const {
20797 DebugLoc DL = MI->getDebugLoc();
20798 MachineFunction *MF = MBB->getParent();
20799 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20800 MachineRegisterInfo &MRI = MF->getRegInfo();
20802 // Memory Reference
20803 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20804 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20806 MVT PVT = getPointerTy();
20807 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20808 "Invalid Pointer Size!");
20810 const TargetRegisterClass *RC =
20811 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20812 unsigned Tmp = MRI.createVirtualRegister(RC);
20813 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20814 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20815 MF->getSubtarget().getRegisterInfo());
20816 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20817 unsigned SP = RegInfo->getStackRegister();
20819 MachineInstrBuilder MIB;
20821 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20822 const int64_t SPOffset = 2 * PVT.getStoreSize();
20824 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20825 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20828 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20829 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20830 MIB.addOperand(MI->getOperand(i));
20831 MIB.setMemRefs(MMOBegin, MMOEnd);
20833 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20834 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20835 if (i == X86::AddrDisp)
20836 MIB.addDisp(MI->getOperand(i), LabelOffset);
20838 MIB.addOperand(MI->getOperand(i));
20840 MIB.setMemRefs(MMOBegin, MMOEnd);
20842 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20843 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20844 if (i == X86::AddrDisp)
20845 MIB.addDisp(MI->getOperand(i), SPOffset);
20847 MIB.addOperand(MI->getOperand(i));
20849 MIB.setMemRefs(MMOBegin, MMOEnd);
20851 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20853 MI->eraseFromParent();
20857 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20858 // accumulator loops. Writing back to the accumulator allows the coalescer
20859 // to remove extra copies in the loop.
20860 MachineBasicBlock *
20861 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20862 MachineBasicBlock *MBB) const {
20863 MachineOperand &AddendOp = MI->getOperand(3);
20865 // Bail out early if the addend isn't a register - we can't switch these.
20866 if (!AddendOp.isReg())
20869 MachineFunction &MF = *MBB->getParent();
20870 MachineRegisterInfo &MRI = MF.getRegInfo();
20872 // Check whether the addend is defined by a PHI:
20873 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20874 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20875 if (!AddendDef.isPHI())
20878 // Look for the following pattern:
20880 // %addend = phi [%entry, 0], [%loop, %result]
20882 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20886 // %addend = phi [%entry, 0], [%loop, %result]
20888 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20890 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20891 assert(AddendDef.getOperand(i).isReg());
20892 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20893 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20894 if (&PHISrcInst == MI) {
20895 // Found a matching instruction.
20896 unsigned NewFMAOpc = 0;
20897 switch (MI->getOpcode()) {
20898 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20899 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20900 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20901 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20902 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20903 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20904 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20905 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20906 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20907 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20908 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20909 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20910 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20911 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20912 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20913 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20914 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20915 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20916 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20917 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20919 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20920 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20921 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20922 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20923 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20924 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20925 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20926 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20927 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20928 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20929 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20930 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20931 default: llvm_unreachable("Unrecognized FMA variant.");
20934 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20935 MachineInstrBuilder MIB =
20936 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20937 .addOperand(MI->getOperand(0))
20938 .addOperand(MI->getOperand(3))
20939 .addOperand(MI->getOperand(2))
20940 .addOperand(MI->getOperand(1));
20941 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20942 MI->eraseFromParent();
20949 MachineBasicBlock *
20950 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20951 MachineBasicBlock *BB) const {
20952 switch (MI->getOpcode()) {
20953 default: llvm_unreachable("Unexpected instr type to insert");
20954 case X86::TAILJMPd64:
20955 case X86::TAILJMPr64:
20956 case X86::TAILJMPm64:
20957 llvm_unreachable("TAILJMP64 would not be touched here.");
20958 case X86::TCRETURNdi64:
20959 case X86::TCRETURNri64:
20960 case X86::TCRETURNmi64:
20962 case X86::WIN_ALLOCA:
20963 return EmitLoweredWinAlloca(MI, BB);
20964 case X86::SEG_ALLOCA_32:
20965 case X86::SEG_ALLOCA_64:
20966 return EmitLoweredSegAlloca(MI, BB);
20967 case X86::TLSCall_32:
20968 case X86::TLSCall_64:
20969 return EmitLoweredTLSCall(MI, BB);
20970 case X86::CMOV_GR8:
20971 case X86::CMOV_FR32:
20972 case X86::CMOV_FR64:
20973 case X86::CMOV_V4F32:
20974 case X86::CMOV_V2F64:
20975 case X86::CMOV_V2I64:
20976 case X86::CMOV_V8F32:
20977 case X86::CMOV_V4F64:
20978 case X86::CMOV_V4I64:
20979 case X86::CMOV_V16F32:
20980 case X86::CMOV_V8F64:
20981 case X86::CMOV_V8I64:
20982 case X86::CMOV_GR16:
20983 case X86::CMOV_GR32:
20984 case X86::CMOV_RFP32:
20985 case X86::CMOV_RFP64:
20986 case X86::CMOV_RFP80:
20987 return EmitLoweredSelect(MI, BB);
20989 case X86::FP32_TO_INT16_IN_MEM:
20990 case X86::FP32_TO_INT32_IN_MEM:
20991 case X86::FP32_TO_INT64_IN_MEM:
20992 case X86::FP64_TO_INT16_IN_MEM:
20993 case X86::FP64_TO_INT32_IN_MEM:
20994 case X86::FP64_TO_INT64_IN_MEM:
20995 case X86::FP80_TO_INT16_IN_MEM:
20996 case X86::FP80_TO_INT32_IN_MEM:
20997 case X86::FP80_TO_INT64_IN_MEM: {
20998 MachineFunction *F = BB->getParent();
20999 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21000 DebugLoc DL = MI->getDebugLoc();
21002 // Change the floating point control register to use "round towards zero"
21003 // mode when truncating to an integer value.
21004 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21005 addFrameReference(BuildMI(*BB, MI, DL,
21006 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21008 // Load the old value of the high byte of the control word...
21010 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21011 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21014 // Set the high part to be round to zero...
21015 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21018 // Reload the modified control word now...
21019 addFrameReference(BuildMI(*BB, MI, DL,
21020 TII->get(X86::FLDCW16m)), CWFrameIdx);
21022 // Restore the memory image of control word to original value
21023 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21026 // Get the X86 opcode to use.
21028 switch (MI->getOpcode()) {
21029 default: llvm_unreachable("illegal opcode!");
21030 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21031 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21032 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21033 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21034 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21035 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21036 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21037 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21038 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21042 MachineOperand &Op = MI->getOperand(0);
21044 AM.BaseType = X86AddressMode::RegBase;
21045 AM.Base.Reg = Op.getReg();
21047 AM.BaseType = X86AddressMode::FrameIndexBase;
21048 AM.Base.FrameIndex = Op.getIndex();
21050 Op = MI->getOperand(1);
21052 AM.Scale = Op.getImm();
21053 Op = MI->getOperand(2);
21055 AM.IndexReg = Op.getImm();
21056 Op = MI->getOperand(3);
21057 if (Op.isGlobal()) {
21058 AM.GV = Op.getGlobal();
21060 AM.Disp = Op.getImm();
21062 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21063 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21065 // Reload the original control word now.
21066 addFrameReference(BuildMI(*BB, MI, DL,
21067 TII->get(X86::FLDCW16m)), CWFrameIdx);
21069 MI->eraseFromParent(); // The pseudo instruction is gone now.
21072 // String/text processing lowering.
21073 case X86::PCMPISTRM128REG:
21074 case X86::VPCMPISTRM128REG:
21075 case X86::PCMPISTRM128MEM:
21076 case X86::VPCMPISTRM128MEM:
21077 case X86::PCMPESTRM128REG:
21078 case X86::VPCMPESTRM128REG:
21079 case X86::PCMPESTRM128MEM:
21080 case X86::VPCMPESTRM128MEM:
21081 assert(Subtarget->hasSSE42() &&
21082 "Target must have SSE4.2 or AVX features enabled");
21083 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21085 // String/text processing lowering.
21086 case X86::PCMPISTRIREG:
21087 case X86::VPCMPISTRIREG:
21088 case X86::PCMPISTRIMEM:
21089 case X86::VPCMPISTRIMEM:
21090 case X86::PCMPESTRIREG:
21091 case X86::VPCMPESTRIREG:
21092 case X86::PCMPESTRIMEM:
21093 case X86::VPCMPESTRIMEM:
21094 assert(Subtarget->hasSSE42() &&
21095 "Target must have SSE4.2 or AVX features enabled");
21096 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21098 // Thread synchronization.
21100 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21105 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21107 case X86::VASTART_SAVE_XMM_REGS:
21108 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21110 case X86::VAARG_64:
21111 return EmitVAARG64WithCustomInserter(MI, BB);
21113 case X86::EH_SjLj_SetJmp32:
21114 case X86::EH_SjLj_SetJmp64:
21115 return emitEHSjLjSetJmp(MI, BB);
21117 case X86::EH_SjLj_LongJmp32:
21118 case X86::EH_SjLj_LongJmp64:
21119 return emitEHSjLjLongJmp(MI, BB);
21121 case TargetOpcode::STACKMAP:
21122 case TargetOpcode::PATCHPOINT:
21123 return emitPatchPoint(MI, BB);
21125 case X86::VFMADDPDr213r:
21126 case X86::VFMADDPSr213r:
21127 case X86::VFMADDSDr213r:
21128 case X86::VFMADDSSr213r:
21129 case X86::VFMSUBPDr213r:
21130 case X86::VFMSUBPSr213r:
21131 case X86::VFMSUBSDr213r:
21132 case X86::VFMSUBSSr213r:
21133 case X86::VFNMADDPDr213r:
21134 case X86::VFNMADDPSr213r:
21135 case X86::VFNMADDSDr213r:
21136 case X86::VFNMADDSSr213r:
21137 case X86::VFNMSUBPDr213r:
21138 case X86::VFNMSUBPSr213r:
21139 case X86::VFNMSUBSDr213r:
21140 case X86::VFNMSUBSSr213r:
21141 case X86::VFMADDSUBPDr213r:
21142 case X86::VFMADDSUBPSr213r:
21143 case X86::VFMSUBADDPDr213r:
21144 case X86::VFMSUBADDPSr213r:
21145 case X86::VFMADDPDr213rY:
21146 case X86::VFMADDPSr213rY:
21147 case X86::VFMSUBPDr213rY:
21148 case X86::VFMSUBPSr213rY:
21149 case X86::VFNMADDPDr213rY:
21150 case X86::VFNMADDPSr213rY:
21151 case X86::VFNMSUBPDr213rY:
21152 case X86::VFNMSUBPSr213rY:
21153 case X86::VFMADDSUBPDr213rY:
21154 case X86::VFMADDSUBPSr213rY:
21155 case X86::VFMSUBADDPDr213rY:
21156 case X86::VFMSUBADDPSr213rY:
21157 return emitFMA3Instr(MI, BB);
21161 //===----------------------------------------------------------------------===//
21162 // X86 Optimization Hooks
21163 //===----------------------------------------------------------------------===//
21165 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21168 const SelectionDAG &DAG,
21169 unsigned Depth) const {
21170 unsigned BitWidth = KnownZero.getBitWidth();
21171 unsigned Opc = Op.getOpcode();
21172 assert((Opc >= ISD::BUILTIN_OP_END ||
21173 Opc == ISD::INTRINSIC_WO_CHAIN ||
21174 Opc == ISD::INTRINSIC_W_CHAIN ||
21175 Opc == ISD::INTRINSIC_VOID) &&
21176 "Should use MaskedValueIsZero if you don't know whether Op"
21177 " is a target node!");
21179 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21193 // These nodes' second result is a boolean.
21194 if (Op.getResNo() == 0)
21197 case X86ISD::SETCC:
21198 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21200 case ISD::INTRINSIC_WO_CHAIN: {
21201 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21202 unsigned NumLoBits = 0;
21205 case Intrinsic::x86_sse_movmsk_ps:
21206 case Intrinsic::x86_avx_movmsk_ps_256:
21207 case Intrinsic::x86_sse2_movmsk_pd:
21208 case Intrinsic::x86_avx_movmsk_pd_256:
21209 case Intrinsic::x86_mmx_pmovmskb:
21210 case Intrinsic::x86_sse2_pmovmskb_128:
21211 case Intrinsic::x86_avx2_pmovmskb: {
21212 // High bits of movmskp{s|d}, pmovmskb are known zero.
21214 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21215 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21216 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21217 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21218 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21219 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21220 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21221 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21223 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21232 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21234 const SelectionDAG &,
21235 unsigned Depth) const {
21236 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21237 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21238 return Op.getValueType().getScalarType().getSizeInBits();
21244 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21245 /// node is a GlobalAddress + offset.
21246 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21247 const GlobalValue* &GA,
21248 int64_t &Offset) const {
21249 if (N->getOpcode() == X86ISD::Wrapper) {
21250 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21251 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21252 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21256 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21259 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21260 /// same as extracting the high 128-bit part of 256-bit vector and then
21261 /// inserting the result into the low part of a new 256-bit vector
21262 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21263 EVT VT = SVOp->getValueType(0);
21264 unsigned NumElems = VT.getVectorNumElements();
21266 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21267 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21268 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21269 SVOp->getMaskElt(j) >= 0)
21275 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21276 /// same as extracting the low 128-bit part of 256-bit vector and then
21277 /// inserting the result into the high part of a new 256-bit vector
21278 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21279 EVT VT = SVOp->getValueType(0);
21280 unsigned NumElems = VT.getVectorNumElements();
21282 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21283 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21284 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21285 SVOp->getMaskElt(j) >= 0)
21291 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21292 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21293 TargetLowering::DAGCombinerInfo &DCI,
21294 const X86Subtarget* Subtarget) {
21296 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21297 SDValue V1 = SVOp->getOperand(0);
21298 SDValue V2 = SVOp->getOperand(1);
21299 EVT VT = SVOp->getValueType(0);
21300 unsigned NumElems = VT.getVectorNumElements();
21302 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21303 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21307 // V UNDEF BUILD_VECTOR UNDEF
21309 // CONCAT_VECTOR CONCAT_VECTOR
21312 // RESULT: V + zero extended
21314 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21315 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21316 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21319 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21322 // To match the shuffle mask, the first half of the mask should
21323 // be exactly the first vector, and all the rest a splat with the
21324 // first element of the second one.
21325 for (unsigned i = 0; i != NumElems/2; ++i)
21326 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21327 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21330 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21331 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21332 if (Ld->hasNUsesOfValue(1, 0)) {
21333 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21334 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21336 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21338 Ld->getPointerInfo(),
21339 Ld->getAlignment(),
21340 false/*isVolatile*/, true/*ReadMem*/,
21341 false/*WriteMem*/);
21343 // Make sure the newly-created LOAD is in the same position as Ld in
21344 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21345 // and update uses of Ld's output chain to use the TokenFactor.
21346 if (Ld->hasAnyUseOfValue(1)) {
21347 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21348 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21349 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21350 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21351 SDValue(ResNode.getNode(), 1));
21354 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21358 // Emit a zeroed vector and insert the desired subvector on its
21360 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21361 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21362 return DCI.CombineTo(N, InsV);
21365 //===--------------------------------------------------------------------===//
21366 // Combine some shuffles into subvector extracts and inserts:
21369 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21370 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21371 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21372 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21373 return DCI.CombineTo(N, InsV);
21376 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21377 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21378 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21379 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21380 return DCI.CombineTo(N, InsV);
21386 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21389 /// This is the leaf of the recursive combinine below. When we have found some
21390 /// chain of single-use x86 shuffle instructions and accumulated the combined
21391 /// shuffle mask represented by them, this will try to pattern match that mask
21392 /// into either a single instruction if there is a special purpose instruction
21393 /// for this operation, or into a PSHUFB instruction which is a fully general
21394 /// instruction but should only be used to replace chains over a certain depth.
21395 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21396 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21397 TargetLowering::DAGCombinerInfo &DCI,
21398 const X86Subtarget *Subtarget) {
21399 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21401 // Find the operand that enters the chain. Note that multiple uses are OK
21402 // here, we're not going to remove the operand we find.
21403 SDValue Input = Op.getOperand(0);
21404 while (Input.getOpcode() == ISD::BITCAST)
21405 Input = Input.getOperand(0);
21407 MVT VT = Input.getSimpleValueType();
21408 MVT RootVT = Root.getSimpleValueType();
21411 // Just remove no-op shuffle masks.
21412 if (Mask.size() == 1) {
21413 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21418 // Use the float domain if the operand type is a floating point type.
21419 bool FloatDomain = VT.isFloatingPoint();
21421 // For floating point shuffles, we don't have free copies in the shuffle
21422 // instructions or the ability to load as part of the instruction, so
21423 // canonicalize their shuffles to UNPCK or MOV variants.
21425 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21426 // vectors because it can have a load folded into it that UNPCK cannot. This
21427 // doesn't preclude something switching to the shorter encoding post-RA.
21429 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21430 bool Lo = Mask.equals(0, 0);
21433 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21434 // is no slower than UNPCKLPD but has the option to fold the input operand
21435 // into even an unaligned memory load.
21436 if (Lo && Subtarget->hasSSE3()) {
21437 Shuffle = X86ISD::MOVDDUP;
21438 ShuffleVT = MVT::v2f64;
21440 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21441 // than the UNPCK variants.
21442 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21443 ShuffleVT = MVT::v4f32;
21445 if (Depth == 1 && Root->getOpcode() == Shuffle)
21446 return false; // Nothing to do!
21447 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21448 DCI.AddToWorklist(Op.getNode());
21449 if (Shuffle == X86ISD::MOVDDUP)
21450 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21452 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21453 DCI.AddToWorklist(Op.getNode());
21454 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21458 if (Subtarget->hasSSE3() &&
21459 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21460 bool Lo = Mask.equals(0, 0, 2, 2);
21461 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21462 MVT ShuffleVT = MVT::v4f32;
21463 if (Depth == 1 && Root->getOpcode() == Shuffle)
21464 return false; // Nothing to do!
21465 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21466 DCI.AddToWorklist(Op.getNode());
21467 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21468 DCI.AddToWorklist(Op.getNode());
21469 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21473 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21474 bool Lo = Mask.equals(0, 0, 1, 1);
21475 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21476 MVT ShuffleVT = MVT::v4f32;
21477 if (Depth == 1 && Root->getOpcode() == Shuffle)
21478 return false; // Nothing to do!
21479 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21480 DCI.AddToWorklist(Op.getNode());
21481 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21482 DCI.AddToWorklist(Op.getNode());
21483 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21489 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21490 // variants as none of these have single-instruction variants that are
21491 // superior to the UNPCK formulation.
21492 if (!FloatDomain &&
21493 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21494 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21495 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21496 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21498 bool Lo = Mask[0] == 0;
21499 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21500 if (Depth == 1 && Root->getOpcode() == Shuffle)
21501 return false; // Nothing to do!
21503 switch (Mask.size()) {
21505 ShuffleVT = MVT::v8i16;
21508 ShuffleVT = MVT::v16i8;
21511 llvm_unreachable("Impossible mask size!");
21513 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21514 DCI.AddToWorklist(Op.getNode());
21515 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21516 DCI.AddToWorklist(Op.getNode());
21517 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21522 // Don't try to re-form single instruction chains under any circumstances now
21523 // that we've done encoding canonicalization for them.
21527 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21528 // can replace them with a single PSHUFB instruction profitably. Intel's
21529 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21530 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21531 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21532 SmallVector<SDValue, 16> PSHUFBMask;
21533 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21534 int Ratio = 16 / Mask.size();
21535 for (unsigned i = 0; i < 16; ++i) {
21536 if (Mask[i / Ratio] == SM_SentinelUndef) {
21537 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21540 int M = Mask[i / Ratio] != SM_SentinelZero
21541 ? Ratio * Mask[i / Ratio] + i % Ratio
21543 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21545 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21546 DCI.AddToWorklist(Op.getNode());
21547 SDValue PSHUFBMaskOp =
21548 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21549 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21550 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21551 DCI.AddToWorklist(Op.getNode());
21552 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21557 // Failed to find any combines.
21561 /// \brief Fully generic combining of x86 shuffle instructions.
21563 /// This should be the last combine run over the x86 shuffle instructions. Once
21564 /// they have been fully optimized, this will recursively consider all chains
21565 /// of single-use shuffle instructions, build a generic model of the cumulative
21566 /// shuffle operation, and check for simpler instructions which implement this
21567 /// operation. We use this primarily for two purposes:
21569 /// 1) Collapse generic shuffles to specialized single instructions when
21570 /// equivalent. In most cases, this is just an encoding size win, but
21571 /// sometimes we will collapse multiple generic shuffles into a single
21572 /// special-purpose shuffle.
21573 /// 2) Look for sequences of shuffle instructions with 3 or more total
21574 /// instructions, and replace them with the slightly more expensive SSSE3
21575 /// PSHUFB instruction if available. We do this as the last combining step
21576 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21577 /// a suitable short sequence of other instructions. The PHUFB will either
21578 /// use a register or have to read from memory and so is slightly (but only
21579 /// slightly) more expensive than the other shuffle instructions.
21581 /// Because this is inherently a quadratic operation (for each shuffle in
21582 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21583 /// This should never be an issue in practice as the shuffle lowering doesn't
21584 /// produce sequences of more than 8 instructions.
21586 /// FIXME: We will currently miss some cases where the redundant shuffling
21587 /// would simplify under the threshold for PSHUFB formation because of
21588 /// combine-ordering. To fix this, we should do the redundant instruction
21589 /// combining in this recursive walk.
21590 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21591 ArrayRef<int> RootMask,
21592 int Depth, bool HasPSHUFB,
21594 TargetLowering::DAGCombinerInfo &DCI,
21595 const X86Subtarget *Subtarget) {
21596 // Bound the depth of our recursive combine because this is ultimately
21597 // quadratic in nature.
21601 // Directly rip through bitcasts to find the underlying operand.
21602 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21603 Op = Op.getOperand(0);
21605 MVT VT = Op.getSimpleValueType();
21606 if (!VT.isVector())
21607 return false; // Bail if we hit a non-vector.
21608 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21609 // version should be added.
21610 if (VT.getSizeInBits() != 128)
21613 assert(Root.getSimpleValueType().isVector() &&
21614 "Shuffles operate on vector types!");
21615 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21616 "Can only combine shuffles of the same vector register size.");
21618 if (!isTargetShuffle(Op.getOpcode()))
21620 SmallVector<int, 16> OpMask;
21622 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21623 // We only can combine unary shuffles which we can decode the mask for.
21624 if (!HaveMask || !IsUnary)
21627 assert(VT.getVectorNumElements() == OpMask.size() &&
21628 "Different mask size from vector size!");
21629 assert(((RootMask.size() > OpMask.size() &&
21630 RootMask.size() % OpMask.size() == 0) ||
21631 (OpMask.size() > RootMask.size() &&
21632 OpMask.size() % RootMask.size() == 0) ||
21633 OpMask.size() == RootMask.size()) &&
21634 "The smaller number of elements must divide the larger.");
21635 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21636 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21637 assert(((RootRatio == 1 && OpRatio == 1) ||
21638 (RootRatio == 1) != (OpRatio == 1)) &&
21639 "Must not have a ratio for both incoming and op masks!");
21641 SmallVector<int, 16> Mask;
21642 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21644 // Merge this shuffle operation's mask into our accumulated mask. Note that
21645 // this shuffle's mask will be the first applied to the input, followed by the
21646 // root mask to get us all the way to the root value arrangement. The reason
21647 // for this order is that we are recursing up the operation chain.
21648 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21649 int RootIdx = i / RootRatio;
21650 if (RootMask[RootIdx] < 0) {
21651 // This is a zero or undef lane, we're done.
21652 Mask.push_back(RootMask[RootIdx]);
21656 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21657 int OpIdx = RootMaskedIdx / OpRatio;
21658 if (OpMask[OpIdx] < 0) {
21659 // The incoming lanes are zero or undef, it doesn't matter which ones we
21661 Mask.push_back(OpMask[OpIdx]);
21665 // Ok, we have non-zero lanes, map them through.
21666 Mask.push_back(OpMask[OpIdx] * OpRatio +
21667 RootMaskedIdx % OpRatio);
21670 // See if we can recurse into the operand to combine more things.
21671 switch (Op.getOpcode()) {
21672 case X86ISD::PSHUFB:
21674 case X86ISD::PSHUFD:
21675 case X86ISD::PSHUFHW:
21676 case X86ISD::PSHUFLW:
21677 if (Op.getOperand(0).hasOneUse() &&
21678 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21679 HasPSHUFB, DAG, DCI, Subtarget))
21683 case X86ISD::UNPCKL:
21684 case X86ISD::UNPCKH:
21685 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21686 // We can't check for single use, we have to check that this shuffle is the only user.
21687 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21688 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21689 HasPSHUFB, DAG, DCI, Subtarget))
21694 // Minor canonicalization of the accumulated shuffle mask to make it easier
21695 // to match below. All this does is detect masks with squential pairs of
21696 // elements, and shrink them to the half-width mask. It does this in a loop
21697 // so it will reduce the size of the mask to the minimal width mask which
21698 // performs an equivalent shuffle.
21699 SmallVector<int, 16> WidenedMask;
21700 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21701 Mask = std::move(WidenedMask);
21702 WidenedMask.clear();
21705 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21709 /// \brief Get the PSHUF-style mask from PSHUF node.
21711 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21712 /// PSHUF-style masks that can be reused with such instructions.
21713 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21714 SmallVector<int, 4> Mask;
21716 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21720 switch (N.getOpcode()) {
21721 case X86ISD::PSHUFD:
21723 case X86ISD::PSHUFLW:
21726 case X86ISD::PSHUFHW:
21727 Mask.erase(Mask.begin(), Mask.begin() + 4);
21728 for (int &M : Mask)
21732 llvm_unreachable("No valid shuffle instruction found!");
21736 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21738 /// We walk up the chain and look for a combinable shuffle, skipping over
21739 /// shuffles that we could hoist this shuffle's transformation past without
21740 /// altering anything.
21742 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21744 TargetLowering::DAGCombinerInfo &DCI) {
21745 assert(N.getOpcode() == X86ISD::PSHUFD &&
21746 "Called with something other than an x86 128-bit half shuffle!");
21749 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21750 // of the shuffles in the chain so that we can form a fresh chain to replace
21752 SmallVector<SDValue, 8> Chain;
21753 SDValue V = N.getOperand(0);
21754 for (; V.hasOneUse(); V = V.getOperand(0)) {
21755 switch (V.getOpcode()) {
21757 return SDValue(); // Nothing combined!
21760 // Skip bitcasts as we always know the type for the target specific
21764 case X86ISD::PSHUFD:
21765 // Found another dword shuffle.
21768 case X86ISD::PSHUFLW:
21769 // Check that the low words (being shuffled) are the identity in the
21770 // dword shuffle, and the high words are self-contained.
21771 if (Mask[0] != 0 || Mask[1] != 1 ||
21772 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21775 Chain.push_back(V);
21778 case X86ISD::PSHUFHW:
21779 // Check that the high words (being shuffled) are the identity in the
21780 // dword shuffle, and the low words are self-contained.
21781 if (Mask[2] != 2 || Mask[3] != 3 ||
21782 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21785 Chain.push_back(V);
21788 case X86ISD::UNPCKL:
21789 case X86ISD::UNPCKH:
21790 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21791 // shuffle into a preceding word shuffle.
21792 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21795 // Search for a half-shuffle which we can combine with.
21796 unsigned CombineOp =
21797 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21798 if (V.getOperand(0) != V.getOperand(1) ||
21799 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21801 Chain.push_back(V);
21802 V = V.getOperand(0);
21804 switch (V.getOpcode()) {
21806 return SDValue(); // Nothing to combine.
21808 case X86ISD::PSHUFLW:
21809 case X86ISD::PSHUFHW:
21810 if (V.getOpcode() == CombineOp)
21813 Chain.push_back(V);
21817 V = V.getOperand(0);
21821 } while (V.hasOneUse());
21824 // Break out of the loop if we break out of the switch.
21828 if (!V.hasOneUse())
21829 // We fell out of the loop without finding a viable combining instruction.
21832 // Merge this node's mask and our incoming mask.
21833 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21834 for (int &M : Mask)
21836 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21837 getV4X86ShuffleImm8ForMask(Mask, DAG));
21839 // Rebuild the chain around this new shuffle.
21840 while (!Chain.empty()) {
21841 SDValue W = Chain.pop_back_val();
21843 if (V.getValueType() != W.getOperand(0).getValueType())
21844 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21846 switch (W.getOpcode()) {
21848 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21850 case X86ISD::UNPCKL:
21851 case X86ISD::UNPCKH:
21852 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21855 case X86ISD::PSHUFD:
21856 case X86ISD::PSHUFLW:
21857 case X86ISD::PSHUFHW:
21858 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21862 if (V.getValueType() != N.getValueType())
21863 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21865 // Return the new chain to replace N.
21869 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21871 /// We walk up the chain, skipping shuffles of the other half and looking
21872 /// through shuffles which switch halves trying to find a shuffle of the same
21873 /// pair of dwords.
21874 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21876 TargetLowering::DAGCombinerInfo &DCI) {
21878 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21879 "Called with something other than an x86 128-bit half shuffle!");
21881 unsigned CombineOpcode = N.getOpcode();
21883 // Walk up a single-use chain looking for a combinable shuffle.
21884 SDValue V = N.getOperand(0);
21885 for (; V.hasOneUse(); V = V.getOperand(0)) {
21886 switch (V.getOpcode()) {
21888 return false; // Nothing combined!
21891 // Skip bitcasts as we always know the type for the target specific
21895 case X86ISD::PSHUFLW:
21896 case X86ISD::PSHUFHW:
21897 if (V.getOpcode() == CombineOpcode)
21900 // Other-half shuffles are no-ops.
21903 // Break out of the loop if we break out of the switch.
21907 if (!V.hasOneUse())
21908 // We fell out of the loop without finding a viable combining instruction.
21911 // Combine away the bottom node as its shuffle will be accumulated into
21912 // a preceding shuffle.
21913 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21915 // Record the old value.
21918 // Merge this node's mask and our incoming mask (adjusted to account for all
21919 // the pshufd instructions encountered).
21920 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21921 for (int &M : Mask)
21923 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21924 getV4X86ShuffleImm8ForMask(Mask, DAG));
21926 // Check that the shuffles didn't cancel each other out. If not, we need to
21927 // combine to the new one.
21929 // Replace the combinable shuffle with the combined one, updating all users
21930 // so that we re-evaluate the chain here.
21931 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21936 /// \brief Try to combine x86 target specific shuffles.
21937 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21938 TargetLowering::DAGCombinerInfo &DCI,
21939 const X86Subtarget *Subtarget) {
21941 MVT VT = N.getSimpleValueType();
21942 SmallVector<int, 4> Mask;
21944 switch (N.getOpcode()) {
21945 case X86ISD::PSHUFD:
21946 case X86ISD::PSHUFLW:
21947 case X86ISD::PSHUFHW:
21948 Mask = getPSHUFShuffleMask(N);
21949 assert(Mask.size() == 4);
21955 // Nuke no-op shuffles that show up after combining.
21956 if (isNoopShuffleMask(Mask))
21957 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21959 // Look for simplifications involving one or two shuffle instructions.
21960 SDValue V = N.getOperand(0);
21961 switch (N.getOpcode()) {
21964 case X86ISD::PSHUFLW:
21965 case X86ISD::PSHUFHW:
21966 assert(VT == MVT::v8i16);
21969 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21970 return SDValue(); // We combined away this shuffle, so we're done.
21972 // See if this reduces to a PSHUFD which is no more expensive and can
21973 // combine with more operations. Note that it has to at least flip the
21974 // dwords as otherwise it would have been removed as a no-op.
21975 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21976 int DMask[] = {0, 1, 2, 3};
21977 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21978 DMask[DOffset + 0] = DOffset + 1;
21979 DMask[DOffset + 1] = DOffset + 0;
21980 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21981 DCI.AddToWorklist(V.getNode());
21982 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21983 getV4X86ShuffleImm8ForMask(DMask, DAG));
21984 DCI.AddToWorklist(V.getNode());
21985 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21988 // Look for shuffle patterns which can be implemented as a single unpack.
21989 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21990 // only works when we have a PSHUFD followed by two half-shuffles.
21991 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21992 (V.getOpcode() == X86ISD::PSHUFLW ||
21993 V.getOpcode() == X86ISD::PSHUFHW) &&
21994 V.getOpcode() != N.getOpcode() &&
21996 SDValue D = V.getOperand(0);
21997 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21998 D = D.getOperand(0);
21999 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22000 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22001 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22002 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22003 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22005 for (int i = 0; i < 4; ++i) {
22006 WordMask[i + NOffset] = Mask[i] + NOffset;
22007 WordMask[i + VOffset] = VMask[i] + VOffset;
22009 // Map the word mask through the DWord mask.
22011 for (int i = 0; i < 8; ++i)
22012 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22013 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22014 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22015 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22016 std::begin(UnpackLoMask)) ||
22017 std::equal(std::begin(MappedMask), std::end(MappedMask),
22018 std::begin(UnpackHiMask))) {
22019 // We can replace all three shuffles with an unpack.
22020 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22021 DCI.AddToWorklist(V.getNode());
22022 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22024 DL, MVT::v8i16, V, V);
22031 case X86ISD::PSHUFD:
22032 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22041 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22043 /// We combine this directly on the abstract vector shuffle nodes so it is
22044 /// easier to generically match. We also insert dummy vector shuffle nodes for
22045 /// the operands which explicitly discard the lanes which are unused by this
22046 /// operation to try to flow through the rest of the combiner the fact that
22047 /// they're unused.
22048 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22050 EVT VT = N->getValueType(0);
22052 // We only handle target-independent shuffles.
22053 // FIXME: It would be easy and harmless to use the target shuffle mask
22054 // extraction tool to support more.
22055 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22058 auto *SVN = cast<ShuffleVectorSDNode>(N);
22059 ArrayRef<int> Mask = SVN->getMask();
22060 SDValue V1 = N->getOperand(0);
22061 SDValue V2 = N->getOperand(1);
22063 // We require the first shuffle operand to be the SUB node, and the second to
22064 // be the ADD node.
22065 // FIXME: We should support the commuted patterns.
22066 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22069 // If there are other uses of these operations we can't fold them.
22070 if (!V1->hasOneUse() || !V2->hasOneUse())
22073 // Ensure that both operations have the same operands. Note that we can
22074 // commute the FADD operands.
22075 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22076 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22077 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22080 // We're looking for blends between FADD and FSUB nodes. We insist on these
22081 // nodes being lined up in a specific expected pattern.
22082 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22083 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22084 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22087 // Only specific types are legal at this point, assert so we notice if and
22088 // when these change.
22089 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22090 VT == MVT::v4f64) &&
22091 "Unknown vector type encountered!");
22093 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22096 /// PerformShuffleCombine - Performs several different shuffle combines.
22097 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22098 TargetLowering::DAGCombinerInfo &DCI,
22099 const X86Subtarget *Subtarget) {
22101 SDValue N0 = N->getOperand(0);
22102 SDValue N1 = N->getOperand(1);
22103 EVT VT = N->getValueType(0);
22105 // Don't create instructions with illegal types after legalize types has run.
22106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22107 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22110 // If we have legalized the vector types, look for blends of FADD and FSUB
22111 // nodes that we can fuse into an ADDSUB node.
22112 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22113 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22116 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22117 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22118 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22119 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22121 // During Type Legalization, when promoting illegal vector types,
22122 // the backend might introduce new shuffle dag nodes and bitcasts.
22124 // This code performs the following transformation:
22125 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22126 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22128 // We do this only if both the bitcast and the BINOP dag nodes have
22129 // one use. Also, perform this transformation only if the new binary
22130 // operation is legal. This is to avoid introducing dag nodes that
22131 // potentially need to be further expanded (or custom lowered) into a
22132 // less optimal sequence of dag nodes.
22133 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22134 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22135 N0.getOpcode() == ISD::BITCAST) {
22136 SDValue BC0 = N0.getOperand(0);
22137 EVT SVT = BC0.getValueType();
22138 unsigned Opcode = BC0.getOpcode();
22139 unsigned NumElts = VT.getVectorNumElements();
22141 if (BC0.hasOneUse() && SVT.isVector() &&
22142 SVT.getVectorNumElements() * 2 == NumElts &&
22143 TLI.isOperationLegal(Opcode, VT)) {
22144 bool CanFold = false;
22156 unsigned SVTNumElts = SVT.getVectorNumElements();
22157 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22158 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22159 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22160 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22161 CanFold = SVOp->getMaskElt(i) < 0;
22164 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22165 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22166 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22167 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22172 // Only handle 128 wide vector from here on.
22173 if (!VT.is128BitVector())
22176 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22177 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22178 // consecutive, non-overlapping, and in the right order.
22179 SmallVector<SDValue, 16> Elts;
22180 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22181 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22183 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22187 if (isTargetShuffle(N->getOpcode())) {
22189 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22190 if (Shuffle.getNode())
22193 // Try recursively combining arbitrary sequences of x86 shuffle
22194 // instructions into higher-order shuffles. We do this after combining
22195 // specific PSHUF instruction sequences into their minimal form so that we
22196 // can evaluate how many specialized shuffle instructions are involved in
22197 // a particular chain.
22198 SmallVector<int, 1> NonceMask; // Just a placeholder.
22199 NonceMask.push_back(0);
22200 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22201 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22203 return SDValue(); // This routine will use CombineTo to replace N.
22209 /// PerformTruncateCombine - Converts truncate operation to
22210 /// a sequence of vector shuffle operations.
22211 /// It is possible when we truncate 256-bit vector to 128-bit vector
22212 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22213 TargetLowering::DAGCombinerInfo &DCI,
22214 const X86Subtarget *Subtarget) {
22218 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22219 /// specific shuffle of a load can be folded into a single element load.
22220 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22221 /// shuffles have been custom lowered so we need to handle those here.
22222 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22223 TargetLowering::DAGCombinerInfo &DCI) {
22224 if (DCI.isBeforeLegalizeOps())
22227 SDValue InVec = N->getOperand(0);
22228 SDValue EltNo = N->getOperand(1);
22230 if (!isa<ConstantSDNode>(EltNo))
22233 EVT OriginalVT = InVec.getValueType();
22235 if (InVec.getOpcode() == ISD::BITCAST) {
22236 // Don't duplicate a load with other uses.
22237 if (!InVec.hasOneUse())
22239 EVT BCVT = InVec.getOperand(0).getValueType();
22240 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22242 InVec = InVec.getOperand(0);
22245 EVT CurrentVT = InVec.getValueType();
22247 if (!isTargetShuffle(InVec.getOpcode()))
22250 // Don't duplicate a load with other uses.
22251 if (!InVec.hasOneUse())
22254 SmallVector<int, 16> ShuffleMask;
22256 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22257 ShuffleMask, UnaryShuffle))
22260 // Select the input vector, guarding against out of range extract vector.
22261 unsigned NumElems = CurrentVT.getVectorNumElements();
22262 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22263 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22264 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22265 : InVec.getOperand(1);
22267 // If inputs to shuffle are the same for both ops, then allow 2 uses
22268 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22270 if (LdNode.getOpcode() == ISD::BITCAST) {
22271 // Don't duplicate a load with other uses.
22272 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22275 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22276 LdNode = LdNode.getOperand(0);
22279 if (!ISD::isNormalLoad(LdNode.getNode()))
22282 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22284 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22287 EVT EltVT = N->getValueType(0);
22288 // If there's a bitcast before the shuffle, check if the load type and
22289 // alignment is valid.
22290 unsigned Align = LN0->getAlignment();
22291 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22292 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22293 EltVT.getTypeForEVT(*DAG.getContext()));
22295 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22298 // All checks match so transform back to vector_shuffle so that DAG combiner
22299 // can finish the job
22302 // Create shuffle node taking into account the case that its a unary shuffle
22303 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22304 : InVec.getOperand(1);
22305 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22306 InVec.getOperand(0), Shuffle,
22308 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22309 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22313 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22314 /// generation and convert it from being a bunch of shuffles and extracts
22315 /// to a simple store and scalar loads to extract the elements.
22316 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22317 TargetLowering::DAGCombinerInfo &DCI) {
22318 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22319 if (NewOp.getNode())
22322 SDValue InputVector = N->getOperand(0);
22324 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22325 // from mmx to v2i32 has a single usage.
22326 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22327 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22328 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22329 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22330 N->getValueType(0),
22331 InputVector.getNode()->getOperand(0));
22333 // Only operate on vectors of 4 elements, where the alternative shuffling
22334 // gets to be more expensive.
22335 if (InputVector.getValueType() != MVT::v4i32)
22338 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22339 // single use which is a sign-extend or zero-extend, and all elements are
22341 SmallVector<SDNode *, 4> Uses;
22342 unsigned ExtractedElements = 0;
22343 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22344 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22345 if (UI.getUse().getResNo() != InputVector.getResNo())
22348 SDNode *Extract = *UI;
22349 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22352 if (Extract->getValueType(0) != MVT::i32)
22354 if (!Extract->hasOneUse())
22356 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22357 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22359 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22362 // Record which element was extracted.
22363 ExtractedElements |=
22364 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22366 Uses.push_back(Extract);
22369 // If not all the elements were used, this may not be worthwhile.
22370 if (ExtractedElements != 15)
22373 // Ok, we've now decided to do the transformation.
22374 SDLoc dl(InputVector);
22376 // Store the value to a temporary stack slot.
22377 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22378 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22379 MachinePointerInfo(), false, false, 0);
22381 // Replace each use (extract) with a load of the appropriate element.
22382 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22383 UE = Uses.end(); UI != UE; ++UI) {
22384 SDNode *Extract = *UI;
22386 // cOMpute the element's address.
22387 SDValue Idx = Extract->getOperand(1);
22389 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22390 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22391 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22392 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22394 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22395 StackPtr, OffsetVal);
22397 // Load the scalar.
22398 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22399 ScalarAddr, MachinePointerInfo(),
22400 false, false, false, 0);
22402 // Replace the exact with the load.
22403 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22406 // The replacement was made in place; don't return anything.
22410 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22411 static std::pair<unsigned, bool>
22412 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22413 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22414 if (!VT.isVector())
22415 return std::make_pair(0, false);
22417 bool NeedSplit = false;
22418 switch (VT.getSimpleVT().SimpleTy) {
22419 default: return std::make_pair(0, false);
22423 if (!Subtarget->hasAVX2())
22425 if (!Subtarget->hasAVX())
22426 return std::make_pair(0, false);
22431 if (!Subtarget->hasSSE2())
22432 return std::make_pair(0, false);
22435 // SSE2 has only a small subset of the operations.
22436 bool hasUnsigned = Subtarget->hasSSE41() ||
22437 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22438 bool hasSigned = Subtarget->hasSSE41() ||
22439 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22441 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22444 // Check for x CC y ? x : y.
22445 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22446 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22451 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22454 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22457 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22460 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22462 // Check for x CC y ? y : x -- a min/max with reversed arms.
22463 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22464 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22469 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22472 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22475 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22478 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22482 return std::make_pair(Opc, NeedSplit);
22486 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22487 const X86Subtarget *Subtarget) {
22489 SDValue Cond = N->getOperand(0);
22490 SDValue LHS = N->getOperand(1);
22491 SDValue RHS = N->getOperand(2);
22493 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22494 SDValue CondSrc = Cond->getOperand(0);
22495 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22496 Cond = CondSrc->getOperand(0);
22499 MVT VT = N->getSimpleValueType(0);
22500 MVT EltVT = VT.getVectorElementType();
22501 unsigned NumElems = VT.getVectorNumElements();
22502 // There is no blend with immediate in AVX-512.
22503 if (VT.is512BitVector())
22506 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22508 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22511 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22514 // A vselect where all conditions and data are constants can be optimized into
22515 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22516 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22517 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22520 unsigned MaskValue = 0;
22521 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22524 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22525 for (unsigned i = 0; i < NumElems; ++i) {
22526 // Be sure we emit undef where we can.
22527 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22528 ShuffleMask[i] = -1;
22530 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22533 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22536 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22538 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22539 TargetLowering::DAGCombinerInfo &DCI,
22540 const X86Subtarget *Subtarget) {
22542 SDValue Cond = N->getOperand(0);
22543 // Get the LHS/RHS of the select.
22544 SDValue LHS = N->getOperand(1);
22545 SDValue RHS = N->getOperand(2);
22546 EVT VT = LHS.getValueType();
22547 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22549 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22550 // instructions match the semantics of the common C idiom x<y?x:y but not
22551 // x<=y?x:y, because of how they handle negative zero (which can be
22552 // ignored in unsafe-math mode).
22553 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22554 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22555 (Subtarget->hasSSE2() ||
22556 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22557 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22559 unsigned Opcode = 0;
22560 // Check for x CC y ? x : y.
22561 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22562 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22566 // Converting this to a min would handle NaNs incorrectly, and swapping
22567 // the operands would cause it to handle comparisons between positive
22568 // and negative zero incorrectly.
22569 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22570 if (!DAG.getTarget().Options.UnsafeFPMath &&
22571 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22573 std::swap(LHS, RHS);
22575 Opcode = X86ISD::FMIN;
22578 // Converting this to a min would handle comparisons between positive
22579 // and negative zero incorrectly.
22580 if (!DAG.getTarget().Options.UnsafeFPMath &&
22581 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22583 Opcode = X86ISD::FMIN;
22586 // Converting this to a min would handle both negative zeros and NaNs
22587 // incorrectly, but we can swap the operands to fix both.
22588 std::swap(LHS, RHS);
22592 Opcode = X86ISD::FMIN;
22596 // Converting this to a max would handle comparisons between positive
22597 // and negative zero incorrectly.
22598 if (!DAG.getTarget().Options.UnsafeFPMath &&
22599 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22601 Opcode = X86ISD::FMAX;
22604 // Converting this to a max would handle NaNs incorrectly, and swapping
22605 // the operands would cause it to handle comparisons between positive
22606 // and negative zero incorrectly.
22607 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22608 if (!DAG.getTarget().Options.UnsafeFPMath &&
22609 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22611 std::swap(LHS, RHS);
22613 Opcode = X86ISD::FMAX;
22616 // Converting this to a max would handle both negative zeros and NaNs
22617 // incorrectly, but we can swap the operands to fix both.
22618 std::swap(LHS, RHS);
22622 Opcode = X86ISD::FMAX;
22625 // Check for x CC y ? y : x -- a min/max with reversed arms.
22626 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22627 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22631 // Converting this to a min would handle comparisons between positive
22632 // and negative zero incorrectly, and swapping the operands would
22633 // cause it to handle NaNs incorrectly.
22634 if (!DAG.getTarget().Options.UnsafeFPMath &&
22635 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22636 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22638 std::swap(LHS, RHS);
22640 Opcode = X86ISD::FMIN;
22643 // Converting this to a min would handle NaNs incorrectly.
22644 if (!DAG.getTarget().Options.UnsafeFPMath &&
22645 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22647 Opcode = X86ISD::FMIN;
22650 // Converting this to a min would handle both negative zeros and NaNs
22651 // incorrectly, but we can swap the operands to fix both.
22652 std::swap(LHS, RHS);
22656 Opcode = X86ISD::FMIN;
22660 // Converting this to a max would handle NaNs incorrectly.
22661 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22663 Opcode = X86ISD::FMAX;
22666 // Converting this to a max would handle comparisons between positive
22667 // and negative zero incorrectly, and swapping the operands would
22668 // cause it to handle NaNs incorrectly.
22669 if (!DAG.getTarget().Options.UnsafeFPMath &&
22670 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22671 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22673 std::swap(LHS, RHS);
22675 Opcode = X86ISD::FMAX;
22678 // Converting this to a max would handle both negative zeros and NaNs
22679 // incorrectly, but we can swap the operands to fix both.
22680 std::swap(LHS, RHS);
22684 Opcode = X86ISD::FMAX;
22690 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22693 EVT CondVT = Cond.getValueType();
22694 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22695 CondVT.getVectorElementType() == MVT::i1) {
22696 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22697 // lowering on KNL. In this case we convert it to
22698 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22699 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22700 // Since SKX these selects have a proper lowering.
22701 EVT OpVT = LHS.getValueType();
22702 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22703 (OpVT.getVectorElementType() == MVT::i8 ||
22704 OpVT.getVectorElementType() == MVT::i16) &&
22705 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22706 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22707 DCI.AddToWorklist(Cond.getNode());
22708 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22711 // If this is a select between two integer constants, try to do some
22713 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22714 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22715 // Don't do this for crazy integer types.
22716 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22717 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22718 // so that TrueC (the true value) is larger than FalseC.
22719 bool NeedsCondInvert = false;
22721 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22722 // Efficiently invertible.
22723 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22724 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22725 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22726 NeedsCondInvert = true;
22727 std::swap(TrueC, FalseC);
22730 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22731 if (FalseC->getAPIntValue() == 0 &&
22732 TrueC->getAPIntValue().isPowerOf2()) {
22733 if (NeedsCondInvert) // Invert the condition if needed.
22734 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22735 DAG.getConstant(1, Cond.getValueType()));
22737 // Zero extend the condition if needed.
22738 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22740 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22741 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22742 DAG.getConstant(ShAmt, MVT::i8));
22745 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22746 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22747 if (NeedsCondInvert) // Invert the condition if needed.
22748 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22749 DAG.getConstant(1, Cond.getValueType()));
22751 // Zero extend the condition if needed.
22752 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22753 FalseC->getValueType(0), Cond);
22754 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22755 SDValue(FalseC, 0));
22758 // Optimize cases that will turn into an LEA instruction. This requires
22759 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22760 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22761 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22762 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22764 bool isFastMultiplier = false;
22766 switch ((unsigned char)Diff) {
22768 case 1: // result = add base, cond
22769 case 2: // result = lea base( , cond*2)
22770 case 3: // result = lea base(cond, cond*2)
22771 case 4: // result = lea base( , cond*4)
22772 case 5: // result = lea base(cond, cond*4)
22773 case 8: // result = lea base( , cond*8)
22774 case 9: // result = lea base(cond, cond*8)
22775 isFastMultiplier = true;
22780 if (isFastMultiplier) {
22781 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22782 if (NeedsCondInvert) // Invert the condition if needed.
22783 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22784 DAG.getConstant(1, Cond.getValueType()));
22786 // Zero extend the condition if needed.
22787 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22789 // Scale the condition by the difference.
22791 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22792 DAG.getConstant(Diff, Cond.getValueType()));
22794 // Add the base if non-zero.
22795 if (FalseC->getAPIntValue() != 0)
22796 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22797 SDValue(FalseC, 0));
22804 // Canonicalize max and min:
22805 // (x > y) ? x : y -> (x >= y) ? x : y
22806 // (x < y) ? x : y -> (x <= y) ? x : y
22807 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22808 // the need for an extra compare
22809 // against zero. e.g.
22810 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22812 // testl %edi, %edi
22814 // cmovgl %edi, %eax
22818 // cmovsl %eax, %edi
22819 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22820 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22821 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22822 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22827 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22828 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22829 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22830 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22835 // Early exit check
22836 if (!TLI.isTypeLegal(VT))
22839 // Match VSELECTs into subs with unsigned saturation.
22840 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22841 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22842 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22843 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22844 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22846 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22847 // left side invert the predicate to simplify logic below.
22849 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22851 CC = ISD::getSetCCInverse(CC, true);
22852 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22856 if (Other.getNode() && Other->getNumOperands() == 2 &&
22857 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22858 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22859 SDValue CondRHS = Cond->getOperand(1);
22861 // Look for a general sub with unsigned saturation first.
22862 // x >= y ? x-y : 0 --> subus x, y
22863 // x > y ? x-y : 0 --> subus x, y
22864 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22865 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22866 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22868 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22869 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22870 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22871 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22872 // If the RHS is a constant we have to reverse the const
22873 // canonicalization.
22874 // x > C-1 ? x+-C : 0 --> subus x, C
22875 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22876 CondRHSConst->getAPIntValue() ==
22877 (-OpRHSConst->getAPIntValue() - 1))
22878 return DAG.getNode(
22879 X86ISD::SUBUS, DL, VT, OpLHS,
22880 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22882 // Another special case: If C was a sign bit, the sub has been
22883 // canonicalized into a xor.
22884 // FIXME: Would it be better to use computeKnownBits to determine
22885 // whether it's safe to decanonicalize the xor?
22886 // x s< 0 ? x^C : 0 --> subus x, C
22887 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22888 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22889 OpRHSConst->getAPIntValue().isSignBit())
22890 // Note that we have to rebuild the RHS constant here to ensure we
22891 // don't rely on particular values of undef lanes.
22892 return DAG.getNode(
22893 X86ISD::SUBUS, DL, VT, OpLHS,
22894 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22899 // Try to match a min/max vector operation.
22900 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22901 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22902 unsigned Opc = ret.first;
22903 bool NeedSplit = ret.second;
22905 if (Opc && NeedSplit) {
22906 unsigned NumElems = VT.getVectorNumElements();
22907 // Extract the LHS vectors
22908 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22909 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22911 // Extract the RHS vectors
22912 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22913 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22915 // Create min/max for each subvector
22916 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22917 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22919 // Merge the result
22920 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22922 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22925 // Simplify vector selection if condition value type matches vselect
22927 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22928 assert(Cond.getValueType().isVector() &&
22929 "vector select expects a vector selector!");
22931 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22932 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22934 // Try invert the condition if true value is not all 1s and false value
22936 if (!TValIsAllOnes && !FValIsAllZeros &&
22937 // Check if the selector will be produced by CMPP*/PCMP*
22938 Cond.getOpcode() == ISD::SETCC &&
22939 // Check if SETCC has already been promoted
22940 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22941 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22942 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22944 if (TValIsAllZeros || FValIsAllOnes) {
22945 SDValue CC = Cond.getOperand(2);
22946 ISD::CondCode NewCC =
22947 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22948 Cond.getOperand(0).getValueType().isInteger());
22949 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22950 std::swap(LHS, RHS);
22951 TValIsAllOnes = FValIsAllOnes;
22952 FValIsAllZeros = TValIsAllZeros;
22956 if (TValIsAllOnes || FValIsAllZeros) {
22959 if (TValIsAllOnes && FValIsAllZeros)
22961 else if (TValIsAllOnes)
22962 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22963 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22964 else if (FValIsAllZeros)
22965 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22966 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22968 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22972 // Try to fold this VSELECT into a MOVSS/MOVSD
22973 if (N->getOpcode() == ISD::VSELECT &&
22974 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22975 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22976 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22977 bool CanFold = false;
22978 unsigned NumElems = Cond.getNumOperands();
22982 if (isZero(Cond.getOperand(0))) {
22985 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22986 // fold (vselect <0,-1> -> (movsd A, B)
22987 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22988 CanFold = isAllOnes(Cond.getOperand(i));
22989 } else if (isAllOnes(Cond.getOperand(0))) {
22993 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22994 // fold (vselect <-1,0> -> (movsd B, A)
22995 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22996 CanFold = isZero(Cond.getOperand(i));
23000 if (VT == MVT::v4i32 || VT == MVT::v4f32)
23001 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
23002 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
23005 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
23006 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
23007 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
23008 // (v2i64 (bitcast B)))))
23010 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
23011 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
23012 // (v2f64 (bitcast B)))))
23014 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
23015 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
23016 // (v2i64 (bitcast A)))))
23018 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
23019 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
23020 // (v2f64 (bitcast A)))))
23022 CanFold = (isZero(Cond.getOperand(0)) &&
23023 isZero(Cond.getOperand(1)) &&
23024 isAllOnes(Cond.getOperand(2)) &&
23025 isAllOnes(Cond.getOperand(3)));
23027 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
23028 isAllOnes(Cond.getOperand(1)) &&
23029 isZero(Cond.getOperand(2)) &&
23030 isZero(Cond.getOperand(3))) {
23032 std::swap(LHS, RHS);
23036 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
23037 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
23038 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
23039 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
23041 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
23047 // If we know that this node is legal then we know that it is going to be
23048 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23049 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23050 // to simplify previous instructions.
23051 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23052 !DCI.isBeforeLegalize() &&
23053 // We explicitly check against v8i16 and v16i16 because, although
23054 // they're marked as Custom, they might only be legal when Cond is a
23055 // build_vector of constants. This will be taken care in a later
23057 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23058 VT != MVT::v8i16) &&
23059 // Don't optimize vector of constants. Those are handled by
23060 // the generic code and all the bits must be properly set for
23061 // the generic optimizer.
23062 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23063 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23065 // Don't optimize vector selects that map to mask-registers.
23069 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23070 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23072 APInt KnownZero, KnownOne;
23073 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23074 DCI.isBeforeLegalizeOps());
23075 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23076 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23078 // If we changed the computation somewhere in the DAG, this change
23079 // will affect all users of Cond.
23080 // Make sure it is fine and update all the nodes so that we do not
23081 // use the generic VSELECT anymore. Otherwise, we may perform
23082 // wrong optimizations as we messed up with the actual expectation
23083 // for the vector boolean values.
23084 if (Cond != TLO.Old) {
23085 // Check all uses of that condition operand to check whether it will be
23086 // consumed by non-BLEND instructions, which may depend on all bits are
23088 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23090 if (I->getOpcode() != ISD::VSELECT)
23091 // TODO: Add other opcodes eventually lowered into BLEND.
23094 // Update all the users of the condition, before committing the change,
23095 // so that the VSELECT optimizations that expect the correct vector
23096 // boolean value will not be triggered.
23097 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23099 DAG.ReplaceAllUsesOfValueWith(
23101 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23102 Cond, I->getOperand(1), I->getOperand(2)));
23103 DCI.CommitTargetLoweringOpt(TLO);
23106 // At this point, only Cond is changed. Change the condition
23107 // just for N to keep the opportunity to optimize all other
23108 // users their own way.
23109 DAG.ReplaceAllUsesOfValueWith(
23111 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23112 TLO.New, N->getOperand(1), N->getOperand(2)));
23117 // We should generate an X86ISD::BLENDI from a vselect if its argument
23118 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23119 // constants. This specific pattern gets generated when we split a
23120 // selector for a 512 bit vector in a machine without AVX512 (but with
23121 // 256-bit vectors), during legalization:
23123 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23125 // Iff we find this pattern and the build_vectors are built from
23126 // constants, we translate the vselect into a shuffle_vector that we
23127 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23128 if ((N->getOpcode() == ISD::VSELECT ||
23129 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23130 !DCI.isBeforeLegalize()) {
23131 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23132 if (Shuffle.getNode())
23139 // Check whether a boolean test is testing a boolean value generated by
23140 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23143 // Simplify the following patterns:
23144 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23145 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23146 // to (Op EFLAGS Cond)
23148 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23149 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23150 // to (Op EFLAGS !Cond)
23152 // where Op could be BRCOND or CMOV.
23154 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23155 // Quit if not CMP and SUB with its value result used.
23156 if (Cmp.getOpcode() != X86ISD::CMP &&
23157 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23160 // Quit if not used as a boolean value.
23161 if (CC != X86::COND_E && CC != X86::COND_NE)
23164 // Check CMP operands. One of them should be 0 or 1 and the other should be
23165 // an SetCC or extended from it.
23166 SDValue Op1 = Cmp.getOperand(0);
23167 SDValue Op2 = Cmp.getOperand(1);
23170 const ConstantSDNode* C = nullptr;
23171 bool needOppositeCond = (CC == X86::COND_E);
23172 bool checkAgainstTrue = false; // Is it a comparison against 1?
23174 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23176 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23178 else // Quit if all operands are not constants.
23181 if (C->getZExtValue() == 1) {
23182 needOppositeCond = !needOppositeCond;
23183 checkAgainstTrue = true;
23184 } else if (C->getZExtValue() != 0)
23185 // Quit if the constant is neither 0 or 1.
23188 bool truncatedToBoolWithAnd = false;
23189 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23190 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23191 SetCC.getOpcode() == ISD::TRUNCATE ||
23192 SetCC.getOpcode() == ISD::AND) {
23193 if (SetCC.getOpcode() == ISD::AND) {
23195 ConstantSDNode *CS;
23196 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23197 CS->getZExtValue() == 1)
23199 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23200 CS->getZExtValue() == 1)
23204 SetCC = SetCC.getOperand(OpIdx);
23205 truncatedToBoolWithAnd = true;
23207 SetCC = SetCC.getOperand(0);
23210 switch (SetCC.getOpcode()) {
23211 case X86ISD::SETCC_CARRY:
23212 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23213 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23214 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23215 // truncated to i1 using 'and'.
23216 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23218 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23219 "Invalid use of SETCC_CARRY!");
23221 case X86ISD::SETCC:
23222 // Set the condition code or opposite one if necessary.
23223 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23224 if (needOppositeCond)
23225 CC = X86::GetOppositeBranchCondition(CC);
23226 return SetCC.getOperand(1);
23227 case X86ISD::CMOV: {
23228 // Check whether false/true value has canonical one, i.e. 0 or 1.
23229 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23230 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23231 // Quit if true value is not a constant.
23234 // Quit if false value is not a constant.
23236 SDValue Op = SetCC.getOperand(0);
23237 // Skip 'zext' or 'trunc' node.
23238 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23239 Op.getOpcode() == ISD::TRUNCATE)
23240 Op = Op.getOperand(0);
23241 // A special case for rdrand/rdseed, where 0 is set if false cond is
23243 if ((Op.getOpcode() != X86ISD::RDRAND &&
23244 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23247 // Quit if false value is not the constant 0 or 1.
23248 bool FValIsFalse = true;
23249 if (FVal && FVal->getZExtValue() != 0) {
23250 if (FVal->getZExtValue() != 1)
23252 // If FVal is 1, opposite cond is needed.
23253 needOppositeCond = !needOppositeCond;
23254 FValIsFalse = false;
23256 // Quit if TVal is not the constant opposite of FVal.
23257 if (FValIsFalse && TVal->getZExtValue() != 1)
23259 if (!FValIsFalse && TVal->getZExtValue() != 0)
23261 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23262 if (needOppositeCond)
23263 CC = X86::GetOppositeBranchCondition(CC);
23264 return SetCC.getOperand(3);
23271 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23272 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23273 TargetLowering::DAGCombinerInfo &DCI,
23274 const X86Subtarget *Subtarget) {
23277 // If the flag operand isn't dead, don't touch this CMOV.
23278 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23281 SDValue FalseOp = N->getOperand(0);
23282 SDValue TrueOp = N->getOperand(1);
23283 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23284 SDValue Cond = N->getOperand(3);
23286 if (CC == X86::COND_E || CC == X86::COND_NE) {
23287 switch (Cond.getOpcode()) {
23291 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23292 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23293 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23299 Flags = checkBoolTestSetCCCombine(Cond, CC);
23300 if (Flags.getNode() &&
23301 // Extra check as FCMOV only supports a subset of X86 cond.
23302 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23303 SDValue Ops[] = { FalseOp, TrueOp,
23304 DAG.getConstant(CC, MVT::i8), Flags };
23305 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23308 // If this is a select between two integer constants, try to do some
23309 // optimizations. Note that the operands are ordered the opposite of SELECT
23311 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23312 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23313 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23314 // larger than FalseC (the false value).
23315 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23316 CC = X86::GetOppositeBranchCondition(CC);
23317 std::swap(TrueC, FalseC);
23318 std::swap(TrueOp, FalseOp);
23321 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23322 // This is efficient for any integer data type (including i8/i16) and
23324 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23325 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23326 DAG.getConstant(CC, MVT::i8), Cond);
23328 // Zero extend the condition if needed.
23329 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23331 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23332 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23333 DAG.getConstant(ShAmt, MVT::i8));
23334 if (N->getNumValues() == 2) // Dead flag value?
23335 return DCI.CombineTo(N, Cond, SDValue());
23339 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23340 // for any integer data type, including i8/i16.
23341 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23342 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23343 DAG.getConstant(CC, MVT::i8), Cond);
23345 // Zero extend the condition if needed.
23346 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23347 FalseC->getValueType(0), Cond);
23348 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23349 SDValue(FalseC, 0));
23351 if (N->getNumValues() == 2) // Dead flag value?
23352 return DCI.CombineTo(N, Cond, SDValue());
23356 // Optimize cases that will turn into an LEA instruction. This requires
23357 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23358 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23359 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23360 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23362 bool isFastMultiplier = false;
23364 switch ((unsigned char)Diff) {
23366 case 1: // result = add base, cond
23367 case 2: // result = lea base( , cond*2)
23368 case 3: // result = lea base(cond, cond*2)
23369 case 4: // result = lea base( , cond*4)
23370 case 5: // result = lea base(cond, cond*4)
23371 case 8: // result = lea base( , cond*8)
23372 case 9: // result = lea base(cond, cond*8)
23373 isFastMultiplier = true;
23378 if (isFastMultiplier) {
23379 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23380 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23381 DAG.getConstant(CC, MVT::i8), Cond);
23382 // Zero extend the condition if needed.
23383 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23385 // Scale the condition by the difference.
23387 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23388 DAG.getConstant(Diff, Cond.getValueType()));
23390 // Add the base if non-zero.
23391 if (FalseC->getAPIntValue() != 0)
23392 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23393 SDValue(FalseC, 0));
23394 if (N->getNumValues() == 2) // Dead flag value?
23395 return DCI.CombineTo(N, Cond, SDValue());
23402 // Handle these cases:
23403 // (select (x != c), e, c) -> select (x != c), e, x),
23404 // (select (x == c), c, e) -> select (x == c), x, e)
23405 // where the c is an integer constant, and the "select" is the combination
23406 // of CMOV and CMP.
23408 // The rationale for this change is that the conditional-move from a constant
23409 // needs two instructions, however, conditional-move from a register needs
23410 // only one instruction.
23412 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23413 // some instruction-combining opportunities. This opt needs to be
23414 // postponed as late as possible.
23416 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23417 // the DCI.xxxx conditions are provided to postpone the optimization as
23418 // late as possible.
23420 ConstantSDNode *CmpAgainst = nullptr;
23421 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23422 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23423 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23425 if (CC == X86::COND_NE &&
23426 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23427 CC = X86::GetOppositeBranchCondition(CC);
23428 std::swap(TrueOp, FalseOp);
23431 if (CC == X86::COND_E &&
23432 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23433 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23434 DAG.getConstant(CC, MVT::i8), Cond };
23435 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23443 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23444 const X86Subtarget *Subtarget) {
23445 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23447 default: return SDValue();
23448 // SSE/AVX/AVX2 blend intrinsics.
23449 case Intrinsic::x86_avx2_pblendvb:
23450 case Intrinsic::x86_avx2_pblendw:
23451 case Intrinsic::x86_avx2_pblendd_128:
23452 case Intrinsic::x86_avx2_pblendd_256:
23453 // Don't try to simplify this intrinsic if we don't have AVX2.
23454 if (!Subtarget->hasAVX2())
23457 case Intrinsic::x86_avx_blend_pd_256:
23458 case Intrinsic::x86_avx_blend_ps_256:
23459 case Intrinsic::x86_avx_blendv_pd_256:
23460 case Intrinsic::x86_avx_blendv_ps_256:
23461 // Don't try to simplify this intrinsic if we don't have AVX.
23462 if (!Subtarget->hasAVX())
23465 case Intrinsic::x86_sse41_pblendw:
23466 case Intrinsic::x86_sse41_blendpd:
23467 case Intrinsic::x86_sse41_blendps:
23468 case Intrinsic::x86_sse41_blendvps:
23469 case Intrinsic::x86_sse41_blendvpd:
23470 case Intrinsic::x86_sse41_pblendvb: {
23471 SDValue Op0 = N->getOperand(1);
23472 SDValue Op1 = N->getOperand(2);
23473 SDValue Mask = N->getOperand(3);
23475 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23476 if (!Subtarget->hasSSE41())
23479 // fold (blend A, A, Mask) -> A
23482 // fold (blend A, B, allZeros) -> A
23483 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23485 // fold (blend A, B, allOnes) -> B
23486 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23489 // Simplify the case where the mask is a constant i32 value.
23490 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23491 if (C->isNullValue())
23493 if (C->isAllOnesValue())
23500 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23501 case Intrinsic::x86_sse2_psrai_w:
23502 case Intrinsic::x86_sse2_psrai_d:
23503 case Intrinsic::x86_avx2_psrai_w:
23504 case Intrinsic::x86_avx2_psrai_d:
23505 case Intrinsic::x86_sse2_psra_w:
23506 case Intrinsic::x86_sse2_psra_d:
23507 case Intrinsic::x86_avx2_psra_w:
23508 case Intrinsic::x86_avx2_psra_d: {
23509 SDValue Op0 = N->getOperand(1);
23510 SDValue Op1 = N->getOperand(2);
23511 EVT VT = Op0.getValueType();
23512 assert(VT.isVector() && "Expected a vector type!");
23514 if (isa<BuildVectorSDNode>(Op1))
23515 Op1 = Op1.getOperand(0);
23517 if (!isa<ConstantSDNode>(Op1))
23520 EVT SVT = VT.getVectorElementType();
23521 unsigned SVTBits = SVT.getSizeInBits();
23523 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23524 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23525 uint64_t ShAmt = C.getZExtValue();
23527 // Don't try to convert this shift into a ISD::SRA if the shift
23528 // count is bigger than or equal to the element size.
23529 if (ShAmt >= SVTBits)
23532 // Trivial case: if the shift count is zero, then fold this
23533 // into the first operand.
23537 // Replace this packed shift intrinsic with a target independent
23539 SDValue Splat = DAG.getConstant(C, VT);
23540 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23545 /// PerformMulCombine - Optimize a single multiply with constant into two
23546 /// in order to implement it with two cheaper instructions, e.g.
23547 /// LEA + SHL, LEA + LEA.
23548 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23549 TargetLowering::DAGCombinerInfo &DCI) {
23550 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23553 EVT VT = N->getValueType(0);
23554 if (VT != MVT::i64)
23557 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23560 uint64_t MulAmt = C->getZExtValue();
23561 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23564 uint64_t MulAmt1 = 0;
23565 uint64_t MulAmt2 = 0;
23566 if ((MulAmt % 9) == 0) {
23568 MulAmt2 = MulAmt / 9;
23569 } else if ((MulAmt % 5) == 0) {
23571 MulAmt2 = MulAmt / 5;
23572 } else if ((MulAmt % 3) == 0) {
23574 MulAmt2 = MulAmt / 3;
23577 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23580 if (isPowerOf2_64(MulAmt2) &&
23581 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23582 // If second multiplifer is pow2, issue it first. We want the multiply by
23583 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23585 std::swap(MulAmt1, MulAmt2);
23588 if (isPowerOf2_64(MulAmt1))
23589 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23590 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23592 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23593 DAG.getConstant(MulAmt1, VT));
23595 if (isPowerOf2_64(MulAmt2))
23596 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23597 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23599 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23600 DAG.getConstant(MulAmt2, VT));
23602 // Do not add new nodes to DAG combiner worklist.
23603 DCI.CombineTo(N, NewMul, false);
23608 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23609 SDValue N0 = N->getOperand(0);
23610 SDValue N1 = N->getOperand(1);
23611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23612 EVT VT = N0.getValueType();
23614 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23615 // since the result of setcc_c is all zero's or all ones.
23616 if (VT.isInteger() && !VT.isVector() &&
23617 N1C && N0.getOpcode() == ISD::AND &&
23618 N0.getOperand(1).getOpcode() == ISD::Constant) {
23619 SDValue N00 = N0.getOperand(0);
23620 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23621 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23622 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23623 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23624 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23625 APInt ShAmt = N1C->getAPIntValue();
23626 Mask = Mask.shl(ShAmt);
23628 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23629 N00, DAG.getConstant(Mask, VT));
23633 // Hardware support for vector shifts is sparse which makes us scalarize the
23634 // vector operations in many cases. Also, on sandybridge ADD is faster than
23636 // (shl V, 1) -> add V,V
23637 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23638 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23639 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23640 // We shift all of the values by one. In many cases we do not have
23641 // hardware support for this operation. This is better expressed as an ADD
23643 if (N1SplatC->getZExtValue() == 1)
23644 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23650 /// \brief Returns a vector of 0s if the node in input is a vector logical
23651 /// shift by a constant amount which is known to be bigger than or equal
23652 /// to the vector element size in bits.
23653 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23654 const X86Subtarget *Subtarget) {
23655 EVT VT = N->getValueType(0);
23657 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23658 (!Subtarget->hasInt256() ||
23659 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23662 SDValue Amt = N->getOperand(1);
23664 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23665 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23666 APInt ShiftAmt = AmtSplat->getAPIntValue();
23667 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23669 // SSE2/AVX2 logical shifts always return a vector of 0s
23670 // if the shift amount is bigger than or equal to
23671 // the element size. The constant shift amount will be
23672 // encoded as a 8-bit immediate.
23673 if (ShiftAmt.trunc(8).uge(MaxAmount))
23674 return getZeroVector(VT, Subtarget, DAG, DL);
23680 /// PerformShiftCombine - Combine shifts.
23681 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23682 TargetLowering::DAGCombinerInfo &DCI,
23683 const X86Subtarget *Subtarget) {
23684 if (N->getOpcode() == ISD::SHL) {
23685 SDValue V = PerformSHLCombine(N, DAG);
23686 if (V.getNode()) return V;
23689 if (N->getOpcode() != ISD::SRA) {
23690 // Try to fold this logical shift into a zero vector.
23691 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23692 if (V.getNode()) return V;
23698 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23699 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23700 // and friends. Likewise for OR -> CMPNEQSS.
23701 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23702 TargetLowering::DAGCombinerInfo &DCI,
23703 const X86Subtarget *Subtarget) {
23706 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23707 // we're requiring SSE2 for both.
23708 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23709 SDValue N0 = N->getOperand(0);
23710 SDValue N1 = N->getOperand(1);
23711 SDValue CMP0 = N0->getOperand(1);
23712 SDValue CMP1 = N1->getOperand(1);
23715 // The SETCCs should both refer to the same CMP.
23716 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23719 SDValue CMP00 = CMP0->getOperand(0);
23720 SDValue CMP01 = CMP0->getOperand(1);
23721 EVT VT = CMP00.getValueType();
23723 if (VT == MVT::f32 || VT == MVT::f64) {
23724 bool ExpectingFlags = false;
23725 // Check for any users that want flags:
23726 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23727 !ExpectingFlags && UI != UE; ++UI)
23728 switch (UI->getOpcode()) {
23733 ExpectingFlags = true;
23735 case ISD::CopyToReg:
23736 case ISD::SIGN_EXTEND:
23737 case ISD::ZERO_EXTEND:
23738 case ISD::ANY_EXTEND:
23742 if (!ExpectingFlags) {
23743 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23744 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23746 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23747 X86::CondCode tmp = cc0;
23752 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23753 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23754 // FIXME: need symbolic constants for these magic numbers.
23755 // See X86ATTInstPrinter.cpp:printSSECC().
23756 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23757 if (Subtarget->hasAVX512()) {
23758 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23759 CMP01, DAG.getConstant(x86cc, MVT::i8));
23760 if (N->getValueType(0) != MVT::i1)
23761 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23765 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23766 CMP00.getValueType(), CMP00, CMP01,
23767 DAG.getConstant(x86cc, MVT::i8));
23769 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23770 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23772 if (is64BitFP && !Subtarget->is64Bit()) {
23773 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23774 // 64-bit integer, since that's not a legal type. Since
23775 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23776 // bits, but can do this little dance to extract the lowest 32 bits
23777 // and work with those going forward.
23778 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23780 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23782 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23783 Vector32, DAG.getIntPtrConstant(0));
23787 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23788 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23789 DAG.getConstant(1, IntVT));
23790 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23791 return OneBitOfTruth;
23799 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23800 /// so it can be folded inside ANDNP.
23801 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23802 EVT VT = N->getValueType(0);
23804 // Match direct AllOnes for 128 and 256-bit vectors
23805 if (ISD::isBuildVectorAllOnes(N))
23808 // Look through a bit convert.
23809 if (N->getOpcode() == ISD::BITCAST)
23810 N = N->getOperand(0).getNode();
23812 // Sometimes the operand may come from a insert_subvector building a 256-bit
23814 if (VT.is256BitVector() &&
23815 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23816 SDValue V1 = N->getOperand(0);
23817 SDValue V2 = N->getOperand(1);
23819 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23820 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23821 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23822 ISD::isBuildVectorAllOnes(V2.getNode()))
23829 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23830 // register. In most cases we actually compare or select YMM-sized registers
23831 // and mixing the two types creates horrible code. This method optimizes
23832 // some of the transition sequences.
23833 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23834 TargetLowering::DAGCombinerInfo &DCI,
23835 const X86Subtarget *Subtarget) {
23836 EVT VT = N->getValueType(0);
23837 if (!VT.is256BitVector())
23840 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23841 N->getOpcode() == ISD::ZERO_EXTEND ||
23842 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23844 SDValue Narrow = N->getOperand(0);
23845 EVT NarrowVT = Narrow->getValueType(0);
23846 if (!NarrowVT.is128BitVector())
23849 if (Narrow->getOpcode() != ISD::XOR &&
23850 Narrow->getOpcode() != ISD::AND &&
23851 Narrow->getOpcode() != ISD::OR)
23854 SDValue N0 = Narrow->getOperand(0);
23855 SDValue N1 = Narrow->getOperand(1);
23858 // The Left side has to be a trunc.
23859 if (N0.getOpcode() != ISD::TRUNCATE)
23862 // The type of the truncated inputs.
23863 EVT WideVT = N0->getOperand(0)->getValueType(0);
23867 // The right side has to be a 'trunc' or a constant vector.
23868 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23869 ConstantSDNode *RHSConstSplat = nullptr;
23870 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23871 RHSConstSplat = RHSBV->getConstantSplatNode();
23872 if (!RHSTrunc && !RHSConstSplat)
23875 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23877 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23880 // Set N0 and N1 to hold the inputs to the new wide operation.
23881 N0 = N0->getOperand(0);
23882 if (RHSConstSplat) {
23883 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23884 SDValue(RHSConstSplat, 0));
23885 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23886 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23887 } else if (RHSTrunc) {
23888 N1 = N1->getOperand(0);
23891 // Generate the wide operation.
23892 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23893 unsigned Opcode = N->getOpcode();
23895 case ISD::ANY_EXTEND:
23897 case ISD::ZERO_EXTEND: {
23898 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23899 APInt Mask = APInt::getAllOnesValue(InBits);
23900 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23901 return DAG.getNode(ISD::AND, DL, VT,
23902 Op, DAG.getConstant(Mask, VT));
23904 case ISD::SIGN_EXTEND:
23905 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23906 Op, DAG.getValueType(NarrowVT));
23908 llvm_unreachable("Unexpected opcode");
23912 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23913 TargetLowering::DAGCombinerInfo &DCI,
23914 const X86Subtarget *Subtarget) {
23915 EVT VT = N->getValueType(0);
23916 if (DCI.isBeforeLegalizeOps())
23919 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23923 // Create BEXTR instructions
23924 // BEXTR is ((X >> imm) & (2**size-1))
23925 if (VT == MVT::i32 || VT == MVT::i64) {
23926 SDValue N0 = N->getOperand(0);
23927 SDValue N1 = N->getOperand(1);
23930 // Check for BEXTR.
23931 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23932 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23933 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23934 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23935 if (MaskNode && ShiftNode) {
23936 uint64_t Mask = MaskNode->getZExtValue();
23937 uint64_t Shift = ShiftNode->getZExtValue();
23938 if (isMask_64(Mask)) {
23939 uint64_t MaskSize = CountPopulation_64(Mask);
23940 if (Shift + MaskSize <= VT.getSizeInBits())
23941 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23942 DAG.getConstant(Shift | (MaskSize << 8), VT));
23950 // Want to form ANDNP nodes:
23951 // 1) In the hopes of then easily combining them with OR and AND nodes
23952 // to form PBLEND/PSIGN.
23953 // 2) To match ANDN packed intrinsics
23954 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23957 SDValue N0 = N->getOperand(0);
23958 SDValue N1 = N->getOperand(1);
23961 // Check LHS for vnot
23962 if (N0.getOpcode() == ISD::XOR &&
23963 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23964 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23965 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23967 // Check RHS for vnot
23968 if (N1.getOpcode() == ISD::XOR &&
23969 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23970 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23971 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23976 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23977 TargetLowering::DAGCombinerInfo &DCI,
23978 const X86Subtarget *Subtarget) {
23979 if (DCI.isBeforeLegalizeOps())
23982 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23986 SDValue N0 = N->getOperand(0);
23987 SDValue N1 = N->getOperand(1);
23988 EVT VT = N->getValueType(0);
23990 // look for psign/blend
23991 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23992 if (!Subtarget->hasSSSE3() ||
23993 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23996 // Canonicalize pandn to RHS
23997 if (N0.getOpcode() == X86ISD::ANDNP)
23999 // or (and (m, y), (pandn m, x))
24000 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24001 SDValue Mask = N1.getOperand(0);
24002 SDValue X = N1.getOperand(1);
24004 if (N0.getOperand(0) == Mask)
24005 Y = N0.getOperand(1);
24006 if (N0.getOperand(1) == Mask)
24007 Y = N0.getOperand(0);
24009 // Check to see if the mask appeared in both the AND and ANDNP and
24013 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24014 // Look through mask bitcast.
24015 if (Mask.getOpcode() == ISD::BITCAST)
24016 Mask = Mask.getOperand(0);
24017 if (X.getOpcode() == ISD::BITCAST)
24018 X = X.getOperand(0);
24019 if (Y.getOpcode() == ISD::BITCAST)
24020 Y = Y.getOperand(0);
24022 EVT MaskVT = Mask.getValueType();
24024 // Validate that the Mask operand is a vector sra node.
24025 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24026 // there is no psrai.b
24027 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24028 unsigned SraAmt = ~0;
24029 if (Mask.getOpcode() == ISD::SRA) {
24030 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24031 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24032 SraAmt = AmtConst->getZExtValue();
24033 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24034 SDValue SraC = Mask.getOperand(1);
24035 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24037 if ((SraAmt + 1) != EltBits)
24042 // Now we know we at least have a plendvb with the mask val. See if
24043 // we can form a psignb/w/d.
24044 // psign = x.type == y.type == mask.type && y = sub(0, x);
24045 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24046 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24047 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24048 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24049 "Unsupported VT for PSIGN");
24050 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24051 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24053 // PBLENDVB only available on SSE 4.1
24054 if (!Subtarget->hasSSE41())
24057 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24059 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24060 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24061 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24062 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24063 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24067 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24070 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24071 MachineFunction &MF = DAG.getMachineFunction();
24072 bool OptForSize = MF.getFunction()->getAttributes().
24073 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24075 // SHLD/SHRD instructions have lower register pressure, but on some
24076 // platforms they have higher latency than the equivalent
24077 // series of shifts/or that would otherwise be generated.
24078 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24079 // have higher latencies and we are not optimizing for size.
24080 if (!OptForSize && Subtarget->isSHLDSlow())
24083 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24085 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24087 if (!N0.hasOneUse() || !N1.hasOneUse())
24090 SDValue ShAmt0 = N0.getOperand(1);
24091 if (ShAmt0.getValueType() != MVT::i8)
24093 SDValue ShAmt1 = N1.getOperand(1);
24094 if (ShAmt1.getValueType() != MVT::i8)
24096 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24097 ShAmt0 = ShAmt0.getOperand(0);
24098 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24099 ShAmt1 = ShAmt1.getOperand(0);
24102 unsigned Opc = X86ISD::SHLD;
24103 SDValue Op0 = N0.getOperand(0);
24104 SDValue Op1 = N1.getOperand(0);
24105 if (ShAmt0.getOpcode() == ISD::SUB) {
24106 Opc = X86ISD::SHRD;
24107 std::swap(Op0, Op1);
24108 std::swap(ShAmt0, ShAmt1);
24111 unsigned Bits = VT.getSizeInBits();
24112 if (ShAmt1.getOpcode() == ISD::SUB) {
24113 SDValue Sum = ShAmt1.getOperand(0);
24114 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24115 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24116 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24117 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24118 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24119 return DAG.getNode(Opc, DL, VT,
24121 DAG.getNode(ISD::TRUNCATE, DL,
24124 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24125 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24127 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24128 return DAG.getNode(Opc, DL, VT,
24129 N0.getOperand(0), N1.getOperand(0),
24130 DAG.getNode(ISD::TRUNCATE, DL,
24137 // Generate NEG and CMOV for integer abs.
24138 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24139 EVT VT = N->getValueType(0);
24141 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24142 // 8-bit integer abs to NEG and CMOV.
24143 if (VT.isInteger() && VT.getSizeInBits() == 8)
24146 SDValue N0 = N->getOperand(0);
24147 SDValue N1 = N->getOperand(1);
24150 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24151 // and change it to SUB and CMOV.
24152 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24153 N0.getOpcode() == ISD::ADD &&
24154 N0.getOperand(1) == N1 &&
24155 N1.getOpcode() == ISD::SRA &&
24156 N1.getOperand(0) == N0.getOperand(0))
24157 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24158 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24159 // Generate SUB & CMOV.
24160 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24161 DAG.getConstant(0, VT), N0.getOperand(0));
24163 SDValue Ops[] = { N0.getOperand(0), Neg,
24164 DAG.getConstant(X86::COND_GE, MVT::i8),
24165 SDValue(Neg.getNode(), 1) };
24166 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24171 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24172 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24173 TargetLowering::DAGCombinerInfo &DCI,
24174 const X86Subtarget *Subtarget) {
24175 if (DCI.isBeforeLegalizeOps())
24178 if (Subtarget->hasCMov()) {
24179 SDValue RV = performIntegerAbsCombine(N, DAG);
24187 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24188 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24189 TargetLowering::DAGCombinerInfo &DCI,
24190 const X86Subtarget *Subtarget) {
24191 LoadSDNode *Ld = cast<LoadSDNode>(N);
24192 EVT RegVT = Ld->getValueType(0);
24193 EVT MemVT = Ld->getMemoryVT();
24195 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24197 // On Sandybridge unaligned 256bit loads are inefficient.
24198 ISD::LoadExtType Ext = Ld->getExtensionType();
24199 unsigned Alignment = Ld->getAlignment();
24200 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24201 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
24202 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24203 unsigned NumElems = RegVT.getVectorNumElements();
24207 SDValue Ptr = Ld->getBasePtr();
24208 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24210 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24212 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24213 Ld->getPointerInfo(), Ld->isVolatile(),
24214 Ld->isNonTemporal(), Ld->isInvariant(),
24216 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24217 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24218 Ld->getPointerInfo(), Ld->isVolatile(),
24219 Ld->isNonTemporal(), Ld->isInvariant(),
24220 std::min(16U, Alignment));
24221 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24223 Load2.getValue(1));
24225 SDValue NewVec = DAG.getUNDEF(RegVT);
24226 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24227 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24228 return DCI.CombineTo(N, NewVec, TF, true);
24234 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24235 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24236 const X86Subtarget *Subtarget) {
24237 StoreSDNode *St = cast<StoreSDNode>(N);
24238 EVT VT = St->getValue().getValueType();
24239 EVT StVT = St->getMemoryVT();
24241 SDValue StoredVal = St->getOperand(1);
24242 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24244 // If we are saving a concatenation of two XMM registers, perform two stores.
24245 // On Sandy Bridge, 256-bit memory operations are executed by two
24246 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
24247 // memory operation.
24248 unsigned Alignment = St->getAlignment();
24249 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24250 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
24251 StVT == VT && !IsAligned) {
24252 unsigned NumElems = VT.getVectorNumElements();
24256 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24257 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24259 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24260 SDValue Ptr0 = St->getBasePtr();
24261 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24263 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24264 St->getPointerInfo(), St->isVolatile(),
24265 St->isNonTemporal(), Alignment);
24266 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24267 St->getPointerInfo(), St->isVolatile(),
24268 St->isNonTemporal(),
24269 std::min(16U, Alignment));
24270 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24273 // Optimize trunc store (of multiple scalars) to shuffle and store.
24274 // First, pack all of the elements in one place. Next, store to memory
24275 // in fewer chunks.
24276 if (St->isTruncatingStore() && VT.isVector()) {
24277 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24278 unsigned NumElems = VT.getVectorNumElements();
24279 assert(StVT != VT && "Cannot truncate to the same type");
24280 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24281 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24283 // From, To sizes and ElemCount must be pow of two
24284 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24285 // We are going to use the original vector elt for storing.
24286 // Accumulated smaller vector elements must be a multiple of the store size.
24287 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24289 unsigned SizeRatio = FromSz / ToSz;
24291 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24293 // Create a type on which we perform the shuffle
24294 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24295 StVT.getScalarType(), NumElems*SizeRatio);
24297 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24299 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24300 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24301 for (unsigned i = 0; i != NumElems; ++i)
24302 ShuffleVec[i] = i * SizeRatio;
24304 // Can't shuffle using an illegal type.
24305 if (!TLI.isTypeLegal(WideVecVT))
24308 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24309 DAG.getUNDEF(WideVecVT),
24311 // At this point all of the data is stored at the bottom of the
24312 // register. We now need to save it to mem.
24314 // Find the largest store unit
24315 MVT StoreType = MVT::i8;
24316 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24317 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24318 MVT Tp = (MVT::SimpleValueType)tp;
24319 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24323 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24324 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24325 (64 <= NumElems * ToSz))
24326 StoreType = MVT::f64;
24328 // Bitcast the original vector into a vector of store-size units
24329 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24330 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24331 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24332 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24333 SmallVector<SDValue, 8> Chains;
24334 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24335 TLI.getPointerTy());
24336 SDValue Ptr = St->getBasePtr();
24338 // Perform one or more big stores into memory.
24339 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24340 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24341 StoreType, ShuffWide,
24342 DAG.getIntPtrConstant(i));
24343 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24344 St->getPointerInfo(), St->isVolatile(),
24345 St->isNonTemporal(), St->getAlignment());
24346 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24347 Chains.push_back(Ch);
24350 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24353 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24354 // the FP state in cases where an emms may be missing.
24355 // A preferable solution to the general problem is to figure out the right
24356 // places to insert EMMS. This qualifies as a quick hack.
24358 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24359 if (VT.getSizeInBits() != 64)
24362 const Function *F = DAG.getMachineFunction().getFunction();
24363 bool NoImplicitFloatOps = F->getAttributes().
24364 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24365 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24366 && Subtarget->hasSSE2();
24367 if ((VT.isVector() ||
24368 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24369 isa<LoadSDNode>(St->getValue()) &&
24370 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24371 St->getChain().hasOneUse() && !St->isVolatile()) {
24372 SDNode* LdVal = St->getValue().getNode();
24373 LoadSDNode *Ld = nullptr;
24374 int TokenFactorIndex = -1;
24375 SmallVector<SDValue, 8> Ops;
24376 SDNode* ChainVal = St->getChain().getNode();
24377 // Must be a store of a load. We currently handle two cases: the load
24378 // is a direct child, and it's under an intervening TokenFactor. It is
24379 // possible to dig deeper under nested TokenFactors.
24380 if (ChainVal == LdVal)
24381 Ld = cast<LoadSDNode>(St->getChain());
24382 else if (St->getValue().hasOneUse() &&
24383 ChainVal->getOpcode() == ISD::TokenFactor) {
24384 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24385 if (ChainVal->getOperand(i).getNode() == LdVal) {
24386 TokenFactorIndex = i;
24387 Ld = cast<LoadSDNode>(St->getValue());
24389 Ops.push_back(ChainVal->getOperand(i));
24393 if (!Ld || !ISD::isNormalLoad(Ld))
24396 // If this is not the MMX case, i.e. we are just turning i64 load/store
24397 // into f64 load/store, avoid the transformation if there are multiple
24398 // uses of the loaded value.
24399 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24404 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24405 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24407 if (Subtarget->is64Bit() || F64IsLegal) {
24408 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24409 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24410 Ld->getPointerInfo(), Ld->isVolatile(),
24411 Ld->isNonTemporal(), Ld->isInvariant(),
24412 Ld->getAlignment());
24413 SDValue NewChain = NewLd.getValue(1);
24414 if (TokenFactorIndex != -1) {
24415 Ops.push_back(NewChain);
24416 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24418 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24419 St->getPointerInfo(),
24420 St->isVolatile(), St->isNonTemporal(),
24421 St->getAlignment());
24424 // Otherwise, lower to two pairs of 32-bit loads / stores.
24425 SDValue LoAddr = Ld->getBasePtr();
24426 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24427 DAG.getConstant(4, MVT::i32));
24429 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24430 Ld->getPointerInfo(),
24431 Ld->isVolatile(), Ld->isNonTemporal(),
24432 Ld->isInvariant(), Ld->getAlignment());
24433 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24434 Ld->getPointerInfo().getWithOffset(4),
24435 Ld->isVolatile(), Ld->isNonTemporal(),
24437 MinAlign(Ld->getAlignment(), 4));
24439 SDValue NewChain = LoLd.getValue(1);
24440 if (TokenFactorIndex != -1) {
24441 Ops.push_back(LoLd);
24442 Ops.push_back(HiLd);
24443 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24446 LoAddr = St->getBasePtr();
24447 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24448 DAG.getConstant(4, MVT::i32));
24450 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24451 St->getPointerInfo(),
24452 St->isVolatile(), St->isNonTemporal(),
24453 St->getAlignment());
24454 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24455 St->getPointerInfo().getWithOffset(4),
24457 St->isNonTemporal(),
24458 MinAlign(St->getAlignment(), 4));
24459 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24464 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24465 /// and return the operands for the horizontal operation in LHS and RHS. A
24466 /// horizontal operation performs the binary operation on successive elements
24467 /// of its first operand, then on successive elements of its second operand,
24468 /// returning the resulting values in a vector. For example, if
24469 /// A = < float a0, float a1, float a2, float a3 >
24471 /// B = < float b0, float b1, float b2, float b3 >
24472 /// then the result of doing a horizontal operation on A and B is
24473 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24474 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24475 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24476 /// set to A, RHS to B, and the routine returns 'true'.
24477 /// Note that the binary operation should have the property that if one of the
24478 /// operands is UNDEF then the result is UNDEF.
24479 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24480 // Look for the following pattern: if
24481 // A = < float a0, float a1, float a2, float a3 >
24482 // B = < float b0, float b1, float b2, float b3 >
24484 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24485 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24486 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24487 // which is A horizontal-op B.
24489 // At least one of the operands should be a vector shuffle.
24490 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24491 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24494 MVT VT = LHS.getSimpleValueType();
24496 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24497 "Unsupported vector type for horizontal add/sub");
24499 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24500 // operate independently on 128-bit lanes.
24501 unsigned NumElts = VT.getVectorNumElements();
24502 unsigned NumLanes = VT.getSizeInBits()/128;
24503 unsigned NumLaneElts = NumElts / NumLanes;
24504 assert((NumLaneElts % 2 == 0) &&
24505 "Vector type should have an even number of elements in each lane");
24506 unsigned HalfLaneElts = NumLaneElts/2;
24508 // View LHS in the form
24509 // LHS = VECTOR_SHUFFLE A, B, LMask
24510 // If LHS is not a shuffle then pretend it is the shuffle
24511 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24512 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24515 SmallVector<int, 16> LMask(NumElts);
24516 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24517 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24518 A = LHS.getOperand(0);
24519 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24520 B = LHS.getOperand(1);
24521 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24522 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24524 if (LHS.getOpcode() != ISD::UNDEF)
24526 for (unsigned i = 0; i != NumElts; ++i)
24530 // Likewise, view RHS in the form
24531 // RHS = VECTOR_SHUFFLE C, D, RMask
24533 SmallVector<int, 16> RMask(NumElts);
24534 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24535 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24536 C = RHS.getOperand(0);
24537 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24538 D = RHS.getOperand(1);
24539 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24540 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24542 if (RHS.getOpcode() != ISD::UNDEF)
24544 for (unsigned i = 0; i != NumElts; ++i)
24548 // Check that the shuffles are both shuffling the same vectors.
24549 if (!(A == C && B == D) && !(A == D && B == C))
24552 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24553 if (!A.getNode() && !B.getNode())
24556 // If A and B occur in reverse order in RHS, then "swap" them (which means
24557 // rewriting the mask).
24559 CommuteVectorShuffleMask(RMask, NumElts);
24561 // At this point LHS and RHS are equivalent to
24562 // LHS = VECTOR_SHUFFLE A, B, LMask
24563 // RHS = VECTOR_SHUFFLE A, B, RMask
24564 // Check that the masks correspond to performing a horizontal operation.
24565 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24566 for (unsigned i = 0; i != NumLaneElts; ++i) {
24567 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24569 // Ignore any UNDEF components.
24570 if (LIdx < 0 || RIdx < 0 ||
24571 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24572 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24575 // Check that successive elements are being operated on. If not, this is
24576 // not a horizontal operation.
24577 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24578 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24579 if (!(LIdx == Index && RIdx == Index + 1) &&
24580 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24585 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24586 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24590 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24591 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24592 const X86Subtarget *Subtarget) {
24593 EVT VT = N->getValueType(0);
24594 SDValue LHS = N->getOperand(0);
24595 SDValue RHS = N->getOperand(1);
24597 // Try to synthesize horizontal adds from adds of shuffles.
24598 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24599 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24600 isHorizontalBinOp(LHS, RHS, true))
24601 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24605 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24606 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24607 const X86Subtarget *Subtarget) {
24608 EVT VT = N->getValueType(0);
24609 SDValue LHS = N->getOperand(0);
24610 SDValue RHS = N->getOperand(1);
24612 // Try to synthesize horizontal subs from subs of shuffles.
24613 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24614 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24615 isHorizontalBinOp(LHS, RHS, false))
24616 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24620 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24621 /// X86ISD::FXOR nodes.
24622 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24623 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24624 // F[X]OR(0.0, x) -> x
24625 // F[X]OR(x, 0.0) -> x
24626 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24627 if (C->getValueAPF().isPosZero())
24628 return N->getOperand(1);
24629 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24630 if (C->getValueAPF().isPosZero())
24631 return N->getOperand(0);
24635 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24636 /// X86ISD::FMAX nodes.
24637 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24638 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24640 // Only perform optimizations if UnsafeMath is used.
24641 if (!DAG.getTarget().Options.UnsafeFPMath)
24644 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24645 // into FMINC and FMAXC, which are Commutative operations.
24646 unsigned NewOp = 0;
24647 switch (N->getOpcode()) {
24648 default: llvm_unreachable("unknown opcode");
24649 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24650 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24653 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24654 N->getOperand(0), N->getOperand(1));
24657 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24658 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24659 // FAND(0.0, x) -> 0.0
24660 // FAND(x, 0.0) -> 0.0
24661 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24662 if (C->getValueAPF().isPosZero())
24663 return N->getOperand(0);
24664 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24665 if (C->getValueAPF().isPosZero())
24666 return N->getOperand(1);
24670 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24671 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24672 // FANDN(x, 0.0) -> 0.0
24673 // FANDN(0.0, x) -> x
24674 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24675 if (C->getValueAPF().isPosZero())
24676 return N->getOperand(1);
24677 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24678 if (C->getValueAPF().isPosZero())
24679 return N->getOperand(1);
24683 static SDValue PerformBTCombine(SDNode *N,
24685 TargetLowering::DAGCombinerInfo &DCI) {
24686 // BT ignores high bits in the bit index operand.
24687 SDValue Op1 = N->getOperand(1);
24688 if (Op1.hasOneUse()) {
24689 unsigned BitWidth = Op1.getValueSizeInBits();
24690 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24691 APInt KnownZero, KnownOne;
24692 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24693 !DCI.isBeforeLegalizeOps());
24694 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24695 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24696 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24697 DCI.CommitTargetLoweringOpt(TLO);
24702 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24703 SDValue Op = N->getOperand(0);
24704 if (Op.getOpcode() == ISD::BITCAST)
24705 Op = Op.getOperand(0);
24706 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24707 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24708 VT.getVectorElementType().getSizeInBits() ==
24709 OpVT.getVectorElementType().getSizeInBits()) {
24710 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24715 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24716 const X86Subtarget *Subtarget) {
24717 EVT VT = N->getValueType(0);
24718 if (!VT.isVector())
24721 SDValue N0 = N->getOperand(0);
24722 SDValue N1 = N->getOperand(1);
24723 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24726 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24727 // both SSE and AVX2 since there is no sign-extended shift right
24728 // operation on a vector with 64-bit elements.
24729 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24730 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24731 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24732 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24733 SDValue N00 = N0.getOperand(0);
24735 // EXTLOAD has a better solution on AVX2,
24736 // it may be replaced with X86ISD::VSEXT node.
24737 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24738 if (!ISD::isNormalLoad(N00.getNode()))
24741 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24742 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24744 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24750 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24751 TargetLowering::DAGCombinerInfo &DCI,
24752 const X86Subtarget *Subtarget) {
24753 SDValue N0 = N->getOperand(0);
24754 EVT VT = N->getValueType(0);
24756 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24757 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24758 // This exposes the sext to the sdivrem lowering, so that it directly extends
24759 // from AH (which we otherwise need to do contortions to access).
24760 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24761 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24763 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24764 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24765 N0.getOperand(0), N0.getOperand(1));
24766 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24767 return R.getValue(1);
24770 if (!DCI.isBeforeLegalizeOps())
24773 if (!Subtarget->hasFp256())
24776 if (VT.isVector() && VT.getSizeInBits() == 256) {
24777 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24785 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24786 const X86Subtarget* Subtarget) {
24788 EVT VT = N->getValueType(0);
24790 // Let legalize expand this if it isn't a legal type yet.
24791 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24794 EVT ScalarVT = VT.getScalarType();
24795 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24796 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24799 SDValue A = N->getOperand(0);
24800 SDValue B = N->getOperand(1);
24801 SDValue C = N->getOperand(2);
24803 bool NegA = (A.getOpcode() == ISD::FNEG);
24804 bool NegB = (B.getOpcode() == ISD::FNEG);
24805 bool NegC = (C.getOpcode() == ISD::FNEG);
24807 // Negative multiplication when NegA xor NegB
24808 bool NegMul = (NegA != NegB);
24810 A = A.getOperand(0);
24812 B = B.getOperand(0);
24814 C = C.getOperand(0);
24818 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24820 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24822 return DAG.getNode(Opcode, dl, VT, A, B, C);
24825 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24826 TargetLowering::DAGCombinerInfo &DCI,
24827 const X86Subtarget *Subtarget) {
24828 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24829 // (and (i32 x86isd::setcc_carry), 1)
24830 // This eliminates the zext. This transformation is necessary because
24831 // ISD::SETCC is always legalized to i8.
24833 SDValue N0 = N->getOperand(0);
24834 EVT VT = N->getValueType(0);
24836 if (N0.getOpcode() == ISD::AND &&
24838 N0.getOperand(0).hasOneUse()) {
24839 SDValue N00 = N0.getOperand(0);
24840 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24841 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24842 if (!C || C->getZExtValue() != 1)
24844 return DAG.getNode(ISD::AND, dl, VT,
24845 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24846 N00.getOperand(0), N00.getOperand(1)),
24847 DAG.getConstant(1, VT));
24851 if (N0.getOpcode() == ISD::TRUNCATE &&
24853 N0.getOperand(0).hasOneUse()) {
24854 SDValue N00 = N0.getOperand(0);
24855 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24856 return DAG.getNode(ISD::AND, dl, VT,
24857 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24858 N00.getOperand(0), N00.getOperand(1)),
24859 DAG.getConstant(1, VT));
24862 if (VT.is256BitVector()) {
24863 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24868 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24869 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24870 // This exposes the zext to the udivrem lowering, so that it directly extends
24871 // from AH (which we otherwise need to do contortions to access).
24872 if (N0.getOpcode() == ISD::UDIVREM &&
24873 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24874 (VT == MVT::i32 || VT == MVT::i64)) {
24875 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24876 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24877 N0.getOperand(0), N0.getOperand(1));
24878 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24879 return R.getValue(1);
24885 // Optimize x == -y --> x+y == 0
24886 // x != -y --> x+y != 0
24887 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24888 const X86Subtarget* Subtarget) {
24889 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24890 SDValue LHS = N->getOperand(0);
24891 SDValue RHS = N->getOperand(1);
24892 EVT VT = N->getValueType(0);
24895 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24896 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24897 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24898 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24899 LHS.getValueType(), RHS, LHS.getOperand(1));
24900 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24901 addV, DAG.getConstant(0, addV.getValueType()), CC);
24903 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24904 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24905 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24906 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24907 RHS.getValueType(), LHS, RHS.getOperand(1));
24908 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24909 addV, DAG.getConstant(0, addV.getValueType()), CC);
24912 if (VT.getScalarType() == MVT::i1) {
24913 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24914 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24915 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24916 if (!IsSEXT0 && !IsVZero0)
24918 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24919 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24920 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24922 if (!IsSEXT1 && !IsVZero1)
24925 if (IsSEXT0 && IsVZero1) {
24926 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24927 if (CC == ISD::SETEQ)
24928 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24929 return LHS.getOperand(0);
24931 if (IsSEXT1 && IsVZero0) {
24932 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24933 if (CC == ISD::SETEQ)
24934 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24935 return RHS.getOperand(0);
24942 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24943 const X86Subtarget *Subtarget) {
24945 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24946 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24947 "X86insertps is only defined for v4x32");
24949 SDValue Ld = N->getOperand(1);
24950 if (MayFoldLoad(Ld)) {
24951 // Extract the countS bits from the immediate so we can get the proper
24952 // address when narrowing the vector load to a specific element.
24953 // When the second source op is a memory address, interps doesn't use
24954 // countS and just gets an f32 from that address.
24955 unsigned DestIndex =
24956 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24957 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24961 // Create this as a scalar to vector to match the instruction pattern.
24962 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24963 // countS bits are ignored when loading from memory on insertps, which
24964 // means we don't need to explicitly set them to 0.
24965 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24966 LoadScalarToVector, N->getOperand(2));
24969 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24970 // as "sbb reg,reg", since it can be extended without zext and produces
24971 // an all-ones bit which is more useful than 0/1 in some cases.
24972 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24975 return DAG.getNode(ISD::AND, DL, VT,
24976 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24977 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24978 DAG.getConstant(1, VT));
24979 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24980 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24981 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24982 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24985 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24986 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24987 TargetLowering::DAGCombinerInfo &DCI,
24988 const X86Subtarget *Subtarget) {
24990 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24991 SDValue EFLAGS = N->getOperand(1);
24993 if (CC == X86::COND_A) {
24994 // Try to convert COND_A into COND_B in an attempt to facilitate
24995 // materializing "setb reg".
24997 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24998 // cannot take an immediate as its first operand.
25000 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25001 EFLAGS.getValueType().isInteger() &&
25002 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25003 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25004 EFLAGS.getNode()->getVTList(),
25005 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25006 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25007 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25011 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25012 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25014 if (CC == X86::COND_B)
25015 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25019 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25020 if (Flags.getNode()) {
25021 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25022 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25028 // Optimize branch condition evaluation.
25030 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25031 TargetLowering::DAGCombinerInfo &DCI,
25032 const X86Subtarget *Subtarget) {
25034 SDValue Chain = N->getOperand(0);
25035 SDValue Dest = N->getOperand(1);
25036 SDValue EFLAGS = N->getOperand(3);
25037 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25041 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25042 if (Flags.getNode()) {
25043 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25044 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25051 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25052 SelectionDAG &DAG) {
25053 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25054 // optimize away operation when it's from a constant.
25056 // The general transformation is:
25057 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25058 // AND(VECTOR_CMP(x,y), constant2)
25059 // constant2 = UNARYOP(constant)
25061 // Early exit if this isn't a vector operation, the operand of the
25062 // unary operation isn't a bitwise AND, or if the sizes of the operations
25063 // aren't the same.
25064 EVT VT = N->getValueType(0);
25065 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25066 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25067 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25070 // Now check that the other operand of the AND is a constant. We could
25071 // make the transformation for non-constant splats as well, but it's unclear
25072 // that would be a benefit as it would not eliminate any operations, just
25073 // perform one more step in scalar code before moving to the vector unit.
25074 if (BuildVectorSDNode *BV =
25075 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25076 // Bail out if the vector isn't a constant.
25077 if (!BV->isConstant())
25080 // Everything checks out. Build up the new and improved node.
25082 EVT IntVT = BV->getValueType(0);
25083 // Create a new constant of the appropriate type for the transformed
25085 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25086 // The AND node needs bitcasts to/from an integer vector type around it.
25087 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25088 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25089 N->getOperand(0)->getOperand(0), MaskConst);
25090 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25097 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25098 const X86TargetLowering *XTLI) {
25099 // First try to optimize away the conversion entirely when it's
25100 // conditionally from a constant. Vectors only.
25101 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25102 if (Res != SDValue())
25105 // Now move on to more general possibilities.
25106 SDValue Op0 = N->getOperand(0);
25107 EVT InVT = Op0->getValueType(0);
25109 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25110 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25112 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25113 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25114 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25117 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25118 // a 32-bit target where SSE doesn't support i64->FP operations.
25119 if (Op0.getOpcode() == ISD::LOAD) {
25120 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25121 EVT VT = Ld->getValueType(0);
25122 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25123 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25124 !XTLI->getSubtarget()->is64Bit() &&
25126 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25127 Ld->getChain(), Op0, DAG);
25128 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25135 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25136 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25137 X86TargetLowering::DAGCombinerInfo &DCI) {
25138 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25139 // the result is either zero or one (depending on the input carry bit).
25140 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25141 if (X86::isZeroNode(N->getOperand(0)) &&
25142 X86::isZeroNode(N->getOperand(1)) &&
25143 // We don't have a good way to replace an EFLAGS use, so only do this when
25145 SDValue(N, 1).use_empty()) {
25147 EVT VT = N->getValueType(0);
25148 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25149 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25150 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25151 DAG.getConstant(X86::COND_B,MVT::i8),
25153 DAG.getConstant(1, VT));
25154 return DCI.CombineTo(N, Res1, CarryOut);
25160 // fold (add Y, (sete X, 0)) -> adc 0, Y
25161 // (add Y, (setne X, 0)) -> sbb -1, Y
25162 // (sub (sete X, 0), Y) -> sbb 0, Y
25163 // (sub (setne X, 0), Y) -> adc -1, Y
25164 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25167 // Look through ZExts.
25168 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25169 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25172 SDValue SetCC = Ext.getOperand(0);
25173 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25176 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25177 if (CC != X86::COND_E && CC != X86::COND_NE)
25180 SDValue Cmp = SetCC.getOperand(1);
25181 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25182 !X86::isZeroNode(Cmp.getOperand(1)) ||
25183 !Cmp.getOperand(0).getValueType().isInteger())
25186 SDValue CmpOp0 = Cmp.getOperand(0);
25187 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25188 DAG.getConstant(1, CmpOp0.getValueType()));
25190 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25191 if (CC == X86::COND_NE)
25192 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25193 DL, OtherVal.getValueType(), OtherVal,
25194 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25195 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25196 DL, OtherVal.getValueType(), OtherVal,
25197 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25200 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25201 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25202 const X86Subtarget *Subtarget) {
25203 EVT VT = N->getValueType(0);
25204 SDValue Op0 = N->getOperand(0);
25205 SDValue Op1 = N->getOperand(1);
25207 // Try to synthesize horizontal adds from adds of shuffles.
25208 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25209 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25210 isHorizontalBinOp(Op0, Op1, true))
25211 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25213 return OptimizeConditionalInDecrement(N, DAG);
25216 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25217 const X86Subtarget *Subtarget) {
25218 SDValue Op0 = N->getOperand(0);
25219 SDValue Op1 = N->getOperand(1);
25221 // X86 can't encode an immediate LHS of a sub. See if we can push the
25222 // negation into a preceding instruction.
25223 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25224 // If the RHS of the sub is a XOR with one use and a constant, invert the
25225 // immediate. Then add one to the LHS of the sub so we can turn
25226 // X-Y -> X+~Y+1, saving one register.
25227 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25228 isa<ConstantSDNode>(Op1.getOperand(1))) {
25229 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25230 EVT VT = Op0.getValueType();
25231 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25233 DAG.getConstant(~XorC, VT));
25234 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25235 DAG.getConstant(C->getAPIntValue()+1, VT));
25239 // Try to synthesize horizontal adds from adds of shuffles.
25240 EVT VT = N->getValueType(0);
25241 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25242 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25243 isHorizontalBinOp(Op0, Op1, true))
25244 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25246 return OptimizeConditionalInDecrement(N, DAG);
25249 /// performVZEXTCombine - Performs build vector combines
25250 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25251 TargetLowering::DAGCombinerInfo &DCI,
25252 const X86Subtarget *Subtarget) {
25254 MVT VT = N->getSimpleValueType(0);
25255 SDValue Op = N->getOperand(0);
25256 MVT OpVT = Op.getSimpleValueType();
25257 MVT OpEltVT = OpVT.getVectorElementType();
25258 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25260 // (vzext (bitcast (vzext (x)) -> (vzext x)
25262 while (V.getOpcode() == ISD::BITCAST)
25263 V = V.getOperand(0);
25265 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25266 MVT InnerVT = V.getSimpleValueType();
25267 MVT InnerEltVT = InnerVT.getVectorElementType();
25269 // If the element sizes match exactly, we can just do one larger vzext. This
25270 // is always an exact type match as vzext operates on integer types.
25271 if (OpEltVT == InnerEltVT) {
25272 assert(OpVT == InnerVT && "Types must match for vzext!");
25273 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25276 // The only other way we can combine them is if only a single element of the
25277 // inner vzext is used in the input to the outer vzext.
25278 if (InnerEltVT.getSizeInBits() < InputBits)
25281 // In this case, the inner vzext is completely dead because we're going to
25282 // only look at bits inside of the low element. Just do the outer vzext on
25283 // a bitcast of the input to the inner.
25284 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25285 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25288 // Check if we can bypass extracting and re-inserting an element of an input
25289 // vector. Essentialy:
25290 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25291 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25292 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25293 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25294 SDValue ExtractedV = V.getOperand(0);
25295 SDValue OrigV = ExtractedV.getOperand(0);
25296 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25297 if (ExtractIdx->getZExtValue() == 0) {
25298 MVT OrigVT = OrigV.getSimpleValueType();
25299 // Extract a subvector if necessary...
25300 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25301 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25302 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25303 OrigVT.getVectorNumElements() / Ratio);
25304 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25305 DAG.getIntPtrConstant(0));
25307 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25308 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25315 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25316 DAGCombinerInfo &DCI) const {
25317 SelectionDAG &DAG = DCI.DAG;
25318 switch (N->getOpcode()) {
25320 case ISD::EXTRACT_VECTOR_ELT:
25321 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25324 case X86ISD::SHRUNKBLEND:
25325 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25326 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25327 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25328 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25329 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25330 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25333 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25334 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25335 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25336 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25337 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25338 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25339 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25340 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25341 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25343 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25345 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25346 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25347 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25348 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25349 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25350 case ISD::ANY_EXTEND:
25351 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25352 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25353 case ISD::SIGN_EXTEND_INREG:
25354 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25355 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25356 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25357 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25358 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25359 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25360 case X86ISD::SHUFP: // Handle all target specific shuffles
25361 case X86ISD::PALIGNR:
25362 case X86ISD::UNPCKH:
25363 case X86ISD::UNPCKL:
25364 case X86ISD::MOVHLPS:
25365 case X86ISD::MOVLHPS:
25366 case X86ISD::PSHUFB:
25367 case X86ISD::PSHUFD:
25368 case X86ISD::PSHUFHW:
25369 case X86ISD::PSHUFLW:
25370 case X86ISD::MOVSS:
25371 case X86ISD::MOVSD:
25372 case X86ISD::VPERMILPI:
25373 case X86ISD::VPERM2X128:
25374 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25375 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25376 case ISD::INTRINSIC_WO_CHAIN:
25377 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25378 case X86ISD::INSERTPS:
25379 return PerformINSERTPSCombine(N, DAG, Subtarget);
25380 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25386 /// isTypeDesirableForOp - Return true if the target has native support for
25387 /// the specified value type and it is 'desirable' to use the type for the
25388 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25389 /// instruction encodings are longer and some i16 instructions are slow.
25390 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25391 if (!isTypeLegal(VT))
25393 if (VT != MVT::i16)
25400 case ISD::SIGN_EXTEND:
25401 case ISD::ZERO_EXTEND:
25402 case ISD::ANY_EXTEND:
25415 /// IsDesirableToPromoteOp - This method query the target whether it is
25416 /// beneficial for dag combiner to promote the specified node. If true, it
25417 /// should return the desired promotion type by reference.
25418 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25419 EVT VT = Op.getValueType();
25420 if (VT != MVT::i16)
25423 bool Promote = false;
25424 bool Commute = false;
25425 switch (Op.getOpcode()) {
25428 LoadSDNode *LD = cast<LoadSDNode>(Op);
25429 // If the non-extending load has a single use and it's not live out, then it
25430 // might be folded.
25431 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25432 Op.hasOneUse()*/) {
25433 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25434 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25435 // The only case where we'd want to promote LOAD (rather then it being
25436 // promoted as an operand is when it's only use is liveout.
25437 if (UI->getOpcode() != ISD::CopyToReg)
25444 case ISD::SIGN_EXTEND:
25445 case ISD::ZERO_EXTEND:
25446 case ISD::ANY_EXTEND:
25451 SDValue N0 = Op.getOperand(0);
25452 // Look out for (store (shl (load), x)).
25453 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25466 SDValue N0 = Op.getOperand(0);
25467 SDValue N1 = Op.getOperand(1);
25468 if (!Commute && MayFoldLoad(N1))
25470 // Avoid disabling potential load folding opportunities.
25471 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25473 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25483 //===----------------------------------------------------------------------===//
25484 // X86 Inline Assembly Support
25485 //===----------------------------------------------------------------------===//
25488 // Helper to match a string separated by whitespace.
25489 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25490 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25492 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25493 StringRef piece(*args[i]);
25494 if (!s.startswith(piece)) // Check if the piece matches.
25497 s = s.substr(piece.size());
25498 StringRef::size_type pos = s.find_first_not_of(" \t");
25499 if (pos == 0) // We matched a prefix.
25507 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25510 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25512 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25513 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25514 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25515 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25517 if (AsmPieces.size() == 3)
25519 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25526 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25527 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25529 std::string AsmStr = IA->getAsmString();
25531 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25532 if (!Ty || Ty->getBitWidth() % 16 != 0)
25535 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25536 SmallVector<StringRef, 4> AsmPieces;
25537 SplitString(AsmStr, AsmPieces, ";\n");
25539 switch (AsmPieces.size()) {
25540 default: return false;
25542 // FIXME: this should verify that we are targeting a 486 or better. If not,
25543 // we will turn this bswap into something that will be lowered to logical
25544 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25545 // lower so don't worry about this.
25547 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25548 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25549 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25550 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25551 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25552 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25553 // No need to check constraints, nothing other than the equivalent of
25554 // "=r,0" would be valid here.
25555 return IntrinsicLowering::LowerToByteSwap(CI);
25558 // rorw $$8, ${0:w} --> llvm.bswap.i16
25559 if (CI->getType()->isIntegerTy(16) &&
25560 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25561 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25562 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25564 const std::string &ConstraintsStr = IA->getConstraintString();
25565 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25566 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25567 if (clobbersFlagRegisters(AsmPieces))
25568 return IntrinsicLowering::LowerToByteSwap(CI);
25572 if (CI->getType()->isIntegerTy(32) &&
25573 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25574 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25575 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25576 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25578 const std::string &ConstraintsStr = IA->getConstraintString();
25579 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25580 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25581 if (clobbersFlagRegisters(AsmPieces))
25582 return IntrinsicLowering::LowerToByteSwap(CI);
25585 if (CI->getType()->isIntegerTy(64)) {
25586 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25587 if (Constraints.size() >= 2 &&
25588 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25589 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25590 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25591 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25592 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25593 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25594 return IntrinsicLowering::LowerToByteSwap(CI);
25602 /// getConstraintType - Given a constraint letter, return the type of
25603 /// constraint it is for this target.
25604 X86TargetLowering::ConstraintType
25605 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25606 if (Constraint.size() == 1) {
25607 switch (Constraint[0]) {
25618 return C_RegisterClass;
25642 return TargetLowering::getConstraintType(Constraint);
25645 /// Examine constraint type and operand type and determine a weight value.
25646 /// This object must already have been set up with the operand type
25647 /// and the current alternative constraint selected.
25648 TargetLowering::ConstraintWeight
25649 X86TargetLowering::getSingleConstraintMatchWeight(
25650 AsmOperandInfo &info, const char *constraint) const {
25651 ConstraintWeight weight = CW_Invalid;
25652 Value *CallOperandVal = info.CallOperandVal;
25653 // If we don't have a value, we can't do a match,
25654 // but allow it at the lowest weight.
25655 if (!CallOperandVal)
25657 Type *type = CallOperandVal->getType();
25658 // Look at the constraint type.
25659 switch (*constraint) {
25661 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25672 if (CallOperandVal->getType()->isIntegerTy())
25673 weight = CW_SpecificReg;
25678 if (type->isFloatingPointTy())
25679 weight = CW_SpecificReg;
25682 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25683 weight = CW_SpecificReg;
25687 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25688 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25689 weight = CW_Register;
25692 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25693 if (C->getZExtValue() <= 31)
25694 weight = CW_Constant;
25698 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25699 if (C->getZExtValue() <= 63)
25700 weight = CW_Constant;
25704 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25705 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25706 weight = CW_Constant;
25710 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25711 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25712 weight = CW_Constant;
25716 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25717 if (C->getZExtValue() <= 3)
25718 weight = CW_Constant;
25722 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25723 if (C->getZExtValue() <= 0xff)
25724 weight = CW_Constant;
25729 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25730 weight = CW_Constant;
25734 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25735 if ((C->getSExtValue() >= -0x80000000LL) &&
25736 (C->getSExtValue() <= 0x7fffffffLL))
25737 weight = CW_Constant;
25741 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25742 if (C->getZExtValue() <= 0xffffffff)
25743 weight = CW_Constant;
25750 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25751 /// with another that has more specific requirements based on the type of the
25752 /// corresponding operand.
25753 const char *X86TargetLowering::
25754 LowerXConstraint(EVT ConstraintVT) const {
25755 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25756 // 'f' like normal targets.
25757 if (ConstraintVT.isFloatingPoint()) {
25758 if (Subtarget->hasSSE2())
25760 if (Subtarget->hasSSE1())
25764 return TargetLowering::LowerXConstraint(ConstraintVT);
25767 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25768 /// vector. If it is invalid, don't add anything to Ops.
25769 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25770 std::string &Constraint,
25771 std::vector<SDValue>&Ops,
25772 SelectionDAG &DAG) const {
25775 // Only support length 1 constraints for now.
25776 if (Constraint.length() > 1) return;
25778 char ConstraintLetter = Constraint[0];
25779 switch (ConstraintLetter) {
25782 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25783 if (C->getZExtValue() <= 31) {
25784 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25790 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25791 if (C->getZExtValue() <= 63) {
25792 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25798 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25799 if (isInt<8>(C->getSExtValue())) {
25800 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25806 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25807 if (C->getZExtValue() <= 255) {
25808 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25814 // 32-bit signed value
25815 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25816 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25817 C->getSExtValue())) {
25818 // Widen to 64 bits here to get it sign extended.
25819 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25822 // FIXME gcc accepts some relocatable values here too, but only in certain
25823 // memory models; it's complicated.
25828 // 32-bit unsigned value
25829 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25830 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25831 C->getZExtValue())) {
25832 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25836 // FIXME gcc accepts some relocatable values here too, but only in certain
25837 // memory models; it's complicated.
25841 // Literal immediates are always ok.
25842 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25843 // Widen to 64 bits here to get it sign extended.
25844 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25848 // In any sort of PIC mode addresses need to be computed at runtime by
25849 // adding in a register or some sort of table lookup. These can't
25850 // be used as immediates.
25851 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25854 // If we are in non-pic codegen mode, we allow the address of a global (with
25855 // an optional displacement) to be used with 'i'.
25856 GlobalAddressSDNode *GA = nullptr;
25857 int64_t Offset = 0;
25859 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25861 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25862 Offset += GA->getOffset();
25864 } else if (Op.getOpcode() == ISD::ADD) {
25865 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25866 Offset += C->getZExtValue();
25867 Op = Op.getOperand(0);
25870 } else if (Op.getOpcode() == ISD::SUB) {
25871 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25872 Offset += -C->getZExtValue();
25873 Op = Op.getOperand(0);
25878 // Otherwise, this isn't something we can handle, reject it.
25882 const GlobalValue *GV = GA->getGlobal();
25883 // If we require an extra load to get this address, as in PIC mode, we
25884 // can't accept it.
25885 if (isGlobalStubReference(
25886 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25889 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25890 GA->getValueType(0), Offset);
25895 if (Result.getNode()) {
25896 Ops.push_back(Result);
25899 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25902 std::pair<unsigned, const TargetRegisterClass*>
25903 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25905 // First, see if this is a constraint that directly corresponds to an LLVM
25907 if (Constraint.size() == 1) {
25908 // GCC Constraint Letters
25909 switch (Constraint[0]) {
25911 // TODO: Slight differences here in allocation order and leaving
25912 // RIP in the class. Do they matter any more here than they do
25913 // in the normal allocation?
25914 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25915 if (Subtarget->is64Bit()) {
25916 if (VT == MVT::i32 || VT == MVT::f32)
25917 return std::make_pair(0U, &X86::GR32RegClass);
25918 if (VT == MVT::i16)
25919 return std::make_pair(0U, &X86::GR16RegClass);
25920 if (VT == MVT::i8 || VT == MVT::i1)
25921 return std::make_pair(0U, &X86::GR8RegClass);
25922 if (VT == MVT::i64 || VT == MVT::f64)
25923 return std::make_pair(0U, &X86::GR64RegClass);
25926 // 32-bit fallthrough
25927 case 'Q': // Q_REGS
25928 if (VT == MVT::i32 || VT == MVT::f32)
25929 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25930 if (VT == MVT::i16)
25931 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25932 if (VT == MVT::i8 || VT == MVT::i1)
25933 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25934 if (VT == MVT::i64)
25935 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25937 case 'r': // GENERAL_REGS
25938 case 'l': // INDEX_REGS
25939 if (VT == MVT::i8 || VT == MVT::i1)
25940 return std::make_pair(0U, &X86::GR8RegClass);
25941 if (VT == MVT::i16)
25942 return std::make_pair(0U, &X86::GR16RegClass);
25943 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25944 return std::make_pair(0U, &X86::GR32RegClass);
25945 return std::make_pair(0U, &X86::GR64RegClass);
25946 case 'R': // LEGACY_REGS
25947 if (VT == MVT::i8 || VT == MVT::i1)
25948 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25949 if (VT == MVT::i16)
25950 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25951 if (VT == MVT::i32 || !Subtarget->is64Bit())
25952 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25953 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25954 case 'f': // FP Stack registers.
25955 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25956 // value to the correct fpstack register class.
25957 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25958 return std::make_pair(0U, &X86::RFP32RegClass);
25959 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25960 return std::make_pair(0U, &X86::RFP64RegClass);
25961 return std::make_pair(0U, &X86::RFP80RegClass);
25962 case 'y': // MMX_REGS if MMX allowed.
25963 if (!Subtarget->hasMMX()) break;
25964 return std::make_pair(0U, &X86::VR64RegClass);
25965 case 'Y': // SSE_REGS if SSE2 allowed
25966 if (!Subtarget->hasSSE2()) break;
25968 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25969 if (!Subtarget->hasSSE1()) break;
25971 switch (VT.SimpleTy) {
25973 // Scalar SSE types.
25976 return std::make_pair(0U, &X86::FR32RegClass);
25979 return std::make_pair(0U, &X86::FR64RegClass);
25987 return std::make_pair(0U, &X86::VR128RegClass);
25995 return std::make_pair(0U, &X86::VR256RegClass);
26000 return std::make_pair(0U, &X86::VR512RegClass);
26006 // Use the default implementation in TargetLowering to convert the register
26007 // constraint into a member of a register class.
26008 std::pair<unsigned, const TargetRegisterClass*> Res;
26009 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26011 // Not found as a standard register?
26013 // Map st(0) -> st(7) -> ST0
26014 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26015 tolower(Constraint[1]) == 's' &&
26016 tolower(Constraint[2]) == 't' &&
26017 Constraint[3] == '(' &&
26018 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26019 Constraint[5] == ')' &&
26020 Constraint[6] == '}') {
26022 Res.first = X86::FP0+Constraint[4]-'0';
26023 Res.second = &X86::RFP80RegClass;
26027 // GCC allows "st(0)" to be called just plain "st".
26028 if (StringRef("{st}").equals_lower(Constraint)) {
26029 Res.first = X86::FP0;
26030 Res.second = &X86::RFP80RegClass;
26035 if (StringRef("{flags}").equals_lower(Constraint)) {
26036 Res.first = X86::EFLAGS;
26037 Res.second = &X86::CCRRegClass;
26041 // 'A' means EAX + EDX.
26042 if (Constraint == "A") {
26043 Res.first = X86::EAX;
26044 Res.second = &X86::GR32_ADRegClass;
26050 // Otherwise, check to see if this is a register class of the wrong value
26051 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26052 // turn into {ax},{dx}.
26053 if (Res.second->hasType(VT))
26054 return Res; // Correct type already, nothing to do.
26056 // All of the single-register GCC register classes map their values onto
26057 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26058 // really want an 8-bit or 32-bit register, map to the appropriate register
26059 // class and return the appropriate register.
26060 if (Res.second == &X86::GR16RegClass) {
26061 if (VT == MVT::i8 || VT == MVT::i1) {
26062 unsigned DestReg = 0;
26063 switch (Res.first) {
26065 case X86::AX: DestReg = X86::AL; break;
26066 case X86::DX: DestReg = X86::DL; break;
26067 case X86::CX: DestReg = X86::CL; break;
26068 case X86::BX: DestReg = X86::BL; break;
26071 Res.first = DestReg;
26072 Res.second = &X86::GR8RegClass;
26074 } else if (VT == MVT::i32 || VT == MVT::f32) {
26075 unsigned DestReg = 0;
26076 switch (Res.first) {
26078 case X86::AX: DestReg = X86::EAX; break;
26079 case X86::DX: DestReg = X86::EDX; break;
26080 case X86::CX: DestReg = X86::ECX; break;
26081 case X86::BX: DestReg = X86::EBX; break;
26082 case X86::SI: DestReg = X86::ESI; break;
26083 case X86::DI: DestReg = X86::EDI; break;
26084 case X86::BP: DestReg = X86::EBP; break;
26085 case X86::SP: DestReg = X86::ESP; break;
26088 Res.first = DestReg;
26089 Res.second = &X86::GR32RegClass;
26091 } else if (VT == MVT::i64 || VT == MVT::f64) {
26092 unsigned DestReg = 0;
26093 switch (Res.first) {
26095 case X86::AX: DestReg = X86::RAX; break;
26096 case X86::DX: DestReg = X86::RDX; break;
26097 case X86::CX: DestReg = X86::RCX; break;
26098 case X86::BX: DestReg = X86::RBX; break;
26099 case X86::SI: DestReg = X86::RSI; break;
26100 case X86::DI: DestReg = X86::RDI; break;
26101 case X86::BP: DestReg = X86::RBP; break;
26102 case X86::SP: DestReg = X86::RSP; break;
26105 Res.first = DestReg;
26106 Res.second = &X86::GR64RegClass;
26109 } else if (Res.second == &X86::FR32RegClass ||
26110 Res.second == &X86::FR64RegClass ||
26111 Res.second == &X86::VR128RegClass ||
26112 Res.second == &X86::VR256RegClass ||
26113 Res.second == &X86::FR32XRegClass ||
26114 Res.second == &X86::FR64XRegClass ||
26115 Res.second == &X86::VR128XRegClass ||
26116 Res.second == &X86::VR256XRegClass ||
26117 Res.second == &X86::VR512RegClass) {
26118 // Handle references to XMM physical registers that got mapped into the
26119 // wrong class. This can happen with constraints like {xmm0} where the
26120 // target independent register mapper will just pick the first match it can
26121 // find, ignoring the required type.
26123 if (VT == MVT::f32 || VT == MVT::i32)
26124 Res.second = &X86::FR32RegClass;
26125 else if (VT == MVT::f64 || VT == MVT::i64)
26126 Res.second = &X86::FR64RegClass;
26127 else if (X86::VR128RegClass.hasType(VT))
26128 Res.second = &X86::VR128RegClass;
26129 else if (X86::VR256RegClass.hasType(VT))
26130 Res.second = &X86::VR256RegClass;
26131 else if (X86::VR512RegClass.hasType(VT))
26132 Res.second = &X86::VR512RegClass;
26138 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26140 // Scaling factors are not free at all.
26141 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26142 // will take 2 allocations in the out of order engine instead of 1
26143 // for plain addressing mode, i.e. inst (reg1).
26145 // vaddps (%rsi,%drx), %ymm0, %ymm1
26146 // Requires two allocations (one for the load, one for the computation)
26148 // vaddps (%rsi), %ymm0, %ymm1
26149 // Requires just 1 allocation, i.e., freeing allocations for other operations
26150 // and having less micro operations to execute.
26152 // For some X86 architectures, this is even worse because for instance for
26153 // stores, the complex addressing mode forces the instruction to use the
26154 // "load" ports instead of the dedicated "store" port.
26155 // E.g., on Haswell:
26156 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26157 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26158 if (isLegalAddressingMode(AM, Ty))
26159 // Scale represents reg2 * scale, thus account for 1
26160 // as soon as we use a second register.
26161 return AM.Scale != 0;
26165 bool X86TargetLowering::isTargetFTOL() const {
26166 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();