1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1563 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1566 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1567 // of this type with custom code.
1568 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1569 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1570 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1574 // We want to custom lower some of our intrinsics.
1575 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1577 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1578 if (!Subtarget->is64Bit())
1579 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1581 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1582 // handle type legalization for these operations here.
1584 // FIXME: We really should do custom legalization for addition and
1585 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1586 // than generic legalization for 64-bit multiplication-with-overflow, though.
1587 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1588 // Add/Sub/Mul with overflow operations are custom lowered.
1590 setOperationAction(ISD::SADDO, VT, Custom);
1591 setOperationAction(ISD::UADDO, VT, Custom);
1592 setOperationAction(ISD::SSUBO, VT, Custom);
1593 setOperationAction(ISD::USUBO, VT, Custom);
1594 setOperationAction(ISD::SMULO, VT, Custom);
1595 setOperationAction(ISD::UMULO, VT, Custom);
1598 // There are no 8-bit 3-address imul/mul instructions
1599 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1600 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1602 if (!Subtarget->is64Bit()) {
1603 // These libcalls are not available in 32-bit.
1604 setLibcallName(RTLIB::SHL_I128, nullptr);
1605 setLibcallName(RTLIB::SRL_I128, nullptr);
1606 setLibcallName(RTLIB::SRA_I128, nullptr);
1609 // Combine sin / cos into one node or libcall if possible.
1610 if (Subtarget->hasSinCos()) {
1611 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1612 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1613 if (Subtarget->isTargetDarwin()) {
1614 // For MacOSX, we don't want to the normal expansion of a libcall to
1615 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1617 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1618 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1622 if (Subtarget->isTargetWin64()) {
1623 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1625 setOperationAction(ISD::SREM, MVT::i128, Custom);
1626 setOperationAction(ISD::UREM, MVT::i128, Custom);
1627 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1628 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1631 // We have target-specific dag combine patterns for the following nodes:
1632 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1633 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1634 setTargetDAGCombine(ISD::VSELECT);
1635 setTargetDAGCombine(ISD::SELECT);
1636 setTargetDAGCombine(ISD::SHL);
1637 setTargetDAGCombine(ISD::SRA);
1638 setTargetDAGCombine(ISD::SRL);
1639 setTargetDAGCombine(ISD::OR);
1640 setTargetDAGCombine(ISD::AND);
1641 setTargetDAGCombine(ISD::ADD);
1642 setTargetDAGCombine(ISD::FADD);
1643 setTargetDAGCombine(ISD::FSUB);
1644 setTargetDAGCombine(ISD::FMA);
1645 setTargetDAGCombine(ISD::SUB);
1646 setTargetDAGCombine(ISD::LOAD);
1647 setTargetDAGCombine(ISD::STORE);
1648 setTargetDAGCombine(ISD::ZERO_EXTEND);
1649 setTargetDAGCombine(ISD::ANY_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND);
1651 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1652 setTargetDAGCombine(ISD::TRUNCATE);
1653 setTargetDAGCombine(ISD::SINT_TO_FP);
1654 setTargetDAGCombine(ISD::SETCC);
1655 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1656 setTargetDAGCombine(ISD::BUILD_VECTOR);
1657 if (Subtarget->is64Bit())
1658 setTargetDAGCombine(ISD::MUL);
1659 setTargetDAGCombine(ISD::XOR);
1661 computeRegisterProperties();
1663 // On Darwin, -Os means optimize for size without hurting performance,
1664 // do not reduce the limit.
1665 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1666 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1667 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1668 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1669 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1670 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1671 setPrefLoopAlignment(4); // 2^4 bytes.
1673 // Predictable cmov don't hurt on atom because it's in-order.
1674 PredictableSelectIsExpensive = !Subtarget->isAtom();
1676 setPrefFunctionAlignment(4); // 2^4 bytes.
1678 verifyIntrinsicTables();
1681 // This has so far only been implemented for 64-bit MachO.
1682 bool X86TargetLowering::useLoadStackGuardNode() const {
1683 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1684 Subtarget->is64Bit();
1687 TargetLoweringBase::LegalizeTypeAction
1688 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1689 if (ExperimentalVectorWideningLegalization &&
1690 VT.getVectorNumElements() != 1 &&
1691 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1692 return TypeWidenVector;
1694 return TargetLoweringBase::getPreferredVectorAction(VT);
1697 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1699 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1701 const unsigned NumElts = VT.getVectorNumElements();
1702 const EVT EltVT = VT.getVectorElementType();
1703 if (VT.is512BitVector()) {
1704 if (Subtarget->hasAVX512())
1705 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1706 EltVT == MVT::f32 || EltVT == MVT::f64)
1708 case 8: return MVT::v8i1;
1709 case 16: return MVT::v16i1;
1711 if (Subtarget->hasBWI())
1712 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1714 case 32: return MVT::v32i1;
1715 case 64: return MVT::v64i1;
1719 if (VT.is256BitVector() || VT.is128BitVector()) {
1720 if (Subtarget->hasVLX())
1721 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1722 EltVT == MVT::f32 || EltVT == MVT::f64)
1724 case 2: return MVT::v2i1;
1725 case 4: return MVT::v4i1;
1726 case 8: return MVT::v8i1;
1728 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1729 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1731 case 8: return MVT::v8i1;
1732 case 16: return MVT::v16i1;
1733 case 32: return MVT::v32i1;
1737 return VT.changeVectorElementTypeToInteger();
1740 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1741 /// the desired ByVal argument alignment.
1742 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1745 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1746 if (VTy->getBitWidth() == 128)
1748 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1749 unsigned EltAlign = 0;
1750 getMaxByValAlign(ATy->getElementType(), EltAlign);
1751 if (EltAlign > MaxAlign)
1752 MaxAlign = EltAlign;
1753 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1754 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1755 unsigned EltAlign = 0;
1756 getMaxByValAlign(STy->getElementType(i), EltAlign);
1757 if (EltAlign > MaxAlign)
1758 MaxAlign = EltAlign;
1765 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1766 /// function arguments in the caller parameter area. For X86, aggregates
1767 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1768 /// are at 4-byte boundaries.
1769 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1770 if (Subtarget->is64Bit()) {
1771 // Max of 8 and alignment of type.
1772 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1779 if (Subtarget->hasSSE1())
1780 getMaxByValAlign(Ty, Align);
1784 /// getOptimalMemOpType - Returns the target specific optimal type for load
1785 /// and store operations as a result of memset, memcpy, and memmove
1786 /// lowering. If DstAlign is zero that means it's safe to destination
1787 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1788 /// means there isn't a need to check it against alignment requirement,
1789 /// probably because the source does not need to be loaded. If 'IsMemset' is
1790 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1791 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1792 /// source is constant so it does not need to be loaded.
1793 /// It returns EVT::Other if the type should be determined using generic
1794 /// target-independent logic.
1796 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1797 unsigned DstAlign, unsigned SrcAlign,
1798 bool IsMemset, bool ZeroMemset,
1800 MachineFunction &MF) const {
1801 const Function *F = MF.getFunction();
1802 if ((!IsMemset || ZeroMemset) &&
1803 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1804 Attribute::NoImplicitFloat)) {
1806 (Subtarget->isUnalignedMemAccessFast() ||
1807 ((DstAlign == 0 || DstAlign >= 16) &&
1808 (SrcAlign == 0 || SrcAlign >= 16)))) {
1810 if (Subtarget->hasInt256())
1812 if (Subtarget->hasFp256())
1815 if (Subtarget->hasSSE2())
1817 if (Subtarget->hasSSE1())
1819 } else if (!MemcpyStrSrc && Size >= 8 &&
1820 !Subtarget->is64Bit() &&
1821 Subtarget->hasSSE2()) {
1822 // Do not use f64 to lower memcpy if source is string constant. It's
1823 // better to use i32 to avoid the loads.
1827 if (Subtarget->is64Bit() && Size >= 8)
1832 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1834 return X86ScalarSSEf32;
1835 else if (VT == MVT::f64)
1836 return X86ScalarSSEf64;
1841 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1846 *Fast = Subtarget->isUnalignedMemAccessFast();
1850 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1851 /// current function. The returned value is a member of the
1852 /// MachineJumpTableInfo::JTEntryKind enum.
1853 unsigned X86TargetLowering::getJumpTableEncoding() const {
1854 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1856 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1857 Subtarget->isPICStyleGOT())
1858 return MachineJumpTableInfo::EK_Custom32;
1860 // Otherwise, use the normal jump table encoding heuristics.
1861 return TargetLowering::getJumpTableEncoding();
1865 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1866 const MachineBasicBlock *MBB,
1867 unsigned uid,MCContext &Ctx) const{
1868 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1869 Subtarget->isPICStyleGOT());
1870 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1872 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1873 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1876 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1878 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1879 SelectionDAG &DAG) const {
1880 if (!Subtarget->is64Bit())
1881 // This doesn't have SDLoc associated with it, but is not really the
1882 // same as a Register.
1883 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1887 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1888 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1890 const MCExpr *X86TargetLowering::
1891 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1892 MCContext &Ctx) const {
1893 // X86-64 uses RIP relative addressing based on the jump table label.
1894 if (Subtarget->isPICStyleRIPRel())
1895 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1897 // Otherwise, the reference is relative to the PIC base.
1898 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1901 // FIXME: Why this routine is here? Move to RegInfo!
1902 std::pair<const TargetRegisterClass*, uint8_t>
1903 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1904 const TargetRegisterClass *RRC = nullptr;
1906 switch (VT.SimpleTy) {
1908 return TargetLowering::findRepresentativeClass(VT);
1909 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1910 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1913 RRC = &X86::VR64RegClass;
1915 case MVT::f32: case MVT::f64:
1916 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1917 case MVT::v4f32: case MVT::v2f64:
1918 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1920 RRC = &X86::VR128RegClass;
1923 return std::make_pair(RRC, Cost);
1926 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1927 unsigned &Offset) const {
1928 if (!Subtarget->isTargetLinux())
1931 if (Subtarget->is64Bit()) {
1932 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1934 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1946 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1947 unsigned DestAS) const {
1948 assert(SrcAS != DestAS && "Expected different address spaces!");
1950 return SrcAS < 256 && DestAS < 256;
1953 //===----------------------------------------------------------------------===//
1954 // Return Value Calling Convention Implementation
1955 //===----------------------------------------------------------------------===//
1957 #include "X86GenCallingConv.inc"
1960 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1961 MachineFunction &MF, bool isVarArg,
1962 const SmallVectorImpl<ISD::OutputArg> &Outs,
1963 LLVMContext &Context) const {
1964 SmallVector<CCValAssign, 16> RVLocs;
1965 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1966 return CCInfo.CheckReturn(Outs, RetCC_X86);
1969 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1970 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1975 X86TargetLowering::LowerReturn(SDValue Chain,
1976 CallingConv::ID CallConv, bool isVarArg,
1977 const SmallVectorImpl<ISD::OutputArg> &Outs,
1978 const SmallVectorImpl<SDValue> &OutVals,
1979 SDLoc dl, SelectionDAG &DAG) const {
1980 MachineFunction &MF = DAG.getMachineFunction();
1981 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1983 SmallVector<CCValAssign, 16> RVLocs;
1984 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1985 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1988 SmallVector<SDValue, 6> RetOps;
1989 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1990 // Operand #1 = Bytes To Pop
1991 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1994 // Copy the result values into the output registers.
1995 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1996 CCValAssign &VA = RVLocs[i];
1997 assert(VA.isRegLoc() && "Can only return in registers!");
1998 SDValue ValToCopy = OutVals[i];
1999 EVT ValVT = ValToCopy.getValueType();
2001 // Promote values to the appropriate types
2002 if (VA.getLocInfo() == CCValAssign::SExt)
2003 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::ZExt)
2005 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2006 else if (VA.getLocInfo() == CCValAssign::AExt)
2007 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2008 else if (VA.getLocInfo() == CCValAssign::BCvt)
2009 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2011 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2012 "Unexpected FP-extend for return value.");
2014 // If this is x86-64, and we disabled SSE, we can't return FP values,
2015 // or SSE or MMX vectors.
2016 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2017 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2018 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2019 report_fatal_error("SSE register return with SSE disabled");
2021 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2022 // llvm-gcc has never done it right and no one has noticed, so this
2023 // should be OK for now.
2024 if (ValVT == MVT::f64 &&
2025 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2026 report_fatal_error("SSE2 register return with SSE2 disabled");
2028 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2029 // the RET instruction and handled by the FP Stackifier.
2030 if (VA.getLocReg() == X86::FP0 ||
2031 VA.getLocReg() == X86::FP1) {
2032 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2033 // change the value to the FP stack register class.
2034 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2035 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2036 RetOps.push_back(ValToCopy);
2037 // Don't emit a copytoreg.
2041 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2042 // which is returned in RAX / RDX.
2043 if (Subtarget->is64Bit()) {
2044 if (ValVT == MVT::x86mmx) {
2045 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2046 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2047 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2049 // If we don't have SSE2 available, convert to v4f32 so the generated
2050 // register is legal.
2051 if (!Subtarget->hasSSE2())
2052 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2057 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2058 Flag = Chain.getValue(1);
2059 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2062 // The x86-64 ABIs require that for returning structs by value we copy
2063 // the sret argument into %rax/%eax (depending on ABI) for the return.
2064 // Win32 requires us to put the sret argument to %eax as well.
2065 // We saved the argument into a virtual register in the entry block,
2066 // so now we copy the value out and into %rax/%eax.
2067 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2068 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2069 MachineFunction &MF = DAG.getMachineFunction();
2070 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2071 unsigned Reg = FuncInfo->getSRetReturnReg();
2073 "SRetReturnReg should have been set in LowerFormalArguments().");
2074 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2077 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2078 X86::RAX : X86::EAX;
2079 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2080 Flag = Chain.getValue(1);
2082 // RAX/EAX now acts like a return value.
2083 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2086 RetOps[0] = Chain; // Update chain.
2088 // Add the flag if we have it.
2090 RetOps.push_back(Flag);
2092 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2095 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2096 if (N->getNumValues() != 1)
2098 if (!N->hasNUsesOfValue(1, 0))
2101 SDValue TCChain = Chain;
2102 SDNode *Copy = *N->use_begin();
2103 if (Copy->getOpcode() == ISD::CopyToReg) {
2104 // If the copy has a glue operand, we conservatively assume it isn't safe to
2105 // perform a tail call.
2106 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2108 TCChain = Copy->getOperand(0);
2109 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2112 bool HasRet = false;
2113 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2115 if (UI->getOpcode() != X86ISD::RET_FLAG)
2117 // If we are returning more than one value, we can definitely
2118 // not make a tail call see PR19530
2119 if (UI->getNumOperands() > 4)
2121 if (UI->getNumOperands() == 4 &&
2122 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2135 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2136 ISD::NodeType ExtendKind) const {
2138 // TODO: Is this also valid on 32-bit?
2139 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2140 ReturnMVT = MVT::i8;
2142 ReturnMVT = MVT::i32;
2144 EVT MinVT = getRegisterType(Context, ReturnMVT);
2145 return VT.bitsLT(MinVT) ? MinVT : VT;
2148 /// LowerCallResult - Lower the result values of a call into the
2149 /// appropriate copies out of appropriate physical registers.
2152 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2153 CallingConv::ID CallConv, bool isVarArg,
2154 const SmallVectorImpl<ISD::InputArg> &Ins,
2155 SDLoc dl, SelectionDAG &DAG,
2156 SmallVectorImpl<SDValue> &InVals) const {
2158 // Assign locations to each value returned by this call.
2159 SmallVector<CCValAssign, 16> RVLocs;
2160 bool Is64Bit = Subtarget->is64Bit();
2161 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2163 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2165 // Copy all of the result registers out of their specified physreg.
2166 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2167 CCValAssign &VA = RVLocs[i];
2168 EVT CopyVT = VA.getValVT();
2170 // If this is x86-64, and we disabled SSE, we can't return FP values
2171 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2172 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2173 report_fatal_error("SSE register return with SSE disabled");
2176 // If we prefer to use the value in xmm registers, copy it out as f80 and
2177 // use a truncate to move it from fp stack reg to xmm reg.
2178 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2179 isScalarFPTypeInSSEReg(VA.getValVT()))
2182 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2183 CopyVT, InFlag).getValue(1);
2184 SDValue Val = Chain.getValue(0);
2186 if (CopyVT != VA.getValVT())
2187 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2188 // This truncation won't change the value.
2189 DAG.getIntPtrConstant(1));
2191 InFlag = Chain.getValue(2);
2192 InVals.push_back(Val);
2198 //===----------------------------------------------------------------------===//
2199 // C & StdCall & Fast Calling Convention implementation
2200 //===----------------------------------------------------------------------===//
2201 // StdCall calling convention seems to be standard for many Windows' API
2202 // routines and around. It differs from C calling convention just a little:
2203 // callee should clean up the stack, not caller. Symbols should be also
2204 // decorated in some fancy way :) It doesn't support any vector arguments.
2205 // For info on fast calling convention see Fast Calling Convention (tail call)
2206 // implementation LowerX86_32FastCCCallTo.
2208 /// CallIsStructReturn - Determines whether a call uses struct return
2210 enum StructReturnType {
2215 static StructReturnType
2216 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2218 return NotStructReturn;
2220 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2221 if (!Flags.isSRet())
2222 return NotStructReturn;
2223 if (Flags.isInReg())
2224 return RegStructReturn;
2225 return StackStructReturn;
2228 /// ArgsAreStructReturn - Determines whether a function uses struct
2229 /// return semantics.
2230 static StructReturnType
2231 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2233 return NotStructReturn;
2235 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2236 if (!Flags.isSRet())
2237 return NotStructReturn;
2238 if (Flags.isInReg())
2239 return RegStructReturn;
2240 return StackStructReturn;
2243 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2244 /// by "Src" to address "Dst" with size and alignment information specified by
2245 /// the specific parameter attribute. The copy will be passed as a byval
2246 /// function parameter.
2248 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2249 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2251 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2253 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2254 /*isVolatile*/false, /*AlwaysInline=*/true,
2255 MachinePointerInfo(), MachinePointerInfo());
2258 /// IsTailCallConvention - Return true if the calling convention is one that
2259 /// supports tail call optimization.
2260 static bool IsTailCallConvention(CallingConv::ID CC) {
2261 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2262 CC == CallingConv::HiPE);
2265 /// \brief Return true if the calling convention is a C calling convention.
2266 static bool IsCCallConvention(CallingConv::ID CC) {
2267 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2268 CC == CallingConv::X86_64_SysV);
2271 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2272 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2276 CallingConv::ID CalleeCC = CS.getCallingConv();
2277 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2283 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2284 /// a tailcall target by changing its ABI.
2285 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2286 bool GuaranteedTailCallOpt) {
2287 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2291 X86TargetLowering::LowerMemArgument(SDValue Chain,
2292 CallingConv::ID CallConv,
2293 const SmallVectorImpl<ISD::InputArg> &Ins,
2294 SDLoc dl, SelectionDAG &DAG,
2295 const CCValAssign &VA,
2296 MachineFrameInfo *MFI,
2298 // Create the nodes corresponding to a load from this parameter slot.
2299 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2300 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2301 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2302 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2305 // If value is passed by pointer we have address passed instead of the value
2307 if (VA.getLocInfo() == CCValAssign::Indirect)
2308 ValVT = VA.getLocVT();
2310 ValVT = VA.getValVT();
2312 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2313 // changed with more analysis.
2314 // In case of tail call optimization mark all arguments mutable. Since they
2315 // could be overwritten by lowering of arguments in case of a tail call.
2316 if (Flags.isByVal()) {
2317 unsigned Bytes = Flags.getByValSize();
2318 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2319 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2320 return DAG.getFrameIndex(FI, getPointerTy());
2322 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2323 VA.getLocMemOffset(), isImmutable);
2324 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2325 return DAG.getLoad(ValVT, dl, Chain, FIN,
2326 MachinePointerInfo::getFixedStack(FI),
2327 false, false, false, 0);
2331 // FIXME: Get this from tablegen.
2332 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2333 const X86Subtarget *Subtarget) {
2334 assert(Subtarget->is64Bit());
2336 if (Subtarget->isCallingConvWin64(CallConv)) {
2337 static const MCPhysReg GPR64ArgRegsWin64[] = {
2338 X86::RCX, X86::RDX, X86::R8, X86::R9
2340 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2343 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2344 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2346 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2349 // FIXME: Get this from tablegen.
2350 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2351 CallingConv::ID CallConv,
2352 const X86Subtarget *Subtarget) {
2353 assert(Subtarget->is64Bit());
2354 if (Subtarget->isCallingConvWin64(CallConv)) {
2355 // The XMM registers which might contain var arg parameters are shadowed
2356 // in their paired GPR. So we only need to save the GPR to their home
2358 // TODO: __vectorcall will change this.
2362 const Function *Fn = MF.getFunction();
2363 bool NoImplicitFloatOps = Fn->getAttributes().
2364 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2365 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2366 "SSE register cannot be used when SSE is disabled!");
2367 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2368 !Subtarget->hasSSE1())
2369 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2373 static const MCPhysReg XMMArgRegs64Bit[] = {
2374 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2375 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2377 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2381 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2382 CallingConv::ID CallConv,
2384 const SmallVectorImpl<ISD::InputArg> &Ins,
2387 SmallVectorImpl<SDValue> &InVals)
2389 MachineFunction &MF = DAG.getMachineFunction();
2390 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2392 const Function* Fn = MF.getFunction();
2393 if (Fn->hasExternalLinkage() &&
2394 Subtarget->isTargetCygMing() &&
2395 Fn->getName() == "main")
2396 FuncInfo->setForceFramePointer(true);
2398 MachineFrameInfo *MFI = MF.getFrameInfo();
2399 bool Is64Bit = Subtarget->is64Bit();
2400 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2402 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2403 "Var args not supported with calling convention fastcc, ghc or hipe");
2405 // Assign locations to all of the incoming arguments.
2406 SmallVector<CCValAssign, 16> ArgLocs;
2407 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2409 // Allocate shadow area for Win64
2411 CCInfo.AllocateStack(32, 8);
2413 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2415 unsigned LastVal = ~0U;
2417 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2418 CCValAssign &VA = ArgLocs[i];
2419 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2421 assert(VA.getValNo() != LastVal &&
2422 "Don't support value assigned to multiple locs yet");
2424 LastVal = VA.getValNo();
2426 if (VA.isRegLoc()) {
2427 EVT RegVT = VA.getLocVT();
2428 const TargetRegisterClass *RC;
2429 if (RegVT == MVT::i32)
2430 RC = &X86::GR32RegClass;
2431 else if (Is64Bit && RegVT == MVT::i64)
2432 RC = &X86::GR64RegClass;
2433 else if (RegVT == MVT::f32)
2434 RC = &X86::FR32RegClass;
2435 else if (RegVT == MVT::f64)
2436 RC = &X86::FR64RegClass;
2437 else if (RegVT.is512BitVector())
2438 RC = &X86::VR512RegClass;
2439 else if (RegVT.is256BitVector())
2440 RC = &X86::VR256RegClass;
2441 else if (RegVT.is128BitVector())
2442 RC = &X86::VR128RegClass;
2443 else if (RegVT == MVT::x86mmx)
2444 RC = &X86::VR64RegClass;
2445 else if (RegVT == MVT::i1)
2446 RC = &X86::VK1RegClass;
2447 else if (RegVT == MVT::v8i1)
2448 RC = &X86::VK8RegClass;
2449 else if (RegVT == MVT::v16i1)
2450 RC = &X86::VK16RegClass;
2451 else if (RegVT == MVT::v32i1)
2452 RC = &X86::VK32RegClass;
2453 else if (RegVT == MVT::v64i1)
2454 RC = &X86::VK64RegClass;
2456 llvm_unreachable("Unknown argument type!");
2458 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2459 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2461 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2462 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2464 if (VA.getLocInfo() == CCValAssign::SExt)
2465 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2466 DAG.getValueType(VA.getValVT()));
2467 else if (VA.getLocInfo() == CCValAssign::ZExt)
2468 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2469 DAG.getValueType(VA.getValVT()));
2470 else if (VA.getLocInfo() == CCValAssign::BCvt)
2471 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2473 if (VA.isExtInLoc()) {
2474 // Handle MMX values passed in XMM regs.
2475 if (RegVT.isVector())
2476 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2478 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2481 assert(VA.isMemLoc());
2482 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2485 // If value is passed via pointer - do a load.
2486 if (VA.getLocInfo() == CCValAssign::Indirect)
2487 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2488 MachinePointerInfo(), false, false, false, 0);
2490 InVals.push_back(ArgValue);
2493 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2495 // The x86-64 ABIs require that for returning structs by value we copy
2496 // the sret argument into %rax/%eax (depending on ABI) for the return.
2497 // Win32 requires us to put the sret argument to %eax as well.
2498 // Save the argument into a virtual register so that we can access it
2499 // from the return points.
2500 if (Ins[i].Flags.isSRet()) {
2501 unsigned Reg = FuncInfo->getSRetReturnReg();
2503 MVT PtrTy = getPointerTy();
2504 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2505 FuncInfo->setSRetReturnReg(Reg);
2507 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2514 unsigned StackSize = CCInfo.getNextStackOffset();
2515 // Align stack specially for tail calls.
2516 if (FuncIsMadeTailCallSafe(CallConv,
2517 MF.getTarget().Options.GuaranteedTailCallOpt))
2518 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2520 // If the function takes variable number of arguments, make a frame index for
2521 // the start of the first vararg value... for expansion of llvm.va_start. We
2522 // can skip this if there are no va_start calls.
2523 if (MFI->hasVAStart() &&
2524 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2525 CallConv != CallingConv::X86_ThisCall))) {
2526 FuncInfo->setVarArgsFrameIndex(
2527 MFI->CreateFixedObject(1, StackSize, true));
2530 // 64-bit calling conventions support varargs and register parameters, so we
2531 // have to do extra work to spill them in the prologue or forward them to
2533 if (Is64Bit && isVarArg &&
2534 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2535 // Find the first unallocated argument registers.
2536 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2537 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2538 unsigned NumIntRegs =
2539 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2540 unsigned NumXMMRegs =
2541 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2542 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2543 "SSE register cannot be used when SSE is disabled!");
2545 // Gather all the live in physical registers.
2546 SmallVector<SDValue, 6> LiveGPRs;
2547 SmallVector<SDValue, 8> LiveXMMRegs;
2549 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2550 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2552 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2554 if (!ArgXMMs.empty()) {
2555 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2556 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2557 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2558 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2559 LiveXMMRegs.push_back(
2560 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2564 // Store them to the va_list returned by va_start.
2565 if (MFI->hasVAStart()) {
2567 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2568 // Get to the caller-allocated home save location. Add 8 to account
2569 // for the return address.
2570 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2571 FuncInfo->setRegSaveFrameIndex(
2572 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2573 // Fixup to set vararg frame on shadow area (4 x i64).
2575 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2577 // For X86-64, if there are vararg parameters that are passed via
2578 // registers, then we must store them to their spots on the stack so
2579 // they may be loaded by deferencing the result of va_next.
2580 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2581 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2582 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2583 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2586 // Store the integer parameter registers.
2587 SmallVector<SDValue, 8> MemOps;
2588 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2590 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2591 for (SDValue Val : LiveGPRs) {
2592 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2593 DAG.getIntPtrConstant(Offset));
2595 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2596 MachinePointerInfo::getFixedStack(
2597 FuncInfo->getRegSaveFrameIndex(), Offset),
2599 MemOps.push_back(Store);
2603 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2604 // Now store the XMM (fp + vector) parameter registers.
2605 SmallVector<SDValue, 12> SaveXMMOps;
2606 SaveXMMOps.push_back(Chain);
2607 SaveXMMOps.push_back(ALVal);
2608 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2609 FuncInfo->getRegSaveFrameIndex()));
2610 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2611 FuncInfo->getVarArgsFPOffset()));
2612 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2614 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2615 MVT::Other, SaveXMMOps));
2618 if (!MemOps.empty())
2619 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2621 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2622 // to the liveout set on a musttail call.
2623 assert(MFI->hasMustTailInVarArgFunc());
2624 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2625 typedef X86MachineFunctionInfo::Forward Forward;
2627 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2629 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2630 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2631 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2634 if (!ArgXMMs.empty()) {
2636 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2637 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2638 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2640 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2642 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2643 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2645 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2651 // Some CCs need callee pop.
2652 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2653 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2654 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2656 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2657 // If this is an sret function, the return should pop the hidden pointer.
2658 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2659 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2660 argsAreStructReturn(Ins) == StackStructReturn)
2661 FuncInfo->setBytesToPopOnReturn(4);
2665 // RegSaveFrameIndex is X86-64 only.
2666 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2667 if (CallConv == CallingConv::X86_FastCall ||
2668 CallConv == CallingConv::X86_ThisCall)
2669 // fastcc functions can't have varargs.
2670 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2673 FuncInfo->setArgumentStackSize(StackSize);
2679 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2680 SDValue StackPtr, SDValue Arg,
2681 SDLoc dl, SelectionDAG &DAG,
2682 const CCValAssign &VA,
2683 ISD::ArgFlagsTy Flags) const {
2684 unsigned LocMemOffset = VA.getLocMemOffset();
2685 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2686 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2687 if (Flags.isByVal())
2688 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2690 return DAG.getStore(Chain, dl, Arg, PtrOff,
2691 MachinePointerInfo::getStack(LocMemOffset),
2695 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2696 /// optimization is performed and it is required.
2698 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2699 SDValue &OutRetAddr, SDValue Chain,
2700 bool IsTailCall, bool Is64Bit,
2701 int FPDiff, SDLoc dl) const {
2702 // Adjust the Return address stack slot.
2703 EVT VT = getPointerTy();
2704 OutRetAddr = getReturnAddressFrameIndex(DAG);
2706 // Load the "old" Return address.
2707 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2708 false, false, false, 0);
2709 return SDValue(OutRetAddr.getNode(), 1);
2712 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2713 /// optimization is performed and it is required (FPDiff!=0).
2714 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2715 SDValue Chain, SDValue RetAddrFrIdx,
2716 EVT PtrVT, unsigned SlotSize,
2717 int FPDiff, SDLoc dl) {
2718 // Store the return address to the appropriate stack slot.
2719 if (!FPDiff) return Chain;
2720 // Calculate the new stack slot for the return address.
2721 int NewReturnAddrFI =
2722 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2724 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2725 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2726 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2732 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2733 SmallVectorImpl<SDValue> &InVals) const {
2734 SelectionDAG &DAG = CLI.DAG;
2736 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2737 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2738 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2739 SDValue Chain = CLI.Chain;
2740 SDValue Callee = CLI.Callee;
2741 CallingConv::ID CallConv = CLI.CallConv;
2742 bool &isTailCall = CLI.IsTailCall;
2743 bool isVarArg = CLI.IsVarArg;
2745 MachineFunction &MF = DAG.getMachineFunction();
2746 bool Is64Bit = Subtarget->is64Bit();
2747 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2748 StructReturnType SR = callIsStructReturn(Outs);
2749 bool IsSibcall = false;
2750 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2752 if (MF.getTarget().Options.DisableTailCalls)
2755 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2757 // Force this to be a tail call. The verifier rules are enough to ensure
2758 // that we can lower this successfully without moving the return address
2761 } else if (isTailCall) {
2762 // Check if it's really possible to do a tail call.
2763 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2764 isVarArg, SR != NotStructReturn,
2765 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2766 Outs, OutVals, Ins, DAG);
2768 // Sibcalls are automatically detected tailcalls which do not require
2770 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2777 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2778 "Var args not supported with calling convention fastcc, ghc or hipe");
2780 // Analyze operands of the call, assigning locations to each operand.
2781 SmallVector<CCValAssign, 16> ArgLocs;
2782 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2784 // Allocate shadow area for Win64
2786 CCInfo.AllocateStack(32, 8);
2788 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2790 // Get a count of how many bytes are to be pushed on the stack.
2791 unsigned NumBytes = CCInfo.getNextStackOffset();
2793 // This is a sibcall. The memory operands are available in caller's
2794 // own caller's stack.
2796 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2797 IsTailCallConvention(CallConv))
2798 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2801 if (isTailCall && !IsSibcall && !IsMustTail) {
2802 // Lower arguments at fp - stackoffset + fpdiff.
2803 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2805 FPDiff = NumBytesCallerPushed - NumBytes;
2807 // Set the delta of movement of the returnaddr stackslot.
2808 // But only set if delta is greater than previous delta.
2809 if (FPDiff < X86Info->getTCReturnAddrDelta())
2810 X86Info->setTCReturnAddrDelta(FPDiff);
2813 unsigned NumBytesToPush = NumBytes;
2814 unsigned NumBytesToPop = NumBytes;
2816 // If we have an inalloca argument, all stack space has already been allocated
2817 // for us and be right at the top of the stack. We don't support multiple
2818 // arguments passed in memory when using inalloca.
2819 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2821 if (!ArgLocs.back().isMemLoc())
2822 report_fatal_error("cannot use inalloca attribute on a register "
2824 if (ArgLocs.back().getLocMemOffset() != 0)
2825 report_fatal_error("any parameter with the inalloca attribute must be "
2826 "the only memory argument");
2830 Chain = DAG.getCALLSEQ_START(
2831 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2833 SDValue RetAddrFrIdx;
2834 // Load return address for tail calls.
2835 if (isTailCall && FPDiff)
2836 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2837 Is64Bit, FPDiff, dl);
2839 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2840 SmallVector<SDValue, 8> MemOpChains;
2843 // Walk the register/memloc assignments, inserting copies/loads. In the case
2844 // of tail call optimization arguments are handle later.
2845 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2846 DAG.getSubtarget().getRegisterInfo());
2847 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2848 // Skip inalloca arguments, they have already been written.
2849 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2850 if (Flags.isInAlloca())
2853 CCValAssign &VA = ArgLocs[i];
2854 EVT RegVT = VA.getLocVT();
2855 SDValue Arg = OutVals[i];
2856 bool isByVal = Flags.isByVal();
2858 // Promote the value if needed.
2859 switch (VA.getLocInfo()) {
2860 default: llvm_unreachable("Unknown loc info!");
2861 case CCValAssign::Full: break;
2862 case CCValAssign::SExt:
2863 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2865 case CCValAssign::ZExt:
2866 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2868 case CCValAssign::AExt:
2869 if (RegVT.is128BitVector()) {
2870 // Special case: passing MMX values in XMM registers.
2871 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2872 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2873 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2875 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2877 case CCValAssign::BCvt:
2878 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2880 case CCValAssign::Indirect: {
2881 // Store the argument.
2882 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2883 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2884 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2885 MachinePointerInfo::getFixedStack(FI),
2892 if (VA.isRegLoc()) {
2893 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2894 if (isVarArg && IsWin64) {
2895 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2896 // shadow reg if callee is a varargs function.
2897 unsigned ShadowReg = 0;
2898 switch (VA.getLocReg()) {
2899 case X86::XMM0: ShadowReg = X86::RCX; break;
2900 case X86::XMM1: ShadowReg = X86::RDX; break;
2901 case X86::XMM2: ShadowReg = X86::R8; break;
2902 case X86::XMM3: ShadowReg = X86::R9; break;
2905 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2907 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2908 assert(VA.isMemLoc());
2909 if (!StackPtr.getNode())
2910 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2912 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2913 dl, DAG, VA, Flags));
2917 if (!MemOpChains.empty())
2918 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2920 if (Subtarget->isPICStyleGOT()) {
2921 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2924 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2925 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2927 // If we are tail calling and generating PIC/GOT style code load the
2928 // address of the callee into ECX. The value in ecx is used as target of
2929 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2930 // for tail calls on PIC/GOT architectures. Normally we would just put the
2931 // address of GOT into ebx and then call target@PLT. But for tail calls
2932 // ebx would be restored (since ebx is callee saved) before jumping to the
2935 // Note: The actual moving to ECX is done further down.
2936 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2937 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2938 !G->getGlobal()->hasProtectedVisibility())
2939 Callee = LowerGlobalAddress(Callee, DAG);
2940 else if (isa<ExternalSymbolSDNode>(Callee))
2941 Callee = LowerExternalSymbol(Callee, DAG);
2945 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2946 // From AMD64 ABI document:
2947 // For calls that may call functions that use varargs or stdargs
2948 // (prototype-less calls or calls to functions containing ellipsis (...) in
2949 // the declaration) %al is used as hidden argument to specify the number
2950 // of SSE registers used. The contents of %al do not need to match exactly
2951 // the number of registers, but must be an ubound on the number of SSE
2952 // registers used and is in the range 0 - 8 inclusive.
2954 // Count the number of XMM registers allocated.
2955 static const MCPhysReg XMMArgRegs[] = {
2956 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2957 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2959 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2960 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2961 && "SSE registers cannot be used when SSE is disabled");
2963 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2964 DAG.getConstant(NumXMMRegs, MVT::i8)));
2967 if (Is64Bit && isVarArg && IsMustTail) {
2968 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2969 for (const auto &F : Forwards) {
2970 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2971 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2975 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2976 // don't need this because the eligibility check rejects calls that require
2977 // shuffling arguments passed in memory.
2978 if (!IsSibcall && isTailCall) {
2979 // Force all the incoming stack arguments to be loaded from the stack
2980 // before any new outgoing arguments are stored to the stack, because the
2981 // outgoing stack slots may alias the incoming argument stack slots, and
2982 // the alias isn't otherwise explicit. This is slightly more conservative
2983 // than necessary, because it means that each store effectively depends
2984 // on every argument instead of just those arguments it would clobber.
2985 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2987 SmallVector<SDValue, 8> MemOpChains2;
2990 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2991 CCValAssign &VA = ArgLocs[i];
2994 assert(VA.isMemLoc());
2995 SDValue Arg = OutVals[i];
2996 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2997 // Skip inalloca arguments. They don't require any work.
2998 if (Flags.isInAlloca())
3000 // Create frame index.
3001 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3002 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3003 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3004 FIN = DAG.getFrameIndex(FI, getPointerTy());
3006 if (Flags.isByVal()) {
3007 // Copy relative to framepointer.
3008 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3009 if (!StackPtr.getNode())
3010 StackPtr = DAG.getCopyFromReg(Chain, dl,
3011 RegInfo->getStackRegister(),
3013 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3015 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3019 // Store relative to framepointer.
3020 MemOpChains2.push_back(
3021 DAG.getStore(ArgChain, dl, Arg, FIN,
3022 MachinePointerInfo::getFixedStack(FI),
3027 if (!MemOpChains2.empty())
3028 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3030 // Store the return address to the appropriate stack slot.
3031 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3032 getPointerTy(), RegInfo->getSlotSize(),
3036 // Build a sequence of copy-to-reg nodes chained together with token chain
3037 // and flag operands which copy the outgoing args into registers.
3039 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3040 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3041 RegsToPass[i].second, InFlag);
3042 InFlag = Chain.getValue(1);
3045 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3046 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3047 // In the 64-bit large code model, we have to make all calls
3048 // through a register, since the call instruction's 32-bit
3049 // pc-relative offset may not be large enough to hold the whole
3051 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3052 // If the callee is a GlobalAddress node (quite common, every direct call
3053 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3056 // We should use extra load for direct calls to dllimported functions in
3058 const GlobalValue *GV = G->getGlobal();
3059 if (!GV->hasDLLImportStorageClass()) {
3060 unsigned char OpFlags = 0;
3061 bool ExtraLoad = false;
3062 unsigned WrapperKind = ISD::DELETED_NODE;
3064 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3065 // external symbols most go through the PLT in PIC mode. If the symbol
3066 // has hidden or protected visibility, or if it is static or local, then
3067 // we don't need to use the PLT - we can directly call it.
3068 if (Subtarget->isTargetELF() &&
3069 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3070 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3071 OpFlags = X86II::MO_PLT;
3072 } else if (Subtarget->isPICStyleStubAny() &&
3073 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3074 (!Subtarget->getTargetTriple().isMacOSX() ||
3075 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3076 // PC-relative references to external symbols should go through $stub,
3077 // unless we're building with the leopard linker or later, which
3078 // automatically synthesizes these stubs.
3079 OpFlags = X86II::MO_DARWIN_STUB;
3080 } else if (Subtarget->isPICStyleRIPRel() &&
3081 isa<Function>(GV) &&
3082 cast<Function>(GV)->getAttributes().
3083 hasAttribute(AttributeSet::FunctionIndex,
3084 Attribute::NonLazyBind)) {
3085 // If the function is marked as non-lazy, generate an indirect call
3086 // which loads from the GOT directly. This avoids runtime overhead
3087 // at the cost of eager binding (and one extra byte of encoding).
3088 OpFlags = X86II::MO_GOTPCREL;
3089 WrapperKind = X86ISD::WrapperRIP;
3093 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3094 G->getOffset(), OpFlags);
3096 // Add a wrapper if needed.
3097 if (WrapperKind != ISD::DELETED_NODE)
3098 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3099 // Add extra indirection if needed.
3101 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3102 MachinePointerInfo::getGOT(),
3103 false, false, false, 0);
3105 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3106 unsigned char OpFlags = 0;
3108 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3109 // external symbols should go through the PLT.
3110 if (Subtarget->isTargetELF() &&
3111 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3112 OpFlags = X86II::MO_PLT;
3113 } else if (Subtarget->isPICStyleStubAny() &&
3114 (!Subtarget->getTargetTriple().isMacOSX() ||
3115 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3116 // PC-relative references to external symbols should go through $stub,
3117 // unless we're building with the leopard linker or later, which
3118 // automatically synthesizes these stubs.
3119 OpFlags = X86II::MO_DARWIN_STUB;
3122 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3124 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3125 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3126 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3129 // Returns a chain & a flag for retval copy to use.
3130 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3131 SmallVector<SDValue, 8> Ops;
3133 if (!IsSibcall && isTailCall) {
3134 Chain = DAG.getCALLSEQ_END(Chain,
3135 DAG.getIntPtrConstant(NumBytesToPop, true),
3136 DAG.getIntPtrConstant(0, true), InFlag, dl);
3137 InFlag = Chain.getValue(1);
3140 Ops.push_back(Chain);
3141 Ops.push_back(Callee);
3144 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3146 // Add argument registers to the end of the list so that they are known live
3148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3149 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3150 RegsToPass[i].second.getValueType()));
3152 // Add a register mask operand representing the call-preserved registers.
3153 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3154 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3155 assert(Mask && "Missing call preserved mask for calling convention");
3156 Ops.push_back(DAG.getRegisterMask(Mask));
3158 if (InFlag.getNode())
3159 Ops.push_back(InFlag);
3163 //// If this is the first return lowered for this function, add the regs
3164 //// to the liveout set for the function.
3165 // This isn't right, although it's probably harmless on x86; liveouts
3166 // should be computed from returns not tail calls. Consider a void
3167 // function making a tail call to a function returning int.
3168 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3171 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3172 InFlag = Chain.getValue(1);
3174 // Create the CALLSEQ_END node.
3175 unsigned NumBytesForCalleeToPop;
3176 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3177 DAG.getTarget().Options.GuaranteedTailCallOpt))
3178 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3179 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3180 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3181 SR == StackStructReturn)
3182 // If this is a call to a struct-return function, the callee
3183 // pops the hidden struct pointer, so we have to push it back.
3184 // This is common for Darwin/X86, Linux & Mingw32 targets.
3185 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3186 NumBytesForCalleeToPop = 4;
3188 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3190 // Returns a flag for retval copy to use.
3192 Chain = DAG.getCALLSEQ_END(Chain,
3193 DAG.getIntPtrConstant(NumBytesToPop, true),
3194 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3197 InFlag = Chain.getValue(1);
3200 // Handle result values, copying them out of physregs into vregs that we
3202 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3203 Ins, dl, DAG, InVals);
3206 //===----------------------------------------------------------------------===//
3207 // Fast Calling Convention (tail call) implementation
3208 //===----------------------------------------------------------------------===//
3210 // Like std call, callee cleans arguments, convention except that ECX is
3211 // reserved for storing the tail called function address. Only 2 registers are
3212 // free for argument passing (inreg). Tail call optimization is performed
3214 // * tailcallopt is enabled
3215 // * caller/callee are fastcc
3216 // On X86_64 architecture with GOT-style position independent code only local
3217 // (within module) calls are supported at the moment.
3218 // To keep the stack aligned according to platform abi the function
3219 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3220 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3221 // If a tail called function callee has more arguments than the caller the
3222 // caller needs to make sure that there is room to move the RETADDR to. This is
3223 // achieved by reserving an area the size of the argument delta right after the
3224 // original RETADDR, but before the saved framepointer or the spilled registers
3225 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3237 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3238 /// for a 16 byte align requirement.
3240 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3241 SelectionDAG& DAG) const {
3242 MachineFunction &MF = DAG.getMachineFunction();
3243 const TargetMachine &TM = MF.getTarget();
3244 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3245 TM.getSubtargetImpl()->getRegisterInfo());
3246 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3247 unsigned StackAlignment = TFI.getStackAlignment();
3248 uint64_t AlignMask = StackAlignment - 1;
3249 int64_t Offset = StackSize;
3250 unsigned SlotSize = RegInfo->getSlotSize();
3251 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3252 // Number smaller than 12 so just add the difference.
3253 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3255 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3256 Offset = ((~AlignMask) & Offset) + StackAlignment +
3257 (StackAlignment-SlotSize);
3262 /// MatchingStackOffset - Return true if the given stack call argument is
3263 /// already available in the same position (relatively) of the caller's
3264 /// incoming argument stack.
3266 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3267 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3268 const X86InstrInfo *TII) {
3269 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3271 if (Arg.getOpcode() == ISD::CopyFromReg) {
3272 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3273 if (!TargetRegisterInfo::isVirtualRegister(VR))
3275 MachineInstr *Def = MRI->getVRegDef(VR);
3278 if (!Flags.isByVal()) {
3279 if (!TII->isLoadFromStackSlot(Def, FI))
3282 unsigned Opcode = Def->getOpcode();
3283 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3284 Def->getOperand(1).isFI()) {
3285 FI = Def->getOperand(1).getIndex();
3286 Bytes = Flags.getByValSize();
3290 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3291 if (Flags.isByVal())
3292 // ByVal argument is passed in as a pointer but it's now being
3293 // dereferenced. e.g.
3294 // define @foo(%struct.X* %A) {
3295 // tail call @bar(%struct.X* byval %A)
3298 SDValue Ptr = Ld->getBasePtr();
3299 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3302 FI = FINode->getIndex();
3303 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3304 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3305 FI = FINode->getIndex();
3306 Bytes = Flags.getByValSize();
3310 assert(FI != INT_MAX);
3311 if (!MFI->isFixedObjectIndex(FI))
3313 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3316 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3317 /// for tail call optimization. Targets which want to do tail call
3318 /// optimization should implement this function.
3320 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3321 CallingConv::ID CalleeCC,
3323 bool isCalleeStructRet,
3324 bool isCallerStructRet,
3326 const SmallVectorImpl<ISD::OutputArg> &Outs,
3327 const SmallVectorImpl<SDValue> &OutVals,
3328 const SmallVectorImpl<ISD::InputArg> &Ins,
3329 SelectionDAG &DAG) const {
3330 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3333 // If -tailcallopt is specified, make fastcc functions tail-callable.
3334 const MachineFunction &MF = DAG.getMachineFunction();
3335 const Function *CallerF = MF.getFunction();
3337 // If the function return type is x86_fp80 and the callee return type is not,
3338 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3339 // perform a tailcall optimization here.
3340 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3343 CallingConv::ID CallerCC = CallerF->getCallingConv();
3344 bool CCMatch = CallerCC == CalleeCC;
3345 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3346 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3348 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3349 if (IsTailCallConvention(CalleeCC) && CCMatch)
3354 // Look for obvious safe cases to perform tail call optimization that do not
3355 // require ABI changes. This is what gcc calls sibcall.
3357 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3358 // emit a special epilogue.
3359 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3360 DAG.getSubtarget().getRegisterInfo());
3361 if (RegInfo->needsStackRealignment(MF))
3364 // Also avoid sibcall optimization if either caller or callee uses struct
3365 // return semantics.
3366 if (isCalleeStructRet || isCallerStructRet)
3369 // An stdcall/thiscall caller is expected to clean up its arguments; the
3370 // callee isn't going to do that.
3371 // FIXME: this is more restrictive than needed. We could produce a tailcall
3372 // when the stack adjustment matches. For example, with a thiscall that takes
3373 // only one argument.
3374 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3375 CallerCC == CallingConv::X86_ThisCall))
3378 // Do not sibcall optimize vararg calls unless all arguments are passed via
3380 if (isVarArg && !Outs.empty()) {
3382 // Optimizing for varargs on Win64 is unlikely to be safe without
3383 // additional testing.
3384 if (IsCalleeWin64 || IsCallerWin64)
3387 SmallVector<CCValAssign, 16> ArgLocs;
3388 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3391 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3392 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3393 if (!ArgLocs[i].isRegLoc())
3397 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3398 // stack. Therefore, if it's not used by the call it is not safe to optimize
3399 // this into a sibcall.
3400 bool Unused = false;
3401 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3408 SmallVector<CCValAssign, 16> RVLocs;
3409 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3411 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3412 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3413 CCValAssign &VA = RVLocs[i];
3414 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3419 // If the calling conventions do not match, then we'd better make sure the
3420 // results are returned in the same way as what the caller expects.
3422 SmallVector<CCValAssign, 16> RVLocs1;
3423 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3425 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3427 SmallVector<CCValAssign, 16> RVLocs2;
3428 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3430 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3432 if (RVLocs1.size() != RVLocs2.size())
3434 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3435 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3437 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3439 if (RVLocs1[i].isRegLoc()) {
3440 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3443 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3449 // If the callee takes no arguments then go on to check the results of the
3451 if (!Outs.empty()) {
3452 // Check if stack adjustment is needed. For now, do not do this if any
3453 // argument is passed on the stack.
3454 SmallVector<CCValAssign, 16> ArgLocs;
3455 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3458 // Allocate shadow area for Win64
3460 CCInfo.AllocateStack(32, 8);
3462 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3463 if (CCInfo.getNextStackOffset()) {
3464 MachineFunction &MF = DAG.getMachineFunction();
3465 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3468 // Check if the arguments are already laid out in the right way as
3469 // the caller's fixed stack objects.
3470 MachineFrameInfo *MFI = MF.getFrameInfo();
3471 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3472 const X86InstrInfo *TII =
3473 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3474 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3475 CCValAssign &VA = ArgLocs[i];
3476 SDValue Arg = OutVals[i];
3477 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3478 if (VA.getLocInfo() == CCValAssign::Indirect)
3480 if (!VA.isRegLoc()) {
3481 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3488 // If the tailcall address may be in a register, then make sure it's
3489 // possible to register allocate for it. In 32-bit, the call address can
3490 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3491 // callee-saved registers are restored. These happen to be the same
3492 // registers used to pass 'inreg' arguments so watch out for those.
3493 if (!Subtarget->is64Bit() &&
3494 ((!isa<GlobalAddressSDNode>(Callee) &&
3495 !isa<ExternalSymbolSDNode>(Callee)) ||
3496 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3497 unsigned NumInRegs = 0;
3498 // In PIC we need an extra register to formulate the address computation
3500 unsigned MaxInRegs =
3501 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3503 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3504 CCValAssign &VA = ArgLocs[i];
3507 unsigned Reg = VA.getLocReg();
3510 case X86::EAX: case X86::EDX: case X86::ECX:
3511 if (++NumInRegs == MaxInRegs)
3523 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3524 const TargetLibraryInfo *libInfo) const {
3525 return X86::createFastISel(funcInfo, libInfo);
3528 //===----------------------------------------------------------------------===//
3529 // Other Lowering Hooks
3530 //===----------------------------------------------------------------------===//
3532 static bool MayFoldLoad(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3536 static bool MayFoldIntoStore(SDValue Op) {
3537 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3540 static bool isTargetShuffle(unsigned Opcode) {
3542 default: return false;
3543 case X86ISD::BLENDI:
3544 case X86ISD::PSHUFB:
3545 case X86ISD::PSHUFD:
3546 case X86ISD::PSHUFHW:
3547 case X86ISD::PSHUFLW:
3549 case X86ISD::PALIGNR:
3550 case X86ISD::MOVLHPS:
3551 case X86ISD::MOVLHPD:
3552 case X86ISD::MOVHLPS:
3553 case X86ISD::MOVLPS:
3554 case X86ISD::MOVLPD:
3555 case X86ISD::MOVSHDUP:
3556 case X86ISD::MOVSLDUP:
3557 case X86ISD::MOVDDUP:
3560 case X86ISD::UNPCKL:
3561 case X86ISD::UNPCKH:
3562 case X86ISD::VPERMILPI:
3563 case X86ISD::VPERM2X128:
3564 case X86ISD::VPERMI:
3569 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3570 SDValue V1, SelectionDAG &DAG) {
3572 default: llvm_unreachable("Unknown x86 shuffle node");
3573 case X86ISD::MOVSHDUP:
3574 case X86ISD::MOVSLDUP:
3575 case X86ISD::MOVDDUP:
3576 return DAG.getNode(Opc, dl, VT, V1);
3580 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3581 SDValue V1, unsigned TargetMask,
3582 SelectionDAG &DAG) {
3584 default: llvm_unreachable("Unknown x86 shuffle node");
3585 case X86ISD::PSHUFD:
3586 case X86ISD::PSHUFHW:
3587 case X86ISD::PSHUFLW:
3588 case X86ISD::VPERMILPI:
3589 case X86ISD::VPERMI:
3590 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3594 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3595 SDValue V1, SDValue V2, unsigned TargetMask,
3596 SelectionDAG &DAG) {
3598 default: llvm_unreachable("Unknown x86 shuffle node");
3599 case X86ISD::PALIGNR:
3600 case X86ISD::VALIGN:
3602 case X86ISD::VPERM2X128:
3603 return DAG.getNode(Opc, dl, VT, V1, V2,
3604 DAG.getConstant(TargetMask, MVT::i8));
3608 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3609 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3611 default: llvm_unreachable("Unknown x86 shuffle node");
3612 case X86ISD::MOVLHPS:
3613 case X86ISD::MOVLHPD:
3614 case X86ISD::MOVHLPS:
3615 case X86ISD::MOVLPS:
3616 case X86ISD::MOVLPD:
3619 case X86ISD::UNPCKL:
3620 case X86ISD::UNPCKH:
3621 return DAG.getNode(Opc, dl, VT, V1, V2);
3625 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3626 MachineFunction &MF = DAG.getMachineFunction();
3627 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3628 DAG.getSubtarget().getRegisterInfo());
3629 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3630 int ReturnAddrIndex = FuncInfo->getRAIndex();
3632 if (ReturnAddrIndex == 0) {
3633 // Set up a frame object for the return address.
3634 unsigned SlotSize = RegInfo->getSlotSize();
3635 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3638 FuncInfo->setRAIndex(ReturnAddrIndex);
3641 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3644 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3645 bool hasSymbolicDisplacement) {
3646 // Offset should fit into 32 bit immediate field.
3647 if (!isInt<32>(Offset))
3650 // If we don't have a symbolic displacement - we don't have any extra
3652 if (!hasSymbolicDisplacement)
3655 // FIXME: Some tweaks might be needed for medium code model.
3656 if (M != CodeModel::Small && M != CodeModel::Kernel)
3659 // For small code model we assume that latest object is 16MB before end of 31
3660 // bits boundary. We may also accept pretty large negative constants knowing
3661 // that all objects are in the positive half of address space.
3662 if (M == CodeModel::Small && Offset < 16*1024*1024)
3665 // For kernel code model we know that all object resist in the negative half
3666 // of 32bits address space. We may not accept negative offsets, since they may
3667 // be just off and we may accept pretty large positive ones.
3668 if (M == CodeModel::Kernel && Offset > 0)
3674 /// isCalleePop - Determines whether the callee is required to pop its
3675 /// own arguments. Callee pop is necessary to support tail calls.
3676 bool X86::isCalleePop(CallingConv::ID CallingConv,
3677 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3678 switch (CallingConv) {
3681 case CallingConv::X86_StdCall:
3682 case CallingConv::X86_FastCall:
3683 case CallingConv::X86_ThisCall:
3685 case CallingConv::Fast:
3686 case CallingConv::GHC:
3687 case CallingConv::HiPE:
3694 /// \brief Return true if the condition is an unsigned comparison operation.
3695 static bool isX86CCUnsigned(unsigned X86CC) {
3697 default: llvm_unreachable("Invalid integer condition!");
3698 case X86::COND_E: return true;
3699 case X86::COND_G: return false;
3700 case X86::COND_GE: return false;
3701 case X86::COND_L: return false;
3702 case X86::COND_LE: return false;
3703 case X86::COND_NE: return true;
3704 case X86::COND_B: return true;
3705 case X86::COND_A: return true;
3706 case X86::COND_BE: return true;
3707 case X86::COND_AE: return true;
3709 llvm_unreachable("covered switch fell through?!");
3712 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3713 /// specific condition code, returning the condition code and the LHS/RHS of the
3714 /// comparison to make.
3715 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3716 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3718 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3719 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3720 // X > -1 -> X == 0, jump !sign.
3721 RHS = DAG.getConstant(0, RHS.getValueType());
3722 return X86::COND_NS;
3724 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3725 // X < 0 -> X == 0, jump on sign.
3728 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3730 RHS = DAG.getConstant(0, RHS.getValueType());
3731 return X86::COND_LE;
3735 switch (SetCCOpcode) {
3736 default: llvm_unreachable("Invalid integer condition!");
3737 case ISD::SETEQ: return X86::COND_E;
3738 case ISD::SETGT: return X86::COND_G;
3739 case ISD::SETGE: return X86::COND_GE;
3740 case ISD::SETLT: return X86::COND_L;
3741 case ISD::SETLE: return X86::COND_LE;
3742 case ISD::SETNE: return X86::COND_NE;
3743 case ISD::SETULT: return X86::COND_B;
3744 case ISD::SETUGT: return X86::COND_A;
3745 case ISD::SETULE: return X86::COND_BE;
3746 case ISD::SETUGE: return X86::COND_AE;
3750 // First determine if it is required or is profitable to flip the operands.
3752 // If LHS is a foldable load, but RHS is not, flip the condition.
3753 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3754 !ISD::isNON_EXTLoad(RHS.getNode())) {
3755 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3756 std::swap(LHS, RHS);
3759 switch (SetCCOpcode) {
3765 std::swap(LHS, RHS);
3769 // On a floating point condition, the flags are set as follows:
3771 // 0 | 0 | 0 | X > Y
3772 // 0 | 0 | 1 | X < Y
3773 // 1 | 0 | 0 | X == Y
3774 // 1 | 1 | 1 | unordered
3775 switch (SetCCOpcode) {
3776 default: llvm_unreachable("Condcode should be pre-legalized away");
3778 case ISD::SETEQ: return X86::COND_E;
3779 case ISD::SETOLT: // flipped
3781 case ISD::SETGT: return X86::COND_A;
3782 case ISD::SETOLE: // flipped
3784 case ISD::SETGE: return X86::COND_AE;
3785 case ISD::SETUGT: // flipped
3787 case ISD::SETLT: return X86::COND_B;
3788 case ISD::SETUGE: // flipped
3790 case ISD::SETLE: return X86::COND_BE;
3792 case ISD::SETNE: return X86::COND_NE;
3793 case ISD::SETUO: return X86::COND_P;
3794 case ISD::SETO: return X86::COND_NP;
3796 case ISD::SETUNE: return X86::COND_INVALID;
3800 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3801 /// code. Current x86 isa includes the following FP cmov instructions:
3802 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3803 static bool hasFPCMov(unsigned X86CC) {
3819 /// isFPImmLegal - Returns true if the target can instruction select the
3820 /// specified FP immediate natively. If false, the legalizer will
3821 /// materialize the FP immediate as a load from a constant pool.
3822 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3823 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3824 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3830 /// \brief Returns true if it is beneficial to convert a load of a constant
3831 /// to just the constant itself.
3832 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3834 assert(Ty->isIntegerTy());
3836 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3837 if (BitSize == 0 || BitSize > 64)
3842 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3843 /// the specified range (L, H].
3844 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3845 return (Val < 0) || (Val >= Low && Val < Hi);
3848 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3849 /// specified value.
3850 static bool isUndefOrEqual(int Val, int CmpVal) {
3851 return (Val < 0 || Val == CmpVal);
3854 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3855 /// from position Pos and ending in Pos+Size, falls within the specified
3856 /// sequential range (L, L+Pos]. or is undef.
3857 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3858 unsigned Pos, unsigned Size, int Low) {
3859 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3860 if (!isUndefOrEqual(Mask[i], Low))
3865 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3866 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3867 /// the second operand.
3868 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3869 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3870 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3871 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3872 return (Mask[0] < 2 && Mask[1] < 2);
3876 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3877 /// is suitable for input to PSHUFHW.
3878 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3879 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3882 // Lower quadword copied in order or undef.
3883 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3886 // Upper quadword shuffled.
3887 for (unsigned i = 4; i != 8; ++i)
3888 if (!isUndefOrInRange(Mask[i], 4, 8))
3891 if (VT == MVT::v16i16) {
3892 // Lower quadword copied in order or undef.
3893 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3896 // Upper quadword shuffled.
3897 for (unsigned i = 12; i != 16; ++i)
3898 if (!isUndefOrInRange(Mask[i], 12, 16))
3905 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3906 /// is suitable for input to PSHUFLW.
3907 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3908 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3911 // Upper quadword copied in order.
3912 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3915 // Lower quadword shuffled.
3916 for (unsigned i = 0; i != 4; ++i)
3917 if (!isUndefOrInRange(Mask[i], 0, 4))
3920 if (VT == MVT::v16i16) {
3921 // Upper quadword copied in order.
3922 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3925 // Lower quadword shuffled.
3926 for (unsigned i = 8; i != 12; ++i)
3927 if (!isUndefOrInRange(Mask[i], 8, 12))
3934 /// \brief Return true if the mask specifies a shuffle of elements that is
3935 /// suitable for input to intralane (palignr) or interlane (valign) vector
3937 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3938 unsigned NumElts = VT.getVectorNumElements();
3939 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3940 unsigned NumLaneElts = NumElts/NumLanes;
3942 // Do not handle 64-bit element shuffles with palignr.
3943 if (NumLaneElts == 2)
3946 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3948 for (i = 0; i != NumLaneElts; ++i) {
3953 // Lane is all undef, go to next lane
3954 if (i == NumLaneElts)
3957 int Start = Mask[i+l];
3959 // Make sure its in this lane in one of the sources
3960 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3961 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3964 // If not lane 0, then we must match lane 0
3965 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3968 // Correct second source to be contiguous with first source
3969 if (Start >= (int)NumElts)
3970 Start -= NumElts - NumLaneElts;
3972 // Make sure we're shifting in the right direction.
3973 if (Start <= (int)(i+l))
3978 // Check the rest of the elements to see if they are consecutive.
3979 for (++i; i != NumLaneElts; ++i) {
3980 int Idx = Mask[i+l];
3982 // Make sure its in this lane
3983 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3984 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3987 // If not lane 0, then we must match lane 0
3988 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3991 if (Idx >= (int)NumElts)
3992 Idx -= NumElts - NumLaneElts;
3994 if (!isUndefOrEqual(Idx, Start+i))
4003 /// \brief Return true if the node specifies a shuffle of elements that is
4004 /// suitable for input to PALIGNR.
4005 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4006 const X86Subtarget *Subtarget) {
4007 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4008 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4009 VT.is512BitVector())
4010 // FIXME: Add AVX512BW.
4013 return isAlignrMask(Mask, VT, false);
4016 /// \brief Return true if the node specifies a shuffle of elements that is
4017 /// suitable for input to VALIGN.
4018 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4019 const X86Subtarget *Subtarget) {
4020 // FIXME: Add AVX512VL.
4021 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4023 return isAlignrMask(Mask, VT, true);
4026 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4027 /// the two vector operands have swapped position.
4028 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4029 unsigned NumElems) {
4030 for (unsigned i = 0; i != NumElems; ++i) {
4034 else if (idx < (int)NumElems)
4035 Mask[i] = idx + NumElems;
4037 Mask[i] = idx - NumElems;
4041 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4042 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4043 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4044 /// reverse of what x86 shuffles want.
4045 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4047 unsigned NumElems = VT.getVectorNumElements();
4048 unsigned NumLanes = VT.getSizeInBits()/128;
4049 unsigned NumLaneElems = NumElems/NumLanes;
4051 if (NumLaneElems != 2 && NumLaneElems != 4)
4054 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4055 bool symetricMaskRequired =
4056 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4058 // VSHUFPSY divides the resulting vector into 4 chunks.
4059 // The sources are also splitted into 4 chunks, and each destination
4060 // chunk must come from a different source chunk.
4062 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4063 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4065 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4066 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4068 // VSHUFPDY divides the resulting vector into 4 chunks.
4069 // The sources are also splitted into 4 chunks, and each destination
4070 // chunk must come from a different source chunk.
4072 // SRC1 => X3 X2 X1 X0
4073 // SRC2 => Y3 Y2 Y1 Y0
4075 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4077 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4078 unsigned HalfLaneElems = NumLaneElems/2;
4079 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4080 for (unsigned i = 0; i != NumLaneElems; ++i) {
4081 int Idx = Mask[i+l];
4082 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4083 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4085 // For VSHUFPSY, the mask of the second half must be the same as the
4086 // first but with the appropriate offsets. This works in the same way as
4087 // VPERMILPS works with masks.
4088 if (!symetricMaskRequired || Idx < 0)
4090 if (MaskVal[i] < 0) {
4091 MaskVal[i] = Idx - l;
4094 if ((signed)(Idx - l) != MaskVal[i])
4102 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4103 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4104 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4105 if (!VT.is128BitVector())
4108 unsigned NumElems = VT.getVectorNumElements();
4113 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4114 return isUndefOrEqual(Mask[0], 6) &&
4115 isUndefOrEqual(Mask[1], 7) &&
4116 isUndefOrEqual(Mask[2], 2) &&
4117 isUndefOrEqual(Mask[3], 3);
4120 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4121 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4123 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4124 if (!VT.is128BitVector())
4127 unsigned NumElems = VT.getVectorNumElements();
4132 return isUndefOrEqual(Mask[0], 2) &&
4133 isUndefOrEqual(Mask[1], 3) &&
4134 isUndefOrEqual(Mask[2], 2) &&
4135 isUndefOrEqual(Mask[3], 3);
4138 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4139 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4140 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4141 if (!VT.is128BitVector())
4144 unsigned NumElems = VT.getVectorNumElements();
4146 if (NumElems != 2 && NumElems != 4)
4149 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4150 if (!isUndefOrEqual(Mask[i], i + NumElems))
4153 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4154 if (!isUndefOrEqual(Mask[i], i))
4160 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4161 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4162 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4163 if (!VT.is128BitVector())
4166 unsigned NumElems = VT.getVectorNumElements();
4168 if (NumElems != 2 && NumElems != 4)
4171 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4172 if (!isUndefOrEqual(Mask[i], i))
4175 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4176 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4182 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4183 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4184 /// i. e: If all but one element come from the same vector.
4185 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4186 // TODO: Deal with AVX's VINSERTPS
4187 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4190 unsigned CorrectPosV1 = 0;
4191 unsigned CorrectPosV2 = 0;
4192 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4193 if (Mask[i] == -1) {
4201 else if (Mask[i] == i + 4)
4205 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4206 // We have 3 elements (undefs count as elements from any vector) from one
4207 // vector, and one from another.
4214 // Some special combinations that can be optimized.
4217 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4218 SelectionDAG &DAG) {
4219 MVT VT = SVOp->getSimpleValueType(0);
4222 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4225 ArrayRef<int> Mask = SVOp->getMask();
4227 // These are the special masks that may be optimized.
4228 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4229 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4230 bool MatchEvenMask = true;
4231 bool MatchOddMask = true;
4232 for (int i=0; i<8; ++i) {
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4234 MatchEvenMask = false;
4235 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4236 MatchOddMask = false;
4239 if (!MatchEvenMask && !MatchOddMask)
4242 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4244 SDValue Op0 = SVOp->getOperand(0);
4245 SDValue Op1 = SVOp->getOperand(1);
4247 if (MatchEvenMask) {
4248 // Shift the second operand right to 32 bits.
4249 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4250 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4252 // Shift the first operand left to 32 bits.
4253 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4254 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4256 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4257 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4260 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4261 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4262 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4263 bool HasInt256, bool V2IsSplat = false) {
4265 assert(VT.getSizeInBits() >= 128 &&
4266 "Unsupported vector type for unpckl");
4268 unsigned NumElts = VT.getVectorNumElements();
4269 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4270 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4273 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4274 "Unsupported vector type for unpckh");
4276 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4277 unsigned NumLanes = VT.getSizeInBits()/128;
4278 unsigned NumLaneElts = NumElts/NumLanes;
4280 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4281 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4282 int BitI = Mask[l+i];
4283 int BitI1 = Mask[l+i+1];
4284 if (!isUndefOrEqual(BitI, j))
4287 if (!isUndefOrEqual(BitI1, NumElts))
4290 if (!isUndefOrEqual(BitI1, j + NumElts))
4299 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4300 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4301 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4302 bool HasInt256, bool V2IsSplat = false) {
4303 assert(VT.getSizeInBits() >= 128 &&
4304 "Unsupported vector type for unpckh");
4306 unsigned NumElts = VT.getVectorNumElements();
4307 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4308 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4311 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4312 "Unsupported vector type for unpckh");
4314 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4315 unsigned NumLanes = VT.getSizeInBits()/128;
4316 unsigned NumLaneElts = NumElts/NumLanes;
4318 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4319 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4320 int BitI = Mask[l+i];
4321 int BitI1 = Mask[l+i+1];
4322 if (!isUndefOrEqual(BitI, j))
4325 if (isUndefOrEqual(BitI1, NumElts))
4328 if (!isUndefOrEqual(BitI1, j+NumElts))
4336 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4337 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4339 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4340 unsigned NumElts = VT.getVectorNumElements();
4341 bool Is256BitVec = VT.is256BitVector();
4343 if (VT.is512BitVector())
4345 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4346 "Unsupported vector type for unpckh");
4348 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4349 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4352 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4353 // FIXME: Need a better way to get rid of this, there's no latency difference
4354 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4355 // the former later. We should also remove the "_undef" special mask.
4356 if (NumElts == 4 && Is256BitVec)
4359 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4360 // independently on 128-bit lanes.
4361 unsigned NumLanes = VT.getSizeInBits()/128;
4362 unsigned NumLaneElts = NumElts/NumLanes;
4364 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4365 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4366 int BitI = Mask[l+i];
4367 int BitI1 = Mask[l+i+1];
4369 if (!isUndefOrEqual(BitI, j))
4371 if (!isUndefOrEqual(BitI1, j))
4379 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4380 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4382 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4383 unsigned NumElts = VT.getVectorNumElements();
4385 if (VT.is512BitVector())
4388 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4389 "Unsupported vector type for unpckh");
4391 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4392 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4395 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4396 // independently on 128-bit lanes.
4397 unsigned NumLanes = VT.getSizeInBits()/128;
4398 unsigned NumLaneElts = NumElts/NumLanes;
4400 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4401 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4402 int BitI = Mask[l+i];
4403 int BitI1 = Mask[l+i+1];
4404 if (!isUndefOrEqual(BitI, j))
4406 if (!isUndefOrEqual(BitI1, j))
4413 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4414 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4415 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4416 if (!VT.is512BitVector())
4419 unsigned NumElts = VT.getVectorNumElements();
4420 unsigned HalfSize = NumElts/2;
4421 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4422 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4428 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4436 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4437 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4438 /// MOVSD, and MOVD, i.e. setting the lowest element.
4439 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4440 if (VT.getVectorElementType().getSizeInBits() < 32)
4442 if (!VT.is128BitVector())
4445 unsigned NumElts = VT.getVectorNumElements();
4447 if (!isUndefOrEqual(Mask[0], NumElts))
4450 for (unsigned i = 1; i != NumElts; ++i)
4451 if (!isUndefOrEqual(Mask[i], i))
4457 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4458 /// as permutations between 128-bit chunks or halves. As an example: this
4460 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4461 /// The first half comes from the second half of V1 and the second half from the
4462 /// the second half of V2.
4463 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4464 if (!HasFp256 || !VT.is256BitVector())
4467 // The shuffle result is divided into half A and half B. In total the two
4468 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4469 // B must come from C, D, E or F.
4470 unsigned HalfSize = VT.getVectorNumElements()/2;
4471 bool MatchA = false, MatchB = false;
4473 // Check if A comes from one of C, D, E, F.
4474 for (unsigned Half = 0; Half != 4; ++Half) {
4475 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4481 // Check if B comes from one of C, D, E, F.
4482 for (unsigned Half = 0; Half != 4; ++Half) {
4483 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4489 return MatchA && MatchB;
4492 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4493 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4494 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4495 MVT VT = SVOp->getSimpleValueType(0);
4497 unsigned HalfSize = VT.getVectorNumElements()/2;
4499 unsigned FstHalf = 0, SndHalf = 0;
4500 for (unsigned i = 0; i < HalfSize; ++i) {
4501 if (SVOp->getMaskElt(i) > 0) {
4502 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4506 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4507 if (SVOp->getMaskElt(i) > 0) {
4508 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4513 return (FstHalf | (SndHalf << 4));
4516 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4517 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4518 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4522 unsigned NumElts = VT.getVectorNumElements();
4524 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4525 for (unsigned i = 0; i != NumElts; ++i) {
4528 Imm8 |= Mask[i] << (i*2);
4533 unsigned LaneSize = 4;
4534 SmallVector<int, 4> MaskVal(LaneSize, -1);
4536 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4537 for (unsigned i = 0; i != LaneSize; ++i) {
4538 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4542 if (MaskVal[i] < 0) {
4543 MaskVal[i] = Mask[i+l] - l;
4544 Imm8 |= MaskVal[i] << (i*2);
4547 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4554 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4555 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4556 /// Note that VPERMIL mask matching is different depending whether theunderlying
4557 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4558 /// to the same elements of the low, but to the higher half of the source.
4559 /// In VPERMILPD the two lanes could be shuffled independently of each other
4560 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4561 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4562 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4563 if (VT.getSizeInBits() < 256 || EltSize < 32)
4565 bool symetricMaskRequired = (EltSize == 32);
4566 unsigned NumElts = VT.getVectorNumElements();
4568 unsigned NumLanes = VT.getSizeInBits()/128;
4569 unsigned LaneSize = NumElts/NumLanes;
4570 // 2 or 4 elements in one lane
4572 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4573 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4574 for (unsigned i = 0; i != LaneSize; ++i) {
4575 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4577 if (symetricMaskRequired) {
4578 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4579 ExpectedMaskVal[i] = Mask[i+l] - l;
4582 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4590 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4591 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4592 /// element of vector 2 and the other elements to come from vector 1 in order.
4593 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4594 bool V2IsSplat = false, bool V2IsUndef = false) {
4595 if (!VT.is128BitVector())
4598 unsigned NumOps = VT.getVectorNumElements();
4599 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4602 if (!isUndefOrEqual(Mask[0], 0))
4605 for (unsigned i = 1; i != NumOps; ++i)
4606 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4607 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4608 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4614 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4615 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4616 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4617 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4618 const X86Subtarget *Subtarget) {
4619 if (!Subtarget->hasSSE3())
4622 unsigned NumElems = VT.getVectorNumElements();
4624 if ((VT.is128BitVector() && NumElems != 4) ||
4625 (VT.is256BitVector() && NumElems != 8) ||
4626 (VT.is512BitVector() && NumElems != 16))
4629 // "i+1" is the value the indexed mask element must have
4630 for (unsigned i = 0; i != NumElems; i += 2)
4631 if (!isUndefOrEqual(Mask[i], i+1) ||
4632 !isUndefOrEqual(Mask[i+1], i+1))
4638 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4639 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4640 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4641 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4642 const X86Subtarget *Subtarget) {
4643 if (!Subtarget->hasSSE3())
4646 unsigned NumElems = VT.getVectorNumElements();
4648 if ((VT.is128BitVector() && NumElems != 4) ||
4649 (VT.is256BitVector() && NumElems != 8) ||
4650 (VT.is512BitVector() && NumElems != 16))
4653 // "i" is the value the indexed mask element must have
4654 for (unsigned i = 0; i != NumElems; i += 2)
4655 if (!isUndefOrEqual(Mask[i], i) ||
4656 !isUndefOrEqual(Mask[i+1], i))
4662 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4663 /// specifies a shuffle of elements that is suitable for input to 256-bit
4664 /// version of MOVDDUP.
4665 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4666 if (!HasFp256 || !VT.is256BitVector())
4669 unsigned NumElts = VT.getVectorNumElements();
4673 for (unsigned i = 0; i != NumElts/2; ++i)
4674 if (!isUndefOrEqual(Mask[i], 0))
4676 for (unsigned i = NumElts/2; i != NumElts; ++i)
4677 if (!isUndefOrEqual(Mask[i], NumElts/2))
4682 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4683 /// specifies a shuffle of elements that is suitable for input to 128-bit
4684 /// version of MOVDDUP.
4685 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4686 if (!VT.is128BitVector())
4689 unsigned e = VT.getVectorNumElements() / 2;
4690 for (unsigned i = 0; i != e; ++i)
4691 if (!isUndefOrEqual(Mask[i], i))
4693 for (unsigned i = 0; i != e; ++i)
4694 if (!isUndefOrEqual(Mask[e+i], i))
4699 /// isVEXTRACTIndex - Return true if the specified
4700 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4701 /// suitable for instruction that extract 128 or 256 bit vectors
4702 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4703 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4704 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4707 // The index should be aligned on a vecWidth-bit boundary.
4709 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4711 MVT VT = N->getSimpleValueType(0);
4712 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4713 bool Result = (Index * ElSize) % vecWidth == 0;
4718 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4719 /// operand specifies a subvector insert that is suitable for input to
4720 /// insertion of 128 or 256-bit subvectors
4721 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4722 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4723 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4725 // The index should be aligned on a vecWidth-bit boundary.
4727 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4729 MVT VT = N->getSimpleValueType(0);
4730 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4731 bool Result = (Index * ElSize) % vecWidth == 0;
4736 bool X86::isVINSERT128Index(SDNode *N) {
4737 return isVINSERTIndex(N, 128);
4740 bool X86::isVINSERT256Index(SDNode *N) {
4741 return isVINSERTIndex(N, 256);
4744 bool X86::isVEXTRACT128Index(SDNode *N) {
4745 return isVEXTRACTIndex(N, 128);
4748 bool X86::isVEXTRACT256Index(SDNode *N) {
4749 return isVEXTRACTIndex(N, 256);
4752 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4753 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4754 /// Handles 128-bit and 256-bit.
4755 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4756 MVT VT = N->getSimpleValueType(0);
4758 assert((VT.getSizeInBits() >= 128) &&
4759 "Unsupported vector type for PSHUF/SHUFP");
4761 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4762 // independently on 128-bit lanes.
4763 unsigned NumElts = VT.getVectorNumElements();
4764 unsigned NumLanes = VT.getSizeInBits()/128;
4765 unsigned NumLaneElts = NumElts/NumLanes;
4767 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4768 "Only supports 2, 4 or 8 elements per lane");
4770 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4772 for (unsigned i = 0; i != NumElts; ++i) {
4773 int Elt = N->getMaskElt(i);
4774 if (Elt < 0) continue;
4775 Elt &= NumLaneElts - 1;
4776 unsigned ShAmt = (i << Shift) % 8;
4777 Mask |= Elt << ShAmt;
4783 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4784 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4785 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4786 MVT VT = N->getSimpleValueType(0);
4788 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4789 "Unsupported vector type for PSHUFHW");
4791 unsigned NumElts = VT.getVectorNumElements();
4794 for (unsigned l = 0; l != NumElts; l += 8) {
4795 // 8 nodes per lane, but we only care about the last 4.
4796 for (unsigned i = 0; i < 4; ++i) {
4797 int Elt = N->getMaskElt(l+i+4);
4798 if (Elt < 0) continue;
4799 Elt &= 0x3; // only 2-bits.
4800 Mask |= Elt << (i * 2);
4807 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4808 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4809 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4810 MVT VT = N->getSimpleValueType(0);
4812 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4813 "Unsupported vector type for PSHUFHW");
4815 unsigned NumElts = VT.getVectorNumElements();
4818 for (unsigned l = 0; l != NumElts; l += 8) {
4819 // 8 nodes per lane, but we only care about the first 4.
4820 for (unsigned i = 0; i < 4; ++i) {
4821 int Elt = N->getMaskElt(l+i);
4822 if (Elt < 0) continue;
4823 Elt &= 0x3; // only 2-bits
4824 Mask |= Elt << (i * 2);
4831 /// \brief Return the appropriate immediate to shuffle the specified
4832 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4833 /// VALIGN (if Interlane is true) instructions.
4834 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4836 MVT VT = SVOp->getSimpleValueType(0);
4837 unsigned EltSize = InterLane ? 1 :
4838 VT.getVectorElementType().getSizeInBits() >> 3;
4840 unsigned NumElts = VT.getVectorNumElements();
4841 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4842 unsigned NumLaneElts = NumElts/NumLanes;
4846 for (i = 0; i != NumElts; ++i) {
4847 Val = SVOp->getMaskElt(i);
4851 if (Val >= (int)NumElts)
4852 Val -= NumElts - NumLaneElts;
4854 assert(Val - i > 0 && "PALIGNR imm should be positive");
4855 return (Val - i) * EltSize;
4858 /// \brief Return the appropriate immediate to shuffle the specified
4859 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4860 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4861 return getShuffleAlignrImmediate(SVOp, false);
4864 /// \brief Return the appropriate immediate to shuffle the specified
4865 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4866 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4867 return getShuffleAlignrImmediate(SVOp, true);
4871 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4872 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4873 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4874 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4877 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4879 MVT VecVT = N->getOperand(0).getSimpleValueType();
4880 MVT ElVT = VecVT.getVectorElementType();
4882 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4883 return Index / NumElemsPerChunk;
4886 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4887 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4888 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4889 llvm_unreachable("Illegal insert subvector for VINSERT");
4892 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4894 MVT VecVT = N->getSimpleValueType(0);
4895 MVT ElVT = VecVT.getVectorElementType();
4897 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4898 return Index / NumElemsPerChunk;
4901 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4902 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4903 /// and VINSERTI128 instructions.
4904 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4905 return getExtractVEXTRACTImmediate(N, 128);
4908 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4909 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4910 /// and VINSERTI64x4 instructions.
4911 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4912 return getExtractVEXTRACTImmediate(N, 256);
4915 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4916 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4917 /// and VINSERTI128 instructions.
4918 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4919 return getInsertVINSERTImmediate(N, 128);
4922 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4923 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4924 /// and VINSERTI64x4 instructions.
4925 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4926 return getInsertVINSERTImmediate(N, 256);
4929 /// isZero - Returns true if Elt is a constant integer zero
4930 static bool isZero(SDValue V) {
4931 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4932 return C && C->isNullValue();
4935 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4937 bool X86::isZeroNode(SDValue Elt) {
4940 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4941 return CFP->getValueAPF().isPosZero();
4945 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4946 /// match movhlps. The lower half elements should come from upper half of
4947 /// V1 (and in order), and the upper half elements should come from the upper
4948 /// half of V2 (and in order).
4949 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4950 if (!VT.is128BitVector())
4952 if (VT.getVectorNumElements() != 4)
4954 for (unsigned i = 0, e = 2; i != e; ++i)
4955 if (!isUndefOrEqual(Mask[i], i+2))
4957 for (unsigned i = 2; i != 4; ++i)
4958 if (!isUndefOrEqual(Mask[i], i+4))
4963 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4964 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4966 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4967 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4969 N = N->getOperand(0).getNode();
4970 if (!ISD::isNON_EXTLoad(N))
4973 *LD = cast<LoadSDNode>(N);
4977 // Test whether the given value is a vector value which will be legalized
4979 static bool WillBeConstantPoolLoad(SDNode *N) {
4980 if (N->getOpcode() != ISD::BUILD_VECTOR)
4983 // Check for any non-constant elements.
4984 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4985 switch (N->getOperand(i).getNode()->getOpcode()) {
4987 case ISD::ConstantFP:
4994 // Vectors of all-zeros and all-ones are materialized with special
4995 // instructions rather than being loaded.
4996 return !ISD::isBuildVectorAllZeros(N) &&
4997 !ISD::isBuildVectorAllOnes(N);
5000 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5001 /// match movlp{s|d}. The lower half elements should come from lower half of
5002 /// V1 (and in order), and the upper half elements should come from the upper
5003 /// half of V2 (and in order). And since V1 will become the source of the
5004 /// MOVLP, it must be either a vector load or a scalar load to vector.
5005 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5006 ArrayRef<int> Mask, MVT VT) {
5007 if (!VT.is128BitVector())
5010 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5012 // Is V2 is a vector load, don't do this transformation. We will try to use
5013 // load folding shufps op.
5014 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5017 unsigned NumElems = VT.getVectorNumElements();
5019 if (NumElems != 2 && NumElems != 4)
5021 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5022 if (!isUndefOrEqual(Mask[i], i))
5024 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5025 if (!isUndefOrEqual(Mask[i], i+NumElems))
5030 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5031 /// to an zero vector.
5032 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5033 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5034 SDValue V1 = N->getOperand(0);
5035 SDValue V2 = N->getOperand(1);
5036 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5037 for (unsigned i = 0; i != NumElems; ++i) {
5038 int Idx = N->getMaskElt(i);
5039 if (Idx >= (int)NumElems) {
5040 unsigned Opc = V2.getOpcode();
5041 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5043 if (Opc != ISD::BUILD_VECTOR ||
5044 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5046 } else if (Idx >= 0) {
5047 unsigned Opc = V1.getOpcode();
5048 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5050 if (Opc != ISD::BUILD_VECTOR ||
5051 !X86::isZeroNode(V1.getOperand(Idx)))
5058 /// getZeroVector - Returns a vector of specified type with all zero elements.
5060 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5061 SelectionDAG &DAG, SDLoc dl) {
5062 assert(VT.isVector() && "Expected a vector type");
5064 // Always build SSE zero vectors as <4 x i32> bitcasted
5065 // to their dest type. This ensures they get CSE'd.
5067 if (VT.is128BitVector()) { // SSE
5068 if (Subtarget->hasSSE2()) { // SSE2
5069 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5070 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5072 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5073 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5075 } else if (VT.is256BitVector()) { // AVX
5076 if (Subtarget->hasInt256()) { // AVX2
5077 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5078 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5081 // 256-bit logic and arithmetic instructions in AVX are all
5082 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5083 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5084 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5085 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5087 } else if (VT.is512BitVector()) { // AVX-512
5088 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5089 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5090 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5092 } else if (VT.getScalarType() == MVT::i1) {
5093 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5094 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5095 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5096 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5098 llvm_unreachable("Unexpected vector type");
5100 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5103 /// getOnesVector - Returns a vector of specified type with all bits set.
5104 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5105 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5106 /// Then bitcast to their original type, ensuring they get CSE'd.
5107 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5109 assert(VT.isVector() && "Expected a vector type");
5111 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5113 if (VT.is256BitVector()) {
5114 if (HasInt256) { // AVX2
5115 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5118 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5119 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5121 } else if (VT.is128BitVector()) {
5122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5124 llvm_unreachable("Unexpected vector type");
5126 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5129 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5130 /// that point to V2 points to its first element.
5131 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5132 for (unsigned i = 0; i != NumElems; ++i) {
5133 if (Mask[i] > (int)NumElems) {
5139 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5140 /// operation of specified width.
5141 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5143 unsigned NumElems = VT.getVectorNumElements();
5144 SmallVector<int, 8> Mask;
5145 Mask.push_back(NumElems);
5146 for (unsigned i = 1; i != NumElems; ++i)
5148 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5151 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5152 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5154 unsigned NumElems = VT.getVectorNumElements();
5155 SmallVector<int, 8> Mask;
5156 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5158 Mask.push_back(i + NumElems);
5160 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5163 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5164 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5166 unsigned NumElems = VT.getVectorNumElements();
5167 SmallVector<int, 8> Mask;
5168 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5169 Mask.push_back(i + Half);
5170 Mask.push_back(i + NumElems + Half);
5172 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5175 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5176 // a generic shuffle instruction because the target has no such instructions.
5177 // Generate shuffles which repeat i16 and i8 several times until they can be
5178 // represented by v4f32 and then be manipulated by target suported shuffles.
5179 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5180 MVT VT = V.getSimpleValueType();
5181 int NumElems = VT.getVectorNumElements();
5184 while (NumElems > 4) {
5185 if (EltNo < NumElems/2) {
5186 V = getUnpackl(DAG, dl, VT, V, V);
5188 V = getUnpackh(DAG, dl, VT, V, V);
5189 EltNo -= NumElems/2;
5196 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5197 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5198 MVT VT = V.getSimpleValueType();
5201 if (VT.is128BitVector()) {
5202 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5203 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5204 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5206 } else if (VT.is256BitVector()) {
5207 // To use VPERMILPS to splat scalars, the second half of indicies must
5208 // refer to the higher part, which is a duplication of the lower one,
5209 // because VPERMILPS can only handle in-lane permutations.
5210 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5211 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5213 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5214 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5217 llvm_unreachable("Vector size not supported");
5219 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5222 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5223 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5224 MVT SrcVT = SV->getSimpleValueType(0);
5225 SDValue V1 = SV->getOperand(0);
5228 int EltNo = SV->getSplatIndex();
5229 int NumElems = SrcVT.getVectorNumElements();
5230 bool Is256BitVec = SrcVT.is256BitVector();
5232 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5233 "Unknown how to promote splat for type");
5235 // Extract the 128-bit part containing the splat element and update
5236 // the splat element index when it refers to the higher register.
5238 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5239 if (EltNo >= NumElems/2)
5240 EltNo -= NumElems/2;
5243 // All i16 and i8 vector types can't be used directly by a generic shuffle
5244 // instruction because the target has no such instruction. Generate shuffles
5245 // which repeat i16 and i8 several times until they fit in i32, and then can
5246 // be manipulated by target suported shuffles.
5247 MVT EltVT = SrcVT.getVectorElementType();
5248 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5249 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5251 // Recreate the 256-bit vector and place the same 128-bit vector
5252 // into the low and high part. This is necessary because we want
5253 // to use VPERM* to shuffle the vectors
5255 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5258 return getLegalSplat(DAG, V1, EltNo);
5261 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5262 /// vector of zero or undef vector. This produces a shuffle where the low
5263 /// element of V2 is swizzled into the zero/undef vector, landing at element
5264 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5265 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5267 const X86Subtarget *Subtarget,
5268 SelectionDAG &DAG) {
5269 MVT VT = V2.getSimpleValueType();
5271 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5272 unsigned NumElems = VT.getVectorNumElements();
5273 SmallVector<int, 16> MaskVec;
5274 for (unsigned i = 0; i != NumElems; ++i)
5275 // If this is the insertion idx, put the low elt of V2 here.
5276 MaskVec.push_back(i == Idx ? NumElems : i);
5277 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5280 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5281 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5282 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5283 /// shuffles which use a single input multiple times, and in those cases it will
5284 /// adjust the mask to only have indices within that single input.
5285 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5286 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5287 unsigned NumElems = VT.getVectorNumElements();
5291 bool IsFakeUnary = false;
5292 switch(N->getOpcode()) {
5293 case X86ISD::BLENDI:
5294 ImmN = N->getOperand(N->getNumOperands()-1);
5295 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5298 ImmN = N->getOperand(N->getNumOperands()-1);
5299 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5300 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5302 case X86ISD::UNPCKH:
5303 DecodeUNPCKHMask(VT, Mask);
5304 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5306 case X86ISD::UNPCKL:
5307 DecodeUNPCKLMask(VT, Mask);
5308 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5310 case X86ISD::MOVHLPS:
5311 DecodeMOVHLPSMask(NumElems, Mask);
5312 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5314 case X86ISD::MOVLHPS:
5315 DecodeMOVLHPSMask(NumElems, Mask);
5316 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5318 case X86ISD::PALIGNR:
5319 ImmN = N->getOperand(N->getNumOperands()-1);
5320 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5322 case X86ISD::PSHUFD:
5323 case X86ISD::VPERMILPI:
5324 ImmN = N->getOperand(N->getNumOperands()-1);
5325 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5328 case X86ISD::PSHUFHW:
5329 ImmN = N->getOperand(N->getNumOperands()-1);
5330 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5333 case X86ISD::PSHUFLW:
5334 ImmN = N->getOperand(N->getNumOperands()-1);
5335 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5338 case X86ISD::PSHUFB: {
5340 SDValue MaskNode = N->getOperand(1);
5341 while (MaskNode->getOpcode() == ISD::BITCAST)
5342 MaskNode = MaskNode->getOperand(0);
5344 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5345 // If we have a build-vector, then things are easy.
5346 EVT VT = MaskNode.getValueType();
5347 assert(VT.isVector() &&
5348 "Can't produce a non-vector with a build_vector!");
5349 if (!VT.isInteger())
5352 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5354 SmallVector<uint64_t, 32> RawMask;
5355 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5356 SDValue Op = MaskNode->getOperand(i);
5357 if (Op->getOpcode() == ISD::UNDEF) {
5358 RawMask.push_back((uint64_t)SM_SentinelUndef);
5361 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5364 APInt MaskElement = CN->getAPIntValue();
5366 // We now have to decode the element which could be any integer size and
5367 // extract each byte of it.
5368 for (int j = 0; j < NumBytesPerElement; ++j) {
5369 // Note that this is x86 and so always little endian: the low byte is
5370 // the first byte of the mask.
5371 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5372 MaskElement = MaskElement.lshr(8);
5375 DecodePSHUFBMask(RawMask, Mask);
5379 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5383 SDValue Ptr = MaskLoad->getBasePtr();
5384 if (Ptr->getOpcode() == X86ISD::Wrapper)
5385 Ptr = Ptr->getOperand(0);
5387 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5388 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5391 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5392 // FIXME: Support AVX-512 here.
5393 Type *Ty = C->getType();
5394 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5395 Ty->getVectorNumElements() != 32))
5398 DecodePSHUFBMask(C, Mask);
5404 case X86ISD::VPERMI:
5405 ImmN = N->getOperand(N->getNumOperands()-1);
5406 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5410 case X86ISD::MOVSD: {
5411 // The index 0 always comes from the first element of the second source,
5412 // this is why MOVSS and MOVSD are used in the first place. The other
5413 // elements come from the other positions of the first source vector
5414 Mask.push_back(NumElems);
5415 for (unsigned i = 1; i != NumElems; ++i) {
5420 case X86ISD::VPERM2X128:
5421 ImmN = N->getOperand(N->getNumOperands()-1);
5422 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5423 if (Mask.empty()) return false;
5425 case X86ISD::MOVSLDUP:
5426 DecodeMOVSLDUPMask(VT, Mask);
5428 case X86ISD::MOVSHDUP:
5429 DecodeMOVSHDUPMask(VT, Mask);
5431 case X86ISD::MOVDDUP:
5432 case X86ISD::MOVLHPD:
5433 case X86ISD::MOVLPD:
5434 case X86ISD::MOVLPS:
5435 // Not yet implemented
5437 default: llvm_unreachable("unknown target shuffle node");
5440 // If we have a fake unary shuffle, the shuffle mask is spread across two
5441 // inputs that are actually the same node. Re-map the mask to always point
5442 // into the first input.
5445 if (M >= (int)Mask.size())
5451 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5452 /// element of the result of the vector shuffle.
5453 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5456 return SDValue(); // Limit search depth.
5458 SDValue V = SDValue(N, 0);
5459 EVT VT = V.getValueType();
5460 unsigned Opcode = V.getOpcode();
5462 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5463 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5464 int Elt = SV->getMaskElt(Index);
5467 return DAG.getUNDEF(VT.getVectorElementType());
5469 unsigned NumElems = VT.getVectorNumElements();
5470 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5471 : SV->getOperand(1);
5472 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5475 // Recurse into target specific vector shuffles to find scalars.
5476 if (isTargetShuffle(Opcode)) {
5477 MVT ShufVT = V.getSimpleValueType();
5478 unsigned NumElems = ShufVT.getVectorNumElements();
5479 SmallVector<int, 16> ShuffleMask;
5482 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5485 int Elt = ShuffleMask[Index];
5487 return DAG.getUNDEF(ShufVT.getVectorElementType());
5489 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5491 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5495 // Actual nodes that may contain scalar elements
5496 if (Opcode == ISD::BITCAST) {
5497 V = V.getOperand(0);
5498 EVT SrcVT = V.getValueType();
5499 unsigned NumElems = VT.getVectorNumElements();
5501 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5505 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5506 return (Index == 0) ? V.getOperand(0)
5507 : DAG.getUNDEF(VT.getVectorElementType());
5509 if (V.getOpcode() == ISD::BUILD_VECTOR)
5510 return V.getOperand(Index);
5515 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5516 /// shuffle operation which come from a consecutively from a zero. The
5517 /// search can start in two different directions, from left or right.
5518 /// We count undefs as zeros until PreferredNum is reached.
5519 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5520 unsigned NumElems, bool ZerosFromLeft,
5522 unsigned PreferredNum = -1U) {
5523 unsigned NumZeros = 0;
5524 for (unsigned i = 0; i != NumElems; ++i) {
5525 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5526 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5530 if (X86::isZeroNode(Elt))
5532 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5533 NumZeros = std::min(NumZeros + 1, PreferredNum);
5541 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5542 /// correspond consecutively to elements from one of the vector operands,
5543 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5545 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5546 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5547 unsigned NumElems, unsigned &OpNum) {
5548 bool SeenV1 = false;
5549 bool SeenV2 = false;
5551 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5552 int Idx = SVOp->getMaskElt(i);
5553 // Ignore undef indicies
5557 if (Idx < (int)NumElems)
5562 // Only accept consecutive elements from the same vector
5563 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5567 OpNum = SeenV1 ? 0 : 1;
5571 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5572 /// logical left shift of a vector.
5573 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5574 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5576 SVOp->getSimpleValueType(0).getVectorNumElements();
5577 unsigned NumZeros = getNumOfConsecutiveZeros(
5578 SVOp, NumElems, false /* check zeros from right */, DAG,
5579 SVOp->getMaskElt(0));
5585 // Considering the elements in the mask that are not consecutive zeros,
5586 // check if they consecutively come from only one of the source vectors.
5588 // V1 = {X, A, B, C} 0
5590 // vector_shuffle V1, V2 <1, 2, 3, X>
5592 if (!isShuffleMaskConsecutive(SVOp,
5593 0, // Mask Start Index
5594 NumElems-NumZeros, // Mask End Index(exclusive)
5595 NumZeros, // Where to start looking in the src vector
5596 NumElems, // Number of elements in vector
5597 OpSrc)) // Which source operand ?
5602 ShVal = SVOp->getOperand(OpSrc);
5606 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5607 /// logical left shift of a vector.
5608 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5609 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5611 SVOp->getSimpleValueType(0).getVectorNumElements();
5612 unsigned NumZeros = getNumOfConsecutiveZeros(
5613 SVOp, NumElems, true /* check zeros from left */, DAG,
5614 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5620 // Considering the elements in the mask that are not consecutive zeros,
5621 // check if they consecutively come from only one of the source vectors.
5623 // 0 { A, B, X, X } = V2
5625 // vector_shuffle V1, V2 <X, X, 4, 5>
5627 if (!isShuffleMaskConsecutive(SVOp,
5628 NumZeros, // Mask Start Index
5629 NumElems, // Mask End Index(exclusive)
5630 0, // Where to start looking in the src vector
5631 NumElems, // Number of elements in vector
5632 OpSrc)) // Which source operand ?
5637 ShVal = SVOp->getOperand(OpSrc);
5641 /// isVectorShift - Returns true if the shuffle can be implemented as a
5642 /// logical left or right shift of a vector.
5643 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5644 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5645 // Although the logic below support any bitwidth size, there are no
5646 // shift instructions which handle more than 128-bit vectors.
5647 if (!SVOp->getSimpleValueType(0).is128BitVector())
5650 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5651 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5657 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5659 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5660 unsigned NumNonZero, unsigned NumZero,
5662 const X86Subtarget* Subtarget,
5663 const TargetLowering &TLI) {
5670 for (unsigned i = 0; i < 16; ++i) {
5671 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5672 if (ThisIsNonZero && First) {
5674 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5676 V = DAG.getUNDEF(MVT::v8i16);
5681 SDValue ThisElt, LastElt;
5682 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5683 if (LastIsNonZero) {
5684 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5685 MVT::i16, Op.getOperand(i-1));
5687 if (ThisIsNonZero) {
5688 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5689 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5690 ThisElt, DAG.getConstant(8, MVT::i8));
5692 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5696 if (ThisElt.getNode())
5697 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5698 DAG.getIntPtrConstant(i/2));
5702 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5705 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5707 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5708 unsigned NumNonZero, unsigned NumZero,
5710 const X86Subtarget* Subtarget,
5711 const TargetLowering &TLI) {
5718 for (unsigned i = 0; i < 8; ++i) {
5719 bool isNonZero = (NonZeros & (1 << i)) != 0;
5723 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5725 V = DAG.getUNDEF(MVT::v8i16);
5728 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5729 MVT::v8i16, V, Op.getOperand(i),
5730 DAG.getIntPtrConstant(i));
5737 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5738 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5739 unsigned NonZeros, unsigned NumNonZero,
5740 unsigned NumZero, SelectionDAG &DAG,
5741 const X86Subtarget *Subtarget,
5742 const TargetLowering &TLI) {
5743 // We know there's at least one non-zero element
5744 unsigned FirstNonZeroIdx = 0;
5745 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5746 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5747 X86::isZeroNode(FirstNonZero)) {
5749 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5752 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5753 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5756 SDValue V = FirstNonZero.getOperand(0);
5757 MVT VVT = V.getSimpleValueType();
5758 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5761 unsigned FirstNonZeroDst =
5762 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5763 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5764 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5765 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5767 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5768 SDValue Elem = Op.getOperand(Idx);
5769 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5772 // TODO: What else can be here? Deal with it.
5773 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5776 // TODO: Some optimizations are still possible here
5777 // ex: Getting one element from a vector, and the rest from another.
5778 if (Elem.getOperand(0) != V)
5781 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5784 else if (IncorrectIdx == -1U) {
5788 // There was already one element with an incorrect index.
5789 // We can't optimize this case to an insertps.
5793 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5795 EVT VT = Op.getSimpleValueType();
5796 unsigned ElementMoveMask = 0;
5797 if (IncorrectIdx == -1U)
5798 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5800 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5802 SDValue InsertpsMask =
5803 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5804 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5810 /// getVShift - Return a vector logical shift node.
5812 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5813 unsigned NumBits, SelectionDAG &DAG,
5814 const TargetLowering &TLI, SDLoc dl) {
5815 assert(VT.is128BitVector() && "Unknown type for VShift");
5816 EVT ShVT = MVT::v2i64;
5817 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5818 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5819 return DAG.getNode(ISD::BITCAST, dl, VT,
5820 DAG.getNode(Opc, dl, ShVT, SrcOp,
5821 DAG.getConstant(NumBits,
5822 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5826 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5828 // Check if the scalar load can be widened into a vector load. And if
5829 // the address is "base + cst" see if the cst can be "absorbed" into
5830 // the shuffle mask.
5831 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5832 SDValue Ptr = LD->getBasePtr();
5833 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5835 EVT PVT = LD->getValueType(0);
5836 if (PVT != MVT::i32 && PVT != MVT::f32)
5841 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5842 FI = FINode->getIndex();
5844 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5845 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5846 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5847 Offset = Ptr.getConstantOperandVal(1);
5848 Ptr = Ptr.getOperand(0);
5853 // FIXME: 256-bit vector instructions don't require a strict alignment,
5854 // improve this code to support it better.
5855 unsigned RequiredAlign = VT.getSizeInBits()/8;
5856 SDValue Chain = LD->getChain();
5857 // Make sure the stack object alignment is at least 16 or 32.
5858 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5859 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5860 if (MFI->isFixedObjectIndex(FI)) {
5861 // Can't change the alignment. FIXME: It's possible to compute
5862 // the exact stack offset and reference FI + adjust offset instead.
5863 // If someone *really* cares about this. That's the way to implement it.
5866 MFI->setObjectAlignment(FI, RequiredAlign);
5870 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5871 // Ptr + (Offset & ~15).
5874 if ((Offset % RequiredAlign) & 3)
5876 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5878 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5879 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5881 int EltNo = (Offset - StartOffset) >> 2;
5882 unsigned NumElems = VT.getVectorNumElements();
5884 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5885 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5886 LD->getPointerInfo().getWithOffset(StartOffset),
5887 false, false, false, 0);
5889 SmallVector<int, 8> Mask;
5890 for (unsigned i = 0; i != NumElems; ++i)
5891 Mask.push_back(EltNo);
5893 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5899 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5900 /// vector of type 'VT', see if the elements can be replaced by a single large
5901 /// load which has the same value as a build_vector whose operands are 'elts'.
5903 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5905 /// FIXME: we'd also like to handle the case where the last elements are zero
5906 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5907 /// There's even a handy isZeroNode for that purpose.
5908 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5909 SDLoc &DL, SelectionDAG &DAG,
5910 bool isAfterLegalize) {
5911 EVT EltVT = VT.getVectorElementType();
5912 unsigned NumElems = Elts.size();
5914 LoadSDNode *LDBase = nullptr;
5915 unsigned LastLoadedElt = -1U;
5917 // For each element in the initializer, see if we've found a load or an undef.
5918 // If we don't find an initial load element, or later load elements are
5919 // non-consecutive, bail out.
5920 for (unsigned i = 0; i < NumElems; ++i) {
5921 SDValue Elt = Elts[i];
5923 if (!Elt.getNode() ||
5924 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5927 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5929 LDBase = cast<LoadSDNode>(Elt.getNode());
5933 if (Elt.getOpcode() == ISD::UNDEF)
5936 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5937 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5942 // If we have found an entire vector of loads and undefs, then return a large
5943 // load of the entire vector width starting at the base pointer. If we found
5944 // consecutive loads for the low half, generate a vzext_load node.
5945 if (LastLoadedElt == NumElems - 1) {
5947 if (isAfterLegalize &&
5948 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5951 SDValue NewLd = SDValue();
5953 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5954 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5955 LDBase->getPointerInfo(),
5956 LDBase->isVolatile(), LDBase->isNonTemporal(),
5957 LDBase->isInvariant(), 0);
5958 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5959 LDBase->getPointerInfo(),
5960 LDBase->isVolatile(), LDBase->isNonTemporal(),
5961 LDBase->isInvariant(), LDBase->getAlignment());
5963 if (LDBase->hasAnyUseOfValue(1)) {
5964 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5966 SDValue(NewLd.getNode(), 1));
5967 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5968 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5969 SDValue(NewLd.getNode(), 1));
5974 if (NumElems == 4 && LastLoadedElt == 1 &&
5975 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5976 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5977 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5979 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5980 LDBase->getPointerInfo(),
5981 LDBase->getAlignment(),
5982 false/*isVolatile*/, true/*ReadMem*/,
5985 // Make sure the newly-created LOAD is in the same position as LDBase in
5986 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5987 // update uses of LDBase's output chain to use the TokenFactor.
5988 if (LDBase->hasAnyUseOfValue(1)) {
5989 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5990 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5991 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5992 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5993 SDValue(ResNode.getNode(), 1));
5996 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6001 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6002 /// to generate a splat value for the following cases:
6003 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6004 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6005 /// a scalar load, or a constant.
6006 /// The VBROADCAST node is returned when a pattern is found,
6007 /// or SDValue() otherwise.
6008 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6009 SelectionDAG &DAG) {
6010 // VBROADCAST requires AVX.
6011 // TODO: Splats could be generated for non-AVX CPUs using SSE
6012 // instructions, but there's less potential gain for only 128-bit vectors.
6013 if (!Subtarget->hasAVX())
6016 MVT VT = Op.getSimpleValueType();
6019 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6020 "Unsupported vector type for broadcast.");
6025 switch (Op.getOpcode()) {
6027 // Unknown pattern found.
6030 case ISD::BUILD_VECTOR: {
6031 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6032 BitVector UndefElements;
6033 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6035 // We need a splat of a single value to use broadcast, and it doesn't
6036 // make any sense if the value is only in one element of the vector.
6037 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6041 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6042 Ld.getOpcode() == ISD::ConstantFP);
6044 // Make sure that all of the users of a non-constant load are from the
6045 // BUILD_VECTOR node.
6046 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6051 case ISD::VECTOR_SHUFFLE: {
6052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6054 // Shuffles must have a splat mask where the first element is
6056 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6059 SDValue Sc = Op.getOperand(0);
6060 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6061 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6063 if (!Subtarget->hasInt256())
6066 // Use the register form of the broadcast instruction available on AVX2.
6067 if (VT.getSizeInBits() >= 256)
6068 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6069 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6072 Ld = Sc.getOperand(0);
6073 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6074 Ld.getOpcode() == ISD::ConstantFP);
6076 // The scalar_to_vector node and the suspected
6077 // load node must have exactly one user.
6078 // Constants may have multiple users.
6080 // AVX-512 has register version of the broadcast
6081 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6082 Ld.getValueType().getSizeInBits() >= 32;
6083 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6090 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6091 bool IsGE256 = (VT.getSizeInBits() >= 256);
6093 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6094 // instruction to save 8 or more bytes of constant pool data.
6095 // TODO: If multiple splats are generated to load the same constant,
6096 // it may be detrimental to overall size. There needs to be a way to detect
6097 // that condition to know if this is truly a size win.
6098 const Function *F = DAG.getMachineFunction().getFunction();
6099 bool OptForSize = F->getAttributes().
6100 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6102 // Handle broadcasting a single constant scalar from the constant pool
6104 // On Sandybridge (no AVX2), it is still better to load a constant vector
6105 // from the constant pool and not to broadcast it from a scalar.
6106 // But override that restriction when optimizing for size.
6107 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6108 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6109 EVT CVT = Ld.getValueType();
6110 assert(!CVT.isVector() && "Must not broadcast a vector type");
6112 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6113 // For size optimization, also splat v2f64 and v2i64, and for size opt
6114 // with AVX2, also splat i8 and i16.
6115 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6116 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6117 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6118 const Constant *C = nullptr;
6119 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6120 C = CI->getConstantIntValue();
6121 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6122 C = CF->getConstantFPValue();
6124 assert(C && "Invalid constant type");
6126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6127 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6128 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6129 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6130 MachinePointerInfo::getConstantPool(),
6131 false, false, false, Alignment);
6133 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6137 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6139 // Handle AVX2 in-register broadcasts.
6140 if (!IsLoad && Subtarget->hasInt256() &&
6141 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6142 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6144 // The scalar source must be a normal load.
6148 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6149 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6151 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6152 // double since there is no vbroadcastsd xmm
6153 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6154 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6155 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6158 // Unsupported broadcast.
6162 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6163 /// underlying vector and index.
6165 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6167 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6169 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6170 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6173 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6175 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6177 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6178 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6181 // In this case the vector is the extract_subvector expression and the index
6182 // is 2, as specified by the shuffle.
6183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6184 SDValue ShuffleVec = SVOp->getOperand(0);
6185 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6186 assert(ShuffleVecVT.getVectorElementType() ==
6187 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6189 int ShuffleIdx = SVOp->getMaskElt(Idx);
6190 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6191 ExtractedFromVec = ShuffleVec;
6197 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6198 MVT VT = Op.getSimpleValueType();
6200 // Skip if insert_vec_elt is not supported.
6201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6202 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6206 unsigned NumElems = Op.getNumOperands();
6210 SmallVector<unsigned, 4> InsertIndices;
6211 SmallVector<int, 8> Mask(NumElems, -1);
6213 for (unsigned i = 0; i != NumElems; ++i) {
6214 unsigned Opc = Op.getOperand(i).getOpcode();
6216 if (Opc == ISD::UNDEF)
6219 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6220 // Quit if more than 1 elements need inserting.
6221 if (InsertIndices.size() > 1)
6224 InsertIndices.push_back(i);
6228 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6229 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6230 // Quit if non-constant index.
6231 if (!isa<ConstantSDNode>(ExtIdx))
6233 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6235 // Quit if extracted from vector of different type.
6236 if (ExtractedFromVec.getValueType() != VT)
6239 if (!VecIn1.getNode())
6240 VecIn1 = ExtractedFromVec;
6241 else if (VecIn1 != ExtractedFromVec) {
6242 if (!VecIn2.getNode())
6243 VecIn2 = ExtractedFromVec;
6244 else if (VecIn2 != ExtractedFromVec)
6245 // Quit if more than 2 vectors to shuffle
6249 if (ExtractedFromVec == VecIn1)
6251 else if (ExtractedFromVec == VecIn2)
6252 Mask[i] = Idx + NumElems;
6255 if (!VecIn1.getNode())
6258 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6259 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6260 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6261 unsigned Idx = InsertIndices[i];
6262 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6263 DAG.getIntPtrConstant(Idx));
6269 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6271 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6273 MVT VT = Op.getSimpleValueType();
6274 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6275 "Unexpected type in LowerBUILD_VECTORvXi1!");
6278 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6279 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6280 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6281 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6284 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6285 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6286 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6287 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6290 bool AllContants = true;
6291 uint64_t Immediate = 0;
6292 int NonConstIdx = -1;
6293 bool IsSplat = true;
6294 unsigned NumNonConsts = 0;
6295 unsigned NumConsts = 0;
6296 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6297 SDValue In = Op.getOperand(idx);
6298 if (In.getOpcode() == ISD::UNDEF)
6300 if (!isa<ConstantSDNode>(In)) {
6301 AllContants = false;
6307 if (cast<ConstantSDNode>(In)->getZExtValue())
6308 Immediate |= (1ULL << idx);
6310 if (In != Op.getOperand(0))
6315 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6316 DAG.getConstant(Immediate, MVT::i16));
6317 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6318 DAG.getIntPtrConstant(0));
6321 if (NumNonConsts == 1 && NonConstIdx != 0) {
6324 SDValue VecAsImm = DAG.getConstant(Immediate,
6325 MVT::getIntegerVT(VT.getSizeInBits()));
6326 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6329 DstVec = DAG.getUNDEF(VT);
6330 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6331 Op.getOperand(NonConstIdx),
6332 DAG.getIntPtrConstant(NonConstIdx));
6334 if (!IsSplat && (NonConstIdx != 0))
6335 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6336 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6339 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6340 DAG.getConstant(-1, SelectVT),
6341 DAG.getConstant(0, SelectVT));
6343 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6344 DAG.getConstant((Immediate | 1), SelectVT),
6345 DAG.getConstant(Immediate, SelectVT));
6346 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6349 /// \brief Return true if \p N implements a horizontal binop and return the
6350 /// operands for the horizontal binop into V0 and V1.
6352 /// This is a helper function of PerformBUILD_VECTORCombine.
6353 /// This function checks that the build_vector \p N in input implements a
6354 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6355 /// operation to match.
6356 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6357 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6358 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6361 /// This function only analyzes elements of \p N whose indices are
6362 /// in range [BaseIdx, LastIdx).
6363 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6365 unsigned BaseIdx, unsigned LastIdx,
6366 SDValue &V0, SDValue &V1) {
6367 EVT VT = N->getValueType(0);
6369 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6370 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6371 "Invalid Vector in input!");
6373 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6374 bool CanFold = true;
6375 unsigned ExpectedVExtractIdx = BaseIdx;
6376 unsigned NumElts = LastIdx - BaseIdx;
6377 V0 = DAG.getUNDEF(VT);
6378 V1 = DAG.getUNDEF(VT);
6380 // Check if N implements a horizontal binop.
6381 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6382 SDValue Op = N->getOperand(i + BaseIdx);
6385 if (Op->getOpcode() == ISD::UNDEF) {
6386 // Update the expected vector extract index.
6387 if (i * 2 == NumElts)
6388 ExpectedVExtractIdx = BaseIdx;
6389 ExpectedVExtractIdx += 2;
6393 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6398 SDValue Op0 = Op.getOperand(0);
6399 SDValue Op1 = Op.getOperand(1);
6401 // Try to match the following pattern:
6402 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6403 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6405 Op0.getOperand(0) == Op1.getOperand(0) &&
6406 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6407 isa<ConstantSDNode>(Op1.getOperand(1)));
6411 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6412 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6414 if (i * 2 < NumElts) {
6415 if (V0.getOpcode() == ISD::UNDEF)
6416 V0 = Op0.getOperand(0);
6418 if (V1.getOpcode() == ISD::UNDEF)
6419 V1 = Op0.getOperand(0);
6420 if (i * 2 == NumElts)
6421 ExpectedVExtractIdx = BaseIdx;
6424 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6425 if (I0 == ExpectedVExtractIdx)
6426 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6427 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6428 // Try to match the following dag sequence:
6429 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6430 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6434 ExpectedVExtractIdx += 2;
6440 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6441 /// a concat_vector.
6443 /// This is a helper function of PerformBUILD_VECTORCombine.
6444 /// This function expects two 256-bit vectors called V0 and V1.
6445 /// At first, each vector is split into two separate 128-bit vectors.
6446 /// Then, the resulting 128-bit vectors are used to implement two
6447 /// horizontal binary operations.
6449 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6451 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6452 /// the two new horizontal binop.
6453 /// When Mode is set, the first horizontal binop dag node would take as input
6454 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6455 /// horizontal binop dag node would take as input the lower 128-bit of V1
6456 /// and the upper 128-bit of V1.
6458 /// HADD V0_LO, V0_HI
6459 /// HADD V1_LO, V1_HI
6461 /// Otherwise, the first horizontal binop dag node takes as input the lower
6462 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6463 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6465 /// HADD V0_LO, V1_LO
6466 /// HADD V0_HI, V1_HI
6468 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6469 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6470 /// the upper 128-bits of the result.
6471 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6472 SDLoc DL, SelectionDAG &DAG,
6473 unsigned X86Opcode, bool Mode,
6474 bool isUndefLO, bool isUndefHI) {
6475 EVT VT = V0.getValueType();
6476 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6477 "Invalid nodes in input!");
6479 unsigned NumElts = VT.getVectorNumElements();
6480 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6481 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6482 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6483 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6484 EVT NewVT = V0_LO.getValueType();
6486 SDValue LO = DAG.getUNDEF(NewVT);
6487 SDValue HI = DAG.getUNDEF(NewVT);
6490 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6491 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6492 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6493 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6494 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6496 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6497 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6498 V1_LO->getOpcode() != ISD::UNDEF))
6499 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6501 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6502 V1_HI->getOpcode() != ISD::UNDEF))
6503 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6506 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6509 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6510 /// sequence of 'vadd + vsub + blendi'.
6511 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6512 const X86Subtarget *Subtarget) {
6514 EVT VT = BV->getValueType(0);
6515 unsigned NumElts = VT.getVectorNumElements();
6516 SDValue InVec0 = DAG.getUNDEF(VT);
6517 SDValue InVec1 = DAG.getUNDEF(VT);
6519 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6520 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6522 // Odd-numbered elements in the input build vector are obtained from
6523 // adding two integer/float elements.
6524 // Even-numbered elements in the input build vector are obtained from
6525 // subtracting two integer/float elements.
6526 unsigned ExpectedOpcode = ISD::FSUB;
6527 unsigned NextExpectedOpcode = ISD::FADD;
6528 bool AddFound = false;
6529 bool SubFound = false;
6531 for (unsigned i = 0, e = NumElts; i != e; i++) {
6532 SDValue Op = BV->getOperand(i);
6534 // Skip 'undef' values.
6535 unsigned Opcode = Op.getOpcode();
6536 if (Opcode == ISD::UNDEF) {
6537 std::swap(ExpectedOpcode, NextExpectedOpcode);
6541 // Early exit if we found an unexpected opcode.
6542 if (Opcode != ExpectedOpcode)
6545 SDValue Op0 = Op.getOperand(0);
6546 SDValue Op1 = Op.getOperand(1);
6548 // Try to match the following pattern:
6549 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6550 // Early exit if we cannot match that sequence.
6551 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6553 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6554 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6555 Op0.getOperand(1) != Op1.getOperand(1))
6558 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6562 // We found a valid add/sub node. Update the information accordingly.
6568 // Update InVec0 and InVec1.
6569 if (InVec0.getOpcode() == ISD::UNDEF)
6570 InVec0 = Op0.getOperand(0);
6571 if (InVec1.getOpcode() == ISD::UNDEF)
6572 InVec1 = Op1.getOperand(0);
6574 // Make sure that operands in input to each add/sub node always
6575 // come from a same pair of vectors.
6576 if (InVec0 != Op0.getOperand(0)) {
6577 if (ExpectedOpcode == ISD::FSUB)
6580 // FADD is commutable. Try to commute the operands
6581 // and then test again.
6582 std::swap(Op0, Op1);
6583 if (InVec0 != Op0.getOperand(0))
6587 if (InVec1 != Op1.getOperand(0))
6590 // Update the pair of expected opcodes.
6591 std::swap(ExpectedOpcode, NextExpectedOpcode);
6594 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6595 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6596 InVec1.getOpcode() != ISD::UNDEF)
6597 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6602 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6603 const X86Subtarget *Subtarget) {
6605 EVT VT = N->getValueType(0);
6606 unsigned NumElts = VT.getVectorNumElements();
6607 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6608 SDValue InVec0, InVec1;
6610 // Try to match an ADDSUB.
6611 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6612 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6613 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6614 if (Value.getNode())
6618 // Try to match horizontal ADD/SUB.
6619 unsigned NumUndefsLO = 0;
6620 unsigned NumUndefsHI = 0;
6621 unsigned Half = NumElts/2;
6623 // Count the number of UNDEF operands in the build_vector in input.
6624 for (unsigned i = 0, e = Half; i != e; ++i)
6625 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6628 for (unsigned i = Half, e = NumElts; i != e; ++i)
6629 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6632 // Early exit if this is either a build_vector of all UNDEFs or all the
6633 // operands but one are UNDEF.
6634 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6637 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6638 // Try to match an SSE3 float HADD/HSUB.
6639 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6640 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6642 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6643 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6644 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6645 // Try to match an SSSE3 integer HADD/HSUB.
6646 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6647 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6649 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6650 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6653 if (!Subtarget->hasAVX())
6656 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6657 // Try to match an AVX horizontal add/sub of packed single/double
6658 // precision floating point values from 256-bit vectors.
6659 SDValue InVec2, InVec3;
6660 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6661 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6662 ((InVec0.getOpcode() == ISD::UNDEF ||
6663 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6664 ((InVec1.getOpcode() == ISD::UNDEF ||
6665 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6666 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6668 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6669 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6670 ((InVec0.getOpcode() == ISD::UNDEF ||
6671 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6672 ((InVec1.getOpcode() == ISD::UNDEF ||
6673 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6674 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6675 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6676 // Try to match an AVX2 horizontal add/sub of signed integers.
6677 SDValue InVec2, InVec3;
6679 bool CanFold = true;
6681 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6682 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6683 ((InVec0.getOpcode() == ISD::UNDEF ||
6684 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6685 ((InVec1.getOpcode() == ISD::UNDEF ||
6686 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6687 X86Opcode = X86ISD::HADD;
6688 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6689 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6690 ((InVec0.getOpcode() == ISD::UNDEF ||
6691 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6692 ((InVec1.getOpcode() == ISD::UNDEF ||
6693 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6694 X86Opcode = X86ISD::HSUB;
6699 // Fold this build_vector into a single horizontal add/sub.
6700 // Do this only if the target has AVX2.
6701 if (Subtarget->hasAVX2())
6702 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6704 // Do not try to expand this build_vector into a pair of horizontal
6705 // add/sub if we can emit a pair of scalar add/sub.
6706 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6709 // Convert this build_vector into a pair of horizontal binop followed by
6711 bool isUndefLO = NumUndefsLO == Half;
6712 bool isUndefHI = NumUndefsHI == Half;
6713 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6714 isUndefLO, isUndefHI);
6718 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6719 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6721 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6722 X86Opcode = X86ISD::HADD;
6723 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6724 X86Opcode = X86ISD::HSUB;
6725 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6726 X86Opcode = X86ISD::FHADD;
6727 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6728 X86Opcode = X86ISD::FHSUB;
6732 // Don't try to expand this build_vector into a pair of horizontal add/sub
6733 // if we can simply emit a pair of scalar add/sub.
6734 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6737 // Convert this build_vector into two horizontal add/sub followed by
6739 bool isUndefLO = NumUndefsLO == Half;
6740 bool isUndefHI = NumUndefsHI == Half;
6741 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6742 isUndefLO, isUndefHI);
6749 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6752 MVT VT = Op.getSimpleValueType();
6753 MVT ExtVT = VT.getVectorElementType();
6754 unsigned NumElems = Op.getNumOperands();
6756 // Generate vectors for predicate vectors.
6757 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6758 return LowerBUILD_VECTORvXi1(Op, DAG);
6760 // Vectors containing all zeros can be matched by pxor and xorps later
6761 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6762 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6763 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6764 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6767 return getZeroVector(VT, Subtarget, DAG, dl);
6770 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6771 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6772 // vpcmpeqd on 256-bit vectors.
6773 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6774 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6777 if (!VT.is512BitVector())
6778 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6781 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6782 if (Broadcast.getNode())
6785 unsigned EVTBits = ExtVT.getSizeInBits();
6787 unsigned NumZero = 0;
6788 unsigned NumNonZero = 0;
6789 unsigned NonZeros = 0;
6790 bool IsAllConstants = true;
6791 SmallSet<SDValue, 8> Values;
6792 for (unsigned i = 0; i < NumElems; ++i) {
6793 SDValue Elt = Op.getOperand(i);
6794 if (Elt.getOpcode() == ISD::UNDEF)
6797 if (Elt.getOpcode() != ISD::Constant &&
6798 Elt.getOpcode() != ISD::ConstantFP)
6799 IsAllConstants = false;
6800 if (X86::isZeroNode(Elt))
6803 NonZeros |= (1 << i);
6808 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6809 if (NumNonZero == 0)
6810 return DAG.getUNDEF(VT);
6812 // Special case for single non-zero, non-undef, element.
6813 if (NumNonZero == 1) {
6814 unsigned Idx = countTrailingZeros(NonZeros);
6815 SDValue Item = Op.getOperand(Idx);
6817 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6818 // the value are obviously zero, truncate the value to i32 and do the
6819 // insertion that way. Only do this if the value is non-constant or if the
6820 // value is a constant being inserted into element 0. It is cheaper to do
6821 // a constant pool load than it is to do a movd + shuffle.
6822 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6823 (!IsAllConstants || Idx == 0)) {
6824 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6826 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6827 EVT VecVT = MVT::v4i32;
6828 unsigned VecElts = 4;
6830 // Truncate the value (which may itself be a constant) to i32, and
6831 // convert it to a vector with movd (S2V+shuffle to zero extend).
6832 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6833 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6835 // If using the new shuffle lowering, just directly insert this.
6836 if (ExperimentalVectorShuffleLowering)
6838 ISD::BITCAST, dl, VT,
6839 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6841 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6843 // Now we have our 32-bit value zero extended in the low element of
6844 // a vector. If Idx != 0, swizzle it into place.
6846 SmallVector<int, 4> Mask;
6847 Mask.push_back(Idx);
6848 for (unsigned i = 1; i != VecElts; ++i)
6850 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6853 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6857 // If we have a constant or non-constant insertion into the low element of
6858 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6859 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6860 // depending on what the source datatype is.
6863 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6865 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6866 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6867 if (VT.is256BitVector() || VT.is512BitVector()) {
6868 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6869 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6870 Item, DAG.getIntPtrConstant(0));
6872 assert(VT.is128BitVector() && "Expected an SSE value type!");
6873 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6874 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6875 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6878 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6879 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6880 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6881 if (VT.is256BitVector()) {
6882 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6883 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6885 assert(VT.is128BitVector() && "Expected an SSE value type!");
6886 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6888 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6892 // Is it a vector logical left shift?
6893 if (NumElems == 2 && Idx == 1 &&
6894 X86::isZeroNode(Op.getOperand(0)) &&
6895 !X86::isZeroNode(Op.getOperand(1))) {
6896 unsigned NumBits = VT.getSizeInBits();
6897 return getVShift(true, VT,
6898 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6899 VT, Op.getOperand(1)),
6900 NumBits/2, DAG, *this, dl);
6903 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6906 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6907 // is a non-constant being inserted into an element other than the low one,
6908 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6909 // movd/movss) to move this into the low element, then shuffle it into
6911 if (EVTBits == 32) {
6912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6914 // If using the new shuffle lowering, just directly insert this.
6915 if (ExperimentalVectorShuffleLowering)
6916 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6918 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6919 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6920 SmallVector<int, 8> MaskVec;
6921 for (unsigned i = 0; i != NumElems; ++i)
6922 MaskVec.push_back(i == Idx ? 0 : 1);
6923 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6927 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6928 if (Values.size() == 1) {
6929 if (EVTBits == 32) {
6930 // Instead of a shuffle like this:
6931 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6932 // Check if it's possible to issue this instead.
6933 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6934 unsigned Idx = countTrailingZeros(NonZeros);
6935 SDValue Item = Op.getOperand(Idx);
6936 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6937 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6942 // A vector full of immediates; various special cases are already
6943 // handled, so this is best done with a single constant-pool load.
6947 // For AVX-length vectors, build the individual 128-bit pieces and use
6948 // shuffles to put them in place.
6949 if (VT.is256BitVector() || VT.is512BitVector()) {
6950 SmallVector<SDValue, 64> V;
6951 for (unsigned i = 0; i != NumElems; ++i)
6952 V.push_back(Op.getOperand(i));
6954 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6956 // Build both the lower and upper subvector.
6957 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6958 makeArrayRef(&V[0], NumElems/2));
6959 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6960 makeArrayRef(&V[NumElems / 2], NumElems/2));
6962 // Recreate the wider vector with the lower and upper part.
6963 if (VT.is256BitVector())
6964 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6965 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6968 // Let legalizer expand 2-wide build_vectors.
6969 if (EVTBits == 64) {
6970 if (NumNonZero == 1) {
6971 // One half is zero or undef.
6972 unsigned Idx = countTrailingZeros(NonZeros);
6973 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6974 Op.getOperand(Idx));
6975 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6980 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6981 if (EVTBits == 8 && NumElems == 16) {
6982 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6984 if (V.getNode()) return V;
6987 if (EVTBits == 16 && NumElems == 8) {
6988 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6990 if (V.getNode()) return V;
6993 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6994 if (EVTBits == 32 && NumElems == 4) {
6995 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6996 NumZero, DAG, Subtarget, *this);
7001 // If element VT is == 32 bits, turn it into a number of shuffles.
7002 SmallVector<SDValue, 8> V(NumElems);
7003 if (NumElems == 4 && NumZero > 0) {
7004 for (unsigned i = 0; i < 4; ++i) {
7005 bool isZero = !(NonZeros & (1 << i));
7007 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7009 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7012 for (unsigned i = 0; i < 2; ++i) {
7013 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7016 V[i] = V[i*2]; // Must be a zero vector.
7019 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7022 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7025 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7030 bool Reverse1 = (NonZeros & 0x3) == 2;
7031 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7035 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7036 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7038 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7041 if (Values.size() > 1 && VT.is128BitVector()) {
7042 // Check for a build vector of consecutive loads.
7043 for (unsigned i = 0; i < NumElems; ++i)
7044 V[i] = Op.getOperand(i);
7046 // Check for elements which are consecutive loads.
7047 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7051 // Check for a build vector from mostly shuffle plus few inserting.
7052 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7056 // For SSE 4.1, use insertps to put the high elements into the low element.
7057 if (getSubtarget()->hasSSE41()) {
7059 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7060 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7062 Result = DAG.getUNDEF(VT);
7064 for (unsigned i = 1; i < NumElems; ++i) {
7065 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7066 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7067 Op.getOperand(i), DAG.getIntPtrConstant(i));
7072 // Otherwise, expand into a number of unpckl*, start by extending each of
7073 // our (non-undef) elements to the full vector width with the element in the
7074 // bottom slot of the vector (which generates no code for SSE).
7075 for (unsigned i = 0; i < NumElems; ++i) {
7076 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7077 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7079 V[i] = DAG.getUNDEF(VT);
7082 // Next, we iteratively mix elements, e.g. for v4f32:
7083 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7084 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7085 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7086 unsigned EltStride = NumElems >> 1;
7087 while (EltStride != 0) {
7088 for (unsigned i = 0; i < EltStride; ++i) {
7089 // If V[i+EltStride] is undef and this is the first round of mixing,
7090 // then it is safe to just drop this shuffle: V[i] is already in the
7091 // right place, the one element (since it's the first round) being
7092 // inserted as undef can be dropped. This isn't safe for successive
7093 // rounds because they will permute elements within both vectors.
7094 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7095 EltStride == NumElems/2)
7098 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7107 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7108 // to create 256-bit vectors from two other 128-bit ones.
7109 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7111 MVT ResVT = Op.getSimpleValueType();
7113 assert((ResVT.is256BitVector() ||
7114 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7116 SDValue V1 = Op.getOperand(0);
7117 SDValue V2 = Op.getOperand(1);
7118 unsigned NumElems = ResVT.getVectorNumElements();
7119 if(ResVT.is256BitVector())
7120 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7122 if (Op.getNumOperands() == 4) {
7123 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7124 ResVT.getVectorNumElements()/2);
7125 SDValue V3 = Op.getOperand(2);
7126 SDValue V4 = Op.getOperand(3);
7127 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7128 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7130 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7133 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7134 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7135 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7136 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7137 Op.getNumOperands() == 4)));
7139 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7140 // from two other 128-bit ones.
7142 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7143 return LowerAVXCONCAT_VECTORS(Op, DAG);
7147 //===----------------------------------------------------------------------===//
7148 // Vector shuffle lowering
7150 // This is an experimental code path for lowering vector shuffles on x86. It is
7151 // designed to handle arbitrary vector shuffles and blends, gracefully
7152 // degrading performance as necessary. It works hard to recognize idiomatic
7153 // shuffles and lower them to optimal instruction patterns without leaving
7154 // a framework that allows reasonably efficient handling of all vector shuffle
7156 //===----------------------------------------------------------------------===//
7158 /// \brief Tiny helper function to identify a no-op mask.
7160 /// This is a somewhat boring predicate function. It checks whether the mask
7161 /// array input, which is assumed to be a single-input shuffle mask of the kind
7162 /// used by the X86 shuffle instructions (not a fully general
7163 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7164 /// in-place shuffle are 'no-op's.
7165 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7166 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7167 if (Mask[i] != -1 && Mask[i] != i)
7172 /// \brief Helper function to classify a mask as a single-input mask.
7174 /// This isn't a generic single-input test because in the vector shuffle
7175 /// lowering we canonicalize single inputs to be the first input operand. This
7176 /// means we can more quickly test for a single input by only checking whether
7177 /// an input from the second operand exists. We also assume that the size of
7178 /// mask corresponds to the size of the input vectors which isn't true in the
7179 /// fully general case.
7180 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7182 if (M >= (int)Mask.size())
7187 /// \brief Test whether there are elements crossing 128-bit lanes in this
7190 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7191 /// and we routinely test for these.
7192 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7193 int LaneSize = 128 / VT.getScalarSizeInBits();
7194 int Size = Mask.size();
7195 for (int i = 0; i < Size; ++i)
7196 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7201 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7203 /// This checks a shuffle mask to see if it is performing the same
7204 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7205 /// that it is also not lane-crossing. It may however involve a blend from the
7206 /// same lane of a second vector.
7208 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7209 /// non-trivial to compute in the face of undef lanes. The representation is
7210 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7211 /// entries from both V1 and V2 inputs to the wider mask.
7213 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7214 SmallVectorImpl<int> &RepeatedMask) {
7215 int LaneSize = 128 / VT.getScalarSizeInBits();
7216 RepeatedMask.resize(LaneSize, -1);
7217 int Size = Mask.size();
7218 for (int i = 0; i < Size; ++i) {
7221 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7222 // This entry crosses lanes, so there is no way to model this shuffle.
7225 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7226 if (RepeatedMask[i % LaneSize] == -1)
7227 // This is the first non-undef entry in this slot of a 128-bit lane.
7228 RepeatedMask[i % LaneSize] =
7229 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7230 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7231 // Found a mismatch with the repeated mask.
7237 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7238 // 2013 will allow us to use it as a non-type template parameter.
7241 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7243 /// See its documentation for details.
7244 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7245 if (Mask.size() != Args.size())
7247 for (int i = 0, e = Mask.size(); i < e; ++i) {
7248 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7249 if (Mask[i] != -1 && Mask[i] != *Args[i])
7257 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7260 /// This is a fast way to test a shuffle mask against a fixed pattern:
7262 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7264 /// It returns true if the mask is exactly as wide as the argument list, and
7265 /// each element of the mask is either -1 (signifying undef) or the value given
7266 /// in the argument.
7267 static const VariadicFunction1<
7268 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7270 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7272 /// This helper function produces an 8-bit shuffle immediate corresponding to
7273 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7274 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7277 /// NB: We rely heavily on "undef" masks preserving the input lane.
7278 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7279 SelectionDAG &DAG) {
7280 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7281 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7282 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7283 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7284 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7287 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7288 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7289 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7290 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7291 return DAG.getConstant(Imm, MVT::i8);
7294 /// \brief Try to emit a blend instruction for a shuffle.
7296 /// This doesn't do any checks for the availability of instructions for blending
7297 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7298 /// be matched in the backend with the type given. What it does check for is
7299 /// that the shuffle mask is in fact a blend.
7300 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7301 SDValue V2, ArrayRef<int> Mask,
7302 const X86Subtarget *Subtarget,
7303 SelectionDAG &DAG) {
7305 unsigned BlendMask = 0;
7306 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7307 if (Mask[i] >= Size) {
7308 if (Mask[i] != i + Size)
7309 return SDValue(); // Shuffled V2 input!
7310 BlendMask |= 1u << i;
7313 if (Mask[i] >= 0 && Mask[i] != i)
7314 return SDValue(); // Shuffled V1 input!
7316 switch (VT.SimpleTy) {
7321 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7322 DAG.getConstant(BlendMask, MVT::i8));
7326 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7330 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7331 // that instruction.
7332 if (Subtarget->hasAVX2()) {
7333 // Scale the blend by the number of 32-bit dwords per element.
7334 int Scale = VT.getScalarSizeInBits() / 32;
7336 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7337 if (Mask[i] >= Size)
7338 for (int j = 0; j < Scale; ++j)
7339 BlendMask |= 1u << (i * Scale + j);
7341 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7342 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7343 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7344 return DAG.getNode(ISD::BITCAST, DL, VT,
7345 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7346 DAG.getConstant(BlendMask, MVT::i8)));
7350 // For integer shuffles we need to expand the mask and cast the inputs to
7351 // v8i16s prior to blending.
7352 int Scale = 8 / VT.getVectorNumElements();
7354 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7355 if (Mask[i] >= Size)
7356 for (int j = 0; j < Scale; ++j)
7357 BlendMask |= 1u << (i * Scale + j);
7359 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7360 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7361 return DAG.getNode(ISD::BITCAST, DL, VT,
7362 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7363 DAG.getConstant(BlendMask, MVT::i8)));
7367 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7368 SmallVector<int, 8> RepeatedMask;
7369 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7370 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7371 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7373 for (int i = 0; i < 8; ++i)
7374 if (RepeatedMask[i] >= 16)
7375 BlendMask |= 1u << i;
7376 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7377 DAG.getConstant(BlendMask, MVT::i8));
7382 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7383 // Scale the blend by the number of bytes per element.
7384 int Scale = VT.getScalarSizeInBits() / 8;
7385 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7387 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7388 // mix of LLVM's code generator and the x86 backend. We tell the code
7389 // generator that boolean values in the elements of an x86 vector register
7390 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7391 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7392 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7393 // of the element (the remaining are ignored) and 0 in that high bit would
7394 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7395 // the LLVM model for boolean values in vector elements gets the relevant
7396 // bit set, it is set backwards and over constrained relative to x86's
7398 SDValue VSELECTMask[32];
7399 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7400 for (int j = 0; j < Scale; ++j)
7401 VSELECTMask[Scale * i + j] =
7402 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7403 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7405 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7406 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7408 ISD::BITCAST, DL, VT,
7409 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7410 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7415 llvm_unreachable("Not a supported integer vector type!");
7419 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7420 /// unblended shuffles followed by an unshuffled blend.
7422 /// This matches the extremely common pattern for handling combined
7423 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7425 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7429 SelectionDAG &DAG) {
7430 // Shuffle the input elements into the desired positions in V1 and V2 and
7431 // blend them together.
7432 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7433 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7434 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7435 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7436 if (Mask[i] >= 0 && Mask[i] < Size) {
7437 V1Mask[i] = Mask[i];
7439 } else if (Mask[i] >= Size) {
7440 V2Mask[i] = Mask[i] - Size;
7441 BlendMask[i] = i + Size;
7444 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7445 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7446 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7449 /// \brief Try to lower a vector shuffle as a byte rotation.
7451 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7452 /// byte-rotation of a the concatentation of two vectors. This routine will
7453 /// try to generically lower a vector shuffle through such an instruction. It
7454 /// does not check for the availability of PALIGNR-based lowerings, only the
7455 /// applicability of this strategy to the given mask. This matches shuffle
7456 /// vectors that look like:
7458 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7460 /// Essentially it concatenates V1 and V2, shifts right by some number of
7461 /// elements, and takes the low elements as the result. Note that while this is
7462 /// specified as a *right shift* because x86 is little-endian, it is a *left
7463 /// rotate* of the vector lanes.
7465 /// Note that this only handles 128-bit vector widths currently.
7466 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7469 SelectionDAG &DAG) {
7470 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7472 // We need to detect various ways of spelling a rotation:
7473 // [11, 12, 13, 14, 15, 0, 1, 2]
7474 // [-1, 12, 13, 14, -1, -1, 1, -1]
7475 // [-1, -1, -1, -1, -1, -1, 1, 2]
7476 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7477 // [-1, 4, 5, 6, -1, -1, 9, -1]
7478 // [-1, 4, 5, 6, -1, -1, -1, -1]
7481 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7484 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7486 // Based on the mod-Size value of this mask element determine where
7487 // a rotated vector would have started.
7488 int StartIdx = i - (Mask[i] % Size);
7490 // The identity rotation isn't interesting, stop.
7493 // If we found the tail of a vector the rotation must be the missing
7494 // front. If we found the head of a vector, it must be how much of the head.
7495 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7498 Rotation = CandidateRotation;
7499 else if (Rotation != CandidateRotation)
7500 // The rotations don't match, so we can't match this mask.
7503 // Compute which value this mask is pointing at.
7504 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7506 // Compute which of the two target values this index should be assigned to.
7507 // This reflects whether the high elements are remaining or the low elements
7509 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7511 // Either set up this value if we've not encountered it before, or check
7512 // that it remains consistent.
7515 else if (TargetV != MaskV)
7516 // This may be a rotation, but it pulls from the inputs in some
7517 // unsupported interleaving.
7521 // Check that we successfully analyzed the mask, and normalize the results.
7522 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7523 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7529 // Cast the inputs to v16i8 to match PALIGNR.
7530 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7531 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7533 assert(VT.getSizeInBits() == 128 &&
7534 "Rotate-based lowering only supports 128-bit lowering!");
7535 assert(Mask.size() <= 16 &&
7536 "Can shuffle at most 16 bytes in a 128-bit vector!");
7537 // The actual rotate instruction rotates bytes, so we need to scale the
7538 // rotation based on how many bytes are in the vector.
7539 int Scale = 16 / Mask.size();
7541 return DAG.getNode(ISD::BITCAST, DL, VT,
7542 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7543 DAG.getConstant(Rotation * Scale, MVT::i8)));
7546 /// \brief Compute whether each element of a shuffle is zeroable.
7548 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7549 /// Either it is an undef element in the shuffle mask, the element of the input
7550 /// referenced is undef, or the element of the input referenced is known to be
7551 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7552 /// as many lanes with this technique as possible to simplify the remaining
7554 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7555 SDValue V1, SDValue V2) {
7556 SmallBitVector Zeroable(Mask.size(), false);
7558 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7559 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7561 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7563 // Handle the easy cases.
7564 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7569 // If this is an index into a build_vector node, dig out the input value and
7571 SDValue V = M < Size ? V1 : V2;
7572 if (V.getOpcode() != ISD::BUILD_VECTOR)
7575 SDValue Input = V.getOperand(M % Size);
7576 // The UNDEF opcode check really should be dead code here, but not quite
7577 // worth asserting on (it isn't invalid, just unexpected).
7578 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7585 /// \brief Lower a vector shuffle as a zero or any extension.
7587 /// Given a specific number of elements, element bit width, and extension
7588 /// stride, produce either a zero or any extension based on the available
7589 /// features of the subtarget.
7590 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7591 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7592 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7593 assert(Scale > 1 && "Need a scale to extend.");
7594 int EltBits = VT.getSizeInBits() / NumElements;
7595 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7596 "Only 8, 16, and 32 bit elements can be extended.");
7597 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7599 // Found a valid zext mask! Try various lowering strategies based on the
7600 // input type and available ISA extensions.
7601 if (Subtarget->hasSSE41()) {
7602 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7603 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7604 NumElements / Scale);
7605 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7606 return DAG.getNode(ISD::BITCAST, DL, VT,
7607 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7610 // For any extends we can cheat for larger element sizes and use shuffle
7611 // instructions that can fold with a load and/or copy.
7612 if (AnyExt && EltBits == 32) {
7613 int PSHUFDMask[4] = {0, -1, 1, -1};
7615 ISD::BITCAST, DL, VT,
7616 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7617 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7618 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7620 if (AnyExt && EltBits == 16 && Scale > 2) {
7621 int PSHUFDMask[4] = {0, -1, 0, -1};
7622 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7623 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7624 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7625 int PSHUFHWMask[4] = {1, -1, -1, -1};
7627 ISD::BITCAST, DL, VT,
7628 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7629 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7630 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7633 // If this would require more than 2 unpack instructions to expand, use
7634 // pshufb when available. We can only use more than 2 unpack instructions
7635 // when zero extending i8 elements which also makes it easier to use pshufb.
7636 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7637 assert(NumElements == 16 && "Unexpected byte vector width!");
7638 SDValue PSHUFBMask[16];
7639 for (int i = 0; i < 16; ++i)
7641 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7642 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7643 return DAG.getNode(ISD::BITCAST, DL, VT,
7644 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7645 DAG.getNode(ISD::BUILD_VECTOR, DL,
7646 MVT::v16i8, PSHUFBMask)));
7649 // Otherwise emit a sequence of unpacks.
7651 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7652 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7653 : getZeroVector(InputVT, Subtarget, DAG, DL);
7654 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7655 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7659 } while (Scale > 1);
7660 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7663 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7665 /// This routine will try to do everything in its power to cleverly lower
7666 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7667 /// check for the profitability of this lowering, it tries to aggressively
7668 /// match this pattern. It will use all of the micro-architectural details it
7669 /// can to emit an efficient lowering. It handles both blends with all-zero
7670 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7671 /// masking out later).
7673 /// The reason we have dedicated lowering for zext-style shuffles is that they
7674 /// are both incredibly common and often quite performance sensitive.
7675 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7676 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7677 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7678 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7680 int Bits = VT.getSizeInBits();
7681 int NumElements = Mask.size();
7683 // Define a helper function to check a particular ext-scale and lower to it if
7685 auto Lower = [&](int Scale) -> SDValue {
7688 for (int i = 0; i < NumElements; ++i) {
7690 continue; // Valid anywhere but doesn't tell us anything.
7691 if (i % Scale != 0) {
7692 // Each of the extend elements needs to be zeroable.
7696 // We no lorger are in the anyext case.
7701 // Each of the base elements needs to be consecutive indices into the
7702 // same input vector.
7703 SDValue V = Mask[i] < NumElements ? V1 : V2;
7706 else if (InputV != V)
7707 return SDValue(); // Flip-flopping inputs.
7709 if (Mask[i] % NumElements != i / Scale)
7710 return SDValue(); // Non-consecutive strided elemenst.
7713 // If we fail to find an input, we have a zero-shuffle which should always
7714 // have already been handled.
7715 // FIXME: Maybe handle this here in case during blending we end up with one?
7719 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7720 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7723 // The widest scale possible for extending is to a 64-bit integer.
7724 assert(Bits % 64 == 0 &&
7725 "The number of bits in a vector must be divisible by 64 on x86!");
7726 int NumExtElements = Bits / 64;
7728 // Each iteration, try extending the elements half as much, but into twice as
7730 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7731 assert(NumElements % NumExtElements == 0 &&
7732 "The input vector size must be divisble by the extended size.");
7733 if (SDValue V = Lower(NumElements / NumExtElements))
7737 // No viable ext lowering found.
7741 /// \brief Try to get a scalar value for a specific element of a vector.
7743 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7744 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7745 SelectionDAG &DAG) {
7746 MVT VT = V.getSimpleValueType();
7747 MVT EltVT = VT.getVectorElementType();
7748 while (V.getOpcode() == ISD::BITCAST)
7749 V = V.getOperand(0);
7750 // If the bitcasts shift the element size, we can't extract an equivalent
7752 MVT NewVT = V.getSimpleValueType();
7753 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7756 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7757 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7758 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7763 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7765 /// This is particularly important because the set of instructions varies
7766 /// significantly based on whether the operand is a load or not.
7767 static bool isShuffleFoldableLoad(SDValue V) {
7768 while (V.getOpcode() == ISD::BITCAST)
7769 V = V.getOperand(0);
7771 return ISD::isNON_EXTLoad(V.getNode());
7774 /// \brief Try to lower insertion of a single element into a zero vector.
7776 /// This is a common pattern that we have especially efficient patterns to lower
7777 /// across all subtarget feature sets.
7778 static SDValue lowerVectorShuffleAsElementInsertion(
7779 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7780 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7781 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7783 MVT EltVT = VT.getVectorElementType();
7785 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7786 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7788 bool IsV1Zeroable = true;
7789 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7790 if (i != V2Index && !Zeroable[i]) {
7791 IsV1Zeroable = false;
7795 // Check for a single input from a SCALAR_TO_VECTOR node.
7796 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7797 // all the smarts here sunk into that routine. However, the current
7798 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7799 // vector shuffle lowering is dead.
7800 if (SDValue V2S = getScalarValueForVectorElement(
7801 V2, Mask[V2Index] - Mask.size(), DAG)) {
7802 // We need to zext the scalar if it is smaller than an i32.
7803 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7804 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7805 // Using zext to expand a narrow element won't work for non-zero
7810 // Zero-extend directly to i32.
7812 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7814 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7815 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7816 EltVT == MVT::i16) {
7817 // Either not inserting from the low element of the input or the input
7818 // element size is too small to use VZEXT_MOVL to clear the high bits.
7822 if (!IsV1Zeroable) {
7823 // If V1 can't be treated as a zero vector we have fewer options to lower
7824 // this. We can't support integer vectors or non-zero targets cheaply, and
7825 // the V1 elements can't be permuted in any way.
7826 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7827 if (!VT.isFloatingPoint() || V2Index != 0)
7829 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7830 V1Mask[V2Index] = -1;
7831 if (!isNoopShuffleMask(V1Mask))
7833 // This is essentially a special case blend operation, but if we have
7834 // general purpose blend operations, they are always faster. Bail and let
7835 // the rest of the lowering handle these as blends.
7836 if (Subtarget->hasSSE41())
7839 // Otherwise, use MOVSD or MOVSS.
7840 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7841 "Only two types of floating point element types to handle!");
7842 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7846 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7848 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7851 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7852 // the desired position. Otherwise it is more efficient to do a vector
7853 // shift left. We know that we can do a vector shift left because all
7854 // the inputs are zero.
7855 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7856 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7857 V2Shuffle[V2Index] = 0;
7858 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7860 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7862 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7864 V2Index * EltVT.getSizeInBits(),
7865 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7866 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7872 /// \brief Try to lower broadcast of a single element.
7874 /// For convenience, this code also bundles all of the subtarget feature set
7875 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7876 /// a convenient way to factor it out.
7877 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7879 const X86Subtarget *Subtarget,
7880 SelectionDAG &DAG) {
7881 if (!Subtarget->hasAVX())
7883 if (VT.isInteger() && !Subtarget->hasAVX2())
7886 // Check that the mask is a broadcast.
7887 int BroadcastIdx = -1;
7889 if (M >= 0 && BroadcastIdx == -1)
7891 else if (M >= 0 && M != BroadcastIdx)
7894 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7895 "a sorted mask where the broadcast "
7898 // Check if this is a broadcast of a scalar. We special case lowering for
7899 // scalars so that we can more effectively fold with loads.
7900 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7901 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7902 V = V.getOperand(BroadcastIdx);
7904 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
7906 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7908 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7909 // We can't broadcast from a vector register w/o AVX2, and we can only
7910 // broadcast from the zero-element of a vector register.
7914 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7917 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7919 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7920 /// support for floating point shuffles but not integer shuffles. These
7921 /// instructions will incur a domain crossing penalty on some chips though so
7922 /// it is better to avoid lowering through this for integer vectors where
7924 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7925 const X86Subtarget *Subtarget,
7926 SelectionDAG &DAG) {
7928 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7929 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7930 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7931 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7932 ArrayRef<int> Mask = SVOp->getMask();
7933 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7935 if (isSingleInputShuffleMask(Mask)) {
7936 // Straight shuffle of a single input vector. Simulate this by using the
7937 // single input as both of the "inputs" to this instruction..
7938 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7940 if (Subtarget->hasAVX()) {
7941 // If we have AVX, we can use VPERMILPS which will allow folding a load
7942 // into the shuffle.
7943 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7944 DAG.getConstant(SHUFPDMask, MVT::i8));
7947 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7948 DAG.getConstant(SHUFPDMask, MVT::i8));
7950 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7951 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7953 // Use dedicated unpack instructions for masks that match their pattern.
7954 if (isShuffleEquivalent(Mask, 0, 2))
7955 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7956 if (isShuffleEquivalent(Mask, 1, 3))
7957 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7959 // If we have a single input, insert that into V1 if we can do so cheaply.
7960 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7961 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7962 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7964 // Try inverting the insertion since for v2 masks it is easy to do and we
7965 // can't reliably sort the mask one way or the other.
7966 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7967 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7968 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7969 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
7973 // Try to use one of the special instruction patterns to handle two common
7974 // blend patterns if a zero-blend above didn't work.
7975 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
7976 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7977 // We can either use a special instruction to load over the low double or
7978 // to move just the low double.
7980 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7982 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7984 if (Subtarget->hasSSE41())
7985 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7989 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7990 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7991 DAG.getConstant(SHUFPDMask, MVT::i8));
7994 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7996 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7997 /// the integer unit to minimize domain crossing penalties. However, for blends
7998 /// it falls back to the floating point shuffle operation with appropriate bit
8000 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8001 const X86Subtarget *Subtarget,
8002 SelectionDAG &DAG) {
8004 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8005 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8006 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8007 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8008 ArrayRef<int> Mask = SVOp->getMask();
8009 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8011 if (isSingleInputShuffleMask(Mask)) {
8012 // Check for being able to broadcast a single element.
8013 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8014 Mask, Subtarget, DAG))
8017 // Straight shuffle of a single input vector. For everything from SSE2
8018 // onward this has a single fast instruction with no scary immediates.
8019 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8020 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8021 int WidenedMask[4] = {
8022 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8023 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8025 ISD::BITCAST, DL, MVT::v2i64,
8026 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8027 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8030 // If we have a single input from V2 insert that into V1 if we can do so
8032 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8033 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8034 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8036 // Try inverting the insertion since for v2 masks it is easy to do and we
8037 // can't reliably sort the mask one way or the other.
8038 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8039 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8040 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8041 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8045 // Use dedicated unpack instructions for masks that match their pattern.
8046 if (isShuffleEquivalent(Mask, 0, 2))
8047 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8048 if (isShuffleEquivalent(Mask, 1, 3))
8049 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8051 if (Subtarget->hasSSE41())
8052 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8056 // Try to use rotation instructions if available.
8057 if (Subtarget->hasSSSE3())
8058 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8059 DL, MVT::v2i64, V1, V2, Mask, DAG))
8062 // We implement this with SHUFPD which is pretty lame because it will likely
8063 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8064 // However, all the alternatives are still more cycles and newer chips don't
8065 // have this problem. It would be really nice if x86 had better shuffles here.
8066 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8067 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8068 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8069 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8072 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8074 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8075 /// It makes no assumptions about whether this is the *best* lowering, it simply
8077 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8078 ArrayRef<int> Mask, SDValue V1,
8079 SDValue V2, SelectionDAG &DAG) {
8080 SDValue LowV = V1, HighV = V2;
8081 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8084 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8086 if (NumV2Elements == 1) {
8088 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8091 // Compute the index adjacent to V2Index and in the same half by toggling
8093 int V2AdjIndex = V2Index ^ 1;
8095 if (Mask[V2AdjIndex] == -1) {
8096 // Handles all the cases where we have a single V2 element and an undef.
8097 // This will only ever happen in the high lanes because we commute the
8098 // vector otherwise.
8100 std::swap(LowV, HighV);
8101 NewMask[V2Index] -= 4;
8103 // Handle the case where the V2 element ends up adjacent to a V1 element.
8104 // To make this work, blend them together as the first step.
8105 int V1Index = V2AdjIndex;
8106 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8107 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8108 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8110 // Now proceed to reconstruct the final blend as we have the necessary
8111 // high or low half formed.
8118 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8119 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8121 } else if (NumV2Elements == 2) {
8122 if (Mask[0] < 4 && Mask[1] < 4) {
8123 // Handle the easy case where we have V1 in the low lanes and V2 in the
8127 } else if (Mask[2] < 4 && Mask[3] < 4) {
8128 // We also handle the reversed case because this utility may get called
8129 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8130 // arrange things in the right direction.
8136 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8137 // trying to place elements directly, just blend them and set up the final
8138 // shuffle to place them.
8140 // The first two blend mask elements are for V1, the second two are for
8142 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8143 Mask[2] < 4 ? Mask[2] : Mask[3],
8144 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8145 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8146 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8147 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8149 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8152 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8153 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8154 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8155 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8158 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8159 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8162 /// \brief Lower 4-lane 32-bit floating point shuffles.
8164 /// Uses instructions exclusively from the floating point unit to minimize
8165 /// domain crossing penalties, as these are sufficient to implement all v4f32
8167 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8168 const X86Subtarget *Subtarget,
8169 SelectionDAG &DAG) {
8171 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8172 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8173 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8174 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8175 ArrayRef<int> Mask = SVOp->getMask();
8176 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8179 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8181 if (NumV2Elements == 0) {
8182 // Check for being able to broadcast a single element.
8183 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8184 Mask, Subtarget, DAG))
8187 if (Subtarget->hasAVX()) {
8188 // If we have AVX, we can use VPERMILPS which will allow folding a load
8189 // into the shuffle.
8190 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8191 getV4X86ShuffleImm8ForMask(Mask, DAG));
8194 // Otherwise, use a straight shuffle of a single input vector. We pass the
8195 // input vector to both operands to simulate this with a SHUFPS.
8196 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8197 getV4X86ShuffleImm8ForMask(Mask, DAG));
8200 // Use dedicated unpack instructions for masks that match their pattern.
8201 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8202 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8203 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8204 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8206 // There are special ways we can lower some single-element blends. However, we
8207 // have custom ways we can lower more complex single-element blends below that
8208 // we defer to if both this and BLENDPS fail to match, so restrict this to
8209 // when the V2 input is targeting element 0 of the mask -- that is the fast
8211 if (NumV2Elements == 1 && Mask[0] >= 4)
8212 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8213 Mask, Subtarget, DAG))
8216 if (Subtarget->hasSSE41())
8217 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8221 // Check for whether we can use INSERTPS to perform the blend. We only use
8222 // INSERTPS when the V1 elements are already in the correct locations
8223 // because otherwise we can just always use two SHUFPS instructions which
8224 // are much smaller to encode than a SHUFPS and an INSERTPS.
8225 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8227 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8230 // When using INSERTPS we can zero any lane of the destination. Collect
8231 // the zero inputs into a mask and drop them from the lanes of V1 which
8232 // actually need to be present as inputs to the INSERTPS.
8233 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8235 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8236 bool InsertNeedsShuffle = false;
8238 for (int i = 0; i < 4; ++i)
8242 } else if (Mask[i] != i) {
8243 InsertNeedsShuffle = true;
8248 // We don't want to use INSERTPS or other insertion techniques if it will
8249 // require shuffling anyways.
8250 if (!InsertNeedsShuffle) {
8251 // If all of V1 is zeroable, replace it with undef.
8252 if ((ZMask | 1 << V2Index) == 0xF)
8253 V1 = DAG.getUNDEF(MVT::v4f32);
8255 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8256 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8258 // Insert the V2 element into the desired position.
8259 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8260 DAG.getConstant(InsertPSMask, MVT::i8));
8264 // Otherwise fall back to a SHUFPS lowering strategy.
8265 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8268 /// \brief Lower 4-lane i32 vector shuffles.
8270 /// We try to handle these with integer-domain shuffles where we can, but for
8271 /// blends we use the floating point domain blend instructions.
8272 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8273 const X86Subtarget *Subtarget,
8274 SelectionDAG &DAG) {
8276 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8277 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8278 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8279 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8280 ArrayRef<int> Mask = SVOp->getMask();
8281 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8283 // Whenever we can lower this as a zext, that instruction is strictly faster
8284 // than any alternative. It also allows us to fold memory operands into the
8285 // shuffle in many cases.
8286 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8287 Mask, Subtarget, DAG))
8291 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8293 if (NumV2Elements == 0) {
8294 // Check for being able to broadcast a single element.
8295 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8296 Mask, Subtarget, DAG))
8299 // Straight shuffle of a single input vector. For everything from SSE2
8300 // onward this has a single fast instruction with no scary immediates.
8301 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8302 // but we aren't actually going to use the UNPCK instruction because doing
8303 // so prevents folding a load into this instruction or making a copy.
8304 const int UnpackLoMask[] = {0, 0, 1, 1};
8305 const int UnpackHiMask[] = {2, 2, 3, 3};
8306 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8307 Mask = UnpackLoMask;
8308 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8309 Mask = UnpackHiMask;
8311 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8312 getV4X86ShuffleImm8ForMask(Mask, DAG));
8315 // There are special ways we can lower some single-element blends.
8316 if (NumV2Elements == 1)
8317 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8318 Mask, Subtarget, DAG))
8321 // Use dedicated unpack instructions for masks that match their pattern.
8322 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8323 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8324 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8325 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8327 if (Subtarget->hasSSE41())
8328 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8332 // Try to use rotation instructions if available.
8333 if (Subtarget->hasSSSE3())
8334 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8335 DL, MVT::v4i32, V1, V2, Mask, DAG))
8338 // We implement this with SHUFPS because it can blend from two vectors.
8339 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8340 // up the inputs, bypassing domain shift penalties that we would encur if we
8341 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8343 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8344 DAG.getVectorShuffle(
8346 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8347 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8350 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8351 /// shuffle lowering, and the most complex part.
8353 /// The lowering strategy is to try to form pairs of input lanes which are
8354 /// targeted at the same half of the final vector, and then use a dword shuffle
8355 /// to place them onto the right half, and finally unpack the paired lanes into
8356 /// their final position.
8358 /// The exact breakdown of how to form these dword pairs and align them on the
8359 /// correct sides is really tricky. See the comments within the function for
8360 /// more of the details.
8361 static SDValue lowerV8I16SingleInputVectorShuffle(
8362 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8363 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8364 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8365 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8366 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8368 SmallVector<int, 4> LoInputs;
8369 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8370 [](int M) { return M >= 0; });
8371 std::sort(LoInputs.begin(), LoInputs.end());
8372 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8373 SmallVector<int, 4> HiInputs;
8374 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8375 [](int M) { return M >= 0; });
8376 std::sort(HiInputs.begin(), HiInputs.end());
8377 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8379 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8380 int NumHToL = LoInputs.size() - NumLToL;
8382 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8383 int NumHToH = HiInputs.size() - NumLToH;
8384 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8385 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8386 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8387 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8389 // Check for being able to broadcast a single element.
8390 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8391 Mask, Subtarget, DAG))
8394 // Use dedicated unpack instructions for masks that match their pattern.
8395 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8396 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8397 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8398 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8400 // Try to use rotation instructions if available.
8401 if (Subtarget->hasSSSE3())
8402 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8403 DL, MVT::v8i16, V, V, Mask, DAG))
8406 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8407 // such inputs we can swap two of the dwords across the half mark and end up
8408 // with <=2 inputs to each half in each half. Once there, we can fall through
8409 // to the generic code below. For example:
8411 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8412 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8414 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8415 // and an existing 2-into-2 on the other half. In this case we may have to
8416 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8417 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8418 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8419 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8420 // half than the one we target for fixing) will be fixed when we re-enter this
8421 // path. We will also combine away any sequence of PSHUFD instructions that
8422 // result into a single instruction. Here is an example of the tricky case:
8424 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8425 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8427 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8429 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8430 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8432 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8433 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8435 // The result is fine to be handled by the generic logic.
8436 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8437 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8438 int AOffset, int BOffset) {
8439 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8440 "Must call this with A having 3 or 1 inputs from the A half.");
8441 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8442 "Must call this with B having 1 or 3 inputs from the B half.");
8443 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8444 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8446 // Compute the index of dword with only one word among the three inputs in
8447 // a half by taking the sum of the half with three inputs and subtracting
8448 // the sum of the actual three inputs. The difference is the remaining
8451 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8452 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8453 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8454 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8455 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8456 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8457 int TripleNonInputIdx =
8458 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8459 TripleDWord = TripleNonInputIdx / 2;
8461 // We use xor with one to compute the adjacent DWord to whichever one the
8463 OneInputDWord = (OneInput / 2) ^ 1;
8465 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8466 // and BToA inputs. If there is also such a problem with the BToB and AToB
8467 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8468 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8469 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8470 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8471 // Compute how many inputs will be flipped by swapping these DWords. We
8473 // to balance this to ensure we don't form a 3-1 shuffle in the other
8475 int NumFlippedAToBInputs =
8476 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8477 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8478 int NumFlippedBToBInputs =
8479 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8480 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8481 if ((NumFlippedAToBInputs == 1 &&
8482 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8483 (NumFlippedBToBInputs == 1 &&
8484 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8485 // We choose whether to fix the A half or B half based on whether that
8486 // half has zero flipped inputs. At zero, we may not be able to fix it
8487 // with that half. We also bias towards fixing the B half because that
8488 // will more commonly be the high half, and we have to bias one way.
8489 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8490 ArrayRef<int> Inputs) {
8491 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8492 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8493 PinnedIdx ^ 1) != Inputs.end();
8494 // Determine whether the free index is in the flipped dword or the
8495 // unflipped dword based on where the pinned index is. We use this bit
8496 // in an xor to conditionally select the adjacent dword.
8497 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8498 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8499 FixFreeIdx) != Inputs.end();
8500 if (IsFixIdxInput == IsFixFreeIdxInput)
8502 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8503 FixFreeIdx) != Inputs.end();
8504 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8505 "We need to be changing the number of flipped inputs!");
8506 int PSHUFHalfMask[] = {0, 1, 2, 3};
8507 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8508 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8510 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8513 if (M != -1 && M == FixIdx)
8515 else if (M != -1 && M == FixFreeIdx)
8518 if (NumFlippedBToBInputs != 0) {
8520 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8521 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8523 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8525 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8526 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8531 int PSHUFDMask[] = {0, 1, 2, 3};
8532 PSHUFDMask[ADWord] = BDWord;
8533 PSHUFDMask[BDWord] = ADWord;
8534 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8535 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8536 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8537 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8539 // Adjust the mask to match the new locations of A and B.
8541 if (M != -1 && M/2 == ADWord)
8542 M = 2 * BDWord + M % 2;
8543 else if (M != -1 && M/2 == BDWord)
8544 M = 2 * ADWord + M % 2;
8546 // Recurse back into this routine to re-compute state now that this isn't
8547 // a 3 and 1 problem.
8548 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8551 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8552 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8553 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8554 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8556 // At this point there are at most two inputs to the low and high halves from
8557 // each half. That means the inputs can always be grouped into dwords and
8558 // those dwords can then be moved to the correct half with a dword shuffle.
8559 // We use at most one low and one high word shuffle to collect these paired
8560 // inputs into dwords, and finally a dword shuffle to place them.
8561 int PSHUFLMask[4] = {-1, -1, -1, -1};
8562 int PSHUFHMask[4] = {-1, -1, -1, -1};
8563 int PSHUFDMask[4] = {-1, -1, -1, -1};
8565 // First fix the masks for all the inputs that are staying in their
8566 // original halves. This will then dictate the targets of the cross-half
8568 auto fixInPlaceInputs =
8569 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8570 MutableArrayRef<int> SourceHalfMask,
8571 MutableArrayRef<int> HalfMask, int HalfOffset) {
8572 if (InPlaceInputs.empty())
8574 if (InPlaceInputs.size() == 1) {
8575 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8576 InPlaceInputs[0] - HalfOffset;
8577 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8580 if (IncomingInputs.empty()) {
8581 // Just fix all of the in place inputs.
8582 for (int Input : InPlaceInputs) {
8583 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8584 PSHUFDMask[Input / 2] = Input / 2;
8589 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8590 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8591 InPlaceInputs[0] - HalfOffset;
8592 // Put the second input next to the first so that they are packed into
8593 // a dword. We find the adjacent index by toggling the low bit.
8594 int AdjIndex = InPlaceInputs[0] ^ 1;
8595 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8596 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8597 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8599 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8600 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8602 // Now gather the cross-half inputs and place them into a free dword of
8603 // their target half.
8604 // FIXME: This operation could almost certainly be simplified dramatically to
8605 // look more like the 3-1 fixing operation.
8606 auto moveInputsToRightHalf = [&PSHUFDMask](
8607 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8608 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8609 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8611 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8612 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8614 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8616 int LowWord = Word & ~1;
8617 int HighWord = Word | 1;
8618 return isWordClobbered(SourceHalfMask, LowWord) ||
8619 isWordClobbered(SourceHalfMask, HighWord);
8622 if (IncomingInputs.empty())
8625 if (ExistingInputs.empty()) {
8626 // Map any dwords with inputs from them into the right half.
8627 for (int Input : IncomingInputs) {
8628 // If the source half mask maps over the inputs, turn those into
8629 // swaps and use the swapped lane.
8630 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8631 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8632 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8633 Input - SourceOffset;
8634 // We have to swap the uses in our half mask in one sweep.
8635 for (int &M : HalfMask)
8636 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8638 else if (M == Input)
8639 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8641 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8642 Input - SourceOffset &&
8643 "Previous placement doesn't match!");
8645 // Note that this correctly re-maps both when we do a swap and when
8646 // we observe the other side of the swap above. We rely on that to
8647 // avoid swapping the members of the input list directly.
8648 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8651 // Map the input's dword into the correct half.
8652 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8653 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8655 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8657 "Previous placement doesn't match!");
8660 // And just directly shift any other-half mask elements to be same-half
8661 // as we will have mirrored the dword containing the element into the
8662 // same position within that half.
8663 for (int &M : HalfMask)
8664 if (M >= SourceOffset && M < SourceOffset + 4) {
8665 M = M - SourceOffset + DestOffset;
8666 assert(M >= 0 && "This should never wrap below zero!");
8671 // Ensure we have the input in a viable dword of its current half. This
8672 // is particularly tricky because the original position may be clobbered
8673 // by inputs being moved and *staying* in that half.
8674 if (IncomingInputs.size() == 1) {
8675 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8676 int InputFixed = std::find(std::begin(SourceHalfMask),
8677 std::end(SourceHalfMask), -1) -
8678 std::begin(SourceHalfMask) + SourceOffset;
8679 SourceHalfMask[InputFixed - SourceOffset] =
8680 IncomingInputs[0] - SourceOffset;
8681 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8683 IncomingInputs[0] = InputFixed;
8685 } else if (IncomingInputs.size() == 2) {
8686 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8687 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8688 // We have two non-adjacent or clobbered inputs we need to extract from
8689 // the source half. To do this, we need to map them into some adjacent
8690 // dword slot in the source mask.
8691 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8692 IncomingInputs[1] - SourceOffset};
8694 // If there is a free slot in the source half mask adjacent to one of
8695 // the inputs, place the other input in it. We use (Index XOR 1) to
8696 // compute an adjacent index.
8697 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8698 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8699 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8700 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8701 InputsFixed[1] = InputsFixed[0] ^ 1;
8702 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8703 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8704 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8705 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8706 InputsFixed[0] = InputsFixed[1] ^ 1;
8707 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8708 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8709 // The two inputs are in the same DWord but it is clobbered and the
8710 // adjacent DWord isn't used at all. Move both inputs to the free
8712 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8713 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8714 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8715 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8717 // The only way we hit this point is if there is no clobbering
8718 // (because there are no off-half inputs to this half) and there is no
8719 // free slot adjacent to one of the inputs. In this case, we have to
8720 // swap an input with a non-input.
8721 for (int i = 0; i < 4; ++i)
8722 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8723 "We can't handle any clobbers here!");
8724 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8725 "Cannot have adjacent inputs here!");
8727 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8728 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8730 // We also have to update the final source mask in this case because
8731 // it may need to undo the above swap.
8732 for (int &M : FinalSourceHalfMask)
8733 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8734 M = InputsFixed[1] + SourceOffset;
8735 else if (M == InputsFixed[1] + SourceOffset)
8736 M = (InputsFixed[0] ^ 1) + SourceOffset;
8738 InputsFixed[1] = InputsFixed[0] ^ 1;
8741 // Point everything at the fixed inputs.
8742 for (int &M : HalfMask)
8743 if (M == IncomingInputs[0])
8744 M = InputsFixed[0] + SourceOffset;
8745 else if (M == IncomingInputs[1])
8746 M = InputsFixed[1] + SourceOffset;
8748 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8749 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8752 llvm_unreachable("Unhandled input size!");
8755 // Now hoist the DWord down to the right half.
8756 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8757 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8758 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8759 for (int &M : HalfMask)
8760 for (int Input : IncomingInputs)
8762 M = FreeDWord * 2 + Input % 2;
8764 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8765 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8766 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8767 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8769 // Now enact all the shuffles we've computed to move the inputs into their
8771 if (!isNoopShuffleMask(PSHUFLMask))
8772 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8773 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8774 if (!isNoopShuffleMask(PSHUFHMask))
8775 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8776 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8777 if (!isNoopShuffleMask(PSHUFDMask))
8778 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8779 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8780 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8781 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8783 // At this point, each half should contain all its inputs, and we can then
8784 // just shuffle them into their final position.
8785 assert(std::count_if(LoMask.begin(), LoMask.end(),
8786 [](int M) { return M >= 4; }) == 0 &&
8787 "Failed to lift all the high half inputs to the low mask!");
8788 assert(std::count_if(HiMask.begin(), HiMask.end(),
8789 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8790 "Failed to lift all the low half inputs to the high mask!");
8792 // Do a half shuffle for the low mask.
8793 if (!isNoopShuffleMask(LoMask))
8794 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8795 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8797 // Do a half shuffle with the high mask after shifting its values down.
8798 for (int &M : HiMask)
8801 if (!isNoopShuffleMask(HiMask))
8802 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8803 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8808 /// \brief Detect whether the mask pattern should be lowered through
8811 /// This essentially tests whether viewing the mask as an interleaving of two
8812 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8813 /// lowering it through interleaving is a significantly better strategy.
8814 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8815 int NumEvenInputs[2] = {0, 0};
8816 int NumOddInputs[2] = {0, 0};
8817 int NumLoInputs[2] = {0, 0};
8818 int NumHiInputs[2] = {0, 0};
8819 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8823 int InputIdx = Mask[i] >= Size;
8826 ++NumLoInputs[InputIdx];
8828 ++NumHiInputs[InputIdx];
8831 ++NumEvenInputs[InputIdx];
8833 ++NumOddInputs[InputIdx];
8836 // The minimum number of cross-input results for both the interleaved and
8837 // split cases. If interleaving results in fewer cross-input results, return
8839 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8840 NumEvenInputs[0] + NumOddInputs[1]);
8841 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8842 NumLoInputs[0] + NumHiInputs[1]);
8843 return InterleavedCrosses < SplitCrosses;
8846 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8848 /// This strategy only works when the inputs from each vector fit into a single
8849 /// half of that vector, and generally there are not so many inputs as to leave
8850 /// the in-place shuffles required highly constrained (and thus expensive). It
8851 /// shifts all the inputs into a single side of both input vectors and then
8852 /// uses an unpack to interleave these inputs in a single vector. At that
8853 /// point, we will fall back on the generic single input shuffle lowering.
8854 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8856 MutableArrayRef<int> Mask,
8857 const X86Subtarget *Subtarget,
8858 SelectionDAG &DAG) {
8859 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8860 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8861 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8862 for (int i = 0; i < 8; ++i)
8863 if (Mask[i] >= 0 && Mask[i] < 4)
8864 LoV1Inputs.push_back(i);
8865 else if (Mask[i] >= 4 && Mask[i] < 8)
8866 HiV1Inputs.push_back(i);
8867 else if (Mask[i] >= 8 && Mask[i] < 12)
8868 LoV2Inputs.push_back(i);
8869 else if (Mask[i] >= 12)
8870 HiV2Inputs.push_back(i);
8872 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8873 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8876 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8877 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8878 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8880 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8881 HiV1Inputs.size() + HiV2Inputs.size();
8883 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8884 ArrayRef<int> HiInputs, bool MoveToLo,
8886 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8887 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8888 if (BadInputs.empty())
8891 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8892 int MoveOffset = MoveToLo ? 0 : 4;
8894 if (GoodInputs.empty()) {
8895 for (int BadInput : BadInputs) {
8896 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8897 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8900 if (GoodInputs.size() == 2) {
8901 // If the low inputs are spread across two dwords, pack them into
8903 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8904 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8905 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8906 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8908 // Otherwise pin the good inputs.
8909 for (int GoodInput : GoodInputs)
8910 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8913 if (BadInputs.size() == 2) {
8914 // If we have two bad inputs then there may be either one or two good
8915 // inputs fixed in place. Find a fixed input, and then find the *other*
8916 // two adjacent indices by using modular arithmetic.
8918 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8919 [](int M) { return M >= 0; }) -
8920 std::begin(MoveMask);
8922 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8923 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8924 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8925 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8926 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8927 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8928 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8930 assert(BadInputs.size() == 1 && "All sizes handled");
8931 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8932 std::end(MoveMask), -1) -
8933 std::begin(MoveMask);
8934 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8935 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8939 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8942 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8944 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8947 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8948 // cross-half traffic in the final shuffle.
8950 // Munge the mask to be a single-input mask after the unpack merges the
8954 M = 2 * (M % 4) + (M / 8);
8956 return DAG.getVectorShuffle(
8957 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8958 DL, MVT::v8i16, V1, V2),
8959 DAG.getUNDEF(MVT::v8i16), Mask);
8962 /// \brief Generic lowering of 8-lane i16 shuffles.
8964 /// This handles both single-input shuffles and combined shuffle/blends with
8965 /// two inputs. The single input shuffles are immediately delegated to
8966 /// a dedicated lowering routine.
8968 /// The blends are lowered in one of three fundamental ways. If there are few
8969 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8970 /// of the input is significantly cheaper when lowered as an interleaving of
8971 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8972 /// halves of the inputs separately (making them have relatively few inputs)
8973 /// and then concatenate them.
8974 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8975 const X86Subtarget *Subtarget,
8976 SelectionDAG &DAG) {
8978 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8979 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8980 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8982 ArrayRef<int> OrigMask = SVOp->getMask();
8983 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8984 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8985 MutableArrayRef<int> Mask(MaskStorage);
8987 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8989 // Whenever we can lower this as a zext, that instruction is strictly faster
8990 // than any alternative.
8991 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8992 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8995 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8996 auto isV2 = [](int M) { return M >= 8; };
8998 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8999 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9001 if (NumV2Inputs == 0)
9002 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9004 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9005 "to be V1-input shuffles.");
9007 // There are special ways we can lower some single-element blends.
9008 if (NumV2Inputs == 1)
9009 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9010 Mask, Subtarget, DAG))
9013 if (Subtarget->hasSSE41())
9014 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9018 // Try to use rotation instructions if available.
9019 if (Subtarget->hasSSSE3())
9020 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
9023 if (NumV1Inputs + NumV2Inputs <= 4)
9024 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9026 // Check whether an interleaving lowering is likely to be more efficient.
9027 // This isn't perfect but it is a strong heuristic that tends to work well on
9028 // the kinds of shuffles that show up in practice.
9030 // FIXME: Handle 1x, 2x, and 4x interleaving.
9031 if (shouldLowerAsInterleaving(Mask)) {
9032 // FIXME: Figure out whether we should pack these into the low or high
9035 int EMask[8], OMask[8];
9036 for (int i = 0; i < 4; ++i) {
9037 EMask[i] = Mask[2*i];
9038 OMask[i] = Mask[2*i + 1];
9043 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9044 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9046 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9049 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9050 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9052 for (int i = 0; i < 4; ++i) {
9053 LoBlendMask[i] = Mask[i];
9054 HiBlendMask[i] = Mask[i + 4];
9057 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9058 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9059 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9060 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9062 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9063 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9066 /// \brief Check whether a compaction lowering can be done by dropping even
9067 /// elements and compute how many times even elements must be dropped.
9069 /// This handles shuffles which take every Nth element where N is a power of
9070 /// two. Example shuffle masks:
9072 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9073 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9074 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9075 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9076 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9077 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9079 /// Any of these lanes can of course be undef.
9081 /// This routine only supports N <= 3.
9082 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9085 /// \returns N above, or the number of times even elements must be dropped if
9086 /// there is such a number. Otherwise returns zero.
9087 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9088 // Figure out whether we're looping over two inputs or just one.
9089 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9091 // The modulus for the shuffle vector entries is based on whether this is
9092 // a single input or not.
9093 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9094 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9095 "We should only be called with masks with a power-of-2 size!");
9097 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9099 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9100 // and 2^3 simultaneously. This is because we may have ambiguity with
9101 // partially undef inputs.
9102 bool ViableForN[3] = {true, true, true};
9104 for (int i = 0, e = Mask.size(); i < e; ++i) {
9105 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9110 bool IsAnyViable = false;
9111 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9112 if (ViableForN[j]) {
9115 // The shuffle mask must be equal to (i * 2^N) % M.
9116 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9119 ViableForN[j] = false;
9121 // Early exit if we exhaust the possible powers of two.
9126 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9130 // Return 0 as there is no viable power of two.
9134 /// \brief Generic lowering of v16i8 shuffles.
9136 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9137 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9138 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9139 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9141 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9142 const X86Subtarget *Subtarget,
9143 SelectionDAG &DAG) {
9145 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9146 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9147 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9148 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9149 ArrayRef<int> OrigMask = SVOp->getMask();
9150 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9152 // Try to use rotation instructions if available.
9153 if (Subtarget->hasSSSE3())
9154 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
9158 // Try to use a zext lowering.
9159 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9160 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9163 int MaskStorage[16] = {
9164 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9165 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9166 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9167 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9168 MutableArrayRef<int> Mask(MaskStorage);
9169 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9170 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9173 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9175 // For single-input shuffles, there are some nicer lowering tricks we can use.
9176 if (NumV2Elements == 0) {
9177 // Check for being able to broadcast a single element.
9178 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9179 Mask, Subtarget, DAG))
9182 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9183 // Notably, this handles splat and partial-splat shuffles more efficiently.
9184 // However, it only makes sense if the pre-duplication shuffle simplifies
9185 // things significantly. Currently, this means we need to be able to
9186 // express the pre-duplication shuffle as an i16 shuffle.
9188 // FIXME: We should check for other patterns which can be widened into an
9189 // i16 shuffle as well.
9190 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9191 for (int i = 0; i < 16; i += 2)
9192 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9197 auto tryToWidenViaDuplication = [&]() -> SDValue {
9198 if (!canWidenViaDuplication(Mask))
9200 SmallVector<int, 4> LoInputs;
9201 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9202 [](int M) { return M >= 0 && M < 8; });
9203 std::sort(LoInputs.begin(), LoInputs.end());
9204 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9206 SmallVector<int, 4> HiInputs;
9207 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9208 [](int M) { return M >= 8; });
9209 std::sort(HiInputs.begin(), HiInputs.end());
9210 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9213 bool TargetLo = LoInputs.size() >= HiInputs.size();
9214 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9215 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9217 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9218 SmallDenseMap<int, int, 8> LaneMap;
9219 for (int I : InPlaceInputs) {
9220 PreDupI16Shuffle[I/2] = I/2;
9223 int j = TargetLo ? 0 : 4, je = j + 4;
9224 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9225 // Check if j is already a shuffle of this input. This happens when
9226 // there are two adjacent bytes after we move the low one.
9227 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9228 // If we haven't yet mapped the input, search for a slot into which
9230 while (j < je && PreDupI16Shuffle[j] != -1)
9234 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9237 // Map this input with the i16 shuffle.
9238 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9241 // Update the lane map based on the mapping we ended up with.
9242 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9245 ISD::BITCAST, DL, MVT::v16i8,
9246 DAG.getVectorShuffle(MVT::v8i16, DL,
9247 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9248 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9250 // Unpack the bytes to form the i16s that will be shuffled into place.
9251 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9252 MVT::v16i8, V1, V1);
9254 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9255 for (int i = 0; i < 16; ++i)
9256 if (Mask[i] != -1) {
9257 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9258 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9259 if (PostDupI16Shuffle[i / 2] == -1)
9260 PostDupI16Shuffle[i / 2] = MappedMask;
9262 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9263 "Conflicting entrties in the original shuffle!");
9266 ISD::BITCAST, DL, MVT::v16i8,
9267 DAG.getVectorShuffle(MVT::v8i16, DL,
9268 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9269 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9271 if (SDValue V = tryToWidenViaDuplication())
9275 // Check whether an interleaving lowering is likely to be more efficient.
9276 // This isn't perfect but it is a strong heuristic that tends to work well on
9277 // the kinds of shuffles that show up in practice.
9279 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9280 if (shouldLowerAsInterleaving(Mask)) {
9281 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9282 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9284 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9285 return (M >= 8 && M < 16) || M >= 24;
9287 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9288 -1, -1, -1, -1, -1, -1, -1, -1};
9289 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9290 -1, -1, -1, -1, -1, -1, -1, -1};
9291 bool UnpackLo = NumLoHalf >= NumHiHalf;
9292 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9293 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9294 for (int i = 0; i < 8; ++i) {
9295 TargetEMask[i] = Mask[2 * i];
9296 TargetOMask[i] = Mask[2 * i + 1];
9299 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9300 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9302 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9303 MVT::v16i8, Evens, Odds);
9306 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9307 // with PSHUFB. It is important to do this before we attempt to generate any
9308 // blends but after all of the single-input lowerings. If the single input
9309 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9310 // want to preserve that and we can DAG combine any longer sequences into
9311 // a PSHUFB in the end. But once we start blending from multiple inputs,
9312 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9313 // and there are *very* few patterns that would actually be faster than the
9314 // PSHUFB approach because of its ability to zero lanes.
9316 // FIXME: The only exceptions to the above are blends which are exact
9317 // interleavings with direct instructions supporting them. We currently don't
9318 // handle those well here.
9319 if (Subtarget->hasSSSE3()) {
9322 for (int i = 0; i < 16; ++i)
9323 if (Mask[i] == -1) {
9324 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9326 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9328 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9330 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9331 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9332 if (isSingleInputShuffleMask(Mask))
9333 return V1; // Single inputs are easy.
9335 // Otherwise, blend the two.
9336 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9337 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9338 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9341 // There are special ways we can lower some single-element blends.
9342 if (NumV2Elements == 1)
9343 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9344 Mask, Subtarget, DAG))
9347 // Check whether a compaction lowering can be done. This handles shuffles
9348 // which take every Nth element for some even N. See the helper function for
9351 // We special case these as they can be particularly efficiently handled with
9352 // the PACKUSB instruction on x86 and they show up in common patterns of
9353 // rearranging bytes to truncate wide elements.
9354 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9355 // NumEvenDrops is the power of two stride of the elements. Another way of
9356 // thinking about it is that we need to drop the even elements this many
9357 // times to get the original input.
9358 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9360 // First we need to zero all the dropped bytes.
9361 assert(NumEvenDrops <= 3 &&
9362 "No support for dropping even elements more than 3 times.");
9363 // We use the mask type to pick which bytes are preserved based on how many
9364 // elements are dropped.
9365 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9366 SDValue ByteClearMask =
9367 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9368 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9369 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9371 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9373 // Now pack things back together.
9374 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9375 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9376 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9377 for (int i = 1; i < NumEvenDrops; ++i) {
9378 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9379 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9385 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9386 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9387 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9388 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9390 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9391 MutableArrayRef<int> V1HalfBlendMask,
9392 MutableArrayRef<int> V2HalfBlendMask) {
9393 for (int i = 0; i < 8; ++i)
9394 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9395 V1HalfBlendMask[i] = HalfMask[i];
9397 } else if (HalfMask[i] >= 16) {
9398 V2HalfBlendMask[i] = HalfMask[i] - 16;
9399 HalfMask[i] = i + 8;
9402 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9403 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9405 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9407 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9408 MutableArrayRef<int> HiBlendMask) {
9410 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9411 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9413 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9414 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9415 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9416 [](int M) { return M >= 0 && M % 2 == 1; })) {
9417 // Use a mask to drop the high bytes.
9418 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9419 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9420 DAG.getConstant(0x00FF, MVT::v8i16));
9422 // This will be a single vector shuffle instead of a blend so nuke V2.
9423 V2 = DAG.getUNDEF(MVT::v8i16);
9425 // Squash the masks to point directly into V1.
9426 for (int &M : LoBlendMask)
9429 for (int &M : HiBlendMask)
9433 // Otherwise just unpack the low half of V into V1 and the high half into
9434 // V2 so that we can blend them as i16s.
9435 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9436 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9437 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9438 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9441 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9442 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9443 return std::make_pair(BlendedLo, BlendedHi);
9445 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9446 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9447 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9449 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9450 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9452 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9455 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9457 /// This routine breaks down the specific type of 128-bit shuffle and
9458 /// dispatches to the lowering routines accordingly.
9459 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9460 MVT VT, const X86Subtarget *Subtarget,
9461 SelectionDAG &DAG) {
9462 switch (VT.SimpleTy) {
9464 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9466 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9468 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9470 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9472 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9474 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9477 llvm_unreachable("Unimplemented!");
9481 /// \brief Helper function to test whether a shuffle mask could be
9482 /// simplified by widening the elements being shuffled.
9484 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9485 /// leaves it in an unspecified state.
9487 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9488 /// shuffle masks. The latter have the special property of a '-2' representing
9489 /// a zero-ed lane of a vector.
9490 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9491 SmallVectorImpl<int> &WidenedMask) {
9492 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9493 // If both elements are undef, its trivial.
9494 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9495 WidenedMask.push_back(SM_SentinelUndef);
9499 // Check for an undef mask and a mask value properly aligned to fit with
9500 // a pair of values. If we find such a case, use the non-undef mask's value.
9501 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9502 WidenedMask.push_back(Mask[i + 1] / 2);
9505 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9506 WidenedMask.push_back(Mask[i] / 2);
9510 // When zeroing, we need to spread the zeroing across both lanes to widen.
9511 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9512 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9513 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9514 WidenedMask.push_back(SM_SentinelZero);
9520 // Finally check if the two mask values are adjacent and aligned with
9522 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9523 WidenedMask.push_back(Mask[i] / 2);
9527 // Otherwise we can't safely widen the elements used in this shuffle.
9530 assert(WidenedMask.size() == Mask.size() / 2 &&
9531 "Incorrect size of mask after widening the elements!");
9536 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9538 /// This routine just extracts two subvectors, shuffles them independently, and
9539 /// then concatenates them back together. This should work effectively with all
9540 /// AVX vector shuffle types.
9541 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9542 SDValue V2, ArrayRef<int> Mask,
9543 SelectionDAG &DAG) {
9544 assert(VT.getSizeInBits() >= 256 &&
9545 "Only for 256-bit or wider vector shuffles!");
9546 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9547 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9549 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9550 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9552 int NumElements = VT.getVectorNumElements();
9553 int SplitNumElements = NumElements / 2;
9554 MVT ScalarVT = VT.getScalarType();
9555 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9557 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9558 DAG.getIntPtrConstant(0));
9559 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9560 DAG.getIntPtrConstant(SplitNumElements));
9561 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9562 DAG.getIntPtrConstant(0));
9563 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9564 DAG.getIntPtrConstant(SplitNumElements));
9566 // Now create two 4-way blends of these half-width vectors.
9567 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9568 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9569 for (int i = 0; i < SplitNumElements; ++i) {
9570 int M = HalfMask[i];
9571 if (M >= NumElements) {
9572 V2BlendMask.push_back(M - NumElements);
9573 V1BlendMask.push_back(-1);
9574 BlendMask.push_back(SplitNumElements + i);
9575 } else if (M >= 0) {
9576 V2BlendMask.push_back(-1);
9577 V1BlendMask.push_back(M);
9578 BlendMask.push_back(i);
9580 V2BlendMask.push_back(-1);
9581 V1BlendMask.push_back(-1);
9582 BlendMask.push_back(-1);
9586 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9588 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9589 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9591 SDValue Lo = HalfBlend(LoMask);
9592 SDValue Hi = HalfBlend(HiMask);
9593 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9596 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9597 /// a permutation and blend of those lanes.
9599 /// This essentially blends the out-of-lane inputs to each lane into the lane
9600 /// from a permuted copy of the vector. This lowering strategy results in four
9601 /// instructions in the worst case for a single-input cross lane shuffle which
9602 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9603 /// of. Special cases for each particular shuffle pattern should be handled
9604 /// prior to trying this lowering.
9605 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9606 SDValue V1, SDValue V2,
9608 SelectionDAG &DAG) {
9609 // FIXME: This should probably be generalized for 512-bit vectors as well.
9610 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9611 int LaneSize = Mask.size() / 2;
9613 // If there are only inputs from one 128-bit lane, splitting will in fact be
9614 // less expensive. The flags track wether the given lane contains an element
9615 // that crosses to another lane.
9616 bool LaneCrossing[2] = {false, false};
9617 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9618 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9619 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9620 if (!LaneCrossing[0] || !LaneCrossing[1])
9621 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9623 if (isSingleInputShuffleMask(Mask)) {
9624 SmallVector<int, 32> FlippedBlendMask;
9625 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9626 FlippedBlendMask.push_back(
9627 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9629 : Mask[i] % LaneSize +
9630 (i / LaneSize) * LaneSize + Size));
9632 // Flip the vector, and blend the results which should now be in-lane. The
9633 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9634 // 5 for the high source. The value 3 selects the high half of source 2 and
9635 // the value 2 selects the low half of source 2. We only use source 2 to
9636 // allow folding it into a memory operand.
9637 unsigned PERMMask = 3 | 2 << 4;
9638 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9639 V1, DAG.getConstant(PERMMask, MVT::i8));
9640 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9643 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9644 // will be handled by the above logic and a blend of the results, much like
9645 // other patterns in AVX.
9646 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9649 /// \brief Handle lowering 2-lane 128-bit shuffles.
9650 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9651 SDValue V2, ArrayRef<int> Mask,
9652 const X86Subtarget *Subtarget,
9653 SelectionDAG &DAG) {
9654 // Blends are faster and handle all the non-lane-crossing cases.
9655 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9659 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9660 VT.getVectorNumElements() / 2);
9661 // Check for patterns which can be matched with a single insert of a 128-bit
9663 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9664 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9665 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9666 DAG.getIntPtrConstant(0));
9667 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9668 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9669 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9671 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9672 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9673 DAG.getIntPtrConstant(0));
9674 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9675 DAG.getIntPtrConstant(2));
9676 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9679 // Otherwise form a 128-bit permutation.
9680 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9681 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9682 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9683 DAG.getConstant(PermMask, MVT::i8));
9686 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9688 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9689 /// isn't available.
9690 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9691 const X86Subtarget *Subtarget,
9692 SelectionDAG &DAG) {
9694 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9695 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9696 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9697 ArrayRef<int> Mask = SVOp->getMask();
9698 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9700 SmallVector<int, 4> WidenedMask;
9701 if (canWidenShuffleElements(Mask, WidenedMask))
9702 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9705 if (isSingleInputShuffleMask(Mask)) {
9706 // Check for being able to broadcast a single element.
9707 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9708 Mask, Subtarget, DAG))
9711 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9712 // Non-half-crossing single input shuffles can be lowerid with an
9713 // interleaved permutation.
9714 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9715 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9716 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9717 DAG.getConstant(VPERMILPMask, MVT::i8));
9720 // With AVX2 we have direct support for this permutation.
9721 if (Subtarget->hasAVX2())
9722 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9723 getV4X86ShuffleImm8ForMask(Mask, DAG));
9725 // Otherwise, fall back.
9726 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9730 // X86 has dedicated unpack instructions that can handle specific blend
9731 // operations: UNPCKH and UNPCKL.
9732 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9733 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9734 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9735 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9737 // If we have a single input to the zero element, insert that into V1 if we
9738 // can do so cheaply.
9740 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9741 if (NumV2Elements == 1 && Mask[0] >= 4)
9742 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9743 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9746 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9750 // Check if the blend happens to exactly fit that of SHUFPD.
9751 if ((Mask[0] == -1 || Mask[0] < 2) &&
9752 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9753 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9754 (Mask[3] == -1 || Mask[3] >= 6)) {
9755 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9756 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9757 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9758 DAG.getConstant(SHUFPDMask, MVT::i8));
9760 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9761 (Mask[1] == -1 || Mask[1] < 2) &&
9762 (Mask[2] == -1 || Mask[2] >= 6) &&
9763 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9764 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9765 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9766 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9767 DAG.getConstant(SHUFPDMask, MVT::i8));
9770 // Otherwise fall back on generic blend lowering.
9771 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9775 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9777 /// This routine is only called when we have AVX2 and thus a reasonable
9778 /// instruction set for v4i64 shuffling..
9779 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9780 const X86Subtarget *Subtarget,
9781 SelectionDAG &DAG) {
9783 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9784 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9785 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9786 ArrayRef<int> Mask = SVOp->getMask();
9787 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9788 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9790 SmallVector<int, 4> WidenedMask;
9791 if (canWidenShuffleElements(Mask, WidenedMask))
9792 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9795 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9799 // Check for being able to broadcast a single element.
9800 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9801 Mask, Subtarget, DAG))
9804 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9805 // use lower latency instructions that will operate on both 128-bit lanes.
9806 SmallVector<int, 2> RepeatedMask;
9807 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9808 if (isSingleInputShuffleMask(Mask)) {
9809 int PSHUFDMask[] = {-1, -1, -1, -1};
9810 for (int i = 0; i < 2; ++i)
9811 if (RepeatedMask[i] >= 0) {
9812 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9813 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9816 ISD::BITCAST, DL, MVT::v4i64,
9817 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9818 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9819 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9822 // Use dedicated unpack instructions for masks that match their pattern.
9823 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9824 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9825 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9826 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9829 // AVX2 provides a direct instruction for permuting a single input across
9831 if (isSingleInputShuffleMask(Mask))
9832 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9833 getV4X86ShuffleImm8ForMask(Mask, DAG));
9835 // Otherwise fall back on generic blend lowering.
9836 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9840 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9842 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9843 /// isn't available.
9844 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9845 const X86Subtarget *Subtarget,
9846 SelectionDAG &DAG) {
9848 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9849 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9850 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9851 ArrayRef<int> Mask = SVOp->getMask();
9852 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9854 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9858 // Check for being able to broadcast a single element.
9859 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
9860 Mask, Subtarget, DAG))
9863 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9864 // options to efficiently lower the shuffle.
9865 SmallVector<int, 4> RepeatedMask;
9866 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9867 assert(RepeatedMask.size() == 4 &&
9868 "Repeated masks must be half the mask width!");
9869 if (isSingleInputShuffleMask(Mask))
9870 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9871 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9873 // Use dedicated unpack instructions for masks that match their pattern.
9874 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9875 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9876 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9877 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9879 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9880 // have already handled any direct blends. We also need to squash the
9881 // repeated mask into a simulated v4f32 mask.
9882 for (int i = 0; i < 4; ++i)
9883 if (RepeatedMask[i] >= 8)
9884 RepeatedMask[i] -= 4;
9885 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9888 // If we have a single input shuffle with different shuffle patterns in the
9889 // two 128-bit lanes use the variable mask to VPERMILPS.
9890 if (isSingleInputShuffleMask(Mask)) {
9891 SDValue VPermMask[8];
9892 for (int i = 0; i < 8; ++i)
9893 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9894 : DAG.getConstant(Mask[i], MVT::i32);
9895 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9897 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9898 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9900 if (Subtarget->hasAVX2())
9901 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9902 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9903 DAG.getNode(ISD::BUILD_VECTOR, DL,
9904 MVT::v8i32, VPermMask)),
9907 // Otherwise, fall back.
9908 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9912 // Otherwise fall back on generic blend lowering.
9913 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9917 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9919 /// This routine is only called when we have AVX2 and thus a reasonable
9920 /// instruction set for v8i32 shuffling..
9921 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9922 const X86Subtarget *Subtarget,
9923 SelectionDAG &DAG) {
9925 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9926 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9927 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9928 ArrayRef<int> Mask = SVOp->getMask();
9929 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9930 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9932 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9936 // Check for being able to broadcast a single element.
9937 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
9938 Mask, Subtarget, DAG))
9941 // If the shuffle mask is repeated in each 128-bit lane we can use more
9942 // efficient instructions that mirror the shuffles across the two 128-bit
9944 SmallVector<int, 4> RepeatedMask;
9945 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9946 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9947 if (isSingleInputShuffleMask(Mask))
9948 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9949 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9951 // Use dedicated unpack instructions for masks that match their pattern.
9952 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9953 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9954 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9955 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9958 // If the shuffle patterns aren't repeated but it is a single input, directly
9959 // generate a cross-lane VPERMD instruction.
9960 if (isSingleInputShuffleMask(Mask)) {
9961 SDValue VPermMask[8];
9962 for (int i = 0; i < 8; ++i)
9963 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9964 : DAG.getConstant(Mask[i], MVT::i32);
9966 X86ISD::VPERMV, DL, MVT::v8i32,
9967 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9970 // Otherwise fall back on generic blend lowering.
9971 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9975 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9977 /// This routine is only called when we have AVX2 and thus a reasonable
9978 /// instruction set for v16i16 shuffling..
9979 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9980 const X86Subtarget *Subtarget,
9981 SelectionDAG &DAG) {
9983 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9984 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9985 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9986 ArrayRef<int> Mask = SVOp->getMask();
9987 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9988 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9990 // Check for being able to broadcast a single element.
9991 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
9992 Mask, Subtarget, DAG))
9995 // There are no generalized cross-lane shuffle operations available on i16
9997 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9998 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10001 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10005 // Use dedicated unpack instructions for masks that match their pattern.
10006 if (isShuffleEquivalent(Mask,
10007 // First 128-bit lane:
10008 0, 16, 1, 17, 2, 18, 3, 19,
10009 // Second 128-bit lane:
10010 8, 24, 9, 25, 10, 26, 11, 27))
10011 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10012 if (isShuffleEquivalent(Mask,
10013 // First 128-bit lane:
10014 4, 20, 5, 21, 6, 22, 7, 23,
10015 // Second 128-bit lane:
10016 12, 28, 13, 29, 14, 30, 15, 31))
10017 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10019 if (isSingleInputShuffleMask(Mask)) {
10020 SDValue PSHUFBMask[32];
10021 for (int i = 0; i < 16; ++i) {
10022 if (Mask[i] == -1) {
10023 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10027 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10028 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10029 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10030 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10032 return DAG.getNode(
10033 ISD::BITCAST, DL, MVT::v16i16,
10035 X86ISD::PSHUFB, DL, MVT::v32i8,
10036 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10037 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10040 // Otherwise fall back on generic blend lowering.
10041 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
10045 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10047 /// This routine is only called when we have AVX2 and thus a reasonable
10048 /// instruction set for v32i8 shuffling..
10049 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10050 const X86Subtarget *Subtarget,
10051 SelectionDAG &DAG) {
10053 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10054 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10055 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10056 ArrayRef<int> Mask = SVOp->getMask();
10057 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10058 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10060 // Check for being able to broadcast a single element.
10061 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10062 Mask, Subtarget, DAG))
10065 // There are no generalized cross-lane shuffle operations available on i8
10067 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10068 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10071 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10075 // Use dedicated unpack instructions for masks that match their pattern.
10076 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10078 if (isShuffleEquivalent(
10080 // First 128-bit lane:
10081 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10082 // Second 128-bit lane:
10083 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10084 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10085 if (isShuffleEquivalent(
10087 // First 128-bit lane:
10088 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10089 // Second 128-bit lane:
10090 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10091 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10093 if (isSingleInputShuffleMask(Mask)) {
10094 SDValue PSHUFBMask[32];
10095 for (int i = 0; i < 32; ++i)
10098 ? DAG.getUNDEF(MVT::i8)
10099 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10101 return DAG.getNode(
10102 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10103 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10106 // Otherwise fall back on generic blend lowering.
10107 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
10111 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10113 /// This routine either breaks down the specific type of a 256-bit x86 vector
10114 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10115 /// together based on the available instructions.
10116 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10117 MVT VT, const X86Subtarget *Subtarget,
10118 SelectionDAG &DAG) {
10120 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10121 ArrayRef<int> Mask = SVOp->getMask();
10123 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10124 // check for those subtargets here and avoid much of the subtarget querying in
10125 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10126 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10127 // floating point types there eventually, just immediately cast everything to
10128 // a float and operate entirely in that domain.
10129 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10130 int ElementBits = VT.getScalarSizeInBits();
10131 if (ElementBits < 32)
10132 // No floating point type available, decompose into 128-bit vectors.
10133 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10135 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10136 VT.getVectorNumElements());
10137 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10138 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10139 return DAG.getNode(ISD::BITCAST, DL, VT,
10140 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10143 switch (VT.SimpleTy) {
10145 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10147 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10149 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10151 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10153 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10155 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10158 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10162 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10163 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10164 const X86Subtarget *Subtarget,
10165 SelectionDAG &DAG) {
10167 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10168 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10169 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10170 ArrayRef<int> Mask = SVOp->getMask();
10171 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10173 // FIXME: Implement direct support for this type!
10174 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10177 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10178 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10179 const X86Subtarget *Subtarget,
10180 SelectionDAG &DAG) {
10182 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10183 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10184 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10185 ArrayRef<int> Mask = SVOp->getMask();
10186 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10188 // FIXME: Implement direct support for this type!
10189 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10192 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10193 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10194 const X86Subtarget *Subtarget,
10195 SelectionDAG &DAG) {
10197 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10198 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10199 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10200 ArrayRef<int> Mask = SVOp->getMask();
10201 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10202 assert(Subtarget->hasDQI() && "We can only lower v8i64 with AVX-512-DQI");
10204 // FIXME: Implement direct support for this type!
10205 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10208 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10209 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10210 const X86Subtarget *Subtarget,
10211 SelectionDAG &DAG) {
10213 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10214 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10215 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10216 ArrayRef<int> Mask = SVOp->getMask();
10217 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10218 assert(Subtarget->hasDQI() && "We can only lower v16i32 with AVX-512-DQI!");
10220 // FIXME: Implement direct support for this type!
10221 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10224 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10225 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10226 const X86Subtarget *Subtarget,
10227 SelectionDAG &DAG) {
10229 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10230 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10231 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10232 ArrayRef<int> Mask = SVOp->getMask();
10233 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10234 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10236 // FIXME: Implement direct support for this type!
10237 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10240 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10241 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10242 const X86Subtarget *Subtarget,
10243 SelectionDAG &DAG) {
10245 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10246 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10247 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10248 ArrayRef<int> Mask = SVOp->getMask();
10249 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10250 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10252 // FIXME: Implement direct support for this type!
10253 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10256 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10258 /// This routine either breaks down the specific type of a 512-bit x86 vector
10259 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10260 /// together based on the available instructions.
10261 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10262 MVT VT, const X86Subtarget *Subtarget,
10263 SelectionDAG &DAG) {
10265 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10266 ArrayRef<int> Mask = SVOp->getMask();
10267 assert(Subtarget->hasAVX512() &&
10268 "Cannot lower 512-bit vectors w/ basic ISA!");
10270 // Dispatch to each element type for lowering. If we don't have supprot for
10271 // specific element type shuffles at 512 bits, immediately split them and
10272 // lower them. Each lowering routine of a given type is allowed to assume that
10273 // the requisite ISA extensions for that element type are available.
10274 switch (VT.SimpleTy) {
10276 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10278 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10280 if (Subtarget->hasDQI())
10281 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10284 if (Subtarget->hasDQI())
10285 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10288 if (Subtarget->hasBWI())
10289 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10292 if (Subtarget->hasBWI())
10293 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10297 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10300 // Otherwise fall back on splitting.
10301 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10304 /// \brief Top-level lowering for x86 vector shuffles.
10306 /// This handles decomposition, canonicalization, and lowering of all x86
10307 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10308 /// above in helper routines. The canonicalization attempts to widen shuffles
10309 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10310 /// s.t. only one of the two inputs needs to be tested, etc.
10311 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10312 SelectionDAG &DAG) {
10313 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10314 ArrayRef<int> Mask = SVOp->getMask();
10315 SDValue V1 = Op.getOperand(0);
10316 SDValue V2 = Op.getOperand(1);
10317 MVT VT = Op.getSimpleValueType();
10318 int NumElements = VT.getVectorNumElements();
10321 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10323 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10324 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10325 if (V1IsUndef && V2IsUndef)
10326 return DAG.getUNDEF(VT);
10328 // When we create a shuffle node we put the UNDEF node to second operand,
10329 // but in some cases the first operand may be transformed to UNDEF.
10330 // In this case we should just commute the node.
10332 return DAG.getCommutedVectorShuffle(*SVOp);
10334 // Check for non-undef masks pointing at an undef vector and make the masks
10335 // undef as well. This makes it easier to match the shuffle based solely on
10339 if (M >= NumElements) {
10340 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10341 for (int &M : NewMask)
10342 if (M >= NumElements)
10344 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10347 // Try to collapse shuffles into using a vector type with fewer elements but
10348 // wider element types. We cap this to not form integers or floating point
10349 // elements wider than 64 bits, but it might be interesting to form i128
10350 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10351 SmallVector<int, 16> WidenedMask;
10352 if (VT.getScalarSizeInBits() < 64 &&
10353 canWidenShuffleElements(Mask, WidenedMask)) {
10354 MVT NewEltVT = VT.isFloatingPoint()
10355 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10356 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10357 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10358 // Make sure that the new vector type is legal. For example, v2f64 isn't
10360 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10361 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10362 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10363 return DAG.getNode(ISD::BITCAST, dl, VT,
10364 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10368 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10369 for (int M : SVOp->getMask())
10371 ++NumUndefElements;
10372 else if (M < NumElements)
10377 // Commute the shuffle as needed such that more elements come from V1 than
10378 // V2. This allows us to match the shuffle pattern strictly on how many
10379 // elements come from V1 without handling the symmetric cases.
10380 if (NumV2Elements > NumV1Elements)
10381 return DAG.getCommutedVectorShuffle(*SVOp);
10383 // When the number of V1 and V2 elements are the same, try to minimize the
10384 // number of uses of V2 in the low half of the vector. When that is tied,
10385 // ensure that the sum of indices for V1 is equal to or lower than the sum
10387 if (NumV1Elements == NumV2Elements) {
10388 int LowV1Elements = 0, LowV2Elements = 0;
10389 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10390 if (M >= NumElements)
10394 if (LowV2Elements > LowV1Elements) {
10395 return DAG.getCommutedVectorShuffle(*SVOp);
10396 } else if (LowV2Elements == LowV1Elements) {
10397 int SumV1Indices = 0, SumV2Indices = 0;
10398 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10399 if (SVOp->getMask()[i] >= NumElements)
10401 else if (SVOp->getMask()[i] >= 0)
10403 if (SumV2Indices < SumV1Indices)
10404 return DAG.getCommutedVectorShuffle(*SVOp);
10408 // For each vector width, delegate to a specialized lowering routine.
10409 if (VT.getSizeInBits() == 128)
10410 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10412 if (VT.getSizeInBits() == 256)
10413 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10415 // Force AVX-512 vectors to be scalarized for now.
10416 // FIXME: Implement AVX-512 support!
10417 if (VT.getSizeInBits() == 512)
10418 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10420 llvm_unreachable("Unimplemented!");
10424 //===----------------------------------------------------------------------===//
10425 // Legacy vector shuffle lowering
10427 // This code is the legacy code handling vector shuffles until the above
10428 // replaces its functionality and performance.
10429 //===----------------------------------------------------------------------===//
10431 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10432 bool hasInt256, unsigned *MaskOut = nullptr) {
10433 MVT EltVT = VT.getVectorElementType();
10435 // There is no blend with immediate in AVX-512.
10436 if (VT.is512BitVector())
10439 if (!hasSSE41 || EltVT == MVT::i8)
10441 if (!hasInt256 && VT == MVT::v16i16)
10444 unsigned MaskValue = 0;
10445 unsigned NumElems = VT.getVectorNumElements();
10446 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10447 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10448 unsigned NumElemsInLane = NumElems / NumLanes;
10450 // Blend for v16i16 should be symetric for the both lanes.
10451 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10453 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10454 int EltIdx = MaskVals[i];
10456 if ((EltIdx < 0 || EltIdx == (int)i) &&
10457 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10460 if (((unsigned)EltIdx == (i + NumElems)) &&
10461 (SndLaneEltIdx < 0 ||
10462 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10463 MaskValue |= (1 << i);
10469 *MaskOut = MaskValue;
10473 // Try to lower a shuffle node into a simple blend instruction.
10474 // This function assumes isBlendMask returns true for this
10475 // SuffleVectorSDNode
10476 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10477 unsigned MaskValue,
10478 const X86Subtarget *Subtarget,
10479 SelectionDAG &DAG) {
10480 MVT VT = SVOp->getSimpleValueType(0);
10481 MVT EltVT = VT.getVectorElementType();
10482 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10483 Subtarget->hasInt256() && "Trying to lower a "
10484 "VECTOR_SHUFFLE to a Blend but "
10485 "with the wrong mask"));
10486 SDValue V1 = SVOp->getOperand(0);
10487 SDValue V2 = SVOp->getOperand(1);
10489 unsigned NumElems = VT.getVectorNumElements();
10491 // Convert i32 vectors to floating point if it is not AVX2.
10492 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10494 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10495 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10497 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10498 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10501 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10502 DAG.getConstant(MaskValue, MVT::i32));
10503 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10506 /// In vector type \p VT, return true if the element at index \p InputIdx
10507 /// falls on a different 128-bit lane than \p OutputIdx.
10508 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10509 unsigned OutputIdx) {
10510 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10511 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10514 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10515 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10516 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10517 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10519 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10520 SelectionDAG &DAG) {
10521 MVT VT = V1.getSimpleValueType();
10522 assert(VT.is128BitVector() || VT.is256BitVector());
10524 MVT EltVT = VT.getVectorElementType();
10525 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10526 unsigned NumElts = VT.getVectorNumElements();
10528 SmallVector<SDValue, 32> PshufbMask;
10529 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10530 int InputIdx = MaskVals[OutputIdx];
10531 unsigned InputByteIdx;
10533 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10534 InputByteIdx = 0x80;
10536 // Cross lane is not allowed.
10537 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10539 InputByteIdx = InputIdx * EltSizeInBytes;
10540 // Index is an byte offset within the 128-bit lane.
10541 InputByteIdx &= 0xf;
10544 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10545 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10546 if (InputByteIdx != 0x80)
10551 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10553 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10554 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10555 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10558 // v8i16 shuffles - Prefer shuffles in the following order:
10559 // 1. [all] pshuflw, pshufhw, optional move
10560 // 2. [ssse3] 1 x pshufb
10561 // 3. [ssse3] 2 x pshufb + 1 x por
10562 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10564 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10565 SelectionDAG &DAG) {
10566 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10567 SDValue V1 = SVOp->getOperand(0);
10568 SDValue V2 = SVOp->getOperand(1);
10570 SmallVector<int, 8> MaskVals;
10572 // Determine if more than 1 of the words in each of the low and high quadwords
10573 // of the result come from the same quadword of one of the two inputs. Undef
10574 // mask values count as coming from any quadword, for better codegen.
10576 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10577 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10578 unsigned LoQuad[] = { 0, 0, 0, 0 };
10579 unsigned HiQuad[] = { 0, 0, 0, 0 };
10580 // Indices of quads used.
10581 std::bitset<4> InputQuads;
10582 for (unsigned i = 0; i < 8; ++i) {
10583 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10584 int EltIdx = SVOp->getMaskElt(i);
10585 MaskVals.push_back(EltIdx);
10593 ++Quad[EltIdx / 4];
10594 InputQuads.set(EltIdx / 4);
10597 int BestLoQuad = -1;
10598 unsigned MaxQuad = 1;
10599 for (unsigned i = 0; i < 4; ++i) {
10600 if (LoQuad[i] > MaxQuad) {
10602 MaxQuad = LoQuad[i];
10606 int BestHiQuad = -1;
10608 for (unsigned i = 0; i < 4; ++i) {
10609 if (HiQuad[i] > MaxQuad) {
10611 MaxQuad = HiQuad[i];
10615 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10616 // of the two input vectors, shuffle them into one input vector so only a
10617 // single pshufb instruction is necessary. If there are more than 2 input
10618 // quads, disable the next transformation since it does not help SSSE3.
10619 bool V1Used = InputQuads[0] || InputQuads[1];
10620 bool V2Used = InputQuads[2] || InputQuads[3];
10621 if (Subtarget->hasSSSE3()) {
10622 if (InputQuads.count() == 2 && V1Used && V2Used) {
10623 BestLoQuad = InputQuads[0] ? 0 : 1;
10624 BestHiQuad = InputQuads[2] ? 2 : 3;
10626 if (InputQuads.count() > 2) {
10632 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10633 // the shuffle mask. If a quad is scored as -1, that means that it contains
10634 // words from all 4 input quadwords.
10636 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10638 BestLoQuad < 0 ? 0 : BestLoQuad,
10639 BestHiQuad < 0 ? 1 : BestHiQuad
10641 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10642 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10643 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10644 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10646 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10647 // source words for the shuffle, to aid later transformations.
10648 bool AllWordsInNewV = true;
10649 bool InOrder[2] = { true, true };
10650 for (unsigned i = 0; i != 8; ++i) {
10651 int idx = MaskVals[i];
10653 InOrder[i/4] = false;
10654 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10656 AllWordsInNewV = false;
10660 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10661 if (AllWordsInNewV) {
10662 for (int i = 0; i != 8; ++i) {
10663 int idx = MaskVals[i];
10666 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10667 if ((idx != i) && idx < 4)
10669 if ((idx != i) && idx > 3)
10678 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10679 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10680 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10681 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10682 unsigned TargetMask = 0;
10683 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10684 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10685 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10686 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10687 getShufflePSHUFLWImmediate(SVOp);
10688 V1 = NewV.getOperand(0);
10689 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10693 // Promote splats to a larger type which usually leads to more efficient code.
10694 // FIXME: Is this true if pshufb is available?
10695 if (SVOp->isSplat())
10696 return PromoteSplat(SVOp, DAG);
10698 // If we have SSSE3, and all words of the result are from 1 input vector,
10699 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10700 // is present, fall back to case 4.
10701 if (Subtarget->hasSSSE3()) {
10702 SmallVector<SDValue,16> pshufbMask;
10704 // If we have elements from both input vectors, set the high bit of the
10705 // shuffle mask element to zero out elements that come from V2 in the V1
10706 // mask, and elements that come from V1 in the V2 mask, so that the two
10707 // results can be OR'd together.
10708 bool TwoInputs = V1Used && V2Used;
10709 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10711 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10713 // Calculate the shuffle mask for the second input, shuffle it, and
10714 // OR it with the first shuffled input.
10715 CommuteVectorShuffleMask(MaskVals, 8);
10716 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10717 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10718 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10721 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10722 // and update MaskVals with new element order.
10723 std::bitset<8> InOrder;
10724 if (BestLoQuad >= 0) {
10725 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10726 for (int i = 0; i != 4; ++i) {
10727 int idx = MaskVals[i];
10730 } else if ((idx / 4) == BestLoQuad) {
10731 MaskV[i] = idx & 3;
10735 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10738 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10739 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10740 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10741 NewV.getOperand(0),
10742 getShufflePSHUFLWImmediate(SVOp), DAG);
10746 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10747 // and update MaskVals with the new element order.
10748 if (BestHiQuad >= 0) {
10749 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10750 for (unsigned i = 4; i != 8; ++i) {
10751 int idx = MaskVals[i];
10754 } else if ((idx / 4) == BestHiQuad) {
10755 MaskV[i] = (idx & 3) + 4;
10759 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10762 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10763 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10764 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10765 NewV.getOperand(0),
10766 getShufflePSHUFHWImmediate(SVOp), DAG);
10770 // In case BestHi & BestLo were both -1, which means each quadword has a word
10771 // from each of the four input quadwords, calculate the InOrder bitvector now
10772 // before falling through to the insert/extract cleanup.
10773 if (BestLoQuad == -1 && BestHiQuad == -1) {
10775 for (int i = 0; i != 8; ++i)
10776 if (MaskVals[i] < 0 || MaskVals[i] == i)
10780 // The other elements are put in the right place using pextrw and pinsrw.
10781 for (unsigned i = 0; i != 8; ++i) {
10784 int EltIdx = MaskVals[i];
10787 SDValue ExtOp = (EltIdx < 8) ?
10788 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10789 DAG.getIntPtrConstant(EltIdx)) :
10790 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10791 DAG.getIntPtrConstant(EltIdx - 8));
10792 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10793 DAG.getIntPtrConstant(i));
10798 /// \brief v16i16 shuffles
10800 /// FIXME: We only support generation of a single pshufb currently. We can
10801 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10802 /// well (e.g 2 x pshufb + 1 x por).
10804 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10805 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10806 SDValue V1 = SVOp->getOperand(0);
10807 SDValue V2 = SVOp->getOperand(1);
10810 if (V2.getOpcode() != ISD::UNDEF)
10813 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10814 return getPSHUFB(MaskVals, V1, dl, DAG);
10817 // v16i8 shuffles - Prefer shuffles in the following order:
10818 // 1. [ssse3] 1 x pshufb
10819 // 2. [ssse3] 2 x pshufb + 1 x por
10820 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10821 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10822 const X86Subtarget* Subtarget,
10823 SelectionDAG &DAG) {
10824 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10825 SDValue V1 = SVOp->getOperand(0);
10826 SDValue V2 = SVOp->getOperand(1);
10828 ArrayRef<int> MaskVals = SVOp->getMask();
10830 // Promote splats to a larger type which usually leads to more efficient code.
10831 // FIXME: Is this true if pshufb is available?
10832 if (SVOp->isSplat())
10833 return PromoteSplat(SVOp, DAG);
10835 // If we have SSSE3, case 1 is generated when all result bytes come from
10836 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10837 // present, fall back to case 3.
10839 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10840 if (Subtarget->hasSSSE3()) {
10841 SmallVector<SDValue,16> pshufbMask;
10843 // If all result elements are from one input vector, then only translate
10844 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10846 // Otherwise, we have elements from both input vectors, and must zero out
10847 // elements that come from V2 in the first mask, and V1 in the second mask
10848 // so that we can OR them together.
10849 for (unsigned i = 0; i != 16; ++i) {
10850 int EltIdx = MaskVals[i];
10851 if (EltIdx < 0 || EltIdx >= 16)
10853 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10855 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10856 DAG.getNode(ISD::BUILD_VECTOR, dl,
10857 MVT::v16i8, pshufbMask));
10859 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10860 // the 2nd operand if it's undefined or zero.
10861 if (V2.getOpcode() == ISD::UNDEF ||
10862 ISD::isBuildVectorAllZeros(V2.getNode()))
10865 // Calculate the shuffle mask for the second input, shuffle it, and
10866 // OR it with the first shuffled input.
10867 pshufbMask.clear();
10868 for (unsigned i = 0; i != 16; ++i) {
10869 int EltIdx = MaskVals[i];
10870 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10871 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10873 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10874 DAG.getNode(ISD::BUILD_VECTOR, dl,
10875 MVT::v16i8, pshufbMask));
10876 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10879 // No SSSE3 - Calculate in place words and then fix all out of place words
10880 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10881 // the 16 different words that comprise the two doublequadword input vectors.
10882 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10883 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10885 for (int i = 0; i != 8; ++i) {
10886 int Elt0 = MaskVals[i*2];
10887 int Elt1 = MaskVals[i*2+1];
10889 // This word of the result is all undef, skip it.
10890 if (Elt0 < 0 && Elt1 < 0)
10893 // This word of the result is already in the correct place, skip it.
10894 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10897 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10898 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10901 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10902 // using a single extract together, load it and store it.
10903 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10904 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10905 DAG.getIntPtrConstant(Elt1 / 2));
10906 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10907 DAG.getIntPtrConstant(i));
10911 // If Elt1 is defined, extract it from the appropriate source. If the
10912 // source byte is not also odd, shift the extracted word left 8 bits
10913 // otherwise clear the bottom 8 bits if we need to do an or.
10915 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10916 DAG.getIntPtrConstant(Elt1 / 2));
10917 if ((Elt1 & 1) == 0)
10918 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10920 TLI.getShiftAmountTy(InsElt.getValueType())));
10921 else if (Elt0 >= 0)
10922 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10923 DAG.getConstant(0xFF00, MVT::i16));
10925 // If Elt0 is defined, extract it from the appropriate source. If the
10926 // source byte is not also even, shift the extracted word right 8 bits. If
10927 // Elt1 was also defined, OR the extracted values together before
10928 // inserting them in the result.
10930 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10931 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10932 if ((Elt0 & 1) != 0)
10933 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10935 TLI.getShiftAmountTy(InsElt0.getValueType())));
10936 else if (Elt1 >= 0)
10937 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10938 DAG.getConstant(0x00FF, MVT::i16));
10939 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10942 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10943 DAG.getIntPtrConstant(i));
10945 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10948 // v32i8 shuffles - Translate to VPSHUFB if possible.
10950 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10951 const X86Subtarget *Subtarget,
10952 SelectionDAG &DAG) {
10953 MVT VT = SVOp->getSimpleValueType(0);
10954 SDValue V1 = SVOp->getOperand(0);
10955 SDValue V2 = SVOp->getOperand(1);
10957 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10959 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10960 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10961 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10963 // VPSHUFB may be generated if
10964 // (1) one of input vector is undefined or zeroinitializer.
10965 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10966 // And (2) the mask indexes don't cross the 128-bit lane.
10967 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10968 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10971 if (V1IsAllZero && !V2IsAllZero) {
10972 CommuteVectorShuffleMask(MaskVals, 32);
10975 return getPSHUFB(MaskVals, V1, dl, DAG);
10978 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10979 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10980 /// done when every pair / quad of shuffle mask elements point to elements in
10981 /// the right sequence. e.g.
10982 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10984 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10985 SelectionDAG &DAG) {
10986 MVT VT = SVOp->getSimpleValueType(0);
10988 unsigned NumElems = VT.getVectorNumElements();
10991 switch (VT.SimpleTy) {
10992 default: llvm_unreachable("Unexpected!");
10995 return SDValue(SVOp, 0);
10996 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10997 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10998 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10999 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11000 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11001 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11004 SmallVector<int, 8> MaskVec;
11005 for (unsigned i = 0; i != NumElems; i += Scale) {
11007 for (unsigned j = 0; j != Scale; ++j) {
11008 int EltIdx = SVOp->getMaskElt(i+j);
11012 StartIdx = (EltIdx / Scale);
11013 if (EltIdx != (int)(StartIdx*Scale + j))
11016 MaskVec.push_back(StartIdx);
11019 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11020 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11021 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11024 /// getVZextMovL - Return a zero-extending vector move low node.
11026 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11027 SDValue SrcOp, SelectionDAG &DAG,
11028 const X86Subtarget *Subtarget, SDLoc dl) {
11029 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11030 LoadSDNode *LD = nullptr;
11031 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11032 LD = dyn_cast<LoadSDNode>(SrcOp);
11034 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11036 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11037 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11038 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11039 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11040 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11042 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11043 return DAG.getNode(ISD::BITCAST, dl, VT,
11044 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11045 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11047 SrcOp.getOperand(0)
11053 return DAG.getNode(ISD::BITCAST, dl, VT,
11054 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11055 DAG.getNode(ISD::BITCAST, dl,
11059 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11060 /// which could not be matched by any known target speficic shuffle
11062 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11064 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11065 if (NewOp.getNode())
11068 MVT VT = SVOp->getSimpleValueType(0);
11070 unsigned NumElems = VT.getVectorNumElements();
11071 unsigned NumLaneElems = NumElems / 2;
11074 MVT EltVT = VT.getVectorElementType();
11075 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11078 SmallVector<int, 16> Mask;
11079 for (unsigned l = 0; l < 2; ++l) {
11080 // Build a shuffle mask for the output, discovering on the fly which
11081 // input vectors to use as shuffle operands (recorded in InputUsed).
11082 // If building a suitable shuffle vector proves too hard, then bail
11083 // out with UseBuildVector set.
11084 bool UseBuildVector = false;
11085 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11086 unsigned LaneStart = l * NumLaneElems;
11087 for (unsigned i = 0; i != NumLaneElems; ++i) {
11088 // The mask element. This indexes into the input.
11089 int Idx = SVOp->getMaskElt(i+LaneStart);
11091 // the mask element does not index into any input vector.
11092 Mask.push_back(-1);
11096 // The input vector this mask element indexes into.
11097 int Input = Idx / NumLaneElems;
11099 // Turn the index into an offset from the start of the input vector.
11100 Idx -= Input * NumLaneElems;
11102 // Find or create a shuffle vector operand to hold this input.
11104 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11105 if (InputUsed[OpNo] == Input)
11106 // This input vector is already an operand.
11108 if (InputUsed[OpNo] < 0) {
11109 // Create a new operand for this input vector.
11110 InputUsed[OpNo] = Input;
11115 if (OpNo >= array_lengthof(InputUsed)) {
11116 // More than two input vectors used! Give up on trying to create a
11117 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11118 UseBuildVector = true;
11122 // Add the mask index for the new shuffle vector.
11123 Mask.push_back(Idx + OpNo * NumLaneElems);
11126 if (UseBuildVector) {
11127 SmallVector<SDValue, 16> SVOps;
11128 for (unsigned i = 0; i != NumLaneElems; ++i) {
11129 // The mask element. This indexes into the input.
11130 int Idx = SVOp->getMaskElt(i+LaneStart);
11132 SVOps.push_back(DAG.getUNDEF(EltVT));
11136 // The input vector this mask element indexes into.
11137 int Input = Idx / NumElems;
11139 // Turn the index into an offset from the start of the input vector.
11140 Idx -= Input * NumElems;
11142 // Extract the vector element by hand.
11143 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11144 SVOp->getOperand(Input),
11145 DAG.getIntPtrConstant(Idx)));
11148 // Construct the output using a BUILD_VECTOR.
11149 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11150 } else if (InputUsed[0] < 0) {
11151 // No input vectors were used! The result is undefined.
11152 Output[l] = DAG.getUNDEF(NVT);
11154 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11155 (InputUsed[0] % 2) * NumLaneElems,
11157 // If only one input was used, use an undefined vector for the other.
11158 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11159 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11160 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11161 // At least one input vector was used. Create a new shuffle vector.
11162 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11168 // Concatenate the result back
11169 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11172 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11173 /// 4 elements, and match them with several different shuffle types.
11175 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11176 SDValue V1 = SVOp->getOperand(0);
11177 SDValue V2 = SVOp->getOperand(1);
11179 MVT VT = SVOp->getSimpleValueType(0);
11181 assert(VT.is128BitVector() && "Unsupported vector size");
11183 std::pair<int, int> Locs[4];
11184 int Mask1[] = { -1, -1, -1, -1 };
11185 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11187 unsigned NumHi = 0;
11188 unsigned NumLo = 0;
11189 for (unsigned i = 0; i != 4; ++i) {
11190 int Idx = PermMask[i];
11192 Locs[i] = std::make_pair(-1, -1);
11194 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11196 Locs[i] = std::make_pair(0, NumLo);
11197 Mask1[NumLo] = Idx;
11200 Locs[i] = std::make_pair(1, NumHi);
11202 Mask1[2+NumHi] = Idx;
11208 if (NumLo <= 2 && NumHi <= 2) {
11209 // If no more than two elements come from either vector. This can be
11210 // implemented with two shuffles. First shuffle gather the elements.
11211 // The second shuffle, which takes the first shuffle as both of its
11212 // vector operands, put the elements into the right order.
11213 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11215 int Mask2[] = { -1, -1, -1, -1 };
11217 for (unsigned i = 0; i != 4; ++i)
11218 if (Locs[i].first != -1) {
11219 unsigned Idx = (i < 2) ? 0 : 4;
11220 Idx += Locs[i].first * 2 + Locs[i].second;
11224 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11227 if (NumLo == 3 || NumHi == 3) {
11228 // Otherwise, we must have three elements from one vector, call it X, and
11229 // one element from the other, call it Y. First, use a shufps to build an
11230 // intermediate vector with the one element from Y and the element from X
11231 // that will be in the same half in the final destination (the indexes don't
11232 // matter). Then, use a shufps to build the final vector, taking the half
11233 // containing the element from Y from the intermediate, and the other half
11236 // Normalize it so the 3 elements come from V1.
11237 CommuteVectorShuffleMask(PermMask, 4);
11241 // Find the element from V2.
11243 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11244 int Val = PermMask[HiIndex];
11251 Mask1[0] = PermMask[HiIndex];
11253 Mask1[2] = PermMask[HiIndex^1];
11255 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11257 if (HiIndex >= 2) {
11258 Mask1[0] = PermMask[0];
11259 Mask1[1] = PermMask[1];
11260 Mask1[2] = HiIndex & 1 ? 6 : 4;
11261 Mask1[3] = HiIndex & 1 ? 4 : 6;
11262 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11265 Mask1[0] = HiIndex & 1 ? 2 : 0;
11266 Mask1[1] = HiIndex & 1 ? 0 : 2;
11267 Mask1[2] = PermMask[2];
11268 Mask1[3] = PermMask[3];
11273 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11276 // Break it into (shuffle shuffle_hi, shuffle_lo).
11277 int LoMask[] = { -1, -1, -1, -1 };
11278 int HiMask[] = { -1, -1, -1, -1 };
11280 int *MaskPtr = LoMask;
11281 unsigned MaskIdx = 0;
11282 unsigned LoIdx = 0;
11283 unsigned HiIdx = 2;
11284 for (unsigned i = 0; i != 4; ++i) {
11291 int Idx = PermMask[i];
11293 Locs[i] = std::make_pair(-1, -1);
11294 } else if (Idx < 4) {
11295 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11296 MaskPtr[LoIdx] = Idx;
11299 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11300 MaskPtr[HiIdx] = Idx;
11305 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11306 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11307 int MaskOps[] = { -1, -1, -1, -1 };
11308 for (unsigned i = 0; i != 4; ++i)
11309 if (Locs[i].first != -1)
11310 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11311 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11314 static bool MayFoldVectorLoad(SDValue V) {
11315 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11316 V = V.getOperand(0);
11318 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11319 V = V.getOperand(0);
11320 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11321 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11322 // BUILD_VECTOR (load), undef
11323 V = V.getOperand(0);
11325 return MayFoldLoad(V);
11329 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11330 MVT VT = Op.getSimpleValueType();
11332 // Canonizalize to v2f64.
11333 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11334 return DAG.getNode(ISD::BITCAST, dl, VT,
11335 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11340 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11342 SDValue V1 = Op.getOperand(0);
11343 SDValue V2 = Op.getOperand(1);
11344 MVT VT = Op.getSimpleValueType();
11346 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11348 if (HasSSE2 && VT == MVT::v2f64)
11349 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11351 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11352 return DAG.getNode(ISD::BITCAST, dl, VT,
11353 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11354 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11355 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11359 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11360 SDValue V1 = Op.getOperand(0);
11361 SDValue V2 = Op.getOperand(1);
11362 MVT VT = Op.getSimpleValueType();
11364 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11365 "unsupported shuffle type");
11367 if (V2.getOpcode() == ISD::UNDEF)
11371 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11375 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11376 SDValue V1 = Op.getOperand(0);
11377 SDValue V2 = Op.getOperand(1);
11378 MVT VT = Op.getSimpleValueType();
11379 unsigned NumElems = VT.getVectorNumElements();
11381 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11382 // operand of these instructions is only memory, so check if there's a
11383 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11385 bool CanFoldLoad = false;
11387 // Trivial case, when V2 comes from a load.
11388 if (MayFoldVectorLoad(V2))
11389 CanFoldLoad = true;
11391 // When V1 is a load, it can be folded later into a store in isel, example:
11392 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11394 // (MOVLPSmr addr:$src1, VR128:$src2)
11395 // So, recognize this potential and also use MOVLPS or MOVLPD
11396 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11397 CanFoldLoad = true;
11399 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11401 if (HasSSE2 && NumElems == 2)
11402 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11405 // If we don't care about the second element, proceed to use movss.
11406 if (SVOp->getMaskElt(1) != -1)
11407 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11410 // movl and movlp will both match v2i64, but v2i64 is never matched by
11411 // movl earlier because we make it strict to avoid messing with the movlp load
11412 // folding logic (see the code above getMOVLP call). Match it here then,
11413 // this is horrible, but will stay like this until we move all shuffle
11414 // matching to x86 specific nodes. Note that for the 1st condition all
11415 // types are matched with movsd.
11417 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11418 // as to remove this logic from here, as much as possible
11419 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11420 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11421 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11424 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11426 // Invert the operand order and use SHUFPS to match it.
11427 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11428 getShuffleSHUFImmediate(SVOp), DAG);
11431 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11432 SelectionDAG &DAG) {
11434 MVT VT = Load->getSimpleValueType(0);
11435 MVT EVT = VT.getVectorElementType();
11436 SDValue Addr = Load->getOperand(1);
11437 SDValue NewAddr = DAG.getNode(
11438 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11439 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11442 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11443 DAG.getMachineFunction().getMachineMemOperand(
11444 Load->getMemOperand(), 0, EVT.getStoreSize()));
11448 // It is only safe to call this function if isINSERTPSMask is true for
11449 // this shufflevector mask.
11450 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11451 SelectionDAG &DAG) {
11452 // Generate an insertps instruction when inserting an f32 from memory onto a
11453 // v4f32 or when copying a member from one v4f32 to another.
11454 // We also use it for transferring i32 from one register to another,
11455 // since it simply copies the same bits.
11456 // If we're transferring an i32 from memory to a specific element in a
11457 // register, we output a generic DAG that will match the PINSRD
11459 MVT VT = SVOp->getSimpleValueType(0);
11460 MVT EVT = VT.getVectorElementType();
11461 SDValue V1 = SVOp->getOperand(0);
11462 SDValue V2 = SVOp->getOperand(1);
11463 auto Mask = SVOp->getMask();
11464 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11465 "unsupported vector type for insertps/pinsrd");
11467 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11468 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11469 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11473 unsigned DestIndex;
11477 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11480 // If we have 1 element from each vector, we have to check if we're
11481 // changing V1's element's place. If so, we're done. Otherwise, we
11482 // should assume we're changing V2's element's place and behave
11484 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11485 assert(DestIndex <= INT32_MAX && "truncated destination index");
11486 if (FromV1 == FromV2 &&
11487 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11491 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11494 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11495 "More than one element from V1 and from V2, or no elements from one "
11496 "of the vectors. This case should not have returned true from "
11501 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11504 // Get an index into the source vector in the range [0,4) (the mask is
11505 // in the range [0,8) because it can address V1 and V2)
11506 unsigned SrcIndex = Mask[DestIndex] % 4;
11507 if (MayFoldLoad(From)) {
11508 // Trivial case, when From comes from a load and is only used by the
11509 // shuffle. Make it use insertps from the vector that we need from that
11512 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11513 if (!NewLoad.getNode())
11516 if (EVT == MVT::f32) {
11517 // Create this as a scalar to vector to match the instruction pattern.
11518 SDValue LoadScalarToVector =
11519 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11520 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11521 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11523 } else { // EVT == MVT::i32
11524 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11525 // instruction, to match the PINSRD instruction, which loads an i32 to a
11526 // certain vector element.
11527 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11528 DAG.getConstant(DestIndex, MVT::i32));
11532 // Vector-element-to-vector
11533 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11534 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11537 // Reduce a vector shuffle to zext.
11538 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11539 SelectionDAG &DAG) {
11540 // PMOVZX is only available from SSE41.
11541 if (!Subtarget->hasSSE41())
11544 MVT VT = Op.getSimpleValueType();
11546 // Only AVX2 support 256-bit vector integer extending.
11547 if (!Subtarget->hasInt256() && VT.is256BitVector())
11550 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11552 SDValue V1 = Op.getOperand(0);
11553 SDValue V2 = Op.getOperand(1);
11554 unsigned NumElems = VT.getVectorNumElements();
11556 // Extending is an unary operation and the element type of the source vector
11557 // won't be equal to or larger than i64.
11558 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11559 VT.getVectorElementType() == MVT::i64)
11562 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11563 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11564 while ((1U << Shift) < NumElems) {
11565 if (SVOp->getMaskElt(1U << Shift) == 1)
11568 // The maximal ratio is 8, i.e. from i8 to i64.
11573 // Check the shuffle mask.
11574 unsigned Mask = (1U << Shift) - 1;
11575 for (unsigned i = 0; i != NumElems; ++i) {
11576 int EltIdx = SVOp->getMaskElt(i);
11577 if ((i & Mask) != 0 && EltIdx != -1)
11579 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11583 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11584 MVT NeVT = MVT::getIntegerVT(NBits);
11585 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11587 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11590 return DAG.getNode(ISD::BITCAST, DL, VT,
11591 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11594 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11595 SelectionDAG &DAG) {
11596 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11597 MVT VT = Op.getSimpleValueType();
11599 SDValue V1 = Op.getOperand(0);
11600 SDValue V2 = Op.getOperand(1);
11602 if (isZeroShuffle(SVOp))
11603 return getZeroVector(VT, Subtarget, DAG, dl);
11605 // Handle splat operations
11606 if (SVOp->isSplat()) {
11607 // Use vbroadcast whenever the splat comes from a foldable load
11608 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11609 if (Broadcast.getNode())
11613 // Check integer expanding shuffles.
11614 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11615 if (NewOp.getNode())
11618 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11620 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11621 VT == MVT::v32i8) {
11622 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11623 if (NewOp.getNode())
11624 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11625 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11626 // FIXME: Figure out a cleaner way to do this.
11627 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11628 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11629 if (NewOp.getNode()) {
11630 MVT NewVT = NewOp.getSimpleValueType();
11631 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11632 NewVT, true, false))
11633 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11636 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11637 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11638 if (NewOp.getNode()) {
11639 MVT NewVT = NewOp.getSimpleValueType();
11640 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11641 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11650 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11651 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11652 SDValue V1 = Op.getOperand(0);
11653 SDValue V2 = Op.getOperand(1);
11654 MVT VT = Op.getSimpleValueType();
11656 unsigned NumElems = VT.getVectorNumElements();
11657 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11658 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11659 bool V1IsSplat = false;
11660 bool V2IsSplat = false;
11661 bool HasSSE2 = Subtarget->hasSSE2();
11662 bool HasFp256 = Subtarget->hasFp256();
11663 bool HasInt256 = Subtarget->hasInt256();
11664 MachineFunction &MF = DAG.getMachineFunction();
11665 bool OptForSize = MF.getFunction()->getAttributes().
11666 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11668 // Check if we should use the experimental vector shuffle lowering. If so,
11669 // delegate completely to that code path.
11670 if (ExperimentalVectorShuffleLowering)
11671 return lowerVectorShuffle(Op, Subtarget, DAG);
11673 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11675 if (V1IsUndef && V2IsUndef)
11676 return DAG.getUNDEF(VT);
11678 // When we create a shuffle node we put the UNDEF node to second operand,
11679 // but in some cases the first operand may be transformed to UNDEF.
11680 // In this case we should just commute the node.
11682 return DAG.getCommutedVectorShuffle(*SVOp);
11684 // Vector shuffle lowering takes 3 steps:
11686 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11687 // narrowing and commutation of operands should be handled.
11688 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11690 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11691 // so the shuffle can be broken into other shuffles and the legalizer can
11692 // try the lowering again.
11694 // The general idea is that no vector_shuffle operation should be left to
11695 // be matched during isel, all of them must be converted to a target specific
11698 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11699 // narrowing and commutation of operands should be handled. The actual code
11700 // doesn't include all of those, work in progress...
11701 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11702 if (NewOp.getNode())
11705 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11707 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11708 // unpckh_undef). Only use pshufd if speed is more important than size.
11709 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11710 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11711 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11712 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11714 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11715 V2IsUndef && MayFoldVectorLoad(V1))
11716 return getMOVDDup(Op, dl, V1, DAG);
11718 if (isMOVHLPS_v_undef_Mask(M, VT))
11719 return getMOVHighToLow(Op, dl, DAG);
11721 // Use to match splats
11722 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11723 (VT == MVT::v2f64 || VT == MVT::v2i64))
11724 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11726 if (isPSHUFDMask(M, VT)) {
11727 // The actual implementation will match the mask in the if above and then
11728 // during isel it can match several different instructions, not only pshufd
11729 // as its name says, sad but true, emulate the behavior for now...
11730 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11731 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11733 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11735 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11736 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11738 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11739 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11742 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11746 if (isPALIGNRMask(M, VT, Subtarget))
11747 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11748 getShufflePALIGNRImmediate(SVOp),
11751 if (isVALIGNMask(M, VT, Subtarget))
11752 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11753 getShuffleVALIGNImmediate(SVOp),
11756 // Check if this can be converted into a logical shift.
11757 bool isLeft = false;
11758 unsigned ShAmt = 0;
11760 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11761 if (isShift && ShVal.hasOneUse()) {
11762 // If the shifted value has multiple uses, it may be cheaper to use
11763 // v_set0 + movlhps or movhlps, etc.
11764 MVT EltVT = VT.getVectorElementType();
11765 ShAmt *= EltVT.getSizeInBits();
11766 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11769 if (isMOVLMask(M, VT)) {
11770 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11771 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11772 if (!isMOVLPMask(M, VT)) {
11773 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11774 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11776 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11777 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11781 // FIXME: fold these into legal mask.
11782 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11783 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11785 if (isMOVHLPSMask(M, VT))
11786 return getMOVHighToLow(Op, dl, DAG);
11788 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11789 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11791 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11792 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11794 if (isMOVLPMask(M, VT))
11795 return getMOVLP(Op, dl, DAG, HasSSE2);
11797 if (ShouldXformToMOVHLPS(M, VT) ||
11798 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11799 return DAG.getCommutedVectorShuffle(*SVOp);
11802 // No better options. Use a vshldq / vsrldq.
11803 MVT EltVT = VT.getVectorElementType();
11804 ShAmt *= EltVT.getSizeInBits();
11805 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11808 bool Commuted = false;
11809 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11810 // 1,1,1,1 -> v8i16 though.
11811 BitVector UndefElements;
11812 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11813 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11815 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11816 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11819 // Canonicalize the splat or undef, if present, to be on the RHS.
11820 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11821 CommuteVectorShuffleMask(M, NumElems);
11823 std::swap(V1IsSplat, V2IsSplat);
11827 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11828 // Shuffling low element of v1 into undef, just return v1.
11831 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11832 // the instruction selector will not match, so get a canonical MOVL with
11833 // swapped operands to undo the commute.
11834 return getMOVL(DAG, dl, VT, V2, V1);
11837 if (isUNPCKLMask(M, VT, HasInt256))
11838 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11840 if (isUNPCKHMask(M, VT, HasInt256))
11841 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11844 // Normalize mask so all entries that point to V2 points to its first
11845 // element then try to match unpck{h|l} again. If match, return a
11846 // new vector_shuffle with the corrected mask.p
11847 SmallVector<int, 8> NewMask(M.begin(), M.end());
11848 NormalizeMask(NewMask, NumElems);
11849 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11850 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11851 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11852 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11856 // Commute is back and try unpck* again.
11857 // FIXME: this seems wrong.
11858 CommuteVectorShuffleMask(M, NumElems);
11860 std::swap(V1IsSplat, V2IsSplat);
11862 if (isUNPCKLMask(M, VT, HasInt256))
11863 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11865 if (isUNPCKHMask(M, VT, HasInt256))
11866 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11869 // Normalize the node to match x86 shuffle ops if needed
11870 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11871 return DAG.getCommutedVectorShuffle(*SVOp);
11873 // The checks below are all present in isShuffleMaskLegal, but they are
11874 // inlined here right now to enable us to directly emit target specific
11875 // nodes, and remove one by one until they don't return Op anymore.
11877 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11878 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11879 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11880 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11883 if (isPSHUFHWMask(M, VT, HasInt256))
11884 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11885 getShufflePSHUFHWImmediate(SVOp),
11888 if (isPSHUFLWMask(M, VT, HasInt256))
11889 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11890 getShufflePSHUFLWImmediate(SVOp),
11893 unsigned MaskValue;
11894 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11896 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11898 if (isSHUFPMask(M, VT))
11899 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11900 getShuffleSHUFImmediate(SVOp), DAG);
11902 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11903 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11904 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11905 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11907 //===--------------------------------------------------------------------===//
11908 // Generate target specific nodes for 128 or 256-bit shuffles only
11909 // supported in the AVX instruction set.
11912 // Handle VMOVDDUPY permutations
11913 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11914 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11916 // Handle VPERMILPS/D* permutations
11917 if (isVPERMILPMask(M, VT)) {
11918 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11919 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11920 getShuffleSHUFImmediate(SVOp), DAG);
11921 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11922 getShuffleSHUFImmediate(SVOp), DAG);
11926 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11927 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11928 Idx*(NumElems/2), DAG, dl);
11930 // Handle VPERM2F128/VPERM2I128 permutations
11931 if (isVPERM2X128Mask(M, VT, HasFp256))
11932 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11933 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11935 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11936 return getINSERTPS(SVOp, dl, DAG);
11939 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11940 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11942 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11943 VT.is512BitVector()) {
11944 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11945 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11946 SmallVector<SDValue, 16> permclMask;
11947 for (unsigned i = 0; i != NumElems; ++i) {
11948 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11951 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11953 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11954 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11955 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11956 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11957 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11960 //===--------------------------------------------------------------------===//
11961 // Since no target specific shuffle was selected for this generic one,
11962 // lower it into other known shuffles. FIXME: this isn't true yet, but
11963 // this is the plan.
11966 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11967 if (VT == MVT::v8i16) {
11968 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11969 if (NewOp.getNode())
11973 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11974 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11975 if (NewOp.getNode())
11979 if (VT == MVT::v16i8) {
11980 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11981 if (NewOp.getNode())
11985 if (VT == MVT::v32i8) {
11986 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11987 if (NewOp.getNode())
11991 // Handle all 128-bit wide vectors with 4 elements, and match them with
11992 // several different shuffle types.
11993 if (NumElems == 4 && VT.is128BitVector())
11994 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11996 // Handle general 256-bit shuffles
11997 if (VT.is256BitVector())
11998 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12003 // This function assumes its argument is a BUILD_VECTOR of constants or
12004 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12006 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12007 unsigned &MaskValue) {
12009 unsigned NumElems = BuildVector->getNumOperands();
12010 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12011 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12012 unsigned NumElemsInLane = NumElems / NumLanes;
12014 // Blend for v16i16 should be symetric for the both lanes.
12015 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12016 SDValue EltCond = BuildVector->getOperand(i);
12017 SDValue SndLaneEltCond =
12018 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12020 int Lane1Cond = -1, Lane2Cond = -1;
12021 if (isa<ConstantSDNode>(EltCond))
12022 Lane1Cond = !isZero(EltCond);
12023 if (isa<ConstantSDNode>(SndLaneEltCond))
12024 Lane2Cond = !isZero(SndLaneEltCond);
12026 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12027 // Lane1Cond != 0, means we want the first argument.
12028 // Lane1Cond == 0, means we want the second argument.
12029 // The encoding of this argument is 0 for the first argument, 1
12030 // for the second. Therefore, invert the condition.
12031 MaskValue |= !Lane1Cond << i;
12032 else if (Lane1Cond < 0)
12033 MaskValue |= !Lane2Cond << i;
12040 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12042 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12043 SelectionDAG &DAG) {
12044 SDValue Cond = Op.getOperand(0);
12045 SDValue LHS = Op.getOperand(1);
12046 SDValue RHS = Op.getOperand(2);
12048 MVT VT = Op.getSimpleValueType();
12049 MVT EltVT = VT.getVectorElementType();
12050 unsigned NumElems = VT.getVectorNumElements();
12052 // There is no blend with immediate in AVX-512.
12053 if (VT.is512BitVector())
12056 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12058 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12061 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12064 // Check the mask for BLEND and build the value.
12065 unsigned MaskValue = 0;
12066 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12069 // Convert i32 vectors to floating point if it is not AVX2.
12070 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12072 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12073 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12075 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12076 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12079 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12080 DAG.getConstant(MaskValue, MVT::i32));
12081 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12084 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12085 // A vselect where all conditions and data are constants can be optimized into
12086 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12087 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12088 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12089 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12092 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12093 if (BlendOp.getNode())
12096 // Some types for vselect were previously set to Expand, not Legal or
12097 // Custom. Return an empty SDValue so we fall-through to Expand, after
12098 // the Custom lowering phase.
12099 MVT VT = Op.getSimpleValueType();
12100 switch (VT.SimpleTy) {
12105 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12110 // We couldn't create a "Blend with immediate" node.
12111 // This node should still be legal, but we'll have to emit a blendv*
12116 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12117 MVT VT = Op.getSimpleValueType();
12120 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12123 if (VT.getSizeInBits() == 8) {
12124 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12125 Op.getOperand(0), Op.getOperand(1));
12126 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12127 DAG.getValueType(VT));
12128 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12131 if (VT.getSizeInBits() == 16) {
12132 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12133 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12135 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12136 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12137 DAG.getNode(ISD::BITCAST, dl,
12140 Op.getOperand(1)));
12141 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12142 Op.getOperand(0), Op.getOperand(1));
12143 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12144 DAG.getValueType(VT));
12145 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12148 if (VT == MVT::f32) {
12149 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12150 // the result back to FR32 register. It's only worth matching if the
12151 // result has a single use which is a store or a bitcast to i32. And in
12152 // the case of a store, it's not worth it if the index is a constant 0,
12153 // because a MOVSSmr can be used instead, which is smaller and faster.
12154 if (!Op.hasOneUse())
12156 SDNode *User = *Op.getNode()->use_begin();
12157 if ((User->getOpcode() != ISD::STORE ||
12158 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12159 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12160 (User->getOpcode() != ISD::BITCAST ||
12161 User->getValueType(0) != MVT::i32))
12163 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12164 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12167 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12170 if (VT == MVT::i32 || VT == MVT::i64) {
12171 // ExtractPS/pextrq works with constant index.
12172 if (isa<ConstantSDNode>(Op.getOperand(1)))
12178 /// Extract one bit from mask vector, like v16i1 or v8i1.
12179 /// AVX-512 feature.
12181 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12182 SDValue Vec = Op.getOperand(0);
12184 MVT VecVT = Vec.getSimpleValueType();
12185 SDValue Idx = Op.getOperand(1);
12186 MVT EltVT = Op.getSimpleValueType();
12188 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12190 // variable index can't be handled in mask registers,
12191 // extend vector to VR512
12192 if (!isa<ConstantSDNode>(Idx)) {
12193 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12194 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12195 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12196 ExtVT.getVectorElementType(), Ext, Idx);
12197 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12200 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12201 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12202 unsigned MaxSift = rc->getSize()*8 - 1;
12203 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12204 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12205 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12206 DAG.getConstant(MaxSift, MVT::i8));
12207 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12208 DAG.getIntPtrConstant(0));
12212 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12213 SelectionDAG &DAG) const {
12215 SDValue Vec = Op.getOperand(0);
12216 MVT VecVT = Vec.getSimpleValueType();
12217 SDValue Idx = Op.getOperand(1);
12219 if (Op.getSimpleValueType() == MVT::i1)
12220 return ExtractBitFromMaskVector(Op, DAG);
12222 if (!isa<ConstantSDNode>(Idx)) {
12223 if (VecVT.is512BitVector() ||
12224 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12225 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12228 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12229 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12230 MaskEltVT.getSizeInBits());
12232 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12233 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12234 getZeroVector(MaskVT, Subtarget, DAG, dl),
12235 Idx, DAG.getConstant(0, getPointerTy()));
12236 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12237 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12238 Perm, DAG.getConstant(0, getPointerTy()));
12243 // If this is a 256-bit vector result, first extract the 128-bit vector and
12244 // then extract the element from the 128-bit vector.
12245 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12247 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12248 // Get the 128-bit vector.
12249 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12250 MVT EltVT = VecVT.getVectorElementType();
12252 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12254 //if (IdxVal >= NumElems/2)
12255 // IdxVal -= NumElems/2;
12256 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12257 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12258 DAG.getConstant(IdxVal, MVT::i32));
12261 assert(VecVT.is128BitVector() && "Unexpected vector length");
12263 if (Subtarget->hasSSE41()) {
12264 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12269 MVT VT = Op.getSimpleValueType();
12270 // TODO: handle v16i8.
12271 if (VT.getSizeInBits() == 16) {
12272 SDValue Vec = Op.getOperand(0);
12273 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12275 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12276 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12277 DAG.getNode(ISD::BITCAST, dl,
12279 Op.getOperand(1)));
12280 // Transform it so it match pextrw which produces a 32-bit result.
12281 MVT EltVT = MVT::i32;
12282 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12283 Op.getOperand(0), Op.getOperand(1));
12284 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12285 DAG.getValueType(VT));
12286 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12289 if (VT.getSizeInBits() == 32) {
12290 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12294 // SHUFPS the element to the lowest double word, then movss.
12295 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12296 MVT VVT = Op.getOperand(0).getSimpleValueType();
12297 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12298 DAG.getUNDEF(VVT), Mask);
12299 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12300 DAG.getIntPtrConstant(0));
12303 if (VT.getSizeInBits() == 64) {
12304 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12305 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12306 // to match extract_elt for f64.
12307 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12311 // UNPCKHPD the element to the lowest double word, then movsd.
12312 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12313 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12314 int Mask[2] = { 1, -1 };
12315 MVT VVT = Op.getOperand(0).getSimpleValueType();
12316 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12317 DAG.getUNDEF(VVT), Mask);
12318 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12319 DAG.getIntPtrConstant(0));
12325 /// Insert one bit to mask vector, like v16i1 or v8i1.
12326 /// AVX-512 feature.
12328 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12330 SDValue Vec = Op.getOperand(0);
12331 SDValue Elt = Op.getOperand(1);
12332 SDValue Idx = Op.getOperand(2);
12333 MVT VecVT = Vec.getSimpleValueType();
12335 if (!isa<ConstantSDNode>(Idx)) {
12336 // Non constant index. Extend source and destination,
12337 // insert element and then truncate the result.
12338 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12339 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12340 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12341 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12342 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12343 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12346 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12347 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12348 if (Vec.getOpcode() == ISD::UNDEF)
12349 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12350 DAG.getConstant(IdxVal, MVT::i8));
12351 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12352 unsigned MaxSift = rc->getSize()*8 - 1;
12353 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12354 DAG.getConstant(MaxSift, MVT::i8));
12355 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12356 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12357 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12360 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12361 SelectionDAG &DAG) const {
12362 MVT VT = Op.getSimpleValueType();
12363 MVT EltVT = VT.getVectorElementType();
12365 if (EltVT == MVT::i1)
12366 return InsertBitToMaskVector(Op, DAG);
12369 SDValue N0 = Op.getOperand(0);
12370 SDValue N1 = Op.getOperand(1);
12371 SDValue N2 = Op.getOperand(2);
12372 if (!isa<ConstantSDNode>(N2))
12374 auto *N2C = cast<ConstantSDNode>(N2);
12375 unsigned IdxVal = N2C->getZExtValue();
12377 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12378 // into that, and then insert the subvector back into the result.
12379 if (VT.is256BitVector() || VT.is512BitVector()) {
12380 // Get the desired 128-bit vector half.
12381 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12383 // Insert the element into the desired half.
12384 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12385 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12387 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12388 DAG.getConstant(IdxIn128, MVT::i32));
12390 // Insert the changed part back to the 256-bit vector
12391 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12393 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12395 if (Subtarget->hasSSE41()) {
12396 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12398 if (VT == MVT::v8i16) {
12399 Opc = X86ISD::PINSRW;
12401 assert(VT == MVT::v16i8);
12402 Opc = X86ISD::PINSRB;
12405 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12407 if (N1.getValueType() != MVT::i32)
12408 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12409 if (N2.getValueType() != MVT::i32)
12410 N2 = DAG.getIntPtrConstant(IdxVal);
12411 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12414 if (EltVT == MVT::f32) {
12415 // Bits [7:6] of the constant are the source select. This will always be
12416 // zero here. The DAG Combiner may combine an extract_elt index into
12418 // bits. For example (insert (extract, 3), 2) could be matched by
12420 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12421 // Bits [5:4] of the constant are the destination select. This is the
12422 // value of the incoming immediate.
12423 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12424 // combine either bitwise AND or insert of float 0.0 to set these bits.
12425 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12426 // Create this as a scalar to vector..
12427 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12428 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12431 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12432 // PINSR* works with constant index.
12437 if (EltVT == MVT::i8)
12440 if (EltVT.getSizeInBits() == 16) {
12441 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12442 // as its second argument.
12443 if (N1.getValueType() != MVT::i32)
12444 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12445 if (N2.getValueType() != MVT::i32)
12446 N2 = DAG.getIntPtrConstant(IdxVal);
12447 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12452 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12454 MVT OpVT = Op.getSimpleValueType();
12456 // If this is a 256-bit vector result, first insert into a 128-bit
12457 // vector and then insert into the 256-bit vector.
12458 if (!OpVT.is128BitVector()) {
12459 // Insert into a 128-bit vector.
12460 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12461 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12462 OpVT.getVectorNumElements() / SizeFactor);
12464 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12466 // Insert the 128-bit vector.
12467 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12470 if (OpVT == MVT::v1i64 &&
12471 Op.getOperand(0).getValueType() == MVT::i64)
12472 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12474 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12475 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12476 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12477 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12480 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12481 // a simple subregister reference or explicit instructions to grab
12482 // upper bits of a vector.
12483 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12484 SelectionDAG &DAG) {
12486 SDValue In = Op.getOperand(0);
12487 SDValue Idx = Op.getOperand(1);
12488 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12489 MVT ResVT = Op.getSimpleValueType();
12490 MVT InVT = In.getSimpleValueType();
12492 if (Subtarget->hasFp256()) {
12493 if (ResVT.is128BitVector() &&
12494 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12495 isa<ConstantSDNode>(Idx)) {
12496 return Extract128BitVector(In, IdxVal, DAG, dl);
12498 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12499 isa<ConstantSDNode>(Idx)) {
12500 return Extract256BitVector(In, IdxVal, DAG, dl);
12506 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12507 // simple superregister reference or explicit instructions to insert
12508 // the upper bits of a vector.
12509 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12510 SelectionDAG &DAG) {
12511 if (Subtarget->hasFp256()) {
12512 SDLoc dl(Op.getNode());
12513 SDValue Vec = Op.getNode()->getOperand(0);
12514 SDValue SubVec = Op.getNode()->getOperand(1);
12515 SDValue Idx = Op.getNode()->getOperand(2);
12517 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12518 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12519 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12520 isa<ConstantSDNode>(Idx)) {
12521 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12522 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12525 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12526 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12527 isa<ConstantSDNode>(Idx)) {
12528 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12529 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12535 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12536 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12537 // one of the above mentioned nodes. It has to be wrapped because otherwise
12538 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12539 // be used to form addressing mode. These wrapped nodes will be selected
12542 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12543 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12545 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12546 // global base reg.
12547 unsigned char OpFlag = 0;
12548 unsigned WrapperKind = X86ISD::Wrapper;
12549 CodeModel::Model M = DAG.getTarget().getCodeModel();
12551 if (Subtarget->isPICStyleRIPRel() &&
12552 (M == CodeModel::Small || M == CodeModel::Kernel))
12553 WrapperKind = X86ISD::WrapperRIP;
12554 else if (Subtarget->isPICStyleGOT())
12555 OpFlag = X86II::MO_GOTOFF;
12556 else if (Subtarget->isPICStyleStubPIC())
12557 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12559 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12560 CP->getAlignment(),
12561 CP->getOffset(), OpFlag);
12563 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12564 // With PIC, the address is actually $g + Offset.
12566 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12567 DAG.getNode(X86ISD::GlobalBaseReg,
12568 SDLoc(), getPointerTy()),
12575 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12576 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12578 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12579 // global base reg.
12580 unsigned char OpFlag = 0;
12581 unsigned WrapperKind = X86ISD::Wrapper;
12582 CodeModel::Model M = DAG.getTarget().getCodeModel();
12584 if (Subtarget->isPICStyleRIPRel() &&
12585 (M == CodeModel::Small || M == CodeModel::Kernel))
12586 WrapperKind = X86ISD::WrapperRIP;
12587 else if (Subtarget->isPICStyleGOT())
12588 OpFlag = X86II::MO_GOTOFF;
12589 else if (Subtarget->isPICStyleStubPIC())
12590 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12592 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12595 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12597 // With PIC, the address is actually $g + Offset.
12599 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12600 DAG.getNode(X86ISD::GlobalBaseReg,
12601 SDLoc(), getPointerTy()),
12608 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12609 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12611 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12612 // global base reg.
12613 unsigned char OpFlag = 0;
12614 unsigned WrapperKind = X86ISD::Wrapper;
12615 CodeModel::Model M = DAG.getTarget().getCodeModel();
12617 if (Subtarget->isPICStyleRIPRel() &&
12618 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12619 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12620 OpFlag = X86II::MO_GOTPCREL;
12621 WrapperKind = X86ISD::WrapperRIP;
12622 } else if (Subtarget->isPICStyleGOT()) {
12623 OpFlag = X86II::MO_GOT;
12624 } else if (Subtarget->isPICStyleStubPIC()) {
12625 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12626 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12627 OpFlag = X86II::MO_DARWIN_NONLAZY;
12630 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12633 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12635 // With PIC, the address is actually $g + Offset.
12636 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12637 !Subtarget->is64Bit()) {
12638 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12639 DAG.getNode(X86ISD::GlobalBaseReg,
12640 SDLoc(), getPointerTy()),
12644 // For symbols that require a load from a stub to get the address, emit the
12646 if (isGlobalStubReference(OpFlag))
12647 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12648 MachinePointerInfo::getGOT(), false, false, false, 0);
12654 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12655 // Create the TargetBlockAddressAddress node.
12656 unsigned char OpFlags =
12657 Subtarget->ClassifyBlockAddressReference();
12658 CodeModel::Model M = DAG.getTarget().getCodeModel();
12659 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12660 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12662 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12665 if (Subtarget->isPICStyleRIPRel() &&
12666 (M == CodeModel::Small || M == CodeModel::Kernel))
12667 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12669 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12671 // With PIC, the address is actually $g + Offset.
12672 if (isGlobalRelativeToPICBase(OpFlags)) {
12673 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12674 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12682 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12683 int64_t Offset, SelectionDAG &DAG) const {
12684 // Create the TargetGlobalAddress node, folding in the constant
12685 // offset if it is legal.
12686 unsigned char OpFlags =
12687 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12688 CodeModel::Model M = DAG.getTarget().getCodeModel();
12690 if (OpFlags == X86II::MO_NO_FLAG &&
12691 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12692 // A direct static reference to a global.
12693 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12696 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12699 if (Subtarget->isPICStyleRIPRel() &&
12700 (M == CodeModel::Small || M == CodeModel::Kernel))
12701 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12703 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12705 // With PIC, the address is actually $g + Offset.
12706 if (isGlobalRelativeToPICBase(OpFlags)) {
12707 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12708 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12712 // For globals that require a load from a stub to get the address, emit the
12714 if (isGlobalStubReference(OpFlags))
12715 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12716 MachinePointerInfo::getGOT(), false, false, false, 0);
12718 // If there was a non-zero offset that we didn't fold, create an explicit
12719 // addition for it.
12721 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12722 DAG.getConstant(Offset, getPointerTy()));
12728 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12729 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12730 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12731 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12735 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12736 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12737 unsigned char OperandFlags, bool LocalDynamic = false) {
12738 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12739 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12741 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12742 GA->getValueType(0),
12746 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12750 SDValue Ops[] = { Chain, TGA, *InFlag };
12751 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12753 SDValue Ops[] = { Chain, TGA };
12754 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12757 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12758 MFI->setAdjustsStack(true);
12760 SDValue Flag = Chain.getValue(1);
12761 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12764 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12766 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12769 SDLoc dl(GA); // ? function entry point might be better
12770 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12771 DAG.getNode(X86ISD::GlobalBaseReg,
12772 SDLoc(), PtrVT), InFlag);
12773 InFlag = Chain.getValue(1);
12775 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12778 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12780 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12782 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12783 X86::RAX, X86II::MO_TLSGD);
12786 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12792 // Get the start address of the TLS block for this module.
12793 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12794 .getInfo<X86MachineFunctionInfo>();
12795 MFI->incNumLocalDynamicTLSAccesses();
12799 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12800 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12803 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12804 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12805 InFlag = Chain.getValue(1);
12806 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12807 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12810 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12814 unsigned char OperandFlags = X86II::MO_DTPOFF;
12815 unsigned WrapperKind = X86ISD::Wrapper;
12816 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12817 GA->getValueType(0),
12818 GA->getOffset(), OperandFlags);
12819 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12821 // Add x@dtpoff with the base.
12822 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12825 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12826 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12827 const EVT PtrVT, TLSModel::Model model,
12828 bool is64Bit, bool isPIC) {
12831 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12832 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12833 is64Bit ? 257 : 256));
12835 SDValue ThreadPointer =
12836 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12837 MachinePointerInfo(Ptr), false, false, false, 0);
12839 unsigned char OperandFlags = 0;
12840 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12842 unsigned WrapperKind = X86ISD::Wrapper;
12843 if (model == TLSModel::LocalExec) {
12844 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12845 } else if (model == TLSModel::InitialExec) {
12847 OperandFlags = X86II::MO_GOTTPOFF;
12848 WrapperKind = X86ISD::WrapperRIP;
12850 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12853 llvm_unreachable("Unexpected model");
12856 // emit "addl x@ntpoff,%eax" (local exec)
12857 // or "addl x@indntpoff,%eax" (initial exec)
12858 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12860 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12861 GA->getOffset(), OperandFlags);
12862 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12864 if (model == TLSModel::InitialExec) {
12865 if (isPIC && !is64Bit) {
12866 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12867 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12871 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12872 MachinePointerInfo::getGOT(), false, false, false, 0);
12875 // The address of the thread local variable is the add of the thread
12876 // pointer with the offset of the variable.
12877 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12881 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12883 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12884 const GlobalValue *GV = GA->getGlobal();
12886 if (Subtarget->isTargetELF()) {
12887 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12890 case TLSModel::GeneralDynamic:
12891 if (Subtarget->is64Bit())
12892 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12893 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12894 case TLSModel::LocalDynamic:
12895 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12896 Subtarget->is64Bit());
12897 case TLSModel::InitialExec:
12898 case TLSModel::LocalExec:
12899 return LowerToTLSExecModel(
12900 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12901 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12903 llvm_unreachable("Unknown TLS model.");
12906 if (Subtarget->isTargetDarwin()) {
12907 // Darwin only has one model of TLS. Lower to that.
12908 unsigned char OpFlag = 0;
12909 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12910 X86ISD::WrapperRIP : X86ISD::Wrapper;
12912 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12913 // global base reg.
12914 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12915 !Subtarget->is64Bit();
12917 OpFlag = X86II::MO_TLVP_PIC_BASE;
12919 OpFlag = X86II::MO_TLVP;
12921 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12922 GA->getValueType(0),
12923 GA->getOffset(), OpFlag);
12924 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12926 // With PIC32, the address is actually $g + Offset.
12928 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12929 DAG.getNode(X86ISD::GlobalBaseReg,
12930 SDLoc(), getPointerTy()),
12933 // Lowering the machine isd will make sure everything is in the right
12935 SDValue Chain = DAG.getEntryNode();
12936 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12937 SDValue Args[] = { Chain, Offset };
12938 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12940 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12941 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12942 MFI->setAdjustsStack(true);
12944 // And our return value (tls address) is in the standard call return value
12946 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12947 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12948 Chain.getValue(1));
12951 if (Subtarget->isTargetKnownWindowsMSVC() ||
12952 Subtarget->isTargetWindowsGNU()) {
12953 // Just use the implicit TLS architecture
12954 // Need to generate someting similar to:
12955 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12957 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12958 // mov rcx, qword [rdx+rcx*8]
12959 // mov eax, .tls$:tlsvar
12960 // [rax+rcx] contains the address
12961 // Windows 64bit: gs:0x58
12962 // Windows 32bit: fs:__tls_array
12965 SDValue Chain = DAG.getEntryNode();
12967 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12968 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12969 // use its literal value of 0x2C.
12970 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12971 ? Type::getInt8PtrTy(*DAG.getContext(),
12973 : Type::getInt32PtrTy(*DAG.getContext(),
12977 Subtarget->is64Bit()
12978 ? DAG.getIntPtrConstant(0x58)
12979 : (Subtarget->isTargetWindowsGNU()
12980 ? DAG.getIntPtrConstant(0x2C)
12981 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12983 SDValue ThreadPointer =
12984 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12985 MachinePointerInfo(Ptr), false, false, false, 0);
12987 // Load the _tls_index variable
12988 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12989 if (Subtarget->is64Bit())
12990 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12991 IDX, MachinePointerInfo(), MVT::i32,
12992 false, false, false, 0);
12994 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12995 false, false, false, 0);
12997 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12999 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13001 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13002 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13003 false, false, false, 0);
13005 // Get the offset of start of .tls section
13006 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13007 GA->getValueType(0),
13008 GA->getOffset(), X86II::MO_SECREL);
13009 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13011 // The address of the thread local variable is the add of the thread
13012 // pointer with the offset of the variable.
13013 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13016 llvm_unreachable("TLS not implemented for this target.");
13019 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13020 /// and take a 2 x i32 value to shift plus a shift amount.
13021 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13022 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13023 MVT VT = Op.getSimpleValueType();
13024 unsigned VTBits = VT.getSizeInBits();
13026 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13027 SDValue ShOpLo = Op.getOperand(0);
13028 SDValue ShOpHi = Op.getOperand(1);
13029 SDValue ShAmt = Op.getOperand(2);
13030 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13031 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13033 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13034 DAG.getConstant(VTBits - 1, MVT::i8));
13035 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13036 DAG.getConstant(VTBits - 1, MVT::i8))
13037 : DAG.getConstant(0, VT);
13039 SDValue Tmp2, Tmp3;
13040 if (Op.getOpcode() == ISD::SHL_PARTS) {
13041 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13042 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13044 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13045 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13048 // If the shift amount is larger or equal than the width of a part we can't
13049 // rely on the results of shld/shrd. Insert a test and select the appropriate
13050 // values for large shift amounts.
13051 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13052 DAG.getConstant(VTBits, MVT::i8));
13053 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13054 AndNode, DAG.getConstant(0, MVT::i8));
13057 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13058 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13059 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13061 if (Op.getOpcode() == ISD::SHL_PARTS) {
13062 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13063 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13065 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13066 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13069 SDValue Ops[2] = { Lo, Hi };
13070 return DAG.getMergeValues(Ops, dl);
13073 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13074 SelectionDAG &DAG) const {
13075 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13077 if (SrcVT.isVector())
13080 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13081 "Unknown SINT_TO_FP to lower!");
13083 // These are really Legal; return the operand so the caller accepts it as
13085 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13087 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13088 Subtarget->is64Bit()) {
13093 unsigned Size = SrcVT.getSizeInBits()/8;
13094 MachineFunction &MF = DAG.getMachineFunction();
13095 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13096 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13097 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13099 MachinePointerInfo::getFixedStack(SSFI),
13101 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13104 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13106 SelectionDAG &DAG) const {
13110 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13112 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13114 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13116 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13118 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13119 MachineMemOperand *MMO;
13121 int SSFI = FI->getIndex();
13123 DAG.getMachineFunction()
13124 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13125 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13127 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13128 StackSlot = StackSlot.getOperand(1);
13130 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13131 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13133 Tys, Ops, SrcVT, MMO);
13136 Chain = Result.getValue(1);
13137 SDValue InFlag = Result.getValue(2);
13139 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13140 // shouldn't be necessary except that RFP cannot be live across
13141 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13142 MachineFunction &MF = DAG.getMachineFunction();
13143 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13144 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13145 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13146 Tys = DAG.getVTList(MVT::Other);
13148 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13150 MachineMemOperand *MMO =
13151 DAG.getMachineFunction()
13152 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13153 MachineMemOperand::MOStore, SSFISize, SSFISize);
13155 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13156 Ops, Op.getValueType(), MMO);
13157 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13158 MachinePointerInfo::getFixedStack(SSFI),
13159 false, false, false, 0);
13165 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13166 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13167 SelectionDAG &DAG) const {
13168 // This algorithm is not obvious. Here it is what we're trying to output:
13171 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13172 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13174 haddpd %xmm0, %xmm0
13176 pshufd $0x4e, %xmm0, %xmm1
13182 LLVMContext *Context = DAG.getContext();
13184 // Build some magic constants.
13185 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13186 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13187 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13189 SmallVector<Constant*,2> CV1;
13191 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13192 APInt(64, 0x4330000000000000ULL))));
13194 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13195 APInt(64, 0x4530000000000000ULL))));
13196 Constant *C1 = ConstantVector::get(CV1);
13197 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13199 // Load the 64-bit value into an XMM register.
13200 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13202 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13203 MachinePointerInfo::getConstantPool(),
13204 false, false, false, 16);
13205 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13206 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13209 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13210 MachinePointerInfo::getConstantPool(),
13211 false, false, false, 16);
13212 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13213 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13216 if (Subtarget->hasSSE3()) {
13217 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13218 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13220 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13221 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13223 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13224 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13228 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13229 DAG.getIntPtrConstant(0));
13232 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13233 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13234 SelectionDAG &DAG) const {
13236 // FP constant to bias correct the final result.
13237 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13240 // Load the 32-bit value into an XMM register.
13241 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13244 // Zero out the upper parts of the register.
13245 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13247 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13248 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13249 DAG.getIntPtrConstant(0));
13251 // Or the load with the bias.
13252 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13253 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13254 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13255 MVT::v2f64, Load)),
13256 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13257 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13258 MVT::v2f64, Bias)));
13259 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13260 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13261 DAG.getIntPtrConstant(0));
13263 // Subtract the bias.
13264 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13266 // Handle final rounding.
13267 EVT DestVT = Op.getValueType();
13269 if (DestVT.bitsLT(MVT::f64))
13270 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13271 DAG.getIntPtrConstant(0));
13272 if (DestVT.bitsGT(MVT::f64))
13273 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13275 // Handle final rounding.
13279 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13280 SelectionDAG &DAG) const {
13281 SDValue N0 = Op.getOperand(0);
13282 MVT SVT = N0.getSimpleValueType();
13285 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
13286 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
13287 "Custom UINT_TO_FP is not supported!");
13289 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13290 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13291 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13294 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13295 SelectionDAG &DAG) const {
13296 SDValue N0 = Op.getOperand(0);
13299 if (Op.getValueType().isVector())
13300 return lowerUINT_TO_FP_vec(Op, DAG);
13302 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13303 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13304 // the optimization here.
13305 if (DAG.SignBitIsZero(N0))
13306 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13308 MVT SrcVT = N0.getSimpleValueType();
13309 MVT DstVT = Op.getSimpleValueType();
13310 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13311 return LowerUINT_TO_FP_i64(Op, DAG);
13312 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13313 return LowerUINT_TO_FP_i32(Op, DAG);
13314 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13317 // Make a 64-bit buffer, and use it to build an FILD.
13318 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13319 if (SrcVT == MVT::i32) {
13320 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13321 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13322 getPointerTy(), StackSlot, WordOff);
13323 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13324 StackSlot, MachinePointerInfo(),
13326 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13327 OffsetSlot, MachinePointerInfo(),
13329 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13333 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13334 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13335 StackSlot, MachinePointerInfo(),
13337 // For i64 source, we need to add the appropriate power of 2 if the input
13338 // was negative. This is the same as the optimization in
13339 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13340 // we must be careful to do the computation in x87 extended precision, not
13341 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13342 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13343 MachineMemOperand *MMO =
13344 DAG.getMachineFunction()
13345 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13346 MachineMemOperand::MOLoad, 8, 8);
13348 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13349 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13350 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13353 APInt FF(32, 0x5F800000ULL);
13355 // Check whether the sign bit is set.
13356 SDValue SignSet = DAG.getSetCC(dl,
13357 getSetCCResultType(*DAG.getContext(), MVT::i64),
13358 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13361 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13362 SDValue FudgePtr = DAG.getConstantPool(
13363 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13366 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13367 SDValue Zero = DAG.getIntPtrConstant(0);
13368 SDValue Four = DAG.getIntPtrConstant(4);
13369 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13371 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13373 // Load the value out, extending it from f32 to f80.
13374 // FIXME: Avoid the extend by constructing the right constant pool?
13375 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13376 FudgePtr, MachinePointerInfo::getConstantPool(),
13377 MVT::f32, false, false, false, 4);
13378 // Extend everything to 80 bits to force it to be done on x87.
13379 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13380 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13383 std::pair<SDValue,SDValue>
13384 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13385 bool IsSigned, bool IsReplace) const {
13388 EVT DstTy = Op.getValueType();
13390 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13391 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13395 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13396 DstTy.getSimpleVT() >= MVT::i16 &&
13397 "Unknown FP_TO_INT to lower!");
13399 // These are really Legal.
13400 if (DstTy == MVT::i32 &&
13401 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13402 return std::make_pair(SDValue(), SDValue());
13403 if (Subtarget->is64Bit() &&
13404 DstTy == MVT::i64 &&
13405 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13406 return std::make_pair(SDValue(), SDValue());
13408 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13409 // stack slot, or into the FTOL runtime function.
13410 MachineFunction &MF = DAG.getMachineFunction();
13411 unsigned MemSize = DstTy.getSizeInBits()/8;
13412 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13413 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13416 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13417 Opc = X86ISD::WIN_FTOL;
13419 switch (DstTy.getSimpleVT().SimpleTy) {
13420 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13421 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13422 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13423 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13426 SDValue Chain = DAG.getEntryNode();
13427 SDValue Value = Op.getOperand(0);
13428 EVT TheVT = Op.getOperand(0).getValueType();
13429 // FIXME This causes a redundant load/store if the SSE-class value is already
13430 // in memory, such as if it is on the callstack.
13431 if (isScalarFPTypeInSSEReg(TheVT)) {
13432 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13433 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13434 MachinePointerInfo::getFixedStack(SSFI),
13436 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13438 Chain, StackSlot, DAG.getValueType(TheVT)
13441 MachineMemOperand *MMO =
13442 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13443 MachineMemOperand::MOLoad, MemSize, MemSize);
13444 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13445 Chain = Value.getValue(1);
13446 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13447 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13450 MachineMemOperand *MMO =
13451 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13452 MachineMemOperand::MOStore, MemSize, MemSize);
13454 if (Opc != X86ISD::WIN_FTOL) {
13455 // Build the FP_TO_INT*_IN_MEM
13456 SDValue Ops[] = { Chain, Value, StackSlot };
13457 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13459 return std::make_pair(FIST, StackSlot);
13461 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13462 DAG.getVTList(MVT::Other, MVT::Glue),
13464 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13465 MVT::i32, ftol.getValue(1));
13466 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13467 MVT::i32, eax.getValue(2));
13468 SDValue Ops[] = { eax, edx };
13469 SDValue pair = IsReplace
13470 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13471 : DAG.getMergeValues(Ops, DL);
13472 return std::make_pair(pair, SDValue());
13476 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13477 const X86Subtarget *Subtarget) {
13478 MVT VT = Op->getSimpleValueType(0);
13479 SDValue In = Op->getOperand(0);
13480 MVT InVT = In.getSimpleValueType();
13483 // Optimize vectors in AVX mode:
13486 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13487 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13488 // Concat upper and lower parts.
13491 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13492 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13493 // Concat upper and lower parts.
13496 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13497 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13498 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13501 if (Subtarget->hasInt256())
13502 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13504 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13505 SDValue Undef = DAG.getUNDEF(InVT);
13506 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13507 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13508 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13510 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13511 VT.getVectorNumElements()/2);
13513 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13514 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13516 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13519 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13520 SelectionDAG &DAG) {
13521 MVT VT = Op->getSimpleValueType(0);
13522 SDValue In = Op->getOperand(0);
13523 MVT InVT = In.getSimpleValueType();
13525 unsigned int NumElts = VT.getVectorNumElements();
13526 if (NumElts != 8 && NumElts != 16)
13529 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13530 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13532 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13533 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13534 // Now we have only mask extension
13535 assert(InVT.getVectorElementType() == MVT::i1);
13536 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13537 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13538 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13539 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13540 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13541 MachinePointerInfo::getConstantPool(),
13542 false, false, false, Alignment);
13544 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13545 if (VT.is512BitVector())
13547 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13550 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13551 SelectionDAG &DAG) {
13552 if (Subtarget->hasFp256()) {
13553 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13561 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13562 SelectionDAG &DAG) {
13564 MVT VT = Op.getSimpleValueType();
13565 SDValue In = Op.getOperand(0);
13566 MVT SVT = In.getSimpleValueType();
13568 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13569 return LowerZERO_EXTEND_AVX512(Op, DAG);
13571 if (Subtarget->hasFp256()) {
13572 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13577 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13578 VT.getVectorNumElements() != SVT.getVectorNumElements());
13582 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13584 MVT VT = Op.getSimpleValueType();
13585 SDValue In = Op.getOperand(0);
13586 MVT InVT = In.getSimpleValueType();
13588 if (VT == MVT::i1) {
13589 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13590 "Invalid scalar TRUNCATE operation");
13591 if (InVT.getSizeInBits() >= 32)
13593 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13594 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13596 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13597 "Invalid TRUNCATE operation");
13599 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13600 if (VT.getVectorElementType().getSizeInBits() >=8)
13601 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13603 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13604 unsigned NumElts = InVT.getVectorNumElements();
13605 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13606 if (InVT.getSizeInBits() < 512) {
13607 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13608 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13612 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13613 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13614 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13615 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13616 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13617 MachinePointerInfo::getConstantPool(),
13618 false, false, false, Alignment);
13619 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13620 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13621 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13624 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13625 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13626 if (Subtarget->hasInt256()) {
13627 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13628 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13629 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13631 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13632 DAG.getIntPtrConstant(0));
13635 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13636 DAG.getIntPtrConstant(0));
13637 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13638 DAG.getIntPtrConstant(2));
13639 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13640 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13641 static const int ShufMask[] = {0, 2, 4, 6};
13642 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13645 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13646 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13647 if (Subtarget->hasInt256()) {
13648 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13650 SmallVector<SDValue,32> pshufbMask;
13651 for (unsigned i = 0; i < 2; ++i) {
13652 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13653 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13654 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13655 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13656 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13657 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13658 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13659 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13660 for (unsigned j = 0; j < 8; ++j)
13661 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13663 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13664 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13665 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13667 static const int ShufMask[] = {0, 2, -1, -1};
13668 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13670 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13671 DAG.getIntPtrConstant(0));
13672 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13675 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13676 DAG.getIntPtrConstant(0));
13678 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13679 DAG.getIntPtrConstant(4));
13681 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13682 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13684 // The PSHUFB mask:
13685 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13686 -1, -1, -1, -1, -1, -1, -1, -1};
13688 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13689 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13690 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13692 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13693 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13695 // The MOVLHPS Mask:
13696 static const int ShufMask2[] = {0, 1, 4, 5};
13697 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13698 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13701 // Handle truncation of V256 to V128 using shuffles.
13702 if (!VT.is128BitVector() || !InVT.is256BitVector())
13705 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13707 unsigned NumElems = VT.getVectorNumElements();
13708 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13710 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13711 // Prepare truncation shuffle mask
13712 for (unsigned i = 0; i != NumElems; ++i)
13713 MaskVec[i] = i * 2;
13714 SDValue V = DAG.getVectorShuffle(NVT, DL,
13715 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13716 DAG.getUNDEF(NVT), &MaskVec[0]);
13717 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13718 DAG.getIntPtrConstant(0));
13721 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13722 SelectionDAG &DAG) const {
13723 assert(!Op.getSimpleValueType().isVector());
13725 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13726 /*IsSigned=*/ true, /*IsReplace=*/ false);
13727 SDValue FIST = Vals.first, StackSlot = Vals.second;
13728 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13729 if (!FIST.getNode()) return Op;
13731 if (StackSlot.getNode())
13732 // Load the result.
13733 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13734 FIST, StackSlot, MachinePointerInfo(),
13735 false, false, false, 0);
13737 // The node is the result.
13741 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13742 SelectionDAG &DAG) const {
13743 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13744 /*IsSigned=*/ false, /*IsReplace=*/ false);
13745 SDValue FIST = Vals.first, StackSlot = Vals.second;
13746 assert(FIST.getNode() && "Unexpected failure");
13748 if (StackSlot.getNode())
13749 // Load the result.
13750 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13751 FIST, StackSlot, MachinePointerInfo(),
13752 false, false, false, 0);
13754 // The node is the result.
13758 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13760 MVT VT = Op.getSimpleValueType();
13761 SDValue In = Op.getOperand(0);
13762 MVT SVT = In.getSimpleValueType();
13764 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13766 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13767 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13768 In, DAG.getUNDEF(SVT)));
13771 /// The only differences between FABS and FNEG are the mask and the logic op.
13772 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13773 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13774 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13775 "Wrong opcode for lowering FABS or FNEG.");
13777 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13779 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13780 // into an FNABS. We'll lower the FABS after that if it is still in use.
13782 for (SDNode *User : Op->uses())
13783 if (User->getOpcode() == ISD::FNEG)
13786 SDValue Op0 = Op.getOperand(0);
13787 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13790 MVT VT = Op.getSimpleValueType();
13791 // Assume scalar op for initialization; update for vector if needed.
13792 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13793 // generate a 16-byte vector constant and logic op even for the scalar case.
13794 // Using a 16-byte mask allows folding the load of the mask with
13795 // the logic op, so it can save (~4 bytes) on code size.
13797 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13798 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13799 // decide if we should generate a 16-byte constant mask when we only need 4 or
13800 // 8 bytes for the scalar case.
13801 if (VT.isVector()) {
13802 EltVT = VT.getVectorElementType();
13803 NumElts = VT.getVectorNumElements();
13806 unsigned EltBits = EltVT.getSizeInBits();
13807 LLVMContext *Context = DAG.getContext();
13808 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13810 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13811 Constant *C = ConstantInt::get(*Context, MaskElt);
13812 C = ConstantVector::getSplat(NumElts, C);
13813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13814 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13815 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13816 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13817 MachinePointerInfo::getConstantPool(),
13818 false, false, false, Alignment);
13820 if (VT.isVector()) {
13821 // For a vector, cast operands to a vector type, perform the logic op,
13822 // and cast the result back to the original value type.
13823 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13824 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13825 SDValue Operand = IsFNABS ?
13826 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
13827 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
13828 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
13829 return DAG.getNode(ISD::BITCAST, dl, VT,
13830 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
13833 // If not vector, then scalar.
13834 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13835 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13836 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
13839 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13840 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13841 LLVMContext *Context = DAG.getContext();
13842 SDValue Op0 = Op.getOperand(0);
13843 SDValue Op1 = Op.getOperand(1);
13845 MVT VT = Op.getSimpleValueType();
13846 MVT SrcVT = Op1.getSimpleValueType();
13848 // If second operand is smaller, extend it first.
13849 if (SrcVT.bitsLT(VT)) {
13850 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13853 // And if it is bigger, shrink it first.
13854 if (SrcVT.bitsGT(VT)) {
13855 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13859 // At this point the operands and the result should have the same
13860 // type, and that won't be f80 since that is not custom lowered.
13862 // First get the sign bit of second operand.
13863 SmallVector<Constant*,4> CV;
13864 if (SrcVT == MVT::f64) {
13865 const fltSemantics &Sem = APFloat::IEEEdouble;
13866 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13867 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13869 const fltSemantics &Sem = APFloat::IEEEsingle;
13870 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13871 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13872 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13873 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13875 Constant *C = ConstantVector::get(CV);
13876 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13877 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13878 MachinePointerInfo::getConstantPool(),
13879 false, false, false, 16);
13880 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13882 // Shift sign bit right or left if the two operands have different types.
13883 if (SrcVT.bitsGT(VT)) {
13884 // Op0 is MVT::f32, Op1 is MVT::f64.
13885 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13886 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13887 DAG.getConstant(32, MVT::i32));
13888 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13889 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13890 DAG.getIntPtrConstant(0));
13893 // Clear first operand sign bit.
13895 if (VT == MVT::f64) {
13896 const fltSemantics &Sem = APFloat::IEEEdouble;
13897 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13898 APInt(64, ~(1ULL << 63)))));
13899 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13901 const fltSemantics &Sem = APFloat::IEEEsingle;
13902 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13903 APInt(32, ~(1U << 31)))));
13904 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13905 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13906 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13908 C = ConstantVector::get(CV);
13909 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13910 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13911 MachinePointerInfo::getConstantPool(),
13912 false, false, false, 16);
13913 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13915 // Or the value with the sign bit.
13916 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13919 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13920 SDValue N0 = Op.getOperand(0);
13922 MVT VT = Op.getSimpleValueType();
13924 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13925 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13926 DAG.getConstant(1, VT));
13927 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13930 // Check whether an OR'd tree is PTEST-able.
13931 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13932 SelectionDAG &DAG) {
13933 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13935 if (!Subtarget->hasSSE41())
13938 if (!Op->hasOneUse())
13941 SDNode *N = Op.getNode();
13944 SmallVector<SDValue, 8> Opnds;
13945 DenseMap<SDValue, unsigned> VecInMap;
13946 SmallVector<SDValue, 8> VecIns;
13947 EVT VT = MVT::Other;
13949 // Recognize a special case where a vector is casted into wide integer to
13951 Opnds.push_back(N->getOperand(0));
13952 Opnds.push_back(N->getOperand(1));
13954 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13955 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13956 // BFS traverse all OR'd operands.
13957 if (I->getOpcode() == ISD::OR) {
13958 Opnds.push_back(I->getOperand(0));
13959 Opnds.push_back(I->getOperand(1));
13960 // Re-evaluate the number of nodes to be traversed.
13961 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13965 // Quit if a non-EXTRACT_VECTOR_ELT
13966 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13969 // Quit if without a constant index.
13970 SDValue Idx = I->getOperand(1);
13971 if (!isa<ConstantSDNode>(Idx))
13974 SDValue ExtractedFromVec = I->getOperand(0);
13975 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13976 if (M == VecInMap.end()) {
13977 VT = ExtractedFromVec.getValueType();
13978 // Quit if not 128/256-bit vector.
13979 if (!VT.is128BitVector() && !VT.is256BitVector())
13981 // Quit if not the same type.
13982 if (VecInMap.begin() != VecInMap.end() &&
13983 VT != VecInMap.begin()->first.getValueType())
13985 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13986 VecIns.push_back(ExtractedFromVec);
13988 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13991 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13992 "Not extracted from 128-/256-bit vector.");
13994 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13996 for (DenseMap<SDValue, unsigned>::const_iterator
13997 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13998 // Quit if not all elements are used.
13999 if (I->second != FullMask)
14003 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14005 // Cast all vectors into TestVT for PTEST.
14006 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14007 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14009 // If more than one full vectors are evaluated, OR them first before PTEST.
14010 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14011 // Each iteration will OR 2 nodes and append the result until there is only
14012 // 1 node left, i.e. the final OR'd value of all vectors.
14013 SDValue LHS = VecIns[Slot];
14014 SDValue RHS = VecIns[Slot + 1];
14015 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14018 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14019 VecIns.back(), VecIns.back());
14022 /// \brief return true if \c Op has a use that doesn't just read flags.
14023 static bool hasNonFlagsUse(SDValue Op) {
14024 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14026 SDNode *User = *UI;
14027 unsigned UOpNo = UI.getOperandNo();
14028 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14029 // Look pass truncate.
14030 UOpNo = User->use_begin().getOperandNo();
14031 User = *User->use_begin();
14034 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14035 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14041 /// Emit nodes that will be selected as "test Op0,Op0", or something
14043 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14044 SelectionDAG &DAG) const {
14045 if (Op.getValueType() == MVT::i1)
14046 // KORTEST instruction should be selected
14047 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14048 DAG.getConstant(0, Op.getValueType()));
14050 // CF and OF aren't always set the way we want. Determine which
14051 // of these we need.
14052 bool NeedCF = false;
14053 bool NeedOF = false;
14056 case X86::COND_A: case X86::COND_AE:
14057 case X86::COND_B: case X86::COND_BE:
14060 case X86::COND_G: case X86::COND_GE:
14061 case X86::COND_L: case X86::COND_LE:
14062 case X86::COND_O: case X86::COND_NO: {
14063 // Check if we really need to set the
14064 // Overflow flag. If NoSignedWrap is present
14065 // that is not actually needed.
14066 switch (Op->getOpcode()) {
14071 const BinaryWithFlagsSDNode *BinNode =
14072 cast<BinaryWithFlagsSDNode>(Op.getNode());
14073 if (BinNode->hasNoSignedWrap())
14083 // See if we can use the EFLAGS value from the operand instead of
14084 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14085 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14086 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14087 // Emit a CMP with 0, which is the TEST pattern.
14088 //if (Op.getValueType() == MVT::i1)
14089 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14090 // DAG.getConstant(0, MVT::i1));
14091 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14092 DAG.getConstant(0, Op.getValueType()));
14094 unsigned Opcode = 0;
14095 unsigned NumOperands = 0;
14097 // Truncate operations may prevent the merge of the SETCC instruction
14098 // and the arithmetic instruction before it. Attempt to truncate the operands
14099 // of the arithmetic instruction and use a reduced bit-width instruction.
14100 bool NeedTruncation = false;
14101 SDValue ArithOp = Op;
14102 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14103 SDValue Arith = Op->getOperand(0);
14104 // Both the trunc and the arithmetic op need to have one user each.
14105 if (Arith->hasOneUse())
14106 switch (Arith.getOpcode()) {
14113 NeedTruncation = true;
14119 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14120 // which may be the result of a CAST. We use the variable 'Op', which is the
14121 // non-casted variable when we check for possible users.
14122 switch (ArithOp.getOpcode()) {
14124 // Due to an isel shortcoming, be conservative if this add is likely to be
14125 // selected as part of a load-modify-store instruction. When the root node
14126 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14127 // uses of other nodes in the match, such as the ADD in this case. This
14128 // leads to the ADD being left around and reselected, with the result being
14129 // two adds in the output. Alas, even if none our users are stores, that
14130 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14131 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14132 // climbing the DAG back to the root, and it doesn't seem to be worth the
14134 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14135 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14136 if (UI->getOpcode() != ISD::CopyToReg &&
14137 UI->getOpcode() != ISD::SETCC &&
14138 UI->getOpcode() != ISD::STORE)
14141 if (ConstantSDNode *C =
14142 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14143 // An add of one will be selected as an INC.
14144 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14145 Opcode = X86ISD::INC;
14150 // An add of negative one (subtract of one) will be selected as a DEC.
14151 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14152 Opcode = X86ISD::DEC;
14158 // Otherwise use a regular EFLAGS-setting add.
14159 Opcode = X86ISD::ADD;
14164 // If we have a constant logical shift that's only used in a comparison
14165 // against zero turn it into an equivalent AND. This allows turning it into
14166 // a TEST instruction later.
14167 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14168 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14169 EVT VT = Op.getValueType();
14170 unsigned BitWidth = VT.getSizeInBits();
14171 unsigned ShAmt = Op->getConstantOperandVal(1);
14172 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14174 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14175 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14176 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14177 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14179 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14180 DAG.getConstant(Mask, VT));
14181 DAG.ReplaceAllUsesWith(Op, New);
14187 // If the primary and result isn't used, don't bother using X86ISD::AND,
14188 // because a TEST instruction will be better.
14189 if (!hasNonFlagsUse(Op))
14195 // Due to the ISEL shortcoming noted above, be conservative if this op is
14196 // likely to be selected as part of a load-modify-store instruction.
14197 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14198 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14199 if (UI->getOpcode() == ISD::STORE)
14202 // Otherwise use a regular EFLAGS-setting instruction.
14203 switch (ArithOp.getOpcode()) {
14204 default: llvm_unreachable("unexpected operator!");
14205 case ISD::SUB: Opcode = X86ISD::SUB; break;
14206 case ISD::XOR: Opcode = X86ISD::XOR; break;
14207 case ISD::AND: Opcode = X86ISD::AND; break;
14209 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14210 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14211 if (EFLAGS.getNode())
14214 Opcode = X86ISD::OR;
14228 return SDValue(Op.getNode(), 1);
14234 // If we found that truncation is beneficial, perform the truncation and
14236 if (NeedTruncation) {
14237 EVT VT = Op.getValueType();
14238 SDValue WideVal = Op->getOperand(0);
14239 EVT WideVT = WideVal.getValueType();
14240 unsigned ConvertedOp = 0;
14241 // Use a target machine opcode to prevent further DAGCombine
14242 // optimizations that may separate the arithmetic operations
14243 // from the setcc node.
14244 switch (WideVal.getOpcode()) {
14246 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14247 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14248 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14249 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14250 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14254 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14255 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14256 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14257 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14258 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14264 // Emit a CMP with 0, which is the TEST pattern.
14265 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14266 DAG.getConstant(0, Op.getValueType()));
14268 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14269 SmallVector<SDValue, 4> Ops;
14270 for (unsigned i = 0; i != NumOperands; ++i)
14271 Ops.push_back(Op.getOperand(i));
14273 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14274 DAG.ReplaceAllUsesWith(Op, New);
14275 return SDValue(New.getNode(), 1);
14278 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14280 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14281 SDLoc dl, SelectionDAG &DAG) const {
14282 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14283 if (C->getAPIntValue() == 0)
14284 return EmitTest(Op0, X86CC, dl, DAG);
14286 if (Op0.getValueType() == MVT::i1)
14287 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14290 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14291 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14292 // Do the comparison at i32 if it's smaller, besides the Atom case.
14293 // This avoids subregister aliasing issues. Keep the smaller reference
14294 // if we're optimizing for size, however, as that'll allow better folding
14295 // of memory operations.
14296 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14297 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14298 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14299 !Subtarget->isAtom()) {
14300 unsigned ExtendOp =
14301 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14302 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14303 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14305 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14306 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14307 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14309 return SDValue(Sub.getNode(), 1);
14311 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14314 /// Convert a comparison if required by the subtarget.
14315 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14316 SelectionDAG &DAG) const {
14317 // If the subtarget does not support the FUCOMI instruction, floating-point
14318 // comparisons have to be converted.
14319 if (Subtarget->hasCMov() ||
14320 Cmp.getOpcode() != X86ISD::CMP ||
14321 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14322 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14325 // The instruction selector will select an FUCOM instruction instead of
14326 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14327 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14328 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14330 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14331 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14332 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14333 DAG.getConstant(8, MVT::i8));
14334 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14335 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14338 static bool isAllOnes(SDValue V) {
14339 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14340 return C && C->isAllOnesValue();
14343 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14344 /// if it's possible.
14345 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14346 SDLoc dl, SelectionDAG &DAG) const {
14347 SDValue Op0 = And.getOperand(0);
14348 SDValue Op1 = And.getOperand(1);
14349 if (Op0.getOpcode() == ISD::TRUNCATE)
14350 Op0 = Op0.getOperand(0);
14351 if (Op1.getOpcode() == ISD::TRUNCATE)
14352 Op1 = Op1.getOperand(0);
14355 if (Op1.getOpcode() == ISD::SHL)
14356 std::swap(Op0, Op1);
14357 if (Op0.getOpcode() == ISD::SHL) {
14358 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14359 if (And00C->getZExtValue() == 1) {
14360 // If we looked past a truncate, check that it's only truncating away
14362 unsigned BitWidth = Op0.getValueSizeInBits();
14363 unsigned AndBitWidth = And.getValueSizeInBits();
14364 if (BitWidth > AndBitWidth) {
14366 DAG.computeKnownBits(Op0, Zeros, Ones);
14367 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14371 RHS = Op0.getOperand(1);
14373 } else if (Op1.getOpcode() == ISD::Constant) {
14374 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14375 uint64_t AndRHSVal = AndRHS->getZExtValue();
14376 SDValue AndLHS = Op0;
14378 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14379 LHS = AndLHS.getOperand(0);
14380 RHS = AndLHS.getOperand(1);
14383 // Use BT if the immediate can't be encoded in a TEST instruction.
14384 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14386 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14390 if (LHS.getNode()) {
14391 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14392 // instruction. Since the shift amount is in-range-or-undefined, we know
14393 // that doing a bittest on the i32 value is ok. We extend to i32 because
14394 // the encoding for the i16 version is larger than the i32 version.
14395 // Also promote i16 to i32 for performance / code size reason.
14396 if (LHS.getValueType() == MVT::i8 ||
14397 LHS.getValueType() == MVT::i16)
14398 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14400 // If the operand types disagree, extend the shift amount to match. Since
14401 // BT ignores high bits (like shifts) we can use anyextend.
14402 if (LHS.getValueType() != RHS.getValueType())
14403 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14405 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14406 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14407 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14408 DAG.getConstant(Cond, MVT::i8), BT);
14414 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14416 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14421 // SSE Condition code mapping:
14430 switch (SetCCOpcode) {
14431 default: llvm_unreachable("Unexpected SETCC condition");
14433 case ISD::SETEQ: SSECC = 0; break;
14435 case ISD::SETGT: Swap = true; // Fallthrough
14437 case ISD::SETOLT: SSECC = 1; break;
14439 case ISD::SETGE: Swap = true; // Fallthrough
14441 case ISD::SETOLE: SSECC = 2; break;
14442 case ISD::SETUO: SSECC = 3; break;
14444 case ISD::SETNE: SSECC = 4; break;
14445 case ISD::SETULE: Swap = true; // Fallthrough
14446 case ISD::SETUGE: SSECC = 5; break;
14447 case ISD::SETULT: Swap = true; // Fallthrough
14448 case ISD::SETUGT: SSECC = 6; break;
14449 case ISD::SETO: SSECC = 7; break;
14451 case ISD::SETONE: SSECC = 8; break;
14454 std::swap(Op0, Op1);
14459 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14460 // ones, and then concatenate the result back.
14461 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14462 MVT VT = Op.getSimpleValueType();
14464 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14465 "Unsupported value type for operation");
14467 unsigned NumElems = VT.getVectorNumElements();
14469 SDValue CC = Op.getOperand(2);
14471 // Extract the LHS vectors
14472 SDValue LHS = Op.getOperand(0);
14473 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14474 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14476 // Extract the RHS vectors
14477 SDValue RHS = Op.getOperand(1);
14478 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14479 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14481 // Issue the operation on the smaller types and concatenate the result back
14482 MVT EltVT = VT.getVectorElementType();
14483 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14484 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14485 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14486 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14489 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14490 const X86Subtarget *Subtarget) {
14491 SDValue Op0 = Op.getOperand(0);
14492 SDValue Op1 = Op.getOperand(1);
14493 SDValue CC = Op.getOperand(2);
14494 MVT VT = Op.getSimpleValueType();
14497 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14498 Op.getValueType().getScalarType() == MVT::i1 &&
14499 "Cannot set masked compare for this operation");
14501 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14503 bool Unsigned = false;
14506 switch (SetCCOpcode) {
14507 default: llvm_unreachable("Unexpected SETCC condition");
14508 case ISD::SETNE: SSECC = 4; break;
14509 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14510 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14511 case ISD::SETLT: Swap = true; //fall-through
14512 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14513 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14514 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14515 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14516 case ISD::SETULE: Unsigned = true; //fall-through
14517 case ISD::SETLE: SSECC = 2; break;
14521 std::swap(Op0, Op1);
14523 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14524 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14525 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14526 DAG.getConstant(SSECC, MVT::i8));
14529 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14530 /// operand \p Op1. If non-trivial (for example because it's not constant)
14531 /// return an empty value.
14532 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14534 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14538 MVT VT = Op1.getSimpleValueType();
14539 MVT EVT = VT.getVectorElementType();
14540 unsigned n = VT.getVectorNumElements();
14541 SmallVector<SDValue, 8> ULTOp1;
14543 for (unsigned i = 0; i < n; ++i) {
14544 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14545 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14548 // Avoid underflow.
14549 APInt Val = Elt->getAPIntValue();
14553 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14556 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14559 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14560 SelectionDAG &DAG) {
14561 SDValue Op0 = Op.getOperand(0);
14562 SDValue Op1 = Op.getOperand(1);
14563 SDValue CC = Op.getOperand(2);
14564 MVT VT = Op.getSimpleValueType();
14565 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14566 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14571 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14572 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14575 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14576 unsigned Opc = X86ISD::CMPP;
14577 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14578 assert(VT.getVectorNumElements() <= 16);
14579 Opc = X86ISD::CMPM;
14581 // In the two special cases we can't handle, emit two comparisons.
14584 unsigned CombineOpc;
14585 if (SetCCOpcode == ISD::SETUEQ) {
14586 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14588 assert(SetCCOpcode == ISD::SETONE);
14589 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14592 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14593 DAG.getConstant(CC0, MVT::i8));
14594 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14595 DAG.getConstant(CC1, MVT::i8));
14596 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14598 // Handle all other FP comparisons here.
14599 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14600 DAG.getConstant(SSECC, MVT::i8));
14603 // Break 256-bit integer vector compare into smaller ones.
14604 if (VT.is256BitVector() && !Subtarget->hasInt256())
14605 return Lower256IntVSETCC(Op, DAG);
14607 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14608 EVT OpVT = Op1.getValueType();
14609 if (Subtarget->hasAVX512()) {
14610 if (Op1.getValueType().is512BitVector() ||
14611 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14612 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14613 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14615 // In AVX-512 architecture setcc returns mask with i1 elements,
14616 // But there is no compare instruction for i8 and i16 elements in KNL.
14617 // We are not talking about 512-bit operands in this case, these
14618 // types are illegal.
14620 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14621 OpVT.getVectorElementType().getSizeInBits() >= 8))
14622 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14623 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14626 // We are handling one of the integer comparisons here. Since SSE only has
14627 // GT and EQ comparisons for integer, swapping operands and multiple
14628 // operations may be required for some comparisons.
14630 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14631 bool Subus = false;
14633 switch (SetCCOpcode) {
14634 default: llvm_unreachable("Unexpected SETCC condition");
14635 case ISD::SETNE: Invert = true;
14636 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14637 case ISD::SETLT: Swap = true;
14638 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14639 case ISD::SETGE: Swap = true;
14640 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14641 Invert = true; break;
14642 case ISD::SETULT: Swap = true;
14643 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14644 FlipSigns = true; break;
14645 case ISD::SETUGE: Swap = true;
14646 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14647 FlipSigns = true; Invert = true; break;
14650 // Special case: Use min/max operations for SETULE/SETUGE
14651 MVT VET = VT.getVectorElementType();
14653 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14654 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14657 switch (SetCCOpcode) {
14659 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14660 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14663 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14666 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14667 if (!MinMax && hasSubus) {
14668 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14670 // t = psubus Op0, Op1
14671 // pcmpeq t, <0..0>
14672 switch (SetCCOpcode) {
14674 case ISD::SETULT: {
14675 // If the comparison is against a constant we can turn this into a
14676 // setule. With psubus, setule does not require a swap. This is
14677 // beneficial because the constant in the register is no longer
14678 // destructed as the destination so it can be hoisted out of a loop.
14679 // Only do this pre-AVX since vpcmp* is no longer destructive.
14680 if (Subtarget->hasAVX())
14682 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14683 if (ULEOp1.getNode()) {
14685 Subus = true; Invert = false; Swap = false;
14689 // Psubus is better than flip-sign because it requires no inversion.
14690 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14691 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14695 Opc = X86ISD::SUBUS;
14701 std::swap(Op0, Op1);
14703 // Check that the operation in question is available (most are plain SSE2,
14704 // but PCMPGTQ and PCMPEQQ have different requirements).
14705 if (VT == MVT::v2i64) {
14706 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14707 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14709 // First cast everything to the right type.
14710 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14711 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14713 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14714 // bits of the inputs before performing those operations. The lower
14715 // compare is always unsigned.
14718 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14720 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14721 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14722 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14723 Sign, Zero, Sign, Zero);
14725 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14726 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14728 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14729 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14730 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14732 // Create masks for only the low parts/high parts of the 64 bit integers.
14733 static const int MaskHi[] = { 1, 1, 3, 3 };
14734 static const int MaskLo[] = { 0, 0, 2, 2 };
14735 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14736 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14737 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14739 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14740 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14743 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14745 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14748 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14749 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14750 // pcmpeqd + pshufd + pand.
14751 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14753 // First cast everything to the right type.
14754 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14755 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14758 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14760 // Make sure the lower and upper halves are both all-ones.
14761 static const int Mask[] = { 1, 0, 3, 2 };
14762 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14763 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14766 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14768 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14772 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14773 // bits of the inputs before performing those operations.
14775 EVT EltVT = VT.getVectorElementType();
14776 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14777 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14778 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14781 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14783 // If the logical-not of the result is required, perform that now.
14785 Result = DAG.getNOT(dl, Result, VT);
14788 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14791 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14792 getZeroVector(VT, Subtarget, DAG, dl));
14797 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14799 MVT VT = Op.getSimpleValueType();
14801 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14803 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14804 && "SetCC type must be 8-bit or 1-bit integer");
14805 SDValue Op0 = Op.getOperand(0);
14806 SDValue Op1 = Op.getOperand(1);
14808 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14810 // Optimize to BT if possible.
14811 // Lower (X & (1 << N)) == 0 to BT(X, N).
14812 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14813 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14814 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14815 Op1.getOpcode() == ISD::Constant &&
14816 cast<ConstantSDNode>(Op1)->isNullValue() &&
14817 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14818 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14819 if (NewSetCC.getNode())
14823 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14825 if (Op1.getOpcode() == ISD::Constant &&
14826 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14827 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14828 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14830 // If the input is a setcc, then reuse the input setcc or use a new one with
14831 // the inverted condition.
14832 if (Op0.getOpcode() == X86ISD::SETCC) {
14833 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14834 bool Invert = (CC == ISD::SETNE) ^
14835 cast<ConstantSDNode>(Op1)->isNullValue();
14839 CCode = X86::GetOppositeBranchCondition(CCode);
14840 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14841 DAG.getConstant(CCode, MVT::i8),
14842 Op0.getOperand(1));
14844 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14848 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14849 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14850 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14852 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14853 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14856 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14857 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14858 if (X86CC == X86::COND_INVALID)
14861 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14862 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14863 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14864 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14866 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14870 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14871 static bool isX86LogicalCmp(SDValue Op) {
14872 unsigned Opc = Op.getNode()->getOpcode();
14873 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14874 Opc == X86ISD::SAHF)
14876 if (Op.getResNo() == 1 &&
14877 (Opc == X86ISD::ADD ||
14878 Opc == X86ISD::SUB ||
14879 Opc == X86ISD::ADC ||
14880 Opc == X86ISD::SBB ||
14881 Opc == X86ISD::SMUL ||
14882 Opc == X86ISD::UMUL ||
14883 Opc == X86ISD::INC ||
14884 Opc == X86ISD::DEC ||
14885 Opc == X86ISD::OR ||
14886 Opc == X86ISD::XOR ||
14887 Opc == X86ISD::AND))
14890 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14896 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14897 if (V.getOpcode() != ISD::TRUNCATE)
14900 SDValue VOp0 = V.getOperand(0);
14901 unsigned InBits = VOp0.getValueSizeInBits();
14902 unsigned Bits = V.getValueSizeInBits();
14903 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14906 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14907 bool addTest = true;
14908 SDValue Cond = Op.getOperand(0);
14909 SDValue Op1 = Op.getOperand(1);
14910 SDValue Op2 = Op.getOperand(2);
14912 EVT VT = Op1.getValueType();
14915 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14916 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14917 // sequence later on.
14918 if (Cond.getOpcode() == ISD::SETCC &&
14919 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14920 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14921 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14922 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14923 int SSECC = translateX86FSETCC(
14924 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14927 if (Subtarget->hasAVX512()) {
14928 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14929 DAG.getConstant(SSECC, MVT::i8));
14930 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14932 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14933 DAG.getConstant(SSECC, MVT::i8));
14934 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14935 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14936 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14940 if (Cond.getOpcode() == ISD::SETCC) {
14941 SDValue NewCond = LowerSETCC(Cond, DAG);
14942 if (NewCond.getNode())
14946 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14947 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14948 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14949 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14950 if (Cond.getOpcode() == X86ISD::SETCC &&
14951 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14952 isZero(Cond.getOperand(1).getOperand(1))) {
14953 SDValue Cmp = Cond.getOperand(1);
14955 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14957 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14958 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14959 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14961 SDValue CmpOp0 = Cmp.getOperand(0);
14962 // Apply further optimizations for special cases
14963 // (select (x != 0), -1, 0) -> neg & sbb
14964 // (select (x == 0), 0, -1) -> neg & sbb
14965 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14966 if (YC->isNullValue() &&
14967 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14968 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14969 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14970 DAG.getConstant(0, CmpOp0.getValueType()),
14972 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14973 DAG.getConstant(X86::COND_B, MVT::i8),
14974 SDValue(Neg.getNode(), 1));
14978 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14979 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14980 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14982 SDValue Res = // Res = 0 or -1.
14983 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14984 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14986 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14987 Res = DAG.getNOT(DL, Res, Res.getValueType());
14989 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14990 if (!N2C || !N2C->isNullValue())
14991 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14996 // Look past (and (setcc_carry (cmp ...)), 1).
14997 if (Cond.getOpcode() == ISD::AND &&
14998 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14999 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15000 if (C && C->getAPIntValue() == 1)
15001 Cond = Cond.getOperand(0);
15004 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15005 // setting operand in place of the X86ISD::SETCC.
15006 unsigned CondOpcode = Cond.getOpcode();
15007 if (CondOpcode == X86ISD::SETCC ||
15008 CondOpcode == X86ISD::SETCC_CARRY) {
15009 CC = Cond.getOperand(0);
15011 SDValue Cmp = Cond.getOperand(1);
15012 unsigned Opc = Cmp.getOpcode();
15013 MVT VT = Op.getSimpleValueType();
15015 bool IllegalFPCMov = false;
15016 if (VT.isFloatingPoint() && !VT.isVector() &&
15017 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15018 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15020 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15021 Opc == X86ISD::BT) { // FIXME
15025 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15026 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15027 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15028 Cond.getOperand(0).getValueType() != MVT::i8)) {
15029 SDValue LHS = Cond.getOperand(0);
15030 SDValue RHS = Cond.getOperand(1);
15031 unsigned X86Opcode;
15034 switch (CondOpcode) {
15035 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15036 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15037 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15038 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15039 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15040 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15041 default: llvm_unreachable("unexpected overflowing operator");
15043 if (CondOpcode == ISD::UMULO)
15044 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15047 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15049 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15051 if (CondOpcode == ISD::UMULO)
15052 Cond = X86Op.getValue(2);
15054 Cond = X86Op.getValue(1);
15056 CC = DAG.getConstant(X86Cond, MVT::i8);
15061 // Look pass the truncate if the high bits are known zero.
15062 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15063 Cond = Cond.getOperand(0);
15065 // We know the result of AND is compared against zero. Try to match
15067 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15068 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15069 if (NewSetCC.getNode()) {
15070 CC = NewSetCC.getOperand(0);
15071 Cond = NewSetCC.getOperand(1);
15078 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15079 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15082 // a < b ? -1 : 0 -> RES = ~setcc_carry
15083 // a < b ? 0 : -1 -> RES = setcc_carry
15084 // a >= b ? -1 : 0 -> RES = setcc_carry
15085 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15086 if (Cond.getOpcode() == X86ISD::SUB) {
15087 Cond = ConvertCmpIfNecessary(Cond, DAG);
15088 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15090 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15091 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15092 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15093 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15094 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15095 return DAG.getNOT(DL, Res, Res.getValueType());
15100 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15101 // widen the cmov and push the truncate through. This avoids introducing a new
15102 // branch during isel and doesn't add any extensions.
15103 if (Op.getValueType() == MVT::i8 &&
15104 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15105 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15106 if (T1.getValueType() == T2.getValueType() &&
15107 // Blacklist CopyFromReg to avoid partial register stalls.
15108 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15109 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15110 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15111 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15115 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15116 // condition is true.
15117 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15118 SDValue Ops[] = { Op2, Op1, CC, Cond };
15119 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15122 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15123 SelectionDAG &DAG) {
15124 MVT VT = Op->getSimpleValueType(0);
15125 SDValue In = Op->getOperand(0);
15126 MVT InVT = In.getSimpleValueType();
15127 MVT VTElt = VT.getVectorElementType();
15128 MVT InVTElt = InVT.getVectorElementType();
15132 if ((InVTElt == MVT::i1) &&
15133 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15134 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15136 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15137 VTElt.getSizeInBits() <= 16)) ||
15139 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15140 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15142 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15143 VTElt.getSizeInBits() >= 32))))
15144 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15146 unsigned int NumElts = VT.getVectorNumElements();
15148 if (NumElts != 8 && NumElts != 16)
15151 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
15152 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15154 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15155 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15157 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15158 Constant *C = ConstantInt::get(*DAG.getContext(),
15159 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15161 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15162 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15163 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15164 MachinePointerInfo::getConstantPool(),
15165 false, false, false, Alignment);
15166 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15167 if (VT.is512BitVector())
15169 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15172 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15173 SelectionDAG &DAG) {
15174 MVT VT = Op->getSimpleValueType(0);
15175 SDValue In = Op->getOperand(0);
15176 MVT InVT = In.getSimpleValueType();
15179 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15180 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15182 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15183 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15184 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15187 if (Subtarget->hasInt256())
15188 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15190 // Optimize vectors in AVX mode
15191 // Sign extend v8i16 to v8i32 and
15194 // Divide input vector into two parts
15195 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15196 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15197 // concat the vectors to original VT
15199 unsigned NumElems = InVT.getVectorNumElements();
15200 SDValue Undef = DAG.getUNDEF(InVT);
15202 SmallVector<int,8> ShufMask1(NumElems, -1);
15203 for (unsigned i = 0; i != NumElems/2; ++i)
15206 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15208 SmallVector<int,8> ShufMask2(NumElems, -1);
15209 for (unsigned i = 0; i != NumElems/2; ++i)
15210 ShufMask2[i] = i + NumElems/2;
15212 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15214 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15215 VT.getVectorNumElements()/2);
15217 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15218 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15220 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15223 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15224 // may emit an illegal shuffle but the expansion is still better than scalar
15225 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15226 // we'll emit a shuffle and a arithmetic shift.
15227 // TODO: It is possible to support ZExt by zeroing the undef values during
15228 // the shuffle phase or after the shuffle.
15229 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15230 SelectionDAG &DAG) {
15231 MVT RegVT = Op.getSimpleValueType();
15232 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15233 assert(RegVT.isInteger() &&
15234 "We only custom lower integer vector sext loads.");
15236 // Nothing useful we can do without SSE2 shuffles.
15237 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15239 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15241 EVT MemVT = Ld->getMemoryVT();
15242 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15243 unsigned RegSz = RegVT.getSizeInBits();
15245 ISD::LoadExtType Ext = Ld->getExtensionType();
15247 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15248 && "Only anyext and sext are currently implemented.");
15249 assert(MemVT != RegVT && "Cannot extend to the same type");
15250 assert(MemVT.isVector() && "Must load a vector from memory");
15252 unsigned NumElems = RegVT.getVectorNumElements();
15253 unsigned MemSz = MemVT.getSizeInBits();
15254 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15256 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15257 // The only way in which we have a legal 256-bit vector result but not the
15258 // integer 256-bit operations needed to directly lower a sextload is if we
15259 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15260 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15261 // correctly legalized. We do this late to allow the canonical form of
15262 // sextload to persist throughout the rest of the DAG combiner -- it wants
15263 // to fold together any extensions it can, and so will fuse a sign_extend
15264 // of an sextload into a sextload targeting a wider value.
15266 if (MemSz == 128) {
15267 // Just switch this to a normal load.
15268 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15269 "it must be a legal 128-bit vector "
15271 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15272 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15273 Ld->isInvariant(), Ld->getAlignment());
15275 assert(MemSz < 128 &&
15276 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15277 // Do an sext load to a 128-bit vector type. We want to use the same
15278 // number of elements, but elements half as wide. This will end up being
15279 // recursively lowered by this routine, but will succeed as we definitely
15280 // have all the necessary features if we're using AVX1.
15282 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15283 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15285 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15286 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15287 Ld->isNonTemporal(), Ld->isInvariant(),
15288 Ld->getAlignment());
15291 // Replace chain users with the new chain.
15292 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15293 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15295 // Finally, do a normal sign-extend to the desired register.
15296 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15299 // All sizes must be a power of two.
15300 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15301 "Non-power-of-two elements are not custom lowered!");
15303 // Attempt to load the original value using scalar loads.
15304 // Find the largest scalar type that divides the total loaded size.
15305 MVT SclrLoadTy = MVT::i8;
15306 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15307 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15308 MVT Tp = (MVT::SimpleValueType)tp;
15309 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15314 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15315 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15317 SclrLoadTy = MVT::f64;
15319 // Calculate the number of scalar loads that we need to perform
15320 // in order to load our vector from memory.
15321 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15323 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15324 "Can only lower sext loads with a single scalar load!");
15326 unsigned loadRegZize = RegSz;
15327 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15330 // Represent our vector as a sequence of elements which are the
15331 // largest scalar that we can load.
15332 EVT LoadUnitVecVT = EVT::getVectorVT(
15333 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15335 // Represent the data using the same element type that is stored in
15336 // memory. In practice, we ''widen'' MemVT.
15338 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15339 loadRegZize / MemVT.getScalarType().getSizeInBits());
15341 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15342 "Invalid vector type");
15344 // We can't shuffle using an illegal type.
15345 assert(TLI.isTypeLegal(WideVecVT) &&
15346 "We only lower types that form legal widened vector types");
15348 SmallVector<SDValue, 8> Chains;
15349 SDValue Ptr = Ld->getBasePtr();
15350 SDValue Increment =
15351 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15352 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15354 for (unsigned i = 0; i < NumLoads; ++i) {
15355 // Perform a single load.
15356 SDValue ScalarLoad =
15357 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15358 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15359 Ld->getAlignment());
15360 Chains.push_back(ScalarLoad.getValue(1));
15361 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15362 // another round of DAGCombining.
15364 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15366 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15367 ScalarLoad, DAG.getIntPtrConstant(i));
15369 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15372 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15374 // Bitcast the loaded value to a vector of the original element type, in
15375 // the size of the target vector type.
15376 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15377 unsigned SizeRatio = RegSz / MemSz;
15379 if (Ext == ISD::SEXTLOAD) {
15380 // If we have SSE4.1, we can directly emit a VSEXT node.
15381 if (Subtarget->hasSSE41()) {
15382 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15383 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15387 // Otherwise we'll shuffle the small elements in the high bits of the
15388 // larger type and perform an arithmetic shift. If the shift is not legal
15389 // it's better to scalarize.
15390 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15391 "We can't implement a sext load without an arithmetic right shift!");
15393 // Redistribute the loaded elements into the different locations.
15394 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15395 for (unsigned i = 0; i != NumElems; ++i)
15396 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15398 SDValue Shuff = DAG.getVectorShuffle(
15399 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15401 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15403 // Build the arithmetic shift.
15404 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15405 MemVT.getVectorElementType().getSizeInBits();
15407 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15409 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15413 // Redistribute the loaded elements into the different locations.
15414 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15415 for (unsigned i = 0; i != NumElems; ++i)
15416 ShuffleVec[i * SizeRatio] = i;
15418 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15419 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15421 // Bitcast to the requested type.
15422 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15423 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15427 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15428 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15429 // from the AND / OR.
15430 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15431 Opc = Op.getOpcode();
15432 if (Opc != ISD::OR && Opc != ISD::AND)
15434 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15435 Op.getOperand(0).hasOneUse() &&
15436 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15437 Op.getOperand(1).hasOneUse());
15440 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15441 // 1 and that the SETCC node has a single use.
15442 static bool isXor1OfSetCC(SDValue Op) {
15443 if (Op.getOpcode() != ISD::XOR)
15445 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15446 if (N1C && N1C->getAPIntValue() == 1) {
15447 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15448 Op.getOperand(0).hasOneUse();
15453 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15454 bool addTest = true;
15455 SDValue Chain = Op.getOperand(0);
15456 SDValue Cond = Op.getOperand(1);
15457 SDValue Dest = Op.getOperand(2);
15460 bool Inverted = false;
15462 if (Cond.getOpcode() == ISD::SETCC) {
15463 // Check for setcc([su]{add,sub,mul}o == 0).
15464 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15465 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15466 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15467 Cond.getOperand(0).getResNo() == 1 &&
15468 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15469 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15470 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15471 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15472 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15473 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15475 Cond = Cond.getOperand(0);
15477 SDValue NewCond = LowerSETCC(Cond, DAG);
15478 if (NewCond.getNode())
15483 // FIXME: LowerXALUO doesn't handle these!!
15484 else if (Cond.getOpcode() == X86ISD::ADD ||
15485 Cond.getOpcode() == X86ISD::SUB ||
15486 Cond.getOpcode() == X86ISD::SMUL ||
15487 Cond.getOpcode() == X86ISD::UMUL)
15488 Cond = LowerXALUO(Cond, DAG);
15491 // Look pass (and (setcc_carry (cmp ...)), 1).
15492 if (Cond.getOpcode() == ISD::AND &&
15493 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15494 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15495 if (C && C->getAPIntValue() == 1)
15496 Cond = Cond.getOperand(0);
15499 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15500 // setting operand in place of the X86ISD::SETCC.
15501 unsigned CondOpcode = Cond.getOpcode();
15502 if (CondOpcode == X86ISD::SETCC ||
15503 CondOpcode == X86ISD::SETCC_CARRY) {
15504 CC = Cond.getOperand(0);
15506 SDValue Cmp = Cond.getOperand(1);
15507 unsigned Opc = Cmp.getOpcode();
15508 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15509 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15513 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15517 // These can only come from an arithmetic instruction with overflow,
15518 // e.g. SADDO, UADDO.
15519 Cond = Cond.getNode()->getOperand(1);
15525 CondOpcode = Cond.getOpcode();
15526 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15527 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15528 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15529 Cond.getOperand(0).getValueType() != MVT::i8)) {
15530 SDValue LHS = Cond.getOperand(0);
15531 SDValue RHS = Cond.getOperand(1);
15532 unsigned X86Opcode;
15535 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15536 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15538 switch (CondOpcode) {
15539 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15541 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15543 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15546 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15547 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15549 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15551 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15554 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15555 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15556 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15557 default: llvm_unreachable("unexpected overflowing operator");
15560 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15561 if (CondOpcode == ISD::UMULO)
15562 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15565 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15567 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15569 if (CondOpcode == ISD::UMULO)
15570 Cond = X86Op.getValue(2);
15572 Cond = X86Op.getValue(1);
15574 CC = DAG.getConstant(X86Cond, MVT::i8);
15578 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15579 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15580 if (CondOpc == ISD::OR) {
15581 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15582 // two branches instead of an explicit OR instruction with a
15584 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15585 isX86LogicalCmp(Cmp)) {
15586 CC = Cond.getOperand(0).getOperand(0);
15587 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15588 Chain, Dest, CC, Cmp);
15589 CC = Cond.getOperand(1).getOperand(0);
15593 } else { // ISD::AND
15594 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15595 // two branches instead of an explicit AND instruction with a
15596 // separate test. However, we only do this if this block doesn't
15597 // have a fall-through edge, because this requires an explicit
15598 // jmp when the condition is false.
15599 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15600 isX86LogicalCmp(Cmp) &&
15601 Op.getNode()->hasOneUse()) {
15602 X86::CondCode CCode =
15603 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15604 CCode = X86::GetOppositeBranchCondition(CCode);
15605 CC = DAG.getConstant(CCode, MVT::i8);
15606 SDNode *User = *Op.getNode()->use_begin();
15607 // Look for an unconditional branch following this conditional branch.
15608 // We need this because we need to reverse the successors in order
15609 // to implement FCMP_OEQ.
15610 if (User->getOpcode() == ISD::BR) {
15611 SDValue FalseBB = User->getOperand(1);
15613 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15614 assert(NewBR == User);
15618 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15619 Chain, Dest, CC, Cmp);
15620 X86::CondCode CCode =
15621 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15622 CCode = X86::GetOppositeBranchCondition(CCode);
15623 CC = DAG.getConstant(CCode, MVT::i8);
15629 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15630 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15631 // It should be transformed during dag combiner except when the condition
15632 // is set by a arithmetics with overflow node.
15633 X86::CondCode CCode =
15634 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15635 CCode = X86::GetOppositeBranchCondition(CCode);
15636 CC = DAG.getConstant(CCode, MVT::i8);
15637 Cond = Cond.getOperand(0).getOperand(1);
15639 } else if (Cond.getOpcode() == ISD::SETCC &&
15640 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15641 // For FCMP_OEQ, we can emit
15642 // two branches instead of an explicit AND instruction with a
15643 // separate test. However, we only do this if this block doesn't
15644 // have a fall-through edge, because this requires an explicit
15645 // jmp when the condition is false.
15646 if (Op.getNode()->hasOneUse()) {
15647 SDNode *User = *Op.getNode()->use_begin();
15648 // Look for an unconditional branch following this conditional branch.
15649 // We need this because we need to reverse the successors in order
15650 // to implement FCMP_OEQ.
15651 if (User->getOpcode() == ISD::BR) {
15652 SDValue FalseBB = User->getOperand(1);
15654 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15655 assert(NewBR == User);
15659 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15660 Cond.getOperand(0), Cond.getOperand(1));
15661 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15662 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15663 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15664 Chain, Dest, CC, Cmp);
15665 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15670 } else if (Cond.getOpcode() == ISD::SETCC &&
15671 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15672 // For FCMP_UNE, we can emit
15673 // two branches instead of an explicit AND instruction with a
15674 // separate test. However, we only do this if this block doesn't
15675 // have a fall-through edge, because this requires an explicit
15676 // jmp when the condition is false.
15677 if (Op.getNode()->hasOneUse()) {
15678 SDNode *User = *Op.getNode()->use_begin();
15679 // Look for an unconditional branch following this conditional branch.
15680 // We need this because we need to reverse the successors in order
15681 // to implement FCMP_UNE.
15682 if (User->getOpcode() == ISD::BR) {
15683 SDValue FalseBB = User->getOperand(1);
15685 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15686 assert(NewBR == User);
15689 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15690 Cond.getOperand(0), Cond.getOperand(1));
15691 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15692 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15693 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15694 Chain, Dest, CC, Cmp);
15695 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15705 // Look pass the truncate if the high bits are known zero.
15706 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15707 Cond = Cond.getOperand(0);
15709 // We know the result of AND is compared against zero. Try to match
15711 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15712 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15713 if (NewSetCC.getNode()) {
15714 CC = NewSetCC.getOperand(0);
15715 Cond = NewSetCC.getOperand(1);
15722 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15723 CC = DAG.getConstant(X86Cond, MVT::i8);
15724 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15726 Cond = ConvertCmpIfNecessary(Cond, DAG);
15727 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15728 Chain, Dest, CC, Cond);
15731 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15732 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15733 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15734 // that the guard pages used by the OS virtual memory manager are allocated in
15735 // correct sequence.
15737 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15738 SelectionDAG &DAG) const {
15739 MachineFunction &MF = DAG.getMachineFunction();
15740 bool SplitStack = MF.shouldSplitStack();
15741 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15746 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15747 SDNode* Node = Op.getNode();
15749 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15750 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15751 " not tell us which reg is the stack pointer!");
15752 EVT VT = Node->getValueType(0);
15753 SDValue Tmp1 = SDValue(Node, 0);
15754 SDValue Tmp2 = SDValue(Node, 1);
15755 SDValue Tmp3 = Node->getOperand(2);
15756 SDValue Chain = Tmp1.getOperand(0);
15758 // Chain the dynamic stack allocation so that it doesn't modify the stack
15759 // pointer when other instructions are using the stack.
15760 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15763 SDValue Size = Tmp2.getOperand(1);
15764 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15765 Chain = SP.getValue(1);
15766 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15767 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15768 unsigned StackAlign = TFI.getStackAlignment();
15769 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15770 if (Align > StackAlign)
15771 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15772 DAG.getConstant(-(uint64_t)Align, VT));
15773 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15775 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15776 DAG.getIntPtrConstant(0, true), SDValue(),
15779 SDValue Ops[2] = { Tmp1, Tmp2 };
15780 return DAG.getMergeValues(Ops, dl);
15784 SDValue Chain = Op.getOperand(0);
15785 SDValue Size = Op.getOperand(1);
15786 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15787 EVT VT = Op.getNode()->getValueType(0);
15789 bool Is64Bit = Subtarget->is64Bit();
15790 EVT SPTy = getPointerTy();
15793 MachineRegisterInfo &MRI = MF.getRegInfo();
15796 // The 64 bit implementation of segmented stacks needs to clobber both r10
15797 // r11. This makes it impossible to use it along with nested parameters.
15798 const Function *F = MF.getFunction();
15800 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15802 if (I->hasNestAttr())
15803 report_fatal_error("Cannot use segmented stacks with functions that "
15804 "have nested arguments.");
15807 const TargetRegisterClass *AddrRegClass =
15808 getRegClassFor(getPointerTy());
15809 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15810 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15811 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15812 DAG.getRegister(Vreg, SPTy));
15813 SDValue Ops1[2] = { Value, Chain };
15814 return DAG.getMergeValues(Ops1, dl);
15817 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15819 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15820 Flag = Chain.getValue(1);
15821 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15823 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15825 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15826 DAG.getSubtarget().getRegisterInfo());
15827 unsigned SPReg = RegInfo->getStackRegister();
15828 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15829 Chain = SP.getValue(1);
15832 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15833 DAG.getConstant(-(uint64_t)Align, VT));
15834 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15837 SDValue Ops1[2] = { SP, Chain };
15838 return DAG.getMergeValues(Ops1, dl);
15842 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15843 MachineFunction &MF = DAG.getMachineFunction();
15844 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15846 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15849 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15850 // vastart just stores the address of the VarArgsFrameIndex slot into the
15851 // memory location argument.
15852 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15854 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15855 MachinePointerInfo(SV), false, false, 0);
15859 // gp_offset (0 - 6 * 8)
15860 // fp_offset (48 - 48 + 8 * 16)
15861 // overflow_arg_area (point to parameters coming in memory).
15863 SmallVector<SDValue, 8> MemOps;
15864 SDValue FIN = Op.getOperand(1);
15866 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15867 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15869 FIN, MachinePointerInfo(SV), false, false, 0);
15870 MemOps.push_back(Store);
15873 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15874 FIN, DAG.getIntPtrConstant(4));
15875 Store = DAG.getStore(Op.getOperand(0), DL,
15876 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15878 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15879 MemOps.push_back(Store);
15881 // Store ptr to overflow_arg_area
15882 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15883 FIN, DAG.getIntPtrConstant(4));
15884 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15886 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15887 MachinePointerInfo(SV, 8),
15889 MemOps.push_back(Store);
15891 // Store ptr to reg_save_area.
15892 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15893 FIN, DAG.getIntPtrConstant(8));
15894 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15896 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15897 MachinePointerInfo(SV, 16), false, false, 0);
15898 MemOps.push_back(Store);
15899 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15902 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15903 assert(Subtarget->is64Bit() &&
15904 "LowerVAARG only handles 64-bit va_arg!");
15905 assert((Subtarget->isTargetLinux() ||
15906 Subtarget->isTargetDarwin()) &&
15907 "Unhandled target in LowerVAARG");
15908 assert(Op.getNode()->getNumOperands() == 4);
15909 SDValue Chain = Op.getOperand(0);
15910 SDValue SrcPtr = Op.getOperand(1);
15911 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15912 unsigned Align = Op.getConstantOperandVal(3);
15915 EVT ArgVT = Op.getNode()->getValueType(0);
15916 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15917 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15920 // Decide which area this value should be read from.
15921 // TODO: Implement the AMD64 ABI in its entirety. This simple
15922 // selection mechanism works only for the basic types.
15923 if (ArgVT == MVT::f80) {
15924 llvm_unreachable("va_arg for f80 not yet implemented");
15925 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15926 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15927 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15928 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15930 llvm_unreachable("Unhandled argument type in LowerVAARG");
15933 if (ArgMode == 2) {
15934 // Sanity Check: Make sure using fp_offset makes sense.
15935 assert(!DAG.getTarget().Options.UseSoftFloat &&
15936 !(DAG.getMachineFunction()
15937 .getFunction()->getAttributes()
15938 .hasAttribute(AttributeSet::FunctionIndex,
15939 Attribute::NoImplicitFloat)) &&
15940 Subtarget->hasSSE1());
15943 // Insert VAARG_64 node into the DAG
15944 // VAARG_64 returns two values: Variable Argument Address, Chain
15945 SmallVector<SDValue, 11> InstOps;
15946 InstOps.push_back(Chain);
15947 InstOps.push_back(SrcPtr);
15948 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15949 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15950 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15951 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15952 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15953 VTs, InstOps, MVT::i64,
15954 MachinePointerInfo(SV),
15956 /*Volatile=*/false,
15958 /*WriteMem=*/true);
15959 Chain = VAARG.getValue(1);
15961 // Load the next argument and return it
15962 return DAG.getLoad(ArgVT, dl,
15965 MachinePointerInfo(),
15966 false, false, false, 0);
15969 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15970 SelectionDAG &DAG) {
15971 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15972 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15973 SDValue Chain = Op.getOperand(0);
15974 SDValue DstPtr = Op.getOperand(1);
15975 SDValue SrcPtr = Op.getOperand(2);
15976 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15977 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15980 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15981 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15983 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15986 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15987 // amount is a constant. Takes immediate version of shift as input.
15988 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15989 SDValue SrcOp, uint64_t ShiftAmt,
15990 SelectionDAG &DAG) {
15991 MVT ElementType = VT.getVectorElementType();
15993 // Fold this packed shift into its first operand if ShiftAmt is 0.
15997 // Check for ShiftAmt >= element width
15998 if (ShiftAmt >= ElementType.getSizeInBits()) {
15999 if (Opc == X86ISD::VSRAI)
16000 ShiftAmt = ElementType.getSizeInBits() - 1;
16002 return DAG.getConstant(0, VT);
16005 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16006 && "Unknown target vector shift-by-constant node");
16008 // Fold this packed vector shift into a build vector if SrcOp is a
16009 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16010 if (VT == SrcOp.getSimpleValueType() &&
16011 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16012 SmallVector<SDValue, 8> Elts;
16013 unsigned NumElts = SrcOp->getNumOperands();
16014 ConstantSDNode *ND;
16017 default: llvm_unreachable(nullptr);
16018 case X86ISD::VSHLI:
16019 for (unsigned i=0; i!=NumElts; ++i) {
16020 SDValue CurrentOp = SrcOp->getOperand(i);
16021 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16022 Elts.push_back(CurrentOp);
16025 ND = cast<ConstantSDNode>(CurrentOp);
16026 const APInt &C = ND->getAPIntValue();
16027 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16030 case X86ISD::VSRLI:
16031 for (unsigned i=0; i!=NumElts; ++i) {
16032 SDValue CurrentOp = SrcOp->getOperand(i);
16033 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16034 Elts.push_back(CurrentOp);
16037 ND = cast<ConstantSDNode>(CurrentOp);
16038 const APInt &C = ND->getAPIntValue();
16039 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16042 case X86ISD::VSRAI:
16043 for (unsigned i=0; i!=NumElts; ++i) {
16044 SDValue CurrentOp = SrcOp->getOperand(i);
16045 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16046 Elts.push_back(CurrentOp);
16049 ND = cast<ConstantSDNode>(CurrentOp);
16050 const APInt &C = ND->getAPIntValue();
16051 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16056 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16059 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16062 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16063 // may or may not be a constant. Takes immediate version of shift as input.
16064 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16065 SDValue SrcOp, SDValue ShAmt,
16066 SelectionDAG &DAG) {
16067 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16069 // Catch shift-by-constant.
16070 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16071 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16072 CShAmt->getZExtValue(), DAG);
16074 // Change opcode to non-immediate version
16076 default: llvm_unreachable("Unknown target vector shift node");
16077 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16078 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16079 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16082 // Need to build a vector containing shift amount
16083 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16086 ShOps[1] = DAG.getConstant(0, MVT::i32);
16087 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16088 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16090 // The return type has to be a 128-bit type with the same element
16091 // type as the input type.
16092 MVT EltVT = VT.getVectorElementType();
16093 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16095 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16096 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16099 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16100 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16101 /// necessary casting for \p Mask when lowering masking intrinsics.
16102 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16103 SDValue PreservedSrc, SelectionDAG &DAG) {
16104 EVT VT = Op.getValueType();
16105 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16106 MVT::i1, VT.getVectorNumElements());
16107 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16108 Mask.getValueType().getSizeInBits());
16111 assert(MaskVT.isSimple() && "invalid mask type");
16113 if (isAllOnes(Mask))
16116 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16117 // are extracted by EXTRACT_SUBVECTOR.
16118 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16119 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16120 DAG.getIntPtrConstant(0));
16122 switch (Op.getOpcode()) {
16124 case X86ISD::PCMPEQM:
16125 case X86ISD::PCMPGTM:
16127 case X86ISD::CMPMU:
16128 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16131 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16134 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16136 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16137 case Intrinsic::x86_fma_vfmadd_ps:
16138 case Intrinsic::x86_fma_vfmadd_pd:
16139 case Intrinsic::x86_fma_vfmadd_ps_256:
16140 case Intrinsic::x86_fma_vfmadd_pd_256:
16141 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16142 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16143 return X86ISD::FMADD;
16144 case Intrinsic::x86_fma_vfmsub_ps:
16145 case Intrinsic::x86_fma_vfmsub_pd:
16146 case Intrinsic::x86_fma_vfmsub_ps_256:
16147 case Intrinsic::x86_fma_vfmsub_pd_256:
16148 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16149 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16150 return X86ISD::FMSUB;
16151 case Intrinsic::x86_fma_vfnmadd_ps:
16152 case Intrinsic::x86_fma_vfnmadd_pd:
16153 case Intrinsic::x86_fma_vfnmadd_ps_256:
16154 case Intrinsic::x86_fma_vfnmadd_pd_256:
16155 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16156 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16157 return X86ISD::FNMADD;
16158 case Intrinsic::x86_fma_vfnmsub_ps:
16159 case Intrinsic::x86_fma_vfnmsub_pd:
16160 case Intrinsic::x86_fma_vfnmsub_ps_256:
16161 case Intrinsic::x86_fma_vfnmsub_pd_256:
16162 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16163 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16164 return X86ISD::FNMSUB;
16165 case Intrinsic::x86_fma_vfmaddsub_ps:
16166 case Intrinsic::x86_fma_vfmaddsub_pd:
16167 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16168 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16169 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16170 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16171 return X86ISD::FMADDSUB;
16172 case Intrinsic::x86_fma_vfmsubadd_ps:
16173 case Intrinsic::x86_fma_vfmsubadd_pd:
16174 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16175 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16176 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16177 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16178 return X86ISD::FMSUBADD;
16182 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
16184 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16186 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16188 switch(IntrData->Type) {
16189 case INTR_TYPE_1OP:
16190 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16191 case INTR_TYPE_2OP:
16192 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16194 case INTR_TYPE_3OP:
16195 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16196 Op.getOperand(2), Op.getOperand(3));
16198 // Comparison intrinsics with masks.
16199 // Example of transformation:
16200 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16201 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16203 // (v8i1 (insert_subvector undef,
16204 // (v2i1 (and (PCMPEQM %a, %b),
16205 // (extract_subvector
16206 // (v8i1 (bitcast %mask)), 0))), 0))))
16207 EVT VT = Op.getOperand(1).getValueType();
16208 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16209 VT.getVectorNumElements());
16210 SDValue Mask = Op.getOperand(3);
16211 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16212 Mask.getValueType().getSizeInBits());
16213 SDValue Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT,
16214 Op.getOperand(1), Op.getOperand(2));
16215 SDValue CmpMask = getVectorMaskingNode(Cmp, Op.getOperand(3),
16216 DAG.getTargetConstant(0, MaskVT), DAG);
16217 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16218 DAG.getUNDEF(BitcastVT), CmpMask,
16219 DAG.getIntPtrConstant(0));
16220 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16222 case COMI: { // Comparison intrinsics
16223 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16224 SDValue LHS = Op.getOperand(1);
16225 SDValue RHS = Op.getOperand(2);
16226 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16227 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16228 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16229 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16230 DAG.getConstant(X86CC, MVT::i8), Cond);
16231 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16234 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16235 Op.getOperand(1), Op.getOperand(2), DAG);
16242 default: return SDValue(); // Don't custom lower most intrinsics.
16244 // Arithmetic intrinsics.
16245 case Intrinsic::x86_sse2_pmulu_dq:
16246 case Intrinsic::x86_avx2_pmulu_dq:
16247 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16248 Op.getOperand(1), Op.getOperand(2));
16250 case Intrinsic::x86_sse41_pmuldq:
16251 case Intrinsic::x86_avx2_pmul_dq:
16252 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16253 Op.getOperand(1), Op.getOperand(2));
16255 case Intrinsic::x86_sse2_pmulhu_w:
16256 case Intrinsic::x86_avx2_pmulhu_w:
16257 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16258 Op.getOperand(1), Op.getOperand(2));
16260 case Intrinsic::x86_sse2_pmulh_w:
16261 case Intrinsic::x86_avx2_pmulh_w:
16262 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16263 Op.getOperand(1), Op.getOperand(2));
16265 // SSE/SSE2/AVX floating point max/min intrinsics.
16266 case Intrinsic::x86_sse_max_ps:
16267 case Intrinsic::x86_sse2_max_pd:
16268 case Intrinsic::x86_avx_max_ps_256:
16269 case Intrinsic::x86_avx_max_pd_256:
16270 case Intrinsic::x86_sse_min_ps:
16271 case Intrinsic::x86_sse2_min_pd:
16272 case Intrinsic::x86_avx_min_ps_256:
16273 case Intrinsic::x86_avx_min_pd_256: {
16276 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16277 case Intrinsic::x86_sse_max_ps:
16278 case Intrinsic::x86_sse2_max_pd:
16279 case Intrinsic::x86_avx_max_ps_256:
16280 case Intrinsic::x86_avx_max_pd_256:
16281 Opcode = X86ISD::FMAX;
16283 case Intrinsic::x86_sse_min_ps:
16284 case Intrinsic::x86_sse2_min_pd:
16285 case Intrinsic::x86_avx_min_ps_256:
16286 case Intrinsic::x86_avx_min_pd_256:
16287 Opcode = X86ISD::FMIN;
16290 return DAG.getNode(Opcode, dl, Op.getValueType(),
16291 Op.getOperand(1), Op.getOperand(2));
16294 // AVX2 variable shift intrinsics
16295 case Intrinsic::x86_avx2_psllv_d:
16296 case Intrinsic::x86_avx2_psllv_q:
16297 case Intrinsic::x86_avx2_psllv_d_256:
16298 case Intrinsic::x86_avx2_psllv_q_256:
16299 case Intrinsic::x86_avx2_psrlv_d:
16300 case Intrinsic::x86_avx2_psrlv_q:
16301 case Intrinsic::x86_avx2_psrlv_d_256:
16302 case Intrinsic::x86_avx2_psrlv_q_256:
16303 case Intrinsic::x86_avx2_psrav_d:
16304 case Intrinsic::x86_avx2_psrav_d_256: {
16307 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16308 case Intrinsic::x86_avx2_psllv_d:
16309 case Intrinsic::x86_avx2_psllv_q:
16310 case Intrinsic::x86_avx2_psllv_d_256:
16311 case Intrinsic::x86_avx2_psllv_q_256:
16314 case Intrinsic::x86_avx2_psrlv_d:
16315 case Intrinsic::x86_avx2_psrlv_q:
16316 case Intrinsic::x86_avx2_psrlv_d_256:
16317 case Intrinsic::x86_avx2_psrlv_q_256:
16320 case Intrinsic::x86_avx2_psrav_d:
16321 case Intrinsic::x86_avx2_psrav_d_256:
16325 return DAG.getNode(Opcode, dl, Op.getValueType(),
16326 Op.getOperand(1), Op.getOperand(2));
16329 case Intrinsic::x86_sse2_packssdw_128:
16330 case Intrinsic::x86_sse2_packsswb_128:
16331 case Intrinsic::x86_avx2_packssdw:
16332 case Intrinsic::x86_avx2_packsswb:
16333 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16334 Op.getOperand(1), Op.getOperand(2));
16336 case Intrinsic::x86_sse2_packuswb_128:
16337 case Intrinsic::x86_sse41_packusdw:
16338 case Intrinsic::x86_avx2_packuswb:
16339 case Intrinsic::x86_avx2_packusdw:
16340 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16341 Op.getOperand(1), Op.getOperand(2));
16343 case Intrinsic::x86_ssse3_pshuf_b_128:
16344 case Intrinsic::x86_avx2_pshuf_b:
16345 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16346 Op.getOperand(1), Op.getOperand(2));
16348 case Intrinsic::x86_sse2_pshuf_d:
16349 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16350 Op.getOperand(1), Op.getOperand(2));
16352 case Intrinsic::x86_sse2_pshufl_w:
16353 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16354 Op.getOperand(1), Op.getOperand(2));
16356 case Intrinsic::x86_sse2_pshufh_w:
16357 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16358 Op.getOperand(1), Op.getOperand(2));
16360 case Intrinsic::x86_ssse3_psign_b_128:
16361 case Intrinsic::x86_ssse3_psign_w_128:
16362 case Intrinsic::x86_ssse3_psign_d_128:
16363 case Intrinsic::x86_avx2_psign_b:
16364 case Intrinsic::x86_avx2_psign_w:
16365 case Intrinsic::x86_avx2_psign_d:
16366 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16367 Op.getOperand(1), Op.getOperand(2));
16369 case Intrinsic::x86_avx2_permd:
16370 case Intrinsic::x86_avx2_permps:
16371 // Operands intentionally swapped. Mask is last operand to intrinsic,
16372 // but second operand for node/instruction.
16373 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16374 Op.getOperand(2), Op.getOperand(1));
16376 case Intrinsic::x86_avx512_mask_valign_q_512:
16377 case Intrinsic::x86_avx512_mask_valign_d_512:
16378 // Vector source operands are swapped.
16379 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16380 Op.getValueType(), Op.getOperand(2),
16383 Op.getOperand(5), Op.getOperand(4), DAG);
16385 // ptest and testp intrinsics. The intrinsic these come from are designed to
16386 // return an integer value, not just an instruction so lower it to the ptest
16387 // or testp pattern and a setcc for the result.
16388 case Intrinsic::x86_sse41_ptestz:
16389 case Intrinsic::x86_sse41_ptestc:
16390 case Intrinsic::x86_sse41_ptestnzc:
16391 case Intrinsic::x86_avx_ptestz_256:
16392 case Intrinsic::x86_avx_ptestc_256:
16393 case Intrinsic::x86_avx_ptestnzc_256:
16394 case Intrinsic::x86_avx_vtestz_ps:
16395 case Intrinsic::x86_avx_vtestc_ps:
16396 case Intrinsic::x86_avx_vtestnzc_ps:
16397 case Intrinsic::x86_avx_vtestz_pd:
16398 case Intrinsic::x86_avx_vtestc_pd:
16399 case Intrinsic::x86_avx_vtestnzc_pd:
16400 case Intrinsic::x86_avx_vtestz_ps_256:
16401 case Intrinsic::x86_avx_vtestc_ps_256:
16402 case Intrinsic::x86_avx_vtestnzc_ps_256:
16403 case Intrinsic::x86_avx_vtestz_pd_256:
16404 case Intrinsic::x86_avx_vtestc_pd_256:
16405 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16406 bool IsTestPacked = false;
16409 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16410 case Intrinsic::x86_avx_vtestz_ps:
16411 case Intrinsic::x86_avx_vtestz_pd:
16412 case Intrinsic::x86_avx_vtestz_ps_256:
16413 case Intrinsic::x86_avx_vtestz_pd_256:
16414 IsTestPacked = true; // Fallthrough
16415 case Intrinsic::x86_sse41_ptestz:
16416 case Intrinsic::x86_avx_ptestz_256:
16418 X86CC = X86::COND_E;
16420 case Intrinsic::x86_avx_vtestc_ps:
16421 case Intrinsic::x86_avx_vtestc_pd:
16422 case Intrinsic::x86_avx_vtestc_ps_256:
16423 case Intrinsic::x86_avx_vtestc_pd_256:
16424 IsTestPacked = true; // Fallthrough
16425 case Intrinsic::x86_sse41_ptestc:
16426 case Intrinsic::x86_avx_ptestc_256:
16428 X86CC = X86::COND_B;
16430 case Intrinsic::x86_avx_vtestnzc_ps:
16431 case Intrinsic::x86_avx_vtestnzc_pd:
16432 case Intrinsic::x86_avx_vtestnzc_ps_256:
16433 case Intrinsic::x86_avx_vtestnzc_pd_256:
16434 IsTestPacked = true; // Fallthrough
16435 case Intrinsic::x86_sse41_ptestnzc:
16436 case Intrinsic::x86_avx_ptestnzc_256:
16438 X86CC = X86::COND_A;
16442 SDValue LHS = Op.getOperand(1);
16443 SDValue RHS = Op.getOperand(2);
16444 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16445 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16446 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16447 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16448 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16450 case Intrinsic::x86_avx512_kortestz_w:
16451 case Intrinsic::x86_avx512_kortestc_w: {
16452 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16453 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16454 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16455 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16456 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16457 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16458 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16461 case Intrinsic::x86_sse42_pcmpistria128:
16462 case Intrinsic::x86_sse42_pcmpestria128:
16463 case Intrinsic::x86_sse42_pcmpistric128:
16464 case Intrinsic::x86_sse42_pcmpestric128:
16465 case Intrinsic::x86_sse42_pcmpistrio128:
16466 case Intrinsic::x86_sse42_pcmpestrio128:
16467 case Intrinsic::x86_sse42_pcmpistris128:
16468 case Intrinsic::x86_sse42_pcmpestris128:
16469 case Intrinsic::x86_sse42_pcmpistriz128:
16470 case Intrinsic::x86_sse42_pcmpestriz128: {
16474 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16475 case Intrinsic::x86_sse42_pcmpistria128:
16476 Opcode = X86ISD::PCMPISTRI;
16477 X86CC = X86::COND_A;
16479 case Intrinsic::x86_sse42_pcmpestria128:
16480 Opcode = X86ISD::PCMPESTRI;
16481 X86CC = X86::COND_A;
16483 case Intrinsic::x86_sse42_pcmpistric128:
16484 Opcode = X86ISD::PCMPISTRI;
16485 X86CC = X86::COND_B;
16487 case Intrinsic::x86_sse42_pcmpestric128:
16488 Opcode = X86ISD::PCMPESTRI;
16489 X86CC = X86::COND_B;
16491 case Intrinsic::x86_sse42_pcmpistrio128:
16492 Opcode = X86ISD::PCMPISTRI;
16493 X86CC = X86::COND_O;
16495 case Intrinsic::x86_sse42_pcmpestrio128:
16496 Opcode = X86ISD::PCMPESTRI;
16497 X86CC = X86::COND_O;
16499 case Intrinsic::x86_sse42_pcmpistris128:
16500 Opcode = X86ISD::PCMPISTRI;
16501 X86CC = X86::COND_S;
16503 case Intrinsic::x86_sse42_pcmpestris128:
16504 Opcode = X86ISD::PCMPESTRI;
16505 X86CC = X86::COND_S;
16507 case Intrinsic::x86_sse42_pcmpistriz128:
16508 Opcode = X86ISD::PCMPISTRI;
16509 X86CC = X86::COND_E;
16511 case Intrinsic::x86_sse42_pcmpestriz128:
16512 Opcode = X86ISD::PCMPESTRI;
16513 X86CC = X86::COND_E;
16516 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16517 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16518 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16519 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16520 DAG.getConstant(X86CC, MVT::i8),
16521 SDValue(PCMP.getNode(), 1));
16522 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16525 case Intrinsic::x86_sse42_pcmpistri128:
16526 case Intrinsic::x86_sse42_pcmpestri128: {
16528 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16529 Opcode = X86ISD::PCMPISTRI;
16531 Opcode = X86ISD::PCMPESTRI;
16533 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16534 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16535 return DAG.getNode(Opcode, dl, VTs, NewOps);
16538 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16539 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16540 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16541 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16542 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16543 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16544 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16545 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16546 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16547 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16548 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16549 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16550 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16551 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16552 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16553 dl, Op.getValueType(),
16557 Op.getOperand(4), Op.getOperand(1), DAG);
16562 case Intrinsic::x86_fma_vfmadd_ps:
16563 case Intrinsic::x86_fma_vfmadd_pd:
16564 case Intrinsic::x86_fma_vfmsub_ps:
16565 case Intrinsic::x86_fma_vfmsub_pd:
16566 case Intrinsic::x86_fma_vfnmadd_ps:
16567 case Intrinsic::x86_fma_vfnmadd_pd:
16568 case Intrinsic::x86_fma_vfnmsub_ps:
16569 case Intrinsic::x86_fma_vfnmsub_pd:
16570 case Intrinsic::x86_fma_vfmaddsub_ps:
16571 case Intrinsic::x86_fma_vfmaddsub_pd:
16572 case Intrinsic::x86_fma_vfmsubadd_ps:
16573 case Intrinsic::x86_fma_vfmsubadd_pd:
16574 case Intrinsic::x86_fma_vfmadd_ps_256:
16575 case Intrinsic::x86_fma_vfmadd_pd_256:
16576 case Intrinsic::x86_fma_vfmsub_ps_256:
16577 case Intrinsic::x86_fma_vfmsub_pd_256:
16578 case Intrinsic::x86_fma_vfnmadd_ps_256:
16579 case Intrinsic::x86_fma_vfnmadd_pd_256:
16580 case Intrinsic::x86_fma_vfnmsub_ps_256:
16581 case Intrinsic::x86_fma_vfnmsub_pd_256:
16582 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16583 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16584 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16585 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16586 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16587 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16591 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16592 SDValue Src, SDValue Mask, SDValue Base,
16593 SDValue Index, SDValue ScaleOp, SDValue Chain,
16594 const X86Subtarget * Subtarget) {
16596 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16597 assert(C && "Invalid scale type");
16598 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16599 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16600 Index.getSimpleValueType().getVectorNumElements());
16602 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16604 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16606 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16607 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16608 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16609 SDValue Segment = DAG.getRegister(0, MVT::i32);
16610 if (Src.getOpcode() == ISD::UNDEF)
16611 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16612 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16613 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16614 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16615 return DAG.getMergeValues(RetOps, dl);
16618 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16619 SDValue Src, SDValue Mask, SDValue Base,
16620 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16622 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16623 assert(C && "Invalid scale type");
16624 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16625 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16626 SDValue Segment = DAG.getRegister(0, MVT::i32);
16627 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16628 Index.getSimpleValueType().getVectorNumElements());
16630 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16632 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16634 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16635 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16636 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16637 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16638 return SDValue(Res, 1);
16641 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16642 SDValue Mask, SDValue Base, SDValue Index,
16643 SDValue ScaleOp, SDValue Chain) {
16645 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16646 assert(C && "Invalid scale type");
16647 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16648 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16649 SDValue Segment = DAG.getRegister(0, MVT::i32);
16651 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16653 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16655 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16657 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16658 //SDVTList VTs = DAG.getVTList(MVT::Other);
16659 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16660 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16661 return SDValue(Res, 0);
16664 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16665 // read performance monitor counters (x86_rdpmc).
16666 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16667 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16668 SmallVectorImpl<SDValue> &Results) {
16669 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16670 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16673 // The ECX register is used to select the index of the performance counter
16675 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16677 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16679 // Reads the content of a 64-bit performance counter and returns it in the
16680 // registers EDX:EAX.
16681 if (Subtarget->is64Bit()) {
16682 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16683 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16686 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16687 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16690 Chain = HI.getValue(1);
16692 if (Subtarget->is64Bit()) {
16693 // The EAX register is loaded with the low-order 32 bits. The EDX register
16694 // is loaded with the supported high-order bits of the counter.
16695 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16696 DAG.getConstant(32, MVT::i8));
16697 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16698 Results.push_back(Chain);
16702 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16703 SDValue Ops[] = { LO, HI };
16704 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16705 Results.push_back(Pair);
16706 Results.push_back(Chain);
16709 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16710 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16711 // also used to custom lower READCYCLECOUNTER nodes.
16712 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16713 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16714 SmallVectorImpl<SDValue> &Results) {
16715 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16716 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16719 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16720 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16721 // and the EAX register is loaded with the low-order 32 bits.
16722 if (Subtarget->is64Bit()) {
16723 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16724 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16727 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16728 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16731 SDValue Chain = HI.getValue(1);
16733 if (Opcode == X86ISD::RDTSCP_DAG) {
16734 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16736 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16737 // the ECX register. Add 'ecx' explicitly to the chain.
16738 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16740 // Explicitly store the content of ECX at the location passed in input
16741 // to the 'rdtscp' intrinsic.
16742 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16743 MachinePointerInfo(), false, false, 0);
16746 if (Subtarget->is64Bit()) {
16747 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16748 // the EAX register is loaded with the low-order 32 bits.
16749 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16750 DAG.getConstant(32, MVT::i8));
16751 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16752 Results.push_back(Chain);
16756 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16757 SDValue Ops[] = { LO, HI };
16758 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16759 Results.push_back(Pair);
16760 Results.push_back(Chain);
16763 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16764 SelectionDAG &DAG) {
16765 SmallVector<SDValue, 2> Results;
16767 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16769 return DAG.getMergeValues(Results, DL);
16773 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16774 SelectionDAG &DAG) {
16775 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16777 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16782 switch(IntrData->Type) {
16784 llvm_unreachable("Unknown Intrinsic Type");
16788 // Emit the node with the right value type.
16789 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16790 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16792 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16793 // Otherwise return the value from Rand, which is always 0, casted to i32.
16794 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16795 DAG.getConstant(1, Op->getValueType(1)),
16796 DAG.getConstant(X86::COND_B, MVT::i32),
16797 SDValue(Result.getNode(), 1) };
16798 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16799 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16802 // Return { result, isValid, chain }.
16803 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16804 SDValue(Result.getNode(), 2));
16807 //gather(v1, mask, index, base, scale);
16808 SDValue Chain = Op.getOperand(0);
16809 SDValue Src = Op.getOperand(2);
16810 SDValue Base = Op.getOperand(3);
16811 SDValue Index = Op.getOperand(4);
16812 SDValue Mask = Op.getOperand(5);
16813 SDValue Scale = Op.getOperand(6);
16814 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16818 //scatter(base, mask, index, v1, scale);
16819 SDValue Chain = Op.getOperand(0);
16820 SDValue Base = Op.getOperand(2);
16821 SDValue Mask = Op.getOperand(3);
16822 SDValue Index = Op.getOperand(4);
16823 SDValue Src = Op.getOperand(5);
16824 SDValue Scale = Op.getOperand(6);
16825 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16828 SDValue Hint = Op.getOperand(6);
16830 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16831 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16832 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16833 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16834 SDValue Chain = Op.getOperand(0);
16835 SDValue Mask = Op.getOperand(2);
16836 SDValue Index = Op.getOperand(3);
16837 SDValue Base = Op.getOperand(4);
16838 SDValue Scale = Op.getOperand(5);
16839 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16841 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16843 SmallVector<SDValue, 2> Results;
16844 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16845 return DAG.getMergeValues(Results, dl);
16847 // Read Performance Monitoring Counters.
16849 SmallVector<SDValue, 2> Results;
16850 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16851 return DAG.getMergeValues(Results, dl);
16853 // XTEST intrinsics.
16855 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16856 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16857 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16858 DAG.getConstant(X86::COND_NE, MVT::i8),
16860 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16861 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16862 Ret, SDValue(InTrans.getNode(), 1));
16866 SmallVector<SDValue, 2> Results;
16867 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16868 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16869 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16870 DAG.getConstant(-1, MVT::i8));
16871 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16872 Op.getOperand(4), GenCF.getValue(1));
16873 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16874 Op.getOperand(5), MachinePointerInfo(),
16876 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16877 DAG.getConstant(X86::COND_B, MVT::i8),
16879 Results.push_back(SetCC);
16880 Results.push_back(Store);
16881 return DAG.getMergeValues(Results, dl);
16886 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16887 SelectionDAG &DAG) const {
16888 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16889 MFI->setReturnAddressIsTaken(true);
16891 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16894 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16896 EVT PtrVT = getPointerTy();
16899 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16900 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16901 DAG.getSubtarget().getRegisterInfo());
16902 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16903 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16904 DAG.getNode(ISD::ADD, dl, PtrVT,
16905 FrameAddr, Offset),
16906 MachinePointerInfo(), false, false, false, 0);
16909 // Just load the return address.
16910 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16911 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16912 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16915 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16916 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16917 MFI->setFrameAddressIsTaken(true);
16919 EVT VT = Op.getValueType();
16920 SDLoc dl(Op); // FIXME probably not meaningful
16921 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16922 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16923 DAG.getSubtarget().getRegisterInfo());
16924 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16925 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16926 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16927 "Invalid Frame Register!");
16928 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16930 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16931 MachinePointerInfo(),
16932 false, false, false, 0);
16936 // FIXME? Maybe this could be a TableGen attribute on some registers and
16937 // this table could be generated automatically from RegInfo.
16938 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16940 unsigned Reg = StringSwitch<unsigned>(RegName)
16941 .Case("esp", X86::ESP)
16942 .Case("rsp", X86::RSP)
16946 report_fatal_error("Invalid register name global variable");
16949 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16950 SelectionDAG &DAG) const {
16951 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16952 DAG.getSubtarget().getRegisterInfo());
16953 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16956 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16957 SDValue Chain = Op.getOperand(0);
16958 SDValue Offset = Op.getOperand(1);
16959 SDValue Handler = Op.getOperand(2);
16962 EVT PtrVT = getPointerTy();
16963 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16964 DAG.getSubtarget().getRegisterInfo());
16965 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16966 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16967 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16968 "Invalid Frame Register!");
16969 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16970 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16972 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16973 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16974 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16975 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16977 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16979 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16980 DAG.getRegister(StoreAddrReg, PtrVT));
16983 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16984 SelectionDAG &DAG) const {
16986 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16987 DAG.getVTList(MVT::i32, MVT::Other),
16988 Op.getOperand(0), Op.getOperand(1));
16991 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16992 SelectionDAG &DAG) const {
16994 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16995 Op.getOperand(0), Op.getOperand(1));
16998 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16999 return Op.getOperand(0);
17002 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17003 SelectionDAG &DAG) const {
17004 SDValue Root = Op.getOperand(0);
17005 SDValue Trmp = Op.getOperand(1); // trampoline
17006 SDValue FPtr = Op.getOperand(2); // nested function
17007 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17010 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17011 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17013 if (Subtarget->is64Bit()) {
17014 SDValue OutChains[6];
17016 // Large code-model.
17017 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17018 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17020 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17021 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17023 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17025 // Load the pointer to the nested function into R11.
17026 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17027 SDValue Addr = Trmp;
17028 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17029 Addr, MachinePointerInfo(TrmpAddr),
17032 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17033 DAG.getConstant(2, MVT::i64));
17034 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17035 MachinePointerInfo(TrmpAddr, 2),
17038 // Load the 'nest' parameter value into R10.
17039 // R10 is specified in X86CallingConv.td
17040 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17041 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17042 DAG.getConstant(10, MVT::i64));
17043 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17044 Addr, MachinePointerInfo(TrmpAddr, 10),
17047 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17048 DAG.getConstant(12, MVT::i64));
17049 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17050 MachinePointerInfo(TrmpAddr, 12),
17053 // Jump to the nested function.
17054 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17055 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17056 DAG.getConstant(20, MVT::i64));
17057 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17058 Addr, MachinePointerInfo(TrmpAddr, 20),
17061 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17062 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17063 DAG.getConstant(22, MVT::i64));
17064 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17065 MachinePointerInfo(TrmpAddr, 22),
17068 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17070 const Function *Func =
17071 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17072 CallingConv::ID CC = Func->getCallingConv();
17077 llvm_unreachable("Unsupported calling convention");
17078 case CallingConv::C:
17079 case CallingConv::X86_StdCall: {
17080 // Pass 'nest' parameter in ECX.
17081 // Must be kept in sync with X86CallingConv.td
17082 NestReg = X86::ECX;
17084 // Check that ECX wasn't needed by an 'inreg' parameter.
17085 FunctionType *FTy = Func->getFunctionType();
17086 const AttributeSet &Attrs = Func->getAttributes();
17088 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17089 unsigned InRegCount = 0;
17092 for (FunctionType::param_iterator I = FTy->param_begin(),
17093 E = FTy->param_end(); I != E; ++I, ++Idx)
17094 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17095 // FIXME: should only count parameters that are lowered to integers.
17096 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17098 if (InRegCount > 2) {
17099 report_fatal_error("Nest register in use - reduce number of inreg"
17105 case CallingConv::X86_FastCall:
17106 case CallingConv::X86_ThisCall:
17107 case CallingConv::Fast:
17108 // Pass 'nest' parameter in EAX.
17109 // Must be kept in sync with X86CallingConv.td
17110 NestReg = X86::EAX;
17114 SDValue OutChains[4];
17115 SDValue Addr, Disp;
17117 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17118 DAG.getConstant(10, MVT::i32));
17119 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17121 // This is storing the opcode for MOV32ri.
17122 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17123 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17124 OutChains[0] = DAG.getStore(Root, dl,
17125 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17126 Trmp, MachinePointerInfo(TrmpAddr),
17129 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17130 DAG.getConstant(1, MVT::i32));
17131 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17132 MachinePointerInfo(TrmpAddr, 1),
17135 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17136 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17137 DAG.getConstant(5, MVT::i32));
17138 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17139 MachinePointerInfo(TrmpAddr, 5),
17142 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17143 DAG.getConstant(6, MVT::i32));
17144 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17145 MachinePointerInfo(TrmpAddr, 6),
17148 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17152 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17153 SelectionDAG &DAG) const {
17155 The rounding mode is in bits 11:10 of FPSR, and has the following
17157 00 Round to nearest
17162 FLT_ROUNDS, on the other hand, expects the following:
17169 To perform the conversion, we do:
17170 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17173 MachineFunction &MF = DAG.getMachineFunction();
17174 const TargetMachine &TM = MF.getTarget();
17175 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17176 unsigned StackAlignment = TFI.getStackAlignment();
17177 MVT VT = Op.getSimpleValueType();
17180 // Save FP Control Word to stack slot
17181 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17182 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17184 MachineMemOperand *MMO =
17185 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17186 MachineMemOperand::MOStore, 2, 2);
17188 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17189 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17190 DAG.getVTList(MVT::Other),
17191 Ops, MVT::i16, MMO);
17193 // Load FP Control Word from stack slot
17194 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17195 MachinePointerInfo(), false, false, false, 0);
17197 // Transform as necessary
17199 DAG.getNode(ISD::SRL, DL, MVT::i16,
17200 DAG.getNode(ISD::AND, DL, MVT::i16,
17201 CWD, DAG.getConstant(0x800, MVT::i16)),
17202 DAG.getConstant(11, MVT::i8));
17204 DAG.getNode(ISD::SRL, DL, MVT::i16,
17205 DAG.getNode(ISD::AND, DL, MVT::i16,
17206 CWD, DAG.getConstant(0x400, MVT::i16)),
17207 DAG.getConstant(9, MVT::i8));
17210 DAG.getNode(ISD::AND, DL, MVT::i16,
17211 DAG.getNode(ISD::ADD, DL, MVT::i16,
17212 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17213 DAG.getConstant(1, MVT::i16)),
17214 DAG.getConstant(3, MVT::i16));
17216 return DAG.getNode((VT.getSizeInBits() < 16 ?
17217 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17220 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17221 MVT VT = Op.getSimpleValueType();
17223 unsigned NumBits = VT.getSizeInBits();
17226 Op = Op.getOperand(0);
17227 if (VT == MVT::i8) {
17228 // Zero extend to i32 since there is not an i8 bsr.
17230 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17233 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17234 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17235 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17237 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17240 DAG.getConstant(NumBits+NumBits-1, OpVT),
17241 DAG.getConstant(X86::COND_E, MVT::i8),
17244 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17246 // Finally xor with NumBits-1.
17247 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17250 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17254 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17255 MVT VT = Op.getSimpleValueType();
17257 unsigned NumBits = VT.getSizeInBits();
17260 Op = Op.getOperand(0);
17261 if (VT == MVT::i8) {
17262 // Zero extend to i32 since there is not an i8 bsr.
17264 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17267 // Issue a bsr (scan bits in reverse).
17268 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17269 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17271 // And xor with NumBits-1.
17272 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17275 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17279 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17280 MVT VT = Op.getSimpleValueType();
17281 unsigned NumBits = VT.getSizeInBits();
17283 Op = Op.getOperand(0);
17285 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17286 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17287 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17289 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17292 DAG.getConstant(NumBits, VT),
17293 DAG.getConstant(X86::COND_E, MVT::i8),
17296 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17299 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17300 // ones, and then concatenate the result back.
17301 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17302 MVT VT = Op.getSimpleValueType();
17304 assert(VT.is256BitVector() && VT.isInteger() &&
17305 "Unsupported value type for operation");
17307 unsigned NumElems = VT.getVectorNumElements();
17310 // Extract the LHS vectors
17311 SDValue LHS = Op.getOperand(0);
17312 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17313 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17315 // Extract the RHS vectors
17316 SDValue RHS = Op.getOperand(1);
17317 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17318 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17320 MVT EltVT = VT.getVectorElementType();
17321 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17323 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17324 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17325 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17328 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17329 assert(Op.getSimpleValueType().is256BitVector() &&
17330 Op.getSimpleValueType().isInteger() &&
17331 "Only handle AVX 256-bit vector integer operation");
17332 return Lower256IntArith(Op, DAG);
17335 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17336 assert(Op.getSimpleValueType().is256BitVector() &&
17337 Op.getSimpleValueType().isInteger() &&
17338 "Only handle AVX 256-bit vector integer operation");
17339 return Lower256IntArith(Op, DAG);
17342 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17343 SelectionDAG &DAG) {
17345 MVT VT = Op.getSimpleValueType();
17347 // Decompose 256-bit ops into smaller 128-bit ops.
17348 if (VT.is256BitVector() && !Subtarget->hasInt256())
17349 return Lower256IntArith(Op, DAG);
17351 SDValue A = Op.getOperand(0);
17352 SDValue B = Op.getOperand(1);
17354 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17355 if (VT == MVT::v4i32) {
17356 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17357 "Should not custom lower when pmuldq is available!");
17359 // Extract the odd parts.
17360 static const int UnpackMask[] = { 1, -1, 3, -1 };
17361 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17362 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17364 // Multiply the even parts.
17365 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17366 // Now multiply odd parts.
17367 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17369 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17370 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17372 // Merge the two vectors back together with a shuffle. This expands into 2
17374 static const int ShufMask[] = { 0, 4, 2, 6 };
17375 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17378 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17379 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17381 // Ahi = psrlqi(a, 32);
17382 // Bhi = psrlqi(b, 32);
17384 // AloBlo = pmuludq(a, b);
17385 // AloBhi = pmuludq(a, Bhi);
17386 // AhiBlo = pmuludq(Ahi, b);
17388 // AloBhi = psllqi(AloBhi, 32);
17389 // AhiBlo = psllqi(AhiBlo, 32);
17390 // return AloBlo + AloBhi + AhiBlo;
17392 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17393 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17395 // Bit cast to 32-bit vectors for MULUDQ
17396 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17397 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17398 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17399 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17400 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17401 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17403 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17404 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17405 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17407 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17408 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17410 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17411 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17414 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17415 assert(Subtarget->isTargetWin64() && "Unexpected target");
17416 EVT VT = Op.getValueType();
17417 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17418 "Unexpected return type for lowering");
17422 switch (Op->getOpcode()) {
17423 default: llvm_unreachable("Unexpected request for libcall!");
17424 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17425 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17426 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17427 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17428 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17429 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17433 SDValue InChain = DAG.getEntryNode();
17435 TargetLowering::ArgListTy Args;
17436 TargetLowering::ArgListEntry Entry;
17437 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17438 EVT ArgVT = Op->getOperand(i).getValueType();
17439 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17440 "Unexpected argument type for lowering");
17441 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17442 Entry.Node = StackPtr;
17443 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17445 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17446 Entry.Ty = PointerType::get(ArgTy,0);
17447 Entry.isSExt = false;
17448 Entry.isZExt = false;
17449 Args.push_back(Entry);
17452 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17455 TargetLowering::CallLoweringInfo CLI(DAG);
17456 CLI.setDebugLoc(dl).setChain(InChain)
17457 .setCallee(getLibcallCallingConv(LC),
17458 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17459 Callee, std::move(Args), 0)
17460 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17462 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17463 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17466 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17467 SelectionDAG &DAG) {
17468 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17469 EVT VT = Op0.getValueType();
17472 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17473 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17475 // PMULxD operations multiply each even value (starting at 0) of LHS with
17476 // the related value of RHS and produce a widen result.
17477 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17478 // => <2 x i64> <ae|cg>
17480 // In other word, to have all the results, we need to perform two PMULxD:
17481 // 1. one with the even values.
17482 // 2. one with the odd values.
17483 // To achieve #2, with need to place the odd values at an even position.
17485 // Place the odd value at an even position (basically, shift all values 1
17486 // step to the left):
17487 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17488 // <a|b|c|d> => <b|undef|d|undef>
17489 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17490 // <e|f|g|h> => <f|undef|h|undef>
17491 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17493 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17495 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17496 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17498 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17499 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17500 // => <2 x i64> <ae|cg>
17501 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17502 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17503 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17504 // => <2 x i64> <bf|dh>
17505 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17506 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17508 // Shuffle it back into the right order.
17509 SDValue Highs, Lows;
17510 if (VT == MVT::v8i32) {
17511 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17512 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17513 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17514 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17516 const int HighMask[] = {1, 5, 3, 7};
17517 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17518 const int LowMask[] = {0, 4, 2, 6};
17519 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17522 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17523 // unsigned multiply.
17524 if (IsSigned && !Subtarget->hasSSE41()) {
17526 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17527 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17528 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17529 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17530 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17532 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17533 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17536 // The first result of MUL_LOHI is actually the low value, followed by the
17538 SDValue Ops[] = {Lows, Highs};
17539 return DAG.getMergeValues(Ops, dl);
17542 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17543 const X86Subtarget *Subtarget) {
17544 MVT VT = Op.getSimpleValueType();
17546 SDValue R = Op.getOperand(0);
17547 SDValue Amt = Op.getOperand(1);
17549 // Optimize shl/srl/sra with constant shift amount.
17550 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17551 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17552 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17554 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17555 (Subtarget->hasInt256() &&
17556 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17557 (Subtarget->hasAVX512() &&
17558 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17559 if (Op.getOpcode() == ISD::SHL)
17560 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17562 if (Op.getOpcode() == ISD::SRL)
17563 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17565 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17566 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17570 if (VT == MVT::v16i8) {
17571 if (Op.getOpcode() == ISD::SHL) {
17572 // Make a large shift.
17573 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17574 MVT::v8i16, R, ShiftAmt,
17576 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17577 // Zero out the rightmost bits.
17578 SmallVector<SDValue, 16> V(16,
17579 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17581 return DAG.getNode(ISD::AND, dl, VT, SHL,
17582 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17584 if (Op.getOpcode() == ISD::SRL) {
17585 // Make a large shift.
17586 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17587 MVT::v8i16, R, ShiftAmt,
17589 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17590 // Zero out the leftmost bits.
17591 SmallVector<SDValue, 16> V(16,
17592 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17594 return DAG.getNode(ISD::AND, dl, VT, SRL,
17595 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17597 if (Op.getOpcode() == ISD::SRA) {
17598 if (ShiftAmt == 7) {
17599 // R s>> 7 === R s< 0
17600 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17601 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17604 // R s>> a === ((R u>> a) ^ m) - m
17605 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17606 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17608 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17609 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17610 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17613 llvm_unreachable("Unknown shift opcode.");
17616 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17617 if (Op.getOpcode() == ISD::SHL) {
17618 // Make a large shift.
17619 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17620 MVT::v16i16, R, ShiftAmt,
17622 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17623 // Zero out the rightmost bits.
17624 SmallVector<SDValue, 32> V(32,
17625 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17627 return DAG.getNode(ISD::AND, dl, VT, SHL,
17628 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17630 if (Op.getOpcode() == ISD::SRL) {
17631 // Make a large shift.
17632 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17633 MVT::v16i16, R, ShiftAmt,
17635 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17636 // Zero out the leftmost bits.
17637 SmallVector<SDValue, 32> V(32,
17638 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17640 return DAG.getNode(ISD::AND, dl, VT, SRL,
17641 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17643 if (Op.getOpcode() == ISD::SRA) {
17644 if (ShiftAmt == 7) {
17645 // R s>> 7 === R s< 0
17646 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17647 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17650 // R s>> a === ((R u>> a) ^ m) - m
17651 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17652 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17654 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17655 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17656 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17659 llvm_unreachable("Unknown shift opcode.");
17664 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17665 if (!Subtarget->is64Bit() &&
17666 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17667 Amt.getOpcode() == ISD::BITCAST &&
17668 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17669 Amt = Amt.getOperand(0);
17670 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17671 VT.getVectorNumElements();
17672 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17673 uint64_t ShiftAmt = 0;
17674 for (unsigned i = 0; i != Ratio; ++i) {
17675 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17679 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17681 // Check remaining shift amounts.
17682 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17683 uint64_t ShAmt = 0;
17684 for (unsigned j = 0; j != Ratio; ++j) {
17685 ConstantSDNode *C =
17686 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17690 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17692 if (ShAmt != ShiftAmt)
17695 switch (Op.getOpcode()) {
17697 llvm_unreachable("Unknown shift opcode!");
17699 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17702 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17705 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17713 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17714 const X86Subtarget* Subtarget) {
17715 MVT VT = Op.getSimpleValueType();
17717 SDValue R = Op.getOperand(0);
17718 SDValue Amt = Op.getOperand(1);
17720 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17721 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17722 (Subtarget->hasInt256() &&
17723 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17724 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17725 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17727 EVT EltVT = VT.getVectorElementType();
17729 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17730 unsigned NumElts = VT.getVectorNumElements();
17732 for (i = 0; i != NumElts; ++i) {
17733 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17737 for (j = i; j != NumElts; ++j) {
17738 SDValue Arg = Amt.getOperand(j);
17739 if (Arg.getOpcode() == ISD::UNDEF) continue;
17740 if (Arg != Amt.getOperand(i))
17743 if (i != NumElts && j == NumElts)
17744 BaseShAmt = Amt.getOperand(i);
17746 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17747 Amt = Amt.getOperand(0);
17748 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17749 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17750 SDValue InVec = Amt.getOperand(0);
17751 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17752 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17754 for (; i != NumElts; ++i) {
17755 SDValue Arg = InVec.getOperand(i);
17756 if (Arg.getOpcode() == ISD::UNDEF) continue;
17760 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17761 if (ConstantSDNode *C =
17762 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17763 unsigned SplatIdx =
17764 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17765 if (C->getZExtValue() == SplatIdx)
17766 BaseShAmt = InVec.getOperand(1);
17769 if (!BaseShAmt.getNode())
17770 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17771 DAG.getIntPtrConstant(0));
17775 if (BaseShAmt.getNode()) {
17776 if (EltVT.bitsGT(MVT::i32))
17777 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17778 else if (EltVT.bitsLT(MVT::i32))
17779 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17781 switch (Op.getOpcode()) {
17783 llvm_unreachable("Unknown shift opcode!");
17785 switch (VT.SimpleTy) {
17786 default: return SDValue();
17795 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17798 switch (VT.SimpleTy) {
17799 default: return SDValue();
17806 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17809 switch (VT.SimpleTy) {
17810 default: return SDValue();
17819 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17825 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17826 if (!Subtarget->is64Bit() &&
17827 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17828 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17829 Amt.getOpcode() == ISD::BITCAST &&
17830 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17831 Amt = Amt.getOperand(0);
17832 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17833 VT.getVectorNumElements();
17834 std::vector<SDValue> Vals(Ratio);
17835 for (unsigned i = 0; i != Ratio; ++i)
17836 Vals[i] = Amt.getOperand(i);
17837 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17838 for (unsigned j = 0; j != Ratio; ++j)
17839 if (Vals[j] != Amt.getOperand(i + j))
17842 switch (Op.getOpcode()) {
17844 llvm_unreachable("Unknown shift opcode!");
17846 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17848 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17850 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17857 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17858 SelectionDAG &DAG) {
17859 MVT VT = Op.getSimpleValueType();
17861 SDValue R = Op.getOperand(0);
17862 SDValue Amt = Op.getOperand(1);
17865 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17866 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17868 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17872 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17876 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17878 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17879 if (Subtarget->hasInt256()) {
17880 if (Op.getOpcode() == ISD::SRL &&
17881 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17882 VT == MVT::v4i64 || VT == MVT::v8i32))
17884 if (Op.getOpcode() == ISD::SHL &&
17885 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17886 VT == MVT::v4i64 || VT == MVT::v8i32))
17888 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17892 // If possible, lower this packed shift into a vector multiply instead of
17893 // expanding it into a sequence of scalar shifts.
17894 // Do this only if the vector shift count is a constant build_vector.
17895 if (Op.getOpcode() == ISD::SHL &&
17896 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17897 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17898 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17899 SmallVector<SDValue, 8> Elts;
17900 EVT SVT = VT.getScalarType();
17901 unsigned SVTBits = SVT.getSizeInBits();
17902 const APInt &One = APInt(SVTBits, 1);
17903 unsigned NumElems = VT.getVectorNumElements();
17905 for (unsigned i=0; i !=NumElems; ++i) {
17906 SDValue Op = Amt->getOperand(i);
17907 if (Op->getOpcode() == ISD::UNDEF) {
17908 Elts.push_back(Op);
17912 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17913 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17914 uint64_t ShAmt = C.getZExtValue();
17915 if (ShAmt >= SVTBits) {
17916 Elts.push_back(DAG.getUNDEF(SVT));
17919 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17921 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17922 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17925 // Lower SHL with variable shift amount.
17926 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17927 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17929 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17930 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17931 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17932 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17935 // If possible, lower this shift as a sequence of two shifts by
17936 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17938 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17940 // Could be rewritten as:
17941 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17943 // The advantage is that the two shifts from the example would be
17944 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17945 // the vector shift into four scalar shifts plus four pairs of vector
17947 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17948 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17949 unsigned TargetOpcode = X86ISD::MOVSS;
17950 bool CanBeSimplified;
17951 // The splat value for the first packed shift (the 'X' from the example).
17952 SDValue Amt1 = Amt->getOperand(0);
17953 // The splat value for the second packed shift (the 'Y' from the example).
17954 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17955 Amt->getOperand(2);
17957 // See if it is possible to replace this node with a sequence of
17958 // two shifts followed by a MOVSS/MOVSD
17959 if (VT == MVT::v4i32) {
17960 // Check if it is legal to use a MOVSS.
17961 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17962 Amt2 == Amt->getOperand(3);
17963 if (!CanBeSimplified) {
17964 // Otherwise, check if we can still simplify this node using a MOVSD.
17965 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17966 Amt->getOperand(2) == Amt->getOperand(3);
17967 TargetOpcode = X86ISD::MOVSD;
17968 Amt2 = Amt->getOperand(2);
17971 // Do similar checks for the case where the machine value type
17973 CanBeSimplified = Amt1 == Amt->getOperand(1);
17974 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17975 CanBeSimplified = Amt2 == Amt->getOperand(i);
17977 if (!CanBeSimplified) {
17978 TargetOpcode = X86ISD::MOVSD;
17979 CanBeSimplified = true;
17980 Amt2 = Amt->getOperand(4);
17981 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17982 CanBeSimplified = Amt1 == Amt->getOperand(i);
17983 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17984 CanBeSimplified = Amt2 == Amt->getOperand(j);
17988 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17989 isa<ConstantSDNode>(Amt2)) {
17990 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17991 EVT CastVT = MVT::v4i32;
17993 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17994 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17996 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17997 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17998 if (TargetOpcode == X86ISD::MOVSD)
17999 CastVT = MVT::v2i64;
18000 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18001 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18002 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18004 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18008 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18009 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18012 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18013 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18015 // Turn 'a' into a mask suitable for VSELECT
18016 SDValue VSelM = DAG.getConstant(0x80, VT);
18017 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18018 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18020 SDValue CM1 = DAG.getConstant(0x0f, VT);
18021 SDValue CM2 = DAG.getConstant(0x3f, VT);
18023 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18024 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18025 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18026 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18027 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18030 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18031 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18032 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18034 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18035 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18036 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18037 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18038 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18041 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18042 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18043 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18045 // return VSELECT(r, r+r, a);
18046 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18047 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18051 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18052 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18053 // solution better.
18054 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18055 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18057 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18058 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18059 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18060 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18061 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18064 // Decompose 256-bit shifts into smaller 128-bit shifts.
18065 if (VT.is256BitVector()) {
18066 unsigned NumElems = VT.getVectorNumElements();
18067 MVT EltVT = VT.getVectorElementType();
18068 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18070 // Extract the two vectors
18071 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18072 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18074 // Recreate the shift amount vectors
18075 SDValue Amt1, Amt2;
18076 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18077 // Constant shift amount
18078 SmallVector<SDValue, 4> Amt1Csts;
18079 SmallVector<SDValue, 4> Amt2Csts;
18080 for (unsigned i = 0; i != NumElems/2; ++i)
18081 Amt1Csts.push_back(Amt->getOperand(i));
18082 for (unsigned i = NumElems/2; i != NumElems; ++i)
18083 Amt2Csts.push_back(Amt->getOperand(i));
18085 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18086 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18088 // Variable shift amount
18089 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18090 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18093 // Issue new vector shifts for the smaller types
18094 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18095 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18097 // Concatenate the result back
18098 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18104 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18105 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18106 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18107 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18108 // has only one use.
18109 SDNode *N = Op.getNode();
18110 SDValue LHS = N->getOperand(0);
18111 SDValue RHS = N->getOperand(1);
18112 unsigned BaseOp = 0;
18115 switch (Op.getOpcode()) {
18116 default: llvm_unreachable("Unknown ovf instruction!");
18118 // A subtract of one will be selected as a INC. Note that INC doesn't
18119 // set CF, so we can't do this for UADDO.
18120 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18122 BaseOp = X86ISD::INC;
18123 Cond = X86::COND_O;
18126 BaseOp = X86ISD::ADD;
18127 Cond = X86::COND_O;
18130 BaseOp = X86ISD::ADD;
18131 Cond = X86::COND_B;
18134 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18135 // set CF, so we can't do this for USUBO.
18136 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18138 BaseOp = X86ISD::DEC;
18139 Cond = X86::COND_O;
18142 BaseOp = X86ISD::SUB;
18143 Cond = X86::COND_O;
18146 BaseOp = X86ISD::SUB;
18147 Cond = X86::COND_B;
18150 BaseOp = X86ISD::SMUL;
18151 Cond = X86::COND_O;
18153 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18154 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18156 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18159 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18160 DAG.getConstant(X86::COND_O, MVT::i32),
18161 SDValue(Sum.getNode(), 2));
18163 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18167 // Also sets EFLAGS.
18168 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18169 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18172 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18173 DAG.getConstant(Cond, MVT::i32),
18174 SDValue(Sum.getNode(), 1));
18176 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18179 // Sign extension of the low part of vector elements. This may be used either
18180 // when sign extend instructions are not available or if the vector element
18181 // sizes already match the sign-extended size. If the vector elements are in
18182 // their pre-extended size and sign extend instructions are available, that will
18183 // be handled by LowerSIGN_EXTEND.
18184 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18185 SelectionDAG &DAG) const {
18187 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18188 MVT VT = Op.getSimpleValueType();
18190 if (!Subtarget->hasSSE2() || !VT.isVector())
18193 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18194 ExtraVT.getScalarType().getSizeInBits();
18196 switch (VT.SimpleTy) {
18197 default: return SDValue();
18200 if (!Subtarget->hasFp256())
18202 if (!Subtarget->hasInt256()) {
18203 // needs to be split
18204 unsigned NumElems = VT.getVectorNumElements();
18206 // Extract the LHS vectors
18207 SDValue LHS = Op.getOperand(0);
18208 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18209 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18211 MVT EltVT = VT.getVectorElementType();
18212 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18214 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18215 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18216 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18218 SDValue Extra = DAG.getValueType(ExtraVT);
18220 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18221 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18223 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18228 SDValue Op0 = Op.getOperand(0);
18230 // This is a sign extension of some low part of vector elements without
18231 // changing the size of the vector elements themselves:
18232 // Shift-Left + Shift-Right-Algebraic.
18233 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18235 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18241 /// Returns true if the operand type is exactly twice the native width, and
18242 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18243 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18244 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18245 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18246 const X86Subtarget &Subtarget =
18247 getTargetMachine().getSubtarget<X86Subtarget>();
18248 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18251 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18252 else if (OpWidth == 128)
18253 return Subtarget.hasCmpxchg16b();
18258 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18259 return needsCmpXchgNb(SI->getValueOperand()->getType());
18262 // Note: this turns large loads into lock cmpxchg8b/16b.
18263 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18264 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18265 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18266 return needsCmpXchgNb(PTy->getElementType());
18269 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18270 const X86Subtarget &Subtarget =
18271 getTargetMachine().getSubtarget<X86Subtarget>();
18272 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18273 const Type *MemType = AI->getType();
18275 // If the operand is too big, we must see if cmpxchg8/16b is available
18276 // and default to library calls otherwise.
18277 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18278 return needsCmpXchgNb(MemType);
18280 AtomicRMWInst::BinOp Op = AI->getOperation();
18283 llvm_unreachable("Unknown atomic operation");
18284 case AtomicRMWInst::Xchg:
18285 case AtomicRMWInst::Add:
18286 case AtomicRMWInst::Sub:
18287 // It's better to use xadd, xsub or xchg for these in all cases.
18289 case AtomicRMWInst::Or:
18290 case AtomicRMWInst::And:
18291 case AtomicRMWInst::Xor:
18292 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18293 // prefix to a normal instruction for these operations.
18294 return !AI->use_empty();
18295 case AtomicRMWInst::Nand:
18296 case AtomicRMWInst::Max:
18297 case AtomicRMWInst::Min:
18298 case AtomicRMWInst::UMax:
18299 case AtomicRMWInst::UMin:
18300 // These always require a non-trivial set of data operations on x86. We must
18301 // use a cmpxchg loop.
18306 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18307 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18308 // no-sse2). There isn't any reason to disable it if the target processor
18310 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18314 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18315 const X86Subtarget &Subtarget =
18316 getTargetMachine().getSubtarget<X86Subtarget>();
18317 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18318 const Type *MemType = AI->getType();
18319 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18320 // there is no benefit in turning such RMWs into loads, and it is actually
18321 // harmful as it introduces a mfence.
18322 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18325 auto Builder = IRBuilder<>(AI);
18326 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18327 auto SynchScope = AI->getSynchScope();
18328 // We must restrict the ordering to avoid generating loads with Release or
18329 // ReleaseAcquire orderings.
18330 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18331 auto Ptr = AI->getPointerOperand();
18333 // Before the load we need a fence. Here is an example lifted from
18334 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18337 // x.store(1, relaxed);
18338 // r1 = y.fetch_add(0, release);
18340 // y.fetch_add(42, acquire);
18341 // r2 = x.load(relaxed);
18342 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18343 // lowered to just a load without a fence. A mfence flushes the store buffer,
18344 // making the optimization clearly correct.
18345 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18346 // otherwise, we might be able to be more agressive on relaxed idempotent
18347 // rmw. In practice, they do not look useful, so we don't try to be
18348 // especially clever.
18349 if (SynchScope == SingleThread) {
18350 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18351 // the IR level, so we must wrap it in an intrinsic.
18353 } else if (hasMFENCE(Subtarget)) {
18354 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18355 Intrinsic::x86_sse2_mfence);
18356 Builder.CreateCall(MFence);
18358 // FIXME: it might make sense to use a locked operation here but on a
18359 // different cache-line to prevent cache-line bouncing. In practice it
18360 // is probably a small win, and x86 processors without mfence are rare
18361 // enough that we do not bother.
18365 // Finally we can emit the atomic load.
18366 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18367 AI->getType()->getPrimitiveSizeInBits());
18368 Loaded->setAtomic(Order, SynchScope);
18369 AI->replaceAllUsesWith(Loaded);
18370 AI->eraseFromParent();
18374 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18375 SelectionDAG &DAG) {
18377 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18378 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18379 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18380 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18382 // The only fence that needs an instruction is a sequentially-consistent
18383 // cross-thread fence.
18384 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18385 if (hasMFENCE(*Subtarget))
18386 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18388 SDValue Chain = Op.getOperand(0);
18389 SDValue Zero = DAG.getConstant(0, MVT::i32);
18391 DAG.getRegister(X86::ESP, MVT::i32), // Base
18392 DAG.getTargetConstant(1, MVT::i8), // Scale
18393 DAG.getRegister(0, MVT::i32), // Index
18394 DAG.getTargetConstant(0, MVT::i32), // Disp
18395 DAG.getRegister(0, MVT::i32), // Segment.
18399 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18400 return SDValue(Res, 0);
18403 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18404 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18407 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18408 SelectionDAG &DAG) {
18409 MVT T = Op.getSimpleValueType();
18413 switch(T.SimpleTy) {
18414 default: llvm_unreachable("Invalid value type!");
18415 case MVT::i8: Reg = X86::AL; size = 1; break;
18416 case MVT::i16: Reg = X86::AX; size = 2; break;
18417 case MVT::i32: Reg = X86::EAX; size = 4; break;
18419 assert(Subtarget->is64Bit() && "Node not type legal!");
18420 Reg = X86::RAX; size = 8;
18423 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18424 Op.getOperand(2), SDValue());
18425 SDValue Ops[] = { cpIn.getValue(0),
18428 DAG.getTargetConstant(size, MVT::i8),
18429 cpIn.getValue(1) };
18430 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18431 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18432 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18436 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18437 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18438 MVT::i32, cpOut.getValue(2));
18439 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18440 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18442 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18443 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18444 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18448 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18449 SelectionDAG &DAG) {
18450 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18451 MVT DstVT = Op.getSimpleValueType();
18453 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18454 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18455 if (DstVT != MVT::f64)
18456 // This conversion needs to be expanded.
18459 SDValue InVec = Op->getOperand(0);
18461 unsigned NumElts = SrcVT.getVectorNumElements();
18462 EVT SVT = SrcVT.getVectorElementType();
18464 // Widen the vector in input in the case of MVT::v2i32.
18465 // Example: from MVT::v2i32 to MVT::v4i32.
18466 SmallVector<SDValue, 16> Elts;
18467 for (unsigned i = 0, e = NumElts; i != e; ++i)
18468 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18469 DAG.getIntPtrConstant(i)));
18471 // Explicitly mark the extra elements as Undef.
18472 SDValue Undef = DAG.getUNDEF(SVT);
18473 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18474 Elts.push_back(Undef);
18476 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18477 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18478 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18479 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18480 DAG.getIntPtrConstant(0));
18483 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18484 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18485 assert((DstVT == MVT::i64 ||
18486 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18487 "Unexpected custom BITCAST");
18488 // i64 <=> MMX conversions are Legal.
18489 if (SrcVT==MVT::i64 && DstVT.isVector())
18491 if (DstVT==MVT::i64 && SrcVT.isVector())
18493 // MMX <=> MMX conversions are Legal.
18494 if (SrcVT.isVector() && DstVT.isVector())
18496 // All other conversions need to be expanded.
18500 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18501 SDNode *Node = Op.getNode();
18503 EVT T = Node->getValueType(0);
18504 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18505 DAG.getConstant(0, T), Node->getOperand(2));
18506 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18507 cast<AtomicSDNode>(Node)->getMemoryVT(),
18508 Node->getOperand(0),
18509 Node->getOperand(1), negOp,
18510 cast<AtomicSDNode>(Node)->getMemOperand(),
18511 cast<AtomicSDNode>(Node)->getOrdering(),
18512 cast<AtomicSDNode>(Node)->getSynchScope());
18515 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18516 SDNode *Node = Op.getNode();
18518 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18520 // Convert seq_cst store -> xchg
18521 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18522 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18523 // (The only way to get a 16-byte store is cmpxchg16b)
18524 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18525 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18526 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18527 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18528 cast<AtomicSDNode>(Node)->getMemoryVT(),
18529 Node->getOperand(0),
18530 Node->getOperand(1), Node->getOperand(2),
18531 cast<AtomicSDNode>(Node)->getMemOperand(),
18532 cast<AtomicSDNode>(Node)->getOrdering(),
18533 cast<AtomicSDNode>(Node)->getSynchScope());
18534 return Swap.getValue(1);
18536 // Other atomic stores have a simple pattern.
18540 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18541 EVT VT = Op.getNode()->getSimpleValueType(0);
18543 // Let legalize expand this if it isn't a legal type yet.
18544 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18547 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18550 bool ExtraOp = false;
18551 switch (Op.getOpcode()) {
18552 default: llvm_unreachable("Invalid code");
18553 case ISD::ADDC: Opc = X86ISD::ADD; break;
18554 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18555 case ISD::SUBC: Opc = X86ISD::SUB; break;
18556 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18560 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18562 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18563 Op.getOperand(1), Op.getOperand(2));
18566 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18567 SelectionDAG &DAG) {
18568 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18570 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18571 // which returns the values as { float, float } (in XMM0) or
18572 // { double, double } (which is returned in XMM0, XMM1).
18574 SDValue Arg = Op.getOperand(0);
18575 EVT ArgVT = Arg.getValueType();
18576 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18578 TargetLowering::ArgListTy Args;
18579 TargetLowering::ArgListEntry Entry;
18583 Entry.isSExt = false;
18584 Entry.isZExt = false;
18585 Args.push_back(Entry);
18587 bool isF64 = ArgVT == MVT::f64;
18588 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18589 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18590 // the results are returned via SRet in memory.
18591 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18592 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18593 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18595 Type *RetTy = isF64
18596 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18597 : (Type*)VectorType::get(ArgTy, 4);
18599 TargetLowering::CallLoweringInfo CLI(DAG);
18600 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18601 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18603 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18606 // Returned in xmm0 and xmm1.
18607 return CallResult.first;
18609 // Returned in bits 0:31 and 32:64 xmm0.
18610 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18611 CallResult.first, DAG.getIntPtrConstant(0));
18612 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18613 CallResult.first, DAG.getIntPtrConstant(1));
18614 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18615 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18618 /// LowerOperation - Provide custom lowering hooks for some operations.
18620 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18621 switch (Op.getOpcode()) {
18622 default: llvm_unreachable("Should not custom lower this!");
18623 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18624 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18625 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18626 return LowerCMP_SWAP(Op, Subtarget, DAG);
18627 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18628 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18629 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18630 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18631 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18632 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18633 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18634 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18635 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18636 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18637 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18638 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18639 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18640 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18641 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18642 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18643 case ISD::SHL_PARTS:
18644 case ISD::SRA_PARTS:
18645 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18646 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18647 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18648 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18649 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18650 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18651 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18652 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18653 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18654 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18655 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18657 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18658 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18659 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18660 case ISD::SETCC: return LowerSETCC(Op, DAG);
18661 case ISD::SELECT: return LowerSELECT(Op, DAG);
18662 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18663 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18664 case ISD::VASTART: return LowerVASTART(Op, DAG);
18665 case ISD::VAARG: return LowerVAARG(Op, DAG);
18666 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18667 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18668 case ISD::INTRINSIC_VOID:
18669 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18670 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18671 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18672 case ISD::FRAME_TO_ARGS_OFFSET:
18673 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18674 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18675 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18676 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18677 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18678 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18679 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18680 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18681 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18682 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18683 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18684 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18685 case ISD::UMUL_LOHI:
18686 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18689 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18695 case ISD::UMULO: return LowerXALUO(Op, DAG);
18696 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18697 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18701 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18702 case ISD::ADD: return LowerADD(Op, DAG);
18703 case ISD::SUB: return LowerSUB(Op, DAG);
18704 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18708 /// ReplaceNodeResults - Replace a node with an illegal result type
18709 /// with a new node built out of custom code.
18710 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18711 SmallVectorImpl<SDValue>&Results,
18712 SelectionDAG &DAG) const {
18714 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18715 switch (N->getOpcode()) {
18717 llvm_unreachable("Do not know how to custom type legalize this operation!");
18718 case ISD::SIGN_EXTEND_INREG:
18723 // We don't want to expand or promote these.
18730 case ISD::UDIVREM: {
18731 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18732 Results.push_back(V);
18735 case ISD::FP_TO_SINT:
18736 case ISD::FP_TO_UINT: {
18737 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18739 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18742 std::pair<SDValue,SDValue> Vals =
18743 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18744 SDValue FIST = Vals.first, StackSlot = Vals.second;
18745 if (FIST.getNode()) {
18746 EVT VT = N->getValueType(0);
18747 // Return a load from the stack slot.
18748 if (StackSlot.getNode())
18749 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18750 MachinePointerInfo(),
18751 false, false, false, 0));
18753 Results.push_back(FIST);
18757 case ISD::UINT_TO_FP: {
18758 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18759 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18760 N->getValueType(0) != MVT::v2f32)
18762 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18764 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18766 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18767 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18768 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18769 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18770 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18771 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18774 case ISD::FP_ROUND: {
18775 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18777 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18778 Results.push_back(V);
18781 case ISD::INTRINSIC_W_CHAIN: {
18782 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18784 default : llvm_unreachable("Do not know how to custom type "
18785 "legalize this intrinsic operation!");
18786 case Intrinsic::x86_rdtsc:
18787 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18789 case Intrinsic::x86_rdtscp:
18790 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18792 case Intrinsic::x86_rdpmc:
18793 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18796 case ISD::READCYCLECOUNTER: {
18797 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18800 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18801 EVT T = N->getValueType(0);
18802 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18803 bool Regs64bit = T == MVT::i128;
18804 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18805 SDValue cpInL, cpInH;
18806 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18807 DAG.getConstant(0, HalfT));
18808 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18809 DAG.getConstant(1, HalfT));
18810 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18811 Regs64bit ? X86::RAX : X86::EAX,
18813 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18814 Regs64bit ? X86::RDX : X86::EDX,
18815 cpInH, cpInL.getValue(1));
18816 SDValue swapInL, swapInH;
18817 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18818 DAG.getConstant(0, HalfT));
18819 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18820 DAG.getConstant(1, HalfT));
18821 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18822 Regs64bit ? X86::RBX : X86::EBX,
18823 swapInL, cpInH.getValue(1));
18824 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18825 Regs64bit ? X86::RCX : X86::ECX,
18826 swapInH, swapInL.getValue(1));
18827 SDValue Ops[] = { swapInH.getValue(0),
18829 swapInH.getValue(1) };
18830 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18831 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18832 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18833 X86ISD::LCMPXCHG8_DAG;
18834 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18835 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18836 Regs64bit ? X86::RAX : X86::EAX,
18837 HalfT, Result.getValue(1));
18838 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18839 Regs64bit ? X86::RDX : X86::EDX,
18840 HalfT, cpOutL.getValue(2));
18841 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18843 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18844 MVT::i32, cpOutH.getValue(2));
18846 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18847 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18848 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18850 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18851 Results.push_back(Success);
18852 Results.push_back(EFLAGS.getValue(1));
18855 case ISD::ATOMIC_SWAP:
18856 case ISD::ATOMIC_LOAD_ADD:
18857 case ISD::ATOMIC_LOAD_SUB:
18858 case ISD::ATOMIC_LOAD_AND:
18859 case ISD::ATOMIC_LOAD_OR:
18860 case ISD::ATOMIC_LOAD_XOR:
18861 case ISD::ATOMIC_LOAD_NAND:
18862 case ISD::ATOMIC_LOAD_MIN:
18863 case ISD::ATOMIC_LOAD_MAX:
18864 case ISD::ATOMIC_LOAD_UMIN:
18865 case ISD::ATOMIC_LOAD_UMAX:
18866 case ISD::ATOMIC_LOAD: {
18867 // Delegate to generic TypeLegalization. Situations we can really handle
18868 // should have already been dealt with by AtomicExpandPass.cpp.
18871 case ISD::BITCAST: {
18872 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18873 EVT DstVT = N->getValueType(0);
18874 EVT SrcVT = N->getOperand(0)->getValueType(0);
18876 if (SrcVT != MVT::f64 ||
18877 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18880 unsigned NumElts = DstVT.getVectorNumElements();
18881 EVT SVT = DstVT.getVectorElementType();
18882 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18883 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18884 MVT::v2f64, N->getOperand(0));
18885 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18887 if (ExperimentalVectorWideningLegalization) {
18888 // If we are legalizing vectors by widening, we already have the desired
18889 // legal vector type, just return it.
18890 Results.push_back(ToVecInt);
18894 SmallVector<SDValue, 8> Elts;
18895 for (unsigned i = 0, e = NumElts; i != e; ++i)
18896 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18897 ToVecInt, DAG.getIntPtrConstant(i)));
18899 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18904 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18906 default: return nullptr;
18907 case X86ISD::BSF: return "X86ISD::BSF";
18908 case X86ISD::BSR: return "X86ISD::BSR";
18909 case X86ISD::SHLD: return "X86ISD::SHLD";
18910 case X86ISD::SHRD: return "X86ISD::SHRD";
18911 case X86ISD::FAND: return "X86ISD::FAND";
18912 case X86ISD::FANDN: return "X86ISD::FANDN";
18913 case X86ISD::FOR: return "X86ISD::FOR";
18914 case X86ISD::FXOR: return "X86ISD::FXOR";
18915 case X86ISD::FSRL: return "X86ISD::FSRL";
18916 case X86ISD::FILD: return "X86ISD::FILD";
18917 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18918 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18919 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18920 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18921 case X86ISD::FLD: return "X86ISD::FLD";
18922 case X86ISD::FST: return "X86ISD::FST";
18923 case X86ISD::CALL: return "X86ISD::CALL";
18924 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18925 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18926 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18927 case X86ISD::BT: return "X86ISD::BT";
18928 case X86ISD::CMP: return "X86ISD::CMP";
18929 case X86ISD::COMI: return "X86ISD::COMI";
18930 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18931 case X86ISD::CMPM: return "X86ISD::CMPM";
18932 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18933 case X86ISD::SETCC: return "X86ISD::SETCC";
18934 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18935 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18936 case X86ISD::CMOV: return "X86ISD::CMOV";
18937 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18938 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18939 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18940 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18941 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18942 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18943 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18944 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18945 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18946 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18947 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18948 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18949 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18950 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18951 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18952 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18953 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18954 case X86ISD::HADD: return "X86ISD::HADD";
18955 case X86ISD::HSUB: return "X86ISD::HSUB";
18956 case X86ISD::FHADD: return "X86ISD::FHADD";
18957 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18958 case X86ISD::UMAX: return "X86ISD::UMAX";
18959 case X86ISD::UMIN: return "X86ISD::UMIN";
18960 case X86ISD::SMAX: return "X86ISD::SMAX";
18961 case X86ISD::SMIN: return "X86ISD::SMIN";
18962 case X86ISD::FMAX: return "X86ISD::FMAX";
18963 case X86ISD::FMIN: return "X86ISD::FMIN";
18964 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18965 case X86ISD::FMINC: return "X86ISD::FMINC";
18966 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18967 case X86ISD::FRCP: return "X86ISD::FRCP";
18968 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18969 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18970 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18971 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18972 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18973 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18974 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18975 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18976 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18977 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18978 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18979 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18980 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18981 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18982 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18983 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18984 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18985 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18986 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18987 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18988 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18989 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18990 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18991 case X86ISD::VSHL: return "X86ISD::VSHL";
18992 case X86ISD::VSRL: return "X86ISD::VSRL";
18993 case X86ISD::VSRA: return "X86ISD::VSRA";
18994 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18995 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18996 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18997 case X86ISD::CMPP: return "X86ISD::CMPP";
18998 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18999 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19000 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19001 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19002 case X86ISD::ADD: return "X86ISD::ADD";
19003 case X86ISD::SUB: return "X86ISD::SUB";
19004 case X86ISD::ADC: return "X86ISD::ADC";
19005 case X86ISD::SBB: return "X86ISD::SBB";
19006 case X86ISD::SMUL: return "X86ISD::SMUL";
19007 case X86ISD::UMUL: return "X86ISD::UMUL";
19008 case X86ISD::INC: return "X86ISD::INC";
19009 case X86ISD::DEC: return "X86ISD::DEC";
19010 case X86ISD::OR: return "X86ISD::OR";
19011 case X86ISD::XOR: return "X86ISD::XOR";
19012 case X86ISD::AND: return "X86ISD::AND";
19013 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19014 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19015 case X86ISD::PTEST: return "X86ISD::PTEST";
19016 case X86ISD::TESTP: return "X86ISD::TESTP";
19017 case X86ISD::TESTM: return "X86ISD::TESTM";
19018 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19019 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19020 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19021 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19022 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19023 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19024 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19025 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19026 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19027 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19028 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19029 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19030 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19031 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19032 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19033 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19034 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19035 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19036 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19037 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19038 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19039 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19040 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19041 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19042 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19043 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19044 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19045 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19046 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19047 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19048 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19049 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19050 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19051 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19052 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19053 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19054 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19055 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19056 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19057 case X86ISD::SAHF: return "X86ISD::SAHF";
19058 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19059 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19060 case X86ISD::FMADD: return "X86ISD::FMADD";
19061 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19062 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19063 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19064 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19065 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19066 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19067 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19068 case X86ISD::XTEST: return "X86ISD::XTEST";
19072 // isLegalAddressingMode - Return true if the addressing mode represented
19073 // by AM is legal for this target, for a load/store of the specified type.
19074 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19076 // X86 supports extremely general addressing modes.
19077 CodeModel::Model M = getTargetMachine().getCodeModel();
19078 Reloc::Model R = getTargetMachine().getRelocationModel();
19080 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19081 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19086 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19088 // If a reference to this global requires an extra load, we can't fold it.
19089 if (isGlobalStubReference(GVFlags))
19092 // If BaseGV requires a register for the PIC base, we cannot also have a
19093 // BaseReg specified.
19094 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19097 // If lower 4G is not available, then we must use rip-relative addressing.
19098 if ((M != CodeModel::Small || R != Reloc::Static) &&
19099 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19103 switch (AM.Scale) {
19109 // These scales always work.
19114 // These scales are formed with basereg+scalereg. Only accept if there is
19119 default: // Other stuff never works.
19126 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19127 unsigned Bits = Ty->getScalarSizeInBits();
19129 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19130 // particularly cheaper than those without.
19134 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19135 // variable shifts just as cheap as scalar ones.
19136 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19139 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19140 // fully general vector.
19144 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19145 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19147 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19148 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19149 return NumBits1 > NumBits2;
19152 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19153 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19156 if (!isTypeLegal(EVT::getEVT(Ty1)))
19159 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19161 // Assuming the caller doesn't have a zeroext or signext return parameter,
19162 // truncation all the way down to i1 is valid.
19166 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19167 return isInt<32>(Imm);
19170 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19171 // Can also use sub to handle negated immediates.
19172 return isInt<32>(Imm);
19175 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19176 if (!VT1.isInteger() || !VT2.isInteger())
19178 unsigned NumBits1 = VT1.getSizeInBits();
19179 unsigned NumBits2 = VT2.getSizeInBits();
19180 return NumBits1 > NumBits2;
19183 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19184 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19185 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19188 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19189 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19190 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19193 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19194 EVT VT1 = Val.getValueType();
19195 if (isZExtFree(VT1, VT2))
19198 if (Val.getOpcode() != ISD::LOAD)
19201 if (!VT1.isSimple() || !VT1.isInteger() ||
19202 !VT2.isSimple() || !VT2.isInteger())
19205 switch (VT1.getSimpleVT().SimpleTy) {
19210 // X86 has 8, 16, and 32-bit zero-extending loads.
19218 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19219 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19222 VT = VT.getScalarType();
19224 if (!VT.isSimple())
19227 switch (VT.getSimpleVT().SimpleTy) {
19238 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19239 // i16 instructions are longer (0x66 prefix) and potentially slower.
19240 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19243 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19244 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19245 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19246 /// are assumed to be legal.
19248 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19250 if (!VT.isSimple())
19253 MVT SVT = VT.getSimpleVT();
19255 // Very little shuffling can be done for 64-bit vectors right now.
19256 if (VT.getSizeInBits() == 64)
19259 // If this is a single-input shuffle with no 128 bit lane crossings we can
19260 // lower it into pshufb.
19261 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19262 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19263 bool isLegal = true;
19264 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19265 if (M[I] >= (int)SVT.getVectorNumElements() ||
19266 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19275 // FIXME: blends, shifts.
19276 return (SVT.getVectorNumElements() == 2 ||
19277 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19278 isMOVLMask(M, SVT) ||
19279 isMOVHLPSMask(M, SVT) ||
19280 isSHUFPMask(M, SVT) ||
19281 isPSHUFDMask(M, SVT) ||
19282 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19283 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19284 isPALIGNRMask(M, SVT, Subtarget) ||
19285 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19286 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19287 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19288 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19289 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
19293 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19295 if (!VT.isSimple())
19298 MVT SVT = VT.getSimpleVT();
19299 unsigned NumElts = SVT.getVectorNumElements();
19300 // FIXME: This collection of masks seems suspect.
19303 if (NumElts == 4 && SVT.is128BitVector()) {
19304 return (isMOVLMask(Mask, SVT) ||
19305 isCommutedMOVLMask(Mask, SVT, true) ||
19306 isSHUFPMask(Mask, SVT) ||
19307 isSHUFPMask(Mask, SVT, /* Commuted */ true));
19312 //===----------------------------------------------------------------------===//
19313 // X86 Scheduler Hooks
19314 //===----------------------------------------------------------------------===//
19316 /// Utility function to emit xbegin specifying the start of an RTM region.
19317 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19318 const TargetInstrInfo *TII) {
19319 DebugLoc DL = MI->getDebugLoc();
19321 const BasicBlock *BB = MBB->getBasicBlock();
19322 MachineFunction::iterator I = MBB;
19325 // For the v = xbegin(), we generate
19336 MachineBasicBlock *thisMBB = MBB;
19337 MachineFunction *MF = MBB->getParent();
19338 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19339 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19340 MF->insert(I, mainMBB);
19341 MF->insert(I, sinkMBB);
19343 // Transfer the remainder of BB and its successor edges to sinkMBB.
19344 sinkMBB->splice(sinkMBB->begin(), MBB,
19345 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19346 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19350 // # fallthrough to mainMBB
19351 // # abortion to sinkMBB
19352 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19353 thisMBB->addSuccessor(mainMBB);
19354 thisMBB->addSuccessor(sinkMBB);
19358 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19359 mainMBB->addSuccessor(sinkMBB);
19362 // EAX is live into the sinkMBB
19363 sinkMBB->addLiveIn(X86::EAX);
19364 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19365 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19368 MI->eraseFromParent();
19372 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19373 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19374 // in the .td file.
19375 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19376 const TargetInstrInfo *TII) {
19378 switch (MI->getOpcode()) {
19379 default: llvm_unreachable("illegal opcode!");
19380 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19381 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19382 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19383 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19384 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19385 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19386 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19387 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19390 DebugLoc dl = MI->getDebugLoc();
19391 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19393 unsigned NumArgs = MI->getNumOperands();
19394 for (unsigned i = 1; i < NumArgs; ++i) {
19395 MachineOperand &Op = MI->getOperand(i);
19396 if (!(Op.isReg() && Op.isImplicit()))
19397 MIB.addOperand(Op);
19399 if (MI->hasOneMemOperand())
19400 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19402 BuildMI(*BB, MI, dl,
19403 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19404 .addReg(X86::XMM0);
19406 MI->eraseFromParent();
19410 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19411 // defs in an instruction pattern
19412 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19413 const TargetInstrInfo *TII) {
19415 switch (MI->getOpcode()) {
19416 default: llvm_unreachable("illegal opcode!");
19417 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19418 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19419 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19420 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19421 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19422 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19423 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19424 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19427 DebugLoc dl = MI->getDebugLoc();
19428 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19430 unsigned NumArgs = MI->getNumOperands(); // remove the results
19431 for (unsigned i = 1; i < NumArgs; ++i) {
19432 MachineOperand &Op = MI->getOperand(i);
19433 if (!(Op.isReg() && Op.isImplicit()))
19434 MIB.addOperand(Op);
19436 if (MI->hasOneMemOperand())
19437 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19439 BuildMI(*BB, MI, dl,
19440 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19443 MI->eraseFromParent();
19447 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19448 const TargetInstrInfo *TII,
19449 const X86Subtarget* Subtarget) {
19450 DebugLoc dl = MI->getDebugLoc();
19452 // Address into RAX/EAX, other two args into ECX, EDX.
19453 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19454 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19455 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19456 for (int i = 0; i < X86::AddrNumOperands; ++i)
19457 MIB.addOperand(MI->getOperand(i));
19459 unsigned ValOps = X86::AddrNumOperands;
19460 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19461 .addReg(MI->getOperand(ValOps).getReg());
19462 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19463 .addReg(MI->getOperand(ValOps+1).getReg());
19465 // The instruction doesn't actually take any operands though.
19466 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19468 MI->eraseFromParent(); // The pseudo is gone now.
19472 MachineBasicBlock *
19473 X86TargetLowering::EmitVAARG64WithCustomInserter(
19475 MachineBasicBlock *MBB) const {
19476 // Emit va_arg instruction on X86-64.
19478 // Operands to this pseudo-instruction:
19479 // 0 ) Output : destination address (reg)
19480 // 1-5) Input : va_list address (addr, i64mem)
19481 // 6 ) ArgSize : Size (in bytes) of vararg type
19482 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19483 // 8 ) Align : Alignment of type
19484 // 9 ) EFLAGS (implicit-def)
19486 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19487 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19489 unsigned DestReg = MI->getOperand(0).getReg();
19490 MachineOperand &Base = MI->getOperand(1);
19491 MachineOperand &Scale = MI->getOperand(2);
19492 MachineOperand &Index = MI->getOperand(3);
19493 MachineOperand &Disp = MI->getOperand(4);
19494 MachineOperand &Segment = MI->getOperand(5);
19495 unsigned ArgSize = MI->getOperand(6).getImm();
19496 unsigned ArgMode = MI->getOperand(7).getImm();
19497 unsigned Align = MI->getOperand(8).getImm();
19499 // Memory Reference
19500 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19501 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19502 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19504 // Machine Information
19505 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19506 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19507 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19508 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19509 DebugLoc DL = MI->getDebugLoc();
19511 // struct va_list {
19514 // i64 overflow_area (address)
19515 // i64 reg_save_area (address)
19517 // sizeof(va_list) = 24
19518 // alignment(va_list) = 8
19520 unsigned TotalNumIntRegs = 6;
19521 unsigned TotalNumXMMRegs = 8;
19522 bool UseGPOffset = (ArgMode == 1);
19523 bool UseFPOffset = (ArgMode == 2);
19524 unsigned MaxOffset = TotalNumIntRegs * 8 +
19525 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19527 /* Align ArgSize to a multiple of 8 */
19528 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19529 bool NeedsAlign = (Align > 8);
19531 MachineBasicBlock *thisMBB = MBB;
19532 MachineBasicBlock *overflowMBB;
19533 MachineBasicBlock *offsetMBB;
19534 MachineBasicBlock *endMBB;
19536 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19537 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19538 unsigned OffsetReg = 0;
19540 if (!UseGPOffset && !UseFPOffset) {
19541 // If we only pull from the overflow region, we don't create a branch.
19542 // We don't need to alter control flow.
19543 OffsetDestReg = 0; // unused
19544 OverflowDestReg = DestReg;
19546 offsetMBB = nullptr;
19547 overflowMBB = thisMBB;
19550 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19551 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19552 // If not, pull from overflow_area. (branch to overflowMBB)
19557 // offsetMBB overflowMBB
19562 // Registers for the PHI in endMBB
19563 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19564 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19566 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19567 MachineFunction *MF = MBB->getParent();
19568 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19569 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19570 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19572 MachineFunction::iterator MBBIter = MBB;
19575 // Insert the new basic blocks
19576 MF->insert(MBBIter, offsetMBB);
19577 MF->insert(MBBIter, overflowMBB);
19578 MF->insert(MBBIter, endMBB);
19580 // Transfer the remainder of MBB and its successor edges to endMBB.
19581 endMBB->splice(endMBB->begin(), thisMBB,
19582 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19583 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19585 // Make offsetMBB and overflowMBB successors of thisMBB
19586 thisMBB->addSuccessor(offsetMBB);
19587 thisMBB->addSuccessor(overflowMBB);
19589 // endMBB is a successor of both offsetMBB and overflowMBB
19590 offsetMBB->addSuccessor(endMBB);
19591 overflowMBB->addSuccessor(endMBB);
19593 // Load the offset value into a register
19594 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19595 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19599 .addDisp(Disp, UseFPOffset ? 4 : 0)
19600 .addOperand(Segment)
19601 .setMemRefs(MMOBegin, MMOEnd);
19603 // Check if there is enough room left to pull this argument.
19604 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19606 .addImm(MaxOffset + 8 - ArgSizeA8);
19608 // Branch to "overflowMBB" if offset >= max
19609 // Fall through to "offsetMBB" otherwise
19610 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19611 .addMBB(overflowMBB);
19614 // In offsetMBB, emit code to use the reg_save_area.
19616 assert(OffsetReg != 0);
19618 // Read the reg_save_area address.
19619 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19620 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19625 .addOperand(Segment)
19626 .setMemRefs(MMOBegin, MMOEnd);
19628 // Zero-extend the offset
19629 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19630 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19633 .addImm(X86::sub_32bit);
19635 // Add the offset to the reg_save_area to get the final address.
19636 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19637 .addReg(OffsetReg64)
19638 .addReg(RegSaveReg);
19640 // Compute the offset for the next argument
19641 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19642 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19644 .addImm(UseFPOffset ? 16 : 8);
19646 // Store it back into the va_list.
19647 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19651 .addDisp(Disp, UseFPOffset ? 4 : 0)
19652 .addOperand(Segment)
19653 .addReg(NextOffsetReg)
19654 .setMemRefs(MMOBegin, MMOEnd);
19657 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19662 // Emit code to use overflow area
19665 // Load the overflow_area address into a register.
19666 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19667 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19672 .addOperand(Segment)
19673 .setMemRefs(MMOBegin, MMOEnd);
19675 // If we need to align it, do so. Otherwise, just copy the address
19676 // to OverflowDestReg.
19678 // Align the overflow address
19679 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19680 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19682 // aligned_addr = (addr + (align-1)) & ~(align-1)
19683 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19684 .addReg(OverflowAddrReg)
19687 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19689 .addImm(~(uint64_t)(Align-1));
19691 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19692 .addReg(OverflowAddrReg);
19695 // Compute the next overflow address after this argument.
19696 // (the overflow address should be kept 8-byte aligned)
19697 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19698 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19699 .addReg(OverflowDestReg)
19700 .addImm(ArgSizeA8);
19702 // Store the new overflow address.
19703 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19708 .addOperand(Segment)
19709 .addReg(NextAddrReg)
19710 .setMemRefs(MMOBegin, MMOEnd);
19712 // If we branched, emit the PHI to the front of endMBB.
19714 BuildMI(*endMBB, endMBB->begin(), DL,
19715 TII->get(X86::PHI), DestReg)
19716 .addReg(OffsetDestReg).addMBB(offsetMBB)
19717 .addReg(OverflowDestReg).addMBB(overflowMBB);
19720 // Erase the pseudo instruction
19721 MI->eraseFromParent();
19726 MachineBasicBlock *
19727 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19729 MachineBasicBlock *MBB) const {
19730 // Emit code to save XMM registers to the stack. The ABI says that the
19731 // number of registers to save is given in %al, so it's theoretically
19732 // possible to do an indirect jump trick to avoid saving all of them,
19733 // however this code takes a simpler approach and just executes all
19734 // of the stores if %al is non-zero. It's less code, and it's probably
19735 // easier on the hardware branch predictor, and stores aren't all that
19736 // expensive anyway.
19738 // Create the new basic blocks. One block contains all the XMM stores,
19739 // and one block is the final destination regardless of whether any
19740 // stores were performed.
19741 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19742 MachineFunction *F = MBB->getParent();
19743 MachineFunction::iterator MBBIter = MBB;
19745 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19746 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19747 F->insert(MBBIter, XMMSaveMBB);
19748 F->insert(MBBIter, EndMBB);
19750 // Transfer the remainder of MBB and its successor edges to EndMBB.
19751 EndMBB->splice(EndMBB->begin(), MBB,
19752 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19753 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19755 // The original block will now fall through to the XMM save block.
19756 MBB->addSuccessor(XMMSaveMBB);
19757 // The XMMSaveMBB will fall through to the end block.
19758 XMMSaveMBB->addSuccessor(EndMBB);
19760 // Now add the instructions.
19761 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19762 DebugLoc DL = MI->getDebugLoc();
19764 unsigned CountReg = MI->getOperand(0).getReg();
19765 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19766 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19768 if (!Subtarget->isTargetWin64()) {
19769 // If %al is 0, branch around the XMM save block.
19770 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19771 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19772 MBB->addSuccessor(EndMBB);
19775 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19776 // that was just emitted, but clearly shouldn't be "saved".
19777 assert((MI->getNumOperands() <= 3 ||
19778 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19779 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19780 && "Expected last argument to be EFLAGS");
19781 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19782 // In the XMM save block, save all the XMM argument registers.
19783 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19784 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19785 MachineMemOperand *MMO =
19786 F->getMachineMemOperand(
19787 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19788 MachineMemOperand::MOStore,
19789 /*Size=*/16, /*Align=*/16);
19790 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19791 .addFrameIndex(RegSaveFrameIndex)
19792 .addImm(/*Scale=*/1)
19793 .addReg(/*IndexReg=*/0)
19794 .addImm(/*Disp=*/Offset)
19795 .addReg(/*Segment=*/0)
19796 .addReg(MI->getOperand(i).getReg())
19797 .addMemOperand(MMO);
19800 MI->eraseFromParent(); // The pseudo instruction is gone now.
19805 // The EFLAGS operand of SelectItr might be missing a kill marker
19806 // because there were multiple uses of EFLAGS, and ISel didn't know
19807 // which to mark. Figure out whether SelectItr should have had a
19808 // kill marker, and set it if it should. Returns the correct kill
19810 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19811 MachineBasicBlock* BB,
19812 const TargetRegisterInfo* TRI) {
19813 // Scan forward through BB for a use/def of EFLAGS.
19814 MachineBasicBlock::iterator miI(std::next(SelectItr));
19815 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19816 const MachineInstr& mi = *miI;
19817 if (mi.readsRegister(X86::EFLAGS))
19819 if (mi.definesRegister(X86::EFLAGS))
19820 break; // Should have kill-flag - update below.
19823 // If we hit the end of the block, check whether EFLAGS is live into a
19825 if (miI == BB->end()) {
19826 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19827 sEnd = BB->succ_end();
19828 sItr != sEnd; ++sItr) {
19829 MachineBasicBlock* succ = *sItr;
19830 if (succ->isLiveIn(X86::EFLAGS))
19835 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19836 // out. SelectMI should have a kill flag on EFLAGS.
19837 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19841 MachineBasicBlock *
19842 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19843 MachineBasicBlock *BB) const {
19844 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19845 DebugLoc DL = MI->getDebugLoc();
19847 // To "insert" a SELECT_CC instruction, we actually have to insert the
19848 // diamond control-flow pattern. The incoming instruction knows the
19849 // destination vreg to set, the condition code register to branch on, the
19850 // true/false values to select between, and a branch opcode to use.
19851 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19852 MachineFunction::iterator It = BB;
19858 // cmpTY ccX, r1, r2
19860 // fallthrough --> copy0MBB
19861 MachineBasicBlock *thisMBB = BB;
19862 MachineFunction *F = BB->getParent();
19863 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19864 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19865 F->insert(It, copy0MBB);
19866 F->insert(It, sinkMBB);
19868 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19869 // live into the sink and copy blocks.
19870 const TargetRegisterInfo *TRI =
19871 BB->getParent()->getSubtarget().getRegisterInfo();
19872 if (!MI->killsRegister(X86::EFLAGS) &&
19873 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19874 copy0MBB->addLiveIn(X86::EFLAGS);
19875 sinkMBB->addLiveIn(X86::EFLAGS);
19878 // Transfer the remainder of BB and its successor edges to sinkMBB.
19879 sinkMBB->splice(sinkMBB->begin(), BB,
19880 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19881 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19883 // Add the true and fallthrough blocks as its successors.
19884 BB->addSuccessor(copy0MBB);
19885 BB->addSuccessor(sinkMBB);
19887 // Create the conditional branch instruction.
19889 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19890 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19893 // %FalseValue = ...
19894 // # fallthrough to sinkMBB
19895 copy0MBB->addSuccessor(sinkMBB);
19898 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19900 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19901 TII->get(X86::PHI), MI->getOperand(0).getReg())
19902 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19903 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19905 MI->eraseFromParent(); // The pseudo instruction is gone now.
19909 MachineBasicBlock *
19910 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19911 MachineBasicBlock *BB) const {
19912 MachineFunction *MF = BB->getParent();
19913 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19914 DebugLoc DL = MI->getDebugLoc();
19915 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19917 assert(MF->shouldSplitStack());
19919 const bool Is64Bit = Subtarget->is64Bit();
19920 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19922 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19923 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19926 // ... [Till the alloca]
19927 // If stacklet is not large enough, jump to mallocMBB
19930 // Allocate by subtracting from RSP
19931 // Jump to continueMBB
19934 // Allocate by call to runtime
19938 // [rest of original BB]
19941 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19942 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19943 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19945 MachineRegisterInfo &MRI = MF->getRegInfo();
19946 const TargetRegisterClass *AddrRegClass =
19947 getRegClassFor(getPointerTy());
19949 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19950 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19951 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19952 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19953 sizeVReg = MI->getOperand(1).getReg(),
19954 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19956 MachineFunction::iterator MBBIter = BB;
19959 MF->insert(MBBIter, bumpMBB);
19960 MF->insert(MBBIter, mallocMBB);
19961 MF->insert(MBBIter, continueMBB);
19963 continueMBB->splice(continueMBB->begin(), BB,
19964 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19965 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19967 // Add code to the main basic block to check if the stack limit has been hit,
19968 // and if so, jump to mallocMBB otherwise to bumpMBB.
19969 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19970 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19971 .addReg(tmpSPVReg).addReg(sizeVReg);
19972 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19973 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19974 .addReg(SPLimitVReg);
19975 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19977 // bumpMBB simply decreases the stack pointer, since we know the current
19978 // stacklet has enough space.
19979 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19980 .addReg(SPLimitVReg);
19981 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19982 .addReg(SPLimitVReg);
19983 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19985 // Calls into a routine in libgcc to allocate more space from the heap.
19986 const uint32_t *RegMask = MF->getTarget()
19987 .getSubtargetImpl()
19988 ->getRegisterInfo()
19989 ->getCallPreservedMask(CallingConv::C);
19991 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19993 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19994 .addExternalSymbol("__morestack_allocate_stack_space")
19995 .addRegMask(RegMask)
19996 .addReg(X86::RDI, RegState::Implicit)
19997 .addReg(X86::RAX, RegState::ImplicitDefine);
19998 } else if (Is64Bit) {
19999 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20001 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20002 .addExternalSymbol("__morestack_allocate_stack_space")
20003 .addRegMask(RegMask)
20004 .addReg(X86::EDI, RegState::Implicit)
20005 .addReg(X86::EAX, RegState::ImplicitDefine);
20007 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20009 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20010 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20011 .addExternalSymbol("__morestack_allocate_stack_space")
20012 .addRegMask(RegMask)
20013 .addReg(X86::EAX, RegState::ImplicitDefine);
20017 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20020 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20021 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20022 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20024 // Set up the CFG correctly.
20025 BB->addSuccessor(bumpMBB);
20026 BB->addSuccessor(mallocMBB);
20027 mallocMBB->addSuccessor(continueMBB);
20028 bumpMBB->addSuccessor(continueMBB);
20030 // Take care of the PHI nodes.
20031 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20032 MI->getOperand(0).getReg())
20033 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20034 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20036 // Delete the original pseudo instruction.
20037 MI->eraseFromParent();
20040 return continueMBB;
20043 MachineBasicBlock *
20044 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20045 MachineBasicBlock *BB) const {
20046 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20047 DebugLoc DL = MI->getDebugLoc();
20049 assert(!Subtarget->isTargetMacho());
20051 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20052 // non-trivial part is impdef of ESP.
20054 if (Subtarget->isTargetWin64()) {
20055 if (Subtarget->isTargetCygMing()) {
20056 // ___chkstk(Mingw64):
20057 // Clobbers R10, R11, RAX and EFLAGS.
20059 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20060 .addExternalSymbol("___chkstk")
20061 .addReg(X86::RAX, RegState::Implicit)
20062 .addReg(X86::RSP, RegState::Implicit)
20063 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20064 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20065 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20067 // __chkstk(MSVCRT): does not update stack pointer.
20068 // Clobbers R10, R11 and EFLAGS.
20069 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20070 .addExternalSymbol("__chkstk")
20071 .addReg(X86::RAX, RegState::Implicit)
20072 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20073 // RAX has the offset to be subtracted from RSP.
20074 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20079 const char *StackProbeSymbol =
20080 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
20082 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20083 .addExternalSymbol(StackProbeSymbol)
20084 .addReg(X86::EAX, RegState::Implicit)
20085 .addReg(X86::ESP, RegState::Implicit)
20086 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20087 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20088 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20091 MI->eraseFromParent(); // The pseudo instruction is gone now.
20095 MachineBasicBlock *
20096 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20097 MachineBasicBlock *BB) const {
20098 // This is pretty easy. We're taking the value that we received from
20099 // our load from the relocation, sticking it in either RDI (x86-64)
20100 // or EAX and doing an indirect call. The return value will then
20101 // be in the normal return register.
20102 MachineFunction *F = BB->getParent();
20103 const X86InstrInfo *TII =
20104 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20105 DebugLoc DL = MI->getDebugLoc();
20107 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20108 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20110 // Get a register mask for the lowered call.
20111 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20112 // proper register mask.
20113 const uint32_t *RegMask = F->getTarget()
20114 .getSubtargetImpl()
20115 ->getRegisterInfo()
20116 ->getCallPreservedMask(CallingConv::C);
20117 if (Subtarget->is64Bit()) {
20118 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20119 TII->get(X86::MOV64rm), X86::RDI)
20121 .addImm(0).addReg(0)
20122 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20123 MI->getOperand(3).getTargetFlags())
20125 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20126 addDirectMem(MIB, X86::RDI);
20127 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20128 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20129 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20130 TII->get(X86::MOV32rm), X86::EAX)
20132 .addImm(0).addReg(0)
20133 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20134 MI->getOperand(3).getTargetFlags())
20136 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20137 addDirectMem(MIB, X86::EAX);
20138 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20140 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20141 TII->get(X86::MOV32rm), X86::EAX)
20142 .addReg(TII->getGlobalBaseReg(F))
20143 .addImm(0).addReg(0)
20144 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20145 MI->getOperand(3).getTargetFlags())
20147 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20148 addDirectMem(MIB, X86::EAX);
20149 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20152 MI->eraseFromParent(); // The pseudo instruction is gone now.
20156 MachineBasicBlock *
20157 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20158 MachineBasicBlock *MBB) const {
20159 DebugLoc DL = MI->getDebugLoc();
20160 MachineFunction *MF = MBB->getParent();
20161 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20162 MachineRegisterInfo &MRI = MF->getRegInfo();
20164 const BasicBlock *BB = MBB->getBasicBlock();
20165 MachineFunction::iterator I = MBB;
20168 // Memory Reference
20169 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20170 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20173 unsigned MemOpndSlot = 0;
20175 unsigned CurOp = 0;
20177 DstReg = MI->getOperand(CurOp++).getReg();
20178 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20179 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20180 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20181 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20183 MemOpndSlot = CurOp;
20185 MVT PVT = getPointerTy();
20186 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20187 "Invalid Pointer Size!");
20189 // For v = setjmp(buf), we generate
20192 // buf[LabelOffset] = restoreMBB
20193 // SjLjSetup restoreMBB
20199 // v = phi(main, restore)
20204 MachineBasicBlock *thisMBB = MBB;
20205 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20206 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20207 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20208 MF->insert(I, mainMBB);
20209 MF->insert(I, sinkMBB);
20210 MF->push_back(restoreMBB);
20212 MachineInstrBuilder MIB;
20214 // Transfer the remainder of BB and its successor edges to sinkMBB.
20215 sinkMBB->splice(sinkMBB->begin(), MBB,
20216 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20217 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20220 unsigned PtrStoreOpc = 0;
20221 unsigned LabelReg = 0;
20222 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20223 Reloc::Model RM = MF->getTarget().getRelocationModel();
20224 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20225 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20227 // Prepare IP either in reg or imm.
20228 if (!UseImmLabel) {
20229 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20230 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20231 LabelReg = MRI.createVirtualRegister(PtrRC);
20232 if (Subtarget->is64Bit()) {
20233 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20237 .addMBB(restoreMBB)
20240 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20241 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20242 .addReg(XII->getGlobalBaseReg(MF))
20245 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20249 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20251 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20252 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20253 if (i == X86::AddrDisp)
20254 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20256 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20259 MIB.addReg(LabelReg);
20261 MIB.addMBB(restoreMBB);
20262 MIB.setMemRefs(MMOBegin, MMOEnd);
20264 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20265 .addMBB(restoreMBB);
20267 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20268 MF->getSubtarget().getRegisterInfo());
20269 MIB.addRegMask(RegInfo->getNoPreservedMask());
20270 thisMBB->addSuccessor(mainMBB);
20271 thisMBB->addSuccessor(restoreMBB);
20275 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20276 mainMBB->addSuccessor(sinkMBB);
20279 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20280 TII->get(X86::PHI), DstReg)
20281 .addReg(mainDstReg).addMBB(mainMBB)
20282 .addReg(restoreDstReg).addMBB(restoreMBB);
20285 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20286 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20287 restoreMBB->addSuccessor(sinkMBB);
20289 MI->eraseFromParent();
20293 MachineBasicBlock *
20294 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20295 MachineBasicBlock *MBB) const {
20296 DebugLoc DL = MI->getDebugLoc();
20297 MachineFunction *MF = MBB->getParent();
20298 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20299 MachineRegisterInfo &MRI = MF->getRegInfo();
20301 // Memory Reference
20302 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20303 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20305 MVT PVT = getPointerTy();
20306 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20307 "Invalid Pointer Size!");
20309 const TargetRegisterClass *RC =
20310 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20311 unsigned Tmp = MRI.createVirtualRegister(RC);
20312 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20313 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20314 MF->getSubtarget().getRegisterInfo());
20315 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20316 unsigned SP = RegInfo->getStackRegister();
20318 MachineInstrBuilder MIB;
20320 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20321 const int64_t SPOffset = 2 * PVT.getStoreSize();
20323 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20324 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20327 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20328 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20329 MIB.addOperand(MI->getOperand(i));
20330 MIB.setMemRefs(MMOBegin, MMOEnd);
20332 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20333 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20334 if (i == X86::AddrDisp)
20335 MIB.addDisp(MI->getOperand(i), LabelOffset);
20337 MIB.addOperand(MI->getOperand(i));
20339 MIB.setMemRefs(MMOBegin, MMOEnd);
20341 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20342 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20343 if (i == X86::AddrDisp)
20344 MIB.addDisp(MI->getOperand(i), SPOffset);
20346 MIB.addOperand(MI->getOperand(i));
20348 MIB.setMemRefs(MMOBegin, MMOEnd);
20350 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20352 MI->eraseFromParent();
20356 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20357 // accumulator loops. Writing back to the accumulator allows the coalescer
20358 // to remove extra copies in the loop.
20359 MachineBasicBlock *
20360 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20361 MachineBasicBlock *MBB) const {
20362 MachineOperand &AddendOp = MI->getOperand(3);
20364 // Bail out early if the addend isn't a register - we can't switch these.
20365 if (!AddendOp.isReg())
20368 MachineFunction &MF = *MBB->getParent();
20369 MachineRegisterInfo &MRI = MF.getRegInfo();
20371 // Check whether the addend is defined by a PHI:
20372 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20373 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20374 if (!AddendDef.isPHI())
20377 // Look for the following pattern:
20379 // %addend = phi [%entry, 0], [%loop, %result]
20381 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20385 // %addend = phi [%entry, 0], [%loop, %result]
20387 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20389 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20390 assert(AddendDef.getOperand(i).isReg());
20391 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20392 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20393 if (&PHISrcInst == MI) {
20394 // Found a matching instruction.
20395 unsigned NewFMAOpc = 0;
20396 switch (MI->getOpcode()) {
20397 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20398 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20399 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20400 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20401 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20402 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20403 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20404 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20405 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20406 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20407 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20408 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20409 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20410 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20411 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20412 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20413 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20414 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20415 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20416 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20417 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20418 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20419 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20420 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20421 default: llvm_unreachable("Unrecognized FMA variant.");
20424 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20425 MachineInstrBuilder MIB =
20426 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20427 .addOperand(MI->getOperand(0))
20428 .addOperand(MI->getOperand(3))
20429 .addOperand(MI->getOperand(2))
20430 .addOperand(MI->getOperand(1));
20431 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20432 MI->eraseFromParent();
20439 MachineBasicBlock *
20440 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20441 MachineBasicBlock *BB) const {
20442 switch (MI->getOpcode()) {
20443 default: llvm_unreachable("Unexpected instr type to insert");
20444 case X86::TAILJMPd64:
20445 case X86::TAILJMPr64:
20446 case X86::TAILJMPm64:
20447 llvm_unreachable("TAILJMP64 would not be touched here.");
20448 case X86::TCRETURNdi64:
20449 case X86::TCRETURNri64:
20450 case X86::TCRETURNmi64:
20452 case X86::WIN_ALLOCA:
20453 return EmitLoweredWinAlloca(MI, BB);
20454 case X86::SEG_ALLOCA_32:
20455 case X86::SEG_ALLOCA_64:
20456 return EmitLoweredSegAlloca(MI, BB);
20457 case X86::TLSCall_32:
20458 case X86::TLSCall_64:
20459 return EmitLoweredTLSCall(MI, BB);
20460 case X86::CMOV_GR8:
20461 case X86::CMOV_FR32:
20462 case X86::CMOV_FR64:
20463 case X86::CMOV_V4F32:
20464 case X86::CMOV_V2F64:
20465 case X86::CMOV_V2I64:
20466 case X86::CMOV_V8F32:
20467 case X86::CMOV_V4F64:
20468 case X86::CMOV_V4I64:
20469 case X86::CMOV_V16F32:
20470 case X86::CMOV_V8F64:
20471 case X86::CMOV_V8I64:
20472 case X86::CMOV_GR16:
20473 case X86::CMOV_GR32:
20474 case X86::CMOV_RFP32:
20475 case X86::CMOV_RFP64:
20476 case X86::CMOV_RFP80:
20477 return EmitLoweredSelect(MI, BB);
20479 case X86::FP32_TO_INT16_IN_MEM:
20480 case X86::FP32_TO_INT32_IN_MEM:
20481 case X86::FP32_TO_INT64_IN_MEM:
20482 case X86::FP64_TO_INT16_IN_MEM:
20483 case X86::FP64_TO_INT32_IN_MEM:
20484 case X86::FP64_TO_INT64_IN_MEM:
20485 case X86::FP80_TO_INT16_IN_MEM:
20486 case X86::FP80_TO_INT32_IN_MEM:
20487 case X86::FP80_TO_INT64_IN_MEM: {
20488 MachineFunction *F = BB->getParent();
20489 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20490 DebugLoc DL = MI->getDebugLoc();
20492 // Change the floating point control register to use "round towards zero"
20493 // mode when truncating to an integer value.
20494 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20495 addFrameReference(BuildMI(*BB, MI, DL,
20496 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20498 // Load the old value of the high byte of the control word...
20500 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20501 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20504 // Set the high part to be round to zero...
20505 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20508 // Reload the modified control word now...
20509 addFrameReference(BuildMI(*BB, MI, DL,
20510 TII->get(X86::FLDCW16m)), CWFrameIdx);
20512 // Restore the memory image of control word to original value
20513 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20516 // Get the X86 opcode to use.
20518 switch (MI->getOpcode()) {
20519 default: llvm_unreachable("illegal opcode!");
20520 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20521 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20522 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20523 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20524 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20525 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20526 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20527 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20528 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20532 MachineOperand &Op = MI->getOperand(0);
20534 AM.BaseType = X86AddressMode::RegBase;
20535 AM.Base.Reg = Op.getReg();
20537 AM.BaseType = X86AddressMode::FrameIndexBase;
20538 AM.Base.FrameIndex = Op.getIndex();
20540 Op = MI->getOperand(1);
20542 AM.Scale = Op.getImm();
20543 Op = MI->getOperand(2);
20545 AM.IndexReg = Op.getImm();
20546 Op = MI->getOperand(3);
20547 if (Op.isGlobal()) {
20548 AM.GV = Op.getGlobal();
20550 AM.Disp = Op.getImm();
20552 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20553 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20555 // Reload the original control word now.
20556 addFrameReference(BuildMI(*BB, MI, DL,
20557 TII->get(X86::FLDCW16m)), CWFrameIdx);
20559 MI->eraseFromParent(); // The pseudo instruction is gone now.
20562 // String/text processing lowering.
20563 case X86::PCMPISTRM128REG:
20564 case X86::VPCMPISTRM128REG:
20565 case X86::PCMPISTRM128MEM:
20566 case X86::VPCMPISTRM128MEM:
20567 case X86::PCMPESTRM128REG:
20568 case X86::VPCMPESTRM128REG:
20569 case X86::PCMPESTRM128MEM:
20570 case X86::VPCMPESTRM128MEM:
20571 assert(Subtarget->hasSSE42() &&
20572 "Target must have SSE4.2 or AVX features enabled");
20573 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20575 // String/text processing lowering.
20576 case X86::PCMPISTRIREG:
20577 case X86::VPCMPISTRIREG:
20578 case X86::PCMPISTRIMEM:
20579 case X86::VPCMPISTRIMEM:
20580 case X86::PCMPESTRIREG:
20581 case X86::VPCMPESTRIREG:
20582 case X86::PCMPESTRIMEM:
20583 case X86::VPCMPESTRIMEM:
20584 assert(Subtarget->hasSSE42() &&
20585 "Target must have SSE4.2 or AVX features enabled");
20586 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20588 // Thread synchronization.
20590 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20595 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20597 case X86::VASTART_SAVE_XMM_REGS:
20598 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20600 case X86::VAARG_64:
20601 return EmitVAARG64WithCustomInserter(MI, BB);
20603 case X86::EH_SjLj_SetJmp32:
20604 case X86::EH_SjLj_SetJmp64:
20605 return emitEHSjLjSetJmp(MI, BB);
20607 case X86::EH_SjLj_LongJmp32:
20608 case X86::EH_SjLj_LongJmp64:
20609 return emitEHSjLjLongJmp(MI, BB);
20611 case TargetOpcode::STACKMAP:
20612 case TargetOpcode::PATCHPOINT:
20613 return emitPatchPoint(MI, BB);
20615 case X86::VFMADDPDr213r:
20616 case X86::VFMADDPSr213r:
20617 case X86::VFMADDSDr213r:
20618 case X86::VFMADDSSr213r:
20619 case X86::VFMSUBPDr213r:
20620 case X86::VFMSUBPSr213r:
20621 case X86::VFMSUBSDr213r:
20622 case X86::VFMSUBSSr213r:
20623 case X86::VFNMADDPDr213r:
20624 case X86::VFNMADDPSr213r:
20625 case X86::VFNMADDSDr213r:
20626 case X86::VFNMADDSSr213r:
20627 case X86::VFNMSUBPDr213r:
20628 case X86::VFNMSUBPSr213r:
20629 case X86::VFNMSUBSDr213r:
20630 case X86::VFNMSUBSSr213r:
20631 case X86::VFMADDPDr213rY:
20632 case X86::VFMADDPSr213rY:
20633 case X86::VFMSUBPDr213rY:
20634 case X86::VFMSUBPSr213rY:
20635 case X86::VFNMADDPDr213rY:
20636 case X86::VFNMADDPSr213rY:
20637 case X86::VFNMSUBPDr213rY:
20638 case X86::VFNMSUBPSr213rY:
20639 return emitFMA3Instr(MI, BB);
20643 //===----------------------------------------------------------------------===//
20644 // X86 Optimization Hooks
20645 //===----------------------------------------------------------------------===//
20647 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20650 const SelectionDAG &DAG,
20651 unsigned Depth) const {
20652 unsigned BitWidth = KnownZero.getBitWidth();
20653 unsigned Opc = Op.getOpcode();
20654 assert((Opc >= ISD::BUILTIN_OP_END ||
20655 Opc == ISD::INTRINSIC_WO_CHAIN ||
20656 Opc == ISD::INTRINSIC_W_CHAIN ||
20657 Opc == ISD::INTRINSIC_VOID) &&
20658 "Should use MaskedValueIsZero if you don't know whether Op"
20659 " is a target node!");
20661 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20675 // These nodes' second result is a boolean.
20676 if (Op.getResNo() == 0)
20679 case X86ISD::SETCC:
20680 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20682 case ISD::INTRINSIC_WO_CHAIN: {
20683 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20684 unsigned NumLoBits = 0;
20687 case Intrinsic::x86_sse_movmsk_ps:
20688 case Intrinsic::x86_avx_movmsk_ps_256:
20689 case Intrinsic::x86_sse2_movmsk_pd:
20690 case Intrinsic::x86_avx_movmsk_pd_256:
20691 case Intrinsic::x86_mmx_pmovmskb:
20692 case Intrinsic::x86_sse2_pmovmskb_128:
20693 case Intrinsic::x86_avx2_pmovmskb: {
20694 // High bits of movmskp{s|d}, pmovmskb are known zero.
20696 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20697 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20698 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20699 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20700 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20701 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20702 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20703 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20705 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20714 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20716 const SelectionDAG &,
20717 unsigned Depth) const {
20718 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20719 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20720 return Op.getValueType().getScalarType().getSizeInBits();
20726 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20727 /// node is a GlobalAddress + offset.
20728 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20729 const GlobalValue* &GA,
20730 int64_t &Offset) const {
20731 if (N->getOpcode() == X86ISD::Wrapper) {
20732 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20733 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20734 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20738 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20741 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20742 /// same as extracting the high 128-bit part of 256-bit vector and then
20743 /// inserting the result into the low part of a new 256-bit vector
20744 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20745 EVT VT = SVOp->getValueType(0);
20746 unsigned NumElems = VT.getVectorNumElements();
20748 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20749 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20750 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20751 SVOp->getMaskElt(j) >= 0)
20757 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20758 /// same as extracting the low 128-bit part of 256-bit vector and then
20759 /// inserting the result into the high part of a new 256-bit vector
20760 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20761 EVT VT = SVOp->getValueType(0);
20762 unsigned NumElems = VT.getVectorNumElements();
20764 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20765 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20766 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20767 SVOp->getMaskElt(j) >= 0)
20773 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20774 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20775 TargetLowering::DAGCombinerInfo &DCI,
20776 const X86Subtarget* Subtarget) {
20778 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20779 SDValue V1 = SVOp->getOperand(0);
20780 SDValue V2 = SVOp->getOperand(1);
20781 EVT VT = SVOp->getValueType(0);
20782 unsigned NumElems = VT.getVectorNumElements();
20784 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20785 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20789 // V UNDEF BUILD_VECTOR UNDEF
20791 // CONCAT_VECTOR CONCAT_VECTOR
20794 // RESULT: V + zero extended
20796 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20797 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20798 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20801 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20804 // To match the shuffle mask, the first half of the mask should
20805 // be exactly the first vector, and all the rest a splat with the
20806 // first element of the second one.
20807 for (unsigned i = 0; i != NumElems/2; ++i)
20808 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20809 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20812 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20813 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20814 if (Ld->hasNUsesOfValue(1, 0)) {
20815 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20816 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20818 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20820 Ld->getPointerInfo(),
20821 Ld->getAlignment(),
20822 false/*isVolatile*/, true/*ReadMem*/,
20823 false/*WriteMem*/);
20825 // Make sure the newly-created LOAD is in the same position as Ld in
20826 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20827 // and update uses of Ld's output chain to use the TokenFactor.
20828 if (Ld->hasAnyUseOfValue(1)) {
20829 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20830 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20831 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20832 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20833 SDValue(ResNode.getNode(), 1));
20836 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20840 // Emit a zeroed vector and insert the desired subvector on its
20842 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20843 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20844 return DCI.CombineTo(N, InsV);
20847 //===--------------------------------------------------------------------===//
20848 // Combine some shuffles into subvector extracts and inserts:
20851 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20852 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20853 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20854 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20855 return DCI.CombineTo(N, InsV);
20858 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20859 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20860 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20861 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20862 return DCI.CombineTo(N, InsV);
20868 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20871 /// This is the leaf of the recursive combinine below. When we have found some
20872 /// chain of single-use x86 shuffle instructions and accumulated the combined
20873 /// shuffle mask represented by them, this will try to pattern match that mask
20874 /// into either a single instruction if there is a special purpose instruction
20875 /// for this operation, or into a PSHUFB instruction which is a fully general
20876 /// instruction but should only be used to replace chains over a certain depth.
20877 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20878 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20879 TargetLowering::DAGCombinerInfo &DCI,
20880 const X86Subtarget *Subtarget) {
20881 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20883 // Find the operand that enters the chain. Note that multiple uses are OK
20884 // here, we're not going to remove the operand we find.
20885 SDValue Input = Op.getOperand(0);
20886 while (Input.getOpcode() == ISD::BITCAST)
20887 Input = Input.getOperand(0);
20889 MVT VT = Input.getSimpleValueType();
20890 MVT RootVT = Root.getSimpleValueType();
20893 // Just remove no-op shuffle masks.
20894 if (Mask.size() == 1) {
20895 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20900 // Use the float domain if the operand type is a floating point type.
20901 bool FloatDomain = VT.isFloatingPoint();
20903 // For floating point shuffles, we don't have free copies in the shuffle
20904 // instructions or the ability to load as part of the instruction, so
20905 // canonicalize their shuffles to UNPCK or MOV variants.
20907 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20908 // vectors because it can have a load folded into it that UNPCK cannot. This
20909 // doesn't preclude something switching to the shorter encoding post-RA.
20911 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20912 bool Lo = Mask.equals(0, 0);
20915 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20916 // is no slower than UNPCKLPD but has the option to fold the input operand
20917 // into even an unaligned memory load.
20918 if (Lo && Subtarget->hasSSE3()) {
20919 Shuffle = X86ISD::MOVDDUP;
20920 ShuffleVT = MVT::v2f64;
20922 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20923 // than the UNPCK variants.
20924 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20925 ShuffleVT = MVT::v4f32;
20927 if (Depth == 1 && Root->getOpcode() == Shuffle)
20928 return false; // Nothing to do!
20929 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20930 DCI.AddToWorklist(Op.getNode());
20931 if (Shuffle == X86ISD::MOVDDUP)
20932 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20934 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20935 DCI.AddToWorklist(Op.getNode());
20936 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20940 if (Subtarget->hasSSE3() &&
20941 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20942 bool Lo = Mask.equals(0, 0, 2, 2);
20943 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20944 MVT ShuffleVT = MVT::v4f32;
20945 if (Depth == 1 && Root->getOpcode() == Shuffle)
20946 return false; // Nothing to do!
20947 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20948 DCI.AddToWorklist(Op.getNode());
20949 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20950 DCI.AddToWorklist(Op.getNode());
20951 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20955 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20956 bool Lo = Mask.equals(0, 0, 1, 1);
20957 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20958 MVT ShuffleVT = MVT::v4f32;
20959 if (Depth == 1 && Root->getOpcode() == Shuffle)
20960 return false; // Nothing to do!
20961 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20962 DCI.AddToWorklist(Op.getNode());
20963 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20964 DCI.AddToWorklist(Op.getNode());
20965 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20971 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20972 // variants as none of these have single-instruction variants that are
20973 // superior to the UNPCK formulation.
20974 if (!FloatDomain &&
20975 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20976 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20977 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20978 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20980 bool Lo = Mask[0] == 0;
20981 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20982 if (Depth == 1 && Root->getOpcode() == Shuffle)
20983 return false; // Nothing to do!
20985 switch (Mask.size()) {
20987 ShuffleVT = MVT::v8i16;
20990 ShuffleVT = MVT::v16i8;
20993 llvm_unreachable("Impossible mask size!");
20995 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20996 DCI.AddToWorklist(Op.getNode());
20997 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20998 DCI.AddToWorklist(Op.getNode());
20999 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21004 // Don't try to re-form single instruction chains under any circumstances now
21005 // that we've done encoding canonicalization for them.
21009 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21010 // can replace them with a single PSHUFB instruction profitably. Intel's
21011 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21012 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21013 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21014 SmallVector<SDValue, 16> PSHUFBMask;
21015 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21016 int Ratio = 16 / Mask.size();
21017 for (unsigned i = 0; i < 16; ++i) {
21018 if (Mask[i / Ratio] == SM_SentinelUndef) {
21019 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21022 int M = Mask[i / Ratio] != SM_SentinelZero
21023 ? Ratio * Mask[i / Ratio] + i % Ratio
21025 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21027 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21028 DCI.AddToWorklist(Op.getNode());
21029 SDValue PSHUFBMaskOp =
21030 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21031 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21032 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21033 DCI.AddToWorklist(Op.getNode());
21034 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21039 // Failed to find any combines.
21043 /// \brief Fully generic combining of x86 shuffle instructions.
21045 /// This should be the last combine run over the x86 shuffle instructions. Once
21046 /// they have been fully optimized, this will recursively consider all chains
21047 /// of single-use shuffle instructions, build a generic model of the cumulative
21048 /// shuffle operation, and check for simpler instructions which implement this
21049 /// operation. We use this primarily for two purposes:
21051 /// 1) Collapse generic shuffles to specialized single instructions when
21052 /// equivalent. In most cases, this is just an encoding size win, but
21053 /// sometimes we will collapse multiple generic shuffles into a single
21054 /// special-purpose shuffle.
21055 /// 2) Look for sequences of shuffle instructions with 3 or more total
21056 /// instructions, and replace them with the slightly more expensive SSSE3
21057 /// PSHUFB instruction if available. We do this as the last combining step
21058 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21059 /// a suitable short sequence of other instructions. The PHUFB will either
21060 /// use a register or have to read from memory and so is slightly (but only
21061 /// slightly) more expensive than the other shuffle instructions.
21063 /// Because this is inherently a quadratic operation (for each shuffle in
21064 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21065 /// This should never be an issue in practice as the shuffle lowering doesn't
21066 /// produce sequences of more than 8 instructions.
21068 /// FIXME: We will currently miss some cases where the redundant shuffling
21069 /// would simplify under the threshold for PSHUFB formation because of
21070 /// combine-ordering. To fix this, we should do the redundant instruction
21071 /// combining in this recursive walk.
21072 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21073 ArrayRef<int> RootMask,
21074 int Depth, bool HasPSHUFB,
21076 TargetLowering::DAGCombinerInfo &DCI,
21077 const X86Subtarget *Subtarget) {
21078 // Bound the depth of our recursive combine because this is ultimately
21079 // quadratic in nature.
21083 // Directly rip through bitcasts to find the underlying operand.
21084 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21085 Op = Op.getOperand(0);
21087 MVT VT = Op.getSimpleValueType();
21088 if (!VT.isVector())
21089 return false; // Bail if we hit a non-vector.
21090 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21091 // version should be added.
21092 if (VT.getSizeInBits() != 128)
21095 assert(Root.getSimpleValueType().isVector() &&
21096 "Shuffles operate on vector types!");
21097 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21098 "Can only combine shuffles of the same vector register size.");
21100 if (!isTargetShuffle(Op.getOpcode()))
21102 SmallVector<int, 16> OpMask;
21104 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21105 // We only can combine unary shuffles which we can decode the mask for.
21106 if (!HaveMask || !IsUnary)
21109 assert(VT.getVectorNumElements() == OpMask.size() &&
21110 "Different mask size from vector size!");
21111 assert(((RootMask.size() > OpMask.size() &&
21112 RootMask.size() % OpMask.size() == 0) ||
21113 (OpMask.size() > RootMask.size() &&
21114 OpMask.size() % RootMask.size() == 0) ||
21115 OpMask.size() == RootMask.size()) &&
21116 "The smaller number of elements must divide the larger.");
21117 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21118 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21119 assert(((RootRatio == 1 && OpRatio == 1) ||
21120 (RootRatio == 1) != (OpRatio == 1)) &&
21121 "Must not have a ratio for both incoming and op masks!");
21123 SmallVector<int, 16> Mask;
21124 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21126 // Merge this shuffle operation's mask into our accumulated mask. Note that
21127 // this shuffle's mask will be the first applied to the input, followed by the
21128 // root mask to get us all the way to the root value arrangement. The reason
21129 // for this order is that we are recursing up the operation chain.
21130 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21131 int RootIdx = i / RootRatio;
21132 if (RootMask[RootIdx] < 0) {
21133 // This is a zero or undef lane, we're done.
21134 Mask.push_back(RootMask[RootIdx]);
21138 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21139 int OpIdx = RootMaskedIdx / OpRatio;
21140 if (OpMask[OpIdx] < 0) {
21141 // The incoming lanes are zero or undef, it doesn't matter which ones we
21143 Mask.push_back(OpMask[OpIdx]);
21147 // Ok, we have non-zero lanes, map them through.
21148 Mask.push_back(OpMask[OpIdx] * OpRatio +
21149 RootMaskedIdx % OpRatio);
21152 // See if we can recurse into the operand to combine more things.
21153 switch (Op.getOpcode()) {
21154 case X86ISD::PSHUFB:
21156 case X86ISD::PSHUFD:
21157 case X86ISD::PSHUFHW:
21158 case X86ISD::PSHUFLW:
21159 if (Op.getOperand(0).hasOneUse() &&
21160 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21161 HasPSHUFB, DAG, DCI, Subtarget))
21165 case X86ISD::UNPCKL:
21166 case X86ISD::UNPCKH:
21167 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21168 // We can't check for single use, we have to check that this shuffle is the only user.
21169 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21170 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21171 HasPSHUFB, DAG, DCI, Subtarget))
21176 // Minor canonicalization of the accumulated shuffle mask to make it easier
21177 // to match below. All this does is detect masks with squential pairs of
21178 // elements, and shrink them to the half-width mask. It does this in a loop
21179 // so it will reduce the size of the mask to the minimal width mask which
21180 // performs an equivalent shuffle.
21181 SmallVector<int, 16> WidenedMask;
21182 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21183 Mask = std::move(WidenedMask);
21184 WidenedMask.clear();
21187 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21191 /// \brief Get the PSHUF-style mask from PSHUF node.
21193 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21194 /// PSHUF-style masks that can be reused with such instructions.
21195 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21196 SmallVector<int, 4> Mask;
21198 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21202 switch (N.getOpcode()) {
21203 case X86ISD::PSHUFD:
21205 case X86ISD::PSHUFLW:
21208 case X86ISD::PSHUFHW:
21209 Mask.erase(Mask.begin(), Mask.begin() + 4);
21210 for (int &M : Mask)
21214 llvm_unreachable("No valid shuffle instruction found!");
21218 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21220 /// We walk up the chain and look for a combinable shuffle, skipping over
21221 /// shuffles that we could hoist this shuffle's transformation past without
21222 /// altering anything.
21224 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21226 TargetLowering::DAGCombinerInfo &DCI) {
21227 assert(N.getOpcode() == X86ISD::PSHUFD &&
21228 "Called with something other than an x86 128-bit half shuffle!");
21231 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21232 // of the shuffles in the chain so that we can form a fresh chain to replace
21234 SmallVector<SDValue, 8> Chain;
21235 SDValue V = N.getOperand(0);
21236 for (; V.hasOneUse(); V = V.getOperand(0)) {
21237 switch (V.getOpcode()) {
21239 return SDValue(); // Nothing combined!
21242 // Skip bitcasts as we always know the type for the target specific
21246 case X86ISD::PSHUFD:
21247 // Found another dword shuffle.
21250 case X86ISD::PSHUFLW:
21251 // Check that the low words (being shuffled) are the identity in the
21252 // dword shuffle, and the high words are self-contained.
21253 if (Mask[0] != 0 || Mask[1] != 1 ||
21254 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21257 Chain.push_back(V);
21260 case X86ISD::PSHUFHW:
21261 // Check that the high words (being shuffled) are the identity in the
21262 // dword shuffle, and the low words are self-contained.
21263 if (Mask[2] != 2 || Mask[3] != 3 ||
21264 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21267 Chain.push_back(V);
21270 case X86ISD::UNPCKL:
21271 case X86ISD::UNPCKH:
21272 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21273 // shuffle into a preceding word shuffle.
21274 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21277 // Search for a half-shuffle which we can combine with.
21278 unsigned CombineOp =
21279 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21280 if (V.getOperand(0) != V.getOperand(1) ||
21281 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21283 Chain.push_back(V);
21284 V = V.getOperand(0);
21286 switch (V.getOpcode()) {
21288 return SDValue(); // Nothing to combine.
21290 case X86ISD::PSHUFLW:
21291 case X86ISD::PSHUFHW:
21292 if (V.getOpcode() == CombineOp)
21295 Chain.push_back(V);
21299 V = V.getOperand(0);
21303 } while (V.hasOneUse());
21306 // Break out of the loop if we break out of the switch.
21310 if (!V.hasOneUse())
21311 // We fell out of the loop without finding a viable combining instruction.
21314 // Merge this node's mask and our incoming mask.
21315 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21316 for (int &M : Mask)
21318 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21319 getV4X86ShuffleImm8ForMask(Mask, DAG));
21321 // Rebuild the chain around this new shuffle.
21322 while (!Chain.empty()) {
21323 SDValue W = Chain.pop_back_val();
21325 if (V.getValueType() != W.getOperand(0).getValueType())
21326 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21328 switch (W.getOpcode()) {
21330 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21332 case X86ISD::UNPCKL:
21333 case X86ISD::UNPCKH:
21334 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21337 case X86ISD::PSHUFD:
21338 case X86ISD::PSHUFLW:
21339 case X86ISD::PSHUFHW:
21340 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21344 if (V.getValueType() != N.getValueType())
21345 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21347 // Return the new chain to replace N.
21351 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21353 /// We walk up the chain, skipping shuffles of the other half and looking
21354 /// through shuffles which switch halves trying to find a shuffle of the same
21355 /// pair of dwords.
21356 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21358 TargetLowering::DAGCombinerInfo &DCI) {
21360 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21361 "Called with something other than an x86 128-bit half shuffle!");
21363 unsigned CombineOpcode = N.getOpcode();
21365 // Walk up a single-use chain looking for a combinable shuffle.
21366 SDValue V = N.getOperand(0);
21367 for (; V.hasOneUse(); V = V.getOperand(0)) {
21368 switch (V.getOpcode()) {
21370 return false; // Nothing combined!
21373 // Skip bitcasts as we always know the type for the target specific
21377 case X86ISD::PSHUFLW:
21378 case X86ISD::PSHUFHW:
21379 if (V.getOpcode() == CombineOpcode)
21382 // Other-half shuffles are no-ops.
21385 // Break out of the loop if we break out of the switch.
21389 if (!V.hasOneUse())
21390 // We fell out of the loop without finding a viable combining instruction.
21393 // Combine away the bottom node as its shuffle will be accumulated into
21394 // a preceding shuffle.
21395 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21397 // Record the old value.
21400 // Merge this node's mask and our incoming mask (adjusted to account for all
21401 // the pshufd instructions encountered).
21402 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21403 for (int &M : Mask)
21405 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21406 getV4X86ShuffleImm8ForMask(Mask, DAG));
21408 // Check that the shuffles didn't cancel each other out. If not, we need to
21409 // combine to the new one.
21411 // Replace the combinable shuffle with the combined one, updating all users
21412 // so that we re-evaluate the chain here.
21413 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21418 /// \brief Try to combine x86 target specific shuffles.
21419 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21420 TargetLowering::DAGCombinerInfo &DCI,
21421 const X86Subtarget *Subtarget) {
21423 MVT VT = N.getSimpleValueType();
21424 SmallVector<int, 4> Mask;
21426 switch (N.getOpcode()) {
21427 case X86ISD::PSHUFD:
21428 case X86ISD::PSHUFLW:
21429 case X86ISD::PSHUFHW:
21430 Mask = getPSHUFShuffleMask(N);
21431 assert(Mask.size() == 4);
21437 // Nuke no-op shuffles that show up after combining.
21438 if (isNoopShuffleMask(Mask))
21439 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21441 // Look for simplifications involving one or two shuffle instructions.
21442 SDValue V = N.getOperand(0);
21443 switch (N.getOpcode()) {
21446 case X86ISD::PSHUFLW:
21447 case X86ISD::PSHUFHW:
21448 assert(VT == MVT::v8i16);
21451 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21452 return SDValue(); // We combined away this shuffle, so we're done.
21454 // See if this reduces to a PSHUFD which is no more expensive and can
21455 // combine with more operations. Note that it has to at least flip the
21456 // dwords as otherwise it would have been removed as a no-op.
21457 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21458 int DMask[] = {0, 1, 2, 3};
21459 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21460 DMask[DOffset + 0] = DOffset + 1;
21461 DMask[DOffset + 1] = DOffset + 0;
21462 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21463 DCI.AddToWorklist(V.getNode());
21464 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21465 getV4X86ShuffleImm8ForMask(DMask, DAG));
21466 DCI.AddToWorklist(V.getNode());
21467 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21470 // Look for shuffle patterns which can be implemented as a single unpack.
21471 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21472 // only works when we have a PSHUFD followed by two half-shuffles.
21473 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21474 (V.getOpcode() == X86ISD::PSHUFLW ||
21475 V.getOpcode() == X86ISD::PSHUFHW) &&
21476 V.getOpcode() != N.getOpcode() &&
21478 SDValue D = V.getOperand(0);
21479 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21480 D = D.getOperand(0);
21481 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21482 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21483 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21484 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21485 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21487 for (int i = 0; i < 4; ++i) {
21488 WordMask[i + NOffset] = Mask[i] + NOffset;
21489 WordMask[i + VOffset] = VMask[i] + VOffset;
21491 // Map the word mask through the DWord mask.
21493 for (int i = 0; i < 8; ++i)
21494 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21495 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21496 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21497 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21498 std::begin(UnpackLoMask)) ||
21499 std::equal(std::begin(MappedMask), std::end(MappedMask),
21500 std::begin(UnpackHiMask))) {
21501 // We can replace all three shuffles with an unpack.
21502 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21503 DCI.AddToWorklist(V.getNode());
21504 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21506 DL, MVT::v8i16, V, V);
21513 case X86ISD::PSHUFD:
21514 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21523 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21525 /// We combine this directly on the abstract vector shuffle nodes so it is
21526 /// easier to generically match. We also insert dummy vector shuffle nodes for
21527 /// the operands which explicitly discard the lanes which are unused by this
21528 /// operation to try to flow through the rest of the combiner the fact that
21529 /// they're unused.
21530 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21532 EVT VT = N->getValueType(0);
21534 // We only handle target-independent shuffles.
21535 // FIXME: It would be easy and harmless to use the target shuffle mask
21536 // extraction tool to support more.
21537 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21540 auto *SVN = cast<ShuffleVectorSDNode>(N);
21541 ArrayRef<int> Mask = SVN->getMask();
21542 SDValue V1 = N->getOperand(0);
21543 SDValue V2 = N->getOperand(1);
21545 // We require the first shuffle operand to be the SUB node, and the second to
21546 // be the ADD node.
21547 // FIXME: We should support the commuted patterns.
21548 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21551 // If there are other uses of these operations we can't fold them.
21552 if (!V1->hasOneUse() || !V2->hasOneUse())
21555 // Ensure that both operations have the same operands. Note that we can
21556 // commute the FADD operands.
21557 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21558 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21559 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21562 // We're looking for blends between FADD and FSUB nodes. We insist on these
21563 // nodes being lined up in a specific expected pattern.
21564 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21565 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21566 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21569 // Only specific types are legal at this point, assert so we notice if and
21570 // when these change.
21571 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21572 VT == MVT::v4f64) &&
21573 "Unknown vector type encountered!");
21575 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21578 /// PerformShuffleCombine - Performs several different shuffle combines.
21579 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21580 TargetLowering::DAGCombinerInfo &DCI,
21581 const X86Subtarget *Subtarget) {
21583 SDValue N0 = N->getOperand(0);
21584 SDValue N1 = N->getOperand(1);
21585 EVT VT = N->getValueType(0);
21587 // Don't create instructions with illegal types after legalize types has run.
21588 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21589 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21592 // If we have legalized the vector types, look for blends of FADD and FSUB
21593 // nodes that we can fuse into an ADDSUB node.
21594 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21595 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21598 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21599 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21600 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21601 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21603 // During Type Legalization, when promoting illegal vector types,
21604 // the backend might introduce new shuffle dag nodes and bitcasts.
21606 // This code performs the following transformation:
21607 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21608 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21610 // We do this only if both the bitcast and the BINOP dag nodes have
21611 // one use. Also, perform this transformation only if the new binary
21612 // operation is legal. This is to avoid introducing dag nodes that
21613 // potentially need to be further expanded (or custom lowered) into a
21614 // less optimal sequence of dag nodes.
21615 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21616 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21617 N0.getOpcode() == ISD::BITCAST) {
21618 SDValue BC0 = N0.getOperand(0);
21619 EVT SVT = BC0.getValueType();
21620 unsigned Opcode = BC0.getOpcode();
21621 unsigned NumElts = VT.getVectorNumElements();
21623 if (BC0.hasOneUse() && SVT.isVector() &&
21624 SVT.getVectorNumElements() * 2 == NumElts &&
21625 TLI.isOperationLegal(Opcode, VT)) {
21626 bool CanFold = false;
21638 unsigned SVTNumElts = SVT.getVectorNumElements();
21639 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21640 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21641 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21642 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21643 CanFold = SVOp->getMaskElt(i) < 0;
21646 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21647 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21648 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21649 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21654 // Only handle 128 wide vector from here on.
21655 if (!VT.is128BitVector())
21658 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21659 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21660 // consecutive, non-overlapping, and in the right order.
21661 SmallVector<SDValue, 16> Elts;
21662 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21663 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21665 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21669 if (isTargetShuffle(N->getOpcode())) {
21671 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21672 if (Shuffle.getNode())
21675 // Try recursively combining arbitrary sequences of x86 shuffle
21676 // instructions into higher-order shuffles. We do this after combining
21677 // specific PSHUF instruction sequences into their minimal form so that we
21678 // can evaluate how many specialized shuffle instructions are involved in
21679 // a particular chain.
21680 SmallVector<int, 1> NonceMask; // Just a placeholder.
21681 NonceMask.push_back(0);
21682 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21683 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21685 return SDValue(); // This routine will use CombineTo to replace N.
21691 /// PerformTruncateCombine - Converts truncate operation to
21692 /// a sequence of vector shuffle operations.
21693 /// It is possible when we truncate 256-bit vector to 128-bit vector
21694 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21695 TargetLowering::DAGCombinerInfo &DCI,
21696 const X86Subtarget *Subtarget) {
21700 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21701 /// specific shuffle of a load can be folded into a single element load.
21702 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21703 /// shuffles have been customed lowered so we need to handle those here.
21704 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21705 TargetLowering::DAGCombinerInfo &DCI) {
21706 if (DCI.isBeforeLegalizeOps())
21709 SDValue InVec = N->getOperand(0);
21710 SDValue EltNo = N->getOperand(1);
21712 if (!isa<ConstantSDNode>(EltNo))
21715 EVT VT = InVec.getValueType();
21717 if (InVec.getOpcode() == ISD::BITCAST) {
21718 // Don't duplicate a load with other uses.
21719 if (!InVec.hasOneUse())
21721 EVT BCVT = InVec.getOperand(0).getValueType();
21722 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21724 InVec = InVec.getOperand(0);
21727 if (!isTargetShuffle(InVec.getOpcode()))
21730 // Don't duplicate a load with other uses.
21731 if (!InVec.hasOneUse())
21734 SmallVector<int, 16> ShuffleMask;
21736 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21740 // Select the input vector, guarding against out of range extract vector.
21741 unsigned NumElems = VT.getVectorNumElements();
21742 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21743 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21744 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21745 : InVec.getOperand(1);
21747 // If inputs to shuffle are the same for both ops, then allow 2 uses
21748 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21750 if (LdNode.getOpcode() == ISD::BITCAST) {
21751 // Don't duplicate a load with other uses.
21752 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21755 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21756 LdNode = LdNode.getOperand(0);
21759 if (!ISD::isNormalLoad(LdNode.getNode()))
21762 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21764 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21767 EVT EltVT = N->getValueType(0);
21768 // If there's a bitcast before the shuffle, check if the load type and
21769 // alignment is valid.
21770 unsigned Align = LN0->getAlignment();
21771 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21772 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21773 EltVT.getTypeForEVT(*DAG.getContext()));
21775 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21778 // All checks match so transform back to vector_shuffle so that DAG combiner
21779 // can finish the job
21782 // Create shuffle node taking into account the case that its a unary shuffle
21783 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21784 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21785 InVec.getOperand(0), Shuffle,
21787 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21788 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21792 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21793 /// generation and convert it from being a bunch of shuffles and extracts
21794 /// to a simple store and scalar loads to extract the elements.
21795 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21796 TargetLowering::DAGCombinerInfo &DCI) {
21797 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21798 if (NewOp.getNode())
21801 SDValue InputVector = N->getOperand(0);
21803 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21804 // from mmx to v2i32 has a single usage.
21805 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21806 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21807 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21808 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21809 N->getValueType(0),
21810 InputVector.getNode()->getOperand(0));
21812 // Only operate on vectors of 4 elements, where the alternative shuffling
21813 // gets to be more expensive.
21814 if (InputVector.getValueType() != MVT::v4i32)
21817 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21818 // single use which is a sign-extend or zero-extend, and all elements are
21820 SmallVector<SDNode *, 4> Uses;
21821 unsigned ExtractedElements = 0;
21822 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21823 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21824 if (UI.getUse().getResNo() != InputVector.getResNo())
21827 SDNode *Extract = *UI;
21828 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21831 if (Extract->getValueType(0) != MVT::i32)
21833 if (!Extract->hasOneUse())
21835 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21836 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21838 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21841 // Record which element was extracted.
21842 ExtractedElements |=
21843 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21845 Uses.push_back(Extract);
21848 // If not all the elements were used, this may not be worthwhile.
21849 if (ExtractedElements != 15)
21852 // Ok, we've now decided to do the transformation.
21853 SDLoc dl(InputVector);
21855 // Store the value to a temporary stack slot.
21856 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21857 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21858 MachinePointerInfo(), false, false, 0);
21860 // Replace each use (extract) with a load of the appropriate element.
21861 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21862 UE = Uses.end(); UI != UE; ++UI) {
21863 SDNode *Extract = *UI;
21865 // cOMpute the element's address.
21866 SDValue Idx = Extract->getOperand(1);
21868 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21869 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21870 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21871 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21873 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21874 StackPtr, OffsetVal);
21876 // Load the scalar.
21877 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21878 ScalarAddr, MachinePointerInfo(),
21879 false, false, false, 0);
21881 // Replace the exact with the load.
21882 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21885 // The replacement was made in place; don't return anything.
21889 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21890 static std::pair<unsigned, bool>
21891 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21892 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21893 if (!VT.isVector())
21894 return std::make_pair(0, false);
21896 bool NeedSplit = false;
21897 switch (VT.getSimpleVT().SimpleTy) {
21898 default: return std::make_pair(0, false);
21902 if (!Subtarget->hasAVX2())
21904 if (!Subtarget->hasAVX())
21905 return std::make_pair(0, false);
21910 if (!Subtarget->hasSSE2())
21911 return std::make_pair(0, false);
21914 // SSE2 has only a small subset of the operations.
21915 bool hasUnsigned = Subtarget->hasSSE41() ||
21916 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21917 bool hasSigned = Subtarget->hasSSE41() ||
21918 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21920 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21923 // Check for x CC y ? x : y.
21924 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21925 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21930 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21933 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21936 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21939 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21941 // Check for x CC y ? y : x -- a min/max with reversed arms.
21942 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21943 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21948 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21951 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21954 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21957 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21961 return std::make_pair(Opc, NeedSplit);
21965 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21966 const X86Subtarget *Subtarget) {
21968 SDValue Cond = N->getOperand(0);
21969 SDValue LHS = N->getOperand(1);
21970 SDValue RHS = N->getOperand(2);
21972 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21973 SDValue CondSrc = Cond->getOperand(0);
21974 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21975 Cond = CondSrc->getOperand(0);
21978 MVT VT = N->getSimpleValueType(0);
21979 MVT EltVT = VT.getVectorElementType();
21980 unsigned NumElems = VT.getVectorNumElements();
21981 // There is no blend with immediate in AVX-512.
21982 if (VT.is512BitVector())
21985 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21987 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21990 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21993 // A vselect where all conditions and data are constants can be optimized into
21994 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21995 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21996 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21999 unsigned MaskValue = 0;
22000 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22003 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22004 for (unsigned i = 0; i < NumElems; ++i) {
22005 // Be sure we emit undef where we can.
22006 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22007 ShuffleMask[i] = -1;
22009 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22012 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22015 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22017 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22018 TargetLowering::DAGCombinerInfo &DCI,
22019 const X86Subtarget *Subtarget) {
22021 SDValue Cond = N->getOperand(0);
22022 // Get the LHS/RHS of the select.
22023 SDValue LHS = N->getOperand(1);
22024 SDValue RHS = N->getOperand(2);
22025 EVT VT = LHS.getValueType();
22026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22028 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22029 // instructions match the semantics of the common C idiom x<y?x:y but not
22030 // x<=y?x:y, because of how they handle negative zero (which can be
22031 // ignored in unsafe-math mode).
22032 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22033 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22034 (Subtarget->hasSSE2() ||
22035 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22036 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22038 unsigned Opcode = 0;
22039 // Check for x CC y ? x : y.
22040 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22041 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22045 // Converting this to a min would handle NaNs incorrectly, and swapping
22046 // the operands would cause it to handle comparisons between positive
22047 // and negative zero incorrectly.
22048 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22049 if (!DAG.getTarget().Options.UnsafeFPMath &&
22050 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22052 std::swap(LHS, RHS);
22054 Opcode = X86ISD::FMIN;
22057 // Converting this to a min would handle comparisons between positive
22058 // and negative zero incorrectly.
22059 if (!DAG.getTarget().Options.UnsafeFPMath &&
22060 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22062 Opcode = X86ISD::FMIN;
22065 // Converting this to a min would handle both negative zeros and NaNs
22066 // incorrectly, but we can swap the operands to fix both.
22067 std::swap(LHS, RHS);
22071 Opcode = X86ISD::FMIN;
22075 // Converting this to a max would handle comparisons between positive
22076 // and negative zero incorrectly.
22077 if (!DAG.getTarget().Options.UnsafeFPMath &&
22078 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22080 Opcode = X86ISD::FMAX;
22083 // Converting this to a max would handle NaNs incorrectly, and swapping
22084 // the operands would cause it to handle comparisons between positive
22085 // and negative zero incorrectly.
22086 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22087 if (!DAG.getTarget().Options.UnsafeFPMath &&
22088 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22090 std::swap(LHS, RHS);
22092 Opcode = X86ISD::FMAX;
22095 // Converting this to a max would handle both negative zeros and NaNs
22096 // incorrectly, but we can swap the operands to fix both.
22097 std::swap(LHS, RHS);
22101 Opcode = X86ISD::FMAX;
22104 // Check for x CC y ? y : x -- a min/max with reversed arms.
22105 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22106 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22110 // Converting this to a min would handle comparisons between positive
22111 // and negative zero incorrectly, and swapping the operands would
22112 // cause it to handle NaNs incorrectly.
22113 if (!DAG.getTarget().Options.UnsafeFPMath &&
22114 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22115 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22117 std::swap(LHS, RHS);
22119 Opcode = X86ISD::FMIN;
22122 // Converting this to a min would handle NaNs incorrectly.
22123 if (!DAG.getTarget().Options.UnsafeFPMath &&
22124 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22126 Opcode = X86ISD::FMIN;
22129 // Converting this to a min would handle both negative zeros and NaNs
22130 // incorrectly, but we can swap the operands to fix both.
22131 std::swap(LHS, RHS);
22135 Opcode = X86ISD::FMIN;
22139 // Converting this to a max would handle NaNs incorrectly.
22140 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22142 Opcode = X86ISD::FMAX;
22145 // Converting this to a max would handle comparisons between positive
22146 // and negative zero incorrectly, and swapping the operands would
22147 // cause it to handle NaNs incorrectly.
22148 if (!DAG.getTarget().Options.UnsafeFPMath &&
22149 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22150 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22152 std::swap(LHS, RHS);
22154 Opcode = X86ISD::FMAX;
22157 // Converting this to a max would handle both negative zeros and NaNs
22158 // incorrectly, but we can swap the operands to fix both.
22159 std::swap(LHS, RHS);
22163 Opcode = X86ISD::FMAX;
22169 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22172 EVT CondVT = Cond.getValueType();
22173 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22174 CondVT.getVectorElementType() == MVT::i1) {
22175 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22176 // lowering on KNL. In this case we convert it to
22177 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22178 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22179 // Since SKX these selects have a proper lowering.
22180 EVT OpVT = LHS.getValueType();
22181 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22182 (OpVT.getVectorElementType() == MVT::i8 ||
22183 OpVT.getVectorElementType() == MVT::i16) &&
22184 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22185 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22186 DCI.AddToWorklist(Cond.getNode());
22187 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22190 // If this is a select between two integer constants, try to do some
22192 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22193 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22194 // Don't do this for crazy integer types.
22195 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22196 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22197 // so that TrueC (the true value) is larger than FalseC.
22198 bool NeedsCondInvert = false;
22200 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22201 // Efficiently invertible.
22202 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22203 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22204 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22205 NeedsCondInvert = true;
22206 std::swap(TrueC, FalseC);
22209 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22210 if (FalseC->getAPIntValue() == 0 &&
22211 TrueC->getAPIntValue().isPowerOf2()) {
22212 if (NeedsCondInvert) // Invert the condition if needed.
22213 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22214 DAG.getConstant(1, Cond.getValueType()));
22216 // Zero extend the condition if needed.
22217 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22219 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22220 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22221 DAG.getConstant(ShAmt, MVT::i8));
22224 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22225 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22226 if (NeedsCondInvert) // Invert the condition if needed.
22227 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22228 DAG.getConstant(1, Cond.getValueType()));
22230 // Zero extend the condition if needed.
22231 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22232 FalseC->getValueType(0), Cond);
22233 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22234 SDValue(FalseC, 0));
22237 // Optimize cases that will turn into an LEA instruction. This requires
22238 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22239 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22240 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22241 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22243 bool isFastMultiplier = false;
22245 switch ((unsigned char)Diff) {
22247 case 1: // result = add base, cond
22248 case 2: // result = lea base( , cond*2)
22249 case 3: // result = lea base(cond, cond*2)
22250 case 4: // result = lea base( , cond*4)
22251 case 5: // result = lea base(cond, cond*4)
22252 case 8: // result = lea base( , cond*8)
22253 case 9: // result = lea base(cond, cond*8)
22254 isFastMultiplier = true;
22259 if (isFastMultiplier) {
22260 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22261 if (NeedsCondInvert) // Invert the condition if needed.
22262 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22263 DAG.getConstant(1, Cond.getValueType()));
22265 // Zero extend the condition if needed.
22266 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22268 // Scale the condition by the difference.
22270 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22271 DAG.getConstant(Diff, Cond.getValueType()));
22273 // Add the base if non-zero.
22274 if (FalseC->getAPIntValue() != 0)
22275 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22276 SDValue(FalseC, 0));
22283 // Canonicalize max and min:
22284 // (x > y) ? x : y -> (x >= y) ? x : y
22285 // (x < y) ? x : y -> (x <= y) ? x : y
22286 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22287 // the need for an extra compare
22288 // against zero. e.g.
22289 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22291 // testl %edi, %edi
22293 // cmovgl %edi, %eax
22297 // cmovsl %eax, %edi
22298 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22299 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22300 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22301 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22306 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22307 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22308 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22309 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22314 // Early exit check
22315 if (!TLI.isTypeLegal(VT))
22318 // Match VSELECTs into subs with unsigned saturation.
22319 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22320 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22321 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22322 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22323 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22325 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22326 // left side invert the predicate to simplify logic below.
22328 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22330 CC = ISD::getSetCCInverse(CC, true);
22331 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22335 if (Other.getNode() && Other->getNumOperands() == 2 &&
22336 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22337 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22338 SDValue CondRHS = Cond->getOperand(1);
22340 // Look for a general sub with unsigned saturation first.
22341 // x >= y ? x-y : 0 --> subus x, y
22342 // x > y ? x-y : 0 --> subus x, y
22343 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22344 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22345 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22347 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22348 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22349 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22350 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22351 // If the RHS is a constant we have to reverse the const
22352 // canonicalization.
22353 // x > C-1 ? x+-C : 0 --> subus x, C
22354 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22355 CondRHSConst->getAPIntValue() ==
22356 (-OpRHSConst->getAPIntValue() - 1))
22357 return DAG.getNode(
22358 X86ISD::SUBUS, DL, VT, OpLHS,
22359 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22361 // Another special case: If C was a sign bit, the sub has been
22362 // canonicalized into a xor.
22363 // FIXME: Would it be better to use computeKnownBits to determine
22364 // whether it's safe to decanonicalize the xor?
22365 // x s< 0 ? x^C : 0 --> subus x, C
22366 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22367 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22368 OpRHSConst->getAPIntValue().isSignBit())
22369 // Note that we have to rebuild the RHS constant here to ensure we
22370 // don't rely on particular values of undef lanes.
22371 return DAG.getNode(
22372 X86ISD::SUBUS, DL, VT, OpLHS,
22373 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22378 // Try to match a min/max vector operation.
22379 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22380 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22381 unsigned Opc = ret.first;
22382 bool NeedSplit = ret.second;
22384 if (Opc && NeedSplit) {
22385 unsigned NumElems = VT.getVectorNumElements();
22386 // Extract the LHS vectors
22387 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22388 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22390 // Extract the RHS vectors
22391 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22392 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22394 // Create min/max for each subvector
22395 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22396 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22398 // Merge the result
22399 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22401 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22404 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
22405 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22406 // Check if SETCC has already been promoted
22407 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
22408 // Check that condition value type matches vselect operand type
22411 assert(Cond.getValueType().isVector() &&
22412 "vector select expects a vector selector!");
22414 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22415 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22417 if (!TValIsAllOnes && !FValIsAllZeros) {
22418 // Try invert the condition if true value is not all 1s and false value
22420 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22421 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22423 if (TValIsAllZeros || FValIsAllOnes) {
22424 SDValue CC = Cond.getOperand(2);
22425 ISD::CondCode NewCC =
22426 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22427 Cond.getOperand(0).getValueType().isInteger());
22428 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22429 std::swap(LHS, RHS);
22430 TValIsAllOnes = FValIsAllOnes;
22431 FValIsAllZeros = TValIsAllZeros;
22435 if (TValIsAllOnes || FValIsAllZeros) {
22438 if (TValIsAllOnes && FValIsAllZeros)
22440 else if (TValIsAllOnes)
22441 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22442 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22443 else if (FValIsAllZeros)
22444 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22445 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22447 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22451 // Try to fold this VSELECT into a MOVSS/MOVSD
22452 if (N->getOpcode() == ISD::VSELECT &&
22453 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22454 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22455 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22456 bool CanFold = false;
22457 unsigned NumElems = Cond.getNumOperands();
22461 if (isZero(Cond.getOperand(0))) {
22464 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22465 // fold (vselect <0,-1> -> (movsd A, B)
22466 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22467 CanFold = isAllOnes(Cond.getOperand(i));
22468 } else if (isAllOnes(Cond.getOperand(0))) {
22472 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22473 // fold (vselect <-1,0> -> (movsd B, A)
22474 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22475 CanFold = isZero(Cond.getOperand(i));
22479 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22480 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22481 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22484 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22485 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22486 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22487 // (v2i64 (bitcast B)))))
22489 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22490 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22491 // (v2f64 (bitcast B)))))
22493 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22494 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22495 // (v2i64 (bitcast A)))))
22497 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22498 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22499 // (v2f64 (bitcast A)))))
22501 CanFold = (isZero(Cond.getOperand(0)) &&
22502 isZero(Cond.getOperand(1)) &&
22503 isAllOnes(Cond.getOperand(2)) &&
22504 isAllOnes(Cond.getOperand(3)));
22506 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22507 isAllOnes(Cond.getOperand(1)) &&
22508 isZero(Cond.getOperand(2)) &&
22509 isZero(Cond.getOperand(3))) {
22511 std::swap(LHS, RHS);
22515 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22516 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22517 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22518 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22520 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22526 // If we know that this node is legal then we know that it is going to be
22527 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22528 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22529 // to simplify previous instructions.
22530 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22531 !DCI.isBeforeLegalize() &&
22532 // We explicitly check against v8i16 and v16i16 because, although
22533 // they're marked as Custom, they might only be legal when Cond is a
22534 // build_vector of constants. This will be taken care in a later
22536 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22537 VT != MVT::v8i16)) {
22538 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22540 // Don't optimize vector selects that map to mask-registers.
22544 // Check all uses of that condition operand to check whether it will be
22545 // consumed by non-BLEND instructions, which may depend on all bits are set
22547 for (SDNode::use_iterator I = Cond->use_begin(),
22548 E = Cond->use_end(); I != E; ++I)
22549 if (I->getOpcode() != ISD::VSELECT)
22550 // TODO: Add other opcodes eventually lowered into BLEND.
22553 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22554 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22556 APInt KnownZero, KnownOne;
22557 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22558 DCI.isBeforeLegalizeOps());
22559 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22560 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
22561 DCI.CommitTargetLoweringOpt(TLO);
22564 // We should generate an X86ISD::BLENDI from a vselect if its argument
22565 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22566 // constants. This specific pattern gets generated when we split a
22567 // selector for a 512 bit vector in a machine without AVX512 (but with
22568 // 256-bit vectors), during legalization:
22570 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22572 // Iff we find this pattern and the build_vectors are built from
22573 // constants, we translate the vselect into a shuffle_vector that we
22574 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22575 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
22576 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22577 if (Shuffle.getNode())
22584 // Check whether a boolean test is testing a boolean value generated by
22585 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22588 // Simplify the following patterns:
22589 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22590 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22591 // to (Op EFLAGS Cond)
22593 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22594 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22595 // to (Op EFLAGS !Cond)
22597 // where Op could be BRCOND or CMOV.
22599 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22600 // Quit if not CMP and SUB with its value result used.
22601 if (Cmp.getOpcode() != X86ISD::CMP &&
22602 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22605 // Quit if not used as a boolean value.
22606 if (CC != X86::COND_E && CC != X86::COND_NE)
22609 // Check CMP operands. One of them should be 0 or 1 and the other should be
22610 // an SetCC or extended from it.
22611 SDValue Op1 = Cmp.getOperand(0);
22612 SDValue Op2 = Cmp.getOperand(1);
22615 const ConstantSDNode* C = nullptr;
22616 bool needOppositeCond = (CC == X86::COND_E);
22617 bool checkAgainstTrue = false; // Is it a comparison against 1?
22619 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22621 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22623 else // Quit if all operands are not constants.
22626 if (C->getZExtValue() == 1) {
22627 needOppositeCond = !needOppositeCond;
22628 checkAgainstTrue = true;
22629 } else if (C->getZExtValue() != 0)
22630 // Quit if the constant is neither 0 or 1.
22633 bool truncatedToBoolWithAnd = false;
22634 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22635 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22636 SetCC.getOpcode() == ISD::TRUNCATE ||
22637 SetCC.getOpcode() == ISD::AND) {
22638 if (SetCC.getOpcode() == ISD::AND) {
22640 ConstantSDNode *CS;
22641 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22642 CS->getZExtValue() == 1)
22644 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22645 CS->getZExtValue() == 1)
22649 SetCC = SetCC.getOperand(OpIdx);
22650 truncatedToBoolWithAnd = true;
22652 SetCC = SetCC.getOperand(0);
22655 switch (SetCC.getOpcode()) {
22656 case X86ISD::SETCC_CARRY:
22657 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22658 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22659 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22660 // truncated to i1 using 'and'.
22661 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22663 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22664 "Invalid use of SETCC_CARRY!");
22666 case X86ISD::SETCC:
22667 // Set the condition code or opposite one if necessary.
22668 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22669 if (needOppositeCond)
22670 CC = X86::GetOppositeBranchCondition(CC);
22671 return SetCC.getOperand(1);
22672 case X86ISD::CMOV: {
22673 // Check whether false/true value has canonical one, i.e. 0 or 1.
22674 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22675 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22676 // Quit if true value is not a constant.
22679 // Quit if false value is not a constant.
22681 SDValue Op = SetCC.getOperand(0);
22682 // Skip 'zext' or 'trunc' node.
22683 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22684 Op.getOpcode() == ISD::TRUNCATE)
22685 Op = Op.getOperand(0);
22686 // A special case for rdrand/rdseed, where 0 is set if false cond is
22688 if ((Op.getOpcode() != X86ISD::RDRAND &&
22689 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22692 // Quit if false value is not the constant 0 or 1.
22693 bool FValIsFalse = true;
22694 if (FVal && FVal->getZExtValue() != 0) {
22695 if (FVal->getZExtValue() != 1)
22697 // If FVal is 1, opposite cond is needed.
22698 needOppositeCond = !needOppositeCond;
22699 FValIsFalse = false;
22701 // Quit if TVal is not the constant opposite of FVal.
22702 if (FValIsFalse && TVal->getZExtValue() != 1)
22704 if (!FValIsFalse && TVal->getZExtValue() != 0)
22706 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22707 if (needOppositeCond)
22708 CC = X86::GetOppositeBranchCondition(CC);
22709 return SetCC.getOperand(3);
22716 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22717 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22718 TargetLowering::DAGCombinerInfo &DCI,
22719 const X86Subtarget *Subtarget) {
22722 // If the flag operand isn't dead, don't touch this CMOV.
22723 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22726 SDValue FalseOp = N->getOperand(0);
22727 SDValue TrueOp = N->getOperand(1);
22728 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22729 SDValue Cond = N->getOperand(3);
22731 if (CC == X86::COND_E || CC == X86::COND_NE) {
22732 switch (Cond.getOpcode()) {
22736 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22737 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22738 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22744 Flags = checkBoolTestSetCCCombine(Cond, CC);
22745 if (Flags.getNode() &&
22746 // Extra check as FCMOV only supports a subset of X86 cond.
22747 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22748 SDValue Ops[] = { FalseOp, TrueOp,
22749 DAG.getConstant(CC, MVT::i8), Flags };
22750 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22753 // If this is a select between two integer constants, try to do some
22754 // optimizations. Note that the operands are ordered the opposite of SELECT
22756 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22757 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22758 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22759 // larger than FalseC (the false value).
22760 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22761 CC = X86::GetOppositeBranchCondition(CC);
22762 std::swap(TrueC, FalseC);
22763 std::swap(TrueOp, FalseOp);
22766 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22767 // This is efficient for any integer data type (including i8/i16) and
22769 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22770 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22771 DAG.getConstant(CC, MVT::i8), Cond);
22773 // Zero extend the condition if needed.
22774 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22776 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22777 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22778 DAG.getConstant(ShAmt, MVT::i8));
22779 if (N->getNumValues() == 2) // Dead flag value?
22780 return DCI.CombineTo(N, Cond, SDValue());
22784 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22785 // for any integer data type, including i8/i16.
22786 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22787 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22788 DAG.getConstant(CC, MVT::i8), Cond);
22790 // Zero extend the condition if needed.
22791 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22792 FalseC->getValueType(0), Cond);
22793 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22794 SDValue(FalseC, 0));
22796 if (N->getNumValues() == 2) // Dead flag value?
22797 return DCI.CombineTo(N, Cond, SDValue());
22801 // Optimize cases that will turn into an LEA instruction. This requires
22802 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22803 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22804 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22805 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22807 bool isFastMultiplier = false;
22809 switch ((unsigned char)Diff) {
22811 case 1: // result = add base, cond
22812 case 2: // result = lea base( , cond*2)
22813 case 3: // result = lea base(cond, cond*2)
22814 case 4: // result = lea base( , cond*4)
22815 case 5: // result = lea base(cond, cond*4)
22816 case 8: // result = lea base( , cond*8)
22817 case 9: // result = lea base(cond, cond*8)
22818 isFastMultiplier = true;
22823 if (isFastMultiplier) {
22824 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22825 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22826 DAG.getConstant(CC, MVT::i8), Cond);
22827 // Zero extend the condition if needed.
22828 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22830 // Scale the condition by the difference.
22832 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22833 DAG.getConstant(Diff, Cond.getValueType()));
22835 // Add the base if non-zero.
22836 if (FalseC->getAPIntValue() != 0)
22837 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22838 SDValue(FalseC, 0));
22839 if (N->getNumValues() == 2) // Dead flag value?
22840 return DCI.CombineTo(N, Cond, SDValue());
22847 // Handle these cases:
22848 // (select (x != c), e, c) -> select (x != c), e, x),
22849 // (select (x == c), c, e) -> select (x == c), x, e)
22850 // where the c is an integer constant, and the "select" is the combination
22851 // of CMOV and CMP.
22853 // The rationale for this change is that the conditional-move from a constant
22854 // needs two instructions, however, conditional-move from a register needs
22855 // only one instruction.
22857 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22858 // some instruction-combining opportunities. This opt needs to be
22859 // postponed as late as possible.
22861 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22862 // the DCI.xxxx conditions are provided to postpone the optimization as
22863 // late as possible.
22865 ConstantSDNode *CmpAgainst = nullptr;
22866 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22867 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22868 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22870 if (CC == X86::COND_NE &&
22871 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22872 CC = X86::GetOppositeBranchCondition(CC);
22873 std::swap(TrueOp, FalseOp);
22876 if (CC == X86::COND_E &&
22877 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22878 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22879 DAG.getConstant(CC, MVT::i8), Cond };
22880 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22888 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22889 const X86Subtarget *Subtarget) {
22890 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22892 default: return SDValue();
22893 // SSE/AVX/AVX2 blend intrinsics.
22894 case Intrinsic::x86_avx2_pblendvb:
22895 case Intrinsic::x86_avx2_pblendw:
22896 case Intrinsic::x86_avx2_pblendd_128:
22897 case Intrinsic::x86_avx2_pblendd_256:
22898 // Don't try to simplify this intrinsic if we don't have AVX2.
22899 if (!Subtarget->hasAVX2())
22902 case Intrinsic::x86_avx_blend_pd_256:
22903 case Intrinsic::x86_avx_blend_ps_256:
22904 case Intrinsic::x86_avx_blendv_pd_256:
22905 case Intrinsic::x86_avx_blendv_ps_256:
22906 // Don't try to simplify this intrinsic if we don't have AVX.
22907 if (!Subtarget->hasAVX())
22910 case Intrinsic::x86_sse41_pblendw:
22911 case Intrinsic::x86_sse41_blendpd:
22912 case Intrinsic::x86_sse41_blendps:
22913 case Intrinsic::x86_sse41_blendvps:
22914 case Intrinsic::x86_sse41_blendvpd:
22915 case Intrinsic::x86_sse41_pblendvb: {
22916 SDValue Op0 = N->getOperand(1);
22917 SDValue Op1 = N->getOperand(2);
22918 SDValue Mask = N->getOperand(3);
22920 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22921 if (!Subtarget->hasSSE41())
22924 // fold (blend A, A, Mask) -> A
22927 // fold (blend A, B, allZeros) -> A
22928 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22930 // fold (blend A, B, allOnes) -> B
22931 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22934 // Simplify the case where the mask is a constant i32 value.
22935 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22936 if (C->isNullValue())
22938 if (C->isAllOnesValue())
22945 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22946 case Intrinsic::x86_sse2_psrai_w:
22947 case Intrinsic::x86_sse2_psrai_d:
22948 case Intrinsic::x86_avx2_psrai_w:
22949 case Intrinsic::x86_avx2_psrai_d:
22950 case Intrinsic::x86_sse2_psra_w:
22951 case Intrinsic::x86_sse2_psra_d:
22952 case Intrinsic::x86_avx2_psra_w:
22953 case Intrinsic::x86_avx2_psra_d: {
22954 SDValue Op0 = N->getOperand(1);
22955 SDValue Op1 = N->getOperand(2);
22956 EVT VT = Op0.getValueType();
22957 assert(VT.isVector() && "Expected a vector type!");
22959 if (isa<BuildVectorSDNode>(Op1))
22960 Op1 = Op1.getOperand(0);
22962 if (!isa<ConstantSDNode>(Op1))
22965 EVT SVT = VT.getVectorElementType();
22966 unsigned SVTBits = SVT.getSizeInBits();
22968 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22969 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22970 uint64_t ShAmt = C.getZExtValue();
22972 // Don't try to convert this shift into a ISD::SRA if the shift
22973 // count is bigger than or equal to the element size.
22974 if (ShAmt >= SVTBits)
22977 // Trivial case: if the shift count is zero, then fold this
22978 // into the first operand.
22982 // Replace this packed shift intrinsic with a target independent
22984 SDValue Splat = DAG.getConstant(C, VT);
22985 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22990 /// PerformMulCombine - Optimize a single multiply with constant into two
22991 /// in order to implement it with two cheaper instructions, e.g.
22992 /// LEA + SHL, LEA + LEA.
22993 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22994 TargetLowering::DAGCombinerInfo &DCI) {
22995 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22998 EVT VT = N->getValueType(0);
22999 if (VT != MVT::i64)
23002 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23005 uint64_t MulAmt = C->getZExtValue();
23006 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23009 uint64_t MulAmt1 = 0;
23010 uint64_t MulAmt2 = 0;
23011 if ((MulAmt % 9) == 0) {
23013 MulAmt2 = MulAmt / 9;
23014 } else if ((MulAmt % 5) == 0) {
23016 MulAmt2 = MulAmt / 5;
23017 } else if ((MulAmt % 3) == 0) {
23019 MulAmt2 = MulAmt / 3;
23022 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23025 if (isPowerOf2_64(MulAmt2) &&
23026 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23027 // If second multiplifer is pow2, issue it first. We want the multiply by
23028 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23030 std::swap(MulAmt1, MulAmt2);
23033 if (isPowerOf2_64(MulAmt1))
23034 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23035 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23037 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23038 DAG.getConstant(MulAmt1, VT));
23040 if (isPowerOf2_64(MulAmt2))
23041 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23042 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23044 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23045 DAG.getConstant(MulAmt2, VT));
23047 // Do not add new nodes to DAG combiner worklist.
23048 DCI.CombineTo(N, NewMul, false);
23053 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23054 SDValue N0 = N->getOperand(0);
23055 SDValue N1 = N->getOperand(1);
23056 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23057 EVT VT = N0.getValueType();
23059 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23060 // since the result of setcc_c is all zero's or all ones.
23061 if (VT.isInteger() && !VT.isVector() &&
23062 N1C && N0.getOpcode() == ISD::AND &&
23063 N0.getOperand(1).getOpcode() == ISD::Constant) {
23064 SDValue N00 = N0.getOperand(0);
23065 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23066 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23067 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23068 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23069 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23070 APInt ShAmt = N1C->getAPIntValue();
23071 Mask = Mask.shl(ShAmt);
23073 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23074 N00, DAG.getConstant(Mask, VT));
23078 // Hardware support for vector shifts is sparse which makes us scalarize the
23079 // vector operations in many cases. Also, on sandybridge ADD is faster than
23081 // (shl V, 1) -> add V,V
23082 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23083 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23084 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23085 // We shift all of the values by one. In many cases we do not have
23086 // hardware support for this operation. This is better expressed as an ADD
23088 if (N1SplatC->getZExtValue() == 1)
23089 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23095 /// \brief Returns a vector of 0s if the node in input is a vector logical
23096 /// shift by a constant amount which is known to be bigger than or equal
23097 /// to the vector element size in bits.
23098 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23099 const X86Subtarget *Subtarget) {
23100 EVT VT = N->getValueType(0);
23102 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23103 (!Subtarget->hasInt256() ||
23104 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23107 SDValue Amt = N->getOperand(1);
23109 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23110 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23111 APInt ShiftAmt = AmtSplat->getAPIntValue();
23112 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23114 // SSE2/AVX2 logical shifts always return a vector of 0s
23115 // if the shift amount is bigger than or equal to
23116 // the element size. The constant shift amount will be
23117 // encoded as a 8-bit immediate.
23118 if (ShiftAmt.trunc(8).uge(MaxAmount))
23119 return getZeroVector(VT, Subtarget, DAG, DL);
23125 /// PerformShiftCombine - Combine shifts.
23126 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23127 TargetLowering::DAGCombinerInfo &DCI,
23128 const X86Subtarget *Subtarget) {
23129 if (N->getOpcode() == ISD::SHL) {
23130 SDValue V = PerformSHLCombine(N, DAG);
23131 if (V.getNode()) return V;
23134 if (N->getOpcode() != ISD::SRA) {
23135 // Try to fold this logical shift into a zero vector.
23136 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23137 if (V.getNode()) return V;
23143 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23144 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23145 // and friends. Likewise for OR -> CMPNEQSS.
23146 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23147 TargetLowering::DAGCombinerInfo &DCI,
23148 const X86Subtarget *Subtarget) {
23151 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23152 // we're requiring SSE2 for both.
23153 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23154 SDValue N0 = N->getOperand(0);
23155 SDValue N1 = N->getOperand(1);
23156 SDValue CMP0 = N0->getOperand(1);
23157 SDValue CMP1 = N1->getOperand(1);
23160 // The SETCCs should both refer to the same CMP.
23161 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23164 SDValue CMP00 = CMP0->getOperand(0);
23165 SDValue CMP01 = CMP0->getOperand(1);
23166 EVT VT = CMP00.getValueType();
23168 if (VT == MVT::f32 || VT == MVT::f64) {
23169 bool ExpectingFlags = false;
23170 // Check for any users that want flags:
23171 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23172 !ExpectingFlags && UI != UE; ++UI)
23173 switch (UI->getOpcode()) {
23178 ExpectingFlags = true;
23180 case ISD::CopyToReg:
23181 case ISD::SIGN_EXTEND:
23182 case ISD::ZERO_EXTEND:
23183 case ISD::ANY_EXTEND:
23187 if (!ExpectingFlags) {
23188 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23189 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23191 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23192 X86::CondCode tmp = cc0;
23197 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23198 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23199 // FIXME: need symbolic constants for these magic numbers.
23200 // See X86ATTInstPrinter.cpp:printSSECC().
23201 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23202 if (Subtarget->hasAVX512()) {
23203 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23204 CMP01, DAG.getConstant(x86cc, MVT::i8));
23205 if (N->getValueType(0) != MVT::i1)
23206 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23210 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23211 CMP00.getValueType(), CMP00, CMP01,
23212 DAG.getConstant(x86cc, MVT::i8));
23214 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23215 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23217 if (is64BitFP && !Subtarget->is64Bit()) {
23218 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23219 // 64-bit integer, since that's not a legal type. Since
23220 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23221 // bits, but can do this little dance to extract the lowest 32 bits
23222 // and work with those going forward.
23223 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23225 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23227 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23228 Vector32, DAG.getIntPtrConstant(0));
23232 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23233 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23234 DAG.getConstant(1, IntVT));
23235 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23236 return OneBitOfTruth;
23244 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23245 /// so it can be folded inside ANDNP.
23246 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23247 EVT VT = N->getValueType(0);
23249 // Match direct AllOnes for 128 and 256-bit vectors
23250 if (ISD::isBuildVectorAllOnes(N))
23253 // Look through a bit convert.
23254 if (N->getOpcode() == ISD::BITCAST)
23255 N = N->getOperand(0).getNode();
23257 // Sometimes the operand may come from a insert_subvector building a 256-bit
23259 if (VT.is256BitVector() &&
23260 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23261 SDValue V1 = N->getOperand(0);
23262 SDValue V2 = N->getOperand(1);
23264 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23265 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23266 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23267 ISD::isBuildVectorAllOnes(V2.getNode()))
23274 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23275 // register. In most cases we actually compare or select YMM-sized registers
23276 // and mixing the two types creates horrible code. This method optimizes
23277 // some of the transition sequences.
23278 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23279 TargetLowering::DAGCombinerInfo &DCI,
23280 const X86Subtarget *Subtarget) {
23281 EVT VT = N->getValueType(0);
23282 if (!VT.is256BitVector())
23285 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23286 N->getOpcode() == ISD::ZERO_EXTEND ||
23287 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23289 SDValue Narrow = N->getOperand(0);
23290 EVT NarrowVT = Narrow->getValueType(0);
23291 if (!NarrowVT.is128BitVector())
23294 if (Narrow->getOpcode() != ISD::XOR &&
23295 Narrow->getOpcode() != ISD::AND &&
23296 Narrow->getOpcode() != ISD::OR)
23299 SDValue N0 = Narrow->getOperand(0);
23300 SDValue N1 = Narrow->getOperand(1);
23303 // The Left side has to be a trunc.
23304 if (N0.getOpcode() != ISD::TRUNCATE)
23307 // The type of the truncated inputs.
23308 EVT WideVT = N0->getOperand(0)->getValueType(0);
23312 // The right side has to be a 'trunc' or a constant vector.
23313 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23314 ConstantSDNode *RHSConstSplat = nullptr;
23315 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23316 RHSConstSplat = RHSBV->getConstantSplatNode();
23317 if (!RHSTrunc && !RHSConstSplat)
23320 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23322 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23325 // Set N0 and N1 to hold the inputs to the new wide operation.
23326 N0 = N0->getOperand(0);
23327 if (RHSConstSplat) {
23328 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23329 SDValue(RHSConstSplat, 0));
23330 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23331 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23332 } else if (RHSTrunc) {
23333 N1 = N1->getOperand(0);
23336 // Generate the wide operation.
23337 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23338 unsigned Opcode = N->getOpcode();
23340 case ISD::ANY_EXTEND:
23342 case ISD::ZERO_EXTEND: {
23343 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23344 APInt Mask = APInt::getAllOnesValue(InBits);
23345 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23346 return DAG.getNode(ISD::AND, DL, VT,
23347 Op, DAG.getConstant(Mask, VT));
23349 case ISD::SIGN_EXTEND:
23350 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23351 Op, DAG.getValueType(NarrowVT));
23353 llvm_unreachable("Unexpected opcode");
23357 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23358 TargetLowering::DAGCombinerInfo &DCI,
23359 const X86Subtarget *Subtarget) {
23360 EVT VT = N->getValueType(0);
23361 if (DCI.isBeforeLegalizeOps())
23364 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23368 // Create BEXTR instructions
23369 // BEXTR is ((X >> imm) & (2**size-1))
23370 if (VT == MVT::i32 || VT == MVT::i64) {
23371 SDValue N0 = N->getOperand(0);
23372 SDValue N1 = N->getOperand(1);
23375 // Check for BEXTR.
23376 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23377 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23378 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23379 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23380 if (MaskNode && ShiftNode) {
23381 uint64_t Mask = MaskNode->getZExtValue();
23382 uint64_t Shift = ShiftNode->getZExtValue();
23383 if (isMask_64(Mask)) {
23384 uint64_t MaskSize = CountPopulation_64(Mask);
23385 if (Shift + MaskSize <= VT.getSizeInBits())
23386 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23387 DAG.getConstant(Shift | (MaskSize << 8), VT));
23395 // Want to form ANDNP nodes:
23396 // 1) In the hopes of then easily combining them with OR and AND nodes
23397 // to form PBLEND/PSIGN.
23398 // 2) To match ANDN packed intrinsics
23399 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23402 SDValue N0 = N->getOperand(0);
23403 SDValue N1 = N->getOperand(1);
23406 // Check LHS for vnot
23407 if (N0.getOpcode() == ISD::XOR &&
23408 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23409 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23410 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23412 // Check RHS for vnot
23413 if (N1.getOpcode() == ISD::XOR &&
23414 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23415 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23416 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23421 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23422 TargetLowering::DAGCombinerInfo &DCI,
23423 const X86Subtarget *Subtarget) {
23424 if (DCI.isBeforeLegalizeOps())
23427 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23431 SDValue N0 = N->getOperand(0);
23432 SDValue N1 = N->getOperand(1);
23433 EVT VT = N->getValueType(0);
23435 // look for psign/blend
23436 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23437 if (!Subtarget->hasSSSE3() ||
23438 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23441 // Canonicalize pandn to RHS
23442 if (N0.getOpcode() == X86ISD::ANDNP)
23444 // or (and (m, y), (pandn m, x))
23445 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23446 SDValue Mask = N1.getOperand(0);
23447 SDValue X = N1.getOperand(1);
23449 if (N0.getOperand(0) == Mask)
23450 Y = N0.getOperand(1);
23451 if (N0.getOperand(1) == Mask)
23452 Y = N0.getOperand(0);
23454 // Check to see if the mask appeared in both the AND and ANDNP and
23458 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23459 // Look through mask bitcast.
23460 if (Mask.getOpcode() == ISD::BITCAST)
23461 Mask = Mask.getOperand(0);
23462 if (X.getOpcode() == ISD::BITCAST)
23463 X = X.getOperand(0);
23464 if (Y.getOpcode() == ISD::BITCAST)
23465 Y = Y.getOperand(0);
23467 EVT MaskVT = Mask.getValueType();
23469 // Validate that the Mask operand is a vector sra node.
23470 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23471 // there is no psrai.b
23472 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23473 unsigned SraAmt = ~0;
23474 if (Mask.getOpcode() == ISD::SRA) {
23475 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23476 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23477 SraAmt = AmtConst->getZExtValue();
23478 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23479 SDValue SraC = Mask.getOperand(1);
23480 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23482 if ((SraAmt + 1) != EltBits)
23487 // Now we know we at least have a plendvb with the mask val. See if
23488 // we can form a psignb/w/d.
23489 // psign = x.type == y.type == mask.type && y = sub(0, x);
23490 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23491 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23492 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23493 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23494 "Unsupported VT for PSIGN");
23495 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23496 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23498 // PBLENDVB only available on SSE 4.1
23499 if (!Subtarget->hasSSE41())
23502 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23504 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23505 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23506 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23507 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23508 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23512 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23515 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23516 MachineFunction &MF = DAG.getMachineFunction();
23517 bool OptForSize = MF.getFunction()->getAttributes().
23518 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23520 // SHLD/SHRD instructions have lower register pressure, but on some
23521 // platforms they have higher latency than the equivalent
23522 // series of shifts/or that would otherwise be generated.
23523 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23524 // have higher latencies and we are not optimizing for size.
23525 if (!OptForSize && Subtarget->isSHLDSlow())
23528 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23530 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23532 if (!N0.hasOneUse() || !N1.hasOneUse())
23535 SDValue ShAmt0 = N0.getOperand(1);
23536 if (ShAmt0.getValueType() != MVT::i8)
23538 SDValue ShAmt1 = N1.getOperand(1);
23539 if (ShAmt1.getValueType() != MVT::i8)
23541 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23542 ShAmt0 = ShAmt0.getOperand(0);
23543 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23544 ShAmt1 = ShAmt1.getOperand(0);
23547 unsigned Opc = X86ISD::SHLD;
23548 SDValue Op0 = N0.getOperand(0);
23549 SDValue Op1 = N1.getOperand(0);
23550 if (ShAmt0.getOpcode() == ISD::SUB) {
23551 Opc = X86ISD::SHRD;
23552 std::swap(Op0, Op1);
23553 std::swap(ShAmt0, ShAmt1);
23556 unsigned Bits = VT.getSizeInBits();
23557 if (ShAmt1.getOpcode() == ISD::SUB) {
23558 SDValue Sum = ShAmt1.getOperand(0);
23559 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23560 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23561 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23562 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23563 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23564 return DAG.getNode(Opc, DL, VT,
23566 DAG.getNode(ISD::TRUNCATE, DL,
23569 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23570 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23572 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23573 return DAG.getNode(Opc, DL, VT,
23574 N0.getOperand(0), N1.getOperand(0),
23575 DAG.getNode(ISD::TRUNCATE, DL,
23582 // Generate NEG and CMOV for integer abs.
23583 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23584 EVT VT = N->getValueType(0);
23586 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23587 // 8-bit integer abs to NEG and CMOV.
23588 if (VT.isInteger() && VT.getSizeInBits() == 8)
23591 SDValue N0 = N->getOperand(0);
23592 SDValue N1 = N->getOperand(1);
23595 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23596 // and change it to SUB and CMOV.
23597 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23598 N0.getOpcode() == ISD::ADD &&
23599 N0.getOperand(1) == N1 &&
23600 N1.getOpcode() == ISD::SRA &&
23601 N1.getOperand(0) == N0.getOperand(0))
23602 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23603 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23604 // Generate SUB & CMOV.
23605 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23606 DAG.getConstant(0, VT), N0.getOperand(0));
23608 SDValue Ops[] = { N0.getOperand(0), Neg,
23609 DAG.getConstant(X86::COND_GE, MVT::i8),
23610 SDValue(Neg.getNode(), 1) };
23611 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23616 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23617 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23618 TargetLowering::DAGCombinerInfo &DCI,
23619 const X86Subtarget *Subtarget) {
23620 if (DCI.isBeforeLegalizeOps())
23623 if (Subtarget->hasCMov()) {
23624 SDValue RV = performIntegerAbsCombine(N, DAG);
23632 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23633 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23634 TargetLowering::DAGCombinerInfo &DCI,
23635 const X86Subtarget *Subtarget) {
23636 LoadSDNode *Ld = cast<LoadSDNode>(N);
23637 EVT RegVT = Ld->getValueType(0);
23638 EVT MemVT = Ld->getMemoryVT();
23640 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23642 // On Sandybridge unaligned 256bit loads are inefficient.
23643 ISD::LoadExtType Ext = Ld->getExtensionType();
23644 unsigned Alignment = Ld->getAlignment();
23645 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23646 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23647 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23648 unsigned NumElems = RegVT.getVectorNumElements();
23652 SDValue Ptr = Ld->getBasePtr();
23653 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23655 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23657 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23658 Ld->getPointerInfo(), Ld->isVolatile(),
23659 Ld->isNonTemporal(), Ld->isInvariant(),
23661 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23662 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23663 Ld->getPointerInfo(), Ld->isVolatile(),
23664 Ld->isNonTemporal(), Ld->isInvariant(),
23665 std::min(16U, Alignment));
23666 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23668 Load2.getValue(1));
23670 SDValue NewVec = DAG.getUNDEF(RegVT);
23671 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23672 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23673 return DCI.CombineTo(N, NewVec, TF, true);
23679 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23680 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23681 const X86Subtarget *Subtarget) {
23682 StoreSDNode *St = cast<StoreSDNode>(N);
23683 EVT VT = St->getValue().getValueType();
23684 EVT StVT = St->getMemoryVT();
23686 SDValue StoredVal = St->getOperand(1);
23687 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23689 // If we are saving a concatenation of two XMM registers, perform two stores.
23690 // On Sandy Bridge, 256-bit memory operations are executed by two
23691 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23692 // memory operation.
23693 unsigned Alignment = St->getAlignment();
23694 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23695 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23696 StVT == VT && !IsAligned) {
23697 unsigned NumElems = VT.getVectorNumElements();
23701 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23702 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23704 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23705 SDValue Ptr0 = St->getBasePtr();
23706 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23708 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23709 St->getPointerInfo(), St->isVolatile(),
23710 St->isNonTemporal(), Alignment);
23711 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23712 St->getPointerInfo(), St->isVolatile(),
23713 St->isNonTemporal(),
23714 std::min(16U, Alignment));
23715 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23718 // Optimize trunc store (of multiple scalars) to shuffle and store.
23719 // First, pack all of the elements in one place. Next, store to memory
23720 // in fewer chunks.
23721 if (St->isTruncatingStore() && VT.isVector()) {
23722 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23723 unsigned NumElems = VT.getVectorNumElements();
23724 assert(StVT != VT && "Cannot truncate to the same type");
23725 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23726 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23728 // From, To sizes and ElemCount must be pow of two
23729 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23730 // We are going to use the original vector elt for storing.
23731 // Accumulated smaller vector elements must be a multiple of the store size.
23732 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23734 unsigned SizeRatio = FromSz / ToSz;
23736 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23738 // Create a type on which we perform the shuffle
23739 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23740 StVT.getScalarType(), NumElems*SizeRatio);
23742 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23744 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23745 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23746 for (unsigned i = 0; i != NumElems; ++i)
23747 ShuffleVec[i] = i * SizeRatio;
23749 // Can't shuffle using an illegal type.
23750 if (!TLI.isTypeLegal(WideVecVT))
23753 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23754 DAG.getUNDEF(WideVecVT),
23756 // At this point all of the data is stored at the bottom of the
23757 // register. We now need to save it to mem.
23759 // Find the largest store unit
23760 MVT StoreType = MVT::i8;
23761 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23762 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23763 MVT Tp = (MVT::SimpleValueType)tp;
23764 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23768 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23769 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23770 (64 <= NumElems * ToSz))
23771 StoreType = MVT::f64;
23773 // Bitcast the original vector into a vector of store-size units
23774 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23775 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23776 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23777 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23778 SmallVector<SDValue, 8> Chains;
23779 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23780 TLI.getPointerTy());
23781 SDValue Ptr = St->getBasePtr();
23783 // Perform one or more big stores into memory.
23784 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23785 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23786 StoreType, ShuffWide,
23787 DAG.getIntPtrConstant(i));
23788 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23789 St->getPointerInfo(), St->isVolatile(),
23790 St->isNonTemporal(), St->getAlignment());
23791 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23792 Chains.push_back(Ch);
23795 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23798 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23799 // the FP state in cases where an emms may be missing.
23800 // A preferable solution to the general problem is to figure out the right
23801 // places to insert EMMS. This qualifies as a quick hack.
23803 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23804 if (VT.getSizeInBits() != 64)
23807 const Function *F = DAG.getMachineFunction().getFunction();
23808 bool NoImplicitFloatOps = F->getAttributes().
23809 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23810 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23811 && Subtarget->hasSSE2();
23812 if ((VT.isVector() ||
23813 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23814 isa<LoadSDNode>(St->getValue()) &&
23815 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23816 St->getChain().hasOneUse() && !St->isVolatile()) {
23817 SDNode* LdVal = St->getValue().getNode();
23818 LoadSDNode *Ld = nullptr;
23819 int TokenFactorIndex = -1;
23820 SmallVector<SDValue, 8> Ops;
23821 SDNode* ChainVal = St->getChain().getNode();
23822 // Must be a store of a load. We currently handle two cases: the load
23823 // is a direct child, and it's under an intervening TokenFactor. It is
23824 // possible to dig deeper under nested TokenFactors.
23825 if (ChainVal == LdVal)
23826 Ld = cast<LoadSDNode>(St->getChain());
23827 else if (St->getValue().hasOneUse() &&
23828 ChainVal->getOpcode() == ISD::TokenFactor) {
23829 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23830 if (ChainVal->getOperand(i).getNode() == LdVal) {
23831 TokenFactorIndex = i;
23832 Ld = cast<LoadSDNode>(St->getValue());
23834 Ops.push_back(ChainVal->getOperand(i));
23838 if (!Ld || !ISD::isNormalLoad(Ld))
23841 // If this is not the MMX case, i.e. we are just turning i64 load/store
23842 // into f64 load/store, avoid the transformation if there are multiple
23843 // uses of the loaded value.
23844 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23849 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23850 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23852 if (Subtarget->is64Bit() || F64IsLegal) {
23853 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23854 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23855 Ld->getPointerInfo(), Ld->isVolatile(),
23856 Ld->isNonTemporal(), Ld->isInvariant(),
23857 Ld->getAlignment());
23858 SDValue NewChain = NewLd.getValue(1);
23859 if (TokenFactorIndex != -1) {
23860 Ops.push_back(NewChain);
23861 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23863 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23864 St->getPointerInfo(),
23865 St->isVolatile(), St->isNonTemporal(),
23866 St->getAlignment());
23869 // Otherwise, lower to two pairs of 32-bit loads / stores.
23870 SDValue LoAddr = Ld->getBasePtr();
23871 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23872 DAG.getConstant(4, MVT::i32));
23874 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23875 Ld->getPointerInfo(),
23876 Ld->isVolatile(), Ld->isNonTemporal(),
23877 Ld->isInvariant(), Ld->getAlignment());
23878 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23879 Ld->getPointerInfo().getWithOffset(4),
23880 Ld->isVolatile(), Ld->isNonTemporal(),
23882 MinAlign(Ld->getAlignment(), 4));
23884 SDValue NewChain = LoLd.getValue(1);
23885 if (TokenFactorIndex != -1) {
23886 Ops.push_back(LoLd);
23887 Ops.push_back(HiLd);
23888 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23891 LoAddr = St->getBasePtr();
23892 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23893 DAG.getConstant(4, MVT::i32));
23895 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23896 St->getPointerInfo(),
23897 St->isVolatile(), St->isNonTemporal(),
23898 St->getAlignment());
23899 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23900 St->getPointerInfo().getWithOffset(4),
23902 St->isNonTemporal(),
23903 MinAlign(St->getAlignment(), 4));
23904 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23909 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23910 /// and return the operands for the horizontal operation in LHS and RHS. A
23911 /// horizontal operation performs the binary operation on successive elements
23912 /// of its first operand, then on successive elements of its second operand,
23913 /// returning the resulting values in a vector. For example, if
23914 /// A = < float a0, float a1, float a2, float a3 >
23916 /// B = < float b0, float b1, float b2, float b3 >
23917 /// then the result of doing a horizontal operation on A and B is
23918 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23919 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23920 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23921 /// set to A, RHS to B, and the routine returns 'true'.
23922 /// Note that the binary operation should have the property that if one of the
23923 /// operands is UNDEF then the result is UNDEF.
23924 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23925 // Look for the following pattern: if
23926 // A = < float a0, float a1, float a2, float a3 >
23927 // B = < float b0, float b1, float b2, float b3 >
23929 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23930 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23931 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23932 // which is A horizontal-op B.
23934 // At least one of the operands should be a vector shuffle.
23935 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23936 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23939 MVT VT = LHS.getSimpleValueType();
23941 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23942 "Unsupported vector type for horizontal add/sub");
23944 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23945 // operate independently on 128-bit lanes.
23946 unsigned NumElts = VT.getVectorNumElements();
23947 unsigned NumLanes = VT.getSizeInBits()/128;
23948 unsigned NumLaneElts = NumElts / NumLanes;
23949 assert((NumLaneElts % 2 == 0) &&
23950 "Vector type should have an even number of elements in each lane");
23951 unsigned HalfLaneElts = NumLaneElts/2;
23953 // View LHS in the form
23954 // LHS = VECTOR_SHUFFLE A, B, LMask
23955 // If LHS is not a shuffle then pretend it is the shuffle
23956 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23957 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23960 SmallVector<int, 16> LMask(NumElts);
23961 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23962 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23963 A = LHS.getOperand(0);
23964 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23965 B = LHS.getOperand(1);
23966 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23967 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23969 if (LHS.getOpcode() != ISD::UNDEF)
23971 for (unsigned i = 0; i != NumElts; ++i)
23975 // Likewise, view RHS in the form
23976 // RHS = VECTOR_SHUFFLE C, D, RMask
23978 SmallVector<int, 16> RMask(NumElts);
23979 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23980 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23981 C = RHS.getOperand(0);
23982 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23983 D = RHS.getOperand(1);
23984 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23985 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23987 if (RHS.getOpcode() != ISD::UNDEF)
23989 for (unsigned i = 0; i != NumElts; ++i)
23993 // Check that the shuffles are both shuffling the same vectors.
23994 if (!(A == C && B == D) && !(A == D && B == C))
23997 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23998 if (!A.getNode() && !B.getNode())
24001 // If A and B occur in reverse order in RHS, then "swap" them (which means
24002 // rewriting the mask).
24004 CommuteVectorShuffleMask(RMask, NumElts);
24006 // At this point LHS and RHS are equivalent to
24007 // LHS = VECTOR_SHUFFLE A, B, LMask
24008 // RHS = VECTOR_SHUFFLE A, B, RMask
24009 // Check that the masks correspond to performing a horizontal operation.
24010 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24011 for (unsigned i = 0; i != NumLaneElts; ++i) {
24012 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24014 // Ignore any UNDEF components.
24015 if (LIdx < 0 || RIdx < 0 ||
24016 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24017 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24020 // Check that successive elements are being operated on. If not, this is
24021 // not a horizontal operation.
24022 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24023 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24024 if (!(LIdx == Index && RIdx == Index + 1) &&
24025 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24030 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24031 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24035 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24036 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24037 const X86Subtarget *Subtarget) {
24038 EVT VT = N->getValueType(0);
24039 SDValue LHS = N->getOperand(0);
24040 SDValue RHS = N->getOperand(1);
24042 // Try to synthesize horizontal adds from adds of shuffles.
24043 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24044 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24045 isHorizontalBinOp(LHS, RHS, true))
24046 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24050 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24051 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24052 const X86Subtarget *Subtarget) {
24053 EVT VT = N->getValueType(0);
24054 SDValue LHS = N->getOperand(0);
24055 SDValue RHS = N->getOperand(1);
24057 // Try to synthesize horizontal subs from subs of shuffles.
24058 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24059 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24060 isHorizontalBinOp(LHS, RHS, false))
24061 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24065 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24066 /// X86ISD::FXOR nodes.
24067 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24068 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24069 // F[X]OR(0.0, x) -> x
24070 // F[X]OR(x, 0.0) -> x
24071 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24072 if (C->getValueAPF().isPosZero())
24073 return N->getOperand(1);
24074 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24075 if (C->getValueAPF().isPosZero())
24076 return N->getOperand(0);
24080 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24081 /// X86ISD::FMAX nodes.
24082 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24083 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24085 // Only perform optimizations if UnsafeMath is used.
24086 if (!DAG.getTarget().Options.UnsafeFPMath)
24089 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24090 // into FMINC and FMAXC, which are Commutative operations.
24091 unsigned NewOp = 0;
24092 switch (N->getOpcode()) {
24093 default: llvm_unreachable("unknown opcode");
24094 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24095 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24098 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24099 N->getOperand(0), N->getOperand(1));
24102 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24103 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24104 // FAND(0.0, x) -> 0.0
24105 // FAND(x, 0.0) -> 0.0
24106 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24107 if (C->getValueAPF().isPosZero())
24108 return N->getOperand(0);
24109 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24110 if (C->getValueAPF().isPosZero())
24111 return N->getOperand(1);
24115 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24116 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24117 // FANDN(x, 0.0) -> 0.0
24118 // FANDN(0.0, x) -> x
24119 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24120 if (C->getValueAPF().isPosZero())
24121 return N->getOperand(1);
24122 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24123 if (C->getValueAPF().isPosZero())
24124 return N->getOperand(1);
24128 static SDValue PerformBTCombine(SDNode *N,
24130 TargetLowering::DAGCombinerInfo &DCI) {
24131 // BT ignores high bits in the bit index operand.
24132 SDValue Op1 = N->getOperand(1);
24133 if (Op1.hasOneUse()) {
24134 unsigned BitWidth = Op1.getValueSizeInBits();
24135 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24136 APInt KnownZero, KnownOne;
24137 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24138 !DCI.isBeforeLegalizeOps());
24139 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24140 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24141 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24142 DCI.CommitTargetLoweringOpt(TLO);
24147 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24148 SDValue Op = N->getOperand(0);
24149 if (Op.getOpcode() == ISD::BITCAST)
24150 Op = Op.getOperand(0);
24151 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24152 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24153 VT.getVectorElementType().getSizeInBits() ==
24154 OpVT.getVectorElementType().getSizeInBits()) {
24155 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24160 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24161 const X86Subtarget *Subtarget) {
24162 EVT VT = N->getValueType(0);
24163 if (!VT.isVector())
24166 SDValue N0 = N->getOperand(0);
24167 SDValue N1 = N->getOperand(1);
24168 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24171 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24172 // both SSE and AVX2 since there is no sign-extended shift right
24173 // operation on a vector with 64-bit elements.
24174 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24175 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24176 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24177 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24178 SDValue N00 = N0.getOperand(0);
24180 // EXTLOAD has a better solution on AVX2,
24181 // it may be replaced with X86ISD::VSEXT node.
24182 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24183 if (!ISD::isNormalLoad(N00.getNode()))
24186 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24187 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24189 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24195 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24196 TargetLowering::DAGCombinerInfo &DCI,
24197 const X86Subtarget *Subtarget) {
24198 if (!DCI.isBeforeLegalizeOps())
24201 if (!Subtarget->hasFp256())
24204 EVT VT = N->getValueType(0);
24205 if (VT.isVector() && VT.getSizeInBits() == 256) {
24206 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24214 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24215 const X86Subtarget* Subtarget) {
24217 EVT VT = N->getValueType(0);
24219 // Let legalize expand this if it isn't a legal type yet.
24220 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24223 EVT ScalarVT = VT.getScalarType();
24224 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24225 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24228 SDValue A = N->getOperand(0);
24229 SDValue B = N->getOperand(1);
24230 SDValue C = N->getOperand(2);
24232 bool NegA = (A.getOpcode() == ISD::FNEG);
24233 bool NegB = (B.getOpcode() == ISD::FNEG);
24234 bool NegC = (C.getOpcode() == ISD::FNEG);
24236 // Negative multiplication when NegA xor NegB
24237 bool NegMul = (NegA != NegB);
24239 A = A.getOperand(0);
24241 B = B.getOperand(0);
24243 C = C.getOperand(0);
24247 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24249 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24251 return DAG.getNode(Opcode, dl, VT, A, B, C);
24254 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24255 TargetLowering::DAGCombinerInfo &DCI,
24256 const X86Subtarget *Subtarget) {
24257 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24258 // (and (i32 x86isd::setcc_carry), 1)
24259 // This eliminates the zext. This transformation is necessary because
24260 // ISD::SETCC is always legalized to i8.
24262 SDValue N0 = N->getOperand(0);
24263 EVT VT = N->getValueType(0);
24265 if (N0.getOpcode() == ISD::AND &&
24267 N0.getOperand(0).hasOneUse()) {
24268 SDValue N00 = N0.getOperand(0);
24269 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24270 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24271 if (!C || C->getZExtValue() != 1)
24273 return DAG.getNode(ISD::AND, dl, VT,
24274 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24275 N00.getOperand(0), N00.getOperand(1)),
24276 DAG.getConstant(1, VT));
24280 if (N0.getOpcode() == ISD::TRUNCATE &&
24282 N0.getOperand(0).hasOneUse()) {
24283 SDValue N00 = N0.getOperand(0);
24284 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24285 return DAG.getNode(ISD::AND, dl, VT,
24286 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24287 N00.getOperand(0), N00.getOperand(1)),
24288 DAG.getConstant(1, VT));
24291 if (VT.is256BitVector()) {
24292 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24300 // Optimize x == -y --> x+y == 0
24301 // x != -y --> x+y != 0
24302 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24303 const X86Subtarget* Subtarget) {
24304 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24305 SDValue LHS = N->getOperand(0);
24306 SDValue RHS = N->getOperand(1);
24307 EVT VT = N->getValueType(0);
24310 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24311 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24312 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24313 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24314 LHS.getValueType(), RHS, LHS.getOperand(1));
24315 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24316 addV, DAG.getConstant(0, addV.getValueType()), CC);
24318 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24319 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24320 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24321 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24322 RHS.getValueType(), LHS, RHS.getOperand(1));
24323 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24324 addV, DAG.getConstant(0, addV.getValueType()), CC);
24327 if (VT.getScalarType() == MVT::i1) {
24328 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24329 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24330 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24331 if (!IsSEXT0 && !IsVZero0)
24333 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24334 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24335 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24337 if (!IsSEXT1 && !IsVZero1)
24340 if (IsSEXT0 && IsVZero1) {
24341 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24342 if (CC == ISD::SETEQ)
24343 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24344 return LHS.getOperand(0);
24346 if (IsSEXT1 && IsVZero0) {
24347 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24348 if (CC == ISD::SETEQ)
24349 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24350 return RHS.getOperand(0);
24357 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24358 const X86Subtarget *Subtarget) {
24360 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24361 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24362 "X86insertps is only defined for v4x32");
24364 SDValue Ld = N->getOperand(1);
24365 if (MayFoldLoad(Ld)) {
24366 // Extract the countS bits from the immediate so we can get the proper
24367 // address when narrowing the vector load to a specific element.
24368 // When the second source op is a memory address, interps doesn't use
24369 // countS and just gets an f32 from that address.
24370 unsigned DestIndex =
24371 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24372 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24376 // Create this as a scalar to vector to match the instruction pattern.
24377 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24378 // countS bits are ignored when loading from memory on insertps, which
24379 // means we don't need to explicitly set them to 0.
24380 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24381 LoadScalarToVector, N->getOperand(2));
24384 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24385 // as "sbb reg,reg", since it can be extended without zext and produces
24386 // an all-ones bit which is more useful than 0/1 in some cases.
24387 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24390 return DAG.getNode(ISD::AND, DL, VT,
24391 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24392 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24393 DAG.getConstant(1, VT));
24394 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24395 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24396 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24397 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24400 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24401 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24402 TargetLowering::DAGCombinerInfo &DCI,
24403 const X86Subtarget *Subtarget) {
24405 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24406 SDValue EFLAGS = N->getOperand(1);
24408 if (CC == X86::COND_A) {
24409 // Try to convert COND_A into COND_B in an attempt to facilitate
24410 // materializing "setb reg".
24412 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24413 // cannot take an immediate as its first operand.
24415 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24416 EFLAGS.getValueType().isInteger() &&
24417 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24418 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24419 EFLAGS.getNode()->getVTList(),
24420 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24421 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24422 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24426 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24427 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24429 if (CC == X86::COND_B)
24430 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24434 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24435 if (Flags.getNode()) {
24436 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24437 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24443 // Optimize branch condition evaluation.
24445 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24446 TargetLowering::DAGCombinerInfo &DCI,
24447 const X86Subtarget *Subtarget) {
24449 SDValue Chain = N->getOperand(0);
24450 SDValue Dest = N->getOperand(1);
24451 SDValue EFLAGS = N->getOperand(3);
24452 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24456 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24457 if (Flags.getNode()) {
24458 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24459 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24466 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24467 SelectionDAG &DAG) {
24468 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24469 // optimize away operation when it's from a constant.
24471 // The general transformation is:
24472 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24473 // AND(VECTOR_CMP(x,y), constant2)
24474 // constant2 = UNARYOP(constant)
24476 // Early exit if this isn't a vector operation, the operand of the
24477 // unary operation isn't a bitwise AND, or if the sizes of the operations
24478 // aren't the same.
24479 EVT VT = N->getValueType(0);
24480 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24481 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24482 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24485 // Now check that the other operand of the AND is a constant. We could
24486 // make the transformation for non-constant splats as well, but it's unclear
24487 // that would be a benefit as it would not eliminate any operations, just
24488 // perform one more step in scalar code before moving to the vector unit.
24489 if (BuildVectorSDNode *BV =
24490 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24491 // Bail out if the vector isn't a constant.
24492 if (!BV->isConstant())
24495 // Everything checks out. Build up the new and improved node.
24497 EVT IntVT = BV->getValueType(0);
24498 // Create a new constant of the appropriate type for the transformed
24500 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24501 // The AND node needs bitcasts to/from an integer vector type around it.
24502 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24503 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24504 N->getOperand(0)->getOperand(0), MaskConst);
24505 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24512 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24513 const X86TargetLowering *XTLI) {
24514 // First try to optimize away the conversion entirely when it's
24515 // conditionally from a constant. Vectors only.
24516 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24517 if (Res != SDValue())
24520 // Now move on to more general possibilities.
24521 SDValue Op0 = N->getOperand(0);
24522 EVT InVT = Op0->getValueType(0);
24524 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24525 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24527 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24528 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24529 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24532 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24533 // a 32-bit target where SSE doesn't support i64->FP operations.
24534 if (Op0.getOpcode() == ISD::LOAD) {
24535 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24536 EVT VT = Ld->getValueType(0);
24537 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24538 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24539 !XTLI->getSubtarget()->is64Bit() &&
24541 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24542 Ld->getChain(), Op0, DAG);
24543 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24550 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24551 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24552 X86TargetLowering::DAGCombinerInfo &DCI) {
24553 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24554 // the result is either zero or one (depending on the input carry bit).
24555 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24556 if (X86::isZeroNode(N->getOperand(0)) &&
24557 X86::isZeroNode(N->getOperand(1)) &&
24558 // We don't have a good way to replace an EFLAGS use, so only do this when
24560 SDValue(N, 1).use_empty()) {
24562 EVT VT = N->getValueType(0);
24563 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24564 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24565 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24566 DAG.getConstant(X86::COND_B,MVT::i8),
24568 DAG.getConstant(1, VT));
24569 return DCI.CombineTo(N, Res1, CarryOut);
24575 // fold (add Y, (sete X, 0)) -> adc 0, Y
24576 // (add Y, (setne X, 0)) -> sbb -1, Y
24577 // (sub (sete X, 0), Y) -> sbb 0, Y
24578 // (sub (setne X, 0), Y) -> adc -1, Y
24579 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24582 // Look through ZExts.
24583 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24584 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24587 SDValue SetCC = Ext.getOperand(0);
24588 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24591 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24592 if (CC != X86::COND_E && CC != X86::COND_NE)
24595 SDValue Cmp = SetCC.getOperand(1);
24596 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24597 !X86::isZeroNode(Cmp.getOperand(1)) ||
24598 !Cmp.getOperand(0).getValueType().isInteger())
24601 SDValue CmpOp0 = Cmp.getOperand(0);
24602 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24603 DAG.getConstant(1, CmpOp0.getValueType()));
24605 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24606 if (CC == X86::COND_NE)
24607 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24608 DL, OtherVal.getValueType(), OtherVal,
24609 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24610 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24611 DL, OtherVal.getValueType(), OtherVal,
24612 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24615 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24616 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24617 const X86Subtarget *Subtarget) {
24618 EVT VT = N->getValueType(0);
24619 SDValue Op0 = N->getOperand(0);
24620 SDValue Op1 = N->getOperand(1);
24622 // Try to synthesize horizontal adds from adds of shuffles.
24623 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24624 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24625 isHorizontalBinOp(Op0, Op1, true))
24626 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24628 return OptimizeConditionalInDecrement(N, DAG);
24631 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24632 const X86Subtarget *Subtarget) {
24633 SDValue Op0 = N->getOperand(0);
24634 SDValue Op1 = N->getOperand(1);
24636 // X86 can't encode an immediate LHS of a sub. See if we can push the
24637 // negation into a preceding instruction.
24638 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24639 // If the RHS of the sub is a XOR with one use and a constant, invert the
24640 // immediate. Then add one to the LHS of the sub so we can turn
24641 // X-Y -> X+~Y+1, saving one register.
24642 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24643 isa<ConstantSDNode>(Op1.getOperand(1))) {
24644 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24645 EVT VT = Op0.getValueType();
24646 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24648 DAG.getConstant(~XorC, VT));
24649 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24650 DAG.getConstant(C->getAPIntValue()+1, VT));
24654 // Try to synthesize horizontal adds from adds of shuffles.
24655 EVT VT = N->getValueType(0);
24656 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24657 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24658 isHorizontalBinOp(Op0, Op1, true))
24659 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24661 return OptimizeConditionalInDecrement(N, DAG);
24664 /// performVZEXTCombine - Performs build vector combines
24665 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24666 TargetLowering::DAGCombinerInfo &DCI,
24667 const X86Subtarget *Subtarget) {
24669 MVT VT = N->getSimpleValueType(0);
24670 SDValue Op = N->getOperand(0);
24671 MVT OpVT = Op.getSimpleValueType();
24672 MVT OpEltVT = OpVT.getVectorElementType();
24673 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24675 // (vzext (bitcast (vzext (x)) -> (vzext x)
24677 while (V.getOpcode() == ISD::BITCAST)
24678 V = V.getOperand(0);
24680 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24681 MVT InnerVT = V.getSimpleValueType();
24682 MVT InnerEltVT = InnerVT.getVectorElementType();
24684 // If the element sizes match exactly, we can just do one larger vzext. This
24685 // is always an exact type match as vzext operates on integer types.
24686 if (OpEltVT == InnerEltVT) {
24687 assert(OpVT == InnerVT && "Types must match for vzext!");
24688 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24691 // The only other way we can combine them is if only a single element of the
24692 // inner vzext is used in the input to the outer vzext.
24693 if (InnerEltVT.getSizeInBits() < InputBits)
24696 // In this case, the inner vzext is completely dead because we're going to
24697 // only look at bits inside of the low element. Just do the outer vzext on
24698 // a bitcast of the input to the inner.
24699 return DAG.getNode(X86ISD::VZEXT, DL, VT,
24700 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
24703 // Check if we can bypass extracting and re-inserting an element of an input
24704 // vector. Essentialy:
24705 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24706 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24707 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24708 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24709 SDValue ExtractedV = V.getOperand(0);
24710 SDValue OrigV = ExtractedV.getOperand(0);
24711 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24712 if (ExtractIdx->getZExtValue() == 0) {
24713 MVT OrigVT = OrigV.getSimpleValueType();
24714 // Extract a subvector if necessary...
24715 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24716 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24717 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24718 OrigVT.getVectorNumElements() / Ratio);
24719 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24720 DAG.getIntPtrConstant(0));
24722 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
24723 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24730 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24731 DAGCombinerInfo &DCI) const {
24732 SelectionDAG &DAG = DCI.DAG;
24733 switch (N->getOpcode()) {
24735 case ISD::EXTRACT_VECTOR_ELT:
24736 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24738 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24739 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24740 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24741 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24742 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24743 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24746 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24747 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24748 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24749 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24750 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24751 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24752 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24753 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24754 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24756 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24758 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24759 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24760 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24761 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24762 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24763 case ISD::ANY_EXTEND:
24764 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24765 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24766 case ISD::SIGN_EXTEND_INREG:
24767 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24768 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24769 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24770 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24771 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24772 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24773 case X86ISD::SHUFP: // Handle all target specific shuffles
24774 case X86ISD::PALIGNR:
24775 case X86ISD::UNPCKH:
24776 case X86ISD::UNPCKL:
24777 case X86ISD::MOVHLPS:
24778 case X86ISD::MOVLHPS:
24779 case X86ISD::PSHUFB:
24780 case X86ISD::PSHUFD:
24781 case X86ISD::PSHUFHW:
24782 case X86ISD::PSHUFLW:
24783 case X86ISD::MOVSS:
24784 case X86ISD::MOVSD:
24785 case X86ISD::VPERMILPI:
24786 case X86ISD::VPERM2X128:
24787 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24788 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24789 case ISD::INTRINSIC_WO_CHAIN:
24790 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24791 case X86ISD::INSERTPS:
24792 return PerformINSERTPSCombine(N, DAG, Subtarget);
24793 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24799 /// isTypeDesirableForOp - Return true if the target has native support for
24800 /// the specified value type and it is 'desirable' to use the type for the
24801 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24802 /// instruction encodings are longer and some i16 instructions are slow.
24803 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24804 if (!isTypeLegal(VT))
24806 if (VT != MVT::i16)
24813 case ISD::SIGN_EXTEND:
24814 case ISD::ZERO_EXTEND:
24815 case ISD::ANY_EXTEND:
24828 /// IsDesirableToPromoteOp - This method query the target whether it is
24829 /// beneficial for dag combiner to promote the specified node. If true, it
24830 /// should return the desired promotion type by reference.
24831 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24832 EVT VT = Op.getValueType();
24833 if (VT != MVT::i16)
24836 bool Promote = false;
24837 bool Commute = false;
24838 switch (Op.getOpcode()) {
24841 LoadSDNode *LD = cast<LoadSDNode>(Op);
24842 // If the non-extending load has a single use and it's not live out, then it
24843 // might be folded.
24844 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24845 Op.hasOneUse()*/) {
24846 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24847 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24848 // The only case where we'd want to promote LOAD (rather then it being
24849 // promoted as an operand is when it's only use is liveout.
24850 if (UI->getOpcode() != ISD::CopyToReg)
24857 case ISD::SIGN_EXTEND:
24858 case ISD::ZERO_EXTEND:
24859 case ISD::ANY_EXTEND:
24864 SDValue N0 = Op.getOperand(0);
24865 // Look out for (store (shl (load), x)).
24866 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24879 SDValue N0 = Op.getOperand(0);
24880 SDValue N1 = Op.getOperand(1);
24881 if (!Commute && MayFoldLoad(N1))
24883 // Avoid disabling potential load folding opportunities.
24884 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24886 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24896 //===----------------------------------------------------------------------===//
24897 // X86 Inline Assembly Support
24898 //===----------------------------------------------------------------------===//
24901 // Helper to match a string separated by whitespace.
24902 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24903 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24905 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24906 StringRef piece(*args[i]);
24907 if (!s.startswith(piece)) // Check if the piece matches.
24910 s = s.substr(piece.size());
24911 StringRef::size_type pos = s.find_first_not_of(" \t");
24912 if (pos == 0) // We matched a prefix.
24920 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24923 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24925 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24926 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24927 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24928 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24930 if (AsmPieces.size() == 3)
24932 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24939 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24940 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24942 std::string AsmStr = IA->getAsmString();
24944 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24945 if (!Ty || Ty->getBitWidth() % 16 != 0)
24948 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24949 SmallVector<StringRef, 4> AsmPieces;
24950 SplitString(AsmStr, AsmPieces, ";\n");
24952 switch (AsmPieces.size()) {
24953 default: return false;
24955 // FIXME: this should verify that we are targeting a 486 or better. If not,
24956 // we will turn this bswap into something that will be lowered to logical
24957 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24958 // lower so don't worry about this.
24960 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24961 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24962 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24963 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24964 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24965 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24966 // No need to check constraints, nothing other than the equivalent of
24967 // "=r,0" would be valid here.
24968 return IntrinsicLowering::LowerToByteSwap(CI);
24971 // rorw $$8, ${0:w} --> llvm.bswap.i16
24972 if (CI->getType()->isIntegerTy(16) &&
24973 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24974 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24975 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24977 const std::string &ConstraintsStr = IA->getConstraintString();
24978 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24979 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24980 if (clobbersFlagRegisters(AsmPieces))
24981 return IntrinsicLowering::LowerToByteSwap(CI);
24985 if (CI->getType()->isIntegerTy(32) &&
24986 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24987 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24988 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24989 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24991 const std::string &ConstraintsStr = IA->getConstraintString();
24992 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24993 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24994 if (clobbersFlagRegisters(AsmPieces))
24995 return IntrinsicLowering::LowerToByteSwap(CI);
24998 if (CI->getType()->isIntegerTy(64)) {
24999 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25000 if (Constraints.size() >= 2 &&
25001 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25002 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25003 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25004 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25005 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25006 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25007 return IntrinsicLowering::LowerToByteSwap(CI);
25015 /// getConstraintType - Given a constraint letter, return the type of
25016 /// constraint it is for this target.
25017 X86TargetLowering::ConstraintType
25018 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25019 if (Constraint.size() == 1) {
25020 switch (Constraint[0]) {
25031 return C_RegisterClass;
25055 return TargetLowering::getConstraintType(Constraint);
25058 /// Examine constraint type and operand type and determine a weight value.
25059 /// This object must already have been set up with the operand type
25060 /// and the current alternative constraint selected.
25061 TargetLowering::ConstraintWeight
25062 X86TargetLowering::getSingleConstraintMatchWeight(
25063 AsmOperandInfo &info, const char *constraint) const {
25064 ConstraintWeight weight = CW_Invalid;
25065 Value *CallOperandVal = info.CallOperandVal;
25066 // If we don't have a value, we can't do a match,
25067 // but allow it at the lowest weight.
25068 if (!CallOperandVal)
25070 Type *type = CallOperandVal->getType();
25071 // Look at the constraint type.
25072 switch (*constraint) {
25074 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25085 if (CallOperandVal->getType()->isIntegerTy())
25086 weight = CW_SpecificReg;
25091 if (type->isFloatingPointTy())
25092 weight = CW_SpecificReg;
25095 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25096 weight = CW_SpecificReg;
25100 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25101 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25102 weight = CW_Register;
25105 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25106 if (C->getZExtValue() <= 31)
25107 weight = CW_Constant;
25111 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25112 if (C->getZExtValue() <= 63)
25113 weight = CW_Constant;
25117 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25118 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25119 weight = CW_Constant;
25123 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25124 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25125 weight = CW_Constant;
25129 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25130 if (C->getZExtValue() <= 3)
25131 weight = CW_Constant;
25135 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25136 if (C->getZExtValue() <= 0xff)
25137 weight = CW_Constant;
25142 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25143 weight = CW_Constant;
25147 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25148 if ((C->getSExtValue() >= -0x80000000LL) &&
25149 (C->getSExtValue() <= 0x7fffffffLL))
25150 weight = CW_Constant;
25154 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25155 if (C->getZExtValue() <= 0xffffffff)
25156 weight = CW_Constant;
25163 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25164 /// with another that has more specific requirements based on the type of the
25165 /// corresponding operand.
25166 const char *X86TargetLowering::
25167 LowerXConstraint(EVT ConstraintVT) const {
25168 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25169 // 'f' like normal targets.
25170 if (ConstraintVT.isFloatingPoint()) {
25171 if (Subtarget->hasSSE2())
25173 if (Subtarget->hasSSE1())
25177 return TargetLowering::LowerXConstraint(ConstraintVT);
25180 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25181 /// vector. If it is invalid, don't add anything to Ops.
25182 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25183 std::string &Constraint,
25184 std::vector<SDValue>&Ops,
25185 SelectionDAG &DAG) const {
25188 // Only support length 1 constraints for now.
25189 if (Constraint.length() > 1) return;
25191 char ConstraintLetter = Constraint[0];
25192 switch (ConstraintLetter) {
25195 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25196 if (C->getZExtValue() <= 31) {
25197 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25203 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25204 if (C->getZExtValue() <= 63) {
25205 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25212 if (isInt<8>(C->getSExtValue())) {
25213 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25219 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25220 if (C->getZExtValue() <= 255) {
25221 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25227 // 32-bit signed value
25228 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25229 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25230 C->getSExtValue())) {
25231 // Widen to 64 bits here to get it sign extended.
25232 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25235 // FIXME gcc accepts some relocatable values here too, but only in certain
25236 // memory models; it's complicated.
25241 // 32-bit unsigned value
25242 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25243 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25244 C->getZExtValue())) {
25245 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25249 // FIXME gcc accepts some relocatable values here too, but only in certain
25250 // memory models; it's complicated.
25254 // Literal immediates are always ok.
25255 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25256 // Widen to 64 bits here to get it sign extended.
25257 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25261 // In any sort of PIC mode addresses need to be computed at runtime by
25262 // adding in a register or some sort of table lookup. These can't
25263 // be used as immediates.
25264 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25267 // If we are in non-pic codegen mode, we allow the address of a global (with
25268 // an optional displacement) to be used with 'i'.
25269 GlobalAddressSDNode *GA = nullptr;
25270 int64_t Offset = 0;
25272 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25274 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25275 Offset += GA->getOffset();
25277 } else if (Op.getOpcode() == ISD::ADD) {
25278 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25279 Offset += C->getZExtValue();
25280 Op = Op.getOperand(0);
25283 } else if (Op.getOpcode() == ISD::SUB) {
25284 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25285 Offset += -C->getZExtValue();
25286 Op = Op.getOperand(0);
25291 // Otherwise, this isn't something we can handle, reject it.
25295 const GlobalValue *GV = GA->getGlobal();
25296 // If we require an extra load to get this address, as in PIC mode, we
25297 // can't accept it.
25298 if (isGlobalStubReference(
25299 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25302 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25303 GA->getValueType(0), Offset);
25308 if (Result.getNode()) {
25309 Ops.push_back(Result);
25312 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25315 std::pair<unsigned, const TargetRegisterClass*>
25316 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25318 // First, see if this is a constraint that directly corresponds to an LLVM
25320 if (Constraint.size() == 1) {
25321 // GCC Constraint Letters
25322 switch (Constraint[0]) {
25324 // TODO: Slight differences here in allocation order and leaving
25325 // RIP in the class. Do they matter any more here than they do
25326 // in the normal allocation?
25327 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25328 if (Subtarget->is64Bit()) {
25329 if (VT == MVT::i32 || VT == MVT::f32)
25330 return std::make_pair(0U, &X86::GR32RegClass);
25331 if (VT == MVT::i16)
25332 return std::make_pair(0U, &X86::GR16RegClass);
25333 if (VT == MVT::i8 || VT == MVT::i1)
25334 return std::make_pair(0U, &X86::GR8RegClass);
25335 if (VT == MVT::i64 || VT == MVT::f64)
25336 return std::make_pair(0U, &X86::GR64RegClass);
25339 // 32-bit fallthrough
25340 case 'Q': // Q_REGS
25341 if (VT == MVT::i32 || VT == MVT::f32)
25342 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25343 if (VT == MVT::i16)
25344 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25345 if (VT == MVT::i8 || VT == MVT::i1)
25346 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25347 if (VT == MVT::i64)
25348 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25350 case 'r': // GENERAL_REGS
25351 case 'l': // INDEX_REGS
25352 if (VT == MVT::i8 || VT == MVT::i1)
25353 return std::make_pair(0U, &X86::GR8RegClass);
25354 if (VT == MVT::i16)
25355 return std::make_pair(0U, &X86::GR16RegClass);
25356 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25357 return std::make_pair(0U, &X86::GR32RegClass);
25358 return std::make_pair(0U, &X86::GR64RegClass);
25359 case 'R': // LEGACY_REGS
25360 if (VT == MVT::i8 || VT == MVT::i1)
25361 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25362 if (VT == MVT::i16)
25363 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25364 if (VT == MVT::i32 || !Subtarget->is64Bit())
25365 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25366 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25367 case 'f': // FP Stack registers.
25368 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25369 // value to the correct fpstack register class.
25370 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25371 return std::make_pair(0U, &X86::RFP32RegClass);
25372 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25373 return std::make_pair(0U, &X86::RFP64RegClass);
25374 return std::make_pair(0U, &X86::RFP80RegClass);
25375 case 'y': // MMX_REGS if MMX allowed.
25376 if (!Subtarget->hasMMX()) break;
25377 return std::make_pair(0U, &X86::VR64RegClass);
25378 case 'Y': // SSE_REGS if SSE2 allowed
25379 if (!Subtarget->hasSSE2()) break;
25381 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25382 if (!Subtarget->hasSSE1()) break;
25384 switch (VT.SimpleTy) {
25386 // Scalar SSE types.
25389 return std::make_pair(0U, &X86::FR32RegClass);
25392 return std::make_pair(0U, &X86::FR64RegClass);
25400 return std::make_pair(0U, &X86::VR128RegClass);
25408 return std::make_pair(0U, &X86::VR256RegClass);
25413 return std::make_pair(0U, &X86::VR512RegClass);
25419 // Use the default implementation in TargetLowering to convert the register
25420 // constraint into a member of a register class.
25421 std::pair<unsigned, const TargetRegisterClass*> Res;
25422 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25424 // Not found as a standard register?
25426 // Map st(0) -> st(7) -> ST0
25427 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25428 tolower(Constraint[1]) == 's' &&
25429 tolower(Constraint[2]) == 't' &&
25430 Constraint[3] == '(' &&
25431 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25432 Constraint[5] == ')' &&
25433 Constraint[6] == '}') {
25435 Res.first = X86::FP0+Constraint[4]-'0';
25436 Res.second = &X86::RFP80RegClass;
25440 // GCC allows "st(0)" to be called just plain "st".
25441 if (StringRef("{st}").equals_lower(Constraint)) {
25442 Res.first = X86::FP0;
25443 Res.second = &X86::RFP80RegClass;
25448 if (StringRef("{flags}").equals_lower(Constraint)) {
25449 Res.first = X86::EFLAGS;
25450 Res.second = &X86::CCRRegClass;
25454 // 'A' means EAX + EDX.
25455 if (Constraint == "A") {
25456 Res.first = X86::EAX;
25457 Res.second = &X86::GR32_ADRegClass;
25463 // Otherwise, check to see if this is a register class of the wrong value
25464 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25465 // turn into {ax},{dx}.
25466 if (Res.second->hasType(VT))
25467 return Res; // Correct type already, nothing to do.
25469 // All of the single-register GCC register classes map their values onto
25470 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25471 // really want an 8-bit or 32-bit register, map to the appropriate register
25472 // class and return the appropriate register.
25473 if (Res.second == &X86::GR16RegClass) {
25474 if (VT == MVT::i8 || VT == MVT::i1) {
25475 unsigned DestReg = 0;
25476 switch (Res.first) {
25478 case X86::AX: DestReg = X86::AL; break;
25479 case X86::DX: DestReg = X86::DL; break;
25480 case X86::CX: DestReg = X86::CL; break;
25481 case X86::BX: DestReg = X86::BL; break;
25484 Res.first = DestReg;
25485 Res.second = &X86::GR8RegClass;
25487 } else if (VT == MVT::i32 || VT == MVT::f32) {
25488 unsigned DestReg = 0;
25489 switch (Res.first) {
25491 case X86::AX: DestReg = X86::EAX; break;
25492 case X86::DX: DestReg = X86::EDX; break;
25493 case X86::CX: DestReg = X86::ECX; break;
25494 case X86::BX: DestReg = X86::EBX; break;
25495 case X86::SI: DestReg = X86::ESI; break;
25496 case X86::DI: DestReg = X86::EDI; break;
25497 case X86::BP: DestReg = X86::EBP; break;
25498 case X86::SP: DestReg = X86::ESP; break;
25501 Res.first = DestReg;
25502 Res.second = &X86::GR32RegClass;
25504 } else if (VT == MVT::i64 || VT == MVT::f64) {
25505 unsigned DestReg = 0;
25506 switch (Res.first) {
25508 case X86::AX: DestReg = X86::RAX; break;
25509 case X86::DX: DestReg = X86::RDX; break;
25510 case X86::CX: DestReg = X86::RCX; break;
25511 case X86::BX: DestReg = X86::RBX; break;
25512 case X86::SI: DestReg = X86::RSI; break;
25513 case X86::DI: DestReg = X86::RDI; break;
25514 case X86::BP: DestReg = X86::RBP; break;
25515 case X86::SP: DestReg = X86::RSP; break;
25518 Res.first = DestReg;
25519 Res.second = &X86::GR64RegClass;
25522 } else if (Res.second == &X86::FR32RegClass ||
25523 Res.second == &X86::FR64RegClass ||
25524 Res.second == &X86::VR128RegClass ||
25525 Res.second == &X86::VR256RegClass ||
25526 Res.second == &X86::FR32XRegClass ||
25527 Res.second == &X86::FR64XRegClass ||
25528 Res.second == &X86::VR128XRegClass ||
25529 Res.second == &X86::VR256XRegClass ||
25530 Res.second == &X86::VR512RegClass) {
25531 // Handle references to XMM physical registers that got mapped into the
25532 // wrong class. This can happen with constraints like {xmm0} where the
25533 // target independent register mapper will just pick the first match it can
25534 // find, ignoring the required type.
25536 if (VT == MVT::f32 || VT == MVT::i32)
25537 Res.second = &X86::FR32RegClass;
25538 else if (VT == MVT::f64 || VT == MVT::i64)
25539 Res.second = &X86::FR64RegClass;
25540 else if (X86::VR128RegClass.hasType(VT))
25541 Res.second = &X86::VR128RegClass;
25542 else if (X86::VR256RegClass.hasType(VT))
25543 Res.second = &X86::VR256RegClass;
25544 else if (X86::VR512RegClass.hasType(VT))
25545 Res.second = &X86::VR512RegClass;
25551 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25553 // Scaling factors are not free at all.
25554 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25555 // will take 2 allocations in the out of order engine instead of 1
25556 // for plain addressing mode, i.e. inst (reg1).
25558 // vaddps (%rsi,%drx), %ymm0, %ymm1
25559 // Requires two allocations (one for the load, one for the computation)
25561 // vaddps (%rsi), %ymm0, %ymm1
25562 // Requires just 1 allocation, i.e., freeing allocations for other operations
25563 // and having less micro operations to execute.
25565 // For some X86 architectures, this is even worse because for instance for
25566 // stores, the complex addressing mode forces the instruction to use the
25567 // "load" ports instead of the dedicated "store" port.
25568 // E.g., on Haswell:
25569 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25570 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25571 if (isLegalAddressingMode(AM, Ty))
25572 // Scale represents reg2 * scale, thus account for 1
25573 // as soon as we use a second register.
25574 return AM.Scale != 0;
25578 bool X86TargetLowering::isTargetFTOL() const {
25579 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();