1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::PSHUFB:
3543 case X86ISD::PSHUFD:
3544 case X86ISD::PSHUFHW:
3545 case X86ISD::PSHUFLW:
3547 case X86ISD::PALIGNR:
3548 case X86ISD::MOVLHPS:
3549 case X86ISD::MOVLHPD:
3550 case X86ISD::MOVHLPS:
3551 case X86ISD::MOVLPS:
3552 case X86ISD::MOVLPD:
3553 case X86ISD::MOVSHDUP:
3554 case X86ISD::MOVSLDUP:
3555 case X86ISD::MOVDDUP:
3558 case X86ISD::UNPCKL:
3559 case X86ISD::UNPCKH:
3560 case X86ISD::VPERMILP:
3561 case X86ISD::VPERM2X128:
3562 case X86ISD::VPERMI:
3567 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3568 SDValue V1, SelectionDAG &DAG) {
3570 default: llvm_unreachable("Unknown x86 shuffle node");
3571 case X86ISD::MOVSHDUP:
3572 case X86ISD::MOVSLDUP:
3573 case X86ISD::MOVDDUP:
3574 return DAG.getNode(Opc, dl, VT, V1);
3578 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3579 SDValue V1, unsigned TargetMask,
3580 SelectionDAG &DAG) {
3582 default: llvm_unreachable("Unknown x86 shuffle node");
3583 case X86ISD::PSHUFD:
3584 case X86ISD::PSHUFHW:
3585 case X86ISD::PSHUFLW:
3586 case X86ISD::VPERMILP:
3587 case X86ISD::VPERMI:
3588 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3592 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3593 SDValue V1, SDValue V2, unsigned TargetMask,
3594 SelectionDAG &DAG) {
3596 default: llvm_unreachable("Unknown x86 shuffle node");
3597 case X86ISD::PALIGNR:
3598 case X86ISD::VALIGN:
3600 case X86ISD::VPERM2X128:
3601 return DAG.getNode(Opc, dl, VT, V1, V2,
3602 DAG.getConstant(TargetMask, MVT::i8));
3606 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3607 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3609 default: llvm_unreachable("Unknown x86 shuffle node");
3610 case X86ISD::MOVLHPS:
3611 case X86ISD::MOVLHPD:
3612 case X86ISD::MOVHLPS:
3613 case X86ISD::MOVLPS:
3614 case X86ISD::MOVLPD:
3617 case X86ISD::UNPCKL:
3618 case X86ISD::UNPCKH:
3619 return DAG.getNode(Opc, dl, VT, V1, V2);
3623 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3624 MachineFunction &MF = DAG.getMachineFunction();
3625 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3626 DAG.getSubtarget().getRegisterInfo());
3627 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3628 int ReturnAddrIndex = FuncInfo->getRAIndex();
3630 if (ReturnAddrIndex == 0) {
3631 // Set up a frame object for the return address.
3632 unsigned SlotSize = RegInfo->getSlotSize();
3633 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3636 FuncInfo->setRAIndex(ReturnAddrIndex);
3639 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3642 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3643 bool hasSymbolicDisplacement) {
3644 // Offset should fit into 32 bit immediate field.
3645 if (!isInt<32>(Offset))
3648 // If we don't have a symbolic displacement - we don't have any extra
3650 if (!hasSymbolicDisplacement)
3653 // FIXME: Some tweaks might be needed for medium code model.
3654 if (M != CodeModel::Small && M != CodeModel::Kernel)
3657 // For small code model we assume that latest object is 16MB before end of 31
3658 // bits boundary. We may also accept pretty large negative constants knowing
3659 // that all objects are in the positive half of address space.
3660 if (M == CodeModel::Small && Offset < 16*1024*1024)
3663 // For kernel code model we know that all object resist in the negative half
3664 // of 32bits address space. We may not accept negative offsets, since they may
3665 // be just off and we may accept pretty large positive ones.
3666 if (M == CodeModel::Kernel && Offset > 0)
3672 /// isCalleePop - Determines whether the callee is required to pop its
3673 /// own arguments. Callee pop is necessary to support tail calls.
3674 bool X86::isCalleePop(CallingConv::ID CallingConv,
3675 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3676 switch (CallingConv) {
3679 case CallingConv::X86_StdCall:
3680 case CallingConv::X86_FastCall:
3681 case CallingConv::X86_ThisCall:
3683 case CallingConv::Fast:
3684 case CallingConv::GHC:
3685 case CallingConv::HiPE:
3692 /// \brief Return true if the condition is an unsigned comparison operation.
3693 static bool isX86CCUnsigned(unsigned X86CC) {
3695 default: llvm_unreachable("Invalid integer condition!");
3696 case X86::COND_E: return true;
3697 case X86::COND_G: return false;
3698 case X86::COND_GE: return false;
3699 case X86::COND_L: return false;
3700 case X86::COND_LE: return false;
3701 case X86::COND_NE: return true;
3702 case X86::COND_B: return true;
3703 case X86::COND_A: return true;
3704 case X86::COND_BE: return true;
3705 case X86::COND_AE: return true;
3707 llvm_unreachable("covered switch fell through?!");
3710 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3711 /// specific condition code, returning the condition code and the LHS/RHS of the
3712 /// comparison to make.
3713 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3714 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3716 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3717 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3718 // X > -1 -> X == 0, jump !sign.
3719 RHS = DAG.getConstant(0, RHS.getValueType());
3720 return X86::COND_NS;
3722 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3723 // X < 0 -> X == 0, jump on sign.
3726 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3728 RHS = DAG.getConstant(0, RHS.getValueType());
3729 return X86::COND_LE;
3733 switch (SetCCOpcode) {
3734 default: llvm_unreachable("Invalid integer condition!");
3735 case ISD::SETEQ: return X86::COND_E;
3736 case ISD::SETGT: return X86::COND_G;
3737 case ISD::SETGE: return X86::COND_GE;
3738 case ISD::SETLT: return X86::COND_L;
3739 case ISD::SETLE: return X86::COND_LE;
3740 case ISD::SETNE: return X86::COND_NE;
3741 case ISD::SETULT: return X86::COND_B;
3742 case ISD::SETUGT: return X86::COND_A;
3743 case ISD::SETULE: return X86::COND_BE;
3744 case ISD::SETUGE: return X86::COND_AE;
3748 // First determine if it is required or is profitable to flip the operands.
3750 // If LHS is a foldable load, but RHS is not, flip the condition.
3751 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3752 !ISD::isNON_EXTLoad(RHS.getNode())) {
3753 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3754 std::swap(LHS, RHS);
3757 switch (SetCCOpcode) {
3763 std::swap(LHS, RHS);
3767 // On a floating point condition, the flags are set as follows:
3769 // 0 | 0 | 0 | X > Y
3770 // 0 | 0 | 1 | X < Y
3771 // 1 | 0 | 0 | X == Y
3772 // 1 | 1 | 1 | unordered
3773 switch (SetCCOpcode) {
3774 default: llvm_unreachable("Condcode should be pre-legalized away");
3776 case ISD::SETEQ: return X86::COND_E;
3777 case ISD::SETOLT: // flipped
3779 case ISD::SETGT: return X86::COND_A;
3780 case ISD::SETOLE: // flipped
3782 case ISD::SETGE: return X86::COND_AE;
3783 case ISD::SETUGT: // flipped
3785 case ISD::SETLT: return X86::COND_B;
3786 case ISD::SETUGE: // flipped
3788 case ISD::SETLE: return X86::COND_BE;
3790 case ISD::SETNE: return X86::COND_NE;
3791 case ISD::SETUO: return X86::COND_P;
3792 case ISD::SETO: return X86::COND_NP;
3794 case ISD::SETUNE: return X86::COND_INVALID;
3798 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3799 /// code. Current x86 isa includes the following FP cmov instructions:
3800 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3801 static bool hasFPCMov(unsigned X86CC) {
3817 /// isFPImmLegal - Returns true if the target can instruction select the
3818 /// specified FP immediate natively. If false, the legalizer will
3819 /// materialize the FP immediate as a load from a constant pool.
3820 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3821 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3822 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3828 /// \brief Returns true if it is beneficial to convert a load of a constant
3829 /// to just the constant itself.
3830 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3832 assert(Ty->isIntegerTy());
3834 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3835 if (BitSize == 0 || BitSize > 64)
3840 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3841 /// the specified range (L, H].
3842 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3843 return (Val < 0) || (Val >= Low && Val < Hi);
3846 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3847 /// specified value.
3848 static bool isUndefOrEqual(int Val, int CmpVal) {
3849 return (Val < 0 || Val == CmpVal);
3852 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3853 /// from position Pos and ending in Pos+Size, falls within the specified
3854 /// sequential range (L, L+Pos]. or is undef.
3855 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3856 unsigned Pos, unsigned Size, int Low) {
3857 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3858 if (!isUndefOrEqual(Mask[i], Low))
3863 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3864 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3865 /// the second operand.
3866 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3867 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3868 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3869 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3870 return (Mask[0] < 2 && Mask[1] < 2);
3874 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3875 /// is suitable for input to PSHUFHW.
3876 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3877 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3880 // Lower quadword copied in order or undef.
3881 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3884 // Upper quadword shuffled.
3885 for (unsigned i = 4; i != 8; ++i)
3886 if (!isUndefOrInRange(Mask[i], 4, 8))
3889 if (VT == MVT::v16i16) {
3890 // Lower quadword copied in order or undef.
3891 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3894 // Upper quadword shuffled.
3895 for (unsigned i = 12; i != 16; ++i)
3896 if (!isUndefOrInRange(Mask[i], 12, 16))
3903 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3904 /// is suitable for input to PSHUFLW.
3905 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3906 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3909 // Upper quadword copied in order.
3910 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3913 // Lower quadword shuffled.
3914 for (unsigned i = 0; i != 4; ++i)
3915 if (!isUndefOrInRange(Mask[i], 0, 4))
3918 if (VT == MVT::v16i16) {
3919 // Upper quadword copied in order.
3920 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3923 // Lower quadword shuffled.
3924 for (unsigned i = 8; i != 12; ++i)
3925 if (!isUndefOrInRange(Mask[i], 8, 12))
3932 /// \brief Return true if the mask specifies a shuffle of elements that is
3933 /// suitable for input to intralane (palignr) or interlane (valign) vector
3935 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3936 unsigned NumElts = VT.getVectorNumElements();
3937 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3938 unsigned NumLaneElts = NumElts/NumLanes;
3940 // Do not handle 64-bit element shuffles with palignr.
3941 if (NumLaneElts == 2)
3944 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3946 for (i = 0; i != NumLaneElts; ++i) {
3951 // Lane is all undef, go to next lane
3952 if (i == NumLaneElts)
3955 int Start = Mask[i+l];
3957 // Make sure its in this lane in one of the sources
3958 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3959 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3962 // If not lane 0, then we must match lane 0
3963 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3966 // Correct second source to be contiguous with first source
3967 if (Start >= (int)NumElts)
3968 Start -= NumElts - NumLaneElts;
3970 // Make sure we're shifting in the right direction.
3971 if (Start <= (int)(i+l))
3976 // Check the rest of the elements to see if they are consecutive.
3977 for (++i; i != NumLaneElts; ++i) {
3978 int Idx = Mask[i+l];
3980 // Make sure its in this lane
3981 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3982 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3985 // If not lane 0, then we must match lane 0
3986 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3989 if (Idx >= (int)NumElts)
3990 Idx -= NumElts - NumLaneElts;
3992 if (!isUndefOrEqual(Idx, Start+i))
4001 /// \brief Return true if the node specifies a shuffle of elements that is
4002 /// suitable for input to PALIGNR.
4003 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4004 const X86Subtarget *Subtarget) {
4005 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4006 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4007 VT.is512BitVector())
4008 // FIXME: Add AVX512BW.
4011 return isAlignrMask(Mask, VT, false);
4014 /// \brief Return true if the node specifies a shuffle of elements that is
4015 /// suitable for input to VALIGN.
4016 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4017 const X86Subtarget *Subtarget) {
4018 // FIXME: Add AVX512VL.
4019 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4021 return isAlignrMask(Mask, VT, true);
4024 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4025 /// the two vector operands have swapped position.
4026 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4027 unsigned NumElems) {
4028 for (unsigned i = 0; i != NumElems; ++i) {
4032 else if (idx < (int)NumElems)
4033 Mask[i] = idx + NumElems;
4035 Mask[i] = idx - NumElems;
4039 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4040 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4041 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4042 /// reverse of what x86 shuffles want.
4043 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4045 unsigned NumElems = VT.getVectorNumElements();
4046 unsigned NumLanes = VT.getSizeInBits()/128;
4047 unsigned NumLaneElems = NumElems/NumLanes;
4049 if (NumLaneElems != 2 && NumLaneElems != 4)
4052 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4053 bool symetricMaskRequired =
4054 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4056 // VSHUFPSY divides the resulting vector into 4 chunks.
4057 // The sources are also splitted into 4 chunks, and each destination
4058 // chunk must come from a different source chunk.
4060 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4061 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4063 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4064 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4066 // VSHUFPDY divides the resulting vector into 4 chunks.
4067 // The sources are also splitted into 4 chunks, and each destination
4068 // chunk must come from a different source chunk.
4070 // SRC1 => X3 X2 X1 X0
4071 // SRC2 => Y3 Y2 Y1 Y0
4073 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4075 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4076 unsigned HalfLaneElems = NumLaneElems/2;
4077 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4078 for (unsigned i = 0; i != NumLaneElems; ++i) {
4079 int Idx = Mask[i+l];
4080 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4081 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4083 // For VSHUFPSY, the mask of the second half must be the same as the
4084 // first but with the appropriate offsets. This works in the same way as
4085 // VPERMILPS works with masks.
4086 if (!symetricMaskRequired || Idx < 0)
4088 if (MaskVal[i] < 0) {
4089 MaskVal[i] = Idx - l;
4092 if ((signed)(Idx - l) != MaskVal[i])
4100 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4101 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4102 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4103 if (!VT.is128BitVector())
4106 unsigned NumElems = VT.getVectorNumElements();
4111 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4112 return isUndefOrEqual(Mask[0], 6) &&
4113 isUndefOrEqual(Mask[1], 7) &&
4114 isUndefOrEqual(Mask[2], 2) &&
4115 isUndefOrEqual(Mask[3], 3);
4118 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4119 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4121 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4122 if (!VT.is128BitVector())
4125 unsigned NumElems = VT.getVectorNumElements();
4130 return isUndefOrEqual(Mask[0], 2) &&
4131 isUndefOrEqual(Mask[1], 3) &&
4132 isUndefOrEqual(Mask[2], 2) &&
4133 isUndefOrEqual(Mask[3], 3);
4136 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4137 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4138 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4139 if (!VT.is128BitVector())
4142 unsigned NumElems = VT.getVectorNumElements();
4144 if (NumElems != 2 && NumElems != 4)
4147 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4148 if (!isUndefOrEqual(Mask[i], i + NumElems))
4151 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4152 if (!isUndefOrEqual(Mask[i], i))
4158 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4159 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4160 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4161 if (!VT.is128BitVector())
4164 unsigned NumElems = VT.getVectorNumElements();
4166 if (NumElems != 2 && NumElems != 4)
4169 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i], i))
4173 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4174 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4180 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4181 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4182 /// i. e: If all but one element come from the same vector.
4183 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4184 // TODO: Deal with AVX's VINSERTPS
4185 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4188 unsigned CorrectPosV1 = 0;
4189 unsigned CorrectPosV2 = 0;
4190 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4191 if (Mask[i] == -1) {
4199 else if (Mask[i] == i + 4)
4203 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4204 // We have 3 elements (undefs count as elements from any vector) from one
4205 // vector, and one from another.
4212 // Some special combinations that can be optimized.
4215 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4216 SelectionDAG &DAG) {
4217 MVT VT = SVOp->getSimpleValueType(0);
4220 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4223 ArrayRef<int> Mask = SVOp->getMask();
4225 // These are the special masks that may be optimized.
4226 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4227 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4228 bool MatchEvenMask = true;
4229 bool MatchOddMask = true;
4230 for (int i=0; i<8; ++i) {
4231 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4232 MatchEvenMask = false;
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4234 MatchOddMask = false;
4237 if (!MatchEvenMask && !MatchOddMask)
4240 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4242 SDValue Op0 = SVOp->getOperand(0);
4243 SDValue Op1 = SVOp->getOperand(1);
4245 if (MatchEvenMask) {
4246 // Shift the second operand right to 32 bits.
4247 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4248 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4250 // Shift the first operand left to 32 bits.
4251 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4252 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4254 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4255 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4258 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4259 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4260 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4261 bool HasInt256, bool V2IsSplat = false) {
4263 assert(VT.getSizeInBits() >= 128 &&
4264 "Unsupported vector type for unpckl");
4266 unsigned NumElts = VT.getVectorNumElements();
4267 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4268 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4271 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4272 "Unsupported vector type for unpckh");
4274 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4275 unsigned NumLanes = VT.getSizeInBits()/128;
4276 unsigned NumLaneElts = NumElts/NumLanes;
4278 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4279 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4280 int BitI = Mask[l+i];
4281 int BitI1 = Mask[l+i+1];
4282 if (!isUndefOrEqual(BitI, j))
4285 if (!isUndefOrEqual(BitI1, NumElts))
4288 if (!isUndefOrEqual(BitI1, j + NumElts))
4297 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4298 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4299 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4300 bool HasInt256, bool V2IsSplat = false) {
4301 assert(VT.getSizeInBits() >= 128 &&
4302 "Unsupported vector type for unpckh");
4304 unsigned NumElts = VT.getVectorNumElements();
4305 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4306 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4309 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4310 "Unsupported vector type for unpckh");
4312 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4313 unsigned NumLanes = VT.getSizeInBits()/128;
4314 unsigned NumLaneElts = NumElts/NumLanes;
4316 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4317 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4318 int BitI = Mask[l+i];
4319 int BitI1 = Mask[l+i+1];
4320 if (!isUndefOrEqual(BitI, j))
4323 if (isUndefOrEqual(BitI1, NumElts))
4326 if (!isUndefOrEqual(BitI1, j+NumElts))
4334 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4335 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4337 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4338 unsigned NumElts = VT.getVectorNumElements();
4339 bool Is256BitVec = VT.is256BitVector();
4341 if (VT.is512BitVector())
4343 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4344 "Unsupported vector type for unpckh");
4346 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4347 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4350 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4351 // FIXME: Need a better way to get rid of this, there's no latency difference
4352 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4353 // the former later. We should also remove the "_undef" special mask.
4354 if (NumElts == 4 && Is256BitVec)
4357 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4358 // independently on 128-bit lanes.
4359 unsigned NumLanes = VT.getSizeInBits()/128;
4360 unsigned NumLaneElts = NumElts/NumLanes;
4362 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4363 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4364 int BitI = Mask[l+i];
4365 int BitI1 = Mask[l+i+1];
4367 if (!isUndefOrEqual(BitI, j))
4369 if (!isUndefOrEqual(BitI1, j))
4377 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4378 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4380 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4381 unsigned NumElts = VT.getVectorNumElements();
4383 if (VT.is512BitVector())
4386 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4387 "Unsupported vector type for unpckh");
4389 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4390 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4393 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4394 // independently on 128-bit lanes.
4395 unsigned NumLanes = VT.getSizeInBits()/128;
4396 unsigned NumLaneElts = NumElts/NumLanes;
4398 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4399 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4400 int BitI = Mask[l+i];
4401 int BitI1 = Mask[l+i+1];
4402 if (!isUndefOrEqual(BitI, j))
4404 if (!isUndefOrEqual(BitI1, j))
4411 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4412 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4413 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4414 if (!VT.is512BitVector())
4417 unsigned NumElts = VT.getVectorNumElements();
4418 unsigned HalfSize = NumElts/2;
4419 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4420 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4425 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4434 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4435 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4436 /// MOVSD, and MOVD, i.e. setting the lowest element.
4437 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4438 if (VT.getVectorElementType().getSizeInBits() < 32)
4440 if (!VT.is128BitVector())
4443 unsigned NumElts = VT.getVectorNumElements();
4445 if (!isUndefOrEqual(Mask[0], NumElts))
4448 for (unsigned i = 1; i != NumElts; ++i)
4449 if (!isUndefOrEqual(Mask[i], i))
4455 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4456 /// as permutations between 128-bit chunks or halves. As an example: this
4458 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4459 /// The first half comes from the second half of V1 and the second half from the
4460 /// the second half of V2.
4461 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4462 if (!HasFp256 || !VT.is256BitVector())
4465 // The shuffle result is divided into half A and half B. In total the two
4466 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4467 // B must come from C, D, E or F.
4468 unsigned HalfSize = VT.getVectorNumElements()/2;
4469 bool MatchA = false, MatchB = false;
4471 // Check if A comes from one of C, D, E, F.
4472 for (unsigned Half = 0; Half != 4; ++Half) {
4473 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4479 // Check if B comes from one of C, D, E, F.
4480 for (unsigned Half = 0; Half != 4; ++Half) {
4481 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4487 return MatchA && MatchB;
4490 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4491 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4492 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4493 MVT VT = SVOp->getSimpleValueType(0);
4495 unsigned HalfSize = VT.getVectorNumElements()/2;
4497 unsigned FstHalf = 0, SndHalf = 0;
4498 for (unsigned i = 0; i < HalfSize; ++i) {
4499 if (SVOp->getMaskElt(i) > 0) {
4500 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4504 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4505 if (SVOp->getMaskElt(i) > 0) {
4506 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4511 return (FstHalf | (SndHalf << 4));
4514 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4515 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4516 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4520 unsigned NumElts = VT.getVectorNumElements();
4522 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4523 for (unsigned i = 0; i != NumElts; ++i) {
4526 Imm8 |= Mask[i] << (i*2);
4531 unsigned LaneSize = 4;
4532 SmallVector<int, 4> MaskVal(LaneSize, -1);
4534 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4535 for (unsigned i = 0; i != LaneSize; ++i) {
4536 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4540 if (MaskVal[i] < 0) {
4541 MaskVal[i] = Mask[i+l] - l;
4542 Imm8 |= MaskVal[i] << (i*2);
4545 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4552 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4553 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4554 /// Note that VPERMIL mask matching is different depending whether theunderlying
4555 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4556 /// to the same elements of the low, but to the higher half of the source.
4557 /// In VPERMILPD the two lanes could be shuffled independently of each other
4558 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4559 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4560 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4561 if (VT.getSizeInBits() < 256 || EltSize < 32)
4563 bool symetricMaskRequired = (EltSize == 32);
4564 unsigned NumElts = VT.getVectorNumElements();
4566 unsigned NumLanes = VT.getSizeInBits()/128;
4567 unsigned LaneSize = NumElts/NumLanes;
4568 // 2 or 4 elements in one lane
4570 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4571 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4572 for (unsigned i = 0; i != LaneSize; ++i) {
4573 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4575 if (symetricMaskRequired) {
4576 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4577 ExpectedMaskVal[i] = Mask[i+l] - l;
4580 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4588 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4589 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4590 /// element of vector 2 and the other elements to come from vector 1 in order.
4591 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4592 bool V2IsSplat = false, bool V2IsUndef = false) {
4593 if (!VT.is128BitVector())
4596 unsigned NumOps = VT.getVectorNumElements();
4597 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4600 if (!isUndefOrEqual(Mask[0], 0))
4603 for (unsigned i = 1; i != NumOps; ++i)
4604 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4605 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4606 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4612 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4613 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4614 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4615 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4616 const X86Subtarget *Subtarget) {
4617 if (!Subtarget->hasSSE3())
4620 unsigned NumElems = VT.getVectorNumElements();
4622 if ((VT.is128BitVector() && NumElems != 4) ||
4623 (VT.is256BitVector() && NumElems != 8) ||
4624 (VT.is512BitVector() && NumElems != 16))
4627 // "i+1" is the value the indexed mask element must have
4628 for (unsigned i = 0; i != NumElems; i += 2)
4629 if (!isUndefOrEqual(Mask[i], i+1) ||
4630 !isUndefOrEqual(Mask[i+1], i+1))
4636 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4637 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4638 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4639 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4640 const X86Subtarget *Subtarget) {
4641 if (!Subtarget->hasSSE3())
4644 unsigned NumElems = VT.getVectorNumElements();
4646 if ((VT.is128BitVector() && NumElems != 4) ||
4647 (VT.is256BitVector() && NumElems != 8) ||
4648 (VT.is512BitVector() && NumElems != 16))
4651 // "i" is the value the indexed mask element must have
4652 for (unsigned i = 0; i != NumElems; i += 2)
4653 if (!isUndefOrEqual(Mask[i], i) ||
4654 !isUndefOrEqual(Mask[i+1], i))
4660 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4661 /// specifies a shuffle of elements that is suitable for input to 256-bit
4662 /// version of MOVDDUP.
4663 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4664 if (!HasFp256 || !VT.is256BitVector())
4667 unsigned NumElts = VT.getVectorNumElements();
4671 for (unsigned i = 0; i != NumElts/2; ++i)
4672 if (!isUndefOrEqual(Mask[i], 0))
4674 for (unsigned i = NumElts/2; i != NumElts; ++i)
4675 if (!isUndefOrEqual(Mask[i], NumElts/2))
4680 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4681 /// specifies a shuffle of elements that is suitable for input to 128-bit
4682 /// version of MOVDDUP.
4683 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4684 if (!VT.is128BitVector())
4687 unsigned e = VT.getVectorNumElements() / 2;
4688 for (unsigned i = 0; i != e; ++i)
4689 if (!isUndefOrEqual(Mask[i], i))
4691 for (unsigned i = 0; i != e; ++i)
4692 if (!isUndefOrEqual(Mask[e+i], i))
4697 /// isVEXTRACTIndex - Return true if the specified
4698 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4699 /// suitable for instruction that extract 128 or 256 bit vectors
4700 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4701 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4702 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4705 // The index should be aligned on a vecWidth-bit boundary.
4707 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4709 MVT VT = N->getSimpleValueType(0);
4710 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4711 bool Result = (Index * ElSize) % vecWidth == 0;
4716 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4717 /// operand specifies a subvector insert that is suitable for input to
4718 /// insertion of 128 or 256-bit subvectors
4719 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4720 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4721 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4723 // The index should be aligned on a vecWidth-bit boundary.
4725 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4727 MVT VT = N->getSimpleValueType(0);
4728 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4729 bool Result = (Index * ElSize) % vecWidth == 0;
4734 bool X86::isVINSERT128Index(SDNode *N) {
4735 return isVINSERTIndex(N, 128);
4738 bool X86::isVINSERT256Index(SDNode *N) {
4739 return isVINSERTIndex(N, 256);
4742 bool X86::isVEXTRACT128Index(SDNode *N) {
4743 return isVEXTRACTIndex(N, 128);
4746 bool X86::isVEXTRACT256Index(SDNode *N) {
4747 return isVEXTRACTIndex(N, 256);
4750 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4751 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4752 /// Handles 128-bit and 256-bit.
4753 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4754 MVT VT = N->getSimpleValueType(0);
4756 assert((VT.getSizeInBits() >= 128) &&
4757 "Unsupported vector type for PSHUF/SHUFP");
4759 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4760 // independently on 128-bit lanes.
4761 unsigned NumElts = VT.getVectorNumElements();
4762 unsigned NumLanes = VT.getSizeInBits()/128;
4763 unsigned NumLaneElts = NumElts/NumLanes;
4765 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4766 "Only supports 2, 4 or 8 elements per lane");
4768 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4770 for (unsigned i = 0; i != NumElts; ++i) {
4771 int Elt = N->getMaskElt(i);
4772 if (Elt < 0) continue;
4773 Elt &= NumLaneElts - 1;
4774 unsigned ShAmt = (i << Shift) % 8;
4775 Mask |= Elt << ShAmt;
4781 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4782 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4783 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4784 MVT VT = N->getSimpleValueType(0);
4786 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4787 "Unsupported vector type for PSHUFHW");
4789 unsigned NumElts = VT.getVectorNumElements();
4792 for (unsigned l = 0; l != NumElts; l += 8) {
4793 // 8 nodes per lane, but we only care about the last 4.
4794 for (unsigned i = 0; i < 4; ++i) {
4795 int Elt = N->getMaskElt(l+i+4);
4796 if (Elt < 0) continue;
4797 Elt &= 0x3; // only 2-bits.
4798 Mask |= Elt << (i * 2);
4805 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4806 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4807 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4808 MVT VT = N->getSimpleValueType(0);
4810 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4811 "Unsupported vector type for PSHUFHW");
4813 unsigned NumElts = VT.getVectorNumElements();
4816 for (unsigned l = 0; l != NumElts; l += 8) {
4817 // 8 nodes per lane, but we only care about the first 4.
4818 for (unsigned i = 0; i < 4; ++i) {
4819 int Elt = N->getMaskElt(l+i);
4820 if (Elt < 0) continue;
4821 Elt &= 0x3; // only 2-bits
4822 Mask |= Elt << (i * 2);
4829 /// \brief Return the appropriate immediate to shuffle the specified
4830 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4831 /// VALIGN (if Interlane is true) instructions.
4832 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4834 MVT VT = SVOp->getSimpleValueType(0);
4835 unsigned EltSize = InterLane ? 1 :
4836 VT.getVectorElementType().getSizeInBits() >> 3;
4838 unsigned NumElts = VT.getVectorNumElements();
4839 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4840 unsigned NumLaneElts = NumElts/NumLanes;
4844 for (i = 0; i != NumElts; ++i) {
4845 Val = SVOp->getMaskElt(i);
4849 if (Val >= (int)NumElts)
4850 Val -= NumElts - NumLaneElts;
4852 assert(Val - i > 0 && "PALIGNR imm should be positive");
4853 return (Val - i) * EltSize;
4856 /// \brief Return the appropriate immediate to shuffle the specified
4857 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4858 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4859 return getShuffleAlignrImmediate(SVOp, false);
4862 /// \brief Return the appropriate immediate to shuffle the specified
4863 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4864 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4865 return getShuffleAlignrImmediate(SVOp, true);
4869 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4870 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4871 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4872 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4875 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4877 MVT VecVT = N->getOperand(0).getSimpleValueType();
4878 MVT ElVT = VecVT.getVectorElementType();
4880 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4881 return Index / NumElemsPerChunk;
4884 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4885 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4886 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4887 llvm_unreachable("Illegal insert subvector for VINSERT");
4890 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4892 MVT VecVT = N->getSimpleValueType(0);
4893 MVT ElVT = VecVT.getVectorElementType();
4895 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4896 return Index / NumElemsPerChunk;
4899 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4900 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4901 /// and VINSERTI128 instructions.
4902 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4903 return getExtractVEXTRACTImmediate(N, 128);
4906 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4907 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4908 /// and VINSERTI64x4 instructions.
4909 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4910 return getExtractVEXTRACTImmediate(N, 256);
4913 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4914 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4915 /// and VINSERTI128 instructions.
4916 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4917 return getInsertVINSERTImmediate(N, 128);
4920 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4921 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4922 /// and VINSERTI64x4 instructions.
4923 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4924 return getInsertVINSERTImmediate(N, 256);
4927 /// isZero - Returns true if Elt is a constant integer zero
4928 static bool isZero(SDValue V) {
4929 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4930 return C && C->isNullValue();
4933 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4935 bool X86::isZeroNode(SDValue Elt) {
4938 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4939 return CFP->getValueAPF().isPosZero();
4943 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4944 /// match movhlps. The lower half elements should come from upper half of
4945 /// V1 (and in order), and the upper half elements should come from the upper
4946 /// half of V2 (and in order).
4947 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4948 if (!VT.is128BitVector())
4950 if (VT.getVectorNumElements() != 4)
4952 for (unsigned i = 0, e = 2; i != e; ++i)
4953 if (!isUndefOrEqual(Mask[i], i+2))
4955 for (unsigned i = 2; i != 4; ++i)
4956 if (!isUndefOrEqual(Mask[i], i+4))
4961 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4962 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4964 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4965 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4967 N = N->getOperand(0).getNode();
4968 if (!ISD::isNON_EXTLoad(N))
4971 *LD = cast<LoadSDNode>(N);
4975 // Test whether the given value is a vector value which will be legalized
4977 static bool WillBeConstantPoolLoad(SDNode *N) {
4978 if (N->getOpcode() != ISD::BUILD_VECTOR)
4981 // Check for any non-constant elements.
4982 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4983 switch (N->getOperand(i).getNode()->getOpcode()) {
4985 case ISD::ConstantFP:
4992 // Vectors of all-zeros and all-ones are materialized with special
4993 // instructions rather than being loaded.
4994 return !ISD::isBuildVectorAllZeros(N) &&
4995 !ISD::isBuildVectorAllOnes(N);
4998 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4999 /// match movlp{s|d}. The lower half elements should come from lower half of
5000 /// V1 (and in order), and the upper half elements should come from the upper
5001 /// half of V2 (and in order). And since V1 will become the source of the
5002 /// MOVLP, it must be either a vector load or a scalar load to vector.
5003 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5004 ArrayRef<int> Mask, MVT VT) {
5005 if (!VT.is128BitVector())
5008 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5010 // Is V2 is a vector load, don't do this transformation. We will try to use
5011 // load folding shufps op.
5012 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5015 unsigned NumElems = VT.getVectorNumElements();
5017 if (NumElems != 2 && NumElems != 4)
5019 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5020 if (!isUndefOrEqual(Mask[i], i))
5022 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5023 if (!isUndefOrEqual(Mask[i], i+NumElems))
5028 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5029 /// to an zero vector.
5030 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5031 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5032 SDValue V1 = N->getOperand(0);
5033 SDValue V2 = N->getOperand(1);
5034 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5035 for (unsigned i = 0; i != NumElems; ++i) {
5036 int Idx = N->getMaskElt(i);
5037 if (Idx >= (int)NumElems) {
5038 unsigned Opc = V2.getOpcode();
5039 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5041 if (Opc != ISD::BUILD_VECTOR ||
5042 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5044 } else if (Idx >= 0) {
5045 unsigned Opc = V1.getOpcode();
5046 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5048 if (Opc != ISD::BUILD_VECTOR ||
5049 !X86::isZeroNode(V1.getOperand(Idx)))
5056 /// getZeroVector - Returns a vector of specified type with all zero elements.
5058 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5059 SelectionDAG &DAG, SDLoc dl) {
5060 assert(VT.isVector() && "Expected a vector type");
5062 // Always build SSE zero vectors as <4 x i32> bitcasted
5063 // to their dest type. This ensures they get CSE'd.
5065 if (VT.is128BitVector()) { // SSE
5066 if (Subtarget->hasSSE2()) { // SSE2
5067 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5068 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5070 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5071 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5073 } else if (VT.is256BitVector()) { // AVX
5074 if (Subtarget->hasInt256()) { // AVX2
5075 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5076 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5077 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5079 // 256-bit logic and arithmetic instructions in AVX are all
5080 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5081 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5082 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5085 } else if (VT.is512BitVector()) { // AVX-512
5086 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5087 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5088 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5089 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5090 } else if (VT.getScalarType() == MVT::i1) {
5091 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5092 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5093 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5094 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5096 llvm_unreachable("Unexpected vector type");
5098 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5101 /// getOnesVector - Returns a vector of specified type with all bits set.
5102 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5103 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5104 /// Then bitcast to their original type, ensuring they get CSE'd.
5105 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5107 assert(VT.isVector() && "Expected a vector type");
5109 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5111 if (VT.is256BitVector()) {
5112 if (HasInt256) { // AVX2
5113 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5114 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5117 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5119 } else if (VT.is128BitVector()) {
5120 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5122 llvm_unreachable("Unexpected vector type");
5124 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5127 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5128 /// that point to V2 points to its first element.
5129 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5130 for (unsigned i = 0; i != NumElems; ++i) {
5131 if (Mask[i] > (int)NumElems) {
5137 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5138 /// operation of specified width.
5139 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5141 unsigned NumElems = VT.getVectorNumElements();
5142 SmallVector<int, 8> Mask;
5143 Mask.push_back(NumElems);
5144 for (unsigned i = 1; i != NumElems; ++i)
5146 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5149 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5150 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5152 unsigned NumElems = VT.getVectorNumElements();
5153 SmallVector<int, 8> Mask;
5154 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5156 Mask.push_back(i + NumElems);
5158 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5161 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5162 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5164 unsigned NumElems = VT.getVectorNumElements();
5165 SmallVector<int, 8> Mask;
5166 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5167 Mask.push_back(i + Half);
5168 Mask.push_back(i + NumElems + Half);
5170 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5173 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5174 // a generic shuffle instruction because the target has no such instructions.
5175 // Generate shuffles which repeat i16 and i8 several times until they can be
5176 // represented by v4f32 and then be manipulated by target suported shuffles.
5177 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5178 MVT VT = V.getSimpleValueType();
5179 int NumElems = VT.getVectorNumElements();
5182 while (NumElems > 4) {
5183 if (EltNo < NumElems/2) {
5184 V = getUnpackl(DAG, dl, VT, V, V);
5186 V = getUnpackh(DAG, dl, VT, V, V);
5187 EltNo -= NumElems/2;
5194 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5195 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5196 MVT VT = V.getSimpleValueType();
5199 if (VT.is128BitVector()) {
5200 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5201 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5202 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5204 } else if (VT.is256BitVector()) {
5205 // To use VPERMILPS to splat scalars, the second half of indicies must
5206 // refer to the higher part, which is a duplication of the lower one,
5207 // because VPERMILPS can only handle in-lane permutations.
5208 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5209 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5211 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5212 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5215 llvm_unreachable("Vector size not supported");
5217 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5220 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5221 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5222 MVT SrcVT = SV->getSimpleValueType(0);
5223 SDValue V1 = SV->getOperand(0);
5226 int EltNo = SV->getSplatIndex();
5227 int NumElems = SrcVT.getVectorNumElements();
5228 bool Is256BitVec = SrcVT.is256BitVector();
5230 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5231 "Unknown how to promote splat for type");
5233 // Extract the 128-bit part containing the splat element and update
5234 // the splat element index when it refers to the higher register.
5236 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5237 if (EltNo >= NumElems/2)
5238 EltNo -= NumElems/2;
5241 // All i16 and i8 vector types can't be used directly by a generic shuffle
5242 // instruction because the target has no such instruction. Generate shuffles
5243 // which repeat i16 and i8 several times until they fit in i32, and then can
5244 // be manipulated by target suported shuffles.
5245 MVT EltVT = SrcVT.getVectorElementType();
5246 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5247 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5249 // Recreate the 256-bit vector and place the same 128-bit vector
5250 // into the low and high part. This is necessary because we want
5251 // to use VPERM* to shuffle the vectors
5253 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5256 return getLegalSplat(DAG, V1, EltNo);
5259 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5260 /// vector of zero or undef vector. This produces a shuffle where the low
5261 /// element of V2 is swizzled into the zero/undef vector, landing at element
5262 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5263 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5265 const X86Subtarget *Subtarget,
5266 SelectionDAG &DAG) {
5267 MVT VT = V2.getSimpleValueType();
5269 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5270 unsigned NumElems = VT.getVectorNumElements();
5271 SmallVector<int, 16> MaskVec;
5272 for (unsigned i = 0; i != NumElems; ++i)
5273 // If this is the insertion idx, put the low elt of V2 here.
5274 MaskVec.push_back(i == Idx ? NumElems : i);
5275 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5278 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5279 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5280 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5281 /// shuffles which use a single input multiple times, and in those cases it will
5282 /// adjust the mask to only have indices within that single input.
5283 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5284 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5285 unsigned NumElems = VT.getVectorNumElements();
5289 bool IsFakeUnary = false;
5290 switch(N->getOpcode()) {
5292 ImmN = N->getOperand(N->getNumOperands()-1);
5293 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5294 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5296 case X86ISD::UNPCKH:
5297 DecodeUNPCKHMask(VT, Mask);
5298 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5300 case X86ISD::UNPCKL:
5301 DecodeUNPCKLMask(VT, Mask);
5302 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5304 case X86ISD::MOVHLPS:
5305 DecodeMOVHLPSMask(NumElems, Mask);
5306 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 case X86ISD::MOVLHPS:
5309 DecodeMOVLHPSMask(NumElems, Mask);
5310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 case X86ISD::PALIGNR:
5313 ImmN = N->getOperand(N->getNumOperands()-1);
5314 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5316 case X86ISD::PSHUFD:
5317 case X86ISD::VPERMILP:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5322 case X86ISD::PSHUFHW:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFLW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFB: {
5334 SDValue MaskNode = N->getOperand(1);
5335 while (MaskNode->getOpcode() == ISD::BITCAST)
5336 MaskNode = MaskNode->getOperand(0);
5338 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5339 // If we have a build-vector, then things are easy.
5340 EVT VT = MaskNode.getValueType();
5341 assert(VT.isVector() &&
5342 "Can't produce a non-vector with a build_vector!");
5343 if (!VT.isInteger())
5346 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5348 SmallVector<uint64_t, 32> RawMask;
5349 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5350 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5353 APInt MaskElement = CN->getAPIntValue();
5355 // We now have to decode the element which could be any integer size and
5356 // extract each byte of it.
5357 for (int j = 0; j < NumBytesPerElement; ++j) {
5358 // Note that this is x86 and so always little endian: the low byte is
5359 // the first byte of the mask.
5360 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5361 MaskElement = MaskElement.lshr(8);
5364 DecodePSHUFBMask(RawMask, Mask);
5368 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5372 SDValue Ptr = MaskLoad->getBasePtr();
5373 if (Ptr->getOpcode() == X86ISD::Wrapper)
5374 Ptr = Ptr->getOperand(0);
5376 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5377 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5380 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5381 // FIXME: Support AVX-512 here.
5382 if (!C->getType()->isVectorTy() ||
5383 (C->getNumElements() != 16 && C->getNumElements() != 32))
5386 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5387 DecodePSHUFBMask(C, Mask);
5393 case X86ISD::VPERMI:
5394 ImmN = N->getOperand(N->getNumOperands()-1);
5395 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5399 case X86ISD::MOVSD: {
5400 // The index 0 always comes from the first element of the second source,
5401 // this is why MOVSS and MOVSD are used in the first place. The other
5402 // elements come from the other positions of the first source vector
5403 Mask.push_back(NumElems);
5404 for (unsigned i = 1; i != NumElems; ++i) {
5409 case X86ISD::VPERM2X128:
5410 ImmN = N->getOperand(N->getNumOperands()-1);
5411 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5412 if (Mask.empty()) return false;
5414 case X86ISD::MOVSLDUP:
5415 DecodeMOVSLDUPMask(VT, Mask);
5417 case X86ISD::MOVSHDUP:
5418 DecodeMOVSHDUPMask(VT, Mask);
5420 case X86ISD::MOVDDUP:
5421 case X86ISD::MOVLHPD:
5422 case X86ISD::MOVLPD:
5423 case X86ISD::MOVLPS:
5424 // Not yet implemented
5426 default: llvm_unreachable("unknown target shuffle node");
5429 // If we have a fake unary shuffle, the shuffle mask is spread across two
5430 // inputs that are actually the same node. Re-map the mask to always point
5431 // into the first input.
5434 if (M >= (int)Mask.size())
5440 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5441 /// element of the result of the vector shuffle.
5442 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5445 return SDValue(); // Limit search depth.
5447 SDValue V = SDValue(N, 0);
5448 EVT VT = V.getValueType();
5449 unsigned Opcode = V.getOpcode();
5451 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5452 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5453 int Elt = SV->getMaskElt(Index);
5456 return DAG.getUNDEF(VT.getVectorElementType());
5458 unsigned NumElems = VT.getVectorNumElements();
5459 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5460 : SV->getOperand(1);
5461 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5464 // Recurse into target specific vector shuffles to find scalars.
5465 if (isTargetShuffle(Opcode)) {
5466 MVT ShufVT = V.getSimpleValueType();
5467 unsigned NumElems = ShufVT.getVectorNumElements();
5468 SmallVector<int, 16> ShuffleMask;
5471 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5474 int Elt = ShuffleMask[Index];
5476 return DAG.getUNDEF(ShufVT.getVectorElementType());
5478 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5480 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5484 // Actual nodes that may contain scalar elements
5485 if (Opcode == ISD::BITCAST) {
5486 V = V.getOperand(0);
5487 EVT SrcVT = V.getValueType();
5488 unsigned NumElems = VT.getVectorNumElements();
5490 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5494 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5495 return (Index == 0) ? V.getOperand(0)
5496 : DAG.getUNDEF(VT.getVectorElementType());
5498 if (V.getOpcode() == ISD::BUILD_VECTOR)
5499 return V.getOperand(Index);
5504 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5505 /// shuffle operation which come from a consecutively from a zero. The
5506 /// search can start in two different directions, from left or right.
5507 /// We count undefs as zeros until PreferredNum is reached.
5508 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5509 unsigned NumElems, bool ZerosFromLeft,
5511 unsigned PreferredNum = -1U) {
5512 unsigned NumZeros = 0;
5513 for (unsigned i = 0; i != NumElems; ++i) {
5514 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5515 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5519 if (X86::isZeroNode(Elt))
5521 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5522 NumZeros = std::min(NumZeros + 1, PreferredNum);
5530 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5531 /// correspond consecutively to elements from one of the vector operands,
5532 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5534 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5535 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5536 unsigned NumElems, unsigned &OpNum) {
5537 bool SeenV1 = false;
5538 bool SeenV2 = false;
5540 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5541 int Idx = SVOp->getMaskElt(i);
5542 // Ignore undef indicies
5546 if (Idx < (int)NumElems)
5551 // Only accept consecutive elements from the same vector
5552 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5556 OpNum = SeenV1 ? 0 : 1;
5560 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5561 /// logical left shift of a vector.
5562 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5563 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5565 SVOp->getSimpleValueType(0).getVectorNumElements();
5566 unsigned NumZeros = getNumOfConsecutiveZeros(
5567 SVOp, NumElems, false /* check zeros from right */, DAG,
5568 SVOp->getMaskElt(0));
5574 // Considering the elements in the mask that are not consecutive zeros,
5575 // check if they consecutively come from only one of the source vectors.
5577 // V1 = {X, A, B, C} 0
5579 // vector_shuffle V1, V2 <1, 2, 3, X>
5581 if (!isShuffleMaskConsecutive(SVOp,
5582 0, // Mask Start Index
5583 NumElems-NumZeros, // Mask End Index(exclusive)
5584 NumZeros, // Where to start looking in the src vector
5585 NumElems, // Number of elements in vector
5586 OpSrc)) // Which source operand ?
5591 ShVal = SVOp->getOperand(OpSrc);
5595 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5596 /// logical left shift of a vector.
5597 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5598 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5600 SVOp->getSimpleValueType(0).getVectorNumElements();
5601 unsigned NumZeros = getNumOfConsecutiveZeros(
5602 SVOp, NumElems, true /* check zeros from left */, DAG,
5603 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5609 // Considering the elements in the mask that are not consecutive zeros,
5610 // check if they consecutively come from only one of the source vectors.
5612 // 0 { A, B, X, X } = V2
5614 // vector_shuffle V1, V2 <X, X, 4, 5>
5616 if (!isShuffleMaskConsecutive(SVOp,
5617 NumZeros, // Mask Start Index
5618 NumElems, // Mask End Index(exclusive)
5619 0, // Where to start looking in the src vector
5620 NumElems, // Number of elements in vector
5621 OpSrc)) // Which source operand ?
5626 ShVal = SVOp->getOperand(OpSrc);
5630 /// isVectorShift - Returns true if the shuffle can be implemented as a
5631 /// logical left or right shift of a vector.
5632 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5633 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5634 // Although the logic below support any bitwidth size, there are no
5635 // shift instructions which handle more than 128-bit vectors.
5636 if (!SVOp->getSimpleValueType(0).is128BitVector())
5639 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5640 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5646 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5648 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5649 unsigned NumNonZero, unsigned NumZero,
5651 const X86Subtarget* Subtarget,
5652 const TargetLowering &TLI) {
5659 for (unsigned i = 0; i < 16; ++i) {
5660 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5661 if (ThisIsNonZero && First) {
5663 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5665 V = DAG.getUNDEF(MVT::v8i16);
5670 SDValue ThisElt, LastElt;
5671 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5672 if (LastIsNonZero) {
5673 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5674 MVT::i16, Op.getOperand(i-1));
5676 if (ThisIsNonZero) {
5677 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5678 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5679 ThisElt, DAG.getConstant(8, MVT::i8));
5681 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5685 if (ThisElt.getNode())
5686 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5687 DAG.getIntPtrConstant(i/2));
5691 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5694 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5696 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5697 unsigned NumNonZero, unsigned NumZero,
5699 const X86Subtarget* Subtarget,
5700 const TargetLowering &TLI) {
5707 for (unsigned i = 0; i < 8; ++i) {
5708 bool isNonZero = (NonZeros & (1 << i)) != 0;
5712 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5714 V = DAG.getUNDEF(MVT::v8i16);
5717 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5718 MVT::v8i16, V, Op.getOperand(i),
5719 DAG.getIntPtrConstant(i));
5726 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5727 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5728 unsigned NonZeros, unsigned NumNonZero,
5729 unsigned NumZero, SelectionDAG &DAG,
5730 const X86Subtarget *Subtarget,
5731 const TargetLowering &TLI) {
5732 // We know there's at least one non-zero element
5733 unsigned FirstNonZeroIdx = 0;
5734 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5735 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5736 X86::isZeroNode(FirstNonZero)) {
5738 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5741 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5742 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5745 SDValue V = FirstNonZero.getOperand(0);
5746 MVT VVT = V.getSimpleValueType();
5747 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5750 unsigned FirstNonZeroDst =
5751 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5752 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5753 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5754 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5756 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5757 SDValue Elem = Op.getOperand(Idx);
5758 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5761 // TODO: What else can be here? Deal with it.
5762 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5765 // TODO: Some optimizations are still possible here
5766 // ex: Getting one element from a vector, and the rest from another.
5767 if (Elem.getOperand(0) != V)
5770 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5773 else if (IncorrectIdx == -1U) {
5777 // There was already one element with an incorrect index.
5778 // We can't optimize this case to an insertps.
5782 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5784 EVT VT = Op.getSimpleValueType();
5785 unsigned ElementMoveMask = 0;
5786 if (IncorrectIdx == -1U)
5787 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5789 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5791 SDValue InsertpsMask =
5792 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5793 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5799 /// getVShift - Return a vector logical shift node.
5801 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5802 unsigned NumBits, SelectionDAG &DAG,
5803 const TargetLowering &TLI, SDLoc dl) {
5804 assert(VT.is128BitVector() && "Unknown type for VShift");
5805 EVT ShVT = MVT::v2i64;
5806 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5807 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5808 return DAG.getNode(ISD::BITCAST, dl, VT,
5809 DAG.getNode(Opc, dl, ShVT, SrcOp,
5810 DAG.getConstant(NumBits,
5811 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5815 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5817 // Check if the scalar load can be widened into a vector load. And if
5818 // the address is "base + cst" see if the cst can be "absorbed" into
5819 // the shuffle mask.
5820 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5821 SDValue Ptr = LD->getBasePtr();
5822 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5824 EVT PVT = LD->getValueType(0);
5825 if (PVT != MVT::i32 && PVT != MVT::f32)
5830 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5831 FI = FINode->getIndex();
5833 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5834 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5835 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5836 Offset = Ptr.getConstantOperandVal(1);
5837 Ptr = Ptr.getOperand(0);
5842 // FIXME: 256-bit vector instructions don't require a strict alignment,
5843 // improve this code to support it better.
5844 unsigned RequiredAlign = VT.getSizeInBits()/8;
5845 SDValue Chain = LD->getChain();
5846 // Make sure the stack object alignment is at least 16 or 32.
5847 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5848 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5849 if (MFI->isFixedObjectIndex(FI)) {
5850 // Can't change the alignment. FIXME: It's possible to compute
5851 // the exact stack offset and reference FI + adjust offset instead.
5852 // If someone *really* cares about this. That's the way to implement it.
5855 MFI->setObjectAlignment(FI, RequiredAlign);
5859 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5860 // Ptr + (Offset & ~15).
5863 if ((Offset % RequiredAlign) & 3)
5865 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5867 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5868 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5870 int EltNo = (Offset - StartOffset) >> 2;
5871 unsigned NumElems = VT.getVectorNumElements();
5873 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5874 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5875 LD->getPointerInfo().getWithOffset(StartOffset),
5876 false, false, false, 0);
5878 SmallVector<int, 8> Mask;
5879 for (unsigned i = 0; i != NumElems; ++i)
5880 Mask.push_back(EltNo);
5882 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5888 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5889 /// vector of type 'VT', see if the elements can be replaced by a single large
5890 /// load which has the same value as a build_vector whose operands are 'elts'.
5892 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5894 /// FIXME: we'd also like to handle the case where the last elements are zero
5895 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5896 /// There's even a handy isZeroNode for that purpose.
5897 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5898 SDLoc &DL, SelectionDAG &DAG,
5899 bool isAfterLegalize) {
5900 EVT EltVT = VT.getVectorElementType();
5901 unsigned NumElems = Elts.size();
5903 LoadSDNode *LDBase = nullptr;
5904 unsigned LastLoadedElt = -1U;
5906 // For each element in the initializer, see if we've found a load or an undef.
5907 // If we don't find an initial load element, or later load elements are
5908 // non-consecutive, bail out.
5909 for (unsigned i = 0; i < NumElems; ++i) {
5910 SDValue Elt = Elts[i];
5912 if (!Elt.getNode() ||
5913 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5916 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5918 LDBase = cast<LoadSDNode>(Elt.getNode());
5922 if (Elt.getOpcode() == ISD::UNDEF)
5925 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5926 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5931 // If we have found an entire vector of loads and undefs, then return a large
5932 // load of the entire vector width starting at the base pointer. If we found
5933 // consecutive loads for the low half, generate a vzext_load node.
5934 if (LastLoadedElt == NumElems - 1) {
5936 if (isAfterLegalize &&
5937 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5940 SDValue NewLd = SDValue();
5942 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5943 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5944 LDBase->getPointerInfo(),
5945 LDBase->isVolatile(), LDBase->isNonTemporal(),
5946 LDBase->isInvariant(), 0);
5947 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5948 LDBase->getPointerInfo(),
5949 LDBase->isVolatile(), LDBase->isNonTemporal(),
5950 LDBase->isInvariant(), LDBase->getAlignment());
5952 if (LDBase->hasAnyUseOfValue(1)) {
5953 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5955 SDValue(NewLd.getNode(), 1));
5956 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5957 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5958 SDValue(NewLd.getNode(), 1));
5963 if (NumElems == 4 && LastLoadedElt == 1 &&
5964 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5965 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5966 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5968 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5969 LDBase->getPointerInfo(),
5970 LDBase->getAlignment(),
5971 false/*isVolatile*/, true/*ReadMem*/,
5974 // Make sure the newly-created LOAD is in the same position as LDBase in
5975 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5976 // update uses of LDBase's output chain to use the TokenFactor.
5977 if (LDBase->hasAnyUseOfValue(1)) {
5978 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5979 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5980 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5981 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5982 SDValue(ResNode.getNode(), 1));
5985 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5990 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5991 /// to generate a splat value for the following cases:
5992 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5993 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5994 /// a scalar load, or a constant.
5995 /// The VBROADCAST node is returned when a pattern is found,
5996 /// or SDValue() otherwise.
5997 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5998 SelectionDAG &DAG) {
5999 if (!Subtarget->hasFp256())
6002 MVT VT = Op.getSimpleValueType();
6005 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6006 "Unsupported vector type for broadcast.");
6011 switch (Op.getOpcode()) {
6013 // Unknown pattern found.
6016 case ISD::BUILD_VECTOR: {
6017 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6018 BitVector UndefElements;
6019 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6021 // We need a splat of a single value to use broadcast, and it doesn't
6022 // make any sense if the value is only in one element of the vector.
6023 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6027 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6028 Ld.getOpcode() == ISD::ConstantFP);
6030 // Make sure that all of the users of a non-constant load are from the
6031 // BUILD_VECTOR node.
6032 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6037 case ISD::VECTOR_SHUFFLE: {
6038 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6040 // Shuffles must have a splat mask where the first element is
6042 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6045 SDValue Sc = Op.getOperand(0);
6046 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6047 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6049 if (!Subtarget->hasInt256())
6052 // Use the register form of the broadcast instruction available on AVX2.
6053 if (VT.getSizeInBits() >= 256)
6054 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6055 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6058 Ld = Sc.getOperand(0);
6059 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6060 Ld.getOpcode() == ISD::ConstantFP);
6062 // The scalar_to_vector node and the suspected
6063 // load node must have exactly one user.
6064 // Constants may have multiple users.
6066 // AVX-512 has register version of the broadcast
6067 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6068 Ld.getValueType().getSizeInBits() >= 32;
6069 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6076 bool IsGE256 = (VT.getSizeInBits() >= 256);
6078 // Handle the broadcasting a single constant scalar from the constant pool
6079 // into a vector. On Sandybridge it is still better to load a constant vector
6080 // from the constant pool and not to broadcast it from a scalar.
6081 if (ConstSplatVal && Subtarget->hasInt256()) {
6082 EVT CVT = Ld.getValueType();
6083 assert(!CVT.isVector() && "Must not broadcast a vector type");
6084 unsigned ScalarSize = CVT.getSizeInBits();
6086 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
6087 const Constant *C = nullptr;
6088 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6089 C = CI->getConstantIntValue();
6090 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6091 C = CF->getConstantFPValue();
6093 assert(C && "Invalid constant type");
6095 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6096 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6097 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6098 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6099 MachinePointerInfo::getConstantPool(),
6100 false, false, false, Alignment);
6102 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6106 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6107 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6109 // Handle AVX2 in-register broadcasts.
6110 if (!IsLoad && Subtarget->hasInt256() &&
6111 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6112 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6114 // The scalar source must be a normal load.
6118 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6119 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6121 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6122 // double since there is no vbroadcastsd xmm
6123 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6124 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6125 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6128 // Unsupported broadcast.
6132 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6133 /// underlying vector and index.
6135 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6137 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6139 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6140 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6143 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6145 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6147 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6148 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6151 // In this case the vector is the extract_subvector expression and the index
6152 // is 2, as specified by the shuffle.
6153 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6154 SDValue ShuffleVec = SVOp->getOperand(0);
6155 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6156 assert(ShuffleVecVT.getVectorElementType() ==
6157 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6159 int ShuffleIdx = SVOp->getMaskElt(Idx);
6160 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6161 ExtractedFromVec = ShuffleVec;
6167 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6168 MVT VT = Op.getSimpleValueType();
6170 // Skip if insert_vec_elt is not supported.
6171 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6172 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6176 unsigned NumElems = Op.getNumOperands();
6180 SmallVector<unsigned, 4> InsertIndices;
6181 SmallVector<int, 8> Mask(NumElems, -1);
6183 for (unsigned i = 0; i != NumElems; ++i) {
6184 unsigned Opc = Op.getOperand(i).getOpcode();
6186 if (Opc == ISD::UNDEF)
6189 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6190 // Quit if more than 1 elements need inserting.
6191 if (InsertIndices.size() > 1)
6194 InsertIndices.push_back(i);
6198 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6199 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6200 // Quit if non-constant index.
6201 if (!isa<ConstantSDNode>(ExtIdx))
6203 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6205 // Quit if extracted from vector of different type.
6206 if (ExtractedFromVec.getValueType() != VT)
6209 if (!VecIn1.getNode())
6210 VecIn1 = ExtractedFromVec;
6211 else if (VecIn1 != ExtractedFromVec) {
6212 if (!VecIn2.getNode())
6213 VecIn2 = ExtractedFromVec;
6214 else if (VecIn2 != ExtractedFromVec)
6215 // Quit if more than 2 vectors to shuffle
6219 if (ExtractedFromVec == VecIn1)
6221 else if (ExtractedFromVec == VecIn2)
6222 Mask[i] = Idx + NumElems;
6225 if (!VecIn1.getNode())
6228 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6229 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6230 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6231 unsigned Idx = InsertIndices[i];
6232 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6233 DAG.getIntPtrConstant(Idx));
6239 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6241 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6243 MVT VT = Op.getSimpleValueType();
6244 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6245 "Unexpected type in LowerBUILD_VECTORvXi1!");
6248 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6249 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6250 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6251 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6254 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6255 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6256 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6257 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6260 bool AllContants = true;
6261 uint64_t Immediate = 0;
6262 int NonConstIdx = -1;
6263 bool IsSplat = true;
6264 unsigned NumNonConsts = 0;
6265 unsigned NumConsts = 0;
6266 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6267 SDValue In = Op.getOperand(idx);
6268 if (In.getOpcode() == ISD::UNDEF)
6270 if (!isa<ConstantSDNode>(In)) {
6271 AllContants = false;
6277 if (cast<ConstantSDNode>(In)->getZExtValue())
6278 Immediate |= (1ULL << idx);
6280 if (In != Op.getOperand(0))
6285 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6286 DAG.getConstant(Immediate, MVT::i16));
6287 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6288 DAG.getIntPtrConstant(0));
6291 if (NumNonConsts == 1 && NonConstIdx != 0) {
6294 SDValue VecAsImm = DAG.getConstant(Immediate,
6295 MVT::getIntegerVT(VT.getSizeInBits()));
6296 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6299 DstVec = DAG.getUNDEF(VT);
6300 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6301 Op.getOperand(NonConstIdx),
6302 DAG.getIntPtrConstant(NonConstIdx));
6304 if (!IsSplat && (NonConstIdx != 0))
6305 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6306 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6309 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6310 DAG.getConstant(-1, SelectVT),
6311 DAG.getConstant(0, SelectVT));
6313 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6314 DAG.getConstant((Immediate | 1), SelectVT),
6315 DAG.getConstant(Immediate, SelectVT));
6316 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6319 /// \brief Return true if \p N implements a horizontal binop and return the
6320 /// operands for the horizontal binop into V0 and V1.
6322 /// This is a helper function of PerformBUILD_VECTORCombine.
6323 /// This function checks that the build_vector \p N in input implements a
6324 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6325 /// operation to match.
6326 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6327 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6328 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6331 /// This function only analyzes elements of \p N whose indices are
6332 /// in range [BaseIdx, LastIdx).
6333 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6335 unsigned BaseIdx, unsigned LastIdx,
6336 SDValue &V0, SDValue &V1) {
6337 EVT VT = N->getValueType(0);
6339 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6340 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6341 "Invalid Vector in input!");
6343 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6344 bool CanFold = true;
6345 unsigned ExpectedVExtractIdx = BaseIdx;
6346 unsigned NumElts = LastIdx - BaseIdx;
6347 V0 = DAG.getUNDEF(VT);
6348 V1 = DAG.getUNDEF(VT);
6350 // Check if N implements a horizontal binop.
6351 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6352 SDValue Op = N->getOperand(i + BaseIdx);
6355 if (Op->getOpcode() == ISD::UNDEF) {
6356 // Update the expected vector extract index.
6357 if (i * 2 == NumElts)
6358 ExpectedVExtractIdx = BaseIdx;
6359 ExpectedVExtractIdx += 2;
6363 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6368 SDValue Op0 = Op.getOperand(0);
6369 SDValue Op1 = Op.getOperand(1);
6371 // Try to match the following pattern:
6372 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6373 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6374 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6375 Op0.getOperand(0) == Op1.getOperand(0) &&
6376 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6377 isa<ConstantSDNode>(Op1.getOperand(1)));
6381 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6382 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6384 if (i * 2 < NumElts) {
6385 if (V0.getOpcode() == ISD::UNDEF)
6386 V0 = Op0.getOperand(0);
6388 if (V1.getOpcode() == ISD::UNDEF)
6389 V1 = Op0.getOperand(0);
6390 if (i * 2 == NumElts)
6391 ExpectedVExtractIdx = BaseIdx;
6394 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6395 if (I0 == ExpectedVExtractIdx)
6396 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6397 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6398 // Try to match the following dag sequence:
6399 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6400 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6404 ExpectedVExtractIdx += 2;
6410 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6411 /// a concat_vector.
6413 /// This is a helper function of PerformBUILD_VECTORCombine.
6414 /// This function expects two 256-bit vectors called V0 and V1.
6415 /// At first, each vector is split into two separate 128-bit vectors.
6416 /// Then, the resulting 128-bit vectors are used to implement two
6417 /// horizontal binary operations.
6419 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6421 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6422 /// the two new horizontal binop.
6423 /// When Mode is set, the first horizontal binop dag node would take as input
6424 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6425 /// horizontal binop dag node would take as input the lower 128-bit of V1
6426 /// and the upper 128-bit of V1.
6428 /// HADD V0_LO, V0_HI
6429 /// HADD V1_LO, V1_HI
6431 /// Otherwise, the first horizontal binop dag node takes as input the lower
6432 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6433 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6435 /// HADD V0_LO, V1_LO
6436 /// HADD V0_HI, V1_HI
6438 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6439 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6440 /// the upper 128-bits of the result.
6441 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6442 SDLoc DL, SelectionDAG &DAG,
6443 unsigned X86Opcode, bool Mode,
6444 bool isUndefLO, bool isUndefHI) {
6445 EVT VT = V0.getValueType();
6446 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6447 "Invalid nodes in input!");
6449 unsigned NumElts = VT.getVectorNumElements();
6450 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6451 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6452 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6453 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6454 EVT NewVT = V0_LO.getValueType();
6456 SDValue LO = DAG.getUNDEF(NewVT);
6457 SDValue HI = DAG.getUNDEF(NewVT);
6460 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6461 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6462 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6463 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6464 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6466 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6467 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6468 V1_LO->getOpcode() != ISD::UNDEF))
6469 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6471 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6472 V1_HI->getOpcode() != ISD::UNDEF))
6473 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6476 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6479 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6480 /// sequence of 'vadd + vsub + blendi'.
6481 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6482 const X86Subtarget *Subtarget) {
6484 EVT VT = BV->getValueType(0);
6485 unsigned NumElts = VT.getVectorNumElements();
6486 SDValue InVec0 = DAG.getUNDEF(VT);
6487 SDValue InVec1 = DAG.getUNDEF(VT);
6489 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6490 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6492 // Odd-numbered elements in the input build vector are obtained from
6493 // adding two integer/float elements.
6494 // Even-numbered elements in the input build vector are obtained from
6495 // subtracting two integer/float elements.
6496 unsigned ExpectedOpcode = ISD::FSUB;
6497 unsigned NextExpectedOpcode = ISD::FADD;
6498 bool AddFound = false;
6499 bool SubFound = false;
6501 for (unsigned i = 0, e = NumElts; i != e; i++) {
6502 SDValue Op = BV->getOperand(i);
6504 // Skip 'undef' values.
6505 unsigned Opcode = Op.getOpcode();
6506 if (Opcode == ISD::UNDEF) {
6507 std::swap(ExpectedOpcode, NextExpectedOpcode);
6511 // Early exit if we found an unexpected opcode.
6512 if (Opcode != ExpectedOpcode)
6515 SDValue Op0 = Op.getOperand(0);
6516 SDValue Op1 = Op.getOperand(1);
6518 // Try to match the following pattern:
6519 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6520 // Early exit if we cannot match that sequence.
6521 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6522 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6523 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6524 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6525 Op0.getOperand(1) != Op1.getOperand(1))
6528 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6532 // We found a valid add/sub node. Update the information accordingly.
6538 // Update InVec0 and InVec1.
6539 if (InVec0.getOpcode() == ISD::UNDEF)
6540 InVec0 = Op0.getOperand(0);
6541 if (InVec1.getOpcode() == ISD::UNDEF)
6542 InVec1 = Op1.getOperand(0);
6544 // Make sure that operands in input to each add/sub node always
6545 // come from a same pair of vectors.
6546 if (InVec0 != Op0.getOperand(0)) {
6547 if (ExpectedOpcode == ISD::FSUB)
6550 // FADD is commutable. Try to commute the operands
6551 // and then test again.
6552 std::swap(Op0, Op1);
6553 if (InVec0 != Op0.getOperand(0))
6557 if (InVec1 != Op1.getOperand(0))
6560 // Update the pair of expected opcodes.
6561 std::swap(ExpectedOpcode, NextExpectedOpcode);
6564 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6565 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6566 InVec1.getOpcode() != ISD::UNDEF)
6567 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6572 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6573 const X86Subtarget *Subtarget) {
6575 EVT VT = N->getValueType(0);
6576 unsigned NumElts = VT.getVectorNumElements();
6577 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6578 SDValue InVec0, InVec1;
6580 // Try to match an ADDSUB.
6581 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6582 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6583 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6584 if (Value.getNode())
6588 // Try to match horizontal ADD/SUB.
6589 unsigned NumUndefsLO = 0;
6590 unsigned NumUndefsHI = 0;
6591 unsigned Half = NumElts/2;
6593 // Count the number of UNDEF operands in the build_vector in input.
6594 for (unsigned i = 0, e = Half; i != e; ++i)
6595 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6598 for (unsigned i = Half, e = NumElts; i != e; ++i)
6599 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6602 // Early exit if this is either a build_vector of all UNDEFs or all the
6603 // operands but one are UNDEF.
6604 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6607 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6608 // Try to match an SSE3 float HADD/HSUB.
6609 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6610 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6612 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6613 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6614 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6615 // Try to match an SSSE3 integer HADD/HSUB.
6616 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6617 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6619 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6620 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6623 if (!Subtarget->hasAVX())
6626 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6627 // Try to match an AVX horizontal add/sub of packed single/double
6628 // precision floating point values from 256-bit vectors.
6629 SDValue InVec2, InVec3;
6630 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6631 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6632 ((InVec0.getOpcode() == ISD::UNDEF ||
6633 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6634 ((InVec1.getOpcode() == ISD::UNDEF ||
6635 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6636 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6638 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6639 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6640 ((InVec0.getOpcode() == ISD::UNDEF ||
6641 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6642 ((InVec1.getOpcode() == ISD::UNDEF ||
6643 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6644 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6645 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6646 // Try to match an AVX2 horizontal add/sub of signed integers.
6647 SDValue InVec2, InVec3;
6649 bool CanFold = true;
6651 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6652 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6653 ((InVec0.getOpcode() == ISD::UNDEF ||
6654 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6655 ((InVec1.getOpcode() == ISD::UNDEF ||
6656 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6657 X86Opcode = X86ISD::HADD;
6658 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6659 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6660 ((InVec0.getOpcode() == ISD::UNDEF ||
6661 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6662 ((InVec1.getOpcode() == ISD::UNDEF ||
6663 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6664 X86Opcode = X86ISD::HSUB;
6669 // Fold this build_vector into a single horizontal add/sub.
6670 // Do this only if the target has AVX2.
6671 if (Subtarget->hasAVX2())
6672 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6674 // Do not try to expand this build_vector into a pair of horizontal
6675 // add/sub if we can emit a pair of scalar add/sub.
6676 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6679 // Convert this build_vector into a pair of horizontal binop followed by
6681 bool isUndefLO = NumUndefsLO == Half;
6682 bool isUndefHI = NumUndefsHI == Half;
6683 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6684 isUndefLO, isUndefHI);
6688 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6689 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6691 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6692 X86Opcode = X86ISD::HADD;
6693 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6694 X86Opcode = X86ISD::HSUB;
6695 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6696 X86Opcode = X86ISD::FHADD;
6697 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6698 X86Opcode = X86ISD::FHSUB;
6702 // Don't try to expand this build_vector into a pair of horizontal add/sub
6703 // if we can simply emit a pair of scalar add/sub.
6704 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6707 // Convert this build_vector into two horizontal add/sub followed by
6709 bool isUndefLO = NumUndefsLO == Half;
6710 bool isUndefHI = NumUndefsHI == Half;
6711 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6712 isUndefLO, isUndefHI);
6719 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6722 MVT VT = Op.getSimpleValueType();
6723 MVT ExtVT = VT.getVectorElementType();
6724 unsigned NumElems = Op.getNumOperands();
6726 // Generate vectors for predicate vectors.
6727 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6728 return LowerBUILD_VECTORvXi1(Op, DAG);
6730 // Vectors containing all zeros can be matched by pxor and xorps later
6731 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6732 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6733 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6734 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6737 return getZeroVector(VT, Subtarget, DAG, dl);
6740 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6741 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6742 // vpcmpeqd on 256-bit vectors.
6743 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6744 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6747 if (!VT.is512BitVector())
6748 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6751 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6752 if (Broadcast.getNode())
6755 unsigned EVTBits = ExtVT.getSizeInBits();
6757 unsigned NumZero = 0;
6758 unsigned NumNonZero = 0;
6759 unsigned NonZeros = 0;
6760 bool IsAllConstants = true;
6761 SmallSet<SDValue, 8> Values;
6762 for (unsigned i = 0; i < NumElems; ++i) {
6763 SDValue Elt = Op.getOperand(i);
6764 if (Elt.getOpcode() == ISD::UNDEF)
6767 if (Elt.getOpcode() != ISD::Constant &&
6768 Elt.getOpcode() != ISD::ConstantFP)
6769 IsAllConstants = false;
6770 if (X86::isZeroNode(Elt))
6773 NonZeros |= (1 << i);
6778 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6779 if (NumNonZero == 0)
6780 return DAG.getUNDEF(VT);
6782 // Special case for single non-zero, non-undef, element.
6783 if (NumNonZero == 1) {
6784 unsigned Idx = countTrailingZeros(NonZeros);
6785 SDValue Item = Op.getOperand(Idx);
6787 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6788 // the value are obviously zero, truncate the value to i32 and do the
6789 // insertion that way. Only do this if the value is non-constant or if the
6790 // value is a constant being inserted into element 0. It is cheaper to do
6791 // a constant pool load than it is to do a movd + shuffle.
6792 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6793 (!IsAllConstants || Idx == 0)) {
6794 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6796 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6797 EVT VecVT = MVT::v4i32;
6798 unsigned VecElts = 4;
6800 // Truncate the value (which may itself be a constant) to i32, and
6801 // convert it to a vector with movd (S2V+shuffle to zero extend).
6802 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6803 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6805 // If using the new shuffle lowering, just directly insert this.
6806 if (ExperimentalVectorShuffleLowering)
6808 ISD::BITCAST, dl, VT,
6809 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6811 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6813 // Now we have our 32-bit value zero extended in the low element of
6814 // a vector. If Idx != 0, swizzle it into place.
6816 SmallVector<int, 4> Mask;
6817 Mask.push_back(Idx);
6818 for (unsigned i = 1; i != VecElts; ++i)
6820 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6823 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6827 // If we have a constant or non-constant insertion into the low element of
6828 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6829 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6830 // depending on what the source datatype is.
6833 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6835 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6836 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6837 if (VT.is256BitVector() || VT.is512BitVector()) {
6838 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6839 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6840 Item, DAG.getIntPtrConstant(0));
6842 assert(VT.is128BitVector() && "Expected an SSE value type!");
6843 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6844 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6845 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6848 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6849 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6850 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6851 if (VT.is256BitVector()) {
6852 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6853 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6855 assert(VT.is128BitVector() && "Expected an SSE value type!");
6856 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6858 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6862 // Is it a vector logical left shift?
6863 if (NumElems == 2 && Idx == 1 &&
6864 X86::isZeroNode(Op.getOperand(0)) &&
6865 !X86::isZeroNode(Op.getOperand(1))) {
6866 unsigned NumBits = VT.getSizeInBits();
6867 return getVShift(true, VT,
6868 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6869 VT, Op.getOperand(1)),
6870 NumBits/2, DAG, *this, dl);
6873 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6876 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6877 // is a non-constant being inserted into an element other than the low one,
6878 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6879 // movd/movss) to move this into the low element, then shuffle it into
6881 if (EVTBits == 32) {
6882 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6884 // If using the new shuffle lowering, just directly insert this.
6885 if (ExperimentalVectorShuffleLowering)
6886 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6888 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6889 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6890 SmallVector<int, 8> MaskVec;
6891 for (unsigned i = 0; i != NumElems; ++i)
6892 MaskVec.push_back(i == Idx ? 0 : 1);
6893 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6897 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6898 if (Values.size() == 1) {
6899 if (EVTBits == 32) {
6900 // Instead of a shuffle like this:
6901 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6902 // Check if it's possible to issue this instead.
6903 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6904 unsigned Idx = countTrailingZeros(NonZeros);
6905 SDValue Item = Op.getOperand(Idx);
6906 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6907 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6912 // A vector full of immediates; various special cases are already
6913 // handled, so this is best done with a single constant-pool load.
6917 // For AVX-length vectors, build the individual 128-bit pieces and use
6918 // shuffles to put them in place.
6919 if (VT.is256BitVector() || VT.is512BitVector()) {
6920 SmallVector<SDValue, 64> V;
6921 for (unsigned i = 0; i != NumElems; ++i)
6922 V.push_back(Op.getOperand(i));
6924 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6926 // Build both the lower and upper subvector.
6927 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6928 makeArrayRef(&V[0], NumElems/2));
6929 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6930 makeArrayRef(&V[NumElems / 2], NumElems/2));
6932 // Recreate the wider vector with the lower and upper part.
6933 if (VT.is256BitVector())
6934 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6935 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6938 // Let legalizer expand 2-wide build_vectors.
6939 if (EVTBits == 64) {
6940 if (NumNonZero == 1) {
6941 // One half is zero or undef.
6942 unsigned Idx = countTrailingZeros(NonZeros);
6943 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6944 Op.getOperand(Idx));
6945 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6950 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6951 if (EVTBits == 8 && NumElems == 16) {
6952 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6954 if (V.getNode()) return V;
6957 if (EVTBits == 16 && NumElems == 8) {
6958 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6960 if (V.getNode()) return V;
6963 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6964 if (EVTBits == 32 && NumElems == 4) {
6965 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6966 NumZero, DAG, Subtarget, *this);
6971 // If element VT is == 32 bits, turn it into a number of shuffles.
6972 SmallVector<SDValue, 8> V(NumElems);
6973 if (NumElems == 4 && NumZero > 0) {
6974 for (unsigned i = 0; i < 4; ++i) {
6975 bool isZero = !(NonZeros & (1 << i));
6977 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6979 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6982 for (unsigned i = 0; i < 2; ++i) {
6983 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6986 V[i] = V[i*2]; // Must be a zero vector.
6989 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6992 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6995 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7000 bool Reverse1 = (NonZeros & 0x3) == 2;
7001 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7005 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7006 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7008 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7011 if (Values.size() > 1 && VT.is128BitVector()) {
7012 // Check for a build vector of consecutive loads.
7013 for (unsigned i = 0; i < NumElems; ++i)
7014 V[i] = Op.getOperand(i);
7016 // Check for elements which are consecutive loads.
7017 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7021 // Check for a build vector from mostly shuffle plus few inserting.
7022 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7026 // For SSE 4.1, use insertps to put the high elements into the low element.
7027 if (getSubtarget()->hasSSE41()) {
7029 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7030 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7032 Result = DAG.getUNDEF(VT);
7034 for (unsigned i = 1; i < NumElems; ++i) {
7035 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7036 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7037 Op.getOperand(i), DAG.getIntPtrConstant(i));
7042 // Otherwise, expand into a number of unpckl*, start by extending each of
7043 // our (non-undef) elements to the full vector width with the element in the
7044 // bottom slot of the vector (which generates no code for SSE).
7045 for (unsigned i = 0; i < NumElems; ++i) {
7046 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7047 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7049 V[i] = DAG.getUNDEF(VT);
7052 // Next, we iteratively mix elements, e.g. for v4f32:
7053 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7054 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7055 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7056 unsigned EltStride = NumElems >> 1;
7057 while (EltStride != 0) {
7058 for (unsigned i = 0; i < EltStride; ++i) {
7059 // If V[i+EltStride] is undef and this is the first round of mixing,
7060 // then it is safe to just drop this shuffle: V[i] is already in the
7061 // right place, the one element (since it's the first round) being
7062 // inserted as undef can be dropped. This isn't safe for successive
7063 // rounds because they will permute elements within both vectors.
7064 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7065 EltStride == NumElems/2)
7068 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7077 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7078 // to create 256-bit vectors from two other 128-bit ones.
7079 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7081 MVT ResVT = Op.getSimpleValueType();
7083 assert((ResVT.is256BitVector() ||
7084 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7086 SDValue V1 = Op.getOperand(0);
7087 SDValue V2 = Op.getOperand(1);
7088 unsigned NumElems = ResVT.getVectorNumElements();
7089 if(ResVT.is256BitVector())
7090 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7092 if (Op.getNumOperands() == 4) {
7093 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7094 ResVT.getVectorNumElements()/2);
7095 SDValue V3 = Op.getOperand(2);
7096 SDValue V4 = Op.getOperand(3);
7097 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7098 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7100 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7103 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7104 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7105 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7106 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7107 Op.getNumOperands() == 4)));
7109 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7110 // from two other 128-bit ones.
7112 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7113 return LowerAVXCONCAT_VECTORS(Op, DAG);
7117 //===----------------------------------------------------------------------===//
7118 // Vector shuffle lowering
7120 // This is an experimental code path for lowering vector shuffles on x86. It is
7121 // designed to handle arbitrary vector shuffles and blends, gracefully
7122 // degrading performance as necessary. It works hard to recognize idiomatic
7123 // shuffles and lower them to optimal instruction patterns without leaving
7124 // a framework that allows reasonably efficient handling of all vector shuffle
7126 //===----------------------------------------------------------------------===//
7128 /// \brief Tiny helper function to identify a no-op mask.
7130 /// This is a somewhat boring predicate function. It checks whether the mask
7131 /// array input, which is assumed to be a single-input shuffle mask of the kind
7132 /// used by the X86 shuffle instructions (not a fully general
7133 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7134 /// in-place shuffle are 'no-op's.
7135 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7136 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7137 if (Mask[i] != -1 && Mask[i] != i)
7142 /// \brief Helper function to classify a mask as a single-input mask.
7144 /// This isn't a generic single-input test because in the vector shuffle
7145 /// lowering we canonicalize single inputs to be the first input operand. This
7146 /// means we can more quickly test for a single input by only checking whether
7147 /// an input from the second operand exists. We also assume that the size of
7148 /// mask corresponds to the size of the input vectors which isn't true in the
7149 /// fully general case.
7150 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7152 if (M >= (int)Mask.size())
7157 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7158 // 2013 will allow us to use it as a non-type template parameter.
7161 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7163 /// See its documentation for details.
7164 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7165 if (Mask.size() != Args.size())
7167 for (int i = 0, e = Mask.size(); i < e; ++i) {
7168 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7169 assert(*Args[i] < (int)Args.size() * 2 &&
7170 "Argument outside the range of possible shuffle inputs!");
7171 if (Mask[i] != -1 && Mask[i] != *Args[i])
7179 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7182 /// This is a fast way to test a shuffle mask against a fixed pattern:
7184 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7186 /// It returns true if the mask is exactly as wide as the argument list, and
7187 /// each element of the mask is either -1 (signifying undef) or the value given
7188 /// in the argument.
7189 static const VariadicFunction1<
7190 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7192 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7194 /// This helper function produces an 8-bit shuffle immediate corresponding to
7195 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7196 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7199 /// NB: We rely heavily on "undef" masks preserving the input lane.
7200 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7201 SelectionDAG &DAG) {
7202 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7203 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7204 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7205 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7206 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7209 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7210 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7211 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7212 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7213 return DAG.getConstant(Imm, MVT::i8);
7216 /// \brief Try to emit a blend instruction for a shuffle.
7218 /// This doesn't do any checks for the availability of instructions for blending
7219 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7220 /// be matched in the backend with the type given. What it does check for is
7221 /// that the shuffle mask is in fact a blend.
7222 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7223 SDValue V2, ArrayRef<int> Mask,
7224 SelectionDAG &DAG) {
7226 unsigned BlendMask = 0;
7227 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7228 if (Mask[i] >= Size) {
7229 if (Mask[i] != i + Size)
7230 return SDValue(); // Shuffled V2 input!
7231 BlendMask |= 1u << i;
7234 if (Mask[i] >= 0 && Mask[i] != i)
7235 return SDValue(); // Shuffled V1 input!
7237 if (VT == MVT::v4f32 || VT == MVT::v2f64)
7238 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7239 DAG.getConstant(BlendMask, MVT::i8));
7240 assert(!VT.isFloatingPoint() && "Only v4f32 and v2f64 are supported!");
7242 // For integer shuffles we need to expand the mask and cast the inputs to
7243 // v8i16s prior to blending.
7244 assert((VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v2i64) &&
7245 "Not a supported integer vector type!");
7246 int Scale = 8 / VT.getVectorNumElements();
7248 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7249 if (Mask[i] >= Size)
7250 for (int j = 0; j < Scale; ++j)
7251 BlendMask |= 1u << (i * Scale + j);
7253 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7254 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7255 return DAG.getNode(ISD::BITCAST, DL, VT,
7256 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7257 DAG.getConstant(BlendMask, MVT::i8)));
7260 /// \brief Try to lower a vector shuffle as a byte rotation.
7262 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7263 /// byte-rotation of a the concatentation of two vectors. This routine will
7264 /// try to generically lower a vector shuffle through such an instruction. It
7265 /// does not check for the availability of PALIGNR-based lowerings, only the
7266 /// applicability of this strategy to the given mask. This matches shuffle
7267 /// vectors that look like:
7269 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7271 /// Essentially it concatenates V1 and V2, shifts right by some number of
7272 /// elements, and takes the low elements as the result. Note that while this is
7273 /// specified as a *right shift* because x86 is little-endian, it is a *left
7274 /// rotate* of the vector lanes.
7276 /// Note that this only handles 128-bit vector widths currently.
7277 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7280 SelectionDAG &DAG) {
7281 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7283 // We need to detect various ways of spelling a rotation:
7284 // [11, 12, 13, 14, 15, 0, 1, 2]
7285 // [-1, 12, 13, 14, -1, -1, 1, -1]
7286 // [-1, -1, -1, -1, -1, -1, 1, 2]
7287 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7288 // [-1, 4, 5, 6, -1, -1, 9, -1]
7289 // [-1, 4, 5, 6, -1, -1, -1, -1]
7292 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7295 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7297 // Based on the mod-Size value of this mask element determine where
7298 // a rotated vector would have started.
7299 int StartIdx = i - (Mask[i] % Size);
7301 // The identity rotation isn't interesting, stop.
7304 // If we found the tail of a vector the rotation must be the missing
7305 // front. If we found the head of a vector, it must be how much of the head.
7306 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7309 Rotation = CandidateRotation;
7310 else if (Rotation != CandidateRotation)
7311 // The rotations don't match, so we can't match this mask.
7314 // Compute which value this mask is pointing at.
7315 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7317 // Compute which of the two target values this index should be assigned to.
7318 // This reflects whether the high elements are remaining or the low elements
7320 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7322 // Either set up this value if we've not encountered it before, or check
7323 // that it remains consistent.
7326 else if (TargetV != MaskV)
7327 // This may be a rotation, but it pulls from the inputs in some
7328 // unsupported interleaving.
7332 // Check that we successfully analyzed the mask, and normalize the results.
7333 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7334 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7340 // Cast the inputs to v16i8 to match PALIGNR.
7341 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7342 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7344 assert(VT.getSizeInBits() == 128 &&
7345 "Rotate-based lowering only supports 128-bit lowering!");
7346 assert(Mask.size() <= 16 &&
7347 "Can shuffle at most 16 bytes in a 128-bit vector!");
7348 // The actual rotate instruction rotates bytes, so we need to scale the
7349 // rotation based on how many bytes are in the vector.
7350 int Scale = 16 / Mask.size();
7352 return DAG.getNode(ISD::BITCAST, DL, VT,
7353 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7354 DAG.getConstant(Rotation * Scale, MVT::i8)));
7357 /// \brief Compute whether each element of a shuffle is zeroable.
7359 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7360 /// Either it is an undef element in the shuffle mask, the element of the input
7361 /// referenced is undef, or the element of the input referenced is known to be
7362 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7363 /// as many lanes with this technique as possible to simplify the remaining
7365 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7366 SDValue V1, SDValue V2) {
7367 SmallBitVector Zeroable(Mask.size(), false);
7369 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7370 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7372 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7374 // Handle the easy cases.
7375 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7380 // If this is an index into a build_vector node, dig out the input value and
7382 SDValue V = M < Size ? V1 : V2;
7383 if (V.getOpcode() != ISD::BUILD_VECTOR)
7386 SDValue Input = V.getOperand(M % Size);
7387 // The UNDEF opcode check really should be dead code here, but not quite
7388 // worth asserting on (it isn't invalid, just unexpected).
7389 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7396 /// \brief Lower a vector shuffle as a zero or any extension.
7398 /// Given a specific number of elements, element bit width, and extension
7399 /// stride, produce either a zero or any extension based on the available
7400 /// features of the subtarget.
7401 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7402 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7403 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7404 assert(Scale > 1 && "Need a scale to extend.");
7405 int EltBits = VT.getSizeInBits() / NumElements;
7406 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7407 "Only 8, 16, and 32 bit elements can be extended.");
7408 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7410 // Found a valid zext mask! Try various lowering strategies based on the
7411 // input type and available ISA extensions.
7412 if (Subtarget->hasSSE41()) {
7413 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7414 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7415 NumElements / Scale);
7416 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7417 return DAG.getNode(ISD::BITCAST, DL, VT,
7418 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7421 // For any extends we can cheat for larger element sizes and use shuffle
7422 // instructions that can fold with a load and/or copy.
7423 if (AnyExt && EltBits == 32) {
7424 int PSHUFDMask[4] = {0, -1, 1, -1};
7426 ISD::BITCAST, DL, VT,
7427 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7428 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7429 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7431 if (AnyExt && EltBits == 16 && Scale > 2) {
7432 int PSHUFDMask[4] = {0, -1, 0, -1};
7433 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7434 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7435 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7436 int PSHUFHWMask[4] = {1, -1, -1, -1};
7438 ISD::BITCAST, DL, VT,
7439 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7440 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7441 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7444 // If this would require more than 2 unpack instructions to expand, use
7445 // pshufb when available. We can only use more than 2 unpack instructions
7446 // when zero extending i8 elements which also makes it easier to use pshufb.
7447 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7448 assert(NumElements == 16 && "Unexpected byte vector width!");
7449 SDValue PSHUFBMask[16];
7450 for (int i = 0; i < 16; ++i)
7452 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7453 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7454 return DAG.getNode(ISD::BITCAST, DL, VT,
7455 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7456 DAG.getNode(ISD::BUILD_VECTOR, DL,
7457 MVT::v16i8, PSHUFBMask)));
7460 // Otherwise emit a sequence of unpacks.
7462 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7463 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7464 : getZeroVector(InputVT, Subtarget, DAG, DL);
7465 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7466 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7470 } while (Scale > 1);
7471 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7474 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7476 /// This routine will try to do everything in its power to cleverly lower
7477 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7478 /// check for the profitability of this lowering, it tries to aggressively
7479 /// match this pattern. It will use all of the micro-architectural details it
7480 /// can to emit an efficient lowering. It handles both blends with all-zero
7481 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7482 /// masking out later).
7484 /// The reason we have dedicated lowering for zext-style shuffles is that they
7485 /// are both incredibly common and often quite performance sensitive.
7486 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7487 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7488 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7489 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7491 int Bits = VT.getSizeInBits();
7492 int NumElements = Mask.size();
7494 // Define a helper function to check a particular ext-scale and lower to it if
7496 auto Lower = [&](int Scale) -> SDValue {
7499 for (int i = 0; i < NumElements; ++i) {
7501 continue; // Valid anywhere but doesn't tell us anything.
7502 if (i % Scale != 0) {
7503 // Each of the extend elements needs to be zeroable.
7507 // We no lorger are in the anyext case.
7512 // Each of the base elements needs to be consecutive indices into the
7513 // same input vector.
7514 SDValue V = Mask[i] < NumElements ? V1 : V2;
7517 else if (InputV != V)
7518 return SDValue(); // Flip-flopping inputs.
7520 if (Mask[i] % NumElements != i / Scale)
7521 return SDValue(); // Non-consecutive strided elemenst.
7524 // If we fail to find an input, we have a zero-shuffle which should always
7525 // have already been handled.
7526 // FIXME: Maybe handle this here in case during blending we end up with one?
7530 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7531 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7534 // The widest scale possible for extending is to a 64-bit integer.
7535 assert(Bits % 64 == 0 &&
7536 "The number of bits in a vector must be divisible by 64 on x86!");
7537 int NumExtElements = Bits / 64;
7539 // Each iteration, try extending the elements half as much, but into twice as
7541 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7542 assert(NumElements % NumExtElements == 0 &&
7543 "The input vector size must be divisble by the extended size.");
7544 if (SDValue V = Lower(NumElements / NumExtElements))
7548 // No viable ext lowering found.
7552 /// \brief Try to lower insertion of a single element into a zero vector.
7554 /// This is a common pattern that we have especially efficient patterns to lower
7555 /// across all subtarget feature sets.
7556 static SDValue lowerIntegerElementInsertionVectorShuffle(
7557 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7558 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7559 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7561 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7562 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7565 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7566 if (i != V2Index && !Zeroable[i])
7567 return SDValue(); // Not inserting into a zero vector.
7569 // Check for a single input from a SCALAR_TO_VECTOR node.
7570 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7571 // all the smarts here sunk into that routine. However, the current
7572 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7573 // vector shuffle lowering is dead.
7574 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7575 Mask[V2Index] == (int)Mask.size()) ||
7576 V2.getOpcode() == ISD::BUILD_VECTOR))
7579 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7581 // First, we need to zext the scalar if it is smaller than an i32.
7582 MVT EltVT = VT.getVectorElementType();
7583 assert(EltVT == V2S.getSimpleValueType() &&
7584 "Different scalar and element types!");
7586 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7587 // Zero-extend directly to i32.
7589 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7592 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7593 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7595 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7598 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7599 // the desired position. Otherwise it is more efficient to do a vector
7600 // shift left. We know that we can do a vector shift left because all
7601 // the inputs are zero.
7602 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7603 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7604 V2Shuffle[V2Index] = 0;
7605 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7607 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7609 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7611 V2Index * EltVT.getSizeInBits(),
7612 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7613 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7619 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7621 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7622 /// support for floating point shuffles but not integer shuffles. These
7623 /// instructions will incur a domain crossing penalty on some chips though so
7624 /// it is better to avoid lowering through this for integer vectors where
7626 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7627 const X86Subtarget *Subtarget,
7628 SelectionDAG &DAG) {
7630 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7631 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7632 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7633 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7634 ArrayRef<int> Mask = SVOp->getMask();
7635 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7637 if (isSingleInputShuffleMask(Mask)) {
7638 // Straight shuffle of a single input vector. Simulate this by using the
7639 // single input as both of the "inputs" to this instruction..
7640 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7641 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7642 DAG.getConstant(SHUFPDMask, MVT::i8));
7644 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7645 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7647 // Use dedicated unpack instructions for masks that match their pattern.
7648 if (isShuffleEquivalent(Mask, 0, 2))
7649 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7650 if (isShuffleEquivalent(Mask, 1, 3))
7651 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7653 if (Subtarget->hasSSE41())
7655 lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask, DAG))
7658 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7659 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7660 DAG.getConstant(SHUFPDMask, MVT::i8));
7663 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7665 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7666 /// the integer unit to minimize domain crossing penalties. However, for blends
7667 /// it falls back to the floating point shuffle operation with appropriate bit
7669 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7670 const X86Subtarget *Subtarget,
7671 SelectionDAG &DAG) {
7673 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7674 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7675 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7676 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7677 ArrayRef<int> Mask = SVOp->getMask();
7678 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7680 if (isSingleInputShuffleMask(Mask)) {
7681 // Straight shuffle of a single input vector. For everything from SSE2
7682 // onward this has a single fast instruction with no scary immediates.
7683 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7684 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7685 int WidenedMask[4] = {
7686 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7687 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7689 ISD::BITCAST, DL, MVT::v2i64,
7690 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7691 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7694 // Use dedicated unpack instructions for masks that match their pattern.
7695 if (isShuffleEquivalent(Mask, 0, 2))
7696 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7697 if (isShuffleEquivalent(Mask, 1, 3))
7698 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7700 if (Subtarget->hasSSE41())
7702 lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask, DAG))
7705 // Try to use rotation instructions if available.
7706 if (Subtarget->hasSSSE3())
7707 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7708 DL, MVT::v2i64, V1, V2, Mask, DAG))
7711 // We implement this with SHUFPD which is pretty lame because it will likely
7712 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7713 // However, all the alternatives are still more cycles and newer chips don't
7714 // have this problem. It would be really nice if x86 had better shuffles here.
7715 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7716 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7717 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7718 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7721 /// \brief Lower 4-lane 32-bit floating point shuffles.
7723 /// Uses instructions exclusively from the floating point unit to minimize
7724 /// domain crossing penalties, as these are sufficient to implement all v4f32
7726 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7727 const X86Subtarget *Subtarget,
7728 SelectionDAG &DAG) {
7730 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7731 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7732 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7733 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7734 ArrayRef<int> Mask = SVOp->getMask();
7735 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7737 SDValue LowV = V1, HighV = V2;
7738 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7741 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7743 if (NumV2Elements == 0)
7744 // Straight shuffle of a single input vector. We pass the input vector to
7745 // both operands to simulate this with a SHUFPS.
7746 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7747 getV4X86ShuffleImm8ForMask(Mask, DAG));
7749 // Use dedicated unpack instructions for masks that match their pattern.
7750 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7751 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7752 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7753 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7755 if (Subtarget->hasSSE41())
7757 lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask, DAG))
7760 if (NumV2Elements == 1) {
7762 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7765 // Check for whether we can use INSERTPS to perform the blend. We only use
7766 // INSERTPS when the V1 elements are already in the correct locations
7767 // because otherwise we can just always use two SHUFPS instructions which
7768 // are much smaller to encode than a SHUFPS and an INSERTPS.
7769 if (Subtarget->hasSSE41()) {
7770 // When using INSERTPS we can zero any lane of the destination. Collect
7771 // the zero inputs into a mask and drop them from the lanes of V1 which
7772 // actually need to be present as inputs to the INSERTPS.
7774 if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7775 ZMask = 0xF ^ (1 << V2Index);
7776 } else if (V1.getOpcode() == ISD::BUILD_VECTOR) {
7777 for (int i = 0; i < 4; ++i) {
7782 SDValue Input = V1.getOperand(M);
7783 if (Input.getOpcode() != ISD::UNDEF &&
7784 !X86::isZeroNode(Input)) {
7785 // A non-zero input!
7794 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
7795 int InsertShuffleMask[4] = {-1, -1, -1, -1};
7796 for (int i = 0; i < 4; ++i)
7797 if (i != V2Index && (ZMask & (1 << i)) == 0)
7798 InsertShuffleMask[i] = Mask[i];
7800 if (isNoopShuffleMask(InsertShuffleMask)) {
7801 // Replace V1 with undef if nothing from V1 survives the INSERTPS.
7802 if ((ZMask | 1 << V2Index) == 0xF)
7803 V1 = DAG.getUNDEF(MVT::v4f32);
7805 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
7806 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7808 // Insert the V2 element into the desired position.
7809 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7810 DAG.getConstant(InsertPSMask, MVT::i8));
7814 // Compute the index adjacent to V2Index and in the same half by toggling
7816 int V2AdjIndex = V2Index ^ 1;
7818 if (Mask[V2AdjIndex] == -1) {
7819 // Handles all the cases where we have a single V2 element and an undef.
7820 // This will only ever happen in the high lanes because we commute the
7821 // vector otherwise.
7823 std::swap(LowV, HighV);
7824 NewMask[V2Index] -= 4;
7826 // Handle the case where the V2 element ends up adjacent to a V1 element.
7827 // To make this work, blend them together as the first step.
7828 int V1Index = V2AdjIndex;
7829 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7830 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7831 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7833 // Now proceed to reconstruct the final blend as we have the necessary
7834 // high or low half formed.
7841 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7842 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7844 } else if (NumV2Elements == 2) {
7845 if (Mask[0] < 4 && Mask[1] < 4) {
7846 // Handle the easy case where we have V1 in the low lanes and V2 in the
7847 // high lanes. We never see this reversed because we sort the shuffle.
7851 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7852 // trying to place elements directly, just blend them and set up the final
7853 // shuffle to place them.
7855 // The first two blend mask elements are for V1, the second two are for
7857 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7858 Mask[2] < 4 ? Mask[2] : Mask[3],
7859 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7860 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7861 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7862 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7864 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7867 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7868 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7869 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7870 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7873 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7874 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7877 /// \brief Lower 4-lane i32 vector shuffles.
7879 /// We try to handle these with integer-domain shuffles where we can, but for
7880 /// blends we use the floating point domain blend instructions.
7881 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7882 const X86Subtarget *Subtarget,
7883 SelectionDAG &DAG) {
7885 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7886 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7887 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7888 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7889 ArrayRef<int> Mask = SVOp->getMask();
7890 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7893 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7895 if (NumV2Elements == 0) {
7896 // Straight shuffle of a single input vector. For everything from SSE2
7897 // onward this has a single fast instruction with no scary immediates.
7898 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7899 // but we aren't actually going to use the UNPCK instruction because doing
7900 // so prevents folding a load into this instruction or making a copy.
7901 const int UnpackLoMask[] = {0, 0, 1, 1};
7902 const int UnpackHiMask[] = {2, 2, 3, 3};
7903 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
7904 Mask = UnpackLoMask;
7905 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
7906 Mask = UnpackHiMask;
7908 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7909 getV4X86ShuffleImm8ForMask(Mask, DAG));
7912 // Whenever we can lower this as a zext, that instruction is strictly faster
7913 // than any alternative.
7914 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7915 Mask, Subtarget, DAG))
7918 // Use dedicated unpack instructions for masks that match their pattern.
7919 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7920 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7921 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7922 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7924 // There are special ways we can lower some single-element blends.
7925 if (NumV2Elements == 1)
7926 if (SDValue V = lowerIntegerElementInsertionVectorShuffle(
7927 MVT::v4i32, DL, V1, V2, Mask, Subtarget, DAG))
7930 if (Subtarget->hasSSE41())
7932 lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask, DAG))
7935 // Try to use rotation instructions if available.
7936 if (Subtarget->hasSSSE3())
7937 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7938 DL, MVT::v4i32, V1, V2, Mask, DAG))
7941 // We implement this with SHUFPS because it can blend from two vectors.
7942 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7943 // up the inputs, bypassing domain shift penalties that we would encur if we
7944 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7946 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7947 DAG.getVectorShuffle(
7949 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7950 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7953 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7954 /// shuffle lowering, and the most complex part.
7956 /// The lowering strategy is to try to form pairs of input lanes which are
7957 /// targeted at the same half of the final vector, and then use a dword shuffle
7958 /// to place them onto the right half, and finally unpack the paired lanes into
7959 /// their final position.
7961 /// The exact breakdown of how to form these dword pairs and align them on the
7962 /// correct sides is really tricky. See the comments within the function for
7963 /// more of the details.
7964 static SDValue lowerV8I16SingleInputVectorShuffle(
7965 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7966 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7967 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7968 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7969 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7971 SmallVector<int, 4> LoInputs;
7972 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7973 [](int M) { return M >= 0; });
7974 std::sort(LoInputs.begin(), LoInputs.end());
7975 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7976 SmallVector<int, 4> HiInputs;
7977 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7978 [](int M) { return M >= 0; });
7979 std::sort(HiInputs.begin(), HiInputs.end());
7980 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7982 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7983 int NumHToL = LoInputs.size() - NumLToL;
7985 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7986 int NumHToH = HiInputs.size() - NumLToH;
7987 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7988 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7989 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7990 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7992 // Use dedicated unpack instructions for masks that match their pattern.
7993 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
7994 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
7995 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
7996 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
7998 // Try to use rotation instructions if available.
7999 if (Subtarget->hasSSSE3())
8000 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8001 DL, MVT::v8i16, V, V, Mask, DAG))
8004 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8005 // such inputs we can swap two of the dwords across the half mark and end up
8006 // with <=2 inputs to each half in each half. Once there, we can fall through
8007 // to the generic code below. For example:
8009 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8010 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8012 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8013 // and an existing 2-into-2 on the other half. In this case we may have to
8014 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8015 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8016 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8017 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8018 // half than the one we target for fixing) will be fixed when we re-enter this
8019 // path. We will also combine away any sequence of PSHUFD instructions that
8020 // result into a single instruction. Here is an example of the tricky case:
8022 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8023 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8025 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8027 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8028 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8030 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8031 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8033 // The result is fine to be handled by the generic logic.
8034 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8035 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8036 int AOffset, int BOffset) {
8037 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8038 "Must call this with A having 3 or 1 inputs from the A half.");
8039 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8040 "Must call this with B having 1 or 3 inputs from the B half.");
8041 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8042 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8044 // Compute the index of dword with only one word among the three inputs in
8045 // a half by taking the sum of the half with three inputs and subtracting
8046 // the sum of the actual three inputs. The difference is the remaining
8049 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8050 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8051 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8052 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8053 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8054 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8055 int TripleNonInputIdx =
8056 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8057 TripleDWord = TripleNonInputIdx / 2;
8059 // We use xor with one to compute the adjacent DWord to whichever one the
8061 OneInputDWord = (OneInput / 2) ^ 1;
8063 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8064 // and BToA inputs. If there is also such a problem with the BToB and AToB
8065 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8066 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8067 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8068 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8069 // Compute how many inputs will be flipped by swapping these DWords. We
8071 // to balance this to ensure we don't form a 3-1 shuffle in the other
8073 int NumFlippedAToBInputs =
8074 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8075 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8076 int NumFlippedBToBInputs =
8077 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8078 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8079 if ((NumFlippedAToBInputs == 1 &&
8080 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8081 (NumFlippedBToBInputs == 1 &&
8082 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8083 // We choose whether to fix the A half or B half based on whether that
8084 // half has zero flipped inputs. At zero, we may not be able to fix it
8085 // with that half. We also bias towards fixing the B half because that
8086 // will more commonly be the high half, and we have to bias one way.
8087 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8088 ArrayRef<int> Inputs) {
8089 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8090 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8091 PinnedIdx ^ 1) != Inputs.end();
8092 // Determine whether the free index is in the flipped dword or the
8093 // unflipped dword based on where the pinned index is. We use this bit
8094 // in an xor to conditionally select the adjacent dword.
8095 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8096 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8097 FixFreeIdx) != Inputs.end();
8098 if (IsFixIdxInput == IsFixFreeIdxInput)
8100 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8101 FixFreeIdx) != Inputs.end();
8102 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8103 "We need to be changing the number of flipped inputs!");
8104 int PSHUFHalfMask[] = {0, 1, 2, 3};
8105 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8106 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8108 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8111 if (M != -1 && M == FixIdx)
8113 else if (M != -1 && M == FixFreeIdx)
8116 if (NumFlippedBToBInputs != 0) {
8118 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8119 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8121 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8123 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8124 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8129 int PSHUFDMask[] = {0, 1, 2, 3};
8130 PSHUFDMask[ADWord] = BDWord;
8131 PSHUFDMask[BDWord] = ADWord;
8132 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8133 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8134 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8135 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8137 // Adjust the mask to match the new locations of A and B.
8139 if (M != -1 && M/2 == ADWord)
8140 M = 2 * BDWord + M % 2;
8141 else if (M != -1 && M/2 == BDWord)
8142 M = 2 * ADWord + M % 2;
8144 // Recurse back into this routine to re-compute state now that this isn't
8145 // a 3 and 1 problem.
8146 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8149 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8150 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8151 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8152 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8154 // At this point there are at most two inputs to the low and high halves from
8155 // each half. That means the inputs can always be grouped into dwords and
8156 // those dwords can then be moved to the correct half with a dword shuffle.
8157 // We use at most one low and one high word shuffle to collect these paired
8158 // inputs into dwords, and finally a dword shuffle to place them.
8159 int PSHUFLMask[4] = {-1, -1, -1, -1};
8160 int PSHUFHMask[4] = {-1, -1, -1, -1};
8161 int PSHUFDMask[4] = {-1, -1, -1, -1};
8163 // First fix the masks for all the inputs that are staying in their
8164 // original halves. This will then dictate the targets of the cross-half
8166 auto fixInPlaceInputs =
8167 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8168 MutableArrayRef<int> SourceHalfMask,
8169 MutableArrayRef<int> HalfMask, int HalfOffset) {
8170 if (InPlaceInputs.empty())
8172 if (InPlaceInputs.size() == 1) {
8173 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8174 InPlaceInputs[0] - HalfOffset;
8175 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8178 if (IncomingInputs.empty()) {
8179 // Just fix all of the in place inputs.
8180 for (int Input : InPlaceInputs) {
8181 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8182 PSHUFDMask[Input / 2] = Input / 2;
8187 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8188 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8189 InPlaceInputs[0] - HalfOffset;
8190 // Put the second input next to the first so that they are packed into
8191 // a dword. We find the adjacent index by toggling the low bit.
8192 int AdjIndex = InPlaceInputs[0] ^ 1;
8193 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8194 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8195 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8197 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8198 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8200 // Now gather the cross-half inputs and place them into a free dword of
8201 // their target half.
8202 // FIXME: This operation could almost certainly be simplified dramatically to
8203 // look more like the 3-1 fixing operation.
8204 auto moveInputsToRightHalf = [&PSHUFDMask](
8205 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8206 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8207 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8209 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8210 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8212 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8214 int LowWord = Word & ~1;
8215 int HighWord = Word | 1;
8216 return isWordClobbered(SourceHalfMask, LowWord) ||
8217 isWordClobbered(SourceHalfMask, HighWord);
8220 if (IncomingInputs.empty())
8223 if (ExistingInputs.empty()) {
8224 // Map any dwords with inputs from them into the right half.
8225 for (int Input : IncomingInputs) {
8226 // If the source half mask maps over the inputs, turn those into
8227 // swaps and use the swapped lane.
8228 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8229 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8230 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8231 Input - SourceOffset;
8232 // We have to swap the uses in our half mask in one sweep.
8233 for (int &M : HalfMask)
8234 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8236 else if (M == Input)
8237 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8239 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8240 Input - SourceOffset &&
8241 "Previous placement doesn't match!");
8243 // Note that this correctly re-maps both when we do a swap and when
8244 // we observe the other side of the swap above. We rely on that to
8245 // avoid swapping the members of the input list directly.
8246 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8249 // Map the input's dword into the correct half.
8250 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8251 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8253 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8255 "Previous placement doesn't match!");
8258 // And just directly shift any other-half mask elements to be same-half
8259 // as we will have mirrored the dword containing the element into the
8260 // same position within that half.
8261 for (int &M : HalfMask)
8262 if (M >= SourceOffset && M < SourceOffset + 4) {
8263 M = M - SourceOffset + DestOffset;
8264 assert(M >= 0 && "This should never wrap below zero!");
8269 // Ensure we have the input in a viable dword of its current half. This
8270 // is particularly tricky because the original position may be clobbered
8271 // by inputs being moved and *staying* in that half.
8272 if (IncomingInputs.size() == 1) {
8273 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8274 int InputFixed = std::find(std::begin(SourceHalfMask),
8275 std::end(SourceHalfMask), -1) -
8276 std::begin(SourceHalfMask) + SourceOffset;
8277 SourceHalfMask[InputFixed - SourceOffset] =
8278 IncomingInputs[0] - SourceOffset;
8279 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8281 IncomingInputs[0] = InputFixed;
8283 } else if (IncomingInputs.size() == 2) {
8284 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8285 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8286 // We have two non-adjacent or clobbered inputs we need to extract from
8287 // the source half. To do this, we need to map them into some adjacent
8288 // dword slot in the source mask.
8289 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8290 IncomingInputs[1] - SourceOffset};
8292 // If there is a free slot in the source half mask adjacent to one of
8293 // the inputs, place the other input in it. We use (Index XOR 1) to
8294 // compute an adjacent index.
8295 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8296 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8297 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8298 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8299 InputsFixed[1] = InputsFixed[0] ^ 1;
8300 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8301 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8302 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8303 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8304 InputsFixed[0] = InputsFixed[1] ^ 1;
8305 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8306 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8307 // The two inputs are in the same DWord but it is clobbered and the
8308 // adjacent DWord isn't used at all. Move both inputs to the free
8310 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8311 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8312 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8313 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8315 // The only way we hit this point is if there is no clobbering
8316 // (because there are no off-half inputs to this half) and there is no
8317 // free slot adjacent to one of the inputs. In this case, we have to
8318 // swap an input with a non-input.
8319 for (int i = 0; i < 4; ++i)
8320 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8321 "We can't handle any clobbers here!");
8322 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8323 "Cannot have adjacent inputs here!");
8325 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8326 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8328 // We also have to update the final source mask in this case because
8329 // it may need to undo the above swap.
8330 for (int &M : FinalSourceHalfMask)
8331 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8332 M = InputsFixed[1] + SourceOffset;
8333 else if (M == InputsFixed[1] + SourceOffset)
8334 M = (InputsFixed[0] ^ 1) + SourceOffset;
8336 InputsFixed[1] = InputsFixed[0] ^ 1;
8339 // Point everything at the fixed inputs.
8340 for (int &M : HalfMask)
8341 if (M == IncomingInputs[0])
8342 M = InputsFixed[0] + SourceOffset;
8343 else if (M == IncomingInputs[1])
8344 M = InputsFixed[1] + SourceOffset;
8346 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8347 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8350 llvm_unreachable("Unhandled input size!");
8353 // Now hoist the DWord down to the right half.
8354 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8355 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8356 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8357 for (int &M : HalfMask)
8358 for (int Input : IncomingInputs)
8360 M = FreeDWord * 2 + Input % 2;
8362 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8363 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8364 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8365 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8367 // Now enact all the shuffles we've computed to move the inputs into their
8369 if (!isNoopShuffleMask(PSHUFLMask))
8370 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8371 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8372 if (!isNoopShuffleMask(PSHUFHMask))
8373 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8374 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8375 if (!isNoopShuffleMask(PSHUFDMask))
8376 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8377 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8378 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8379 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8381 // At this point, each half should contain all its inputs, and we can then
8382 // just shuffle them into their final position.
8383 assert(std::count_if(LoMask.begin(), LoMask.end(),
8384 [](int M) { return M >= 4; }) == 0 &&
8385 "Failed to lift all the high half inputs to the low mask!");
8386 assert(std::count_if(HiMask.begin(), HiMask.end(),
8387 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8388 "Failed to lift all the low half inputs to the high mask!");
8390 // Do a half shuffle for the low mask.
8391 if (!isNoopShuffleMask(LoMask))
8392 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8393 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8395 // Do a half shuffle with the high mask after shifting its values down.
8396 for (int &M : HiMask)
8399 if (!isNoopShuffleMask(HiMask))
8400 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8401 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8406 /// \brief Detect whether the mask pattern should be lowered through
8409 /// This essentially tests whether viewing the mask as an interleaving of two
8410 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8411 /// lowering it through interleaving is a significantly better strategy.
8412 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8413 int NumEvenInputs[2] = {0, 0};
8414 int NumOddInputs[2] = {0, 0};
8415 int NumLoInputs[2] = {0, 0};
8416 int NumHiInputs[2] = {0, 0};
8417 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8421 int InputIdx = Mask[i] >= Size;
8424 ++NumLoInputs[InputIdx];
8426 ++NumHiInputs[InputIdx];
8429 ++NumEvenInputs[InputIdx];
8431 ++NumOddInputs[InputIdx];
8434 // The minimum number of cross-input results for both the interleaved and
8435 // split cases. If interleaving results in fewer cross-input results, return
8437 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8438 NumEvenInputs[0] + NumOddInputs[1]);
8439 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8440 NumLoInputs[0] + NumHiInputs[1]);
8441 return InterleavedCrosses < SplitCrosses;
8444 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8446 /// This strategy only works when the inputs from each vector fit into a single
8447 /// half of that vector, and generally there are not so many inputs as to leave
8448 /// the in-place shuffles required highly constrained (and thus expensive). It
8449 /// shifts all the inputs into a single side of both input vectors and then
8450 /// uses an unpack to interleave these inputs in a single vector. At that
8451 /// point, we will fall back on the generic single input shuffle lowering.
8452 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8454 MutableArrayRef<int> Mask,
8455 const X86Subtarget *Subtarget,
8456 SelectionDAG &DAG) {
8457 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8458 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8459 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8460 for (int i = 0; i < 8; ++i)
8461 if (Mask[i] >= 0 && Mask[i] < 4)
8462 LoV1Inputs.push_back(i);
8463 else if (Mask[i] >= 4 && Mask[i] < 8)
8464 HiV1Inputs.push_back(i);
8465 else if (Mask[i] >= 8 && Mask[i] < 12)
8466 LoV2Inputs.push_back(i);
8467 else if (Mask[i] >= 12)
8468 HiV2Inputs.push_back(i);
8470 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8471 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8474 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8475 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8476 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8478 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8479 HiV1Inputs.size() + HiV2Inputs.size();
8481 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8482 ArrayRef<int> HiInputs, bool MoveToLo,
8484 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8485 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8486 if (BadInputs.empty())
8489 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8490 int MoveOffset = MoveToLo ? 0 : 4;
8492 if (GoodInputs.empty()) {
8493 for (int BadInput : BadInputs) {
8494 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8495 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8498 if (GoodInputs.size() == 2) {
8499 // If the low inputs are spread across two dwords, pack them into
8501 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8502 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8503 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8504 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8506 // Otherwise pin the good inputs.
8507 for (int GoodInput : GoodInputs)
8508 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8511 if (BadInputs.size() == 2) {
8512 // If we have two bad inputs then there may be either one or two good
8513 // inputs fixed in place. Find a fixed input, and then find the *other*
8514 // two adjacent indices by using modular arithmetic.
8516 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8517 [](int M) { return M >= 0; }) -
8518 std::begin(MoveMask);
8520 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8521 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8522 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8523 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8524 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8525 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8526 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8528 assert(BadInputs.size() == 1 && "All sizes handled");
8529 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8530 std::end(MoveMask), -1) -
8531 std::begin(MoveMask);
8532 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8533 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8537 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8540 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8542 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8545 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8546 // cross-half traffic in the final shuffle.
8548 // Munge the mask to be a single-input mask after the unpack merges the
8552 M = 2 * (M % 4) + (M / 8);
8554 return DAG.getVectorShuffle(
8555 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8556 DL, MVT::v8i16, V1, V2),
8557 DAG.getUNDEF(MVT::v8i16), Mask);
8560 /// \brief Generic lowering of 8-lane i16 shuffles.
8562 /// This handles both single-input shuffles and combined shuffle/blends with
8563 /// two inputs. The single input shuffles are immediately delegated to
8564 /// a dedicated lowering routine.
8566 /// The blends are lowered in one of three fundamental ways. If there are few
8567 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8568 /// of the input is significantly cheaper when lowered as an interleaving of
8569 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8570 /// halves of the inputs separately (making them have relatively few inputs)
8571 /// and then concatenate them.
8572 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8573 const X86Subtarget *Subtarget,
8574 SelectionDAG &DAG) {
8576 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8577 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8578 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8579 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8580 ArrayRef<int> OrigMask = SVOp->getMask();
8581 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8582 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8583 MutableArrayRef<int> Mask(MaskStorage);
8585 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8587 // Whenever we can lower this as a zext, that instruction is strictly faster
8588 // than any alternative.
8589 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8590 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8593 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8594 auto isV2 = [](int M) { return M >= 8; };
8596 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8597 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8599 if (NumV2Inputs == 0)
8600 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8602 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8603 "to be V1-input shuffles.");
8605 // There are special ways we can lower some single-element blends.
8606 if (NumV2Inputs == 1)
8607 if (SDValue V = lowerIntegerElementInsertionVectorShuffle(
8608 MVT::v8i16, DL, V1, V2, Mask, Subtarget, DAG))
8611 if (Subtarget->hasSSE41())
8613 lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8616 // Try to use rotation instructions if available.
8617 if (Subtarget->hasSSSE3())
8618 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8621 if (NumV1Inputs + NumV2Inputs <= 4)
8622 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8624 // Check whether an interleaving lowering is likely to be more efficient.
8625 // This isn't perfect but it is a strong heuristic that tends to work well on
8626 // the kinds of shuffles that show up in practice.
8628 // FIXME: Handle 1x, 2x, and 4x interleaving.
8629 if (shouldLowerAsInterleaving(Mask)) {
8630 // FIXME: Figure out whether we should pack these into the low or high
8633 int EMask[8], OMask[8];
8634 for (int i = 0; i < 4; ++i) {
8635 EMask[i] = Mask[2*i];
8636 OMask[i] = Mask[2*i + 1];
8641 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8642 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8644 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8647 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8648 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8650 for (int i = 0; i < 4; ++i) {
8651 LoBlendMask[i] = Mask[i];
8652 HiBlendMask[i] = Mask[i + 4];
8655 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8656 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8657 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8658 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8660 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8661 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8664 /// \brief Check whether a compaction lowering can be done by dropping even
8665 /// elements and compute how many times even elements must be dropped.
8667 /// This handles shuffles which take every Nth element where N is a power of
8668 /// two. Example shuffle masks:
8670 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8671 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8672 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8673 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8674 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8675 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8677 /// Any of these lanes can of course be undef.
8679 /// This routine only supports N <= 3.
8680 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8683 /// \returns N above, or the number of times even elements must be dropped if
8684 /// there is such a number. Otherwise returns zero.
8685 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8686 // Figure out whether we're looping over two inputs or just one.
8687 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8689 // The modulus for the shuffle vector entries is based on whether this is
8690 // a single input or not.
8691 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8692 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8693 "We should only be called with masks with a power-of-2 size!");
8695 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8697 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8698 // and 2^3 simultaneously. This is because we may have ambiguity with
8699 // partially undef inputs.
8700 bool ViableForN[3] = {true, true, true};
8702 for (int i = 0, e = Mask.size(); i < e; ++i) {
8703 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8708 bool IsAnyViable = false;
8709 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8710 if (ViableForN[j]) {
8713 // The shuffle mask must be equal to (i * 2^N) % M.
8714 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8717 ViableForN[j] = false;
8719 // Early exit if we exhaust the possible powers of two.
8724 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8728 // Return 0 as there is no viable power of two.
8732 /// \brief Generic lowering of v16i8 shuffles.
8734 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8735 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8736 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8737 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8739 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8740 const X86Subtarget *Subtarget,
8741 SelectionDAG &DAG) {
8743 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8744 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8745 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8746 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8747 ArrayRef<int> OrigMask = SVOp->getMask();
8748 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8750 // Try to use rotation instructions if available.
8751 if (Subtarget->hasSSSE3())
8752 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
8756 // Try to use a zext lowering.
8757 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8758 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
8761 int MaskStorage[16] = {
8762 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8763 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8764 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8765 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8766 MutableArrayRef<int> Mask(MaskStorage);
8767 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8768 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8771 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8773 // For single-input shuffles, there are some nicer lowering tricks we can use.
8774 if (NumV2Elements == 0) {
8775 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8776 // Notably, this handles splat and partial-splat shuffles more efficiently.
8777 // However, it only makes sense if the pre-duplication shuffle simplifies
8778 // things significantly. Currently, this means we need to be able to
8779 // express the pre-duplication shuffle as an i16 shuffle.
8781 // FIXME: We should check for other patterns which can be widened into an
8782 // i16 shuffle as well.
8783 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8784 for (int i = 0; i < 16; i += 2)
8785 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8790 auto tryToWidenViaDuplication = [&]() -> SDValue {
8791 if (!canWidenViaDuplication(Mask))
8793 SmallVector<int, 4> LoInputs;
8794 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8795 [](int M) { return M >= 0 && M < 8; });
8796 std::sort(LoInputs.begin(), LoInputs.end());
8797 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8799 SmallVector<int, 4> HiInputs;
8800 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8801 [](int M) { return M >= 8; });
8802 std::sort(HiInputs.begin(), HiInputs.end());
8803 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8806 bool TargetLo = LoInputs.size() >= HiInputs.size();
8807 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8808 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8810 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8811 SmallDenseMap<int, int, 8> LaneMap;
8812 for (int I : InPlaceInputs) {
8813 PreDupI16Shuffle[I/2] = I/2;
8816 int j = TargetLo ? 0 : 4, je = j + 4;
8817 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8818 // Check if j is already a shuffle of this input. This happens when
8819 // there are two adjacent bytes after we move the low one.
8820 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8821 // If we haven't yet mapped the input, search for a slot into which
8823 while (j < je && PreDupI16Shuffle[j] != -1)
8827 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8830 // Map this input with the i16 shuffle.
8831 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8834 // Update the lane map based on the mapping we ended up with.
8835 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8838 ISD::BITCAST, DL, MVT::v16i8,
8839 DAG.getVectorShuffle(MVT::v8i16, DL,
8840 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8841 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8843 // Unpack the bytes to form the i16s that will be shuffled into place.
8844 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8845 MVT::v16i8, V1, V1);
8847 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8848 for (int i = 0; i < 16; i += 2) {
8850 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8851 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8854 ISD::BITCAST, DL, MVT::v16i8,
8855 DAG.getVectorShuffle(MVT::v8i16, DL,
8856 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8857 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8859 if (SDValue V = tryToWidenViaDuplication())
8863 // Check whether an interleaving lowering is likely to be more efficient.
8864 // This isn't perfect but it is a strong heuristic that tends to work well on
8865 // the kinds of shuffles that show up in practice.
8867 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8868 if (shouldLowerAsInterleaving(Mask)) {
8869 // FIXME: Figure out whether we should pack these into the low or high
8872 int EMask[16], OMask[16];
8873 for (int i = 0; i < 8; ++i) {
8874 EMask[i] = Mask[2*i];
8875 OMask[i] = Mask[2*i + 1];
8880 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8881 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8883 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8886 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8887 // with PSHUFB. It is important to do this before we attempt to generate any
8888 // blends but after all of the single-input lowerings. If the single input
8889 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8890 // want to preserve that and we can DAG combine any longer sequences into
8891 // a PSHUFB in the end. But once we start blending from multiple inputs,
8892 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8893 // and there are *very* few patterns that would actually be faster than the
8894 // PSHUFB approach because of its ability to zero lanes.
8896 // FIXME: The only exceptions to the above are blends which are exact
8897 // interleavings with direct instructions supporting them. We currently don't
8898 // handle those well here.
8899 if (Subtarget->hasSSSE3()) {
8902 for (int i = 0; i < 16; ++i)
8903 if (Mask[i] == -1) {
8904 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8906 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
8908 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
8910 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
8911 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8912 if (isSingleInputShuffleMask(Mask))
8913 return V1; // Single inputs are easy.
8915 // Otherwise, blend the two.
8916 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
8917 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8918 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8921 // There are special ways we can lower some single-element blends.
8922 if (NumV2Elements == 1)
8923 if (SDValue V = lowerIntegerElementInsertionVectorShuffle(
8924 MVT::v16i8, DL, V1, V2, Mask, Subtarget, DAG))
8927 // Check whether a compaction lowering can be done. This handles shuffles
8928 // which take every Nth element for some even N. See the helper function for
8931 // We special case these as they can be particularly efficiently handled with
8932 // the PACKUSB instruction on x86 and they show up in common patterns of
8933 // rearranging bytes to truncate wide elements.
8934 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8935 // NumEvenDrops is the power of two stride of the elements. Another way of
8936 // thinking about it is that we need to drop the even elements this many
8937 // times to get the original input.
8938 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8940 // First we need to zero all the dropped bytes.
8941 assert(NumEvenDrops <= 3 &&
8942 "No support for dropping even elements more than 3 times.");
8943 // We use the mask type to pick which bytes are preserved based on how many
8944 // elements are dropped.
8945 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8946 SDValue ByteClearMask =
8947 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8948 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8949 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8951 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8953 // Now pack things back together.
8954 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8955 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8956 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8957 for (int i = 1; i < NumEvenDrops; ++i) {
8958 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8959 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8965 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8966 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8967 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8968 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8970 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
8971 MutableArrayRef<int> V1HalfBlendMask,
8972 MutableArrayRef<int> V2HalfBlendMask) {
8973 for (int i = 0; i < 8; ++i)
8974 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
8975 V1HalfBlendMask[i] = HalfMask[i];
8977 } else if (HalfMask[i] >= 16) {
8978 V2HalfBlendMask[i] = HalfMask[i] - 16;
8979 HalfMask[i] = i + 8;
8982 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
8983 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
8985 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8987 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
8988 MutableArrayRef<int> HiBlendMask) {
8990 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8991 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8993 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
8994 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8995 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
8996 [](int M) { return M >= 0 && M % 2 == 1; })) {
8997 // Use a mask to drop the high bytes.
8998 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8999 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9000 DAG.getConstant(0x00FF, MVT::v8i16));
9002 // This will be a single vector shuffle instead of a blend so nuke V2.
9003 V2 = DAG.getUNDEF(MVT::v8i16);
9005 // Squash the masks to point directly into V1.
9006 for (int &M : LoBlendMask)
9009 for (int &M : HiBlendMask)
9013 // Otherwise just unpack the low half of V into V1 and the high half into
9014 // V2 so that we can blend them as i16s.
9015 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9016 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9017 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9018 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9021 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9022 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9023 return std::make_pair(BlendedLo, BlendedHi);
9025 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9026 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9027 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9029 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9030 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9032 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9035 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9037 /// This routine breaks down the specific type of 128-bit shuffle and
9038 /// dispatches to the lowering routines accordingly.
9039 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9040 MVT VT, const X86Subtarget *Subtarget,
9041 SelectionDAG &DAG) {
9042 switch (VT.SimpleTy) {
9044 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9046 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9048 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9050 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9052 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9054 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9057 llvm_unreachable("Unimplemented!");
9061 static bool isHalfCrossingShuffleMask(ArrayRef<int> Mask) {
9062 int Size = Mask.size();
9063 for (int M : Mask.slice(0, Size / 2))
9064 if (M >= 0 && (M % Size) >= Size / 2)
9066 for (int M : Mask.slice(Size / 2, Size / 2))
9067 if (M >= 0 && (M % Size) < Size / 2)
9072 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9075 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9076 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9077 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9078 /// we encode the logic here for specific shuffle lowering routines to bail to
9079 /// when they exhaust the features avaible to more directly handle the shuffle.
9080 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
9082 const X86Subtarget *Subtarget,
9083 SelectionDAG &DAG) {
9085 MVT VT = Op.getSimpleValueType();
9086 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9087 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9088 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9089 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9090 ArrayRef<int> Mask = SVOp->getMask();
9092 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9093 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9095 int NumElements = VT.getVectorNumElements();
9096 int SplitNumElements = NumElements / 2;
9097 MVT ScalarVT = VT.getScalarType();
9098 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9100 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9101 DAG.getIntPtrConstant(0));
9102 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9103 DAG.getIntPtrConstant(SplitNumElements));
9104 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9105 DAG.getIntPtrConstant(0));
9106 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9107 DAG.getIntPtrConstant(SplitNumElements));
9109 // Now create two 4-way blends of these half-width vectors.
9110 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9111 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9112 for (int i = 0; i < SplitNumElements; ++i) {
9113 int M = HalfMask[i];
9114 if (M >= NumElements) {
9115 V2BlendMask.push_back(M - NumElements);
9116 V1BlendMask.push_back(-1);
9117 BlendMask.push_back(SplitNumElements + i);
9118 } else if (M >= 0) {
9119 V2BlendMask.push_back(-1);
9120 V1BlendMask.push_back(M);
9121 BlendMask.push_back(i);
9123 V2BlendMask.push_back(-1);
9124 V1BlendMask.push_back(-1);
9125 BlendMask.push_back(-1);
9128 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9129 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9130 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9132 SDValue Lo = HalfBlend(LoMask);
9133 SDValue Hi = HalfBlend(HiMask);
9134 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9137 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9139 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9140 /// isn't available.
9141 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9142 const X86Subtarget *Subtarget,
9143 SelectionDAG &DAG) {
9145 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9146 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9147 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9148 ArrayRef<int> Mask = SVOp->getMask();
9149 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9151 // FIXME: If we have AVX2, we should delegate to generic code as crossing
9152 // shuffles aren't a problem and FP and int have the same patterns.
9154 // FIXME: We can handle these more cleverly than splitting for v4f64.
9155 if (isHalfCrossingShuffleMask(Mask))
9156 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9158 if (isSingleInputShuffleMask(Mask)) {
9159 // Non-half-crossing single input shuffles can be lowerid with an
9160 // interleaved permutation.
9161 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9162 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9163 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f64, V1,
9164 DAG.getConstant(VPERMILPMask, MVT::i8));
9167 // X86 has dedicated unpack instructions that can handle specific blend
9168 // operations: UNPCKH and UNPCKL.
9169 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9170 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9171 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9172 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9173 // FIXME: It would be nice to find a way to get canonicalization to commute
9175 if (isShuffleEquivalent(Mask, 4, 0, 6, 2))
9176 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9177 if (isShuffleEquivalent(Mask, 5, 1, 7, 3))
9178 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9180 // Check if the blend happens to exactly fit that of SHUFPD.
9181 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
9182 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
9183 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9184 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9185 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9186 DAG.getConstant(SHUFPDMask, MVT::i8));
9188 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
9189 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
9190 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9191 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9192 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9193 DAG.getConstant(SHUFPDMask, MVT::i8));
9196 // Shuffle the input elements into the desired positions in V1 and V2 and
9197 // blend them together.
9198 int V1Mask[] = {-1, -1, -1, -1};
9199 int V2Mask[] = {-1, -1, -1, -1};
9200 for (int i = 0; i < 4; ++i)
9201 if (Mask[i] >= 0 && Mask[i] < 4)
9202 V1Mask[i] = Mask[i];
9203 else if (Mask[i] >= 4)
9204 V2Mask[i] = Mask[i] - 4;
9206 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
9207 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
9209 unsigned BlendMask = 0;
9210 for (int i = 0; i < 4; ++i)
9212 BlendMask |= 1 << i;
9214 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
9215 DAG.getConstant(BlendMask, MVT::i8));
9218 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9220 /// Largely delegates to common code when we have AVX2 and to the floating-point
9221 /// code when we only have AVX.
9222 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9223 const X86Subtarget *Subtarget,
9224 SelectionDAG &DAG) {
9226 assert(Op.getSimpleValueType() == MVT::v4i64 && "Bad shuffle type!");
9227 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9228 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9229 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9230 ArrayRef<int> Mask = SVOp->getMask();
9231 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9233 // FIXME: If we have AVX2, we should delegate to generic code as crossing
9234 // shuffles aren't a problem and FP and int have the same patterns.
9236 if (isHalfCrossingShuffleMask(Mask))
9237 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9239 // AVX1 doesn't provide any facilities for v4i64 shuffles, bitcast and
9240 // delegate to floating point code.
9241 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
9242 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
9243 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
9244 lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG));
9247 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9249 /// This routine either breaks down the specific type of a 256-bit x86 vector
9250 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9251 /// together based on the available instructions.
9252 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9253 MVT VT, const X86Subtarget *Subtarget,
9254 SelectionDAG &DAG) {
9255 switch (VT.SimpleTy) {
9257 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9259 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9264 // Fall back to the basic pattern of extracting the high half and forming
9266 // FIXME: Add targeted lowering for each type that can document rationale
9267 // for delegating to this when necessary.
9268 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9271 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9275 /// \brief Tiny helper function to test whether a shuffle mask could be
9276 /// simplified by widening the elements being shuffled.
9277 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9278 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9279 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9280 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9281 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9287 /// \brief Top-level lowering for x86 vector shuffles.
9289 /// This handles decomposition, canonicalization, and lowering of all x86
9290 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9291 /// above in helper routines. The canonicalization attempts to widen shuffles
9292 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9293 /// s.t. only one of the two inputs needs to be tested, etc.
9294 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9295 SelectionDAG &DAG) {
9296 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9297 ArrayRef<int> Mask = SVOp->getMask();
9298 SDValue V1 = Op.getOperand(0);
9299 SDValue V2 = Op.getOperand(1);
9300 MVT VT = Op.getSimpleValueType();
9301 int NumElements = VT.getVectorNumElements();
9304 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9306 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9307 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9308 if (V1IsUndef && V2IsUndef)
9309 return DAG.getUNDEF(VT);
9311 // When we create a shuffle node we put the UNDEF node to second operand,
9312 // but in some cases the first operand may be transformed to UNDEF.
9313 // In this case we should just commute the node.
9315 return DAG.getCommutedVectorShuffle(*SVOp);
9317 // Check for non-undef masks pointing at an undef vector and make the masks
9318 // undef as well. This makes it easier to match the shuffle based solely on
9322 if (M >= NumElements) {
9323 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9324 for (int &M : NewMask)
9325 if (M >= NumElements)
9327 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9330 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9331 // lanes but wider integers. We cap this to not form integers larger than i64
9332 // but it might be interesting to form i128 integers to handle flipping the
9333 // low and high halves of AVX 256-bit vectors.
9334 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9335 canWidenShuffleElements(Mask)) {
9336 SmallVector<int, 8> NewMask;
9337 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9338 NewMask.push_back(Mask[i] != -1
9340 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9342 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9343 VT.getVectorNumElements() / 2);
9344 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9345 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9346 return DAG.getNode(ISD::BITCAST, dl, VT,
9347 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9350 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9351 for (int M : SVOp->getMask())
9354 else if (M < NumElements)
9359 // Commute the shuffle as needed such that more elements come from V1 than
9360 // V2. This allows us to match the shuffle pattern strictly on how many
9361 // elements come from V1 without handling the symmetric cases.
9362 if (NumV2Elements > NumV1Elements)
9363 return DAG.getCommutedVectorShuffle(*SVOp);
9365 // When the number of V1 and V2 elements are the same, try to minimize the
9366 // number of uses of V2 in the low half of the vector.
9367 if (NumV1Elements == NumV2Elements) {
9368 int LowV1Elements = 0, LowV2Elements = 0;
9369 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9370 if (M >= NumElements)
9374 if (LowV2Elements > LowV1Elements)
9375 return DAG.getCommutedVectorShuffle(*SVOp);
9378 // For each vector width, delegate to a specialized lowering routine.
9379 if (VT.getSizeInBits() == 128)
9380 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9382 if (VT.getSizeInBits() == 256)
9383 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9385 llvm_unreachable("Unimplemented!");
9389 //===----------------------------------------------------------------------===//
9390 // Legacy vector shuffle lowering
9392 // This code is the legacy code handling vector shuffles until the above
9393 // replaces its functionality and performance.
9394 //===----------------------------------------------------------------------===//
9396 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9397 bool hasInt256, unsigned *MaskOut = nullptr) {
9398 MVT EltVT = VT.getVectorElementType();
9400 // There is no blend with immediate in AVX-512.
9401 if (VT.is512BitVector())
9404 if (!hasSSE41 || EltVT == MVT::i8)
9406 if (!hasInt256 && VT == MVT::v16i16)
9409 unsigned MaskValue = 0;
9410 unsigned NumElems = VT.getVectorNumElements();
9411 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9412 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9413 unsigned NumElemsInLane = NumElems / NumLanes;
9415 // Blend for v16i16 should be symetric for the both lanes.
9416 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9418 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9419 int EltIdx = MaskVals[i];
9421 if ((EltIdx < 0 || EltIdx == (int)i) &&
9422 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9425 if (((unsigned)EltIdx == (i + NumElems)) &&
9426 (SndLaneEltIdx < 0 ||
9427 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9428 MaskValue |= (1 << i);
9434 *MaskOut = MaskValue;
9438 // Try to lower a shuffle node into a simple blend instruction.
9439 // This function assumes isBlendMask returns true for this
9440 // SuffleVectorSDNode
9441 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9443 const X86Subtarget *Subtarget,
9444 SelectionDAG &DAG) {
9445 MVT VT = SVOp->getSimpleValueType(0);
9446 MVT EltVT = VT.getVectorElementType();
9447 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9448 Subtarget->hasInt256() && "Trying to lower a "
9449 "VECTOR_SHUFFLE to a Blend but "
9450 "with the wrong mask"));
9451 SDValue V1 = SVOp->getOperand(0);
9452 SDValue V2 = SVOp->getOperand(1);
9454 unsigned NumElems = VT.getVectorNumElements();
9456 // Convert i32 vectors to floating point if it is not AVX2.
9457 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9459 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9460 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9462 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
9463 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
9466 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
9467 DAG.getConstant(MaskValue, MVT::i32));
9468 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9471 /// In vector type \p VT, return true if the element at index \p InputIdx
9472 /// falls on a different 128-bit lane than \p OutputIdx.
9473 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
9474 unsigned OutputIdx) {
9475 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
9476 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
9479 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
9480 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
9481 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
9482 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
9484 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
9485 SelectionDAG &DAG) {
9486 MVT VT = V1.getSimpleValueType();
9487 assert(VT.is128BitVector() || VT.is256BitVector());
9489 MVT EltVT = VT.getVectorElementType();
9490 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
9491 unsigned NumElts = VT.getVectorNumElements();
9493 SmallVector<SDValue, 32> PshufbMask;
9494 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
9495 int InputIdx = MaskVals[OutputIdx];
9496 unsigned InputByteIdx;
9498 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
9499 InputByteIdx = 0x80;
9501 // Cross lane is not allowed.
9502 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
9504 InputByteIdx = InputIdx * EltSizeInBytes;
9505 // Index is an byte offset within the 128-bit lane.
9506 InputByteIdx &= 0xf;
9509 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
9510 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
9511 if (InputByteIdx != 0x80)
9516 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
9518 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
9519 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
9520 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
9523 // v8i16 shuffles - Prefer shuffles in the following order:
9524 // 1. [all] pshuflw, pshufhw, optional move
9525 // 2. [ssse3] 1 x pshufb
9526 // 3. [ssse3] 2 x pshufb + 1 x por
9527 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
9529 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
9530 SelectionDAG &DAG) {
9531 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9532 SDValue V1 = SVOp->getOperand(0);
9533 SDValue V2 = SVOp->getOperand(1);
9535 SmallVector<int, 8> MaskVals;
9537 // Determine if more than 1 of the words in each of the low and high quadwords
9538 // of the result come from the same quadword of one of the two inputs. Undef
9539 // mask values count as coming from any quadword, for better codegen.
9541 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
9542 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
9543 unsigned LoQuad[] = { 0, 0, 0, 0 };
9544 unsigned HiQuad[] = { 0, 0, 0, 0 };
9545 // Indices of quads used.
9546 std::bitset<4> InputQuads;
9547 for (unsigned i = 0; i < 8; ++i) {
9548 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
9549 int EltIdx = SVOp->getMaskElt(i);
9550 MaskVals.push_back(EltIdx);
9559 InputQuads.set(EltIdx / 4);
9562 int BestLoQuad = -1;
9563 unsigned MaxQuad = 1;
9564 for (unsigned i = 0; i < 4; ++i) {
9565 if (LoQuad[i] > MaxQuad) {
9567 MaxQuad = LoQuad[i];
9571 int BestHiQuad = -1;
9573 for (unsigned i = 0; i < 4; ++i) {
9574 if (HiQuad[i] > MaxQuad) {
9576 MaxQuad = HiQuad[i];
9580 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
9581 // of the two input vectors, shuffle them into one input vector so only a
9582 // single pshufb instruction is necessary. If there are more than 2 input
9583 // quads, disable the next transformation since it does not help SSSE3.
9584 bool V1Used = InputQuads[0] || InputQuads[1];
9585 bool V2Used = InputQuads[2] || InputQuads[3];
9586 if (Subtarget->hasSSSE3()) {
9587 if (InputQuads.count() == 2 && V1Used && V2Used) {
9588 BestLoQuad = InputQuads[0] ? 0 : 1;
9589 BestHiQuad = InputQuads[2] ? 2 : 3;
9591 if (InputQuads.count() > 2) {
9597 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
9598 // the shuffle mask. If a quad is scored as -1, that means that it contains
9599 // words from all 4 input quadwords.
9601 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
9603 BestLoQuad < 0 ? 0 : BestLoQuad,
9604 BestHiQuad < 0 ? 1 : BestHiQuad
9606 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
9607 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
9608 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
9609 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
9611 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
9612 // source words for the shuffle, to aid later transformations.
9613 bool AllWordsInNewV = true;
9614 bool InOrder[2] = { true, true };
9615 for (unsigned i = 0; i != 8; ++i) {
9616 int idx = MaskVals[i];
9618 InOrder[i/4] = false;
9619 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
9621 AllWordsInNewV = false;
9625 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
9626 if (AllWordsInNewV) {
9627 for (int i = 0; i != 8; ++i) {
9628 int idx = MaskVals[i];
9631 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
9632 if ((idx != i) && idx < 4)
9634 if ((idx != i) && idx > 3)
9643 // If we've eliminated the use of V2, and the new mask is a pshuflw or
9644 // pshufhw, that's as cheap as it gets. Return the new shuffle.
9645 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
9646 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
9647 unsigned TargetMask = 0;
9648 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
9649 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
9650 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9651 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
9652 getShufflePSHUFLWImmediate(SVOp);
9653 V1 = NewV.getOperand(0);
9654 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
9658 // Promote splats to a larger type which usually leads to more efficient code.
9659 // FIXME: Is this true if pshufb is available?
9660 if (SVOp->isSplat())
9661 return PromoteSplat(SVOp, DAG);
9663 // If we have SSSE3, and all words of the result are from 1 input vector,
9664 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
9665 // is present, fall back to case 4.
9666 if (Subtarget->hasSSSE3()) {
9667 SmallVector<SDValue,16> pshufbMask;
9669 // If we have elements from both input vectors, set the high bit of the
9670 // shuffle mask element to zero out elements that come from V2 in the V1
9671 // mask, and elements that come from V1 in the V2 mask, so that the two
9672 // results can be OR'd together.
9673 bool TwoInputs = V1Used && V2Used;
9674 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
9676 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9678 // Calculate the shuffle mask for the second input, shuffle it, and
9679 // OR it with the first shuffled input.
9680 CommuteVectorShuffleMask(MaskVals, 8);
9681 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
9682 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9683 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9686 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
9687 // and update MaskVals with new element order.
9688 std::bitset<8> InOrder;
9689 if (BestLoQuad >= 0) {
9690 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
9691 for (int i = 0; i != 4; ++i) {
9692 int idx = MaskVals[i];
9695 } else if ((idx / 4) == BestLoQuad) {
9700 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9703 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9704 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9705 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
9707 getShufflePSHUFLWImmediate(SVOp), DAG);
9711 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
9712 // and update MaskVals with the new element order.
9713 if (BestHiQuad >= 0) {
9714 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
9715 for (unsigned i = 4; i != 8; ++i) {
9716 int idx = MaskVals[i];
9719 } else if ((idx / 4) == BestHiQuad) {
9720 MaskV[i] = (idx & 3) + 4;
9724 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9727 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9728 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9729 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
9731 getShufflePSHUFHWImmediate(SVOp), DAG);
9735 // In case BestHi & BestLo were both -1, which means each quadword has a word
9736 // from each of the four input quadwords, calculate the InOrder bitvector now
9737 // before falling through to the insert/extract cleanup.
9738 if (BestLoQuad == -1 && BestHiQuad == -1) {
9740 for (int i = 0; i != 8; ++i)
9741 if (MaskVals[i] < 0 || MaskVals[i] == i)
9745 // The other elements are put in the right place using pextrw and pinsrw.
9746 for (unsigned i = 0; i != 8; ++i) {
9749 int EltIdx = MaskVals[i];
9752 SDValue ExtOp = (EltIdx < 8) ?
9753 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
9754 DAG.getIntPtrConstant(EltIdx)) :
9755 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
9756 DAG.getIntPtrConstant(EltIdx - 8));
9757 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
9758 DAG.getIntPtrConstant(i));
9763 /// \brief v16i16 shuffles
9765 /// FIXME: We only support generation of a single pshufb currently. We can
9766 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
9767 /// well (e.g 2 x pshufb + 1 x por).
9769 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
9770 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9771 SDValue V1 = SVOp->getOperand(0);
9772 SDValue V2 = SVOp->getOperand(1);
9775 if (V2.getOpcode() != ISD::UNDEF)
9778 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9779 return getPSHUFB(MaskVals, V1, dl, DAG);
9782 // v16i8 shuffles - Prefer shuffles in the following order:
9783 // 1. [ssse3] 1 x pshufb
9784 // 2. [ssse3] 2 x pshufb + 1 x por
9785 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
9786 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
9787 const X86Subtarget* Subtarget,
9788 SelectionDAG &DAG) {
9789 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9790 SDValue V1 = SVOp->getOperand(0);
9791 SDValue V2 = SVOp->getOperand(1);
9793 ArrayRef<int> MaskVals = SVOp->getMask();
9795 // Promote splats to a larger type which usually leads to more efficient code.
9796 // FIXME: Is this true if pshufb is available?
9797 if (SVOp->isSplat())
9798 return PromoteSplat(SVOp, DAG);
9800 // If we have SSSE3, case 1 is generated when all result bytes come from
9801 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
9802 // present, fall back to case 3.
9804 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
9805 if (Subtarget->hasSSSE3()) {
9806 SmallVector<SDValue,16> pshufbMask;
9808 // If all result elements are from one input vector, then only translate
9809 // undef mask values to 0x80 (zero out result) in the pshufb mask.
9811 // Otherwise, we have elements from both input vectors, and must zero out
9812 // elements that come from V2 in the first mask, and V1 in the second mask
9813 // so that we can OR them together.
9814 for (unsigned i = 0; i != 16; ++i) {
9815 int EltIdx = MaskVals[i];
9816 if (EltIdx < 0 || EltIdx >= 16)
9818 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9820 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
9821 DAG.getNode(ISD::BUILD_VECTOR, dl,
9822 MVT::v16i8, pshufbMask));
9824 // As PSHUFB will zero elements with negative indices, it's safe to ignore
9825 // the 2nd operand if it's undefined or zero.
9826 if (V2.getOpcode() == ISD::UNDEF ||
9827 ISD::isBuildVectorAllZeros(V2.getNode()))
9830 // Calculate the shuffle mask for the second input, shuffle it, and
9831 // OR it with the first shuffled input.
9833 for (unsigned i = 0; i != 16; ++i) {
9834 int EltIdx = MaskVals[i];
9835 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
9836 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9838 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
9839 DAG.getNode(ISD::BUILD_VECTOR, dl,
9840 MVT::v16i8, pshufbMask));
9841 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9844 // No SSSE3 - Calculate in place words and then fix all out of place words
9845 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
9846 // the 16 different words that comprise the two doublequadword input vectors.
9847 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9848 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
9850 for (int i = 0; i != 8; ++i) {
9851 int Elt0 = MaskVals[i*2];
9852 int Elt1 = MaskVals[i*2+1];
9854 // This word of the result is all undef, skip it.
9855 if (Elt0 < 0 && Elt1 < 0)
9858 // This word of the result is already in the correct place, skip it.
9859 if ((Elt0 == i*2) && (Elt1 == i*2+1))
9862 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
9863 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
9866 // If Elt0 and Elt1 are defined, are consecutive, and can be load
9867 // using a single extract together, load it and store it.
9868 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
9869 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9870 DAG.getIntPtrConstant(Elt1 / 2));
9871 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9872 DAG.getIntPtrConstant(i));
9876 // If Elt1 is defined, extract it from the appropriate source. If the
9877 // source byte is not also odd, shift the extracted word left 8 bits
9878 // otherwise clear the bottom 8 bits if we need to do an or.
9880 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9881 DAG.getIntPtrConstant(Elt1 / 2));
9882 if ((Elt1 & 1) == 0)
9883 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
9885 TLI.getShiftAmountTy(InsElt.getValueType())));
9887 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
9888 DAG.getConstant(0xFF00, MVT::i16));
9890 // If Elt0 is defined, extract it from the appropriate source. If the
9891 // source byte is not also even, shift the extracted word right 8 bits. If
9892 // Elt1 was also defined, OR the extracted values together before
9893 // inserting them in the result.
9895 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
9896 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
9897 if ((Elt0 & 1) != 0)
9898 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
9900 TLI.getShiftAmountTy(InsElt0.getValueType())));
9902 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
9903 DAG.getConstant(0x00FF, MVT::i16));
9904 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
9907 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9908 DAG.getIntPtrConstant(i));
9910 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
9913 // v32i8 shuffles - Translate to VPSHUFB if possible.
9915 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
9916 const X86Subtarget *Subtarget,
9917 SelectionDAG &DAG) {
9918 MVT VT = SVOp->getSimpleValueType(0);
9919 SDValue V1 = SVOp->getOperand(0);
9920 SDValue V2 = SVOp->getOperand(1);
9922 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9924 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9925 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
9926 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
9928 // VPSHUFB may be generated if
9929 // (1) one of input vector is undefined or zeroinitializer.
9930 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
9931 // And (2) the mask indexes don't cross the 128-bit lane.
9932 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
9933 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
9936 if (V1IsAllZero && !V2IsAllZero) {
9937 CommuteVectorShuffleMask(MaskVals, 32);
9940 return getPSHUFB(MaskVals, V1, dl, DAG);
9943 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
9944 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
9945 /// done when every pair / quad of shuffle mask elements point to elements in
9946 /// the right sequence. e.g.
9947 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
9949 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
9950 SelectionDAG &DAG) {
9951 MVT VT = SVOp->getSimpleValueType(0);
9953 unsigned NumElems = VT.getVectorNumElements();
9956 switch (VT.SimpleTy) {
9957 default: llvm_unreachable("Unexpected!");
9960 return SDValue(SVOp, 0);
9961 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
9962 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
9963 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
9964 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
9965 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
9966 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
9969 SmallVector<int, 8> MaskVec;
9970 for (unsigned i = 0; i != NumElems; i += Scale) {
9972 for (unsigned j = 0; j != Scale; ++j) {
9973 int EltIdx = SVOp->getMaskElt(i+j);
9977 StartIdx = (EltIdx / Scale);
9978 if (EltIdx != (int)(StartIdx*Scale + j))
9981 MaskVec.push_back(StartIdx);
9984 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
9985 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
9986 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
9989 /// getVZextMovL - Return a zero-extending vector move low node.
9991 static SDValue getVZextMovL(MVT VT, MVT OpVT,
9992 SDValue SrcOp, SelectionDAG &DAG,
9993 const X86Subtarget *Subtarget, SDLoc dl) {
9994 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
9995 LoadSDNode *LD = nullptr;
9996 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
9997 LD = dyn_cast<LoadSDNode>(SrcOp);
9999 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10001 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10002 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10003 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10004 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10005 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10007 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10008 return DAG.getNode(ISD::BITCAST, dl, VT,
10009 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10010 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10012 SrcOp.getOperand(0)
10018 return DAG.getNode(ISD::BITCAST, dl, VT,
10019 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10020 DAG.getNode(ISD::BITCAST, dl,
10024 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10025 /// which could not be matched by any known target speficic shuffle
10027 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10029 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10030 if (NewOp.getNode())
10033 MVT VT = SVOp->getSimpleValueType(0);
10035 unsigned NumElems = VT.getVectorNumElements();
10036 unsigned NumLaneElems = NumElems / 2;
10039 MVT EltVT = VT.getVectorElementType();
10040 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10043 SmallVector<int, 16> Mask;
10044 for (unsigned l = 0; l < 2; ++l) {
10045 // Build a shuffle mask for the output, discovering on the fly which
10046 // input vectors to use as shuffle operands (recorded in InputUsed).
10047 // If building a suitable shuffle vector proves too hard, then bail
10048 // out with UseBuildVector set.
10049 bool UseBuildVector = false;
10050 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10051 unsigned LaneStart = l * NumLaneElems;
10052 for (unsigned i = 0; i != NumLaneElems; ++i) {
10053 // The mask element. This indexes into the input.
10054 int Idx = SVOp->getMaskElt(i+LaneStart);
10056 // the mask element does not index into any input vector.
10057 Mask.push_back(-1);
10061 // The input vector this mask element indexes into.
10062 int Input = Idx / NumLaneElems;
10064 // Turn the index into an offset from the start of the input vector.
10065 Idx -= Input * NumLaneElems;
10067 // Find or create a shuffle vector operand to hold this input.
10069 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10070 if (InputUsed[OpNo] == Input)
10071 // This input vector is already an operand.
10073 if (InputUsed[OpNo] < 0) {
10074 // Create a new operand for this input vector.
10075 InputUsed[OpNo] = Input;
10080 if (OpNo >= array_lengthof(InputUsed)) {
10081 // More than two input vectors used! Give up on trying to create a
10082 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10083 UseBuildVector = true;
10087 // Add the mask index for the new shuffle vector.
10088 Mask.push_back(Idx + OpNo * NumLaneElems);
10091 if (UseBuildVector) {
10092 SmallVector<SDValue, 16> SVOps;
10093 for (unsigned i = 0; i != NumLaneElems; ++i) {
10094 // The mask element. This indexes into the input.
10095 int Idx = SVOp->getMaskElt(i+LaneStart);
10097 SVOps.push_back(DAG.getUNDEF(EltVT));
10101 // The input vector this mask element indexes into.
10102 int Input = Idx / NumElems;
10104 // Turn the index into an offset from the start of the input vector.
10105 Idx -= Input * NumElems;
10107 // Extract the vector element by hand.
10108 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10109 SVOp->getOperand(Input),
10110 DAG.getIntPtrConstant(Idx)));
10113 // Construct the output using a BUILD_VECTOR.
10114 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10115 } else if (InputUsed[0] < 0) {
10116 // No input vectors were used! The result is undefined.
10117 Output[l] = DAG.getUNDEF(NVT);
10119 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10120 (InputUsed[0] % 2) * NumLaneElems,
10122 // If only one input was used, use an undefined vector for the other.
10123 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10124 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10125 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10126 // At least one input vector was used. Create a new shuffle vector.
10127 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10133 // Concatenate the result back
10134 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10137 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10138 /// 4 elements, and match them with several different shuffle types.
10140 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10141 SDValue V1 = SVOp->getOperand(0);
10142 SDValue V2 = SVOp->getOperand(1);
10144 MVT VT = SVOp->getSimpleValueType(0);
10146 assert(VT.is128BitVector() && "Unsupported vector size");
10148 std::pair<int, int> Locs[4];
10149 int Mask1[] = { -1, -1, -1, -1 };
10150 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10152 unsigned NumHi = 0;
10153 unsigned NumLo = 0;
10154 for (unsigned i = 0; i != 4; ++i) {
10155 int Idx = PermMask[i];
10157 Locs[i] = std::make_pair(-1, -1);
10159 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10161 Locs[i] = std::make_pair(0, NumLo);
10162 Mask1[NumLo] = Idx;
10165 Locs[i] = std::make_pair(1, NumHi);
10167 Mask1[2+NumHi] = Idx;
10173 if (NumLo <= 2 && NumHi <= 2) {
10174 // If no more than two elements come from either vector. This can be
10175 // implemented with two shuffles. First shuffle gather the elements.
10176 // The second shuffle, which takes the first shuffle as both of its
10177 // vector operands, put the elements into the right order.
10178 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10180 int Mask2[] = { -1, -1, -1, -1 };
10182 for (unsigned i = 0; i != 4; ++i)
10183 if (Locs[i].first != -1) {
10184 unsigned Idx = (i < 2) ? 0 : 4;
10185 Idx += Locs[i].first * 2 + Locs[i].second;
10189 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10192 if (NumLo == 3 || NumHi == 3) {
10193 // Otherwise, we must have three elements from one vector, call it X, and
10194 // one element from the other, call it Y. First, use a shufps to build an
10195 // intermediate vector with the one element from Y and the element from X
10196 // that will be in the same half in the final destination (the indexes don't
10197 // matter). Then, use a shufps to build the final vector, taking the half
10198 // containing the element from Y from the intermediate, and the other half
10201 // Normalize it so the 3 elements come from V1.
10202 CommuteVectorShuffleMask(PermMask, 4);
10206 // Find the element from V2.
10208 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10209 int Val = PermMask[HiIndex];
10216 Mask1[0] = PermMask[HiIndex];
10218 Mask1[2] = PermMask[HiIndex^1];
10220 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10222 if (HiIndex >= 2) {
10223 Mask1[0] = PermMask[0];
10224 Mask1[1] = PermMask[1];
10225 Mask1[2] = HiIndex & 1 ? 6 : 4;
10226 Mask1[3] = HiIndex & 1 ? 4 : 6;
10227 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10230 Mask1[0] = HiIndex & 1 ? 2 : 0;
10231 Mask1[1] = HiIndex & 1 ? 0 : 2;
10232 Mask1[2] = PermMask[2];
10233 Mask1[3] = PermMask[3];
10238 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10241 // Break it into (shuffle shuffle_hi, shuffle_lo).
10242 int LoMask[] = { -1, -1, -1, -1 };
10243 int HiMask[] = { -1, -1, -1, -1 };
10245 int *MaskPtr = LoMask;
10246 unsigned MaskIdx = 0;
10247 unsigned LoIdx = 0;
10248 unsigned HiIdx = 2;
10249 for (unsigned i = 0; i != 4; ++i) {
10256 int Idx = PermMask[i];
10258 Locs[i] = std::make_pair(-1, -1);
10259 } else if (Idx < 4) {
10260 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10261 MaskPtr[LoIdx] = Idx;
10264 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10265 MaskPtr[HiIdx] = Idx;
10270 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10271 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10272 int MaskOps[] = { -1, -1, -1, -1 };
10273 for (unsigned i = 0; i != 4; ++i)
10274 if (Locs[i].first != -1)
10275 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10276 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10279 static bool MayFoldVectorLoad(SDValue V) {
10280 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10281 V = V.getOperand(0);
10283 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10284 V = V.getOperand(0);
10285 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10286 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10287 // BUILD_VECTOR (load), undef
10288 V = V.getOperand(0);
10290 return MayFoldLoad(V);
10294 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10295 MVT VT = Op.getSimpleValueType();
10297 // Canonizalize to v2f64.
10298 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10299 return DAG.getNode(ISD::BITCAST, dl, VT,
10300 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10305 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10307 SDValue V1 = Op.getOperand(0);
10308 SDValue V2 = Op.getOperand(1);
10309 MVT VT = Op.getSimpleValueType();
10311 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10313 if (HasSSE2 && VT == MVT::v2f64)
10314 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10316 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10317 return DAG.getNode(ISD::BITCAST, dl, VT,
10318 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10319 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10320 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10324 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10325 SDValue V1 = Op.getOperand(0);
10326 SDValue V2 = Op.getOperand(1);
10327 MVT VT = Op.getSimpleValueType();
10329 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10330 "unsupported shuffle type");
10332 if (V2.getOpcode() == ISD::UNDEF)
10336 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10340 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10341 SDValue V1 = Op.getOperand(0);
10342 SDValue V2 = Op.getOperand(1);
10343 MVT VT = Op.getSimpleValueType();
10344 unsigned NumElems = VT.getVectorNumElements();
10346 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10347 // operand of these instructions is only memory, so check if there's a
10348 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10350 bool CanFoldLoad = false;
10352 // Trivial case, when V2 comes from a load.
10353 if (MayFoldVectorLoad(V2))
10354 CanFoldLoad = true;
10356 // When V1 is a load, it can be folded later into a store in isel, example:
10357 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10359 // (MOVLPSmr addr:$src1, VR128:$src2)
10360 // So, recognize this potential and also use MOVLPS or MOVLPD
10361 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10362 CanFoldLoad = true;
10364 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10366 if (HasSSE2 && NumElems == 2)
10367 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10370 // If we don't care about the second element, proceed to use movss.
10371 if (SVOp->getMaskElt(1) != -1)
10372 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10375 // movl and movlp will both match v2i64, but v2i64 is never matched by
10376 // movl earlier because we make it strict to avoid messing with the movlp load
10377 // folding logic (see the code above getMOVLP call). Match it here then,
10378 // this is horrible, but will stay like this until we move all shuffle
10379 // matching to x86 specific nodes. Note that for the 1st condition all
10380 // types are matched with movsd.
10382 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10383 // as to remove this logic from here, as much as possible
10384 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10385 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10386 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10389 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10391 // Invert the operand order and use SHUFPS to match it.
10392 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10393 getShuffleSHUFImmediate(SVOp), DAG);
10396 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10397 SelectionDAG &DAG) {
10399 MVT VT = Load->getSimpleValueType(0);
10400 MVT EVT = VT.getVectorElementType();
10401 SDValue Addr = Load->getOperand(1);
10402 SDValue NewAddr = DAG.getNode(
10403 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10404 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10407 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10408 DAG.getMachineFunction().getMachineMemOperand(
10409 Load->getMemOperand(), 0, EVT.getStoreSize()));
10413 // It is only safe to call this function if isINSERTPSMask is true for
10414 // this shufflevector mask.
10415 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10416 SelectionDAG &DAG) {
10417 // Generate an insertps instruction when inserting an f32 from memory onto a
10418 // v4f32 or when copying a member from one v4f32 to another.
10419 // We also use it for transferring i32 from one register to another,
10420 // since it simply copies the same bits.
10421 // If we're transferring an i32 from memory to a specific element in a
10422 // register, we output a generic DAG that will match the PINSRD
10424 MVT VT = SVOp->getSimpleValueType(0);
10425 MVT EVT = VT.getVectorElementType();
10426 SDValue V1 = SVOp->getOperand(0);
10427 SDValue V2 = SVOp->getOperand(1);
10428 auto Mask = SVOp->getMask();
10429 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10430 "unsupported vector type for insertps/pinsrd");
10432 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10433 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10434 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10438 unsigned DestIndex;
10442 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10445 // If we have 1 element from each vector, we have to check if we're
10446 // changing V1's element's place. If so, we're done. Otherwise, we
10447 // should assume we're changing V2's element's place and behave
10449 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10450 assert(DestIndex <= INT32_MAX && "truncated destination index");
10451 if (FromV1 == FromV2 &&
10452 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
10456 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10459 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
10460 "More than one element from V1 and from V2, or no elements from one "
10461 "of the vectors. This case should not have returned true from "
10466 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10469 // Get an index into the source vector in the range [0,4) (the mask is
10470 // in the range [0,8) because it can address V1 and V2)
10471 unsigned SrcIndex = Mask[DestIndex] % 4;
10472 if (MayFoldLoad(From)) {
10473 // Trivial case, when From comes from a load and is only used by the
10474 // shuffle. Make it use insertps from the vector that we need from that
10477 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
10478 if (!NewLoad.getNode())
10481 if (EVT == MVT::f32) {
10482 // Create this as a scalar to vector to match the instruction pattern.
10483 SDValue LoadScalarToVector =
10484 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
10485 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
10486 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
10488 } else { // EVT == MVT::i32
10489 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
10490 // instruction, to match the PINSRD instruction, which loads an i32 to a
10491 // certain vector element.
10492 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
10493 DAG.getConstant(DestIndex, MVT::i32));
10497 // Vector-element-to-vector
10498 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
10499 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
10502 // Reduce a vector shuffle to zext.
10503 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
10504 SelectionDAG &DAG) {
10505 // PMOVZX is only available from SSE41.
10506 if (!Subtarget->hasSSE41())
10509 MVT VT = Op.getSimpleValueType();
10511 // Only AVX2 support 256-bit vector integer extending.
10512 if (!Subtarget->hasInt256() && VT.is256BitVector())
10515 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10517 SDValue V1 = Op.getOperand(0);
10518 SDValue V2 = Op.getOperand(1);
10519 unsigned NumElems = VT.getVectorNumElements();
10521 // Extending is an unary operation and the element type of the source vector
10522 // won't be equal to or larger than i64.
10523 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
10524 VT.getVectorElementType() == MVT::i64)
10527 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
10528 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
10529 while ((1U << Shift) < NumElems) {
10530 if (SVOp->getMaskElt(1U << Shift) == 1)
10533 // The maximal ratio is 8, i.e. from i8 to i64.
10538 // Check the shuffle mask.
10539 unsigned Mask = (1U << Shift) - 1;
10540 for (unsigned i = 0; i != NumElems; ++i) {
10541 int EltIdx = SVOp->getMaskElt(i);
10542 if ((i & Mask) != 0 && EltIdx != -1)
10544 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
10548 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
10549 MVT NeVT = MVT::getIntegerVT(NBits);
10550 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
10552 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
10555 // Simplify the operand as it's prepared to be fed into shuffle.
10556 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
10557 if (V1.getOpcode() == ISD::BITCAST &&
10558 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
10559 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
10560 V1.getOperand(0).getOperand(0)
10561 .getSimpleValueType().getSizeInBits() == SignificantBits) {
10562 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
10563 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
10564 ConstantSDNode *CIdx =
10565 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
10566 // If it's foldable, i.e. normal load with single use, we will let code
10567 // selection to fold it. Otherwise, we will short the conversion sequence.
10568 if (CIdx && CIdx->getZExtValue() == 0 &&
10569 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
10570 MVT FullVT = V.getSimpleValueType();
10571 MVT V1VT = V1.getSimpleValueType();
10572 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
10573 // The "ext_vec_elt" node is wider than the result node.
10574 // In this case we should extract subvector from V.
10575 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
10576 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
10577 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
10578 FullVT.getVectorNumElements()/Ratio);
10579 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
10580 DAG.getIntPtrConstant(0));
10582 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
10586 return DAG.getNode(ISD::BITCAST, DL, VT,
10587 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
10590 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10591 SelectionDAG &DAG) {
10592 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10593 MVT VT = Op.getSimpleValueType();
10595 SDValue V1 = Op.getOperand(0);
10596 SDValue V2 = Op.getOperand(1);
10598 if (isZeroShuffle(SVOp))
10599 return getZeroVector(VT, Subtarget, DAG, dl);
10601 // Handle splat operations
10602 if (SVOp->isSplat()) {
10603 // Use vbroadcast whenever the splat comes from a foldable load
10604 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
10605 if (Broadcast.getNode())
10609 // Check integer expanding shuffles.
10610 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
10611 if (NewOp.getNode())
10614 // If the shuffle can be profitably rewritten as a narrower shuffle, then
10616 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
10617 VT == MVT::v32i8) {
10618 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10619 if (NewOp.getNode())
10620 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
10621 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
10622 // FIXME: Figure out a cleaner way to do this.
10623 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
10624 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10625 if (NewOp.getNode()) {
10626 MVT NewVT = NewOp.getSimpleValueType();
10627 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
10628 NewVT, true, false))
10629 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
10632 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
10633 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10634 if (NewOp.getNode()) {
10635 MVT NewVT = NewOp.getSimpleValueType();
10636 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
10637 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
10646 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
10647 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10648 SDValue V1 = Op.getOperand(0);
10649 SDValue V2 = Op.getOperand(1);
10650 MVT VT = Op.getSimpleValueType();
10652 unsigned NumElems = VT.getVectorNumElements();
10653 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10654 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10655 bool V1IsSplat = false;
10656 bool V2IsSplat = false;
10657 bool HasSSE2 = Subtarget->hasSSE2();
10658 bool HasFp256 = Subtarget->hasFp256();
10659 bool HasInt256 = Subtarget->hasInt256();
10660 MachineFunction &MF = DAG.getMachineFunction();
10661 bool OptForSize = MF.getFunction()->getAttributes().
10662 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
10664 // Check if we should use the experimental vector shuffle lowering. If so,
10665 // delegate completely to that code path.
10666 if (ExperimentalVectorShuffleLowering)
10667 return lowerVectorShuffle(Op, Subtarget, DAG);
10669 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10671 if (V1IsUndef && V2IsUndef)
10672 return DAG.getUNDEF(VT);
10674 // When we create a shuffle node we put the UNDEF node to second operand,
10675 // but in some cases the first operand may be transformed to UNDEF.
10676 // In this case we should just commute the node.
10678 return DAG.getCommutedVectorShuffle(*SVOp);
10680 // Vector shuffle lowering takes 3 steps:
10682 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
10683 // narrowing and commutation of operands should be handled.
10684 // 2) Matching of shuffles with known shuffle masks to x86 target specific
10686 // 3) Rewriting of unmatched masks into new generic shuffle operations,
10687 // so the shuffle can be broken into other shuffles and the legalizer can
10688 // try the lowering again.
10690 // The general idea is that no vector_shuffle operation should be left to
10691 // be matched during isel, all of them must be converted to a target specific
10694 // Normalize the input vectors. Here splats, zeroed vectors, profitable
10695 // narrowing and commutation of operands should be handled. The actual code
10696 // doesn't include all of those, work in progress...
10697 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
10698 if (NewOp.getNode())
10701 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
10703 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
10704 // unpckh_undef). Only use pshufd if speed is more important than size.
10705 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10706 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10707 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10708 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10710 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
10711 V2IsUndef && MayFoldVectorLoad(V1))
10712 return getMOVDDup(Op, dl, V1, DAG);
10714 if (isMOVHLPS_v_undef_Mask(M, VT))
10715 return getMOVHighToLow(Op, dl, DAG);
10717 // Use to match splats
10718 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
10719 (VT == MVT::v2f64 || VT == MVT::v2i64))
10720 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10722 if (isPSHUFDMask(M, VT)) {
10723 // The actual implementation will match the mask in the if above and then
10724 // during isel it can match several different instructions, not only pshufd
10725 // as its name says, sad but true, emulate the behavior for now...
10726 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
10727 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
10729 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
10731 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
10732 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
10734 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
10735 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
10738 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
10742 if (isPALIGNRMask(M, VT, Subtarget))
10743 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
10744 getShufflePALIGNRImmediate(SVOp),
10747 if (isVALIGNMask(M, VT, Subtarget))
10748 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
10749 getShuffleVALIGNImmediate(SVOp),
10752 // Check if this can be converted into a logical shift.
10753 bool isLeft = false;
10754 unsigned ShAmt = 0;
10756 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
10757 if (isShift && ShVal.hasOneUse()) {
10758 // If the shifted value has multiple uses, it may be cheaper to use
10759 // v_set0 + movlhps or movhlps, etc.
10760 MVT EltVT = VT.getVectorElementType();
10761 ShAmt *= EltVT.getSizeInBits();
10762 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10765 if (isMOVLMask(M, VT)) {
10766 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10767 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
10768 if (!isMOVLPMask(M, VT)) {
10769 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
10770 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10772 if (VT == MVT::v4i32 || VT == MVT::v4f32)
10773 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10777 // FIXME: fold these into legal mask.
10778 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
10779 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
10781 if (isMOVHLPSMask(M, VT))
10782 return getMOVHighToLow(Op, dl, DAG);
10784 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
10785 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
10787 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
10788 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
10790 if (isMOVLPMask(M, VT))
10791 return getMOVLP(Op, dl, DAG, HasSSE2);
10793 if (ShouldXformToMOVHLPS(M, VT) ||
10794 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
10795 return DAG.getCommutedVectorShuffle(*SVOp);
10798 // No better options. Use a vshldq / vsrldq.
10799 MVT EltVT = VT.getVectorElementType();
10800 ShAmt *= EltVT.getSizeInBits();
10801 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10804 bool Commuted = false;
10805 // FIXME: This should also accept a bitcast of a splat? Be careful, not
10806 // 1,1,1,1 -> v8i16 though.
10807 BitVector UndefElements;
10808 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
10809 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10811 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
10812 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10815 // Canonicalize the splat or undef, if present, to be on the RHS.
10816 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
10817 CommuteVectorShuffleMask(M, NumElems);
10819 std::swap(V1IsSplat, V2IsSplat);
10823 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
10824 // Shuffling low element of v1 into undef, just return v1.
10827 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
10828 // the instruction selector will not match, so get a canonical MOVL with
10829 // swapped operands to undo the commute.
10830 return getMOVL(DAG, dl, VT, V2, V1);
10833 if (isUNPCKLMask(M, VT, HasInt256))
10834 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10836 if (isUNPCKHMask(M, VT, HasInt256))
10837 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10840 // Normalize mask so all entries that point to V2 points to its first
10841 // element then try to match unpck{h|l} again. If match, return a
10842 // new vector_shuffle with the corrected mask.p
10843 SmallVector<int, 8> NewMask(M.begin(), M.end());
10844 NormalizeMask(NewMask, NumElems);
10845 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
10846 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10847 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
10848 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10852 // Commute is back and try unpck* again.
10853 // FIXME: this seems wrong.
10854 CommuteVectorShuffleMask(M, NumElems);
10856 std::swap(V1IsSplat, V2IsSplat);
10858 if (isUNPCKLMask(M, VT, HasInt256))
10859 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10861 if (isUNPCKHMask(M, VT, HasInt256))
10862 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10865 // Normalize the node to match x86 shuffle ops if needed
10866 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
10867 return DAG.getCommutedVectorShuffle(*SVOp);
10869 // The checks below are all present in isShuffleMaskLegal, but they are
10870 // inlined here right now to enable us to directly emit target specific
10871 // nodes, and remove one by one until they don't return Op anymore.
10873 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
10874 SVOp->getSplatIndex() == 0 && V2IsUndef) {
10875 if (VT == MVT::v2f64 || VT == MVT::v2i64)
10876 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10879 if (isPSHUFHWMask(M, VT, HasInt256))
10880 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
10881 getShufflePSHUFHWImmediate(SVOp),
10884 if (isPSHUFLWMask(M, VT, HasInt256))
10885 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
10886 getShufflePSHUFLWImmediate(SVOp),
10889 unsigned MaskValue;
10890 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
10892 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
10894 if (isSHUFPMask(M, VT))
10895 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
10896 getShuffleSHUFImmediate(SVOp), DAG);
10898 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10899 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10900 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10901 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10903 //===--------------------------------------------------------------------===//
10904 // Generate target specific nodes for 128 or 256-bit shuffles only
10905 // supported in the AVX instruction set.
10908 // Handle VMOVDDUPY permutations
10909 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
10910 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
10912 // Handle VPERMILPS/D* permutations
10913 if (isVPERMILPMask(M, VT)) {
10914 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
10915 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
10916 getShuffleSHUFImmediate(SVOp), DAG);
10917 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
10918 getShuffleSHUFImmediate(SVOp), DAG);
10922 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
10923 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
10924 Idx*(NumElems/2), DAG, dl);
10926 // Handle VPERM2F128/VPERM2I128 permutations
10927 if (isVPERM2X128Mask(M, VT, HasFp256))
10928 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
10929 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
10931 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
10932 return getINSERTPS(SVOp, dl, DAG);
10935 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
10936 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
10938 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
10939 VT.is512BitVector()) {
10940 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
10941 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
10942 SmallVector<SDValue, 16> permclMask;
10943 for (unsigned i = 0; i != NumElems; ++i) {
10944 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
10947 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
10949 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
10950 return DAG.getNode(X86ISD::VPERMV, dl, VT,
10951 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
10952 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
10953 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
10956 //===--------------------------------------------------------------------===//
10957 // Since no target specific shuffle was selected for this generic one,
10958 // lower it into other known shuffles. FIXME: this isn't true yet, but
10959 // this is the plan.
10962 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
10963 if (VT == MVT::v8i16) {
10964 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
10965 if (NewOp.getNode())
10969 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
10970 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
10971 if (NewOp.getNode())
10975 if (VT == MVT::v16i8) {
10976 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
10977 if (NewOp.getNode())
10981 if (VT == MVT::v32i8) {
10982 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
10983 if (NewOp.getNode())
10987 // Handle all 128-bit wide vectors with 4 elements, and match them with
10988 // several different shuffle types.
10989 if (NumElems == 4 && VT.is128BitVector())
10990 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
10992 // Handle general 256-bit shuffles
10993 if (VT.is256BitVector())
10994 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
10999 // This function assumes its argument is a BUILD_VECTOR of constants or
11000 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11002 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11003 unsigned &MaskValue) {
11005 unsigned NumElems = BuildVector->getNumOperands();
11006 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11007 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11008 unsigned NumElemsInLane = NumElems / NumLanes;
11010 // Blend for v16i16 should be symetric for the both lanes.
11011 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11012 SDValue EltCond = BuildVector->getOperand(i);
11013 SDValue SndLaneEltCond =
11014 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11016 int Lane1Cond = -1, Lane2Cond = -1;
11017 if (isa<ConstantSDNode>(EltCond))
11018 Lane1Cond = !isZero(EltCond);
11019 if (isa<ConstantSDNode>(SndLaneEltCond))
11020 Lane2Cond = !isZero(SndLaneEltCond);
11022 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11023 // Lane1Cond != 0, means we want the first argument.
11024 // Lane1Cond == 0, means we want the second argument.
11025 // The encoding of this argument is 0 for the first argument, 1
11026 // for the second. Therefore, invert the condition.
11027 MaskValue |= !Lane1Cond << i;
11028 else if (Lane1Cond < 0)
11029 MaskValue |= !Lane2Cond << i;
11036 // Try to lower a vselect node into a simple blend instruction.
11037 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11038 SelectionDAG &DAG) {
11039 SDValue Cond = Op.getOperand(0);
11040 SDValue LHS = Op.getOperand(1);
11041 SDValue RHS = Op.getOperand(2);
11043 MVT VT = Op.getSimpleValueType();
11044 MVT EltVT = VT.getVectorElementType();
11045 unsigned NumElems = VT.getVectorNumElements();
11047 // There is no blend with immediate in AVX-512.
11048 if (VT.is512BitVector())
11051 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11053 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11056 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11059 // Check the mask for BLEND and build the value.
11060 unsigned MaskValue = 0;
11061 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11064 // Convert i32 vectors to floating point if it is not AVX2.
11065 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11067 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11068 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11070 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11071 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11074 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11075 DAG.getConstant(MaskValue, MVT::i32));
11076 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11079 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11080 // A vselect where all conditions and data are constants can be optimized into
11081 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11082 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11083 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11084 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11087 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11088 if (BlendOp.getNode())
11091 // Some types for vselect were previously set to Expand, not Legal or
11092 // Custom. Return an empty SDValue so we fall-through to Expand, after
11093 // the Custom lowering phase.
11094 MVT VT = Op.getSimpleValueType();
11095 switch (VT.SimpleTy) {
11100 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11105 // We couldn't create a "Blend with immediate" node.
11106 // This node should still be legal, but we'll have to emit a blendv*
11111 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11112 MVT VT = Op.getSimpleValueType();
11115 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11118 if (VT.getSizeInBits() == 8) {
11119 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11120 Op.getOperand(0), Op.getOperand(1));
11121 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11122 DAG.getValueType(VT));
11123 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11126 if (VT.getSizeInBits() == 16) {
11127 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11128 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11130 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11131 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11132 DAG.getNode(ISD::BITCAST, dl,
11135 Op.getOperand(1)));
11136 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11137 Op.getOperand(0), Op.getOperand(1));
11138 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11139 DAG.getValueType(VT));
11140 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11143 if (VT == MVT::f32) {
11144 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11145 // the result back to FR32 register. It's only worth matching if the
11146 // result has a single use which is a store or a bitcast to i32. And in
11147 // the case of a store, it's not worth it if the index is a constant 0,
11148 // because a MOVSSmr can be used instead, which is smaller and faster.
11149 if (!Op.hasOneUse())
11151 SDNode *User = *Op.getNode()->use_begin();
11152 if ((User->getOpcode() != ISD::STORE ||
11153 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11154 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11155 (User->getOpcode() != ISD::BITCAST ||
11156 User->getValueType(0) != MVT::i32))
11158 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11159 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11162 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11165 if (VT == MVT::i32 || VT == MVT::i64) {
11166 // ExtractPS/pextrq works with constant index.
11167 if (isa<ConstantSDNode>(Op.getOperand(1)))
11173 /// Extract one bit from mask vector, like v16i1 or v8i1.
11174 /// AVX-512 feature.
11176 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11177 SDValue Vec = Op.getOperand(0);
11179 MVT VecVT = Vec.getSimpleValueType();
11180 SDValue Idx = Op.getOperand(1);
11181 MVT EltVT = Op.getSimpleValueType();
11183 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11185 // variable index can't be handled in mask registers,
11186 // extend vector to VR512
11187 if (!isa<ConstantSDNode>(Idx)) {
11188 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11189 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11190 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11191 ExtVT.getVectorElementType(), Ext, Idx);
11192 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11195 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11196 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11197 unsigned MaxSift = rc->getSize()*8 - 1;
11198 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11199 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11200 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11201 DAG.getConstant(MaxSift, MVT::i8));
11202 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11203 DAG.getIntPtrConstant(0));
11207 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11208 SelectionDAG &DAG) const {
11210 SDValue Vec = Op.getOperand(0);
11211 MVT VecVT = Vec.getSimpleValueType();
11212 SDValue Idx = Op.getOperand(1);
11214 if (Op.getSimpleValueType() == MVT::i1)
11215 return ExtractBitFromMaskVector(Op, DAG);
11217 if (!isa<ConstantSDNode>(Idx)) {
11218 if (VecVT.is512BitVector() ||
11219 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11220 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11223 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11224 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11225 MaskEltVT.getSizeInBits());
11227 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11228 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11229 getZeroVector(MaskVT, Subtarget, DAG, dl),
11230 Idx, DAG.getConstant(0, getPointerTy()));
11231 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11232 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11233 Perm, DAG.getConstant(0, getPointerTy()));
11238 // If this is a 256-bit vector result, first extract the 128-bit vector and
11239 // then extract the element from the 128-bit vector.
11240 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11242 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11243 // Get the 128-bit vector.
11244 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11245 MVT EltVT = VecVT.getVectorElementType();
11247 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11249 //if (IdxVal >= NumElems/2)
11250 // IdxVal -= NumElems/2;
11251 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11252 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11253 DAG.getConstant(IdxVal, MVT::i32));
11256 assert(VecVT.is128BitVector() && "Unexpected vector length");
11258 if (Subtarget->hasSSE41()) {
11259 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11264 MVT VT = Op.getSimpleValueType();
11265 // TODO: handle v16i8.
11266 if (VT.getSizeInBits() == 16) {
11267 SDValue Vec = Op.getOperand(0);
11268 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11270 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11271 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11272 DAG.getNode(ISD::BITCAST, dl,
11274 Op.getOperand(1)));
11275 // Transform it so it match pextrw which produces a 32-bit result.
11276 MVT EltVT = MVT::i32;
11277 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11278 Op.getOperand(0), Op.getOperand(1));
11279 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11280 DAG.getValueType(VT));
11281 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11284 if (VT.getSizeInBits() == 32) {
11285 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11289 // SHUFPS the element to the lowest double word, then movss.
11290 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11291 MVT VVT = Op.getOperand(0).getSimpleValueType();
11292 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11293 DAG.getUNDEF(VVT), Mask);
11294 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11295 DAG.getIntPtrConstant(0));
11298 if (VT.getSizeInBits() == 64) {
11299 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11300 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11301 // to match extract_elt for f64.
11302 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11306 // UNPCKHPD the element to the lowest double word, then movsd.
11307 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11308 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11309 int Mask[2] = { 1, -1 };
11310 MVT VVT = Op.getOperand(0).getSimpleValueType();
11311 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11312 DAG.getUNDEF(VVT), Mask);
11313 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11314 DAG.getIntPtrConstant(0));
11320 /// Insert one bit to mask vector, like v16i1 or v8i1.
11321 /// AVX-512 feature.
11323 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11325 SDValue Vec = Op.getOperand(0);
11326 SDValue Elt = Op.getOperand(1);
11327 SDValue Idx = Op.getOperand(2);
11328 MVT VecVT = Vec.getSimpleValueType();
11330 if (!isa<ConstantSDNode>(Idx)) {
11331 // Non constant index. Extend source and destination,
11332 // insert element and then truncate the result.
11333 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11334 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11335 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11336 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11337 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11338 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11341 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11342 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11343 if (Vec.getOpcode() == ISD::UNDEF)
11344 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11345 DAG.getConstant(IdxVal, MVT::i8));
11346 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11347 unsigned MaxSift = rc->getSize()*8 - 1;
11348 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11349 DAG.getConstant(MaxSift, MVT::i8));
11350 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11351 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11352 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11355 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11356 SelectionDAG &DAG) const {
11357 MVT VT = Op.getSimpleValueType();
11358 MVT EltVT = VT.getVectorElementType();
11360 if (EltVT == MVT::i1)
11361 return InsertBitToMaskVector(Op, DAG);
11364 SDValue N0 = Op.getOperand(0);
11365 SDValue N1 = Op.getOperand(1);
11366 SDValue N2 = Op.getOperand(2);
11367 if (!isa<ConstantSDNode>(N2))
11369 auto *N2C = cast<ConstantSDNode>(N2);
11370 unsigned IdxVal = N2C->getZExtValue();
11372 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11373 // into that, and then insert the subvector back into the result.
11374 if (VT.is256BitVector() || VT.is512BitVector()) {
11375 // Get the desired 128-bit vector half.
11376 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11378 // Insert the element into the desired half.
11379 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11380 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11382 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11383 DAG.getConstant(IdxIn128, MVT::i32));
11385 // Insert the changed part back to the 256-bit vector
11386 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11388 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11390 if (Subtarget->hasSSE41()) {
11391 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11393 if (VT == MVT::v8i16) {
11394 Opc = X86ISD::PINSRW;
11396 assert(VT == MVT::v16i8);
11397 Opc = X86ISD::PINSRB;
11400 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11402 if (N1.getValueType() != MVT::i32)
11403 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11404 if (N2.getValueType() != MVT::i32)
11405 N2 = DAG.getIntPtrConstant(IdxVal);
11406 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11409 if (EltVT == MVT::f32) {
11410 // Bits [7:6] of the constant are the source select. This will always be
11411 // zero here. The DAG Combiner may combine an extract_elt index into
11413 // bits. For example (insert (extract, 3), 2) could be matched by
11415 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11416 // Bits [5:4] of the constant are the destination select. This is the
11417 // value of the incoming immediate.
11418 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11419 // combine either bitwise AND or insert of float 0.0 to set these bits.
11420 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11421 // Create this as a scalar to vector..
11422 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11423 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11426 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11427 // PINSR* works with constant index.
11432 if (EltVT == MVT::i8)
11435 if (EltVT.getSizeInBits() == 16) {
11436 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11437 // as its second argument.
11438 if (N1.getValueType() != MVT::i32)
11439 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11440 if (N2.getValueType() != MVT::i32)
11441 N2 = DAG.getIntPtrConstant(IdxVal);
11442 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11447 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11449 MVT OpVT = Op.getSimpleValueType();
11451 // If this is a 256-bit vector result, first insert into a 128-bit
11452 // vector and then insert into the 256-bit vector.
11453 if (!OpVT.is128BitVector()) {
11454 // Insert into a 128-bit vector.
11455 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11456 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11457 OpVT.getVectorNumElements() / SizeFactor);
11459 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11461 // Insert the 128-bit vector.
11462 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11465 if (OpVT == MVT::v1i64 &&
11466 Op.getOperand(0).getValueType() == MVT::i64)
11467 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11469 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11470 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11471 return DAG.getNode(ISD::BITCAST, dl, OpVT,
11472 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
11475 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11476 // a simple subregister reference or explicit instructions to grab
11477 // upper bits of a vector.
11478 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11479 SelectionDAG &DAG) {
11481 SDValue In = Op.getOperand(0);
11482 SDValue Idx = Op.getOperand(1);
11483 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11484 MVT ResVT = Op.getSimpleValueType();
11485 MVT InVT = In.getSimpleValueType();
11487 if (Subtarget->hasFp256()) {
11488 if (ResVT.is128BitVector() &&
11489 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11490 isa<ConstantSDNode>(Idx)) {
11491 return Extract128BitVector(In, IdxVal, DAG, dl);
11493 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11494 isa<ConstantSDNode>(Idx)) {
11495 return Extract256BitVector(In, IdxVal, DAG, dl);
11501 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11502 // simple superregister reference or explicit instructions to insert
11503 // the upper bits of a vector.
11504 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11505 SelectionDAG &DAG) {
11506 if (Subtarget->hasFp256()) {
11507 SDLoc dl(Op.getNode());
11508 SDValue Vec = Op.getNode()->getOperand(0);
11509 SDValue SubVec = Op.getNode()->getOperand(1);
11510 SDValue Idx = Op.getNode()->getOperand(2);
11512 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
11513 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
11514 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
11515 isa<ConstantSDNode>(Idx)) {
11516 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11517 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11520 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
11521 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
11522 isa<ConstantSDNode>(Idx)) {
11523 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11524 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11530 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11531 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11532 // one of the above mentioned nodes. It has to be wrapped because otherwise
11533 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11534 // be used to form addressing mode. These wrapped nodes will be selected
11537 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11538 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11540 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11541 // global base reg.
11542 unsigned char OpFlag = 0;
11543 unsigned WrapperKind = X86ISD::Wrapper;
11544 CodeModel::Model M = DAG.getTarget().getCodeModel();
11546 if (Subtarget->isPICStyleRIPRel() &&
11547 (M == CodeModel::Small || M == CodeModel::Kernel))
11548 WrapperKind = X86ISD::WrapperRIP;
11549 else if (Subtarget->isPICStyleGOT())
11550 OpFlag = X86II::MO_GOTOFF;
11551 else if (Subtarget->isPICStyleStubPIC())
11552 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11554 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11555 CP->getAlignment(),
11556 CP->getOffset(), OpFlag);
11558 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11559 // With PIC, the address is actually $g + Offset.
11561 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11562 DAG.getNode(X86ISD::GlobalBaseReg,
11563 SDLoc(), getPointerTy()),
11570 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11571 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11573 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11574 // global base reg.
11575 unsigned char OpFlag = 0;
11576 unsigned WrapperKind = X86ISD::Wrapper;
11577 CodeModel::Model M = DAG.getTarget().getCodeModel();
11579 if (Subtarget->isPICStyleRIPRel() &&
11580 (M == CodeModel::Small || M == CodeModel::Kernel))
11581 WrapperKind = X86ISD::WrapperRIP;
11582 else if (Subtarget->isPICStyleGOT())
11583 OpFlag = X86II::MO_GOTOFF;
11584 else if (Subtarget->isPICStyleStubPIC())
11585 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11587 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11590 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11592 // With PIC, the address is actually $g + Offset.
11594 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11595 DAG.getNode(X86ISD::GlobalBaseReg,
11596 SDLoc(), getPointerTy()),
11603 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11604 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11606 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11607 // global base reg.
11608 unsigned char OpFlag = 0;
11609 unsigned WrapperKind = X86ISD::Wrapper;
11610 CodeModel::Model M = DAG.getTarget().getCodeModel();
11612 if (Subtarget->isPICStyleRIPRel() &&
11613 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11614 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11615 OpFlag = X86II::MO_GOTPCREL;
11616 WrapperKind = X86ISD::WrapperRIP;
11617 } else if (Subtarget->isPICStyleGOT()) {
11618 OpFlag = X86II::MO_GOT;
11619 } else if (Subtarget->isPICStyleStubPIC()) {
11620 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11621 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11622 OpFlag = X86II::MO_DARWIN_NONLAZY;
11625 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11628 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11630 // With PIC, the address is actually $g + Offset.
11631 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11632 !Subtarget->is64Bit()) {
11633 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11634 DAG.getNode(X86ISD::GlobalBaseReg,
11635 SDLoc(), getPointerTy()),
11639 // For symbols that require a load from a stub to get the address, emit the
11641 if (isGlobalStubReference(OpFlag))
11642 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11643 MachinePointerInfo::getGOT(), false, false, false, 0);
11649 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11650 // Create the TargetBlockAddressAddress node.
11651 unsigned char OpFlags =
11652 Subtarget->ClassifyBlockAddressReference();
11653 CodeModel::Model M = DAG.getTarget().getCodeModel();
11654 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11655 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11657 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11660 if (Subtarget->isPICStyleRIPRel() &&
11661 (M == CodeModel::Small || M == CodeModel::Kernel))
11662 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11664 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11666 // With PIC, the address is actually $g + Offset.
11667 if (isGlobalRelativeToPICBase(OpFlags)) {
11668 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11669 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11677 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11678 int64_t Offset, SelectionDAG &DAG) const {
11679 // Create the TargetGlobalAddress node, folding in the constant
11680 // offset if it is legal.
11681 unsigned char OpFlags =
11682 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11683 CodeModel::Model M = DAG.getTarget().getCodeModel();
11685 if (OpFlags == X86II::MO_NO_FLAG &&
11686 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11687 // A direct static reference to a global.
11688 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11691 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11694 if (Subtarget->isPICStyleRIPRel() &&
11695 (M == CodeModel::Small || M == CodeModel::Kernel))
11696 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11698 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11700 // With PIC, the address is actually $g + Offset.
11701 if (isGlobalRelativeToPICBase(OpFlags)) {
11702 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11703 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11707 // For globals that require a load from a stub to get the address, emit the
11709 if (isGlobalStubReference(OpFlags))
11710 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11711 MachinePointerInfo::getGOT(), false, false, false, 0);
11713 // If there was a non-zero offset that we didn't fold, create an explicit
11714 // addition for it.
11716 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11717 DAG.getConstant(Offset, getPointerTy()));
11723 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11724 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11725 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11726 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11730 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11731 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11732 unsigned char OperandFlags, bool LocalDynamic = false) {
11733 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11734 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11736 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11737 GA->getValueType(0),
11741 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11745 SDValue Ops[] = { Chain, TGA, *InFlag };
11746 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11748 SDValue Ops[] = { Chain, TGA };
11749 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11752 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11753 MFI->setAdjustsStack(true);
11755 SDValue Flag = Chain.getValue(1);
11756 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11759 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11761 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11764 SDLoc dl(GA); // ? function entry point might be better
11765 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11766 DAG.getNode(X86ISD::GlobalBaseReg,
11767 SDLoc(), PtrVT), InFlag);
11768 InFlag = Chain.getValue(1);
11770 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11773 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11775 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11777 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11778 X86::RAX, X86II::MO_TLSGD);
11781 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11787 // Get the start address of the TLS block for this module.
11788 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11789 .getInfo<X86MachineFunctionInfo>();
11790 MFI->incNumLocalDynamicTLSAccesses();
11794 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11795 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11798 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11799 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11800 InFlag = Chain.getValue(1);
11801 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11802 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11805 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11809 unsigned char OperandFlags = X86II::MO_DTPOFF;
11810 unsigned WrapperKind = X86ISD::Wrapper;
11811 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11812 GA->getValueType(0),
11813 GA->getOffset(), OperandFlags);
11814 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11816 // Add x@dtpoff with the base.
11817 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11820 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11821 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11822 const EVT PtrVT, TLSModel::Model model,
11823 bool is64Bit, bool isPIC) {
11826 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11827 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11828 is64Bit ? 257 : 256));
11830 SDValue ThreadPointer =
11831 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
11832 MachinePointerInfo(Ptr), false, false, false, 0);
11834 unsigned char OperandFlags = 0;
11835 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11837 unsigned WrapperKind = X86ISD::Wrapper;
11838 if (model == TLSModel::LocalExec) {
11839 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11840 } else if (model == TLSModel::InitialExec) {
11842 OperandFlags = X86II::MO_GOTTPOFF;
11843 WrapperKind = X86ISD::WrapperRIP;
11845 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11848 llvm_unreachable("Unexpected model");
11851 // emit "addl x@ntpoff,%eax" (local exec)
11852 // or "addl x@indntpoff,%eax" (initial exec)
11853 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11855 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11856 GA->getOffset(), OperandFlags);
11857 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11859 if (model == TLSModel::InitialExec) {
11860 if (isPIC && !is64Bit) {
11861 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11862 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11866 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11867 MachinePointerInfo::getGOT(), false, false, false, 0);
11870 // The address of the thread local variable is the add of the thread
11871 // pointer with the offset of the variable.
11872 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11876 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11878 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11879 const GlobalValue *GV = GA->getGlobal();
11881 if (Subtarget->isTargetELF()) {
11882 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11885 case TLSModel::GeneralDynamic:
11886 if (Subtarget->is64Bit())
11887 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11888 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11889 case TLSModel::LocalDynamic:
11890 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11891 Subtarget->is64Bit());
11892 case TLSModel::InitialExec:
11893 case TLSModel::LocalExec:
11894 return LowerToTLSExecModel(
11895 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11896 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11898 llvm_unreachable("Unknown TLS model.");
11901 if (Subtarget->isTargetDarwin()) {
11902 // Darwin only has one model of TLS. Lower to that.
11903 unsigned char OpFlag = 0;
11904 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11905 X86ISD::WrapperRIP : X86ISD::Wrapper;
11907 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11908 // global base reg.
11909 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11910 !Subtarget->is64Bit();
11912 OpFlag = X86II::MO_TLVP_PIC_BASE;
11914 OpFlag = X86II::MO_TLVP;
11916 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11917 GA->getValueType(0),
11918 GA->getOffset(), OpFlag);
11919 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11921 // With PIC32, the address is actually $g + Offset.
11923 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11924 DAG.getNode(X86ISD::GlobalBaseReg,
11925 SDLoc(), getPointerTy()),
11928 // Lowering the machine isd will make sure everything is in the right
11930 SDValue Chain = DAG.getEntryNode();
11931 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11932 SDValue Args[] = { Chain, Offset };
11933 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11935 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11936 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11937 MFI->setAdjustsStack(true);
11939 // And our return value (tls address) is in the standard call return value
11941 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11942 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11943 Chain.getValue(1));
11946 if (Subtarget->isTargetKnownWindowsMSVC() ||
11947 Subtarget->isTargetWindowsGNU()) {
11948 // Just use the implicit TLS architecture
11949 // Need to generate someting similar to:
11950 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11952 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11953 // mov rcx, qword [rdx+rcx*8]
11954 // mov eax, .tls$:tlsvar
11955 // [rax+rcx] contains the address
11956 // Windows 64bit: gs:0x58
11957 // Windows 32bit: fs:__tls_array
11960 SDValue Chain = DAG.getEntryNode();
11962 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11963 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11964 // use its literal value of 0x2C.
11965 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11966 ? Type::getInt8PtrTy(*DAG.getContext(),
11968 : Type::getInt32PtrTy(*DAG.getContext(),
11972 Subtarget->is64Bit()
11973 ? DAG.getIntPtrConstant(0x58)
11974 : (Subtarget->isTargetWindowsGNU()
11975 ? DAG.getIntPtrConstant(0x2C)
11976 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11978 SDValue ThreadPointer =
11979 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11980 MachinePointerInfo(Ptr), false, false, false, 0);
11982 // Load the _tls_index variable
11983 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11984 if (Subtarget->is64Bit())
11985 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11986 IDX, MachinePointerInfo(), MVT::i32,
11987 false, false, false, 0);
11989 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11990 false, false, false, 0);
11992 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
11994 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11996 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11997 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11998 false, false, false, 0);
12000 // Get the offset of start of .tls section
12001 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12002 GA->getValueType(0),
12003 GA->getOffset(), X86II::MO_SECREL);
12004 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12006 // The address of the thread local variable is the add of the thread
12007 // pointer with the offset of the variable.
12008 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12011 llvm_unreachable("TLS not implemented for this target.");
12014 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12015 /// and take a 2 x i32 value to shift plus a shift amount.
12016 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12017 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12018 MVT VT = Op.getSimpleValueType();
12019 unsigned VTBits = VT.getSizeInBits();
12021 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12022 SDValue ShOpLo = Op.getOperand(0);
12023 SDValue ShOpHi = Op.getOperand(1);
12024 SDValue ShAmt = Op.getOperand(2);
12025 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12026 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12028 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12029 DAG.getConstant(VTBits - 1, MVT::i8));
12030 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12031 DAG.getConstant(VTBits - 1, MVT::i8))
12032 : DAG.getConstant(0, VT);
12034 SDValue Tmp2, Tmp3;
12035 if (Op.getOpcode() == ISD::SHL_PARTS) {
12036 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12037 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12039 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12040 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12043 // If the shift amount is larger or equal than the width of a part we can't
12044 // rely on the results of shld/shrd. Insert a test and select the appropriate
12045 // values for large shift amounts.
12046 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12047 DAG.getConstant(VTBits, MVT::i8));
12048 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12049 AndNode, DAG.getConstant(0, MVT::i8));
12052 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12053 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12054 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12056 if (Op.getOpcode() == ISD::SHL_PARTS) {
12057 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12058 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12060 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12061 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12064 SDValue Ops[2] = { Lo, Hi };
12065 return DAG.getMergeValues(Ops, dl);
12068 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12069 SelectionDAG &DAG) const {
12070 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12072 if (SrcVT.isVector())
12075 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12076 "Unknown SINT_TO_FP to lower!");
12078 // These are really Legal; return the operand so the caller accepts it as
12080 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12082 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12083 Subtarget->is64Bit()) {
12088 unsigned Size = SrcVT.getSizeInBits()/8;
12089 MachineFunction &MF = DAG.getMachineFunction();
12090 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12091 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12092 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12094 MachinePointerInfo::getFixedStack(SSFI),
12096 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12099 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12101 SelectionDAG &DAG) const {
12105 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12107 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12109 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12111 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12113 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12114 MachineMemOperand *MMO;
12116 int SSFI = FI->getIndex();
12118 DAG.getMachineFunction()
12119 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12120 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12122 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12123 StackSlot = StackSlot.getOperand(1);
12125 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12126 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12128 Tys, Ops, SrcVT, MMO);
12131 Chain = Result.getValue(1);
12132 SDValue InFlag = Result.getValue(2);
12134 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12135 // shouldn't be necessary except that RFP cannot be live across
12136 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12137 MachineFunction &MF = DAG.getMachineFunction();
12138 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12139 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12140 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12141 Tys = DAG.getVTList(MVT::Other);
12143 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12145 MachineMemOperand *MMO =
12146 DAG.getMachineFunction()
12147 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12148 MachineMemOperand::MOStore, SSFISize, SSFISize);
12150 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12151 Ops, Op.getValueType(), MMO);
12152 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12153 MachinePointerInfo::getFixedStack(SSFI),
12154 false, false, false, 0);
12160 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12161 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12162 SelectionDAG &DAG) const {
12163 // This algorithm is not obvious. Here it is what we're trying to output:
12166 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12167 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12169 haddpd %xmm0, %xmm0
12171 pshufd $0x4e, %xmm0, %xmm1
12177 LLVMContext *Context = DAG.getContext();
12179 // Build some magic constants.
12180 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12181 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12182 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12184 SmallVector<Constant*,2> CV1;
12186 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12187 APInt(64, 0x4330000000000000ULL))));
12189 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12190 APInt(64, 0x4530000000000000ULL))));
12191 Constant *C1 = ConstantVector::get(CV1);
12192 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12194 // Load the 64-bit value into an XMM register.
12195 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12197 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12198 MachinePointerInfo::getConstantPool(),
12199 false, false, false, 16);
12200 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12201 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12204 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12205 MachinePointerInfo::getConstantPool(),
12206 false, false, false, 16);
12207 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12208 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12211 if (Subtarget->hasSSE3()) {
12212 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12213 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12215 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12216 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12218 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12219 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12223 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12224 DAG.getIntPtrConstant(0));
12227 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12228 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12229 SelectionDAG &DAG) const {
12231 // FP constant to bias correct the final result.
12232 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12235 // Load the 32-bit value into an XMM register.
12236 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12239 // Zero out the upper parts of the register.
12240 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12242 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12243 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12244 DAG.getIntPtrConstant(0));
12246 // Or the load with the bias.
12247 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12248 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12249 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12250 MVT::v2f64, Load)),
12251 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12252 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12253 MVT::v2f64, Bias)));
12254 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12255 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12256 DAG.getIntPtrConstant(0));
12258 // Subtract the bias.
12259 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12261 // Handle final rounding.
12262 EVT DestVT = Op.getValueType();
12264 if (DestVT.bitsLT(MVT::f64))
12265 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12266 DAG.getIntPtrConstant(0));
12267 if (DestVT.bitsGT(MVT::f64))
12268 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12270 // Handle final rounding.
12274 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12275 SelectionDAG &DAG) const {
12276 SDValue N0 = Op.getOperand(0);
12277 MVT SVT = N0.getSimpleValueType();
12280 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12281 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12282 "Custom UINT_TO_FP is not supported!");
12284 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12285 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12286 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12289 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12290 SelectionDAG &DAG) const {
12291 SDValue N0 = Op.getOperand(0);
12294 if (Op.getValueType().isVector())
12295 return lowerUINT_TO_FP_vec(Op, DAG);
12297 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12298 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12299 // the optimization here.
12300 if (DAG.SignBitIsZero(N0))
12301 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12303 MVT SrcVT = N0.getSimpleValueType();
12304 MVT DstVT = Op.getSimpleValueType();
12305 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12306 return LowerUINT_TO_FP_i64(Op, DAG);
12307 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12308 return LowerUINT_TO_FP_i32(Op, DAG);
12309 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12312 // Make a 64-bit buffer, and use it to build an FILD.
12313 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12314 if (SrcVT == MVT::i32) {
12315 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12316 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12317 getPointerTy(), StackSlot, WordOff);
12318 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12319 StackSlot, MachinePointerInfo(),
12321 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12322 OffsetSlot, MachinePointerInfo(),
12324 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12328 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12329 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12330 StackSlot, MachinePointerInfo(),
12332 // For i64 source, we need to add the appropriate power of 2 if the input
12333 // was negative. This is the same as the optimization in
12334 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12335 // we must be careful to do the computation in x87 extended precision, not
12336 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12337 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12338 MachineMemOperand *MMO =
12339 DAG.getMachineFunction()
12340 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12341 MachineMemOperand::MOLoad, 8, 8);
12343 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12344 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12345 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12348 APInt FF(32, 0x5F800000ULL);
12350 // Check whether the sign bit is set.
12351 SDValue SignSet = DAG.getSetCC(dl,
12352 getSetCCResultType(*DAG.getContext(), MVT::i64),
12353 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12356 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12357 SDValue FudgePtr = DAG.getConstantPool(
12358 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12361 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12362 SDValue Zero = DAG.getIntPtrConstant(0);
12363 SDValue Four = DAG.getIntPtrConstant(4);
12364 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12366 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12368 // Load the value out, extending it from f32 to f80.
12369 // FIXME: Avoid the extend by constructing the right constant pool?
12370 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12371 FudgePtr, MachinePointerInfo::getConstantPool(),
12372 MVT::f32, false, false, false, 4);
12373 // Extend everything to 80 bits to force it to be done on x87.
12374 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12375 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12378 std::pair<SDValue,SDValue>
12379 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12380 bool IsSigned, bool IsReplace) const {
12383 EVT DstTy = Op.getValueType();
12385 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12386 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12390 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12391 DstTy.getSimpleVT() >= MVT::i16 &&
12392 "Unknown FP_TO_INT to lower!");
12394 // These are really Legal.
12395 if (DstTy == MVT::i32 &&
12396 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12397 return std::make_pair(SDValue(), SDValue());
12398 if (Subtarget->is64Bit() &&
12399 DstTy == MVT::i64 &&
12400 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12401 return std::make_pair(SDValue(), SDValue());
12403 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12404 // stack slot, or into the FTOL runtime function.
12405 MachineFunction &MF = DAG.getMachineFunction();
12406 unsigned MemSize = DstTy.getSizeInBits()/8;
12407 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12408 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12411 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12412 Opc = X86ISD::WIN_FTOL;
12414 switch (DstTy.getSimpleVT().SimpleTy) {
12415 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12416 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12417 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12418 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12421 SDValue Chain = DAG.getEntryNode();
12422 SDValue Value = Op.getOperand(0);
12423 EVT TheVT = Op.getOperand(0).getValueType();
12424 // FIXME This causes a redundant load/store if the SSE-class value is already
12425 // in memory, such as if it is on the callstack.
12426 if (isScalarFPTypeInSSEReg(TheVT)) {
12427 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12428 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12429 MachinePointerInfo::getFixedStack(SSFI),
12431 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12433 Chain, StackSlot, DAG.getValueType(TheVT)
12436 MachineMemOperand *MMO =
12437 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12438 MachineMemOperand::MOLoad, MemSize, MemSize);
12439 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12440 Chain = Value.getValue(1);
12441 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12442 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12445 MachineMemOperand *MMO =
12446 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12447 MachineMemOperand::MOStore, MemSize, MemSize);
12449 if (Opc != X86ISD::WIN_FTOL) {
12450 // Build the FP_TO_INT*_IN_MEM
12451 SDValue Ops[] = { Chain, Value, StackSlot };
12452 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12454 return std::make_pair(FIST, StackSlot);
12456 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12457 DAG.getVTList(MVT::Other, MVT::Glue),
12459 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12460 MVT::i32, ftol.getValue(1));
12461 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12462 MVT::i32, eax.getValue(2));
12463 SDValue Ops[] = { eax, edx };
12464 SDValue pair = IsReplace
12465 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12466 : DAG.getMergeValues(Ops, DL);
12467 return std::make_pair(pair, SDValue());
12471 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12472 const X86Subtarget *Subtarget) {
12473 MVT VT = Op->getSimpleValueType(0);
12474 SDValue In = Op->getOperand(0);
12475 MVT InVT = In.getSimpleValueType();
12478 // Optimize vectors in AVX mode:
12481 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12482 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12483 // Concat upper and lower parts.
12486 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12487 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12488 // Concat upper and lower parts.
12491 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12492 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12493 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12496 if (Subtarget->hasInt256())
12497 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12499 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12500 SDValue Undef = DAG.getUNDEF(InVT);
12501 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12502 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12503 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12505 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12506 VT.getVectorNumElements()/2);
12508 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12509 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12511 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12514 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12515 SelectionDAG &DAG) {
12516 MVT VT = Op->getSimpleValueType(0);
12517 SDValue In = Op->getOperand(0);
12518 MVT InVT = In.getSimpleValueType();
12520 unsigned int NumElts = VT.getVectorNumElements();
12521 if (NumElts != 8 && NumElts != 16)
12524 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12525 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12527 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
12528 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12529 // Now we have only mask extension
12530 assert(InVT.getVectorElementType() == MVT::i1);
12531 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
12532 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12533 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12534 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12535 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12536 MachinePointerInfo::getConstantPool(),
12537 false, false, false, Alignment);
12539 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
12540 if (VT.is512BitVector())
12542 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12545 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12546 SelectionDAG &DAG) {
12547 if (Subtarget->hasFp256()) {
12548 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12556 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12557 SelectionDAG &DAG) {
12559 MVT VT = Op.getSimpleValueType();
12560 SDValue In = Op.getOperand(0);
12561 MVT SVT = In.getSimpleValueType();
12563 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12564 return LowerZERO_EXTEND_AVX512(Op, DAG);
12566 if (Subtarget->hasFp256()) {
12567 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12572 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12573 VT.getVectorNumElements() != SVT.getVectorNumElements());
12577 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12579 MVT VT = Op.getSimpleValueType();
12580 SDValue In = Op.getOperand(0);
12581 MVT InVT = In.getSimpleValueType();
12583 if (VT == MVT::i1) {
12584 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12585 "Invalid scalar TRUNCATE operation");
12586 if (InVT.getSizeInBits() >= 32)
12588 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12589 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12591 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12592 "Invalid TRUNCATE operation");
12594 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12595 if (VT.getVectorElementType().getSizeInBits() >=8)
12596 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12598 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12599 unsigned NumElts = InVT.getVectorNumElements();
12600 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12601 if (InVT.getSizeInBits() < 512) {
12602 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12603 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12607 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12608 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12609 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12610 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12611 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12612 MachinePointerInfo::getConstantPool(),
12613 false, false, false, Alignment);
12614 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12615 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12616 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12619 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12620 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12621 if (Subtarget->hasInt256()) {
12622 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12623 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12624 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12626 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12627 DAG.getIntPtrConstant(0));
12630 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12631 DAG.getIntPtrConstant(0));
12632 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12633 DAG.getIntPtrConstant(2));
12634 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12635 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12636 static const int ShufMask[] = {0, 2, 4, 6};
12637 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12640 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12641 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12642 if (Subtarget->hasInt256()) {
12643 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12645 SmallVector<SDValue,32> pshufbMask;
12646 for (unsigned i = 0; i < 2; ++i) {
12647 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12648 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12649 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12650 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12651 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12652 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12653 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12654 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12655 for (unsigned j = 0; j < 8; ++j)
12656 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12658 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12659 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12660 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12662 static const int ShufMask[] = {0, 2, -1, -1};
12663 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12665 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12666 DAG.getIntPtrConstant(0));
12667 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12670 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12671 DAG.getIntPtrConstant(0));
12673 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12674 DAG.getIntPtrConstant(4));
12676 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12677 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12679 // The PSHUFB mask:
12680 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12681 -1, -1, -1, -1, -1, -1, -1, -1};
12683 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12684 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12685 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12687 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12688 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12690 // The MOVLHPS Mask:
12691 static const int ShufMask2[] = {0, 1, 4, 5};
12692 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12693 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12696 // Handle truncation of V256 to V128 using shuffles.
12697 if (!VT.is128BitVector() || !InVT.is256BitVector())
12700 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12702 unsigned NumElems = VT.getVectorNumElements();
12703 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12705 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12706 // Prepare truncation shuffle mask
12707 for (unsigned i = 0; i != NumElems; ++i)
12708 MaskVec[i] = i * 2;
12709 SDValue V = DAG.getVectorShuffle(NVT, DL,
12710 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12711 DAG.getUNDEF(NVT), &MaskVec[0]);
12712 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12713 DAG.getIntPtrConstant(0));
12716 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12717 SelectionDAG &DAG) const {
12718 assert(!Op.getSimpleValueType().isVector());
12720 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12721 /*IsSigned=*/ true, /*IsReplace=*/ false);
12722 SDValue FIST = Vals.first, StackSlot = Vals.second;
12723 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12724 if (!FIST.getNode()) return Op;
12726 if (StackSlot.getNode())
12727 // Load the result.
12728 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12729 FIST, StackSlot, MachinePointerInfo(),
12730 false, false, false, 0);
12732 // The node is the result.
12736 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12737 SelectionDAG &DAG) const {
12738 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12739 /*IsSigned=*/ false, /*IsReplace=*/ false);
12740 SDValue FIST = Vals.first, StackSlot = Vals.second;
12741 assert(FIST.getNode() && "Unexpected failure");
12743 if (StackSlot.getNode())
12744 // Load the result.
12745 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12746 FIST, StackSlot, MachinePointerInfo(),
12747 false, false, false, 0);
12749 // The node is the result.
12753 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12755 MVT VT = Op.getSimpleValueType();
12756 SDValue In = Op.getOperand(0);
12757 MVT SVT = In.getSimpleValueType();
12759 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12761 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12762 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12763 In, DAG.getUNDEF(SVT)));
12766 // The only differences between FABS and FNEG are the mask and the logic op.
12767 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12768 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12769 "Wrong opcode for lowering FABS or FNEG.");
12771 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12773 MVT VT = Op.getSimpleValueType();
12774 // Assume scalar op for initialization; update for vector if needed.
12775 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12776 // generate a 16-byte vector constant and logic op even for the scalar case.
12777 // Using a 16-byte mask allows folding the load of the mask with
12778 // the logic op, so it can save (~4 bytes) on code size.
12780 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12781 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12782 // decide if we should generate a 16-byte constant mask when we only need 4 or
12783 // 8 bytes for the scalar case.
12784 if (VT.isVector()) {
12785 EltVT = VT.getVectorElementType();
12786 NumElts = VT.getVectorNumElements();
12789 unsigned EltBits = EltVT.getSizeInBits();
12790 LLVMContext *Context = DAG.getContext();
12791 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12793 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12794 Constant *C = ConstantInt::get(*Context, MaskElt);
12795 C = ConstantVector::getSplat(NumElts, C);
12796 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12797 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12798 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12799 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12800 MachinePointerInfo::getConstantPool(),
12801 false, false, false, Alignment);
12803 if (VT.isVector()) {
12804 // For a vector, cast operands to a vector type, perform the logic op,
12805 // and cast the result back to the original value type.
12806 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12807 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
12808 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12809 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
12810 return DAG.getNode(ISD::BITCAST, dl, VT,
12811 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
12813 // If not vector, then scalar.
12814 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
12815 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
12818 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12819 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12820 LLVMContext *Context = DAG.getContext();
12821 SDValue Op0 = Op.getOperand(0);
12822 SDValue Op1 = Op.getOperand(1);
12824 MVT VT = Op.getSimpleValueType();
12825 MVT SrcVT = Op1.getSimpleValueType();
12827 // If second operand is smaller, extend it first.
12828 if (SrcVT.bitsLT(VT)) {
12829 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12832 // And if it is bigger, shrink it first.
12833 if (SrcVT.bitsGT(VT)) {
12834 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12838 // At this point the operands and the result should have the same
12839 // type, and that won't be f80 since that is not custom lowered.
12841 // First get the sign bit of second operand.
12842 SmallVector<Constant*,4> CV;
12843 if (SrcVT == MVT::f64) {
12844 const fltSemantics &Sem = APFloat::IEEEdouble;
12845 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
12846 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12848 const fltSemantics &Sem = APFloat::IEEEsingle;
12849 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
12850 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12851 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12852 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12854 Constant *C = ConstantVector::get(CV);
12855 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12856 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12857 MachinePointerInfo::getConstantPool(),
12858 false, false, false, 16);
12859 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12861 // Shift sign bit right or left if the two operands have different types.
12862 if (SrcVT.bitsGT(VT)) {
12863 // Op0 is MVT::f32, Op1 is MVT::f64.
12864 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
12865 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
12866 DAG.getConstant(32, MVT::i32));
12867 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
12868 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
12869 DAG.getIntPtrConstant(0));
12872 // Clear first operand sign bit.
12874 if (VT == MVT::f64) {
12875 const fltSemantics &Sem = APFloat::IEEEdouble;
12876 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12877 APInt(64, ~(1ULL << 63)))));
12878 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12880 const fltSemantics &Sem = APFloat::IEEEsingle;
12881 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12882 APInt(32, ~(1U << 31)))));
12883 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12884 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12885 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12887 C = ConstantVector::get(CV);
12888 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12889 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12890 MachinePointerInfo::getConstantPool(),
12891 false, false, false, 16);
12892 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
12894 // Or the value with the sign bit.
12895 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12898 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12899 SDValue N0 = Op.getOperand(0);
12901 MVT VT = Op.getSimpleValueType();
12903 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12904 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12905 DAG.getConstant(1, VT));
12906 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12909 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
12911 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12912 SelectionDAG &DAG) {
12913 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12915 if (!Subtarget->hasSSE41())
12918 if (!Op->hasOneUse())
12921 SDNode *N = Op.getNode();
12924 SmallVector<SDValue, 8> Opnds;
12925 DenseMap<SDValue, unsigned> VecInMap;
12926 SmallVector<SDValue, 8> VecIns;
12927 EVT VT = MVT::Other;
12929 // Recognize a special case where a vector is casted into wide integer to
12931 Opnds.push_back(N->getOperand(0));
12932 Opnds.push_back(N->getOperand(1));
12934 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12935 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12936 // BFS traverse all OR'd operands.
12937 if (I->getOpcode() == ISD::OR) {
12938 Opnds.push_back(I->getOperand(0));
12939 Opnds.push_back(I->getOperand(1));
12940 // Re-evaluate the number of nodes to be traversed.
12941 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12945 // Quit if a non-EXTRACT_VECTOR_ELT
12946 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12949 // Quit if without a constant index.
12950 SDValue Idx = I->getOperand(1);
12951 if (!isa<ConstantSDNode>(Idx))
12954 SDValue ExtractedFromVec = I->getOperand(0);
12955 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12956 if (M == VecInMap.end()) {
12957 VT = ExtractedFromVec.getValueType();
12958 // Quit if not 128/256-bit vector.
12959 if (!VT.is128BitVector() && !VT.is256BitVector())
12961 // Quit if not the same type.
12962 if (VecInMap.begin() != VecInMap.end() &&
12963 VT != VecInMap.begin()->first.getValueType())
12965 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12966 VecIns.push_back(ExtractedFromVec);
12968 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12971 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12972 "Not extracted from 128-/256-bit vector.");
12974 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12976 for (DenseMap<SDValue, unsigned>::const_iterator
12977 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12978 // Quit if not all elements are used.
12979 if (I->second != FullMask)
12983 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12985 // Cast all vectors into TestVT for PTEST.
12986 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12987 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12989 // If more than one full vectors are evaluated, OR them first before PTEST.
12990 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12991 // Each iteration will OR 2 nodes and append the result until there is only
12992 // 1 node left, i.e. the final OR'd value of all vectors.
12993 SDValue LHS = VecIns[Slot];
12994 SDValue RHS = VecIns[Slot + 1];
12995 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12998 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12999 VecIns.back(), VecIns.back());
13002 /// \brief return true if \c Op has a use that doesn't just read flags.
13003 static bool hasNonFlagsUse(SDValue Op) {
13004 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13006 SDNode *User = *UI;
13007 unsigned UOpNo = UI.getOperandNo();
13008 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13009 // Look pass truncate.
13010 UOpNo = User->use_begin().getOperandNo();
13011 User = *User->use_begin();
13014 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13015 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13021 /// Emit nodes that will be selected as "test Op0,Op0", or something
13023 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13024 SelectionDAG &DAG) const {
13025 if (Op.getValueType() == MVT::i1)
13026 // KORTEST instruction should be selected
13027 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13028 DAG.getConstant(0, Op.getValueType()));
13030 // CF and OF aren't always set the way we want. Determine which
13031 // of these we need.
13032 bool NeedCF = false;
13033 bool NeedOF = false;
13036 case X86::COND_A: case X86::COND_AE:
13037 case X86::COND_B: case X86::COND_BE:
13040 case X86::COND_G: case X86::COND_GE:
13041 case X86::COND_L: case X86::COND_LE:
13042 case X86::COND_O: case X86::COND_NO: {
13043 // Check if we really need to set the
13044 // Overflow flag. If NoSignedWrap is present
13045 // that is not actually needed.
13046 switch (Op->getOpcode()) {
13051 const BinaryWithFlagsSDNode *BinNode =
13052 cast<BinaryWithFlagsSDNode>(Op.getNode());
13053 if (BinNode->hasNoSignedWrap())
13063 // See if we can use the EFLAGS value from the operand instead of
13064 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13065 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13066 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13067 // Emit a CMP with 0, which is the TEST pattern.
13068 //if (Op.getValueType() == MVT::i1)
13069 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13070 // DAG.getConstant(0, MVT::i1));
13071 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13072 DAG.getConstant(0, Op.getValueType()));
13074 unsigned Opcode = 0;
13075 unsigned NumOperands = 0;
13077 // Truncate operations may prevent the merge of the SETCC instruction
13078 // and the arithmetic instruction before it. Attempt to truncate the operands
13079 // of the arithmetic instruction and use a reduced bit-width instruction.
13080 bool NeedTruncation = false;
13081 SDValue ArithOp = Op;
13082 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13083 SDValue Arith = Op->getOperand(0);
13084 // Both the trunc and the arithmetic op need to have one user each.
13085 if (Arith->hasOneUse())
13086 switch (Arith.getOpcode()) {
13093 NeedTruncation = true;
13099 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13100 // which may be the result of a CAST. We use the variable 'Op', which is the
13101 // non-casted variable when we check for possible users.
13102 switch (ArithOp.getOpcode()) {
13104 // Due to an isel shortcoming, be conservative if this add is likely to be
13105 // selected as part of a load-modify-store instruction. When the root node
13106 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13107 // uses of other nodes in the match, such as the ADD in this case. This
13108 // leads to the ADD being left around and reselected, with the result being
13109 // two adds in the output. Alas, even if none our users are stores, that
13110 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13111 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13112 // climbing the DAG back to the root, and it doesn't seem to be worth the
13114 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13115 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13116 if (UI->getOpcode() != ISD::CopyToReg &&
13117 UI->getOpcode() != ISD::SETCC &&
13118 UI->getOpcode() != ISD::STORE)
13121 if (ConstantSDNode *C =
13122 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13123 // An add of one will be selected as an INC.
13124 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13125 Opcode = X86ISD::INC;
13130 // An add of negative one (subtract of one) will be selected as a DEC.
13131 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13132 Opcode = X86ISD::DEC;
13138 // Otherwise use a regular EFLAGS-setting add.
13139 Opcode = X86ISD::ADD;
13144 // If we have a constant logical shift that's only used in a comparison
13145 // against zero turn it into an equivalent AND. This allows turning it into
13146 // a TEST instruction later.
13147 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13148 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13149 EVT VT = Op.getValueType();
13150 unsigned BitWidth = VT.getSizeInBits();
13151 unsigned ShAmt = Op->getConstantOperandVal(1);
13152 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13154 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13155 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13156 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13157 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13159 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13160 DAG.getConstant(Mask, VT));
13161 DAG.ReplaceAllUsesWith(Op, New);
13167 // If the primary and result isn't used, don't bother using X86ISD::AND,
13168 // because a TEST instruction will be better.
13169 if (!hasNonFlagsUse(Op))
13175 // Due to the ISEL shortcoming noted above, be conservative if this op is
13176 // likely to be selected as part of a load-modify-store instruction.
13177 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13178 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13179 if (UI->getOpcode() == ISD::STORE)
13182 // Otherwise use a regular EFLAGS-setting instruction.
13183 switch (ArithOp.getOpcode()) {
13184 default: llvm_unreachable("unexpected operator!");
13185 case ISD::SUB: Opcode = X86ISD::SUB; break;
13186 case ISD::XOR: Opcode = X86ISD::XOR; break;
13187 case ISD::AND: Opcode = X86ISD::AND; break;
13189 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13190 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13191 if (EFLAGS.getNode())
13194 Opcode = X86ISD::OR;
13208 return SDValue(Op.getNode(), 1);
13214 // If we found that truncation is beneficial, perform the truncation and
13216 if (NeedTruncation) {
13217 EVT VT = Op.getValueType();
13218 SDValue WideVal = Op->getOperand(0);
13219 EVT WideVT = WideVal.getValueType();
13220 unsigned ConvertedOp = 0;
13221 // Use a target machine opcode to prevent further DAGCombine
13222 // optimizations that may separate the arithmetic operations
13223 // from the setcc node.
13224 switch (WideVal.getOpcode()) {
13226 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13227 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13228 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13229 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13230 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13234 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13235 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13236 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13237 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13238 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13244 // Emit a CMP with 0, which is the TEST pattern.
13245 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13246 DAG.getConstant(0, Op.getValueType()));
13248 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13249 SmallVector<SDValue, 4> Ops;
13250 for (unsigned i = 0; i != NumOperands; ++i)
13251 Ops.push_back(Op.getOperand(i));
13253 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13254 DAG.ReplaceAllUsesWith(Op, New);
13255 return SDValue(New.getNode(), 1);
13258 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13260 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13261 SDLoc dl, SelectionDAG &DAG) const {
13262 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13263 if (C->getAPIntValue() == 0)
13264 return EmitTest(Op0, X86CC, dl, DAG);
13266 if (Op0.getValueType() == MVT::i1)
13267 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13270 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13271 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13272 // Do the comparison at i32 if it's smaller, besides the Atom case.
13273 // This avoids subregister aliasing issues. Keep the smaller reference
13274 // if we're optimizing for size, however, as that'll allow better folding
13275 // of memory operations.
13276 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13277 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13278 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13279 !Subtarget->isAtom()) {
13280 unsigned ExtendOp =
13281 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13282 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13283 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13285 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13286 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13287 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13289 return SDValue(Sub.getNode(), 1);
13291 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13294 /// Convert a comparison if required by the subtarget.
13295 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13296 SelectionDAG &DAG) const {
13297 // If the subtarget does not support the FUCOMI instruction, floating-point
13298 // comparisons have to be converted.
13299 if (Subtarget->hasCMov() ||
13300 Cmp.getOpcode() != X86ISD::CMP ||
13301 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13302 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13305 // The instruction selector will select an FUCOM instruction instead of
13306 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13307 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13308 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13310 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13311 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13312 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13313 DAG.getConstant(8, MVT::i8));
13314 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13315 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13318 static bool isAllOnes(SDValue V) {
13319 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13320 return C && C->isAllOnesValue();
13323 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13324 /// if it's possible.
13325 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13326 SDLoc dl, SelectionDAG &DAG) const {
13327 SDValue Op0 = And.getOperand(0);
13328 SDValue Op1 = And.getOperand(1);
13329 if (Op0.getOpcode() == ISD::TRUNCATE)
13330 Op0 = Op0.getOperand(0);
13331 if (Op1.getOpcode() == ISD::TRUNCATE)
13332 Op1 = Op1.getOperand(0);
13335 if (Op1.getOpcode() == ISD::SHL)
13336 std::swap(Op0, Op1);
13337 if (Op0.getOpcode() == ISD::SHL) {
13338 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13339 if (And00C->getZExtValue() == 1) {
13340 // If we looked past a truncate, check that it's only truncating away
13342 unsigned BitWidth = Op0.getValueSizeInBits();
13343 unsigned AndBitWidth = And.getValueSizeInBits();
13344 if (BitWidth > AndBitWidth) {
13346 DAG.computeKnownBits(Op0, Zeros, Ones);
13347 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13351 RHS = Op0.getOperand(1);
13353 } else if (Op1.getOpcode() == ISD::Constant) {
13354 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13355 uint64_t AndRHSVal = AndRHS->getZExtValue();
13356 SDValue AndLHS = Op0;
13358 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13359 LHS = AndLHS.getOperand(0);
13360 RHS = AndLHS.getOperand(1);
13363 // Use BT if the immediate can't be encoded in a TEST instruction.
13364 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13366 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13370 if (LHS.getNode()) {
13371 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13372 // instruction. Since the shift amount is in-range-or-undefined, we know
13373 // that doing a bittest on the i32 value is ok. We extend to i32 because
13374 // the encoding for the i16 version is larger than the i32 version.
13375 // Also promote i16 to i32 for performance / code size reason.
13376 if (LHS.getValueType() == MVT::i8 ||
13377 LHS.getValueType() == MVT::i16)
13378 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13380 // If the operand types disagree, extend the shift amount to match. Since
13381 // BT ignores high bits (like shifts) we can use anyextend.
13382 if (LHS.getValueType() != RHS.getValueType())
13383 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13385 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13386 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13387 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13388 DAG.getConstant(Cond, MVT::i8), BT);
13394 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13396 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13401 // SSE Condition code mapping:
13410 switch (SetCCOpcode) {
13411 default: llvm_unreachable("Unexpected SETCC condition");
13413 case ISD::SETEQ: SSECC = 0; break;
13415 case ISD::SETGT: Swap = true; // Fallthrough
13417 case ISD::SETOLT: SSECC = 1; break;
13419 case ISD::SETGE: Swap = true; // Fallthrough
13421 case ISD::SETOLE: SSECC = 2; break;
13422 case ISD::SETUO: SSECC = 3; break;
13424 case ISD::SETNE: SSECC = 4; break;
13425 case ISD::SETULE: Swap = true; // Fallthrough
13426 case ISD::SETUGE: SSECC = 5; break;
13427 case ISD::SETULT: Swap = true; // Fallthrough
13428 case ISD::SETUGT: SSECC = 6; break;
13429 case ISD::SETO: SSECC = 7; break;
13431 case ISD::SETONE: SSECC = 8; break;
13434 std::swap(Op0, Op1);
13439 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13440 // ones, and then concatenate the result back.
13441 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13442 MVT VT = Op.getSimpleValueType();
13444 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13445 "Unsupported value type for operation");
13447 unsigned NumElems = VT.getVectorNumElements();
13449 SDValue CC = Op.getOperand(2);
13451 // Extract the LHS vectors
13452 SDValue LHS = Op.getOperand(0);
13453 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13454 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13456 // Extract the RHS vectors
13457 SDValue RHS = Op.getOperand(1);
13458 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13459 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13461 // Issue the operation on the smaller types and concatenate the result back
13462 MVT EltVT = VT.getVectorElementType();
13463 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13464 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13465 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13466 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13469 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13470 const X86Subtarget *Subtarget) {
13471 SDValue Op0 = Op.getOperand(0);
13472 SDValue Op1 = Op.getOperand(1);
13473 SDValue CC = Op.getOperand(2);
13474 MVT VT = Op.getSimpleValueType();
13477 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13478 Op.getValueType().getScalarType() == MVT::i1 &&
13479 "Cannot set masked compare for this operation");
13481 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13483 bool Unsigned = false;
13486 switch (SetCCOpcode) {
13487 default: llvm_unreachable("Unexpected SETCC condition");
13488 case ISD::SETNE: SSECC = 4; break;
13489 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13490 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13491 case ISD::SETLT: Swap = true; //fall-through
13492 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13493 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13494 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13495 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13496 case ISD::SETULE: Unsigned = true; //fall-through
13497 case ISD::SETLE: SSECC = 2; break;
13501 std::swap(Op0, Op1);
13503 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13504 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13505 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13506 DAG.getConstant(SSECC, MVT::i8));
13509 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13510 /// operand \p Op1. If non-trivial (for example because it's not constant)
13511 /// return an empty value.
13512 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13514 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13518 MVT VT = Op1.getSimpleValueType();
13519 MVT EVT = VT.getVectorElementType();
13520 unsigned n = VT.getVectorNumElements();
13521 SmallVector<SDValue, 8> ULTOp1;
13523 for (unsigned i = 0; i < n; ++i) {
13524 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13525 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13528 // Avoid underflow.
13529 APInt Val = Elt->getAPIntValue();
13533 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13536 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13539 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13540 SelectionDAG &DAG) {
13541 SDValue Op0 = Op.getOperand(0);
13542 SDValue Op1 = Op.getOperand(1);
13543 SDValue CC = Op.getOperand(2);
13544 MVT VT = Op.getSimpleValueType();
13545 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13546 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13551 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13552 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13555 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13556 unsigned Opc = X86ISD::CMPP;
13557 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13558 assert(VT.getVectorNumElements() <= 16);
13559 Opc = X86ISD::CMPM;
13561 // In the two special cases we can't handle, emit two comparisons.
13564 unsigned CombineOpc;
13565 if (SetCCOpcode == ISD::SETUEQ) {
13566 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13568 assert(SetCCOpcode == ISD::SETONE);
13569 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13572 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13573 DAG.getConstant(CC0, MVT::i8));
13574 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13575 DAG.getConstant(CC1, MVT::i8));
13576 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13578 // Handle all other FP comparisons here.
13579 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13580 DAG.getConstant(SSECC, MVT::i8));
13583 // Break 256-bit integer vector compare into smaller ones.
13584 if (VT.is256BitVector() && !Subtarget->hasInt256())
13585 return Lower256IntVSETCC(Op, DAG);
13587 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13588 EVT OpVT = Op1.getValueType();
13589 if (Subtarget->hasAVX512()) {
13590 if (Op1.getValueType().is512BitVector() ||
13591 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13592 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13593 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13595 // In AVX-512 architecture setcc returns mask with i1 elements,
13596 // But there is no compare instruction for i8 and i16 elements in KNL.
13597 // We are not talking about 512-bit operands in this case, these
13598 // types are illegal.
13600 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13601 OpVT.getVectorElementType().getSizeInBits() >= 8))
13602 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13603 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13606 // We are handling one of the integer comparisons here. Since SSE only has
13607 // GT and EQ comparisons for integer, swapping operands and multiple
13608 // operations may be required for some comparisons.
13610 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13611 bool Subus = false;
13613 switch (SetCCOpcode) {
13614 default: llvm_unreachable("Unexpected SETCC condition");
13615 case ISD::SETNE: Invert = true;
13616 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13617 case ISD::SETLT: Swap = true;
13618 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13619 case ISD::SETGE: Swap = true;
13620 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13621 Invert = true; break;
13622 case ISD::SETULT: Swap = true;
13623 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13624 FlipSigns = true; break;
13625 case ISD::SETUGE: Swap = true;
13626 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13627 FlipSigns = true; Invert = true; break;
13630 // Special case: Use min/max operations for SETULE/SETUGE
13631 MVT VET = VT.getVectorElementType();
13633 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13634 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13637 switch (SetCCOpcode) {
13639 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13640 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13643 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13646 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13647 if (!MinMax && hasSubus) {
13648 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13650 // t = psubus Op0, Op1
13651 // pcmpeq t, <0..0>
13652 switch (SetCCOpcode) {
13654 case ISD::SETULT: {
13655 // If the comparison is against a constant we can turn this into a
13656 // setule. With psubus, setule does not require a swap. This is
13657 // beneficial because the constant in the register is no longer
13658 // destructed as the destination so it can be hoisted out of a loop.
13659 // Only do this pre-AVX since vpcmp* is no longer destructive.
13660 if (Subtarget->hasAVX())
13662 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13663 if (ULEOp1.getNode()) {
13665 Subus = true; Invert = false; Swap = false;
13669 // Psubus is better than flip-sign because it requires no inversion.
13670 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13671 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13675 Opc = X86ISD::SUBUS;
13681 std::swap(Op0, Op1);
13683 // Check that the operation in question is available (most are plain SSE2,
13684 // but PCMPGTQ and PCMPEQQ have different requirements).
13685 if (VT == MVT::v2i64) {
13686 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13687 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13689 // First cast everything to the right type.
13690 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13691 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13693 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13694 // bits of the inputs before performing those operations. The lower
13695 // compare is always unsigned.
13698 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13700 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13701 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13702 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13703 Sign, Zero, Sign, Zero);
13705 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13706 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13708 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13709 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13710 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13712 // Create masks for only the low parts/high parts of the 64 bit integers.
13713 static const int MaskHi[] = { 1, 1, 3, 3 };
13714 static const int MaskLo[] = { 0, 0, 2, 2 };
13715 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13716 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13717 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13719 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13720 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13723 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13725 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13728 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13729 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13730 // pcmpeqd + pshufd + pand.
13731 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13733 // First cast everything to the right type.
13734 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13735 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13738 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13740 // Make sure the lower and upper halves are both all-ones.
13741 static const int Mask[] = { 1, 0, 3, 2 };
13742 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13743 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13746 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13748 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13752 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13753 // bits of the inputs before performing those operations.
13755 EVT EltVT = VT.getVectorElementType();
13756 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
13757 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13758 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13761 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13763 // If the logical-not of the result is required, perform that now.
13765 Result = DAG.getNOT(dl, Result, VT);
13768 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13771 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13772 getZeroVector(VT, Subtarget, DAG, dl));
13777 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13779 MVT VT = Op.getSimpleValueType();
13781 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13783 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13784 && "SetCC type must be 8-bit or 1-bit integer");
13785 SDValue Op0 = Op.getOperand(0);
13786 SDValue Op1 = Op.getOperand(1);
13788 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13790 // Optimize to BT if possible.
13791 // Lower (X & (1 << N)) == 0 to BT(X, N).
13792 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13793 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13794 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13795 Op1.getOpcode() == ISD::Constant &&
13796 cast<ConstantSDNode>(Op1)->isNullValue() &&
13797 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13798 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13799 if (NewSetCC.getNode())
13803 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13805 if (Op1.getOpcode() == ISD::Constant &&
13806 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13807 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13808 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13810 // If the input is a setcc, then reuse the input setcc or use a new one with
13811 // the inverted condition.
13812 if (Op0.getOpcode() == X86ISD::SETCC) {
13813 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13814 bool Invert = (CC == ISD::SETNE) ^
13815 cast<ConstantSDNode>(Op1)->isNullValue();
13819 CCode = X86::GetOppositeBranchCondition(CCode);
13820 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13821 DAG.getConstant(CCode, MVT::i8),
13822 Op0.getOperand(1));
13824 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13828 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13829 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13830 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13832 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13833 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13836 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13837 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13838 if (X86CC == X86::COND_INVALID)
13841 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13842 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13843 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13844 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13846 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13850 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13851 static bool isX86LogicalCmp(SDValue Op) {
13852 unsigned Opc = Op.getNode()->getOpcode();
13853 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13854 Opc == X86ISD::SAHF)
13856 if (Op.getResNo() == 1 &&
13857 (Opc == X86ISD::ADD ||
13858 Opc == X86ISD::SUB ||
13859 Opc == X86ISD::ADC ||
13860 Opc == X86ISD::SBB ||
13861 Opc == X86ISD::SMUL ||
13862 Opc == X86ISD::UMUL ||
13863 Opc == X86ISD::INC ||
13864 Opc == X86ISD::DEC ||
13865 Opc == X86ISD::OR ||
13866 Opc == X86ISD::XOR ||
13867 Opc == X86ISD::AND))
13870 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13876 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13877 if (V.getOpcode() != ISD::TRUNCATE)
13880 SDValue VOp0 = V.getOperand(0);
13881 unsigned InBits = VOp0.getValueSizeInBits();
13882 unsigned Bits = V.getValueSizeInBits();
13883 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13886 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13887 bool addTest = true;
13888 SDValue Cond = Op.getOperand(0);
13889 SDValue Op1 = Op.getOperand(1);
13890 SDValue Op2 = Op.getOperand(2);
13892 EVT VT = Op1.getValueType();
13895 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13896 // are available. Otherwise fp cmovs get lowered into a less efficient branch
13897 // sequence later on.
13898 if (Cond.getOpcode() == ISD::SETCC &&
13899 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13900 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13901 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13902 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13903 int SSECC = translateX86FSETCC(
13904 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13907 if (Subtarget->hasAVX512()) {
13908 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13909 DAG.getConstant(SSECC, MVT::i8));
13910 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13912 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13913 DAG.getConstant(SSECC, MVT::i8));
13914 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13915 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13916 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13920 if (Cond.getOpcode() == ISD::SETCC) {
13921 SDValue NewCond = LowerSETCC(Cond, DAG);
13922 if (NewCond.getNode())
13926 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13927 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13928 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13929 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13930 if (Cond.getOpcode() == X86ISD::SETCC &&
13931 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13932 isZero(Cond.getOperand(1).getOperand(1))) {
13933 SDValue Cmp = Cond.getOperand(1);
13935 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13937 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13938 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13939 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13941 SDValue CmpOp0 = Cmp.getOperand(0);
13942 // Apply further optimizations for special cases
13943 // (select (x != 0), -1, 0) -> neg & sbb
13944 // (select (x == 0), 0, -1) -> neg & sbb
13945 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13946 if (YC->isNullValue() &&
13947 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13948 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13949 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13950 DAG.getConstant(0, CmpOp0.getValueType()),
13952 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13953 DAG.getConstant(X86::COND_B, MVT::i8),
13954 SDValue(Neg.getNode(), 1));
13958 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13959 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
13960 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13962 SDValue Res = // Res = 0 or -1.
13963 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13964 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
13966 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13967 Res = DAG.getNOT(DL, Res, Res.getValueType());
13969 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13970 if (!N2C || !N2C->isNullValue())
13971 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13976 // Look past (and (setcc_carry (cmp ...)), 1).
13977 if (Cond.getOpcode() == ISD::AND &&
13978 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13979 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13980 if (C && C->getAPIntValue() == 1)
13981 Cond = Cond.getOperand(0);
13984 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13985 // setting operand in place of the X86ISD::SETCC.
13986 unsigned CondOpcode = Cond.getOpcode();
13987 if (CondOpcode == X86ISD::SETCC ||
13988 CondOpcode == X86ISD::SETCC_CARRY) {
13989 CC = Cond.getOperand(0);
13991 SDValue Cmp = Cond.getOperand(1);
13992 unsigned Opc = Cmp.getOpcode();
13993 MVT VT = Op.getSimpleValueType();
13995 bool IllegalFPCMov = false;
13996 if (VT.isFloatingPoint() && !VT.isVector() &&
13997 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13998 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14000 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14001 Opc == X86ISD::BT) { // FIXME
14005 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14006 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14007 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14008 Cond.getOperand(0).getValueType() != MVT::i8)) {
14009 SDValue LHS = Cond.getOperand(0);
14010 SDValue RHS = Cond.getOperand(1);
14011 unsigned X86Opcode;
14014 switch (CondOpcode) {
14015 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14016 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14017 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14018 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14019 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14020 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14021 default: llvm_unreachable("unexpected overflowing operator");
14023 if (CondOpcode == ISD::UMULO)
14024 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14027 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14029 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14031 if (CondOpcode == ISD::UMULO)
14032 Cond = X86Op.getValue(2);
14034 Cond = X86Op.getValue(1);
14036 CC = DAG.getConstant(X86Cond, MVT::i8);
14041 // Look pass the truncate if the high bits are known zero.
14042 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14043 Cond = Cond.getOperand(0);
14045 // We know the result of AND is compared against zero. Try to match
14047 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14048 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14049 if (NewSetCC.getNode()) {
14050 CC = NewSetCC.getOperand(0);
14051 Cond = NewSetCC.getOperand(1);
14058 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14059 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14062 // a < b ? -1 : 0 -> RES = ~setcc_carry
14063 // a < b ? 0 : -1 -> RES = setcc_carry
14064 // a >= b ? -1 : 0 -> RES = setcc_carry
14065 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14066 if (Cond.getOpcode() == X86ISD::SUB) {
14067 Cond = ConvertCmpIfNecessary(Cond, DAG);
14068 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14070 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14071 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14072 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14073 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14074 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14075 return DAG.getNOT(DL, Res, Res.getValueType());
14080 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14081 // widen the cmov and push the truncate through. This avoids introducing a new
14082 // branch during isel and doesn't add any extensions.
14083 if (Op.getValueType() == MVT::i8 &&
14084 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14085 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14086 if (T1.getValueType() == T2.getValueType() &&
14087 // Blacklist CopyFromReg to avoid partial register stalls.
14088 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14089 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14090 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14091 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14095 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14096 // condition is true.
14097 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14098 SDValue Ops[] = { Op2, Op1, CC, Cond };
14099 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14102 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14103 MVT VT = Op->getSimpleValueType(0);
14104 SDValue In = Op->getOperand(0);
14105 MVT InVT = In.getSimpleValueType();
14108 unsigned int NumElts = VT.getVectorNumElements();
14109 if (NumElts != 8 && NumElts != 16)
14112 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14113 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14115 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14116 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14118 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14119 Constant *C = ConstantInt::get(*DAG.getContext(),
14120 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14122 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14123 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14124 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14125 MachinePointerInfo::getConstantPool(),
14126 false, false, false, Alignment);
14127 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14128 if (VT.is512BitVector())
14130 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14133 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14134 SelectionDAG &DAG) {
14135 MVT VT = Op->getSimpleValueType(0);
14136 SDValue In = Op->getOperand(0);
14137 MVT InVT = In.getSimpleValueType();
14140 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14141 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14143 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14144 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14145 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14148 if (Subtarget->hasInt256())
14149 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14151 // Optimize vectors in AVX mode
14152 // Sign extend v8i16 to v8i32 and
14155 // Divide input vector into two parts
14156 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14157 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14158 // concat the vectors to original VT
14160 unsigned NumElems = InVT.getVectorNumElements();
14161 SDValue Undef = DAG.getUNDEF(InVT);
14163 SmallVector<int,8> ShufMask1(NumElems, -1);
14164 for (unsigned i = 0; i != NumElems/2; ++i)
14167 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14169 SmallVector<int,8> ShufMask2(NumElems, -1);
14170 for (unsigned i = 0; i != NumElems/2; ++i)
14171 ShufMask2[i] = i + NumElems/2;
14173 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14175 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14176 VT.getVectorNumElements()/2);
14178 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14179 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14181 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14184 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14185 // may emit an illegal shuffle but the expansion is still better than scalar
14186 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14187 // we'll emit a shuffle and a arithmetic shift.
14188 // TODO: It is possible to support ZExt by zeroing the undef values during
14189 // the shuffle phase or after the shuffle.
14190 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14191 SelectionDAG &DAG) {
14192 MVT RegVT = Op.getSimpleValueType();
14193 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14194 assert(RegVT.isInteger() &&
14195 "We only custom lower integer vector sext loads.");
14197 // Nothing useful we can do without SSE2 shuffles.
14198 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14200 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14202 EVT MemVT = Ld->getMemoryVT();
14203 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14204 unsigned RegSz = RegVT.getSizeInBits();
14206 ISD::LoadExtType Ext = Ld->getExtensionType();
14208 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14209 && "Only anyext and sext are currently implemented.");
14210 assert(MemVT != RegVT && "Cannot extend to the same type");
14211 assert(MemVT.isVector() && "Must load a vector from memory");
14213 unsigned NumElems = RegVT.getVectorNumElements();
14214 unsigned MemSz = MemVT.getSizeInBits();
14215 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14217 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14218 // The only way in which we have a legal 256-bit vector result but not the
14219 // integer 256-bit operations needed to directly lower a sextload is if we
14220 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14221 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14222 // correctly legalized. We do this late to allow the canonical form of
14223 // sextload to persist throughout the rest of the DAG combiner -- it wants
14224 // to fold together any extensions it can, and so will fuse a sign_extend
14225 // of an sextload into a sextload targeting a wider value.
14227 if (MemSz == 128) {
14228 // Just switch this to a normal load.
14229 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14230 "it must be a legal 128-bit vector "
14232 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14233 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14234 Ld->isInvariant(), Ld->getAlignment());
14236 assert(MemSz < 128 &&
14237 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14238 // Do an sext load to a 128-bit vector type. We want to use the same
14239 // number of elements, but elements half as wide. This will end up being
14240 // recursively lowered by this routine, but will succeed as we definitely
14241 // have all the necessary features if we're using AVX1.
14243 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14244 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14246 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14247 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14248 Ld->isNonTemporal(), Ld->isInvariant(),
14249 Ld->getAlignment());
14252 // Replace chain users with the new chain.
14253 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14254 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14256 // Finally, do a normal sign-extend to the desired register.
14257 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14260 // All sizes must be a power of two.
14261 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14262 "Non-power-of-two elements are not custom lowered!");
14264 // Attempt to load the original value using scalar loads.
14265 // Find the largest scalar type that divides the total loaded size.
14266 MVT SclrLoadTy = MVT::i8;
14267 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14268 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14269 MVT Tp = (MVT::SimpleValueType)tp;
14270 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14275 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14276 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14278 SclrLoadTy = MVT::f64;
14280 // Calculate the number of scalar loads that we need to perform
14281 // in order to load our vector from memory.
14282 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14284 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14285 "Can only lower sext loads with a single scalar load!");
14287 unsigned loadRegZize = RegSz;
14288 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14291 // Represent our vector as a sequence of elements which are the
14292 // largest scalar that we can load.
14293 EVT LoadUnitVecVT = EVT::getVectorVT(
14294 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14296 // Represent the data using the same element type that is stored in
14297 // memory. In practice, we ''widen'' MemVT.
14299 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14300 loadRegZize / MemVT.getScalarType().getSizeInBits());
14302 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14303 "Invalid vector type");
14305 // We can't shuffle using an illegal type.
14306 assert(TLI.isTypeLegal(WideVecVT) &&
14307 "We only lower types that form legal widened vector types");
14309 SmallVector<SDValue, 8> Chains;
14310 SDValue Ptr = Ld->getBasePtr();
14311 SDValue Increment =
14312 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14313 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14315 for (unsigned i = 0; i < NumLoads; ++i) {
14316 // Perform a single load.
14317 SDValue ScalarLoad =
14318 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14319 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14320 Ld->getAlignment());
14321 Chains.push_back(ScalarLoad.getValue(1));
14322 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14323 // another round of DAGCombining.
14325 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14327 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14328 ScalarLoad, DAG.getIntPtrConstant(i));
14330 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14333 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14335 // Bitcast the loaded value to a vector of the original element type, in
14336 // the size of the target vector type.
14337 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14338 unsigned SizeRatio = RegSz / MemSz;
14340 if (Ext == ISD::SEXTLOAD) {
14341 // If we have SSE4.1, we can directly emit a VSEXT node.
14342 if (Subtarget->hasSSE41()) {
14343 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14344 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14348 // Otherwise we'll shuffle the small elements in the high bits of the
14349 // larger type and perform an arithmetic shift. If the shift is not legal
14350 // it's better to scalarize.
14351 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14352 "We can't implement a sext load without an arithmetic right shift!");
14354 // Redistribute the loaded elements into the different locations.
14355 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14356 for (unsigned i = 0; i != NumElems; ++i)
14357 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14359 SDValue Shuff = DAG.getVectorShuffle(
14360 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14362 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14364 // Build the arithmetic shift.
14365 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14366 MemVT.getVectorElementType().getSizeInBits();
14368 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14370 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14374 // Redistribute the loaded elements into the different locations.
14375 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14376 for (unsigned i = 0; i != NumElems; ++i)
14377 ShuffleVec[i * SizeRatio] = i;
14379 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14380 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14382 // Bitcast to the requested type.
14383 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14384 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14388 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14389 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14390 // from the AND / OR.
14391 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14392 Opc = Op.getOpcode();
14393 if (Opc != ISD::OR && Opc != ISD::AND)
14395 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14396 Op.getOperand(0).hasOneUse() &&
14397 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14398 Op.getOperand(1).hasOneUse());
14401 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14402 // 1 and that the SETCC node has a single use.
14403 static bool isXor1OfSetCC(SDValue Op) {
14404 if (Op.getOpcode() != ISD::XOR)
14406 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14407 if (N1C && N1C->getAPIntValue() == 1) {
14408 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14409 Op.getOperand(0).hasOneUse();
14414 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14415 bool addTest = true;
14416 SDValue Chain = Op.getOperand(0);
14417 SDValue Cond = Op.getOperand(1);
14418 SDValue Dest = Op.getOperand(2);
14421 bool Inverted = false;
14423 if (Cond.getOpcode() == ISD::SETCC) {
14424 // Check for setcc([su]{add,sub,mul}o == 0).
14425 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14426 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14427 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14428 Cond.getOperand(0).getResNo() == 1 &&
14429 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14430 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14431 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14432 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14433 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14434 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14436 Cond = Cond.getOperand(0);
14438 SDValue NewCond = LowerSETCC(Cond, DAG);
14439 if (NewCond.getNode())
14444 // FIXME: LowerXALUO doesn't handle these!!
14445 else if (Cond.getOpcode() == X86ISD::ADD ||
14446 Cond.getOpcode() == X86ISD::SUB ||
14447 Cond.getOpcode() == X86ISD::SMUL ||
14448 Cond.getOpcode() == X86ISD::UMUL)
14449 Cond = LowerXALUO(Cond, DAG);
14452 // Look pass (and (setcc_carry (cmp ...)), 1).
14453 if (Cond.getOpcode() == ISD::AND &&
14454 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14455 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14456 if (C && C->getAPIntValue() == 1)
14457 Cond = Cond.getOperand(0);
14460 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14461 // setting operand in place of the X86ISD::SETCC.
14462 unsigned CondOpcode = Cond.getOpcode();
14463 if (CondOpcode == X86ISD::SETCC ||
14464 CondOpcode == X86ISD::SETCC_CARRY) {
14465 CC = Cond.getOperand(0);
14467 SDValue Cmp = Cond.getOperand(1);
14468 unsigned Opc = Cmp.getOpcode();
14469 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14470 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14474 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14478 // These can only come from an arithmetic instruction with overflow,
14479 // e.g. SADDO, UADDO.
14480 Cond = Cond.getNode()->getOperand(1);
14486 CondOpcode = Cond.getOpcode();
14487 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14488 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14489 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14490 Cond.getOperand(0).getValueType() != MVT::i8)) {
14491 SDValue LHS = Cond.getOperand(0);
14492 SDValue RHS = Cond.getOperand(1);
14493 unsigned X86Opcode;
14496 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14497 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14499 switch (CondOpcode) {
14500 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14502 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14504 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14507 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14508 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14510 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14512 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14515 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14516 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14517 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14518 default: llvm_unreachable("unexpected overflowing operator");
14521 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14522 if (CondOpcode == ISD::UMULO)
14523 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14526 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14528 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14530 if (CondOpcode == ISD::UMULO)
14531 Cond = X86Op.getValue(2);
14533 Cond = X86Op.getValue(1);
14535 CC = DAG.getConstant(X86Cond, MVT::i8);
14539 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14540 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14541 if (CondOpc == ISD::OR) {
14542 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14543 // two branches instead of an explicit OR instruction with a
14545 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14546 isX86LogicalCmp(Cmp)) {
14547 CC = Cond.getOperand(0).getOperand(0);
14548 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14549 Chain, Dest, CC, Cmp);
14550 CC = Cond.getOperand(1).getOperand(0);
14554 } else { // ISD::AND
14555 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14556 // two branches instead of an explicit AND instruction with a
14557 // separate test. However, we only do this if this block doesn't
14558 // have a fall-through edge, because this requires an explicit
14559 // jmp when the condition is false.
14560 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14561 isX86LogicalCmp(Cmp) &&
14562 Op.getNode()->hasOneUse()) {
14563 X86::CondCode CCode =
14564 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14565 CCode = X86::GetOppositeBranchCondition(CCode);
14566 CC = DAG.getConstant(CCode, MVT::i8);
14567 SDNode *User = *Op.getNode()->use_begin();
14568 // Look for an unconditional branch following this conditional branch.
14569 // We need this because we need to reverse the successors in order
14570 // to implement FCMP_OEQ.
14571 if (User->getOpcode() == ISD::BR) {
14572 SDValue FalseBB = User->getOperand(1);
14574 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14575 assert(NewBR == User);
14579 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14580 Chain, Dest, CC, Cmp);
14581 X86::CondCode CCode =
14582 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14583 CCode = X86::GetOppositeBranchCondition(CCode);
14584 CC = DAG.getConstant(CCode, MVT::i8);
14590 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14591 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14592 // It should be transformed during dag combiner except when the condition
14593 // is set by a arithmetics with overflow node.
14594 X86::CondCode CCode =
14595 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14596 CCode = X86::GetOppositeBranchCondition(CCode);
14597 CC = DAG.getConstant(CCode, MVT::i8);
14598 Cond = Cond.getOperand(0).getOperand(1);
14600 } else if (Cond.getOpcode() == ISD::SETCC &&
14601 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14602 // For FCMP_OEQ, we can emit
14603 // two branches instead of an explicit AND instruction with a
14604 // separate test. However, we only do this if this block doesn't
14605 // have a fall-through edge, because this requires an explicit
14606 // jmp when the condition is false.
14607 if (Op.getNode()->hasOneUse()) {
14608 SDNode *User = *Op.getNode()->use_begin();
14609 // Look for an unconditional branch following this conditional branch.
14610 // We need this because we need to reverse the successors in order
14611 // to implement FCMP_OEQ.
14612 if (User->getOpcode() == ISD::BR) {
14613 SDValue FalseBB = User->getOperand(1);
14615 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14616 assert(NewBR == User);
14620 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14621 Cond.getOperand(0), Cond.getOperand(1));
14622 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14623 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14624 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14625 Chain, Dest, CC, Cmp);
14626 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14631 } else if (Cond.getOpcode() == ISD::SETCC &&
14632 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14633 // For FCMP_UNE, we can emit
14634 // two branches instead of an explicit AND instruction with a
14635 // separate test. However, we only do this if this block doesn't
14636 // have a fall-through edge, because this requires an explicit
14637 // jmp when the condition is false.
14638 if (Op.getNode()->hasOneUse()) {
14639 SDNode *User = *Op.getNode()->use_begin();
14640 // Look for an unconditional branch following this conditional branch.
14641 // We need this because we need to reverse the successors in order
14642 // to implement FCMP_UNE.
14643 if (User->getOpcode() == ISD::BR) {
14644 SDValue FalseBB = User->getOperand(1);
14646 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14647 assert(NewBR == User);
14650 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14651 Cond.getOperand(0), Cond.getOperand(1));
14652 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14653 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14654 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14655 Chain, Dest, CC, Cmp);
14656 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14666 // Look pass the truncate if the high bits are known zero.
14667 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14668 Cond = Cond.getOperand(0);
14670 // We know the result of AND is compared against zero. Try to match
14672 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14673 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14674 if (NewSetCC.getNode()) {
14675 CC = NewSetCC.getOperand(0);
14676 Cond = NewSetCC.getOperand(1);
14683 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14684 CC = DAG.getConstant(X86Cond, MVT::i8);
14685 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14687 Cond = ConvertCmpIfNecessary(Cond, DAG);
14688 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14689 Chain, Dest, CC, Cond);
14692 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14693 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14694 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14695 // that the guard pages used by the OS virtual memory manager are allocated in
14696 // correct sequence.
14698 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14699 SelectionDAG &DAG) const {
14700 MachineFunction &MF = DAG.getMachineFunction();
14701 bool SplitStack = MF.shouldSplitStack();
14702 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
14707 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14708 SDNode* Node = Op.getNode();
14710 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14711 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14712 " not tell us which reg is the stack pointer!");
14713 EVT VT = Node->getValueType(0);
14714 SDValue Tmp1 = SDValue(Node, 0);
14715 SDValue Tmp2 = SDValue(Node, 1);
14716 SDValue Tmp3 = Node->getOperand(2);
14717 SDValue Chain = Tmp1.getOperand(0);
14719 // Chain the dynamic stack allocation so that it doesn't modify the stack
14720 // pointer when other instructions are using the stack.
14721 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
14724 SDValue Size = Tmp2.getOperand(1);
14725 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14726 Chain = SP.getValue(1);
14727 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14728 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
14729 unsigned StackAlign = TFI.getStackAlignment();
14730 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14731 if (Align > StackAlign)
14732 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14733 DAG.getConstant(-(uint64_t)Align, VT));
14734 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14736 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
14737 DAG.getIntPtrConstant(0, true), SDValue(),
14740 SDValue Ops[2] = { Tmp1, Tmp2 };
14741 return DAG.getMergeValues(Ops, dl);
14745 SDValue Chain = Op.getOperand(0);
14746 SDValue Size = Op.getOperand(1);
14747 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14748 EVT VT = Op.getNode()->getValueType(0);
14750 bool Is64Bit = Subtarget->is64Bit();
14751 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
14754 MachineRegisterInfo &MRI = MF.getRegInfo();
14757 // The 64 bit implementation of segmented stacks needs to clobber both r10
14758 // r11. This makes it impossible to use it along with nested parameters.
14759 const Function *F = MF.getFunction();
14761 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14763 if (I->hasNestAttr())
14764 report_fatal_error("Cannot use segmented stacks with functions that "
14765 "have nested arguments.");
14768 const TargetRegisterClass *AddrRegClass =
14769 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
14770 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14771 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14772 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14773 DAG.getRegister(Vreg, SPTy));
14774 SDValue Ops1[2] = { Value, Chain };
14775 return DAG.getMergeValues(Ops1, dl);
14778 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
14780 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14781 Flag = Chain.getValue(1);
14782 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14784 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14786 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
14787 DAG.getSubtarget().getRegisterInfo());
14788 unsigned SPReg = RegInfo->getStackRegister();
14789 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14790 Chain = SP.getValue(1);
14793 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14794 DAG.getConstant(-(uint64_t)Align, VT));
14795 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14798 SDValue Ops1[2] = { SP, Chain };
14799 return DAG.getMergeValues(Ops1, dl);
14803 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14804 MachineFunction &MF = DAG.getMachineFunction();
14805 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14807 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14810 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14811 // vastart just stores the address of the VarArgsFrameIndex slot into the
14812 // memory location argument.
14813 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14815 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14816 MachinePointerInfo(SV), false, false, 0);
14820 // gp_offset (0 - 6 * 8)
14821 // fp_offset (48 - 48 + 8 * 16)
14822 // overflow_arg_area (point to parameters coming in memory).
14824 SmallVector<SDValue, 8> MemOps;
14825 SDValue FIN = Op.getOperand(1);
14827 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14828 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14830 FIN, MachinePointerInfo(SV), false, false, 0);
14831 MemOps.push_back(Store);
14834 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14835 FIN, DAG.getIntPtrConstant(4));
14836 Store = DAG.getStore(Op.getOperand(0), DL,
14837 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14839 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14840 MemOps.push_back(Store);
14842 // Store ptr to overflow_arg_area
14843 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14844 FIN, DAG.getIntPtrConstant(4));
14845 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14847 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14848 MachinePointerInfo(SV, 8),
14850 MemOps.push_back(Store);
14852 // Store ptr to reg_save_area.
14853 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14854 FIN, DAG.getIntPtrConstant(8));
14855 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14857 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14858 MachinePointerInfo(SV, 16), false, false, 0);
14859 MemOps.push_back(Store);
14860 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14863 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14864 assert(Subtarget->is64Bit() &&
14865 "LowerVAARG only handles 64-bit va_arg!");
14866 assert((Subtarget->isTargetLinux() ||
14867 Subtarget->isTargetDarwin()) &&
14868 "Unhandled target in LowerVAARG");
14869 assert(Op.getNode()->getNumOperands() == 4);
14870 SDValue Chain = Op.getOperand(0);
14871 SDValue SrcPtr = Op.getOperand(1);
14872 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14873 unsigned Align = Op.getConstantOperandVal(3);
14876 EVT ArgVT = Op.getNode()->getValueType(0);
14877 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14878 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14881 // Decide which area this value should be read from.
14882 // TODO: Implement the AMD64 ABI in its entirety. This simple
14883 // selection mechanism works only for the basic types.
14884 if (ArgVT == MVT::f80) {
14885 llvm_unreachable("va_arg for f80 not yet implemented");
14886 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14887 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14888 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14889 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14891 llvm_unreachable("Unhandled argument type in LowerVAARG");
14894 if (ArgMode == 2) {
14895 // Sanity Check: Make sure using fp_offset makes sense.
14896 assert(!DAG.getTarget().Options.UseSoftFloat &&
14897 !(DAG.getMachineFunction()
14898 .getFunction()->getAttributes()
14899 .hasAttribute(AttributeSet::FunctionIndex,
14900 Attribute::NoImplicitFloat)) &&
14901 Subtarget->hasSSE1());
14904 // Insert VAARG_64 node into the DAG
14905 // VAARG_64 returns two values: Variable Argument Address, Chain
14906 SmallVector<SDValue, 11> InstOps;
14907 InstOps.push_back(Chain);
14908 InstOps.push_back(SrcPtr);
14909 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
14910 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
14911 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
14912 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14913 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14914 VTs, InstOps, MVT::i64,
14915 MachinePointerInfo(SV),
14917 /*Volatile=*/false,
14919 /*WriteMem=*/true);
14920 Chain = VAARG.getValue(1);
14922 // Load the next argument and return it
14923 return DAG.getLoad(ArgVT, dl,
14926 MachinePointerInfo(),
14927 false, false, false, 0);
14930 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14931 SelectionDAG &DAG) {
14932 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14933 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14934 SDValue Chain = Op.getOperand(0);
14935 SDValue DstPtr = Op.getOperand(1);
14936 SDValue SrcPtr = Op.getOperand(2);
14937 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14938 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14941 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14942 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14944 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14947 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14948 // amount is a constant. Takes immediate version of shift as input.
14949 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14950 SDValue SrcOp, uint64_t ShiftAmt,
14951 SelectionDAG &DAG) {
14952 MVT ElementType = VT.getVectorElementType();
14954 // Fold this packed shift into its first operand if ShiftAmt is 0.
14958 // Check for ShiftAmt >= element width
14959 if (ShiftAmt >= ElementType.getSizeInBits()) {
14960 if (Opc == X86ISD::VSRAI)
14961 ShiftAmt = ElementType.getSizeInBits() - 1;
14963 return DAG.getConstant(0, VT);
14966 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14967 && "Unknown target vector shift-by-constant node");
14969 // Fold this packed vector shift into a build vector if SrcOp is a
14970 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14971 if (VT == SrcOp.getSimpleValueType() &&
14972 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14973 SmallVector<SDValue, 8> Elts;
14974 unsigned NumElts = SrcOp->getNumOperands();
14975 ConstantSDNode *ND;
14978 default: llvm_unreachable(nullptr);
14979 case X86ISD::VSHLI:
14980 for (unsigned i=0; i!=NumElts; ++i) {
14981 SDValue CurrentOp = SrcOp->getOperand(i);
14982 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14983 Elts.push_back(CurrentOp);
14986 ND = cast<ConstantSDNode>(CurrentOp);
14987 const APInt &C = ND->getAPIntValue();
14988 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
14991 case X86ISD::VSRLI:
14992 for (unsigned i=0; i!=NumElts; ++i) {
14993 SDValue CurrentOp = SrcOp->getOperand(i);
14994 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14995 Elts.push_back(CurrentOp);
14998 ND = cast<ConstantSDNode>(CurrentOp);
14999 const APInt &C = ND->getAPIntValue();
15000 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15003 case X86ISD::VSRAI:
15004 for (unsigned i=0; i!=NumElts; ++i) {
15005 SDValue CurrentOp = SrcOp->getOperand(i);
15006 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15007 Elts.push_back(CurrentOp);
15010 ND = cast<ConstantSDNode>(CurrentOp);
15011 const APInt &C = ND->getAPIntValue();
15012 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15017 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15020 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15023 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15024 // may or may not be a constant. Takes immediate version of shift as input.
15025 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15026 SDValue SrcOp, SDValue ShAmt,
15027 SelectionDAG &DAG) {
15028 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15030 // Catch shift-by-constant.
15031 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15032 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15033 CShAmt->getZExtValue(), DAG);
15035 // Change opcode to non-immediate version
15037 default: llvm_unreachable("Unknown target vector shift node");
15038 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15039 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15040 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15043 // Need to build a vector containing shift amount
15044 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15047 ShOps[1] = DAG.getConstant(0, MVT::i32);
15048 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15049 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15051 // The return type has to be a 128-bit type with the same element
15052 // type as the input type.
15053 MVT EltVT = VT.getVectorElementType();
15054 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15056 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15057 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15060 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15061 /// necessary casting for \p Mask when lowering masking intrinsics.
15062 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15063 SDValue PreservedSrc, SelectionDAG &DAG) {
15064 EVT VT = Op.getValueType();
15065 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15066 MVT::i1, VT.getVectorNumElements());
15069 assert(MaskVT.isSimple() && "invalid mask type");
15070 return DAG.getNode(ISD::VSELECT, dl, VT,
15071 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15075 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15077 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15078 case Intrinsic::x86_fma_vfmadd_ps:
15079 case Intrinsic::x86_fma_vfmadd_pd:
15080 case Intrinsic::x86_fma_vfmadd_ps_256:
15081 case Intrinsic::x86_fma_vfmadd_pd_256:
15082 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15083 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15084 return X86ISD::FMADD;
15085 case Intrinsic::x86_fma_vfmsub_ps:
15086 case Intrinsic::x86_fma_vfmsub_pd:
15087 case Intrinsic::x86_fma_vfmsub_ps_256:
15088 case Intrinsic::x86_fma_vfmsub_pd_256:
15089 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15090 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15091 return X86ISD::FMSUB;
15092 case Intrinsic::x86_fma_vfnmadd_ps:
15093 case Intrinsic::x86_fma_vfnmadd_pd:
15094 case Intrinsic::x86_fma_vfnmadd_ps_256:
15095 case Intrinsic::x86_fma_vfnmadd_pd_256:
15096 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15097 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15098 return X86ISD::FNMADD;
15099 case Intrinsic::x86_fma_vfnmsub_ps:
15100 case Intrinsic::x86_fma_vfnmsub_pd:
15101 case Intrinsic::x86_fma_vfnmsub_ps_256:
15102 case Intrinsic::x86_fma_vfnmsub_pd_256:
15103 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15104 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15105 return X86ISD::FNMSUB;
15106 case Intrinsic::x86_fma_vfmaddsub_ps:
15107 case Intrinsic::x86_fma_vfmaddsub_pd:
15108 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15109 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15110 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15111 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15112 return X86ISD::FMADDSUB;
15113 case Intrinsic::x86_fma_vfmsubadd_ps:
15114 case Intrinsic::x86_fma_vfmsubadd_pd:
15115 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15116 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15117 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15118 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15119 return X86ISD::FMSUBADD;
15123 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15125 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15127 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15129 switch(IntrData->Type) {
15130 case INTR_TYPE_1OP:
15131 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15132 case INTR_TYPE_2OP:
15133 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15135 case INTR_TYPE_3OP:
15136 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15137 Op.getOperand(2), Op.getOperand(3));
15138 case COMI: { // Comparison intrinsics
15139 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15140 SDValue LHS = Op.getOperand(1);
15141 SDValue RHS = Op.getOperand(2);
15142 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15143 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15144 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15145 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15146 DAG.getConstant(X86CC, MVT::i8), Cond);
15147 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15150 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15151 Op.getOperand(1), Op.getOperand(2), DAG);
15158 default: return SDValue(); // Don't custom lower most intrinsics.
15160 // Arithmetic intrinsics.
15161 case Intrinsic::x86_sse2_pmulu_dq:
15162 case Intrinsic::x86_avx2_pmulu_dq:
15163 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15164 Op.getOperand(1), Op.getOperand(2));
15166 case Intrinsic::x86_sse41_pmuldq:
15167 case Intrinsic::x86_avx2_pmul_dq:
15168 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15169 Op.getOperand(1), Op.getOperand(2));
15171 case Intrinsic::x86_sse2_pmulhu_w:
15172 case Intrinsic::x86_avx2_pmulhu_w:
15173 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15174 Op.getOperand(1), Op.getOperand(2));
15176 case Intrinsic::x86_sse2_pmulh_w:
15177 case Intrinsic::x86_avx2_pmulh_w:
15178 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15179 Op.getOperand(1), Op.getOperand(2));
15181 // SSE/SSE2/AVX floating point max/min intrinsics.
15182 case Intrinsic::x86_sse_max_ps:
15183 case Intrinsic::x86_sse2_max_pd:
15184 case Intrinsic::x86_avx_max_ps_256:
15185 case Intrinsic::x86_avx_max_pd_256:
15186 case Intrinsic::x86_sse_min_ps:
15187 case Intrinsic::x86_sse2_min_pd:
15188 case Intrinsic::x86_avx_min_ps_256:
15189 case Intrinsic::x86_avx_min_pd_256: {
15192 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15193 case Intrinsic::x86_sse_max_ps:
15194 case Intrinsic::x86_sse2_max_pd:
15195 case Intrinsic::x86_avx_max_ps_256:
15196 case Intrinsic::x86_avx_max_pd_256:
15197 Opcode = X86ISD::FMAX;
15199 case Intrinsic::x86_sse_min_ps:
15200 case Intrinsic::x86_sse2_min_pd:
15201 case Intrinsic::x86_avx_min_ps_256:
15202 case Intrinsic::x86_avx_min_pd_256:
15203 Opcode = X86ISD::FMIN;
15206 return DAG.getNode(Opcode, dl, Op.getValueType(),
15207 Op.getOperand(1), Op.getOperand(2));
15210 // AVX2 variable shift intrinsics
15211 case Intrinsic::x86_avx2_psllv_d:
15212 case Intrinsic::x86_avx2_psllv_q:
15213 case Intrinsic::x86_avx2_psllv_d_256:
15214 case Intrinsic::x86_avx2_psllv_q_256:
15215 case Intrinsic::x86_avx2_psrlv_d:
15216 case Intrinsic::x86_avx2_psrlv_q:
15217 case Intrinsic::x86_avx2_psrlv_d_256:
15218 case Intrinsic::x86_avx2_psrlv_q_256:
15219 case Intrinsic::x86_avx2_psrav_d:
15220 case Intrinsic::x86_avx2_psrav_d_256: {
15223 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15224 case Intrinsic::x86_avx2_psllv_d:
15225 case Intrinsic::x86_avx2_psllv_q:
15226 case Intrinsic::x86_avx2_psllv_d_256:
15227 case Intrinsic::x86_avx2_psllv_q_256:
15230 case Intrinsic::x86_avx2_psrlv_d:
15231 case Intrinsic::x86_avx2_psrlv_q:
15232 case Intrinsic::x86_avx2_psrlv_d_256:
15233 case Intrinsic::x86_avx2_psrlv_q_256:
15236 case Intrinsic::x86_avx2_psrav_d:
15237 case Intrinsic::x86_avx2_psrav_d_256:
15241 return DAG.getNode(Opcode, dl, Op.getValueType(),
15242 Op.getOperand(1), Op.getOperand(2));
15245 case Intrinsic::x86_sse2_packssdw_128:
15246 case Intrinsic::x86_sse2_packsswb_128:
15247 case Intrinsic::x86_avx2_packssdw:
15248 case Intrinsic::x86_avx2_packsswb:
15249 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15250 Op.getOperand(1), Op.getOperand(2));
15252 case Intrinsic::x86_sse2_packuswb_128:
15253 case Intrinsic::x86_sse41_packusdw:
15254 case Intrinsic::x86_avx2_packuswb:
15255 case Intrinsic::x86_avx2_packusdw:
15256 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15257 Op.getOperand(1), Op.getOperand(2));
15259 case Intrinsic::x86_ssse3_pshuf_b_128:
15260 case Intrinsic::x86_avx2_pshuf_b:
15261 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15262 Op.getOperand(1), Op.getOperand(2));
15264 case Intrinsic::x86_sse2_pshuf_d:
15265 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15266 Op.getOperand(1), Op.getOperand(2));
15268 case Intrinsic::x86_sse2_pshufl_w:
15269 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15270 Op.getOperand(1), Op.getOperand(2));
15272 case Intrinsic::x86_sse2_pshufh_w:
15273 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15274 Op.getOperand(1), Op.getOperand(2));
15276 case Intrinsic::x86_ssse3_psign_b_128:
15277 case Intrinsic::x86_ssse3_psign_w_128:
15278 case Intrinsic::x86_ssse3_psign_d_128:
15279 case Intrinsic::x86_avx2_psign_b:
15280 case Intrinsic::x86_avx2_psign_w:
15281 case Intrinsic::x86_avx2_psign_d:
15282 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15283 Op.getOperand(1), Op.getOperand(2));
15285 case Intrinsic::x86_avx2_permd:
15286 case Intrinsic::x86_avx2_permps:
15287 // Operands intentionally swapped. Mask is last operand to intrinsic,
15288 // but second operand for node/instruction.
15289 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15290 Op.getOperand(2), Op.getOperand(1));
15292 case Intrinsic::x86_avx512_mask_valign_q_512:
15293 case Intrinsic::x86_avx512_mask_valign_d_512:
15294 // Vector source operands are swapped.
15295 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15296 Op.getValueType(), Op.getOperand(2),
15299 Op.getOperand(5), Op.getOperand(4), DAG);
15301 // ptest and testp intrinsics. The intrinsic these come from are designed to
15302 // return an integer value, not just an instruction so lower it to the ptest
15303 // or testp pattern and a setcc for the result.
15304 case Intrinsic::x86_sse41_ptestz:
15305 case Intrinsic::x86_sse41_ptestc:
15306 case Intrinsic::x86_sse41_ptestnzc:
15307 case Intrinsic::x86_avx_ptestz_256:
15308 case Intrinsic::x86_avx_ptestc_256:
15309 case Intrinsic::x86_avx_ptestnzc_256:
15310 case Intrinsic::x86_avx_vtestz_ps:
15311 case Intrinsic::x86_avx_vtestc_ps:
15312 case Intrinsic::x86_avx_vtestnzc_ps:
15313 case Intrinsic::x86_avx_vtestz_pd:
15314 case Intrinsic::x86_avx_vtestc_pd:
15315 case Intrinsic::x86_avx_vtestnzc_pd:
15316 case Intrinsic::x86_avx_vtestz_ps_256:
15317 case Intrinsic::x86_avx_vtestc_ps_256:
15318 case Intrinsic::x86_avx_vtestnzc_ps_256:
15319 case Intrinsic::x86_avx_vtestz_pd_256:
15320 case Intrinsic::x86_avx_vtestc_pd_256:
15321 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15322 bool IsTestPacked = false;
15325 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15326 case Intrinsic::x86_avx_vtestz_ps:
15327 case Intrinsic::x86_avx_vtestz_pd:
15328 case Intrinsic::x86_avx_vtestz_ps_256:
15329 case Intrinsic::x86_avx_vtestz_pd_256:
15330 IsTestPacked = true; // Fallthrough
15331 case Intrinsic::x86_sse41_ptestz:
15332 case Intrinsic::x86_avx_ptestz_256:
15334 X86CC = X86::COND_E;
15336 case Intrinsic::x86_avx_vtestc_ps:
15337 case Intrinsic::x86_avx_vtestc_pd:
15338 case Intrinsic::x86_avx_vtestc_ps_256:
15339 case Intrinsic::x86_avx_vtestc_pd_256:
15340 IsTestPacked = true; // Fallthrough
15341 case Intrinsic::x86_sse41_ptestc:
15342 case Intrinsic::x86_avx_ptestc_256:
15344 X86CC = X86::COND_B;
15346 case Intrinsic::x86_avx_vtestnzc_ps:
15347 case Intrinsic::x86_avx_vtestnzc_pd:
15348 case Intrinsic::x86_avx_vtestnzc_ps_256:
15349 case Intrinsic::x86_avx_vtestnzc_pd_256:
15350 IsTestPacked = true; // Fallthrough
15351 case Intrinsic::x86_sse41_ptestnzc:
15352 case Intrinsic::x86_avx_ptestnzc_256:
15354 X86CC = X86::COND_A;
15358 SDValue LHS = Op.getOperand(1);
15359 SDValue RHS = Op.getOperand(2);
15360 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15361 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15362 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15363 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15364 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15366 case Intrinsic::x86_avx512_kortestz_w:
15367 case Intrinsic::x86_avx512_kortestc_w: {
15368 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15369 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15370 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15371 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15372 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15373 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15374 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15377 case Intrinsic::x86_sse42_pcmpistria128:
15378 case Intrinsic::x86_sse42_pcmpestria128:
15379 case Intrinsic::x86_sse42_pcmpistric128:
15380 case Intrinsic::x86_sse42_pcmpestric128:
15381 case Intrinsic::x86_sse42_pcmpistrio128:
15382 case Intrinsic::x86_sse42_pcmpestrio128:
15383 case Intrinsic::x86_sse42_pcmpistris128:
15384 case Intrinsic::x86_sse42_pcmpestris128:
15385 case Intrinsic::x86_sse42_pcmpistriz128:
15386 case Intrinsic::x86_sse42_pcmpestriz128: {
15390 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15391 case Intrinsic::x86_sse42_pcmpistria128:
15392 Opcode = X86ISD::PCMPISTRI;
15393 X86CC = X86::COND_A;
15395 case Intrinsic::x86_sse42_pcmpestria128:
15396 Opcode = X86ISD::PCMPESTRI;
15397 X86CC = X86::COND_A;
15399 case Intrinsic::x86_sse42_pcmpistric128:
15400 Opcode = X86ISD::PCMPISTRI;
15401 X86CC = X86::COND_B;
15403 case Intrinsic::x86_sse42_pcmpestric128:
15404 Opcode = X86ISD::PCMPESTRI;
15405 X86CC = X86::COND_B;
15407 case Intrinsic::x86_sse42_pcmpistrio128:
15408 Opcode = X86ISD::PCMPISTRI;
15409 X86CC = X86::COND_O;
15411 case Intrinsic::x86_sse42_pcmpestrio128:
15412 Opcode = X86ISD::PCMPESTRI;
15413 X86CC = X86::COND_O;
15415 case Intrinsic::x86_sse42_pcmpistris128:
15416 Opcode = X86ISD::PCMPISTRI;
15417 X86CC = X86::COND_S;
15419 case Intrinsic::x86_sse42_pcmpestris128:
15420 Opcode = X86ISD::PCMPESTRI;
15421 X86CC = X86::COND_S;
15423 case Intrinsic::x86_sse42_pcmpistriz128:
15424 Opcode = X86ISD::PCMPISTRI;
15425 X86CC = X86::COND_E;
15427 case Intrinsic::x86_sse42_pcmpestriz128:
15428 Opcode = X86ISD::PCMPESTRI;
15429 X86CC = X86::COND_E;
15432 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15433 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15434 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15435 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15436 DAG.getConstant(X86CC, MVT::i8),
15437 SDValue(PCMP.getNode(), 1));
15438 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15441 case Intrinsic::x86_sse42_pcmpistri128:
15442 case Intrinsic::x86_sse42_pcmpestri128: {
15444 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15445 Opcode = X86ISD::PCMPISTRI;
15447 Opcode = X86ISD::PCMPESTRI;
15449 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15450 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15451 return DAG.getNode(Opcode, dl, VTs, NewOps);
15454 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15455 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15456 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15457 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15458 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15459 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15460 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15461 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15462 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15463 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15464 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15465 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15466 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15467 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15468 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15469 dl, Op.getValueType(),
15473 Op.getOperand(4), Op.getOperand(1), DAG);
15478 case Intrinsic::x86_fma_vfmadd_ps:
15479 case Intrinsic::x86_fma_vfmadd_pd:
15480 case Intrinsic::x86_fma_vfmsub_ps:
15481 case Intrinsic::x86_fma_vfmsub_pd:
15482 case Intrinsic::x86_fma_vfnmadd_ps:
15483 case Intrinsic::x86_fma_vfnmadd_pd:
15484 case Intrinsic::x86_fma_vfnmsub_ps:
15485 case Intrinsic::x86_fma_vfnmsub_pd:
15486 case Intrinsic::x86_fma_vfmaddsub_ps:
15487 case Intrinsic::x86_fma_vfmaddsub_pd:
15488 case Intrinsic::x86_fma_vfmsubadd_ps:
15489 case Intrinsic::x86_fma_vfmsubadd_pd:
15490 case Intrinsic::x86_fma_vfmadd_ps_256:
15491 case Intrinsic::x86_fma_vfmadd_pd_256:
15492 case Intrinsic::x86_fma_vfmsub_ps_256:
15493 case Intrinsic::x86_fma_vfmsub_pd_256:
15494 case Intrinsic::x86_fma_vfnmadd_ps_256:
15495 case Intrinsic::x86_fma_vfnmadd_pd_256:
15496 case Intrinsic::x86_fma_vfnmsub_ps_256:
15497 case Intrinsic::x86_fma_vfnmsub_pd_256:
15498 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15499 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15500 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15501 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15502 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15503 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15507 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15508 SDValue Src, SDValue Mask, SDValue Base,
15509 SDValue Index, SDValue ScaleOp, SDValue Chain,
15510 const X86Subtarget * Subtarget) {
15512 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15513 assert(C && "Invalid scale type");
15514 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15515 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15516 Index.getSimpleValueType().getVectorNumElements());
15518 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15520 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15522 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15523 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15524 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15525 SDValue Segment = DAG.getRegister(0, MVT::i32);
15526 if (Src.getOpcode() == ISD::UNDEF)
15527 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15528 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15529 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15530 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15531 return DAG.getMergeValues(RetOps, dl);
15534 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15535 SDValue Src, SDValue Mask, SDValue Base,
15536 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15538 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15539 assert(C && "Invalid scale type");
15540 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15541 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15542 SDValue Segment = DAG.getRegister(0, MVT::i32);
15543 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15544 Index.getSimpleValueType().getVectorNumElements());
15546 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15548 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15550 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15551 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15552 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15553 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15554 return SDValue(Res, 1);
15557 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15558 SDValue Mask, SDValue Base, SDValue Index,
15559 SDValue ScaleOp, SDValue Chain) {
15561 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15562 assert(C && "Invalid scale type");
15563 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15564 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15565 SDValue Segment = DAG.getRegister(0, MVT::i32);
15567 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15569 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15571 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15573 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15574 //SDVTList VTs = DAG.getVTList(MVT::Other);
15575 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15576 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15577 return SDValue(Res, 0);
15580 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15581 // read performance monitor counters (x86_rdpmc).
15582 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15583 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15584 SmallVectorImpl<SDValue> &Results) {
15585 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15586 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15589 // The ECX register is used to select the index of the performance counter
15591 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15593 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15595 // Reads the content of a 64-bit performance counter and returns it in the
15596 // registers EDX:EAX.
15597 if (Subtarget->is64Bit()) {
15598 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15599 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15602 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15603 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15606 Chain = HI.getValue(1);
15608 if (Subtarget->is64Bit()) {
15609 // The EAX register is loaded with the low-order 32 bits. The EDX register
15610 // is loaded with the supported high-order bits of the counter.
15611 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15612 DAG.getConstant(32, MVT::i8));
15613 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15614 Results.push_back(Chain);
15618 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15619 SDValue Ops[] = { LO, HI };
15620 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15621 Results.push_back(Pair);
15622 Results.push_back(Chain);
15625 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15626 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15627 // also used to custom lower READCYCLECOUNTER nodes.
15628 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15629 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15630 SmallVectorImpl<SDValue> &Results) {
15631 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15632 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15635 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15636 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15637 // and the EAX register is loaded with the low-order 32 bits.
15638 if (Subtarget->is64Bit()) {
15639 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15640 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15643 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15644 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15647 SDValue Chain = HI.getValue(1);
15649 if (Opcode == X86ISD::RDTSCP_DAG) {
15650 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15652 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15653 // the ECX register. Add 'ecx' explicitly to the chain.
15654 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15656 // Explicitly store the content of ECX at the location passed in input
15657 // to the 'rdtscp' intrinsic.
15658 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15659 MachinePointerInfo(), false, false, 0);
15662 if (Subtarget->is64Bit()) {
15663 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15664 // the EAX register is loaded with the low-order 32 bits.
15665 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15666 DAG.getConstant(32, MVT::i8));
15667 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15668 Results.push_back(Chain);
15672 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15673 SDValue Ops[] = { LO, HI };
15674 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15675 Results.push_back(Pair);
15676 Results.push_back(Chain);
15679 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15680 SelectionDAG &DAG) {
15681 SmallVector<SDValue, 2> Results;
15683 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15685 return DAG.getMergeValues(Results, DL);
15689 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15690 SelectionDAG &DAG) {
15691 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15693 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15698 switch(IntrData->Type) {
15700 llvm_unreachable("Unknown Intrinsic Type");
15704 // Emit the node with the right value type.
15705 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15706 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15708 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15709 // Otherwise return the value from Rand, which is always 0, casted to i32.
15710 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15711 DAG.getConstant(1, Op->getValueType(1)),
15712 DAG.getConstant(X86::COND_B, MVT::i32),
15713 SDValue(Result.getNode(), 1) };
15714 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15715 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15718 // Return { result, isValid, chain }.
15719 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15720 SDValue(Result.getNode(), 2));
15723 //gather(v1, mask, index, base, scale);
15724 SDValue Chain = Op.getOperand(0);
15725 SDValue Src = Op.getOperand(2);
15726 SDValue Base = Op.getOperand(3);
15727 SDValue Index = Op.getOperand(4);
15728 SDValue Mask = Op.getOperand(5);
15729 SDValue Scale = Op.getOperand(6);
15730 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15734 //scatter(base, mask, index, v1, scale);
15735 SDValue Chain = Op.getOperand(0);
15736 SDValue Base = Op.getOperand(2);
15737 SDValue Mask = Op.getOperand(3);
15738 SDValue Index = Op.getOperand(4);
15739 SDValue Src = Op.getOperand(5);
15740 SDValue Scale = Op.getOperand(6);
15741 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15744 SDValue Hint = Op.getOperand(6);
15746 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15747 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15748 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15749 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15750 SDValue Chain = Op.getOperand(0);
15751 SDValue Mask = Op.getOperand(2);
15752 SDValue Index = Op.getOperand(3);
15753 SDValue Base = Op.getOperand(4);
15754 SDValue Scale = Op.getOperand(5);
15755 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15757 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15759 SmallVector<SDValue, 2> Results;
15760 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
15761 return DAG.getMergeValues(Results, dl);
15763 // Read Performance Monitoring Counters.
15765 SmallVector<SDValue, 2> Results;
15766 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15767 return DAG.getMergeValues(Results, dl);
15769 // XTEST intrinsics.
15771 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15772 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15773 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15774 DAG.getConstant(X86::COND_NE, MVT::i8),
15776 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15777 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15778 Ret, SDValue(InTrans.getNode(), 1));
15782 SmallVector<SDValue, 2> Results;
15783 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15784 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15785 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15786 DAG.getConstant(-1, MVT::i8));
15787 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15788 Op.getOperand(4), GenCF.getValue(1));
15789 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15790 Op.getOperand(5), MachinePointerInfo(),
15792 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15793 DAG.getConstant(X86::COND_B, MVT::i8),
15795 Results.push_back(SetCC);
15796 Results.push_back(Store);
15797 return DAG.getMergeValues(Results, dl);
15802 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15803 SelectionDAG &DAG) const {
15804 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15805 MFI->setReturnAddressIsTaken(true);
15807 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15810 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15812 EVT PtrVT = getPointerTy();
15815 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15816 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15817 DAG.getSubtarget().getRegisterInfo());
15818 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15819 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15820 DAG.getNode(ISD::ADD, dl, PtrVT,
15821 FrameAddr, Offset),
15822 MachinePointerInfo(), false, false, false, 0);
15825 // Just load the return address.
15826 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15827 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15828 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15831 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15832 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15833 MFI->setFrameAddressIsTaken(true);
15835 EVT VT = Op.getValueType();
15836 SDLoc dl(Op); // FIXME probably not meaningful
15837 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15838 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15839 DAG.getSubtarget().getRegisterInfo());
15840 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15841 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15842 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15843 "Invalid Frame Register!");
15844 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15846 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15847 MachinePointerInfo(),
15848 false, false, false, 0);
15852 // FIXME? Maybe this could be a TableGen attribute on some registers and
15853 // this table could be generated automatically from RegInfo.
15854 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15856 unsigned Reg = StringSwitch<unsigned>(RegName)
15857 .Case("esp", X86::ESP)
15858 .Case("rsp", X86::RSP)
15862 report_fatal_error("Invalid register name global variable");
15865 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15866 SelectionDAG &DAG) const {
15867 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15868 DAG.getSubtarget().getRegisterInfo());
15869 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15872 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15873 SDValue Chain = Op.getOperand(0);
15874 SDValue Offset = Op.getOperand(1);
15875 SDValue Handler = Op.getOperand(2);
15878 EVT PtrVT = getPointerTy();
15879 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15880 DAG.getSubtarget().getRegisterInfo());
15881 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15882 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15883 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15884 "Invalid Frame Register!");
15885 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15886 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15888 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15889 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15890 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15891 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15893 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15895 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15896 DAG.getRegister(StoreAddrReg, PtrVT));
15899 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15900 SelectionDAG &DAG) const {
15902 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15903 DAG.getVTList(MVT::i32, MVT::Other),
15904 Op.getOperand(0), Op.getOperand(1));
15907 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15908 SelectionDAG &DAG) const {
15910 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15911 Op.getOperand(0), Op.getOperand(1));
15914 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15915 return Op.getOperand(0);
15918 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15919 SelectionDAG &DAG) const {
15920 SDValue Root = Op.getOperand(0);
15921 SDValue Trmp = Op.getOperand(1); // trampoline
15922 SDValue FPtr = Op.getOperand(2); // nested function
15923 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15926 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15927 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
15929 if (Subtarget->is64Bit()) {
15930 SDValue OutChains[6];
15932 // Large code-model.
15933 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15934 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15936 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15937 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15939 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15941 // Load the pointer to the nested function into R11.
15942 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15943 SDValue Addr = Trmp;
15944 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15945 Addr, MachinePointerInfo(TrmpAddr),
15948 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15949 DAG.getConstant(2, MVT::i64));
15950 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15951 MachinePointerInfo(TrmpAddr, 2),
15954 // Load the 'nest' parameter value into R10.
15955 // R10 is specified in X86CallingConv.td
15956 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15957 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15958 DAG.getConstant(10, MVT::i64));
15959 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15960 Addr, MachinePointerInfo(TrmpAddr, 10),
15963 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15964 DAG.getConstant(12, MVT::i64));
15965 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15966 MachinePointerInfo(TrmpAddr, 12),
15969 // Jump to the nested function.
15970 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15971 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15972 DAG.getConstant(20, MVT::i64));
15973 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15974 Addr, MachinePointerInfo(TrmpAddr, 20),
15977 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15978 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15979 DAG.getConstant(22, MVT::i64));
15980 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15981 MachinePointerInfo(TrmpAddr, 22),
15984 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15986 const Function *Func =
15987 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15988 CallingConv::ID CC = Func->getCallingConv();
15993 llvm_unreachable("Unsupported calling convention");
15994 case CallingConv::C:
15995 case CallingConv::X86_StdCall: {
15996 // Pass 'nest' parameter in ECX.
15997 // Must be kept in sync with X86CallingConv.td
15998 NestReg = X86::ECX;
16000 // Check that ECX wasn't needed by an 'inreg' parameter.
16001 FunctionType *FTy = Func->getFunctionType();
16002 const AttributeSet &Attrs = Func->getAttributes();
16004 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16005 unsigned InRegCount = 0;
16008 for (FunctionType::param_iterator I = FTy->param_begin(),
16009 E = FTy->param_end(); I != E; ++I, ++Idx)
16010 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16011 // FIXME: should only count parameters that are lowered to integers.
16012 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16014 if (InRegCount > 2) {
16015 report_fatal_error("Nest register in use - reduce number of inreg"
16021 case CallingConv::X86_FastCall:
16022 case CallingConv::X86_ThisCall:
16023 case CallingConv::Fast:
16024 // Pass 'nest' parameter in EAX.
16025 // Must be kept in sync with X86CallingConv.td
16026 NestReg = X86::EAX;
16030 SDValue OutChains[4];
16031 SDValue Addr, Disp;
16033 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16034 DAG.getConstant(10, MVT::i32));
16035 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16037 // This is storing the opcode for MOV32ri.
16038 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16039 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16040 OutChains[0] = DAG.getStore(Root, dl,
16041 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16042 Trmp, MachinePointerInfo(TrmpAddr),
16045 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16046 DAG.getConstant(1, MVT::i32));
16047 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16048 MachinePointerInfo(TrmpAddr, 1),
16051 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16052 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16053 DAG.getConstant(5, MVT::i32));
16054 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16055 MachinePointerInfo(TrmpAddr, 5),
16058 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16059 DAG.getConstant(6, MVT::i32));
16060 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16061 MachinePointerInfo(TrmpAddr, 6),
16064 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16068 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16069 SelectionDAG &DAG) const {
16071 The rounding mode is in bits 11:10 of FPSR, and has the following
16073 00 Round to nearest
16078 FLT_ROUNDS, on the other hand, expects the following:
16085 To perform the conversion, we do:
16086 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16089 MachineFunction &MF = DAG.getMachineFunction();
16090 const TargetMachine &TM = MF.getTarget();
16091 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16092 unsigned StackAlignment = TFI.getStackAlignment();
16093 MVT VT = Op.getSimpleValueType();
16096 // Save FP Control Word to stack slot
16097 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16098 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16100 MachineMemOperand *MMO =
16101 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16102 MachineMemOperand::MOStore, 2, 2);
16104 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16105 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16106 DAG.getVTList(MVT::Other),
16107 Ops, MVT::i16, MMO);
16109 // Load FP Control Word from stack slot
16110 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16111 MachinePointerInfo(), false, false, false, 0);
16113 // Transform as necessary
16115 DAG.getNode(ISD::SRL, DL, MVT::i16,
16116 DAG.getNode(ISD::AND, DL, MVT::i16,
16117 CWD, DAG.getConstant(0x800, MVT::i16)),
16118 DAG.getConstant(11, MVT::i8));
16120 DAG.getNode(ISD::SRL, DL, MVT::i16,
16121 DAG.getNode(ISD::AND, DL, MVT::i16,
16122 CWD, DAG.getConstant(0x400, MVT::i16)),
16123 DAG.getConstant(9, MVT::i8));
16126 DAG.getNode(ISD::AND, DL, MVT::i16,
16127 DAG.getNode(ISD::ADD, DL, MVT::i16,
16128 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16129 DAG.getConstant(1, MVT::i16)),
16130 DAG.getConstant(3, MVT::i16));
16132 return DAG.getNode((VT.getSizeInBits() < 16 ?
16133 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16136 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16137 MVT VT = Op.getSimpleValueType();
16139 unsigned NumBits = VT.getSizeInBits();
16142 Op = Op.getOperand(0);
16143 if (VT == MVT::i8) {
16144 // Zero extend to i32 since there is not an i8 bsr.
16146 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16149 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16150 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16151 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16153 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16156 DAG.getConstant(NumBits+NumBits-1, OpVT),
16157 DAG.getConstant(X86::COND_E, MVT::i8),
16160 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16162 // Finally xor with NumBits-1.
16163 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16166 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16170 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16171 MVT VT = Op.getSimpleValueType();
16173 unsigned NumBits = VT.getSizeInBits();
16176 Op = Op.getOperand(0);
16177 if (VT == MVT::i8) {
16178 // Zero extend to i32 since there is not an i8 bsr.
16180 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16183 // Issue a bsr (scan bits in reverse).
16184 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16185 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16187 // And xor with NumBits-1.
16188 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16191 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16195 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16196 MVT VT = Op.getSimpleValueType();
16197 unsigned NumBits = VT.getSizeInBits();
16199 Op = Op.getOperand(0);
16201 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16202 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16203 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16205 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16208 DAG.getConstant(NumBits, VT),
16209 DAG.getConstant(X86::COND_E, MVT::i8),
16212 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16215 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16216 // ones, and then concatenate the result back.
16217 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16218 MVT VT = Op.getSimpleValueType();
16220 assert(VT.is256BitVector() && VT.isInteger() &&
16221 "Unsupported value type for operation");
16223 unsigned NumElems = VT.getVectorNumElements();
16226 // Extract the LHS vectors
16227 SDValue LHS = Op.getOperand(0);
16228 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16229 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16231 // Extract the RHS vectors
16232 SDValue RHS = Op.getOperand(1);
16233 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16234 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16236 MVT EltVT = VT.getVectorElementType();
16237 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16239 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16240 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16241 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16244 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16245 assert(Op.getSimpleValueType().is256BitVector() &&
16246 Op.getSimpleValueType().isInteger() &&
16247 "Only handle AVX 256-bit vector integer operation");
16248 return Lower256IntArith(Op, DAG);
16251 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16252 assert(Op.getSimpleValueType().is256BitVector() &&
16253 Op.getSimpleValueType().isInteger() &&
16254 "Only handle AVX 256-bit vector integer operation");
16255 return Lower256IntArith(Op, DAG);
16258 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16259 SelectionDAG &DAG) {
16261 MVT VT = Op.getSimpleValueType();
16263 // Decompose 256-bit ops into smaller 128-bit ops.
16264 if (VT.is256BitVector() && !Subtarget->hasInt256())
16265 return Lower256IntArith(Op, DAG);
16267 SDValue A = Op.getOperand(0);
16268 SDValue B = Op.getOperand(1);
16270 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16271 if (VT == MVT::v4i32) {
16272 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16273 "Should not custom lower when pmuldq is available!");
16275 // Extract the odd parts.
16276 static const int UnpackMask[] = { 1, -1, 3, -1 };
16277 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16278 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16280 // Multiply the even parts.
16281 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16282 // Now multiply odd parts.
16283 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16285 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16286 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16288 // Merge the two vectors back together with a shuffle. This expands into 2
16290 static const int ShufMask[] = { 0, 4, 2, 6 };
16291 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16294 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16295 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16297 // Ahi = psrlqi(a, 32);
16298 // Bhi = psrlqi(b, 32);
16300 // AloBlo = pmuludq(a, b);
16301 // AloBhi = pmuludq(a, Bhi);
16302 // AhiBlo = pmuludq(Ahi, b);
16304 // AloBhi = psllqi(AloBhi, 32);
16305 // AhiBlo = psllqi(AhiBlo, 32);
16306 // return AloBlo + AloBhi + AhiBlo;
16308 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16309 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16311 // Bit cast to 32-bit vectors for MULUDQ
16312 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16313 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16314 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16315 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16316 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16317 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16319 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16320 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16321 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16323 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16324 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16326 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16327 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16330 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16331 assert(Subtarget->isTargetWin64() && "Unexpected target");
16332 EVT VT = Op.getValueType();
16333 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16334 "Unexpected return type for lowering");
16338 switch (Op->getOpcode()) {
16339 default: llvm_unreachable("Unexpected request for libcall!");
16340 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16341 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16342 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16343 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16344 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16345 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16349 SDValue InChain = DAG.getEntryNode();
16351 TargetLowering::ArgListTy Args;
16352 TargetLowering::ArgListEntry Entry;
16353 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16354 EVT ArgVT = Op->getOperand(i).getValueType();
16355 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16356 "Unexpected argument type for lowering");
16357 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16358 Entry.Node = StackPtr;
16359 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16361 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16362 Entry.Ty = PointerType::get(ArgTy,0);
16363 Entry.isSExt = false;
16364 Entry.isZExt = false;
16365 Args.push_back(Entry);
16368 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16371 TargetLowering::CallLoweringInfo CLI(DAG);
16372 CLI.setDebugLoc(dl).setChain(InChain)
16373 .setCallee(getLibcallCallingConv(LC),
16374 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16375 Callee, std::move(Args), 0)
16376 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16378 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16379 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16382 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16383 SelectionDAG &DAG) {
16384 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16385 EVT VT = Op0.getValueType();
16388 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16389 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16391 // PMULxD operations multiply each even value (starting at 0) of LHS with
16392 // the related value of RHS and produce a widen result.
16393 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16394 // => <2 x i64> <ae|cg>
16396 // In other word, to have all the results, we need to perform two PMULxD:
16397 // 1. one with the even values.
16398 // 2. one with the odd values.
16399 // To achieve #2, with need to place the odd values at an even position.
16401 // Place the odd value at an even position (basically, shift all values 1
16402 // step to the left):
16403 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16404 // <a|b|c|d> => <b|undef|d|undef>
16405 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16406 // <e|f|g|h> => <f|undef|h|undef>
16407 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16409 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16411 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16412 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16414 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16415 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16416 // => <2 x i64> <ae|cg>
16417 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16418 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16419 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16420 // => <2 x i64> <bf|dh>
16421 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16422 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16424 // Shuffle it back into the right order.
16425 SDValue Highs, Lows;
16426 if (VT == MVT::v8i32) {
16427 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16428 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16429 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16430 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16432 const int HighMask[] = {1, 5, 3, 7};
16433 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16434 const int LowMask[] = {0, 4, 2, 6};
16435 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16438 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16439 // unsigned multiply.
16440 if (IsSigned && !Subtarget->hasSSE41()) {
16442 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16443 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16444 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16445 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16446 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16448 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16449 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16452 // The first result of MUL_LOHI is actually the low value, followed by the
16454 SDValue Ops[] = {Lows, Highs};
16455 return DAG.getMergeValues(Ops, dl);
16458 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16459 const X86Subtarget *Subtarget) {
16460 MVT VT = Op.getSimpleValueType();
16462 SDValue R = Op.getOperand(0);
16463 SDValue Amt = Op.getOperand(1);
16465 // Optimize shl/srl/sra with constant shift amount.
16466 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16467 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16468 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16470 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16471 (Subtarget->hasInt256() &&
16472 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16473 (Subtarget->hasAVX512() &&
16474 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16475 if (Op.getOpcode() == ISD::SHL)
16476 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16478 if (Op.getOpcode() == ISD::SRL)
16479 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16481 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16482 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16486 if (VT == MVT::v16i8) {
16487 if (Op.getOpcode() == ISD::SHL) {
16488 // Make a large shift.
16489 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16490 MVT::v8i16, R, ShiftAmt,
16492 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16493 // Zero out the rightmost bits.
16494 SmallVector<SDValue, 16> V(16,
16495 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16497 return DAG.getNode(ISD::AND, dl, VT, SHL,
16498 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16500 if (Op.getOpcode() == ISD::SRL) {
16501 // Make a large shift.
16502 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16503 MVT::v8i16, R, ShiftAmt,
16505 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16506 // Zero out the leftmost bits.
16507 SmallVector<SDValue, 16> V(16,
16508 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16510 return DAG.getNode(ISD::AND, dl, VT, SRL,
16511 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16513 if (Op.getOpcode() == ISD::SRA) {
16514 if (ShiftAmt == 7) {
16515 // R s>> 7 === R s< 0
16516 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16517 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16520 // R s>> a === ((R u>> a) ^ m) - m
16521 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16522 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16524 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16525 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16526 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16529 llvm_unreachable("Unknown shift opcode.");
16532 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16533 if (Op.getOpcode() == ISD::SHL) {
16534 // Make a large shift.
16535 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16536 MVT::v16i16, R, ShiftAmt,
16538 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16539 // Zero out the rightmost bits.
16540 SmallVector<SDValue, 32> V(32,
16541 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16543 return DAG.getNode(ISD::AND, dl, VT, SHL,
16544 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16546 if (Op.getOpcode() == ISD::SRL) {
16547 // Make a large shift.
16548 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16549 MVT::v16i16, R, ShiftAmt,
16551 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16552 // Zero out the leftmost bits.
16553 SmallVector<SDValue, 32> V(32,
16554 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16556 return DAG.getNode(ISD::AND, dl, VT, SRL,
16557 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16559 if (Op.getOpcode() == ISD::SRA) {
16560 if (ShiftAmt == 7) {
16561 // R s>> 7 === R s< 0
16562 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16563 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16566 // R s>> a === ((R u>> a) ^ m) - m
16567 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16568 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16570 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16571 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16572 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16575 llvm_unreachable("Unknown shift opcode.");
16580 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16581 if (!Subtarget->is64Bit() &&
16582 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16583 Amt.getOpcode() == ISD::BITCAST &&
16584 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16585 Amt = Amt.getOperand(0);
16586 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16587 VT.getVectorNumElements();
16588 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16589 uint64_t ShiftAmt = 0;
16590 for (unsigned i = 0; i != Ratio; ++i) {
16591 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16595 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16597 // Check remaining shift amounts.
16598 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16599 uint64_t ShAmt = 0;
16600 for (unsigned j = 0; j != Ratio; ++j) {
16601 ConstantSDNode *C =
16602 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16606 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16608 if (ShAmt != ShiftAmt)
16611 switch (Op.getOpcode()) {
16613 llvm_unreachable("Unknown shift opcode!");
16615 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16618 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16621 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16629 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16630 const X86Subtarget* Subtarget) {
16631 MVT VT = Op.getSimpleValueType();
16633 SDValue R = Op.getOperand(0);
16634 SDValue Amt = Op.getOperand(1);
16636 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16637 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16638 (Subtarget->hasInt256() &&
16639 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16640 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16641 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16643 EVT EltVT = VT.getVectorElementType();
16645 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16646 unsigned NumElts = VT.getVectorNumElements();
16648 for (i = 0; i != NumElts; ++i) {
16649 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16653 for (j = i; j != NumElts; ++j) {
16654 SDValue Arg = Amt.getOperand(j);
16655 if (Arg.getOpcode() == ISD::UNDEF) continue;
16656 if (Arg != Amt.getOperand(i))
16659 if (i != NumElts && j == NumElts)
16660 BaseShAmt = Amt.getOperand(i);
16662 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16663 Amt = Amt.getOperand(0);
16664 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16665 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16666 SDValue InVec = Amt.getOperand(0);
16667 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16668 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16670 for (; i != NumElts; ++i) {
16671 SDValue Arg = InVec.getOperand(i);
16672 if (Arg.getOpcode() == ISD::UNDEF) continue;
16676 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16677 if (ConstantSDNode *C =
16678 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16679 unsigned SplatIdx =
16680 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16681 if (C->getZExtValue() == SplatIdx)
16682 BaseShAmt = InVec.getOperand(1);
16685 if (!BaseShAmt.getNode())
16686 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16687 DAG.getIntPtrConstant(0));
16691 if (BaseShAmt.getNode()) {
16692 if (EltVT.bitsGT(MVT::i32))
16693 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16694 else if (EltVT.bitsLT(MVT::i32))
16695 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16697 switch (Op.getOpcode()) {
16699 llvm_unreachable("Unknown shift opcode!");
16701 switch (VT.SimpleTy) {
16702 default: return SDValue();
16711 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16714 switch (VT.SimpleTy) {
16715 default: return SDValue();
16722 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16725 switch (VT.SimpleTy) {
16726 default: return SDValue();
16735 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16741 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16742 if (!Subtarget->is64Bit() &&
16743 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16744 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16745 Amt.getOpcode() == ISD::BITCAST &&
16746 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16747 Amt = Amt.getOperand(0);
16748 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16749 VT.getVectorNumElements();
16750 std::vector<SDValue> Vals(Ratio);
16751 for (unsigned i = 0; i != Ratio; ++i)
16752 Vals[i] = Amt.getOperand(i);
16753 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16754 for (unsigned j = 0; j != Ratio; ++j)
16755 if (Vals[j] != Amt.getOperand(i + j))
16758 switch (Op.getOpcode()) {
16760 llvm_unreachable("Unknown shift opcode!");
16762 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16764 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16766 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16773 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16774 SelectionDAG &DAG) {
16775 MVT VT = Op.getSimpleValueType();
16777 SDValue R = Op.getOperand(0);
16778 SDValue Amt = Op.getOperand(1);
16781 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16782 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16784 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16788 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16792 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16794 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16795 if (Subtarget->hasInt256()) {
16796 if (Op.getOpcode() == ISD::SRL &&
16797 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16798 VT == MVT::v4i64 || VT == MVT::v8i32))
16800 if (Op.getOpcode() == ISD::SHL &&
16801 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16802 VT == MVT::v4i64 || VT == MVT::v8i32))
16804 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16808 // If possible, lower this packed shift into a vector multiply instead of
16809 // expanding it into a sequence of scalar shifts.
16810 // Do this only if the vector shift count is a constant build_vector.
16811 if (Op.getOpcode() == ISD::SHL &&
16812 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16813 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16814 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16815 SmallVector<SDValue, 8> Elts;
16816 EVT SVT = VT.getScalarType();
16817 unsigned SVTBits = SVT.getSizeInBits();
16818 const APInt &One = APInt(SVTBits, 1);
16819 unsigned NumElems = VT.getVectorNumElements();
16821 for (unsigned i=0; i !=NumElems; ++i) {
16822 SDValue Op = Amt->getOperand(i);
16823 if (Op->getOpcode() == ISD::UNDEF) {
16824 Elts.push_back(Op);
16828 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16829 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16830 uint64_t ShAmt = C.getZExtValue();
16831 if (ShAmt >= SVTBits) {
16832 Elts.push_back(DAG.getUNDEF(SVT));
16835 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16837 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16838 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16841 // Lower SHL with variable shift amount.
16842 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16843 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16845 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16846 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16847 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16848 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16851 // If possible, lower this shift as a sequence of two shifts by
16852 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16854 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16856 // Could be rewritten as:
16857 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16859 // The advantage is that the two shifts from the example would be
16860 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16861 // the vector shift into four scalar shifts plus four pairs of vector
16863 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16864 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16865 unsigned TargetOpcode = X86ISD::MOVSS;
16866 bool CanBeSimplified;
16867 // The splat value for the first packed shift (the 'X' from the example).
16868 SDValue Amt1 = Amt->getOperand(0);
16869 // The splat value for the second packed shift (the 'Y' from the example).
16870 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16871 Amt->getOperand(2);
16873 // See if it is possible to replace this node with a sequence of
16874 // two shifts followed by a MOVSS/MOVSD
16875 if (VT == MVT::v4i32) {
16876 // Check if it is legal to use a MOVSS.
16877 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16878 Amt2 == Amt->getOperand(3);
16879 if (!CanBeSimplified) {
16880 // Otherwise, check if we can still simplify this node using a MOVSD.
16881 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16882 Amt->getOperand(2) == Amt->getOperand(3);
16883 TargetOpcode = X86ISD::MOVSD;
16884 Amt2 = Amt->getOperand(2);
16887 // Do similar checks for the case where the machine value type
16889 CanBeSimplified = Amt1 == Amt->getOperand(1);
16890 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16891 CanBeSimplified = Amt2 == Amt->getOperand(i);
16893 if (!CanBeSimplified) {
16894 TargetOpcode = X86ISD::MOVSD;
16895 CanBeSimplified = true;
16896 Amt2 = Amt->getOperand(4);
16897 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16898 CanBeSimplified = Amt1 == Amt->getOperand(i);
16899 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16900 CanBeSimplified = Amt2 == Amt->getOperand(j);
16904 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16905 isa<ConstantSDNode>(Amt2)) {
16906 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16907 EVT CastVT = MVT::v4i32;
16909 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16910 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16912 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16913 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16914 if (TargetOpcode == X86ISD::MOVSD)
16915 CastVT = MVT::v2i64;
16916 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16917 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16918 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16920 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16924 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16925 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16928 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16929 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16931 // Turn 'a' into a mask suitable for VSELECT
16932 SDValue VSelM = DAG.getConstant(0x80, VT);
16933 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16934 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16936 SDValue CM1 = DAG.getConstant(0x0f, VT);
16937 SDValue CM2 = DAG.getConstant(0x3f, VT);
16939 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16940 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16941 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16942 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16943 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16946 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16947 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16948 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16950 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16951 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16952 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16953 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16954 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16957 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16958 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16959 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16961 // return VSELECT(r, r+r, a);
16962 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16963 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16967 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16968 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16969 // solution better.
16970 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16971 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16973 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16974 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16975 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16976 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16977 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16980 // Decompose 256-bit shifts into smaller 128-bit shifts.
16981 if (VT.is256BitVector()) {
16982 unsigned NumElems = VT.getVectorNumElements();
16983 MVT EltVT = VT.getVectorElementType();
16984 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16986 // Extract the two vectors
16987 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16988 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16990 // Recreate the shift amount vectors
16991 SDValue Amt1, Amt2;
16992 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16993 // Constant shift amount
16994 SmallVector<SDValue, 4> Amt1Csts;
16995 SmallVector<SDValue, 4> Amt2Csts;
16996 for (unsigned i = 0; i != NumElems/2; ++i)
16997 Amt1Csts.push_back(Amt->getOperand(i));
16998 for (unsigned i = NumElems/2; i != NumElems; ++i)
16999 Amt2Csts.push_back(Amt->getOperand(i));
17001 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17002 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17004 // Variable shift amount
17005 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17006 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17009 // Issue new vector shifts for the smaller types
17010 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17011 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17013 // Concatenate the result back
17014 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17020 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17021 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17022 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17023 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17024 // has only one use.
17025 SDNode *N = Op.getNode();
17026 SDValue LHS = N->getOperand(0);
17027 SDValue RHS = N->getOperand(1);
17028 unsigned BaseOp = 0;
17031 switch (Op.getOpcode()) {
17032 default: llvm_unreachable("Unknown ovf instruction!");
17034 // A subtract of one will be selected as a INC. Note that INC doesn't
17035 // set CF, so we can't do this for UADDO.
17036 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17038 BaseOp = X86ISD::INC;
17039 Cond = X86::COND_O;
17042 BaseOp = X86ISD::ADD;
17043 Cond = X86::COND_O;
17046 BaseOp = X86ISD::ADD;
17047 Cond = X86::COND_B;
17050 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17051 // set CF, so we can't do this for USUBO.
17052 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17054 BaseOp = X86ISD::DEC;
17055 Cond = X86::COND_O;
17058 BaseOp = X86ISD::SUB;
17059 Cond = X86::COND_O;
17062 BaseOp = X86ISD::SUB;
17063 Cond = X86::COND_B;
17066 BaseOp = X86ISD::SMUL;
17067 Cond = X86::COND_O;
17069 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17070 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17072 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17075 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17076 DAG.getConstant(X86::COND_O, MVT::i32),
17077 SDValue(Sum.getNode(), 2));
17079 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17083 // Also sets EFLAGS.
17084 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17085 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17088 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17089 DAG.getConstant(Cond, MVT::i32),
17090 SDValue(Sum.getNode(), 1));
17092 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17095 // Sign extension of the low part of vector elements. This may be used either
17096 // when sign extend instructions are not available or if the vector element
17097 // sizes already match the sign-extended size. If the vector elements are in
17098 // their pre-extended size and sign extend instructions are available, that will
17099 // be handled by LowerSIGN_EXTEND.
17100 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17101 SelectionDAG &DAG) const {
17103 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17104 MVT VT = Op.getSimpleValueType();
17106 if (!Subtarget->hasSSE2() || !VT.isVector())
17109 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17110 ExtraVT.getScalarType().getSizeInBits();
17112 switch (VT.SimpleTy) {
17113 default: return SDValue();
17116 if (!Subtarget->hasFp256())
17118 if (!Subtarget->hasInt256()) {
17119 // needs to be split
17120 unsigned NumElems = VT.getVectorNumElements();
17122 // Extract the LHS vectors
17123 SDValue LHS = Op.getOperand(0);
17124 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17125 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17127 MVT EltVT = VT.getVectorElementType();
17128 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17130 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17131 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17132 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17134 SDValue Extra = DAG.getValueType(ExtraVT);
17136 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17137 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17139 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17144 SDValue Op0 = Op.getOperand(0);
17146 // This is a sign extension of some low part of vector elements without
17147 // changing the size of the vector elements themselves:
17148 // Shift-Left + Shift-Right-Algebraic.
17149 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17151 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17157 /// Returns true if the operand type is exactly twice the native width, and
17158 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17159 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17160 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17161 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17162 const X86Subtarget &Subtarget =
17163 getTargetMachine().getSubtarget<X86Subtarget>();
17164 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17167 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17168 else if (OpWidth == 128)
17169 return Subtarget.hasCmpxchg16b();
17174 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17175 return needsCmpXchgNb(SI->getValueOperand()->getType());
17178 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *SI) const {
17179 return false; // FIXME, currently these are expanded separately in this file.
17182 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17183 const X86Subtarget &Subtarget =
17184 getTargetMachine().getSubtarget<X86Subtarget>();
17185 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17186 const Type *MemType = AI->getType();
17188 // If the operand is too big, we must see if cmpxchg8/16b is available
17189 // and default to library calls otherwise.
17190 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17191 return needsCmpXchgNb(MemType);
17193 AtomicRMWInst::BinOp Op = AI->getOperation();
17196 llvm_unreachable("Unknown atomic operation");
17197 case AtomicRMWInst::Xchg:
17198 case AtomicRMWInst::Add:
17199 case AtomicRMWInst::Sub:
17200 // It's better to use xadd, xsub or xchg for these in all cases.
17202 case AtomicRMWInst::Or:
17203 case AtomicRMWInst::And:
17204 case AtomicRMWInst::Xor:
17205 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17206 // prefix to a normal instruction for these operations.
17207 return !AI->use_empty();
17208 case AtomicRMWInst::Nand:
17209 case AtomicRMWInst::Max:
17210 case AtomicRMWInst::Min:
17211 case AtomicRMWInst::UMax:
17212 case AtomicRMWInst::UMin:
17213 // These always require a non-trivial set of data operations on x86. We must
17214 // use a cmpxchg loop.
17219 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17220 SelectionDAG &DAG) {
17222 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17223 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17224 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17225 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17227 // The only fence that needs an instruction is a sequentially-consistent
17228 // cross-thread fence.
17229 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17230 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17231 // no-sse2). There isn't any reason to disable it if the target processor
17233 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
17234 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17236 SDValue Chain = Op.getOperand(0);
17237 SDValue Zero = DAG.getConstant(0, MVT::i32);
17239 DAG.getRegister(X86::ESP, MVT::i32), // Base
17240 DAG.getTargetConstant(1, MVT::i8), // Scale
17241 DAG.getRegister(0, MVT::i32), // Index
17242 DAG.getTargetConstant(0, MVT::i32), // Disp
17243 DAG.getRegister(0, MVT::i32), // Segment.
17247 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17248 return SDValue(Res, 0);
17251 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17252 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17255 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17256 SelectionDAG &DAG) {
17257 MVT T = Op.getSimpleValueType();
17261 switch(T.SimpleTy) {
17262 default: llvm_unreachable("Invalid value type!");
17263 case MVT::i8: Reg = X86::AL; size = 1; break;
17264 case MVT::i16: Reg = X86::AX; size = 2; break;
17265 case MVT::i32: Reg = X86::EAX; size = 4; break;
17267 assert(Subtarget->is64Bit() && "Node not type legal!");
17268 Reg = X86::RAX; size = 8;
17271 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17272 Op.getOperand(2), SDValue());
17273 SDValue Ops[] = { cpIn.getValue(0),
17276 DAG.getTargetConstant(size, MVT::i8),
17277 cpIn.getValue(1) };
17278 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17279 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17280 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17284 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17285 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17286 MVT::i32, cpOut.getValue(2));
17287 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17288 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17290 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17291 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17292 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17296 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17297 SelectionDAG &DAG) {
17298 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17299 MVT DstVT = Op.getSimpleValueType();
17301 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17302 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17303 if (DstVT != MVT::f64)
17304 // This conversion needs to be expanded.
17307 SDValue InVec = Op->getOperand(0);
17309 unsigned NumElts = SrcVT.getVectorNumElements();
17310 EVT SVT = SrcVT.getVectorElementType();
17312 // Widen the vector in input in the case of MVT::v2i32.
17313 // Example: from MVT::v2i32 to MVT::v4i32.
17314 SmallVector<SDValue, 16> Elts;
17315 for (unsigned i = 0, e = NumElts; i != e; ++i)
17316 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17317 DAG.getIntPtrConstant(i)));
17319 // Explicitly mark the extra elements as Undef.
17320 SDValue Undef = DAG.getUNDEF(SVT);
17321 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17322 Elts.push_back(Undef);
17324 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17325 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17326 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17327 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17328 DAG.getIntPtrConstant(0));
17331 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17332 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17333 assert((DstVT == MVT::i64 ||
17334 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17335 "Unexpected custom BITCAST");
17336 // i64 <=> MMX conversions are Legal.
17337 if (SrcVT==MVT::i64 && DstVT.isVector())
17339 if (DstVT==MVT::i64 && SrcVT.isVector())
17341 // MMX <=> MMX conversions are Legal.
17342 if (SrcVT.isVector() && DstVT.isVector())
17344 // All other conversions need to be expanded.
17348 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17349 SDNode *Node = Op.getNode();
17351 EVT T = Node->getValueType(0);
17352 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17353 DAG.getConstant(0, T), Node->getOperand(2));
17354 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17355 cast<AtomicSDNode>(Node)->getMemoryVT(),
17356 Node->getOperand(0),
17357 Node->getOperand(1), negOp,
17358 cast<AtomicSDNode>(Node)->getMemOperand(),
17359 cast<AtomicSDNode>(Node)->getOrdering(),
17360 cast<AtomicSDNode>(Node)->getSynchScope());
17363 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17364 SDNode *Node = Op.getNode();
17366 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17368 // Convert seq_cst store -> xchg
17369 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17370 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17371 // (The only way to get a 16-byte store is cmpxchg16b)
17372 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17373 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17374 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17375 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17376 cast<AtomicSDNode>(Node)->getMemoryVT(),
17377 Node->getOperand(0),
17378 Node->getOperand(1), Node->getOperand(2),
17379 cast<AtomicSDNode>(Node)->getMemOperand(),
17380 cast<AtomicSDNode>(Node)->getOrdering(),
17381 cast<AtomicSDNode>(Node)->getSynchScope());
17382 return Swap.getValue(1);
17384 // Other atomic stores have a simple pattern.
17388 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17389 EVT VT = Op.getNode()->getSimpleValueType(0);
17391 // Let legalize expand this if it isn't a legal type yet.
17392 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17395 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17398 bool ExtraOp = false;
17399 switch (Op.getOpcode()) {
17400 default: llvm_unreachable("Invalid code");
17401 case ISD::ADDC: Opc = X86ISD::ADD; break;
17402 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17403 case ISD::SUBC: Opc = X86ISD::SUB; break;
17404 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17408 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17410 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17411 Op.getOperand(1), Op.getOperand(2));
17414 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17415 SelectionDAG &DAG) {
17416 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17418 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17419 // which returns the values as { float, float } (in XMM0) or
17420 // { double, double } (which is returned in XMM0, XMM1).
17422 SDValue Arg = Op.getOperand(0);
17423 EVT ArgVT = Arg.getValueType();
17424 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17426 TargetLowering::ArgListTy Args;
17427 TargetLowering::ArgListEntry Entry;
17431 Entry.isSExt = false;
17432 Entry.isZExt = false;
17433 Args.push_back(Entry);
17435 bool isF64 = ArgVT == MVT::f64;
17436 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17437 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17438 // the results are returned via SRet in memory.
17439 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17440 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17441 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17443 Type *RetTy = isF64
17444 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17445 : (Type*)VectorType::get(ArgTy, 4);
17447 TargetLowering::CallLoweringInfo CLI(DAG);
17448 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17449 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17451 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17454 // Returned in xmm0 and xmm1.
17455 return CallResult.first;
17457 // Returned in bits 0:31 and 32:64 xmm0.
17458 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17459 CallResult.first, DAG.getIntPtrConstant(0));
17460 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17461 CallResult.first, DAG.getIntPtrConstant(1));
17462 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17463 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17466 /// LowerOperation - Provide custom lowering hooks for some operations.
17468 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17469 switch (Op.getOpcode()) {
17470 default: llvm_unreachable("Should not custom lower this!");
17471 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17472 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17473 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17474 return LowerCMP_SWAP(Op, Subtarget, DAG);
17475 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17476 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17477 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17478 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17479 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17480 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17481 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17482 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17483 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17484 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17485 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17486 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17487 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17488 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17489 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17490 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17491 case ISD::SHL_PARTS:
17492 case ISD::SRA_PARTS:
17493 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17494 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17495 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17496 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17497 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17498 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17499 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17500 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17501 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17502 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17503 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17505 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17506 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17507 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17508 case ISD::SETCC: return LowerSETCC(Op, DAG);
17509 case ISD::SELECT: return LowerSELECT(Op, DAG);
17510 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17511 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17512 case ISD::VASTART: return LowerVASTART(Op, DAG);
17513 case ISD::VAARG: return LowerVAARG(Op, DAG);
17514 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17515 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17516 case ISD::INTRINSIC_VOID:
17517 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17518 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17519 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17520 case ISD::FRAME_TO_ARGS_OFFSET:
17521 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17522 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17523 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17524 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17525 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17526 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17527 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17528 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17529 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17530 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17531 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17532 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17533 case ISD::UMUL_LOHI:
17534 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17537 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17543 case ISD::UMULO: return LowerXALUO(Op, DAG);
17544 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17545 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17549 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17550 case ISD::ADD: return LowerADD(Op, DAG);
17551 case ISD::SUB: return LowerSUB(Op, DAG);
17552 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17556 static void ReplaceATOMIC_LOAD(SDNode *Node,
17557 SmallVectorImpl<SDValue> &Results,
17558 SelectionDAG &DAG) {
17560 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17562 // Convert wide load -> cmpxchg8b/cmpxchg16b
17563 // FIXME: On 32-bit, load -> fild or movq would be more efficient
17564 // (The only way to get a 16-byte load is cmpxchg16b)
17565 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
17566 SDValue Zero = DAG.getConstant(0, VT);
17567 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
17569 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
17570 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
17571 cast<AtomicSDNode>(Node)->getMemOperand(),
17572 cast<AtomicSDNode>(Node)->getOrdering(),
17573 cast<AtomicSDNode>(Node)->getOrdering(),
17574 cast<AtomicSDNode>(Node)->getSynchScope());
17575 Results.push_back(Swap.getValue(0));
17576 Results.push_back(Swap.getValue(2));
17579 /// ReplaceNodeResults - Replace a node with an illegal result type
17580 /// with a new node built out of custom code.
17581 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17582 SmallVectorImpl<SDValue>&Results,
17583 SelectionDAG &DAG) const {
17585 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17586 switch (N->getOpcode()) {
17588 llvm_unreachable("Do not know how to custom type legalize this operation!");
17589 case ISD::SIGN_EXTEND_INREG:
17594 // We don't want to expand or promote these.
17601 case ISD::UDIVREM: {
17602 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17603 Results.push_back(V);
17606 case ISD::FP_TO_SINT:
17607 case ISD::FP_TO_UINT: {
17608 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17610 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17613 std::pair<SDValue,SDValue> Vals =
17614 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17615 SDValue FIST = Vals.first, StackSlot = Vals.second;
17616 if (FIST.getNode()) {
17617 EVT VT = N->getValueType(0);
17618 // Return a load from the stack slot.
17619 if (StackSlot.getNode())
17620 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17621 MachinePointerInfo(),
17622 false, false, false, 0));
17624 Results.push_back(FIST);
17628 case ISD::UINT_TO_FP: {
17629 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17630 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17631 N->getValueType(0) != MVT::v2f32)
17633 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17635 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17637 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17638 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17639 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17640 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17641 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17642 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17645 case ISD::FP_ROUND: {
17646 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17648 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17649 Results.push_back(V);
17652 case ISD::INTRINSIC_W_CHAIN: {
17653 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17655 default : llvm_unreachable("Do not know how to custom type "
17656 "legalize this intrinsic operation!");
17657 case Intrinsic::x86_rdtsc:
17658 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17660 case Intrinsic::x86_rdtscp:
17661 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17663 case Intrinsic::x86_rdpmc:
17664 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17667 case ISD::READCYCLECOUNTER: {
17668 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17671 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17672 EVT T = N->getValueType(0);
17673 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17674 bool Regs64bit = T == MVT::i128;
17675 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17676 SDValue cpInL, cpInH;
17677 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17678 DAG.getConstant(0, HalfT));
17679 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17680 DAG.getConstant(1, HalfT));
17681 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17682 Regs64bit ? X86::RAX : X86::EAX,
17684 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17685 Regs64bit ? X86::RDX : X86::EDX,
17686 cpInH, cpInL.getValue(1));
17687 SDValue swapInL, swapInH;
17688 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17689 DAG.getConstant(0, HalfT));
17690 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17691 DAG.getConstant(1, HalfT));
17692 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17693 Regs64bit ? X86::RBX : X86::EBX,
17694 swapInL, cpInH.getValue(1));
17695 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17696 Regs64bit ? X86::RCX : X86::ECX,
17697 swapInH, swapInL.getValue(1));
17698 SDValue Ops[] = { swapInH.getValue(0),
17700 swapInH.getValue(1) };
17701 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17702 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17703 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17704 X86ISD::LCMPXCHG8_DAG;
17705 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17706 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17707 Regs64bit ? X86::RAX : X86::EAX,
17708 HalfT, Result.getValue(1));
17709 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17710 Regs64bit ? X86::RDX : X86::EDX,
17711 HalfT, cpOutL.getValue(2));
17712 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17714 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17715 MVT::i32, cpOutH.getValue(2));
17717 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17718 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17719 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17721 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17722 Results.push_back(Success);
17723 Results.push_back(EFLAGS.getValue(1));
17726 case ISD::ATOMIC_SWAP:
17727 case ISD::ATOMIC_LOAD_ADD:
17728 case ISD::ATOMIC_LOAD_SUB:
17729 case ISD::ATOMIC_LOAD_AND:
17730 case ISD::ATOMIC_LOAD_OR:
17731 case ISD::ATOMIC_LOAD_XOR:
17732 case ISD::ATOMIC_LOAD_NAND:
17733 case ISD::ATOMIC_LOAD_MIN:
17734 case ISD::ATOMIC_LOAD_MAX:
17735 case ISD::ATOMIC_LOAD_UMIN:
17736 case ISD::ATOMIC_LOAD_UMAX:
17737 // Delegate to generic TypeLegalization. Situations we can really handle
17738 // should have already been dealt with by AtomicExpandPass.cpp.
17740 case ISD::ATOMIC_LOAD: {
17741 ReplaceATOMIC_LOAD(N, Results, DAG);
17744 case ISD::BITCAST: {
17745 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17746 EVT DstVT = N->getValueType(0);
17747 EVT SrcVT = N->getOperand(0)->getValueType(0);
17749 if (SrcVT != MVT::f64 ||
17750 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17753 unsigned NumElts = DstVT.getVectorNumElements();
17754 EVT SVT = DstVT.getVectorElementType();
17755 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17756 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17757 MVT::v2f64, N->getOperand(0));
17758 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17760 if (ExperimentalVectorWideningLegalization) {
17761 // If we are legalizing vectors by widening, we already have the desired
17762 // legal vector type, just return it.
17763 Results.push_back(ToVecInt);
17767 SmallVector<SDValue, 8> Elts;
17768 for (unsigned i = 0, e = NumElts; i != e; ++i)
17769 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17770 ToVecInt, DAG.getIntPtrConstant(i)));
17772 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17777 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17779 default: return nullptr;
17780 case X86ISD::BSF: return "X86ISD::BSF";
17781 case X86ISD::BSR: return "X86ISD::BSR";
17782 case X86ISD::SHLD: return "X86ISD::SHLD";
17783 case X86ISD::SHRD: return "X86ISD::SHRD";
17784 case X86ISD::FAND: return "X86ISD::FAND";
17785 case X86ISD::FANDN: return "X86ISD::FANDN";
17786 case X86ISD::FOR: return "X86ISD::FOR";
17787 case X86ISD::FXOR: return "X86ISD::FXOR";
17788 case X86ISD::FSRL: return "X86ISD::FSRL";
17789 case X86ISD::FILD: return "X86ISD::FILD";
17790 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17791 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17792 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17793 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17794 case X86ISD::FLD: return "X86ISD::FLD";
17795 case X86ISD::FST: return "X86ISD::FST";
17796 case X86ISD::CALL: return "X86ISD::CALL";
17797 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17798 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17799 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17800 case X86ISD::BT: return "X86ISD::BT";
17801 case X86ISD::CMP: return "X86ISD::CMP";
17802 case X86ISD::COMI: return "X86ISD::COMI";
17803 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17804 case X86ISD::CMPM: return "X86ISD::CMPM";
17805 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17806 case X86ISD::SETCC: return "X86ISD::SETCC";
17807 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17808 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17809 case X86ISD::CMOV: return "X86ISD::CMOV";
17810 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17811 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17812 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17813 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17814 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17815 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17816 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17817 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17818 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17819 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17820 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17821 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17822 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17823 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17824 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17825 case X86ISD::BLENDV: return "X86ISD::BLENDV";
17826 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17827 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17828 case X86ISD::HADD: return "X86ISD::HADD";
17829 case X86ISD::HSUB: return "X86ISD::HSUB";
17830 case X86ISD::FHADD: return "X86ISD::FHADD";
17831 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17832 case X86ISD::UMAX: return "X86ISD::UMAX";
17833 case X86ISD::UMIN: return "X86ISD::UMIN";
17834 case X86ISD::SMAX: return "X86ISD::SMAX";
17835 case X86ISD::SMIN: return "X86ISD::SMIN";
17836 case X86ISD::FMAX: return "X86ISD::FMAX";
17837 case X86ISD::FMIN: return "X86ISD::FMIN";
17838 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17839 case X86ISD::FMINC: return "X86ISD::FMINC";
17840 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17841 case X86ISD::FRCP: return "X86ISD::FRCP";
17842 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17843 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17844 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17845 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17846 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17847 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17848 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17849 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17850 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17851 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17852 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17853 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17854 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17855 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17856 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17857 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17858 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17859 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17860 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17861 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17862 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17863 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17864 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17865 case X86ISD::VSHL: return "X86ISD::VSHL";
17866 case X86ISD::VSRL: return "X86ISD::VSRL";
17867 case X86ISD::VSRA: return "X86ISD::VSRA";
17868 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17869 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17870 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17871 case X86ISD::CMPP: return "X86ISD::CMPP";
17872 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17873 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17874 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17875 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17876 case X86ISD::ADD: return "X86ISD::ADD";
17877 case X86ISD::SUB: return "X86ISD::SUB";
17878 case X86ISD::ADC: return "X86ISD::ADC";
17879 case X86ISD::SBB: return "X86ISD::SBB";
17880 case X86ISD::SMUL: return "X86ISD::SMUL";
17881 case X86ISD::UMUL: return "X86ISD::UMUL";
17882 case X86ISD::INC: return "X86ISD::INC";
17883 case X86ISD::DEC: return "X86ISD::DEC";
17884 case X86ISD::OR: return "X86ISD::OR";
17885 case X86ISD::XOR: return "X86ISD::XOR";
17886 case X86ISD::AND: return "X86ISD::AND";
17887 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17888 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17889 case X86ISD::PTEST: return "X86ISD::PTEST";
17890 case X86ISD::TESTP: return "X86ISD::TESTP";
17891 case X86ISD::TESTM: return "X86ISD::TESTM";
17892 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17893 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17894 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17895 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17896 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17897 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17898 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17899 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17900 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17901 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17902 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17903 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17904 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17905 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17906 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17907 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17908 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17909 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17910 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17911 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17912 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17913 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17914 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17915 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17916 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17917 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
17918 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17919 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17920 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17921 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17922 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17923 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17924 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17925 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17926 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17927 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17928 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17929 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17930 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17931 case X86ISD::SAHF: return "X86ISD::SAHF";
17932 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17933 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17934 case X86ISD::FMADD: return "X86ISD::FMADD";
17935 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17936 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17937 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17938 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17939 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17940 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17941 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17942 case X86ISD::XTEST: return "X86ISD::XTEST";
17946 // isLegalAddressingMode - Return true if the addressing mode represented
17947 // by AM is legal for this target, for a load/store of the specified type.
17948 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17950 // X86 supports extremely general addressing modes.
17951 CodeModel::Model M = getTargetMachine().getCodeModel();
17952 Reloc::Model R = getTargetMachine().getRelocationModel();
17954 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17955 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17960 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17962 // If a reference to this global requires an extra load, we can't fold it.
17963 if (isGlobalStubReference(GVFlags))
17966 // If BaseGV requires a register for the PIC base, we cannot also have a
17967 // BaseReg specified.
17968 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17971 // If lower 4G is not available, then we must use rip-relative addressing.
17972 if ((M != CodeModel::Small || R != Reloc::Static) &&
17973 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17977 switch (AM.Scale) {
17983 // These scales always work.
17988 // These scales are formed with basereg+scalereg. Only accept if there is
17993 default: // Other stuff never works.
18000 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18001 unsigned Bits = Ty->getScalarSizeInBits();
18003 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18004 // particularly cheaper than those without.
18008 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18009 // variable shifts just as cheap as scalar ones.
18010 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18013 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18014 // fully general vector.
18018 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18019 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18021 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18022 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18023 return NumBits1 > NumBits2;
18026 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18027 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18030 if (!isTypeLegal(EVT::getEVT(Ty1)))
18033 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18035 // Assuming the caller doesn't have a zeroext or signext return parameter,
18036 // truncation all the way down to i1 is valid.
18040 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18041 return isInt<32>(Imm);
18044 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18045 // Can also use sub to handle negated immediates.
18046 return isInt<32>(Imm);
18049 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18050 if (!VT1.isInteger() || !VT2.isInteger())
18052 unsigned NumBits1 = VT1.getSizeInBits();
18053 unsigned NumBits2 = VT2.getSizeInBits();
18054 return NumBits1 > NumBits2;
18057 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18058 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18059 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18062 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18063 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18064 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18067 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18068 EVT VT1 = Val.getValueType();
18069 if (isZExtFree(VT1, VT2))
18072 if (Val.getOpcode() != ISD::LOAD)
18075 if (!VT1.isSimple() || !VT1.isInteger() ||
18076 !VT2.isSimple() || !VT2.isInteger())
18079 switch (VT1.getSimpleVT().SimpleTy) {
18084 // X86 has 8, 16, and 32-bit zero-extending loads.
18092 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18093 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18096 VT = VT.getScalarType();
18098 if (!VT.isSimple())
18101 switch (VT.getSimpleVT().SimpleTy) {
18112 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18113 // i16 instructions are longer (0x66 prefix) and potentially slower.
18114 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18117 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18118 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18119 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18120 /// are assumed to be legal.
18122 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18124 if (!VT.isSimple())
18127 MVT SVT = VT.getSimpleVT();
18129 // Very little shuffling can be done for 64-bit vectors right now.
18130 if (VT.getSizeInBits() == 64)
18133 // If this is a single-input shuffle with no 128 bit lane crossings we can
18134 // lower it into pshufb.
18135 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18136 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18137 bool isLegal = true;
18138 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18139 if (M[I] >= (int)SVT.getVectorNumElements() ||
18140 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18149 // FIXME: blends, shifts.
18150 return (SVT.getVectorNumElements() == 2 ||
18151 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18152 isMOVLMask(M, SVT) ||
18153 isMOVHLPSMask(M, SVT) ||
18154 isSHUFPMask(M, SVT) ||
18155 isPSHUFDMask(M, SVT) ||
18156 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18157 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18158 isPALIGNRMask(M, SVT, Subtarget) ||
18159 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18160 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18161 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18162 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18163 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18167 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18169 if (!VT.isSimple())
18172 MVT SVT = VT.getSimpleVT();
18173 unsigned NumElts = SVT.getVectorNumElements();
18174 // FIXME: This collection of masks seems suspect.
18177 if (NumElts == 4 && SVT.is128BitVector()) {
18178 return (isMOVLMask(Mask, SVT) ||
18179 isCommutedMOVLMask(Mask, SVT, true) ||
18180 isSHUFPMask(Mask, SVT) ||
18181 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18186 //===----------------------------------------------------------------------===//
18187 // X86 Scheduler Hooks
18188 //===----------------------------------------------------------------------===//
18190 /// Utility function to emit xbegin specifying the start of an RTM region.
18191 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18192 const TargetInstrInfo *TII) {
18193 DebugLoc DL = MI->getDebugLoc();
18195 const BasicBlock *BB = MBB->getBasicBlock();
18196 MachineFunction::iterator I = MBB;
18199 // For the v = xbegin(), we generate
18210 MachineBasicBlock *thisMBB = MBB;
18211 MachineFunction *MF = MBB->getParent();
18212 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18213 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18214 MF->insert(I, mainMBB);
18215 MF->insert(I, sinkMBB);
18217 // Transfer the remainder of BB and its successor edges to sinkMBB.
18218 sinkMBB->splice(sinkMBB->begin(), MBB,
18219 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18220 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18224 // # fallthrough to mainMBB
18225 // # abortion to sinkMBB
18226 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18227 thisMBB->addSuccessor(mainMBB);
18228 thisMBB->addSuccessor(sinkMBB);
18232 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18233 mainMBB->addSuccessor(sinkMBB);
18236 // EAX is live into the sinkMBB
18237 sinkMBB->addLiveIn(X86::EAX);
18238 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18239 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18242 MI->eraseFromParent();
18246 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18247 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18248 // in the .td file.
18249 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18250 const TargetInstrInfo *TII) {
18252 switch (MI->getOpcode()) {
18253 default: llvm_unreachable("illegal opcode!");
18254 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18255 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18256 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18257 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18258 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18259 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18260 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18261 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18264 DebugLoc dl = MI->getDebugLoc();
18265 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18267 unsigned NumArgs = MI->getNumOperands();
18268 for (unsigned i = 1; i < NumArgs; ++i) {
18269 MachineOperand &Op = MI->getOperand(i);
18270 if (!(Op.isReg() && Op.isImplicit()))
18271 MIB.addOperand(Op);
18273 if (MI->hasOneMemOperand())
18274 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18276 BuildMI(*BB, MI, dl,
18277 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18278 .addReg(X86::XMM0);
18280 MI->eraseFromParent();
18284 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18285 // defs in an instruction pattern
18286 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18287 const TargetInstrInfo *TII) {
18289 switch (MI->getOpcode()) {
18290 default: llvm_unreachable("illegal opcode!");
18291 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18292 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18293 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18294 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18295 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18296 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18297 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18298 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18301 DebugLoc dl = MI->getDebugLoc();
18302 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18304 unsigned NumArgs = MI->getNumOperands(); // remove the results
18305 for (unsigned i = 1; i < NumArgs; ++i) {
18306 MachineOperand &Op = MI->getOperand(i);
18307 if (!(Op.isReg() && Op.isImplicit()))
18308 MIB.addOperand(Op);
18310 if (MI->hasOneMemOperand())
18311 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18313 BuildMI(*BB, MI, dl,
18314 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18317 MI->eraseFromParent();
18321 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18322 const TargetInstrInfo *TII,
18323 const X86Subtarget* Subtarget) {
18324 DebugLoc dl = MI->getDebugLoc();
18326 // Address into RAX/EAX, other two args into ECX, EDX.
18327 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18328 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18329 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18330 for (int i = 0; i < X86::AddrNumOperands; ++i)
18331 MIB.addOperand(MI->getOperand(i));
18333 unsigned ValOps = X86::AddrNumOperands;
18334 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18335 .addReg(MI->getOperand(ValOps).getReg());
18336 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18337 .addReg(MI->getOperand(ValOps+1).getReg());
18339 // The instruction doesn't actually take any operands though.
18340 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18342 MI->eraseFromParent(); // The pseudo is gone now.
18346 MachineBasicBlock *
18347 X86TargetLowering::EmitVAARG64WithCustomInserter(
18349 MachineBasicBlock *MBB) const {
18350 // Emit va_arg instruction on X86-64.
18352 // Operands to this pseudo-instruction:
18353 // 0 ) Output : destination address (reg)
18354 // 1-5) Input : va_list address (addr, i64mem)
18355 // 6 ) ArgSize : Size (in bytes) of vararg type
18356 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18357 // 8 ) Align : Alignment of type
18358 // 9 ) EFLAGS (implicit-def)
18360 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18361 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18363 unsigned DestReg = MI->getOperand(0).getReg();
18364 MachineOperand &Base = MI->getOperand(1);
18365 MachineOperand &Scale = MI->getOperand(2);
18366 MachineOperand &Index = MI->getOperand(3);
18367 MachineOperand &Disp = MI->getOperand(4);
18368 MachineOperand &Segment = MI->getOperand(5);
18369 unsigned ArgSize = MI->getOperand(6).getImm();
18370 unsigned ArgMode = MI->getOperand(7).getImm();
18371 unsigned Align = MI->getOperand(8).getImm();
18373 // Memory Reference
18374 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18375 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18376 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18378 // Machine Information
18379 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18380 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18381 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18382 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18383 DebugLoc DL = MI->getDebugLoc();
18385 // struct va_list {
18388 // i64 overflow_area (address)
18389 // i64 reg_save_area (address)
18391 // sizeof(va_list) = 24
18392 // alignment(va_list) = 8
18394 unsigned TotalNumIntRegs = 6;
18395 unsigned TotalNumXMMRegs = 8;
18396 bool UseGPOffset = (ArgMode == 1);
18397 bool UseFPOffset = (ArgMode == 2);
18398 unsigned MaxOffset = TotalNumIntRegs * 8 +
18399 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18401 /* Align ArgSize to a multiple of 8 */
18402 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18403 bool NeedsAlign = (Align > 8);
18405 MachineBasicBlock *thisMBB = MBB;
18406 MachineBasicBlock *overflowMBB;
18407 MachineBasicBlock *offsetMBB;
18408 MachineBasicBlock *endMBB;
18410 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18411 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18412 unsigned OffsetReg = 0;
18414 if (!UseGPOffset && !UseFPOffset) {
18415 // If we only pull from the overflow region, we don't create a branch.
18416 // We don't need to alter control flow.
18417 OffsetDestReg = 0; // unused
18418 OverflowDestReg = DestReg;
18420 offsetMBB = nullptr;
18421 overflowMBB = thisMBB;
18424 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18425 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18426 // If not, pull from overflow_area. (branch to overflowMBB)
18431 // offsetMBB overflowMBB
18436 // Registers for the PHI in endMBB
18437 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18438 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18440 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18441 MachineFunction *MF = MBB->getParent();
18442 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18443 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18444 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18446 MachineFunction::iterator MBBIter = MBB;
18449 // Insert the new basic blocks
18450 MF->insert(MBBIter, offsetMBB);
18451 MF->insert(MBBIter, overflowMBB);
18452 MF->insert(MBBIter, endMBB);
18454 // Transfer the remainder of MBB and its successor edges to endMBB.
18455 endMBB->splice(endMBB->begin(), thisMBB,
18456 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18457 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18459 // Make offsetMBB and overflowMBB successors of thisMBB
18460 thisMBB->addSuccessor(offsetMBB);
18461 thisMBB->addSuccessor(overflowMBB);
18463 // endMBB is a successor of both offsetMBB and overflowMBB
18464 offsetMBB->addSuccessor(endMBB);
18465 overflowMBB->addSuccessor(endMBB);
18467 // Load the offset value into a register
18468 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18469 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18473 .addDisp(Disp, UseFPOffset ? 4 : 0)
18474 .addOperand(Segment)
18475 .setMemRefs(MMOBegin, MMOEnd);
18477 // Check if there is enough room left to pull this argument.
18478 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18480 .addImm(MaxOffset + 8 - ArgSizeA8);
18482 // Branch to "overflowMBB" if offset >= max
18483 // Fall through to "offsetMBB" otherwise
18484 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18485 .addMBB(overflowMBB);
18488 // In offsetMBB, emit code to use the reg_save_area.
18490 assert(OffsetReg != 0);
18492 // Read the reg_save_area address.
18493 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18494 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18499 .addOperand(Segment)
18500 .setMemRefs(MMOBegin, MMOEnd);
18502 // Zero-extend the offset
18503 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18504 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18507 .addImm(X86::sub_32bit);
18509 // Add the offset to the reg_save_area to get the final address.
18510 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18511 .addReg(OffsetReg64)
18512 .addReg(RegSaveReg);
18514 // Compute the offset for the next argument
18515 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18516 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18518 .addImm(UseFPOffset ? 16 : 8);
18520 // Store it back into the va_list.
18521 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18525 .addDisp(Disp, UseFPOffset ? 4 : 0)
18526 .addOperand(Segment)
18527 .addReg(NextOffsetReg)
18528 .setMemRefs(MMOBegin, MMOEnd);
18531 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18536 // Emit code to use overflow area
18539 // Load the overflow_area address into a register.
18540 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18541 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18546 .addOperand(Segment)
18547 .setMemRefs(MMOBegin, MMOEnd);
18549 // If we need to align it, do so. Otherwise, just copy the address
18550 // to OverflowDestReg.
18552 // Align the overflow address
18553 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18554 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18556 // aligned_addr = (addr + (align-1)) & ~(align-1)
18557 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18558 .addReg(OverflowAddrReg)
18561 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18563 .addImm(~(uint64_t)(Align-1));
18565 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18566 .addReg(OverflowAddrReg);
18569 // Compute the next overflow address after this argument.
18570 // (the overflow address should be kept 8-byte aligned)
18571 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18572 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18573 .addReg(OverflowDestReg)
18574 .addImm(ArgSizeA8);
18576 // Store the new overflow address.
18577 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18582 .addOperand(Segment)
18583 .addReg(NextAddrReg)
18584 .setMemRefs(MMOBegin, MMOEnd);
18586 // If we branched, emit the PHI to the front of endMBB.
18588 BuildMI(*endMBB, endMBB->begin(), DL,
18589 TII->get(X86::PHI), DestReg)
18590 .addReg(OffsetDestReg).addMBB(offsetMBB)
18591 .addReg(OverflowDestReg).addMBB(overflowMBB);
18594 // Erase the pseudo instruction
18595 MI->eraseFromParent();
18600 MachineBasicBlock *
18601 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18603 MachineBasicBlock *MBB) const {
18604 // Emit code to save XMM registers to the stack. The ABI says that the
18605 // number of registers to save is given in %al, so it's theoretically
18606 // possible to do an indirect jump trick to avoid saving all of them,
18607 // however this code takes a simpler approach and just executes all
18608 // of the stores if %al is non-zero. It's less code, and it's probably
18609 // easier on the hardware branch predictor, and stores aren't all that
18610 // expensive anyway.
18612 // Create the new basic blocks. One block contains all the XMM stores,
18613 // and one block is the final destination regardless of whether any
18614 // stores were performed.
18615 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18616 MachineFunction *F = MBB->getParent();
18617 MachineFunction::iterator MBBIter = MBB;
18619 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18620 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18621 F->insert(MBBIter, XMMSaveMBB);
18622 F->insert(MBBIter, EndMBB);
18624 // Transfer the remainder of MBB and its successor edges to EndMBB.
18625 EndMBB->splice(EndMBB->begin(), MBB,
18626 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18627 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18629 // The original block will now fall through to the XMM save block.
18630 MBB->addSuccessor(XMMSaveMBB);
18631 // The XMMSaveMBB will fall through to the end block.
18632 XMMSaveMBB->addSuccessor(EndMBB);
18634 // Now add the instructions.
18635 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18636 DebugLoc DL = MI->getDebugLoc();
18638 unsigned CountReg = MI->getOperand(0).getReg();
18639 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18640 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18642 if (!Subtarget->isTargetWin64()) {
18643 // If %al is 0, branch around the XMM save block.
18644 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18645 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18646 MBB->addSuccessor(EndMBB);
18649 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18650 // that was just emitted, but clearly shouldn't be "saved".
18651 assert((MI->getNumOperands() <= 3 ||
18652 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18653 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18654 && "Expected last argument to be EFLAGS");
18655 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18656 // In the XMM save block, save all the XMM argument registers.
18657 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18658 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18659 MachineMemOperand *MMO =
18660 F->getMachineMemOperand(
18661 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18662 MachineMemOperand::MOStore,
18663 /*Size=*/16, /*Align=*/16);
18664 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18665 .addFrameIndex(RegSaveFrameIndex)
18666 .addImm(/*Scale=*/1)
18667 .addReg(/*IndexReg=*/0)
18668 .addImm(/*Disp=*/Offset)
18669 .addReg(/*Segment=*/0)
18670 .addReg(MI->getOperand(i).getReg())
18671 .addMemOperand(MMO);
18674 MI->eraseFromParent(); // The pseudo instruction is gone now.
18679 // The EFLAGS operand of SelectItr might be missing a kill marker
18680 // because there were multiple uses of EFLAGS, and ISel didn't know
18681 // which to mark. Figure out whether SelectItr should have had a
18682 // kill marker, and set it if it should. Returns the correct kill
18684 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18685 MachineBasicBlock* BB,
18686 const TargetRegisterInfo* TRI) {
18687 // Scan forward through BB for a use/def of EFLAGS.
18688 MachineBasicBlock::iterator miI(std::next(SelectItr));
18689 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18690 const MachineInstr& mi = *miI;
18691 if (mi.readsRegister(X86::EFLAGS))
18693 if (mi.definesRegister(X86::EFLAGS))
18694 break; // Should have kill-flag - update below.
18697 // If we hit the end of the block, check whether EFLAGS is live into a
18699 if (miI == BB->end()) {
18700 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18701 sEnd = BB->succ_end();
18702 sItr != sEnd; ++sItr) {
18703 MachineBasicBlock* succ = *sItr;
18704 if (succ->isLiveIn(X86::EFLAGS))
18709 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18710 // out. SelectMI should have a kill flag on EFLAGS.
18711 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18715 MachineBasicBlock *
18716 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18717 MachineBasicBlock *BB) const {
18718 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18719 DebugLoc DL = MI->getDebugLoc();
18721 // To "insert" a SELECT_CC instruction, we actually have to insert the
18722 // diamond control-flow pattern. The incoming instruction knows the
18723 // destination vreg to set, the condition code register to branch on, the
18724 // true/false values to select between, and a branch opcode to use.
18725 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18726 MachineFunction::iterator It = BB;
18732 // cmpTY ccX, r1, r2
18734 // fallthrough --> copy0MBB
18735 MachineBasicBlock *thisMBB = BB;
18736 MachineFunction *F = BB->getParent();
18737 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18738 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18739 F->insert(It, copy0MBB);
18740 F->insert(It, sinkMBB);
18742 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18743 // live into the sink and copy blocks.
18744 const TargetRegisterInfo *TRI =
18745 BB->getParent()->getSubtarget().getRegisterInfo();
18746 if (!MI->killsRegister(X86::EFLAGS) &&
18747 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
18748 copy0MBB->addLiveIn(X86::EFLAGS);
18749 sinkMBB->addLiveIn(X86::EFLAGS);
18752 // Transfer the remainder of BB and its successor edges to sinkMBB.
18753 sinkMBB->splice(sinkMBB->begin(), BB,
18754 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18755 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18757 // Add the true and fallthrough blocks as its successors.
18758 BB->addSuccessor(copy0MBB);
18759 BB->addSuccessor(sinkMBB);
18761 // Create the conditional branch instruction.
18763 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18764 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18767 // %FalseValue = ...
18768 // # fallthrough to sinkMBB
18769 copy0MBB->addSuccessor(sinkMBB);
18772 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18774 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18775 TII->get(X86::PHI), MI->getOperand(0).getReg())
18776 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18777 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18779 MI->eraseFromParent(); // The pseudo instruction is gone now.
18783 MachineBasicBlock *
18784 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
18785 bool Is64Bit) const {
18786 MachineFunction *MF = BB->getParent();
18787 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18788 DebugLoc DL = MI->getDebugLoc();
18789 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18791 assert(MF->shouldSplitStack());
18793 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18794 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
18797 // ... [Till the alloca]
18798 // If stacklet is not large enough, jump to mallocMBB
18801 // Allocate by subtracting from RSP
18802 // Jump to continueMBB
18805 // Allocate by call to runtime
18809 // [rest of original BB]
18812 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18813 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18814 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18816 MachineRegisterInfo &MRI = MF->getRegInfo();
18817 const TargetRegisterClass *AddrRegClass =
18818 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
18820 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18821 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18822 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18823 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18824 sizeVReg = MI->getOperand(1).getReg(),
18825 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
18827 MachineFunction::iterator MBBIter = BB;
18830 MF->insert(MBBIter, bumpMBB);
18831 MF->insert(MBBIter, mallocMBB);
18832 MF->insert(MBBIter, continueMBB);
18834 continueMBB->splice(continueMBB->begin(), BB,
18835 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18836 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18838 // Add code to the main basic block to check if the stack limit has been hit,
18839 // and if so, jump to mallocMBB otherwise to bumpMBB.
18840 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18841 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18842 .addReg(tmpSPVReg).addReg(sizeVReg);
18843 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
18844 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18845 .addReg(SPLimitVReg);
18846 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
18848 // bumpMBB simply decreases the stack pointer, since we know the current
18849 // stacklet has enough space.
18850 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18851 .addReg(SPLimitVReg);
18852 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18853 .addReg(SPLimitVReg);
18854 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18856 // Calls into a routine in libgcc to allocate more space from the heap.
18857 const uint32_t *RegMask = MF->getTarget()
18858 .getSubtargetImpl()
18859 ->getRegisterInfo()
18860 ->getCallPreservedMask(CallingConv::C);
18862 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18864 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18865 .addExternalSymbol("__morestack_allocate_stack_space")
18866 .addRegMask(RegMask)
18867 .addReg(X86::RDI, RegState::Implicit)
18868 .addReg(X86::RAX, RegState::ImplicitDefine);
18870 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18872 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18873 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18874 .addExternalSymbol("__morestack_allocate_stack_space")
18875 .addRegMask(RegMask)
18876 .addReg(X86::EAX, RegState::ImplicitDefine);
18880 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18883 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18884 .addReg(Is64Bit ? X86::RAX : X86::EAX);
18885 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18887 // Set up the CFG correctly.
18888 BB->addSuccessor(bumpMBB);
18889 BB->addSuccessor(mallocMBB);
18890 mallocMBB->addSuccessor(continueMBB);
18891 bumpMBB->addSuccessor(continueMBB);
18893 // Take care of the PHI nodes.
18894 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18895 MI->getOperand(0).getReg())
18896 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18897 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18899 // Delete the original pseudo instruction.
18900 MI->eraseFromParent();
18903 return continueMBB;
18906 MachineBasicBlock *
18907 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18908 MachineBasicBlock *BB) const {
18909 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18910 DebugLoc DL = MI->getDebugLoc();
18912 assert(!Subtarget->isTargetMacho());
18914 // The lowering is pretty easy: we're just emitting the call to _alloca. The
18915 // non-trivial part is impdef of ESP.
18917 if (Subtarget->isTargetWin64()) {
18918 if (Subtarget->isTargetCygMing()) {
18919 // ___chkstk(Mingw64):
18920 // Clobbers R10, R11, RAX and EFLAGS.
18922 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18923 .addExternalSymbol("___chkstk")
18924 .addReg(X86::RAX, RegState::Implicit)
18925 .addReg(X86::RSP, RegState::Implicit)
18926 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
18927 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
18928 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18930 // __chkstk(MSVCRT): does not update stack pointer.
18931 // Clobbers R10, R11 and EFLAGS.
18932 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18933 .addExternalSymbol("__chkstk")
18934 .addReg(X86::RAX, RegState::Implicit)
18935 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18936 // RAX has the offset to be subtracted from RSP.
18937 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
18942 const char *StackProbeSymbol =
18943 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
18945 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
18946 .addExternalSymbol(StackProbeSymbol)
18947 .addReg(X86::EAX, RegState::Implicit)
18948 .addReg(X86::ESP, RegState::Implicit)
18949 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
18950 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
18951 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18954 MI->eraseFromParent(); // The pseudo instruction is gone now.
18958 MachineBasicBlock *
18959 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18960 MachineBasicBlock *BB) const {
18961 // This is pretty easy. We're taking the value that we received from
18962 // our load from the relocation, sticking it in either RDI (x86-64)
18963 // or EAX and doing an indirect call. The return value will then
18964 // be in the normal return register.
18965 MachineFunction *F = BB->getParent();
18966 const X86InstrInfo *TII =
18967 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
18968 DebugLoc DL = MI->getDebugLoc();
18970 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18971 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18973 // Get a register mask for the lowered call.
18974 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18975 // proper register mask.
18976 const uint32_t *RegMask = F->getTarget()
18977 .getSubtargetImpl()
18978 ->getRegisterInfo()
18979 ->getCallPreservedMask(CallingConv::C);
18980 if (Subtarget->is64Bit()) {
18981 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18982 TII->get(X86::MOV64rm), X86::RDI)
18984 .addImm(0).addReg(0)
18985 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18986 MI->getOperand(3).getTargetFlags())
18988 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18989 addDirectMem(MIB, X86::RDI);
18990 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18991 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18992 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18993 TII->get(X86::MOV32rm), X86::EAX)
18995 .addImm(0).addReg(0)
18996 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18997 MI->getOperand(3).getTargetFlags())
18999 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19000 addDirectMem(MIB, X86::EAX);
19001 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19003 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19004 TII->get(X86::MOV32rm), X86::EAX)
19005 .addReg(TII->getGlobalBaseReg(F))
19006 .addImm(0).addReg(0)
19007 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19008 MI->getOperand(3).getTargetFlags())
19010 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19011 addDirectMem(MIB, X86::EAX);
19012 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19015 MI->eraseFromParent(); // The pseudo instruction is gone now.
19019 MachineBasicBlock *
19020 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19021 MachineBasicBlock *MBB) const {
19022 DebugLoc DL = MI->getDebugLoc();
19023 MachineFunction *MF = MBB->getParent();
19024 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19025 MachineRegisterInfo &MRI = MF->getRegInfo();
19027 const BasicBlock *BB = MBB->getBasicBlock();
19028 MachineFunction::iterator I = MBB;
19031 // Memory Reference
19032 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19033 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19036 unsigned MemOpndSlot = 0;
19038 unsigned CurOp = 0;
19040 DstReg = MI->getOperand(CurOp++).getReg();
19041 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19042 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19043 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19044 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19046 MemOpndSlot = CurOp;
19048 MVT PVT = getPointerTy();
19049 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19050 "Invalid Pointer Size!");
19052 // For v = setjmp(buf), we generate
19055 // buf[LabelOffset] = restoreMBB
19056 // SjLjSetup restoreMBB
19062 // v = phi(main, restore)
19067 MachineBasicBlock *thisMBB = MBB;
19068 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19069 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19070 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19071 MF->insert(I, mainMBB);
19072 MF->insert(I, sinkMBB);
19073 MF->push_back(restoreMBB);
19075 MachineInstrBuilder MIB;
19077 // Transfer the remainder of BB and its successor edges to sinkMBB.
19078 sinkMBB->splice(sinkMBB->begin(), MBB,
19079 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19080 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19083 unsigned PtrStoreOpc = 0;
19084 unsigned LabelReg = 0;
19085 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19086 Reloc::Model RM = MF->getTarget().getRelocationModel();
19087 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19088 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19090 // Prepare IP either in reg or imm.
19091 if (!UseImmLabel) {
19092 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19093 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19094 LabelReg = MRI.createVirtualRegister(PtrRC);
19095 if (Subtarget->is64Bit()) {
19096 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19100 .addMBB(restoreMBB)
19103 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19104 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19105 .addReg(XII->getGlobalBaseReg(MF))
19108 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19112 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19114 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19115 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19116 if (i == X86::AddrDisp)
19117 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19119 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19122 MIB.addReg(LabelReg);
19124 MIB.addMBB(restoreMBB);
19125 MIB.setMemRefs(MMOBegin, MMOEnd);
19127 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19128 .addMBB(restoreMBB);
19130 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19131 MF->getSubtarget().getRegisterInfo());
19132 MIB.addRegMask(RegInfo->getNoPreservedMask());
19133 thisMBB->addSuccessor(mainMBB);
19134 thisMBB->addSuccessor(restoreMBB);
19138 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19139 mainMBB->addSuccessor(sinkMBB);
19142 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19143 TII->get(X86::PHI), DstReg)
19144 .addReg(mainDstReg).addMBB(mainMBB)
19145 .addReg(restoreDstReg).addMBB(restoreMBB);
19148 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19149 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19150 restoreMBB->addSuccessor(sinkMBB);
19152 MI->eraseFromParent();
19156 MachineBasicBlock *
19157 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19158 MachineBasicBlock *MBB) const {
19159 DebugLoc DL = MI->getDebugLoc();
19160 MachineFunction *MF = MBB->getParent();
19161 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19162 MachineRegisterInfo &MRI = MF->getRegInfo();
19164 // Memory Reference
19165 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19166 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19168 MVT PVT = getPointerTy();
19169 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19170 "Invalid Pointer Size!");
19172 const TargetRegisterClass *RC =
19173 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19174 unsigned Tmp = MRI.createVirtualRegister(RC);
19175 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19176 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19177 MF->getSubtarget().getRegisterInfo());
19178 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19179 unsigned SP = RegInfo->getStackRegister();
19181 MachineInstrBuilder MIB;
19183 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19184 const int64_t SPOffset = 2 * PVT.getStoreSize();
19186 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19187 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19190 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19191 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19192 MIB.addOperand(MI->getOperand(i));
19193 MIB.setMemRefs(MMOBegin, MMOEnd);
19195 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19196 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19197 if (i == X86::AddrDisp)
19198 MIB.addDisp(MI->getOperand(i), LabelOffset);
19200 MIB.addOperand(MI->getOperand(i));
19202 MIB.setMemRefs(MMOBegin, MMOEnd);
19204 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19205 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19206 if (i == X86::AddrDisp)
19207 MIB.addDisp(MI->getOperand(i), SPOffset);
19209 MIB.addOperand(MI->getOperand(i));
19211 MIB.setMemRefs(MMOBegin, MMOEnd);
19213 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19215 MI->eraseFromParent();
19219 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19220 // accumulator loops. Writing back to the accumulator allows the coalescer
19221 // to remove extra copies in the loop.
19222 MachineBasicBlock *
19223 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19224 MachineBasicBlock *MBB) const {
19225 MachineOperand &AddendOp = MI->getOperand(3);
19227 // Bail out early if the addend isn't a register - we can't switch these.
19228 if (!AddendOp.isReg())
19231 MachineFunction &MF = *MBB->getParent();
19232 MachineRegisterInfo &MRI = MF.getRegInfo();
19234 // Check whether the addend is defined by a PHI:
19235 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19236 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19237 if (!AddendDef.isPHI())
19240 // Look for the following pattern:
19242 // %addend = phi [%entry, 0], [%loop, %result]
19244 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19248 // %addend = phi [%entry, 0], [%loop, %result]
19250 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19252 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19253 assert(AddendDef.getOperand(i).isReg());
19254 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19255 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19256 if (&PHISrcInst == MI) {
19257 // Found a matching instruction.
19258 unsigned NewFMAOpc = 0;
19259 switch (MI->getOpcode()) {
19260 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19261 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19262 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19263 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19264 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19265 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19266 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19267 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19268 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19269 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19270 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19271 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19272 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19273 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19274 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19275 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19276 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19277 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19278 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19279 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19280 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19281 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19282 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19283 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19284 default: llvm_unreachable("Unrecognized FMA variant.");
19287 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19288 MachineInstrBuilder MIB =
19289 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19290 .addOperand(MI->getOperand(0))
19291 .addOperand(MI->getOperand(3))
19292 .addOperand(MI->getOperand(2))
19293 .addOperand(MI->getOperand(1));
19294 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19295 MI->eraseFromParent();
19302 MachineBasicBlock *
19303 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19304 MachineBasicBlock *BB) const {
19305 switch (MI->getOpcode()) {
19306 default: llvm_unreachable("Unexpected instr type to insert");
19307 case X86::TAILJMPd64:
19308 case X86::TAILJMPr64:
19309 case X86::TAILJMPm64:
19310 llvm_unreachable("TAILJMP64 would not be touched here.");
19311 case X86::TCRETURNdi64:
19312 case X86::TCRETURNri64:
19313 case X86::TCRETURNmi64:
19315 case X86::WIN_ALLOCA:
19316 return EmitLoweredWinAlloca(MI, BB);
19317 case X86::SEG_ALLOCA_32:
19318 return EmitLoweredSegAlloca(MI, BB, false);
19319 case X86::SEG_ALLOCA_64:
19320 return EmitLoweredSegAlloca(MI, BB, true);
19321 case X86::TLSCall_32:
19322 case X86::TLSCall_64:
19323 return EmitLoweredTLSCall(MI, BB);
19324 case X86::CMOV_GR8:
19325 case X86::CMOV_FR32:
19326 case X86::CMOV_FR64:
19327 case X86::CMOV_V4F32:
19328 case X86::CMOV_V2F64:
19329 case X86::CMOV_V2I64:
19330 case X86::CMOV_V8F32:
19331 case X86::CMOV_V4F64:
19332 case X86::CMOV_V4I64:
19333 case X86::CMOV_V16F32:
19334 case X86::CMOV_V8F64:
19335 case X86::CMOV_V8I64:
19336 case X86::CMOV_GR16:
19337 case X86::CMOV_GR32:
19338 case X86::CMOV_RFP32:
19339 case X86::CMOV_RFP64:
19340 case X86::CMOV_RFP80:
19341 return EmitLoweredSelect(MI, BB);
19343 case X86::FP32_TO_INT16_IN_MEM:
19344 case X86::FP32_TO_INT32_IN_MEM:
19345 case X86::FP32_TO_INT64_IN_MEM:
19346 case X86::FP64_TO_INT16_IN_MEM:
19347 case X86::FP64_TO_INT32_IN_MEM:
19348 case X86::FP64_TO_INT64_IN_MEM:
19349 case X86::FP80_TO_INT16_IN_MEM:
19350 case X86::FP80_TO_INT32_IN_MEM:
19351 case X86::FP80_TO_INT64_IN_MEM: {
19352 MachineFunction *F = BB->getParent();
19353 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19354 DebugLoc DL = MI->getDebugLoc();
19356 // Change the floating point control register to use "round towards zero"
19357 // mode when truncating to an integer value.
19358 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19359 addFrameReference(BuildMI(*BB, MI, DL,
19360 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19362 // Load the old value of the high byte of the control word...
19364 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19365 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19368 // Set the high part to be round to zero...
19369 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19372 // Reload the modified control word now...
19373 addFrameReference(BuildMI(*BB, MI, DL,
19374 TII->get(X86::FLDCW16m)), CWFrameIdx);
19376 // Restore the memory image of control word to original value
19377 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19380 // Get the X86 opcode to use.
19382 switch (MI->getOpcode()) {
19383 default: llvm_unreachable("illegal opcode!");
19384 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19385 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19386 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19387 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19388 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19389 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19390 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19391 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19392 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19396 MachineOperand &Op = MI->getOperand(0);
19398 AM.BaseType = X86AddressMode::RegBase;
19399 AM.Base.Reg = Op.getReg();
19401 AM.BaseType = X86AddressMode::FrameIndexBase;
19402 AM.Base.FrameIndex = Op.getIndex();
19404 Op = MI->getOperand(1);
19406 AM.Scale = Op.getImm();
19407 Op = MI->getOperand(2);
19409 AM.IndexReg = Op.getImm();
19410 Op = MI->getOperand(3);
19411 if (Op.isGlobal()) {
19412 AM.GV = Op.getGlobal();
19414 AM.Disp = Op.getImm();
19416 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19417 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19419 // Reload the original control word now.
19420 addFrameReference(BuildMI(*BB, MI, DL,
19421 TII->get(X86::FLDCW16m)), CWFrameIdx);
19423 MI->eraseFromParent(); // The pseudo instruction is gone now.
19426 // String/text processing lowering.
19427 case X86::PCMPISTRM128REG:
19428 case X86::VPCMPISTRM128REG:
19429 case X86::PCMPISTRM128MEM:
19430 case X86::VPCMPISTRM128MEM:
19431 case X86::PCMPESTRM128REG:
19432 case X86::VPCMPESTRM128REG:
19433 case X86::PCMPESTRM128MEM:
19434 case X86::VPCMPESTRM128MEM:
19435 assert(Subtarget->hasSSE42() &&
19436 "Target must have SSE4.2 or AVX features enabled");
19437 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19439 // String/text processing lowering.
19440 case X86::PCMPISTRIREG:
19441 case X86::VPCMPISTRIREG:
19442 case X86::PCMPISTRIMEM:
19443 case X86::VPCMPISTRIMEM:
19444 case X86::PCMPESTRIREG:
19445 case X86::VPCMPESTRIREG:
19446 case X86::PCMPESTRIMEM:
19447 case X86::VPCMPESTRIMEM:
19448 assert(Subtarget->hasSSE42() &&
19449 "Target must have SSE4.2 or AVX features enabled");
19450 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19452 // Thread synchronization.
19454 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19459 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19461 case X86::VASTART_SAVE_XMM_REGS:
19462 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19464 case X86::VAARG_64:
19465 return EmitVAARG64WithCustomInserter(MI, BB);
19467 case X86::EH_SjLj_SetJmp32:
19468 case X86::EH_SjLj_SetJmp64:
19469 return emitEHSjLjSetJmp(MI, BB);
19471 case X86::EH_SjLj_LongJmp32:
19472 case X86::EH_SjLj_LongJmp64:
19473 return emitEHSjLjLongJmp(MI, BB);
19475 case TargetOpcode::STACKMAP:
19476 case TargetOpcode::PATCHPOINT:
19477 return emitPatchPoint(MI, BB);
19479 case X86::VFMADDPDr213r:
19480 case X86::VFMADDPSr213r:
19481 case X86::VFMADDSDr213r:
19482 case X86::VFMADDSSr213r:
19483 case X86::VFMSUBPDr213r:
19484 case X86::VFMSUBPSr213r:
19485 case X86::VFMSUBSDr213r:
19486 case X86::VFMSUBSSr213r:
19487 case X86::VFNMADDPDr213r:
19488 case X86::VFNMADDPSr213r:
19489 case X86::VFNMADDSDr213r:
19490 case X86::VFNMADDSSr213r:
19491 case X86::VFNMSUBPDr213r:
19492 case X86::VFNMSUBPSr213r:
19493 case X86::VFNMSUBSDr213r:
19494 case X86::VFNMSUBSSr213r:
19495 case X86::VFMADDPDr213rY:
19496 case X86::VFMADDPSr213rY:
19497 case X86::VFMSUBPDr213rY:
19498 case X86::VFMSUBPSr213rY:
19499 case X86::VFNMADDPDr213rY:
19500 case X86::VFNMADDPSr213rY:
19501 case X86::VFNMSUBPDr213rY:
19502 case X86::VFNMSUBPSr213rY:
19503 return emitFMA3Instr(MI, BB);
19507 //===----------------------------------------------------------------------===//
19508 // X86 Optimization Hooks
19509 //===----------------------------------------------------------------------===//
19511 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19514 const SelectionDAG &DAG,
19515 unsigned Depth) const {
19516 unsigned BitWidth = KnownZero.getBitWidth();
19517 unsigned Opc = Op.getOpcode();
19518 assert((Opc >= ISD::BUILTIN_OP_END ||
19519 Opc == ISD::INTRINSIC_WO_CHAIN ||
19520 Opc == ISD::INTRINSIC_W_CHAIN ||
19521 Opc == ISD::INTRINSIC_VOID) &&
19522 "Should use MaskedValueIsZero if you don't know whether Op"
19523 " is a target node!");
19525 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19539 // These nodes' second result is a boolean.
19540 if (Op.getResNo() == 0)
19543 case X86ISD::SETCC:
19544 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19546 case ISD::INTRINSIC_WO_CHAIN: {
19547 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19548 unsigned NumLoBits = 0;
19551 case Intrinsic::x86_sse_movmsk_ps:
19552 case Intrinsic::x86_avx_movmsk_ps_256:
19553 case Intrinsic::x86_sse2_movmsk_pd:
19554 case Intrinsic::x86_avx_movmsk_pd_256:
19555 case Intrinsic::x86_mmx_pmovmskb:
19556 case Intrinsic::x86_sse2_pmovmskb_128:
19557 case Intrinsic::x86_avx2_pmovmskb: {
19558 // High bits of movmskp{s|d}, pmovmskb are known zero.
19560 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19561 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19562 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19563 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19564 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19565 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19566 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19567 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19569 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19578 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19580 const SelectionDAG &,
19581 unsigned Depth) const {
19582 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19583 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19584 return Op.getValueType().getScalarType().getSizeInBits();
19590 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19591 /// node is a GlobalAddress + offset.
19592 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19593 const GlobalValue* &GA,
19594 int64_t &Offset) const {
19595 if (N->getOpcode() == X86ISD::Wrapper) {
19596 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19597 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19598 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19602 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19605 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19606 /// same as extracting the high 128-bit part of 256-bit vector and then
19607 /// inserting the result into the low part of a new 256-bit vector
19608 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19609 EVT VT = SVOp->getValueType(0);
19610 unsigned NumElems = VT.getVectorNumElements();
19612 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19613 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19614 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19615 SVOp->getMaskElt(j) >= 0)
19621 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19622 /// same as extracting the low 128-bit part of 256-bit vector and then
19623 /// inserting the result into the high part of a new 256-bit vector
19624 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19625 EVT VT = SVOp->getValueType(0);
19626 unsigned NumElems = VT.getVectorNumElements();
19628 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19629 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19630 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19631 SVOp->getMaskElt(j) >= 0)
19637 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19638 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19639 TargetLowering::DAGCombinerInfo &DCI,
19640 const X86Subtarget* Subtarget) {
19642 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19643 SDValue V1 = SVOp->getOperand(0);
19644 SDValue V2 = SVOp->getOperand(1);
19645 EVT VT = SVOp->getValueType(0);
19646 unsigned NumElems = VT.getVectorNumElements();
19648 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19649 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19653 // V UNDEF BUILD_VECTOR UNDEF
19655 // CONCAT_VECTOR CONCAT_VECTOR
19658 // RESULT: V + zero extended
19660 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19661 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19662 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19665 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19668 // To match the shuffle mask, the first half of the mask should
19669 // be exactly the first vector, and all the rest a splat with the
19670 // first element of the second one.
19671 for (unsigned i = 0; i != NumElems/2; ++i)
19672 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19673 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19676 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19677 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19678 if (Ld->hasNUsesOfValue(1, 0)) {
19679 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19680 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19682 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19684 Ld->getPointerInfo(),
19685 Ld->getAlignment(),
19686 false/*isVolatile*/, true/*ReadMem*/,
19687 false/*WriteMem*/);
19689 // Make sure the newly-created LOAD is in the same position as Ld in
19690 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19691 // and update uses of Ld's output chain to use the TokenFactor.
19692 if (Ld->hasAnyUseOfValue(1)) {
19693 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19694 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19695 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19696 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19697 SDValue(ResNode.getNode(), 1));
19700 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19704 // Emit a zeroed vector and insert the desired subvector on its
19706 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19707 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19708 return DCI.CombineTo(N, InsV);
19711 //===--------------------------------------------------------------------===//
19712 // Combine some shuffles into subvector extracts and inserts:
19715 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19716 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19717 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19718 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19719 return DCI.CombineTo(N, InsV);
19722 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19723 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19724 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19725 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19726 return DCI.CombineTo(N, InsV);
19732 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19735 /// This is the leaf of the recursive combinine below. When we have found some
19736 /// chain of single-use x86 shuffle instructions and accumulated the combined
19737 /// shuffle mask represented by them, this will try to pattern match that mask
19738 /// into either a single instruction if there is a special purpose instruction
19739 /// for this operation, or into a PSHUFB instruction which is a fully general
19740 /// instruction but should only be used to replace chains over a certain depth.
19741 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19742 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19743 TargetLowering::DAGCombinerInfo &DCI,
19744 const X86Subtarget *Subtarget) {
19745 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19747 // Find the operand that enters the chain. Note that multiple uses are OK
19748 // here, we're not going to remove the operand we find.
19749 SDValue Input = Op.getOperand(0);
19750 while (Input.getOpcode() == ISD::BITCAST)
19751 Input = Input.getOperand(0);
19753 MVT VT = Input.getSimpleValueType();
19754 MVT RootVT = Root.getSimpleValueType();
19757 // Just remove no-op shuffle masks.
19758 if (Mask.size() == 1) {
19759 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19764 // Use the float domain if the operand type is a floating point type.
19765 bool FloatDomain = VT.isFloatingPoint();
19767 // For floating point shuffles, we don't have free copies in the shuffle
19768 // instructions or the ability to load as part of the instruction, so
19769 // canonicalize their shuffles to UNPCK or MOV variants.
19771 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
19772 // vectors because it can have a load folded into it that UNPCK cannot. This
19773 // doesn't preclude something switching to the shorter encoding post-RA.
19775 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19776 bool Lo = Mask.equals(0, 0);
19779 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
19780 // is no slower than UNPCKLPD but has the option to fold the input operand
19781 // into even an unaligned memory load.
19782 if (Lo && Subtarget->hasSSE3()) {
19783 Shuffle = X86ISD::MOVDDUP;
19784 ShuffleVT = MVT::v2f64;
19786 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
19787 // than the UNPCK variants.
19788 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
19789 ShuffleVT = MVT::v4f32;
19791 if (Depth == 1 && Root->getOpcode() == Shuffle)
19792 return false; // Nothing to do!
19793 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19794 DCI.AddToWorklist(Op.getNode());
19795 if (Shuffle == X86ISD::MOVDDUP)
19796 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19798 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19799 DCI.AddToWorklist(Op.getNode());
19800 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19804 if (Subtarget->hasSSE3() &&
19805 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
19806 bool Lo = Mask.equals(0, 0, 2, 2);
19807 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
19808 MVT ShuffleVT = MVT::v4f32;
19809 if (Depth == 1 && Root->getOpcode() == Shuffle)
19810 return false; // Nothing to do!
19811 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19812 DCI.AddToWorklist(Op.getNode());
19813 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19814 DCI.AddToWorklist(Op.getNode());
19815 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19819 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
19820 bool Lo = Mask.equals(0, 0, 1, 1);
19821 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19822 MVT ShuffleVT = MVT::v4f32;
19823 if (Depth == 1 && Root->getOpcode() == Shuffle)
19824 return false; // Nothing to do!
19825 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19826 DCI.AddToWorklist(Op.getNode());
19827 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19828 DCI.AddToWorklist(Op.getNode());
19829 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19835 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
19836 // variants as none of these have single-instruction variants that are
19837 // superior to the UNPCK formulation.
19838 if (!FloatDomain &&
19839 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19840 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19841 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19842 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19844 bool Lo = Mask[0] == 0;
19845 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19846 if (Depth == 1 && Root->getOpcode() == Shuffle)
19847 return false; // Nothing to do!
19849 switch (Mask.size()) {
19851 ShuffleVT = MVT::v8i16;
19854 ShuffleVT = MVT::v16i8;
19857 llvm_unreachable("Impossible mask size!");
19859 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19860 DCI.AddToWorklist(Op.getNode());
19861 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19862 DCI.AddToWorklist(Op.getNode());
19863 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19868 // Don't try to re-form single instruction chains under any circumstances now
19869 // that we've done encoding canonicalization for them.
19873 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19874 // can replace them with a single PSHUFB instruction profitably. Intel's
19875 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19876 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19877 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19878 SmallVector<SDValue, 16> PSHUFBMask;
19879 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19880 int Ratio = 16 / Mask.size();
19881 for (unsigned i = 0; i < 16; ++i) {
19882 int M = Mask[i / Ratio] != SM_SentinelZero
19883 ? Ratio * Mask[i / Ratio] + i % Ratio
19885 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19887 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19888 DCI.AddToWorklist(Op.getNode());
19889 SDValue PSHUFBMaskOp =
19890 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19891 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19892 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19893 DCI.AddToWorklist(Op.getNode());
19894 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19899 // Failed to find any combines.
19903 /// \brief Fully generic combining of x86 shuffle instructions.
19905 /// This should be the last combine run over the x86 shuffle instructions. Once
19906 /// they have been fully optimized, this will recursively consider all chains
19907 /// of single-use shuffle instructions, build a generic model of the cumulative
19908 /// shuffle operation, and check for simpler instructions which implement this
19909 /// operation. We use this primarily for two purposes:
19911 /// 1) Collapse generic shuffles to specialized single instructions when
19912 /// equivalent. In most cases, this is just an encoding size win, but
19913 /// sometimes we will collapse multiple generic shuffles into a single
19914 /// special-purpose shuffle.
19915 /// 2) Look for sequences of shuffle instructions with 3 or more total
19916 /// instructions, and replace them with the slightly more expensive SSSE3
19917 /// PSHUFB instruction if available. We do this as the last combining step
19918 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19919 /// a suitable short sequence of other instructions. The PHUFB will either
19920 /// use a register or have to read from memory and so is slightly (but only
19921 /// slightly) more expensive than the other shuffle instructions.
19923 /// Because this is inherently a quadratic operation (for each shuffle in
19924 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19925 /// This should never be an issue in practice as the shuffle lowering doesn't
19926 /// produce sequences of more than 8 instructions.
19928 /// FIXME: We will currently miss some cases where the redundant shuffling
19929 /// would simplify under the threshold for PSHUFB formation because of
19930 /// combine-ordering. To fix this, we should do the redundant instruction
19931 /// combining in this recursive walk.
19932 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19933 ArrayRef<int> RootMask,
19934 int Depth, bool HasPSHUFB,
19936 TargetLowering::DAGCombinerInfo &DCI,
19937 const X86Subtarget *Subtarget) {
19938 // Bound the depth of our recursive combine because this is ultimately
19939 // quadratic in nature.
19943 // Directly rip through bitcasts to find the underlying operand.
19944 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19945 Op = Op.getOperand(0);
19947 MVT VT = Op.getSimpleValueType();
19948 if (!VT.isVector())
19949 return false; // Bail if we hit a non-vector.
19950 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
19951 // version should be added.
19952 if (VT.getSizeInBits() != 128)
19955 assert(Root.getSimpleValueType().isVector() &&
19956 "Shuffles operate on vector types!");
19957 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19958 "Can only combine shuffles of the same vector register size.");
19960 if (!isTargetShuffle(Op.getOpcode()))
19962 SmallVector<int, 16> OpMask;
19964 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19965 // We only can combine unary shuffles which we can decode the mask for.
19966 if (!HaveMask || !IsUnary)
19969 assert(VT.getVectorNumElements() == OpMask.size() &&
19970 "Different mask size from vector size!");
19971 assert(((RootMask.size() > OpMask.size() &&
19972 RootMask.size() % OpMask.size() == 0) ||
19973 (OpMask.size() > RootMask.size() &&
19974 OpMask.size() % RootMask.size() == 0) ||
19975 OpMask.size() == RootMask.size()) &&
19976 "The smaller number of elements must divide the larger.");
19977 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19978 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19979 assert(((RootRatio == 1 && OpRatio == 1) ||
19980 (RootRatio == 1) != (OpRatio == 1)) &&
19981 "Must not have a ratio for both incoming and op masks!");
19983 SmallVector<int, 16> Mask;
19984 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19986 // Merge this shuffle operation's mask into our accumulated mask. Note that
19987 // this shuffle's mask will be the first applied to the input, followed by the
19988 // root mask to get us all the way to the root value arrangement. The reason
19989 // for this order is that we are recursing up the operation chain.
19990 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19991 int RootIdx = i / RootRatio;
19992 if (RootMask[RootIdx] == SM_SentinelZero) {
19993 // This is a zero-ed lane, we're done.
19994 Mask.push_back(SM_SentinelZero);
19998 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
19999 int OpIdx = RootMaskedIdx / OpRatio;
20000 if (OpMask[OpIdx] == SM_SentinelZero) {
20001 // The incoming lanes are zero, it doesn't matter which ones we are using.
20002 Mask.push_back(SM_SentinelZero);
20006 // Ok, we have non-zero lanes, map them through.
20007 Mask.push_back(OpMask[OpIdx] * OpRatio +
20008 RootMaskedIdx % OpRatio);
20011 // See if we can recurse into the operand to combine more things.
20012 switch (Op.getOpcode()) {
20013 case X86ISD::PSHUFB:
20015 case X86ISD::PSHUFD:
20016 case X86ISD::PSHUFHW:
20017 case X86ISD::PSHUFLW:
20018 if (Op.getOperand(0).hasOneUse() &&
20019 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20020 HasPSHUFB, DAG, DCI, Subtarget))
20024 case X86ISD::UNPCKL:
20025 case X86ISD::UNPCKH:
20026 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20027 // We can't check for single use, we have to check that this shuffle is the only user.
20028 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20029 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20030 HasPSHUFB, DAG, DCI, Subtarget))
20035 // Minor canonicalization of the accumulated shuffle mask to make it easier
20036 // to match below. All this does is detect masks with squential pairs of
20037 // elements, and shrink them to the half-width mask. It does this in a loop
20038 // so it will reduce the size of the mask to the minimal width mask which
20039 // performs an equivalent shuffle.
20040 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20041 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20042 Mask[i] = Mask[2 * i] / 2;
20043 Mask.resize(Mask.size() / 2);
20046 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20050 /// \brief Get the PSHUF-style mask from PSHUF node.
20052 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20053 /// PSHUF-style masks that can be reused with such instructions.
20054 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20055 SmallVector<int, 4> Mask;
20057 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20061 switch (N.getOpcode()) {
20062 case X86ISD::PSHUFD:
20064 case X86ISD::PSHUFLW:
20067 case X86ISD::PSHUFHW:
20068 Mask.erase(Mask.begin(), Mask.begin() + 4);
20069 for (int &M : Mask)
20073 llvm_unreachable("No valid shuffle instruction found!");
20077 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20079 /// We walk up the chain and look for a combinable shuffle, skipping over
20080 /// shuffles that we could hoist this shuffle's transformation past without
20081 /// altering anything.
20083 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20085 TargetLowering::DAGCombinerInfo &DCI) {
20086 assert(N.getOpcode() == X86ISD::PSHUFD &&
20087 "Called with something other than an x86 128-bit half shuffle!");
20090 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20091 // of the shuffles in the chain so that we can form a fresh chain to replace
20093 SmallVector<SDValue, 8> Chain;
20094 SDValue V = N.getOperand(0);
20095 for (; V.hasOneUse(); V = V.getOperand(0)) {
20096 switch (V.getOpcode()) {
20098 return SDValue(); // Nothing combined!
20101 // Skip bitcasts as we always know the type for the target specific
20105 case X86ISD::PSHUFD:
20106 // Found another dword shuffle.
20109 case X86ISD::PSHUFLW:
20110 // Check that the low words (being shuffled) are the identity in the
20111 // dword shuffle, and the high words are self-contained.
20112 if (Mask[0] != 0 || Mask[1] != 1 ||
20113 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20116 Chain.push_back(V);
20119 case X86ISD::PSHUFHW:
20120 // Check that the high words (being shuffled) are the identity in the
20121 // dword shuffle, and the low words are self-contained.
20122 if (Mask[2] != 2 || Mask[3] != 3 ||
20123 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20126 Chain.push_back(V);
20129 case X86ISD::UNPCKL:
20130 case X86ISD::UNPCKH:
20131 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20132 // shuffle into a preceding word shuffle.
20133 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20136 // Search for a half-shuffle which we can combine with.
20137 unsigned CombineOp =
20138 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20139 if (V.getOperand(0) != V.getOperand(1) ||
20140 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20142 Chain.push_back(V);
20143 V = V.getOperand(0);
20145 switch (V.getOpcode()) {
20147 return SDValue(); // Nothing to combine.
20149 case X86ISD::PSHUFLW:
20150 case X86ISD::PSHUFHW:
20151 if (V.getOpcode() == CombineOp)
20154 Chain.push_back(V);
20158 V = V.getOperand(0);
20162 } while (V.hasOneUse());
20165 // Break out of the loop if we break out of the switch.
20169 if (!V.hasOneUse())
20170 // We fell out of the loop without finding a viable combining instruction.
20173 // Merge this node's mask and our incoming mask.
20174 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20175 for (int &M : Mask)
20177 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20178 getV4X86ShuffleImm8ForMask(Mask, DAG));
20180 // Rebuild the chain around this new shuffle.
20181 while (!Chain.empty()) {
20182 SDValue W = Chain.pop_back_val();
20184 if (V.getValueType() != W.getOperand(0).getValueType())
20185 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20187 switch (W.getOpcode()) {
20189 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20191 case X86ISD::UNPCKL:
20192 case X86ISD::UNPCKH:
20193 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20196 case X86ISD::PSHUFD:
20197 case X86ISD::PSHUFLW:
20198 case X86ISD::PSHUFHW:
20199 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20203 if (V.getValueType() != N.getValueType())
20204 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20206 // Return the new chain to replace N.
20210 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20212 /// We walk up the chain, skipping shuffles of the other half and looking
20213 /// through shuffles which switch halves trying to find a shuffle of the same
20214 /// pair of dwords.
20215 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20217 TargetLowering::DAGCombinerInfo &DCI) {
20219 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20220 "Called with something other than an x86 128-bit half shuffle!");
20222 unsigned CombineOpcode = N.getOpcode();
20224 // Walk up a single-use chain looking for a combinable shuffle.
20225 SDValue V = N.getOperand(0);
20226 for (; V.hasOneUse(); V = V.getOperand(0)) {
20227 switch (V.getOpcode()) {
20229 return false; // Nothing combined!
20232 // Skip bitcasts as we always know the type for the target specific
20236 case X86ISD::PSHUFLW:
20237 case X86ISD::PSHUFHW:
20238 if (V.getOpcode() == CombineOpcode)
20241 // Other-half shuffles are no-ops.
20244 // Break out of the loop if we break out of the switch.
20248 if (!V.hasOneUse())
20249 // We fell out of the loop without finding a viable combining instruction.
20252 // Combine away the bottom node as its shuffle will be accumulated into
20253 // a preceding shuffle.
20254 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20256 // Record the old value.
20259 // Merge this node's mask and our incoming mask (adjusted to account for all
20260 // the pshufd instructions encountered).
20261 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20262 for (int &M : Mask)
20264 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20265 getV4X86ShuffleImm8ForMask(Mask, DAG));
20267 // Check that the shuffles didn't cancel each other out. If not, we need to
20268 // combine to the new one.
20270 // Replace the combinable shuffle with the combined one, updating all users
20271 // so that we re-evaluate the chain here.
20272 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20277 /// \brief Try to combine x86 target specific shuffles.
20278 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20279 TargetLowering::DAGCombinerInfo &DCI,
20280 const X86Subtarget *Subtarget) {
20282 MVT VT = N.getSimpleValueType();
20283 SmallVector<int, 4> Mask;
20285 switch (N.getOpcode()) {
20286 case X86ISD::PSHUFD:
20287 case X86ISD::PSHUFLW:
20288 case X86ISD::PSHUFHW:
20289 Mask = getPSHUFShuffleMask(N);
20290 assert(Mask.size() == 4);
20296 // Nuke no-op shuffles that show up after combining.
20297 if (isNoopShuffleMask(Mask))
20298 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20300 // Look for simplifications involving one or two shuffle instructions.
20301 SDValue V = N.getOperand(0);
20302 switch (N.getOpcode()) {
20305 case X86ISD::PSHUFLW:
20306 case X86ISD::PSHUFHW:
20307 assert(VT == MVT::v8i16);
20310 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20311 return SDValue(); // We combined away this shuffle, so we're done.
20313 // See if this reduces to a PSHUFD which is no more expensive and can
20314 // combine with more operations.
20315 if (canWidenShuffleElements(Mask)) {
20316 int DMask[] = {-1, -1, -1, -1};
20317 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20318 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20319 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20320 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20321 DCI.AddToWorklist(V.getNode());
20322 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20323 getV4X86ShuffleImm8ForMask(DMask, DAG));
20324 DCI.AddToWorklist(V.getNode());
20325 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20328 // Look for shuffle patterns which can be implemented as a single unpack.
20329 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20330 // only works when we have a PSHUFD followed by two half-shuffles.
20331 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20332 (V.getOpcode() == X86ISD::PSHUFLW ||
20333 V.getOpcode() == X86ISD::PSHUFHW) &&
20334 V.getOpcode() != N.getOpcode() &&
20336 SDValue D = V.getOperand(0);
20337 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20338 D = D.getOperand(0);
20339 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20340 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20341 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20342 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20343 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20345 for (int i = 0; i < 4; ++i) {
20346 WordMask[i + NOffset] = Mask[i] + NOffset;
20347 WordMask[i + VOffset] = VMask[i] + VOffset;
20349 // Map the word mask through the DWord mask.
20351 for (int i = 0; i < 8; ++i)
20352 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20353 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
20354 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
20355 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
20356 std::begin(UnpackLoMask)) ||
20357 std::equal(std::begin(MappedMask), std::end(MappedMask),
20358 std::begin(UnpackHiMask))) {
20359 // We can replace all three shuffles with an unpack.
20360 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
20361 DCI.AddToWorklist(V.getNode());
20362 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20364 DL, MVT::v8i16, V, V);
20371 case X86ISD::PSHUFD:
20372 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20381 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20383 /// We combine this directly on the abstract vector shuffle nodes so it is
20384 /// easier to generically match. We also insert dummy vector shuffle nodes for
20385 /// the operands which explicitly discard the lanes which are unused by this
20386 /// operation to try to flow through the rest of the combiner the fact that
20387 /// they're unused.
20388 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20390 EVT VT = N->getValueType(0);
20392 // We only handle target-independent shuffles.
20393 // FIXME: It would be easy and harmless to use the target shuffle mask
20394 // extraction tool to support more.
20395 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20398 auto *SVN = cast<ShuffleVectorSDNode>(N);
20399 ArrayRef<int> Mask = SVN->getMask();
20400 SDValue V1 = N->getOperand(0);
20401 SDValue V2 = N->getOperand(1);
20403 // We require the first shuffle operand to be the SUB node, and the second to
20404 // be the ADD node.
20405 // FIXME: We should support the commuted patterns.
20406 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20409 // If there are other uses of these operations we can't fold them.
20410 if (!V1->hasOneUse() || !V2->hasOneUse())
20413 // Ensure that both operations have the same operands. Note that we can
20414 // commute the FADD operands.
20415 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20416 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20417 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20420 // We're looking for blends between FADD and FSUB nodes. We insist on these
20421 // nodes being lined up in a specific expected pattern.
20422 if (!(isShuffleEquivalent(Mask, 0, 3) ||
20423 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
20424 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
20427 // Only specific types are legal at this point, assert so we notice if and
20428 // when these change.
20429 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20430 VT == MVT::v4f64) &&
20431 "Unknown vector type encountered!");
20433 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20436 /// PerformShuffleCombine - Performs several different shuffle combines.
20437 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20438 TargetLowering::DAGCombinerInfo &DCI,
20439 const X86Subtarget *Subtarget) {
20441 SDValue N0 = N->getOperand(0);
20442 SDValue N1 = N->getOperand(1);
20443 EVT VT = N->getValueType(0);
20445 // Don't create instructions with illegal types after legalize types has run.
20446 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20447 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20450 // If we have legalized the vector types, look for blends of FADD and FSUB
20451 // nodes that we can fuse into an ADDSUB node.
20452 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20453 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20456 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20457 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20458 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20459 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20461 // During Type Legalization, when promoting illegal vector types,
20462 // the backend might introduce new shuffle dag nodes and bitcasts.
20464 // This code performs the following transformation:
20465 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20466 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20468 // We do this only if both the bitcast and the BINOP dag nodes have
20469 // one use. Also, perform this transformation only if the new binary
20470 // operation is legal. This is to avoid introducing dag nodes that
20471 // potentially need to be further expanded (or custom lowered) into a
20472 // less optimal sequence of dag nodes.
20473 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20474 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20475 N0.getOpcode() == ISD::BITCAST) {
20476 SDValue BC0 = N0.getOperand(0);
20477 EVT SVT = BC0.getValueType();
20478 unsigned Opcode = BC0.getOpcode();
20479 unsigned NumElts = VT.getVectorNumElements();
20481 if (BC0.hasOneUse() && SVT.isVector() &&
20482 SVT.getVectorNumElements() * 2 == NumElts &&
20483 TLI.isOperationLegal(Opcode, VT)) {
20484 bool CanFold = false;
20496 unsigned SVTNumElts = SVT.getVectorNumElements();
20497 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20498 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20499 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20500 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20501 CanFold = SVOp->getMaskElt(i) < 0;
20504 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20505 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20506 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20507 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20512 // Only handle 128 wide vector from here on.
20513 if (!VT.is128BitVector())
20516 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20517 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20518 // consecutive, non-overlapping, and in the right order.
20519 SmallVector<SDValue, 16> Elts;
20520 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20521 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20523 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20527 if (isTargetShuffle(N->getOpcode())) {
20529 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20530 if (Shuffle.getNode())
20533 // Try recursively combining arbitrary sequences of x86 shuffle
20534 // instructions into higher-order shuffles. We do this after combining
20535 // specific PSHUF instruction sequences into their minimal form so that we
20536 // can evaluate how many specialized shuffle instructions are involved in
20537 // a particular chain.
20538 SmallVector<int, 1> NonceMask; // Just a placeholder.
20539 NonceMask.push_back(0);
20540 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20541 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20543 return SDValue(); // This routine will use CombineTo to replace N.
20549 /// PerformTruncateCombine - Converts truncate operation to
20550 /// a sequence of vector shuffle operations.
20551 /// It is possible when we truncate 256-bit vector to 128-bit vector
20552 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20553 TargetLowering::DAGCombinerInfo &DCI,
20554 const X86Subtarget *Subtarget) {
20558 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20559 /// specific shuffle of a load can be folded into a single element load.
20560 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20561 /// shuffles have been customed lowered so we need to handle those here.
20562 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20563 TargetLowering::DAGCombinerInfo &DCI) {
20564 if (DCI.isBeforeLegalizeOps())
20567 SDValue InVec = N->getOperand(0);
20568 SDValue EltNo = N->getOperand(1);
20570 if (!isa<ConstantSDNode>(EltNo))
20573 EVT VT = InVec.getValueType();
20575 if (InVec.getOpcode() == ISD::BITCAST) {
20576 // Don't duplicate a load with other uses.
20577 if (!InVec.hasOneUse())
20579 EVT BCVT = InVec.getOperand(0).getValueType();
20580 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
20582 InVec = InVec.getOperand(0);
20585 if (!isTargetShuffle(InVec.getOpcode()))
20588 // Don't duplicate a load with other uses.
20589 if (!InVec.hasOneUse())
20592 SmallVector<int, 16> ShuffleMask;
20594 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
20598 // Select the input vector, guarding against out of range extract vector.
20599 unsigned NumElems = VT.getVectorNumElements();
20600 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20601 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20602 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20603 : InVec.getOperand(1);
20605 // If inputs to shuffle are the same for both ops, then allow 2 uses
20606 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20608 if (LdNode.getOpcode() == ISD::BITCAST) {
20609 // Don't duplicate a load with other uses.
20610 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20613 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20614 LdNode = LdNode.getOperand(0);
20617 if (!ISD::isNormalLoad(LdNode.getNode()))
20620 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20622 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20625 EVT EltVT = N->getValueType(0);
20626 // If there's a bitcast before the shuffle, check if the load type and
20627 // alignment is valid.
20628 unsigned Align = LN0->getAlignment();
20629 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20630 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20631 EltVT.getTypeForEVT(*DAG.getContext()));
20633 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20636 // All checks match so transform back to vector_shuffle so that DAG combiner
20637 // can finish the job
20640 // Create shuffle node taking into account the case that its a unary shuffle
20641 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20642 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20643 InVec.getOperand(0), Shuffle,
20645 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20646 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20650 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20651 /// generation and convert it from being a bunch of shuffles and extracts
20652 /// to a simple store and scalar loads to extract the elements.
20653 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20654 TargetLowering::DAGCombinerInfo &DCI) {
20655 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20656 if (NewOp.getNode())
20659 SDValue InputVector = N->getOperand(0);
20661 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20662 // from mmx to v2i32 has a single usage.
20663 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20664 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20665 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20666 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20667 N->getValueType(0),
20668 InputVector.getNode()->getOperand(0));
20670 // Only operate on vectors of 4 elements, where the alternative shuffling
20671 // gets to be more expensive.
20672 if (InputVector.getValueType() != MVT::v4i32)
20675 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20676 // single use which is a sign-extend or zero-extend, and all elements are
20678 SmallVector<SDNode *, 4> Uses;
20679 unsigned ExtractedElements = 0;
20680 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20681 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20682 if (UI.getUse().getResNo() != InputVector.getResNo())
20685 SDNode *Extract = *UI;
20686 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20689 if (Extract->getValueType(0) != MVT::i32)
20691 if (!Extract->hasOneUse())
20693 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20694 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20696 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20699 // Record which element was extracted.
20700 ExtractedElements |=
20701 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20703 Uses.push_back(Extract);
20706 // If not all the elements were used, this may not be worthwhile.
20707 if (ExtractedElements != 15)
20710 // Ok, we've now decided to do the transformation.
20711 SDLoc dl(InputVector);
20713 // Store the value to a temporary stack slot.
20714 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20715 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20716 MachinePointerInfo(), false, false, 0);
20718 // Replace each use (extract) with a load of the appropriate element.
20719 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20720 UE = Uses.end(); UI != UE; ++UI) {
20721 SDNode *Extract = *UI;
20723 // cOMpute the element's address.
20724 SDValue Idx = Extract->getOperand(1);
20726 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
20727 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
20728 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20729 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20731 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20732 StackPtr, OffsetVal);
20734 // Load the scalar.
20735 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
20736 ScalarAddr, MachinePointerInfo(),
20737 false, false, false, 0);
20739 // Replace the exact with the load.
20740 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
20743 // The replacement was made in place; don't return anything.
20747 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20748 static std::pair<unsigned, bool>
20749 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20750 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20751 if (!VT.isVector())
20752 return std::make_pair(0, false);
20754 bool NeedSplit = false;
20755 switch (VT.getSimpleVT().SimpleTy) {
20756 default: return std::make_pair(0, false);
20760 if (!Subtarget->hasAVX2())
20762 if (!Subtarget->hasAVX())
20763 return std::make_pair(0, false);
20768 if (!Subtarget->hasSSE2())
20769 return std::make_pair(0, false);
20772 // SSE2 has only a small subset of the operations.
20773 bool hasUnsigned = Subtarget->hasSSE41() ||
20774 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20775 bool hasSigned = Subtarget->hasSSE41() ||
20776 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20778 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20781 // Check for x CC y ? x : y.
20782 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20783 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20788 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20791 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20794 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20797 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20799 // Check for x CC y ? y : x -- a min/max with reversed arms.
20800 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20801 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20806 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20809 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20812 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20815 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20819 return std::make_pair(Opc, NeedSplit);
20823 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20824 const X86Subtarget *Subtarget) {
20826 SDValue Cond = N->getOperand(0);
20827 SDValue LHS = N->getOperand(1);
20828 SDValue RHS = N->getOperand(2);
20830 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20831 SDValue CondSrc = Cond->getOperand(0);
20832 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20833 Cond = CondSrc->getOperand(0);
20836 MVT VT = N->getSimpleValueType(0);
20837 MVT EltVT = VT.getVectorElementType();
20838 unsigned NumElems = VT.getVectorNumElements();
20839 // There is no blend with immediate in AVX-512.
20840 if (VT.is512BitVector())
20843 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
20845 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
20848 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20851 // A vselect where all conditions and data are constants can be optimized into
20852 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
20853 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
20854 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
20857 unsigned MaskValue = 0;
20858 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20861 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20862 for (unsigned i = 0; i < NumElems; ++i) {
20863 // Be sure we emit undef where we can.
20864 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20865 ShuffleMask[i] = -1;
20867 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20870 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20873 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20875 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20876 TargetLowering::DAGCombinerInfo &DCI,
20877 const X86Subtarget *Subtarget) {
20879 SDValue Cond = N->getOperand(0);
20880 // Get the LHS/RHS of the select.
20881 SDValue LHS = N->getOperand(1);
20882 SDValue RHS = N->getOperand(2);
20883 EVT VT = LHS.getValueType();
20884 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20886 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20887 // instructions match the semantics of the common C idiom x<y?x:y but not
20888 // x<=y?x:y, because of how they handle negative zero (which can be
20889 // ignored in unsafe-math mode).
20890 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20891 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
20892 (Subtarget->hasSSE2() ||
20893 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20894 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20896 unsigned Opcode = 0;
20897 // Check for x CC y ? x : y.
20898 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20899 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20903 // Converting this to a min would handle NaNs incorrectly, and swapping
20904 // the operands would cause it to handle comparisons between positive
20905 // and negative zero incorrectly.
20906 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20907 if (!DAG.getTarget().Options.UnsafeFPMath &&
20908 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20910 std::swap(LHS, RHS);
20912 Opcode = X86ISD::FMIN;
20915 // Converting this to a min would handle comparisons between positive
20916 // and negative zero incorrectly.
20917 if (!DAG.getTarget().Options.UnsafeFPMath &&
20918 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20920 Opcode = X86ISD::FMIN;
20923 // Converting this to a min would handle both negative zeros and NaNs
20924 // incorrectly, but we can swap the operands to fix both.
20925 std::swap(LHS, RHS);
20929 Opcode = X86ISD::FMIN;
20933 // Converting this to a max would handle comparisons between positive
20934 // and negative zero incorrectly.
20935 if (!DAG.getTarget().Options.UnsafeFPMath &&
20936 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20938 Opcode = X86ISD::FMAX;
20941 // Converting this to a max would handle NaNs incorrectly, and swapping
20942 // the operands would cause it to handle comparisons between positive
20943 // and negative zero incorrectly.
20944 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20945 if (!DAG.getTarget().Options.UnsafeFPMath &&
20946 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20948 std::swap(LHS, RHS);
20950 Opcode = X86ISD::FMAX;
20953 // Converting this to a max would handle both negative zeros and NaNs
20954 // incorrectly, but we can swap the operands to fix both.
20955 std::swap(LHS, RHS);
20959 Opcode = X86ISD::FMAX;
20962 // Check for x CC y ? y : x -- a min/max with reversed arms.
20963 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20964 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20968 // Converting this to a min would handle comparisons between positive
20969 // and negative zero incorrectly, and swapping the operands would
20970 // cause it to handle NaNs incorrectly.
20971 if (!DAG.getTarget().Options.UnsafeFPMath &&
20972 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20973 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20975 std::swap(LHS, RHS);
20977 Opcode = X86ISD::FMIN;
20980 // Converting this to a min would handle NaNs incorrectly.
20981 if (!DAG.getTarget().Options.UnsafeFPMath &&
20982 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20984 Opcode = X86ISD::FMIN;
20987 // Converting this to a min would handle both negative zeros and NaNs
20988 // incorrectly, but we can swap the operands to fix both.
20989 std::swap(LHS, RHS);
20993 Opcode = X86ISD::FMIN;
20997 // Converting this to a max would handle NaNs incorrectly.
20998 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21000 Opcode = X86ISD::FMAX;
21003 // Converting this to a max would handle comparisons between positive
21004 // and negative zero incorrectly, and swapping the operands would
21005 // cause it to handle NaNs incorrectly.
21006 if (!DAG.getTarget().Options.UnsafeFPMath &&
21007 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21008 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21010 std::swap(LHS, RHS);
21012 Opcode = X86ISD::FMAX;
21015 // Converting this to a max would handle both negative zeros and NaNs
21016 // incorrectly, but we can swap the operands to fix both.
21017 std::swap(LHS, RHS);
21021 Opcode = X86ISD::FMAX;
21027 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21030 EVT CondVT = Cond.getValueType();
21031 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21032 CondVT.getVectorElementType() == MVT::i1) {
21033 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21034 // lowering on KNL. In this case we convert it to
21035 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21036 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21037 // Since SKX these selects have a proper lowering.
21038 EVT OpVT = LHS.getValueType();
21039 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21040 (OpVT.getVectorElementType() == MVT::i8 ||
21041 OpVT.getVectorElementType() == MVT::i16) &&
21042 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21043 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21044 DCI.AddToWorklist(Cond.getNode());
21045 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21048 // If this is a select between two integer constants, try to do some
21050 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21051 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21052 // Don't do this for crazy integer types.
21053 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21054 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21055 // so that TrueC (the true value) is larger than FalseC.
21056 bool NeedsCondInvert = false;
21058 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21059 // Efficiently invertible.
21060 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21061 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21062 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21063 NeedsCondInvert = true;
21064 std::swap(TrueC, FalseC);
21067 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21068 if (FalseC->getAPIntValue() == 0 &&
21069 TrueC->getAPIntValue().isPowerOf2()) {
21070 if (NeedsCondInvert) // Invert the condition if needed.
21071 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21072 DAG.getConstant(1, Cond.getValueType()));
21074 // Zero extend the condition if needed.
21075 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21077 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21078 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21079 DAG.getConstant(ShAmt, MVT::i8));
21082 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21083 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21084 if (NeedsCondInvert) // Invert the condition if needed.
21085 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21086 DAG.getConstant(1, Cond.getValueType()));
21088 // Zero extend the condition if needed.
21089 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21090 FalseC->getValueType(0), Cond);
21091 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21092 SDValue(FalseC, 0));
21095 // Optimize cases that will turn into an LEA instruction. This requires
21096 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21097 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21098 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21099 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21101 bool isFastMultiplier = false;
21103 switch ((unsigned char)Diff) {
21105 case 1: // result = add base, cond
21106 case 2: // result = lea base( , cond*2)
21107 case 3: // result = lea base(cond, cond*2)
21108 case 4: // result = lea base( , cond*4)
21109 case 5: // result = lea base(cond, cond*4)
21110 case 8: // result = lea base( , cond*8)
21111 case 9: // result = lea base(cond, cond*8)
21112 isFastMultiplier = true;
21117 if (isFastMultiplier) {
21118 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21119 if (NeedsCondInvert) // Invert the condition if needed.
21120 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21121 DAG.getConstant(1, Cond.getValueType()));
21123 // Zero extend the condition if needed.
21124 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21126 // Scale the condition by the difference.
21128 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21129 DAG.getConstant(Diff, Cond.getValueType()));
21131 // Add the base if non-zero.
21132 if (FalseC->getAPIntValue() != 0)
21133 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21134 SDValue(FalseC, 0));
21141 // Canonicalize max and min:
21142 // (x > y) ? x : y -> (x >= y) ? x : y
21143 // (x < y) ? x : y -> (x <= y) ? x : y
21144 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21145 // the need for an extra compare
21146 // against zero. e.g.
21147 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21149 // testl %edi, %edi
21151 // cmovgl %edi, %eax
21155 // cmovsl %eax, %edi
21156 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21157 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21158 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21159 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21164 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21165 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21166 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21167 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21172 // Early exit check
21173 if (!TLI.isTypeLegal(VT))
21176 // Match VSELECTs into subs with unsigned saturation.
21177 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21178 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21179 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21180 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21181 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21183 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21184 // left side invert the predicate to simplify logic below.
21186 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21188 CC = ISD::getSetCCInverse(CC, true);
21189 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21193 if (Other.getNode() && Other->getNumOperands() == 2 &&
21194 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21195 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21196 SDValue CondRHS = Cond->getOperand(1);
21198 // Look for a general sub with unsigned saturation first.
21199 // x >= y ? x-y : 0 --> subus x, y
21200 // x > y ? x-y : 0 --> subus x, y
21201 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21202 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21203 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21205 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21206 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21207 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21208 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21209 // If the RHS is a constant we have to reverse the const
21210 // canonicalization.
21211 // x > C-1 ? x+-C : 0 --> subus x, C
21212 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21213 CondRHSConst->getAPIntValue() ==
21214 (-OpRHSConst->getAPIntValue() - 1))
21215 return DAG.getNode(
21216 X86ISD::SUBUS, DL, VT, OpLHS,
21217 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21219 // Another special case: If C was a sign bit, the sub has been
21220 // canonicalized into a xor.
21221 // FIXME: Would it be better to use computeKnownBits to determine
21222 // whether it's safe to decanonicalize the xor?
21223 // x s< 0 ? x^C : 0 --> subus x, C
21224 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21225 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21226 OpRHSConst->getAPIntValue().isSignBit())
21227 // Note that we have to rebuild the RHS constant here to ensure we
21228 // don't rely on particular values of undef lanes.
21229 return DAG.getNode(
21230 X86ISD::SUBUS, DL, VT, OpLHS,
21231 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21236 // Try to match a min/max vector operation.
21237 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21238 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21239 unsigned Opc = ret.first;
21240 bool NeedSplit = ret.second;
21242 if (Opc && NeedSplit) {
21243 unsigned NumElems = VT.getVectorNumElements();
21244 // Extract the LHS vectors
21245 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21246 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21248 // Extract the RHS vectors
21249 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21250 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21252 // Create min/max for each subvector
21253 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21254 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21256 // Merge the result
21257 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21259 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21262 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21263 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21264 // Check if SETCC has already been promoted
21265 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21266 // Check that condition value type matches vselect operand type
21269 assert(Cond.getValueType().isVector() &&
21270 "vector select expects a vector selector!");
21272 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21273 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21275 if (!TValIsAllOnes && !FValIsAllZeros) {
21276 // Try invert the condition if true value is not all 1s and false value
21278 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21279 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21281 if (TValIsAllZeros || FValIsAllOnes) {
21282 SDValue CC = Cond.getOperand(2);
21283 ISD::CondCode NewCC =
21284 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21285 Cond.getOperand(0).getValueType().isInteger());
21286 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21287 std::swap(LHS, RHS);
21288 TValIsAllOnes = FValIsAllOnes;
21289 FValIsAllZeros = TValIsAllZeros;
21293 if (TValIsAllOnes || FValIsAllZeros) {
21296 if (TValIsAllOnes && FValIsAllZeros)
21298 else if (TValIsAllOnes)
21299 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21300 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21301 else if (FValIsAllZeros)
21302 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21303 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21305 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21309 // Try to fold this VSELECT into a MOVSS/MOVSD
21310 if (N->getOpcode() == ISD::VSELECT &&
21311 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21312 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21313 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21314 bool CanFold = false;
21315 unsigned NumElems = Cond.getNumOperands();
21319 if (isZero(Cond.getOperand(0))) {
21322 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21323 // fold (vselect <0,-1> -> (movsd A, B)
21324 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21325 CanFold = isAllOnes(Cond.getOperand(i));
21326 } else if (isAllOnes(Cond.getOperand(0))) {
21330 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21331 // fold (vselect <-1,0> -> (movsd B, A)
21332 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21333 CanFold = isZero(Cond.getOperand(i));
21337 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21338 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21339 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21342 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21343 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21344 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
21345 // (v2i64 (bitcast B)))))
21347 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
21348 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
21349 // (v2f64 (bitcast B)))))
21351 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
21352 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
21353 // (v2i64 (bitcast A)))))
21355 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
21356 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
21357 // (v2f64 (bitcast A)))))
21359 CanFold = (isZero(Cond.getOperand(0)) &&
21360 isZero(Cond.getOperand(1)) &&
21361 isAllOnes(Cond.getOperand(2)) &&
21362 isAllOnes(Cond.getOperand(3)));
21364 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
21365 isAllOnes(Cond.getOperand(1)) &&
21366 isZero(Cond.getOperand(2)) &&
21367 isZero(Cond.getOperand(3))) {
21369 std::swap(LHS, RHS);
21373 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
21374 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
21375 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
21376 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
21378 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
21384 // If we know that this node is legal then we know that it is going to be
21385 // matched by one of the SSE/AVX BLEND instructions. These instructions only
21386 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
21387 // to simplify previous instructions.
21388 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21389 !DCI.isBeforeLegalize() &&
21390 // We explicitly check against v8i16 and v16i16 because, although
21391 // they're marked as Custom, they might only be legal when Cond is a
21392 // build_vector of constants. This will be taken care in a later
21394 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
21395 VT != MVT::v8i16)) {
21396 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21398 // Don't optimize vector selects that map to mask-registers.
21402 // Check all uses of that condition operand to check whether it will be
21403 // consumed by non-BLEND instructions, which may depend on all bits are set
21405 for (SDNode::use_iterator I = Cond->use_begin(),
21406 E = Cond->use_end(); I != E; ++I)
21407 if (I->getOpcode() != ISD::VSELECT)
21408 // TODO: Add other opcodes eventually lowered into BLEND.
21411 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21412 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21414 APInt KnownZero, KnownOne;
21415 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21416 DCI.isBeforeLegalizeOps());
21417 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21418 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
21419 DCI.CommitTargetLoweringOpt(TLO);
21422 // We should generate an X86ISD::BLENDI from a vselect if its argument
21423 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21424 // constants. This specific pattern gets generated when we split a
21425 // selector for a 512 bit vector in a machine without AVX512 (but with
21426 // 256-bit vectors), during legalization:
21428 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21430 // Iff we find this pattern and the build_vectors are built from
21431 // constants, we translate the vselect into a shuffle_vector that we
21432 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21433 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
21434 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21435 if (Shuffle.getNode())
21442 // Check whether a boolean test is testing a boolean value generated by
21443 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21446 // Simplify the following patterns:
21447 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21448 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21449 // to (Op EFLAGS Cond)
21451 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21452 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21453 // to (Op EFLAGS !Cond)
21455 // where Op could be BRCOND or CMOV.
21457 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21458 // Quit if not CMP and SUB with its value result used.
21459 if (Cmp.getOpcode() != X86ISD::CMP &&
21460 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21463 // Quit if not used as a boolean value.
21464 if (CC != X86::COND_E && CC != X86::COND_NE)
21467 // Check CMP operands. One of them should be 0 or 1 and the other should be
21468 // an SetCC or extended from it.
21469 SDValue Op1 = Cmp.getOperand(0);
21470 SDValue Op2 = Cmp.getOperand(1);
21473 const ConstantSDNode* C = nullptr;
21474 bool needOppositeCond = (CC == X86::COND_E);
21475 bool checkAgainstTrue = false; // Is it a comparison against 1?
21477 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21479 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21481 else // Quit if all operands are not constants.
21484 if (C->getZExtValue() == 1) {
21485 needOppositeCond = !needOppositeCond;
21486 checkAgainstTrue = true;
21487 } else if (C->getZExtValue() != 0)
21488 // Quit if the constant is neither 0 or 1.
21491 bool truncatedToBoolWithAnd = false;
21492 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21493 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21494 SetCC.getOpcode() == ISD::TRUNCATE ||
21495 SetCC.getOpcode() == ISD::AND) {
21496 if (SetCC.getOpcode() == ISD::AND) {
21498 ConstantSDNode *CS;
21499 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21500 CS->getZExtValue() == 1)
21502 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21503 CS->getZExtValue() == 1)
21507 SetCC = SetCC.getOperand(OpIdx);
21508 truncatedToBoolWithAnd = true;
21510 SetCC = SetCC.getOperand(0);
21513 switch (SetCC.getOpcode()) {
21514 case X86ISD::SETCC_CARRY:
21515 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21516 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21517 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21518 // truncated to i1 using 'and'.
21519 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21521 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21522 "Invalid use of SETCC_CARRY!");
21524 case X86ISD::SETCC:
21525 // Set the condition code or opposite one if necessary.
21526 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21527 if (needOppositeCond)
21528 CC = X86::GetOppositeBranchCondition(CC);
21529 return SetCC.getOperand(1);
21530 case X86ISD::CMOV: {
21531 // Check whether false/true value has canonical one, i.e. 0 or 1.
21532 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21533 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21534 // Quit if true value is not a constant.
21537 // Quit if false value is not a constant.
21539 SDValue Op = SetCC.getOperand(0);
21540 // Skip 'zext' or 'trunc' node.
21541 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21542 Op.getOpcode() == ISD::TRUNCATE)
21543 Op = Op.getOperand(0);
21544 // A special case for rdrand/rdseed, where 0 is set if false cond is
21546 if ((Op.getOpcode() != X86ISD::RDRAND &&
21547 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21550 // Quit if false value is not the constant 0 or 1.
21551 bool FValIsFalse = true;
21552 if (FVal && FVal->getZExtValue() != 0) {
21553 if (FVal->getZExtValue() != 1)
21555 // If FVal is 1, opposite cond is needed.
21556 needOppositeCond = !needOppositeCond;
21557 FValIsFalse = false;
21559 // Quit if TVal is not the constant opposite of FVal.
21560 if (FValIsFalse && TVal->getZExtValue() != 1)
21562 if (!FValIsFalse && TVal->getZExtValue() != 0)
21564 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21565 if (needOppositeCond)
21566 CC = X86::GetOppositeBranchCondition(CC);
21567 return SetCC.getOperand(3);
21574 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21575 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21576 TargetLowering::DAGCombinerInfo &DCI,
21577 const X86Subtarget *Subtarget) {
21580 // If the flag operand isn't dead, don't touch this CMOV.
21581 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21584 SDValue FalseOp = N->getOperand(0);
21585 SDValue TrueOp = N->getOperand(1);
21586 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21587 SDValue Cond = N->getOperand(3);
21589 if (CC == X86::COND_E || CC == X86::COND_NE) {
21590 switch (Cond.getOpcode()) {
21594 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21595 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21596 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21602 Flags = checkBoolTestSetCCCombine(Cond, CC);
21603 if (Flags.getNode() &&
21604 // Extra check as FCMOV only supports a subset of X86 cond.
21605 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21606 SDValue Ops[] = { FalseOp, TrueOp,
21607 DAG.getConstant(CC, MVT::i8), Flags };
21608 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21611 // If this is a select between two integer constants, try to do some
21612 // optimizations. Note that the operands are ordered the opposite of SELECT
21614 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21615 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21616 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21617 // larger than FalseC (the false value).
21618 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21619 CC = X86::GetOppositeBranchCondition(CC);
21620 std::swap(TrueC, FalseC);
21621 std::swap(TrueOp, FalseOp);
21624 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21625 // This is efficient for any integer data type (including i8/i16) and
21627 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21628 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21629 DAG.getConstant(CC, MVT::i8), Cond);
21631 // Zero extend the condition if needed.
21632 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21634 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21635 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21636 DAG.getConstant(ShAmt, MVT::i8));
21637 if (N->getNumValues() == 2) // Dead flag value?
21638 return DCI.CombineTo(N, Cond, SDValue());
21642 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21643 // for any integer data type, including i8/i16.
21644 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21645 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21646 DAG.getConstant(CC, MVT::i8), Cond);
21648 // Zero extend the condition if needed.
21649 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21650 FalseC->getValueType(0), Cond);
21651 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21652 SDValue(FalseC, 0));
21654 if (N->getNumValues() == 2) // Dead flag value?
21655 return DCI.CombineTo(N, Cond, SDValue());
21659 // Optimize cases that will turn into an LEA instruction. This requires
21660 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21661 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21662 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21663 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21665 bool isFastMultiplier = false;
21667 switch ((unsigned char)Diff) {
21669 case 1: // result = add base, cond
21670 case 2: // result = lea base( , cond*2)
21671 case 3: // result = lea base(cond, cond*2)
21672 case 4: // result = lea base( , cond*4)
21673 case 5: // result = lea base(cond, cond*4)
21674 case 8: // result = lea base( , cond*8)
21675 case 9: // result = lea base(cond, cond*8)
21676 isFastMultiplier = true;
21681 if (isFastMultiplier) {
21682 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21683 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21684 DAG.getConstant(CC, MVT::i8), Cond);
21685 // Zero extend the condition if needed.
21686 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21688 // Scale the condition by the difference.
21690 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21691 DAG.getConstant(Diff, Cond.getValueType()));
21693 // Add the base if non-zero.
21694 if (FalseC->getAPIntValue() != 0)
21695 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21696 SDValue(FalseC, 0));
21697 if (N->getNumValues() == 2) // Dead flag value?
21698 return DCI.CombineTo(N, Cond, SDValue());
21705 // Handle these cases:
21706 // (select (x != c), e, c) -> select (x != c), e, x),
21707 // (select (x == c), c, e) -> select (x == c), x, e)
21708 // where the c is an integer constant, and the "select" is the combination
21709 // of CMOV and CMP.
21711 // The rationale for this change is that the conditional-move from a constant
21712 // needs two instructions, however, conditional-move from a register needs
21713 // only one instruction.
21715 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21716 // some instruction-combining opportunities. This opt needs to be
21717 // postponed as late as possible.
21719 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21720 // the DCI.xxxx conditions are provided to postpone the optimization as
21721 // late as possible.
21723 ConstantSDNode *CmpAgainst = nullptr;
21724 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21725 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21726 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21728 if (CC == X86::COND_NE &&
21729 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21730 CC = X86::GetOppositeBranchCondition(CC);
21731 std::swap(TrueOp, FalseOp);
21734 if (CC == X86::COND_E &&
21735 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21736 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21737 DAG.getConstant(CC, MVT::i8), Cond };
21738 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21746 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21747 const X86Subtarget *Subtarget) {
21748 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21750 default: return SDValue();
21751 // SSE/AVX/AVX2 blend intrinsics.
21752 case Intrinsic::x86_avx2_pblendvb:
21753 case Intrinsic::x86_avx2_pblendw:
21754 case Intrinsic::x86_avx2_pblendd_128:
21755 case Intrinsic::x86_avx2_pblendd_256:
21756 // Don't try to simplify this intrinsic if we don't have AVX2.
21757 if (!Subtarget->hasAVX2())
21760 case Intrinsic::x86_avx_blend_pd_256:
21761 case Intrinsic::x86_avx_blend_ps_256:
21762 case Intrinsic::x86_avx_blendv_pd_256:
21763 case Intrinsic::x86_avx_blendv_ps_256:
21764 // Don't try to simplify this intrinsic if we don't have AVX.
21765 if (!Subtarget->hasAVX())
21768 case Intrinsic::x86_sse41_pblendw:
21769 case Intrinsic::x86_sse41_blendpd:
21770 case Intrinsic::x86_sse41_blendps:
21771 case Intrinsic::x86_sse41_blendvps:
21772 case Intrinsic::x86_sse41_blendvpd:
21773 case Intrinsic::x86_sse41_pblendvb: {
21774 SDValue Op0 = N->getOperand(1);
21775 SDValue Op1 = N->getOperand(2);
21776 SDValue Mask = N->getOperand(3);
21778 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21779 if (!Subtarget->hasSSE41())
21782 // fold (blend A, A, Mask) -> A
21785 // fold (blend A, B, allZeros) -> A
21786 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21788 // fold (blend A, B, allOnes) -> B
21789 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21792 // Simplify the case where the mask is a constant i32 value.
21793 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21794 if (C->isNullValue())
21796 if (C->isAllOnesValue())
21803 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21804 case Intrinsic::x86_sse2_psrai_w:
21805 case Intrinsic::x86_sse2_psrai_d:
21806 case Intrinsic::x86_avx2_psrai_w:
21807 case Intrinsic::x86_avx2_psrai_d:
21808 case Intrinsic::x86_sse2_psra_w:
21809 case Intrinsic::x86_sse2_psra_d:
21810 case Intrinsic::x86_avx2_psra_w:
21811 case Intrinsic::x86_avx2_psra_d: {
21812 SDValue Op0 = N->getOperand(1);
21813 SDValue Op1 = N->getOperand(2);
21814 EVT VT = Op0.getValueType();
21815 assert(VT.isVector() && "Expected a vector type!");
21817 if (isa<BuildVectorSDNode>(Op1))
21818 Op1 = Op1.getOperand(0);
21820 if (!isa<ConstantSDNode>(Op1))
21823 EVT SVT = VT.getVectorElementType();
21824 unsigned SVTBits = SVT.getSizeInBits();
21826 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21827 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21828 uint64_t ShAmt = C.getZExtValue();
21830 // Don't try to convert this shift into a ISD::SRA if the shift
21831 // count is bigger than or equal to the element size.
21832 if (ShAmt >= SVTBits)
21835 // Trivial case: if the shift count is zero, then fold this
21836 // into the first operand.
21840 // Replace this packed shift intrinsic with a target independent
21842 SDValue Splat = DAG.getConstant(C, VT);
21843 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21848 /// PerformMulCombine - Optimize a single multiply with constant into two
21849 /// in order to implement it with two cheaper instructions, e.g.
21850 /// LEA + SHL, LEA + LEA.
21851 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21852 TargetLowering::DAGCombinerInfo &DCI) {
21853 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21856 EVT VT = N->getValueType(0);
21857 if (VT != MVT::i64)
21860 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21863 uint64_t MulAmt = C->getZExtValue();
21864 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21867 uint64_t MulAmt1 = 0;
21868 uint64_t MulAmt2 = 0;
21869 if ((MulAmt % 9) == 0) {
21871 MulAmt2 = MulAmt / 9;
21872 } else if ((MulAmt % 5) == 0) {
21874 MulAmt2 = MulAmt / 5;
21875 } else if ((MulAmt % 3) == 0) {
21877 MulAmt2 = MulAmt / 3;
21880 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21883 if (isPowerOf2_64(MulAmt2) &&
21884 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21885 // If second multiplifer is pow2, issue it first. We want the multiply by
21886 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21888 std::swap(MulAmt1, MulAmt2);
21891 if (isPowerOf2_64(MulAmt1))
21892 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21893 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21895 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21896 DAG.getConstant(MulAmt1, VT));
21898 if (isPowerOf2_64(MulAmt2))
21899 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21900 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21902 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21903 DAG.getConstant(MulAmt2, VT));
21905 // Do not add new nodes to DAG combiner worklist.
21906 DCI.CombineTo(N, NewMul, false);
21911 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21912 SDValue N0 = N->getOperand(0);
21913 SDValue N1 = N->getOperand(1);
21914 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21915 EVT VT = N0.getValueType();
21917 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21918 // since the result of setcc_c is all zero's or all ones.
21919 if (VT.isInteger() && !VT.isVector() &&
21920 N1C && N0.getOpcode() == ISD::AND &&
21921 N0.getOperand(1).getOpcode() == ISD::Constant) {
21922 SDValue N00 = N0.getOperand(0);
21923 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21924 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21925 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21926 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21927 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21928 APInt ShAmt = N1C->getAPIntValue();
21929 Mask = Mask.shl(ShAmt);
21931 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21932 N00, DAG.getConstant(Mask, VT));
21936 // Hardware support for vector shifts is sparse which makes us scalarize the
21937 // vector operations in many cases. Also, on sandybridge ADD is faster than
21939 // (shl V, 1) -> add V,V
21940 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21941 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21942 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21943 // We shift all of the values by one. In many cases we do not have
21944 // hardware support for this operation. This is better expressed as an ADD
21946 if (N1SplatC->getZExtValue() == 1)
21947 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21953 /// \brief Returns a vector of 0s if the node in input is a vector logical
21954 /// shift by a constant amount which is known to be bigger than or equal
21955 /// to the vector element size in bits.
21956 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21957 const X86Subtarget *Subtarget) {
21958 EVT VT = N->getValueType(0);
21960 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21961 (!Subtarget->hasInt256() ||
21962 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21965 SDValue Amt = N->getOperand(1);
21967 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21968 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21969 APInt ShiftAmt = AmtSplat->getAPIntValue();
21970 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21972 // SSE2/AVX2 logical shifts always return a vector of 0s
21973 // if the shift amount is bigger than or equal to
21974 // the element size. The constant shift amount will be
21975 // encoded as a 8-bit immediate.
21976 if (ShiftAmt.trunc(8).uge(MaxAmount))
21977 return getZeroVector(VT, Subtarget, DAG, DL);
21983 /// PerformShiftCombine - Combine shifts.
21984 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21985 TargetLowering::DAGCombinerInfo &DCI,
21986 const X86Subtarget *Subtarget) {
21987 if (N->getOpcode() == ISD::SHL) {
21988 SDValue V = PerformSHLCombine(N, DAG);
21989 if (V.getNode()) return V;
21992 if (N->getOpcode() != ISD::SRA) {
21993 // Try to fold this logical shift into a zero vector.
21994 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21995 if (V.getNode()) return V;
22001 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22002 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22003 // and friends. Likewise for OR -> CMPNEQSS.
22004 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22005 TargetLowering::DAGCombinerInfo &DCI,
22006 const X86Subtarget *Subtarget) {
22009 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22010 // we're requiring SSE2 for both.
22011 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22012 SDValue N0 = N->getOperand(0);
22013 SDValue N1 = N->getOperand(1);
22014 SDValue CMP0 = N0->getOperand(1);
22015 SDValue CMP1 = N1->getOperand(1);
22018 // The SETCCs should both refer to the same CMP.
22019 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22022 SDValue CMP00 = CMP0->getOperand(0);
22023 SDValue CMP01 = CMP0->getOperand(1);
22024 EVT VT = CMP00.getValueType();
22026 if (VT == MVT::f32 || VT == MVT::f64) {
22027 bool ExpectingFlags = false;
22028 // Check for any users that want flags:
22029 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22030 !ExpectingFlags && UI != UE; ++UI)
22031 switch (UI->getOpcode()) {
22036 ExpectingFlags = true;
22038 case ISD::CopyToReg:
22039 case ISD::SIGN_EXTEND:
22040 case ISD::ZERO_EXTEND:
22041 case ISD::ANY_EXTEND:
22045 if (!ExpectingFlags) {
22046 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22047 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22049 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22050 X86::CondCode tmp = cc0;
22055 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22056 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22057 // FIXME: need symbolic constants for these magic numbers.
22058 // See X86ATTInstPrinter.cpp:printSSECC().
22059 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22060 if (Subtarget->hasAVX512()) {
22061 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22062 CMP01, DAG.getConstant(x86cc, MVT::i8));
22063 if (N->getValueType(0) != MVT::i1)
22064 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22068 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22069 CMP00.getValueType(), CMP00, CMP01,
22070 DAG.getConstant(x86cc, MVT::i8));
22072 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22073 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22075 if (is64BitFP && !Subtarget->is64Bit()) {
22076 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22077 // 64-bit integer, since that's not a legal type. Since
22078 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22079 // bits, but can do this little dance to extract the lowest 32 bits
22080 // and work with those going forward.
22081 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22083 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22085 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22086 Vector32, DAG.getIntPtrConstant(0));
22090 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22091 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22092 DAG.getConstant(1, IntVT));
22093 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22094 return OneBitOfTruth;
22102 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22103 /// so it can be folded inside ANDNP.
22104 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22105 EVT VT = N->getValueType(0);
22107 // Match direct AllOnes for 128 and 256-bit vectors
22108 if (ISD::isBuildVectorAllOnes(N))
22111 // Look through a bit convert.
22112 if (N->getOpcode() == ISD::BITCAST)
22113 N = N->getOperand(0).getNode();
22115 // Sometimes the operand may come from a insert_subvector building a 256-bit
22117 if (VT.is256BitVector() &&
22118 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22119 SDValue V1 = N->getOperand(0);
22120 SDValue V2 = N->getOperand(1);
22122 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22123 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22124 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22125 ISD::isBuildVectorAllOnes(V2.getNode()))
22132 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22133 // register. In most cases we actually compare or select YMM-sized registers
22134 // and mixing the two types creates horrible code. This method optimizes
22135 // some of the transition sequences.
22136 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22137 TargetLowering::DAGCombinerInfo &DCI,
22138 const X86Subtarget *Subtarget) {
22139 EVT VT = N->getValueType(0);
22140 if (!VT.is256BitVector())
22143 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22144 N->getOpcode() == ISD::ZERO_EXTEND ||
22145 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22147 SDValue Narrow = N->getOperand(0);
22148 EVT NarrowVT = Narrow->getValueType(0);
22149 if (!NarrowVT.is128BitVector())
22152 if (Narrow->getOpcode() != ISD::XOR &&
22153 Narrow->getOpcode() != ISD::AND &&
22154 Narrow->getOpcode() != ISD::OR)
22157 SDValue N0 = Narrow->getOperand(0);
22158 SDValue N1 = Narrow->getOperand(1);
22161 // The Left side has to be a trunc.
22162 if (N0.getOpcode() != ISD::TRUNCATE)
22165 // The type of the truncated inputs.
22166 EVT WideVT = N0->getOperand(0)->getValueType(0);
22170 // The right side has to be a 'trunc' or a constant vector.
22171 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22172 ConstantSDNode *RHSConstSplat = nullptr;
22173 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22174 RHSConstSplat = RHSBV->getConstantSplatNode();
22175 if (!RHSTrunc && !RHSConstSplat)
22178 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22180 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22183 // Set N0 and N1 to hold the inputs to the new wide operation.
22184 N0 = N0->getOperand(0);
22185 if (RHSConstSplat) {
22186 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22187 SDValue(RHSConstSplat, 0));
22188 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22189 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22190 } else if (RHSTrunc) {
22191 N1 = N1->getOperand(0);
22194 // Generate the wide operation.
22195 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22196 unsigned Opcode = N->getOpcode();
22198 case ISD::ANY_EXTEND:
22200 case ISD::ZERO_EXTEND: {
22201 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22202 APInt Mask = APInt::getAllOnesValue(InBits);
22203 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22204 return DAG.getNode(ISD::AND, DL, VT,
22205 Op, DAG.getConstant(Mask, VT));
22207 case ISD::SIGN_EXTEND:
22208 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22209 Op, DAG.getValueType(NarrowVT));
22211 llvm_unreachable("Unexpected opcode");
22215 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22216 TargetLowering::DAGCombinerInfo &DCI,
22217 const X86Subtarget *Subtarget) {
22218 EVT VT = N->getValueType(0);
22219 if (DCI.isBeforeLegalizeOps())
22222 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22226 // Create BEXTR instructions
22227 // BEXTR is ((X >> imm) & (2**size-1))
22228 if (VT == MVT::i32 || VT == MVT::i64) {
22229 SDValue N0 = N->getOperand(0);
22230 SDValue N1 = N->getOperand(1);
22233 // Check for BEXTR.
22234 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22235 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22236 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22237 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22238 if (MaskNode && ShiftNode) {
22239 uint64_t Mask = MaskNode->getZExtValue();
22240 uint64_t Shift = ShiftNode->getZExtValue();
22241 if (isMask_64(Mask)) {
22242 uint64_t MaskSize = CountPopulation_64(Mask);
22243 if (Shift + MaskSize <= VT.getSizeInBits())
22244 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22245 DAG.getConstant(Shift | (MaskSize << 8), VT));
22253 // Want to form ANDNP nodes:
22254 // 1) In the hopes of then easily combining them with OR and AND nodes
22255 // to form PBLEND/PSIGN.
22256 // 2) To match ANDN packed intrinsics
22257 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22260 SDValue N0 = N->getOperand(0);
22261 SDValue N1 = N->getOperand(1);
22264 // Check LHS for vnot
22265 if (N0.getOpcode() == ISD::XOR &&
22266 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22267 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22268 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22270 // Check RHS for vnot
22271 if (N1.getOpcode() == ISD::XOR &&
22272 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22273 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22274 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22279 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22280 TargetLowering::DAGCombinerInfo &DCI,
22281 const X86Subtarget *Subtarget) {
22282 if (DCI.isBeforeLegalizeOps())
22285 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22289 SDValue N0 = N->getOperand(0);
22290 SDValue N1 = N->getOperand(1);
22291 EVT VT = N->getValueType(0);
22293 // look for psign/blend
22294 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22295 if (!Subtarget->hasSSSE3() ||
22296 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22299 // Canonicalize pandn to RHS
22300 if (N0.getOpcode() == X86ISD::ANDNP)
22302 // or (and (m, y), (pandn m, x))
22303 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22304 SDValue Mask = N1.getOperand(0);
22305 SDValue X = N1.getOperand(1);
22307 if (N0.getOperand(0) == Mask)
22308 Y = N0.getOperand(1);
22309 if (N0.getOperand(1) == Mask)
22310 Y = N0.getOperand(0);
22312 // Check to see if the mask appeared in both the AND and ANDNP and
22316 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22317 // Look through mask bitcast.
22318 if (Mask.getOpcode() == ISD::BITCAST)
22319 Mask = Mask.getOperand(0);
22320 if (X.getOpcode() == ISD::BITCAST)
22321 X = X.getOperand(0);
22322 if (Y.getOpcode() == ISD::BITCAST)
22323 Y = Y.getOperand(0);
22325 EVT MaskVT = Mask.getValueType();
22327 // Validate that the Mask operand is a vector sra node.
22328 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22329 // there is no psrai.b
22330 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22331 unsigned SraAmt = ~0;
22332 if (Mask.getOpcode() == ISD::SRA) {
22333 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22334 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22335 SraAmt = AmtConst->getZExtValue();
22336 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22337 SDValue SraC = Mask.getOperand(1);
22338 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22340 if ((SraAmt + 1) != EltBits)
22345 // Now we know we at least have a plendvb with the mask val. See if
22346 // we can form a psignb/w/d.
22347 // psign = x.type == y.type == mask.type && y = sub(0, x);
22348 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22349 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22350 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22351 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22352 "Unsupported VT for PSIGN");
22353 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22354 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22356 // PBLENDVB only available on SSE 4.1
22357 if (!Subtarget->hasSSE41())
22360 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22362 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22363 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22364 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22365 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22366 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22370 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22373 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22374 MachineFunction &MF = DAG.getMachineFunction();
22375 bool OptForSize = MF.getFunction()->getAttributes().
22376 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
22378 // SHLD/SHRD instructions have lower register pressure, but on some
22379 // platforms they have higher latency than the equivalent
22380 // series of shifts/or that would otherwise be generated.
22381 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22382 // have higher latencies and we are not optimizing for size.
22383 if (!OptForSize && Subtarget->isSHLDSlow())
22386 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22388 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22390 if (!N0.hasOneUse() || !N1.hasOneUse())
22393 SDValue ShAmt0 = N0.getOperand(1);
22394 if (ShAmt0.getValueType() != MVT::i8)
22396 SDValue ShAmt1 = N1.getOperand(1);
22397 if (ShAmt1.getValueType() != MVT::i8)
22399 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22400 ShAmt0 = ShAmt0.getOperand(0);
22401 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22402 ShAmt1 = ShAmt1.getOperand(0);
22405 unsigned Opc = X86ISD::SHLD;
22406 SDValue Op0 = N0.getOperand(0);
22407 SDValue Op1 = N1.getOperand(0);
22408 if (ShAmt0.getOpcode() == ISD::SUB) {
22409 Opc = X86ISD::SHRD;
22410 std::swap(Op0, Op1);
22411 std::swap(ShAmt0, ShAmt1);
22414 unsigned Bits = VT.getSizeInBits();
22415 if (ShAmt1.getOpcode() == ISD::SUB) {
22416 SDValue Sum = ShAmt1.getOperand(0);
22417 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22418 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22419 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22420 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22421 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22422 return DAG.getNode(Opc, DL, VT,
22424 DAG.getNode(ISD::TRUNCATE, DL,
22427 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22428 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22430 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22431 return DAG.getNode(Opc, DL, VT,
22432 N0.getOperand(0), N1.getOperand(0),
22433 DAG.getNode(ISD::TRUNCATE, DL,
22440 // Generate NEG and CMOV for integer abs.
22441 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22442 EVT VT = N->getValueType(0);
22444 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22445 // 8-bit integer abs to NEG and CMOV.
22446 if (VT.isInteger() && VT.getSizeInBits() == 8)
22449 SDValue N0 = N->getOperand(0);
22450 SDValue N1 = N->getOperand(1);
22453 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22454 // and change it to SUB and CMOV.
22455 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22456 N0.getOpcode() == ISD::ADD &&
22457 N0.getOperand(1) == N1 &&
22458 N1.getOpcode() == ISD::SRA &&
22459 N1.getOperand(0) == N0.getOperand(0))
22460 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22461 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22462 // Generate SUB & CMOV.
22463 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22464 DAG.getConstant(0, VT), N0.getOperand(0));
22466 SDValue Ops[] = { N0.getOperand(0), Neg,
22467 DAG.getConstant(X86::COND_GE, MVT::i8),
22468 SDValue(Neg.getNode(), 1) };
22469 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22474 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22475 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22476 TargetLowering::DAGCombinerInfo &DCI,
22477 const X86Subtarget *Subtarget) {
22478 if (DCI.isBeforeLegalizeOps())
22481 if (Subtarget->hasCMov()) {
22482 SDValue RV = performIntegerAbsCombine(N, DAG);
22490 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22491 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22492 TargetLowering::DAGCombinerInfo &DCI,
22493 const X86Subtarget *Subtarget) {
22494 LoadSDNode *Ld = cast<LoadSDNode>(N);
22495 EVT RegVT = Ld->getValueType(0);
22496 EVT MemVT = Ld->getMemoryVT();
22498 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22500 // On Sandybridge unaligned 256bit loads are inefficient.
22501 ISD::LoadExtType Ext = Ld->getExtensionType();
22502 unsigned Alignment = Ld->getAlignment();
22503 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22504 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
22505 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22506 unsigned NumElems = RegVT.getVectorNumElements();
22510 SDValue Ptr = Ld->getBasePtr();
22511 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22513 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22515 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22516 Ld->getPointerInfo(), Ld->isVolatile(),
22517 Ld->isNonTemporal(), Ld->isInvariant(),
22519 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22520 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22521 Ld->getPointerInfo(), Ld->isVolatile(),
22522 Ld->isNonTemporal(), Ld->isInvariant(),
22523 std::min(16U, Alignment));
22524 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22526 Load2.getValue(1));
22528 SDValue NewVec = DAG.getUNDEF(RegVT);
22529 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22530 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22531 return DCI.CombineTo(N, NewVec, TF, true);
22537 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22538 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22539 const X86Subtarget *Subtarget) {
22540 StoreSDNode *St = cast<StoreSDNode>(N);
22541 EVT VT = St->getValue().getValueType();
22542 EVT StVT = St->getMemoryVT();
22544 SDValue StoredVal = St->getOperand(1);
22545 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22547 // If we are saving a concatenation of two XMM registers, perform two stores.
22548 // On Sandy Bridge, 256-bit memory operations are executed by two
22549 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22550 // memory operation.
22551 unsigned Alignment = St->getAlignment();
22552 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22553 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22554 StVT == VT && !IsAligned) {
22555 unsigned NumElems = VT.getVectorNumElements();
22559 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22560 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22562 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22563 SDValue Ptr0 = St->getBasePtr();
22564 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22566 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22567 St->getPointerInfo(), St->isVolatile(),
22568 St->isNonTemporal(), Alignment);
22569 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22570 St->getPointerInfo(), St->isVolatile(),
22571 St->isNonTemporal(),
22572 std::min(16U, Alignment));
22573 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22576 // Optimize trunc store (of multiple scalars) to shuffle and store.
22577 // First, pack all of the elements in one place. Next, store to memory
22578 // in fewer chunks.
22579 if (St->isTruncatingStore() && VT.isVector()) {
22580 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22581 unsigned NumElems = VT.getVectorNumElements();
22582 assert(StVT != VT && "Cannot truncate to the same type");
22583 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22584 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22586 // From, To sizes and ElemCount must be pow of two
22587 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22588 // We are going to use the original vector elt for storing.
22589 // Accumulated smaller vector elements must be a multiple of the store size.
22590 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22592 unsigned SizeRatio = FromSz / ToSz;
22594 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22596 // Create a type on which we perform the shuffle
22597 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22598 StVT.getScalarType(), NumElems*SizeRatio);
22600 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22602 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22603 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22604 for (unsigned i = 0; i != NumElems; ++i)
22605 ShuffleVec[i] = i * SizeRatio;
22607 // Can't shuffle using an illegal type.
22608 if (!TLI.isTypeLegal(WideVecVT))
22611 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22612 DAG.getUNDEF(WideVecVT),
22614 // At this point all of the data is stored at the bottom of the
22615 // register. We now need to save it to mem.
22617 // Find the largest store unit
22618 MVT StoreType = MVT::i8;
22619 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
22620 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
22621 MVT Tp = (MVT::SimpleValueType)tp;
22622 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22626 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22627 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22628 (64 <= NumElems * ToSz))
22629 StoreType = MVT::f64;
22631 // Bitcast the original vector into a vector of store-size units
22632 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22633 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22634 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22635 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22636 SmallVector<SDValue, 8> Chains;
22637 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22638 TLI.getPointerTy());
22639 SDValue Ptr = St->getBasePtr();
22641 // Perform one or more big stores into memory.
22642 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22643 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22644 StoreType, ShuffWide,
22645 DAG.getIntPtrConstant(i));
22646 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22647 St->getPointerInfo(), St->isVolatile(),
22648 St->isNonTemporal(), St->getAlignment());
22649 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22650 Chains.push_back(Ch);
22653 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22656 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22657 // the FP state in cases where an emms may be missing.
22658 // A preferable solution to the general problem is to figure out the right
22659 // places to insert EMMS. This qualifies as a quick hack.
22661 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22662 if (VT.getSizeInBits() != 64)
22665 const Function *F = DAG.getMachineFunction().getFunction();
22666 bool NoImplicitFloatOps = F->getAttributes().
22667 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22668 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22669 && Subtarget->hasSSE2();
22670 if ((VT.isVector() ||
22671 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22672 isa<LoadSDNode>(St->getValue()) &&
22673 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22674 St->getChain().hasOneUse() && !St->isVolatile()) {
22675 SDNode* LdVal = St->getValue().getNode();
22676 LoadSDNode *Ld = nullptr;
22677 int TokenFactorIndex = -1;
22678 SmallVector<SDValue, 8> Ops;
22679 SDNode* ChainVal = St->getChain().getNode();
22680 // Must be a store of a load. We currently handle two cases: the load
22681 // is a direct child, and it's under an intervening TokenFactor. It is
22682 // possible to dig deeper under nested TokenFactors.
22683 if (ChainVal == LdVal)
22684 Ld = cast<LoadSDNode>(St->getChain());
22685 else if (St->getValue().hasOneUse() &&
22686 ChainVal->getOpcode() == ISD::TokenFactor) {
22687 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22688 if (ChainVal->getOperand(i).getNode() == LdVal) {
22689 TokenFactorIndex = i;
22690 Ld = cast<LoadSDNode>(St->getValue());
22692 Ops.push_back(ChainVal->getOperand(i));
22696 if (!Ld || !ISD::isNormalLoad(Ld))
22699 // If this is not the MMX case, i.e. we are just turning i64 load/store
22700 // into f64 load/store, avoid the transformation if there are multiple
22701 // uses of the loaded value.
22702 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22707 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22708 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22710 if (Subtarget->is64Bit() || F64IsLegal) {
22711 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22712 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22713 Ld->getPointerInfo(), Ld->isVolatile(),
22714 Ld->isNonTemporal(), Ld->isInvariant(),
22715 Ld->getAlignment());
22716 SDValue NewChain = NewLd.getValue(1);
22717 if (TokenFactorIndex != -1) {
22718 Ops.push_back(NewChain);
22719 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22721 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22722 St->getPointerInfo(),
22723 St->isVolatile(), St->isNonTemporal(),
22724 St->getAlignment());
22727 // Otherwise, lower to two pairs of 32-bit loads / stores.
22728 SDValue LoAddr = Ld->getBasePtr();
22729 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22730 DAG.getConstant(4, MVT::i32));
22732 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22733 Ld->getPointerInfo(),
22734 Ld->isVolatile(), Ld->isNonTemporal(),
22735 Ld->isInvariant(), Ld->getAlignment());
22736 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22737 Ld->getPointerInfo().getWithOffset(4),
22738 Ld->isVolatile(), Ld->isNonTemporal(),
22740 MinAlign(Ld->getAlignment(), 4));
22742 SDValue NewChain = LoLd.getValue(1);
22743 if (TokenFactorIndex != -1) {
22744 Ops.push_back(LoLd);
22745 Ops.push_back(HiLd);
22746 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22749 LoAddr = St->getBasePtr();
22750 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22751 DAG.getConstant(4, MVT::i32));
22753 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22754 St->getPointerInfo(),
22755 St->isVolatile(), St->isNonTemporal(),
22756 St->getAlignment());
22757 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22758 St->getPointerInfo().getWithOffset(4),
22760 St->isNonTemporal(),
22761 MinAlign(St->getAlignment(), 4));
22762 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22767 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
22768 /// and return the operands for the horizontal operation in LHS and RHS. A
22769 /// horizontal operation performs the binary operation on successive elements
22770 /// of its first operand, then on successive elements of its second operand,
22771 /// returning the resulting values in a vector. For example, if
22772 /// A = < float a0, float a1, float a2, float a3 >
22774 /// B = < float b0, float b1, float b2, float b3 >
22775 /// then the result of doing a horizontal operation on A and B is
22776 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22777 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22778 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22779 /// set to A, RHS to B, and the routine returns 'true'.
22780 /// Note that the binary operation should have the property that if one of the
22781 /// operands is UNDEF then the result is UNDEF.
22782 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22783 // Look for the following pattern: if
22784 // A = < float a0, float a1, float a2, float a3 >
22785 // B = < float b0, float b1, float b2, float b3 >
22787 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22788 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22789 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22790 // which is A horizontal-op B.
22792 // At least one of the operands should be a vector shuffle.
22793 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22794 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22797 MVT VT = LHS.getSimpleValueType();
22799 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22800 "Unsupported vector type for horizontal add/sub");
22802 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22803 // operate independently on 128-bit lanes.
22804 unsigned NumElts = VT.getVectorNumElements();
22805 unsigned NumLanes = VT.getSizeInBits()/128;
22806 unsigned NumLaneElts = NumElts / NumLanes;
22807 assert((NumLaneElts % 2 == 0) &&
22808 "Vector type should have an even number of elements in each lane");
22809 unsigned HalfLaneElts = NumLaneElts/2;
22811 // View LHS in the form
22812 // LHS = VECTOR_SHUFFLE A, B, LMask
22813 // If LHS is not a shuffle then pretend it is the shuffle
22814 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22815 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22818 SmallVector<int, 16> LMask(NumElts);
22819 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22820 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22821 A = LHS.getOperand(0);
22822 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22823 B = LHS.getOperand(1);
22824 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22825 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22827 if (LHS.getOpcode() != ISD::UNDEF)
22829 for (unsigned i = 0; i != NumElts; ++i)
22833 // Likewise, view RHS in the form
22834 // RHS = VECTOR_SHUFFLE C, D, RMask
22836 SmallVector<int, 16> RMask(NumElts);
22837 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22838 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
22839 C = RHS.getOperand(0);
22840 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
22841 D = RHS.getOperand(1);
22842 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
22843 std::copy(Mask.begin(), Mask.end(), RMask.begin());
22845 if (RHS.getOpcode() != ISD::UNDEF)
22847 for (unsigned i = 0; i != NumElts; ++i)
22851 // Check that the shuffles are both shuffling the same vectors.
22852 if (!(A == C && B == D) && !(A == D && B == C))
22855 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
22856 if (!A.getNode() && !B.getNode())
22859 // If A and B occur in reverse order in RHS, then "swap" them (which means
22860 // rewriting the mask).
22862 CommuteVectorShuffleMask(RMask, NumElts);
22864 // At this point LHS and RHS are equivalent to
22865 // LHS = VECTOR_SHUFFLE A, B, LMask
22866 // RHS = VECTOR_SHUFFLE A, B, RMask
22867 // Check that the masks correspond to performing a horizontal operation.
22868 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
22869 for (unsigned i = 0; i != NumLaneElts; ++i) {
22870 int LIdx = LMask[i+l], RIdx = RMask[i+l];
22872 // Ignore any UNDEF components.
22873 if (LIdx < 0 || RIdx < 0 ||
22874 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
22875 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
22878 // Check that successive elements are being operated on. If not, this is
22879 // not a horizontal operation.
22880 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
22881 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
22882 if (!(LIdx == Index && RIdx == Index + 1) &&
22883 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
22888 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
22889 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
22893 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
22894 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22895 const X86Subtarget *Subtarget) {
22896 EVT VT = N->getValueType(0);
22897 SDValue LHS = N->getOperand(0);
22898 SDValue RHS = N->getOperand(1);
22900 // Try to synthesize horizontal adds from adds of shuffles.
22901 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22902 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22903 isHorizontalBinOp(LHS, RHS, true))
22904 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
22908 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
22909 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
22910 const X86Subtarget *Subtarget) {
22911 EVT VT = N->getValueType(0);
22912 SDValue LHS = N->getOperand(0);
22913 SDValue RHS = N->getOperand(1);
22915 // Try to synthesize horizontal subs from subs of shuffles.
22916 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22917 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22918 isHorizontalBinOp(LHS, RHS, false))
22919 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
22923 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
22924 /// X86ISD::FXOR nodes.
22925 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
22926 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
22927 // F[X]OR(0.0, x) -> x
22928 // F[X]OR(x, 0.0) -> x
22929 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22930 if (C->getValueAPF().isPosZero())
22931 return N->getOperand(1);
22932 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22933 if (C->getValueAPF().isPosZero())
22934 return N->getOperand(0);
22938 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
22939 /// X86ISD::FMAX nodes.
22940 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
22941 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22943 // Only perform optimizations if UnsafeMath is used.
22944 if (!DAG.getTarget().Options.UnsafeFPMath)
22947 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22948 // into FMINC and FMAXC, which are Commutative operations.
22949 unsigned NewOp = 0;
22950 switch (N->getOpcode()) {
22951 default: llvm_unreachable("unknown opcode");
22952 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
22953 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
22956 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
22957 N->getOperand(0), N->getOperand(1));
22960 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
22961 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
22962 // FAND(0.0, x) -> 0.0
22963 // FAND(x, 0.0) -> 0.0
22964 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22965 if (C->getValueAPF().isPosZero())
22966 return N->getOperand(0);
22967 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22968 if (C->getValueAPF().isPosZero())
22969 return N->getOperand(1);
22973 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
22974 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
22975 // FANDN(x, 0.0) -> 0.0
22976 // FANDN(0.0, x) -> x
22977 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22978 if (C->getValueAPF().isPosZero())
22979 return N->getOperand(1);
22980 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22981 if (C->getValueAPF().isPosZero())
22982 return N->getOperand(1);
22986 static SDValue PerformBTCombine(SDNode *N,
22988 TargetLowering::DAGCombinerInfo &DCI) {
22989 // BT ignores high bits in the bit index operand.
22990 SDValue Op1 = N->getOperand(1);
22991 if (Op1.hasOneUse()) {
22992 unsigned BitWidth = Op1.getValueSizeInBits();
22993 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
22994 APInt KnownZero, KnownOne;
22995 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22996 !DCI.isBeforeLegalizeOps());
22997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22998 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
22999 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23000 DCI.CommitTargetLoweringOpt(TLO);
23005 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23006 SDValue Op = N->getOperand(0);
23007 if (Op.getOpcode() == ISD::BITCAST)
23008 Op = Op.getOperand(0);
23009 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23010 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23011 VT.getVectorElementType().getSizeInBits() ==
23012 OpVT.getVectorElementType().getSizeInBits()) {
23013 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23018 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23019 const X86Subtarget *Subtarget) {
23020 EVT VT = N->getValueType(0);
23021 if (!VT.isVector())
23024 SDValue N0 = N->getOperand(0);
23025 SDValue N1 = N->getOperand(1);
23026 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23029 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23030 // both SSE and AVX2 since there is no sign-extended shift right
23031 // operation on a vector with 64-bit elements.
23032 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23033 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23034 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23035 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23036 SDValue N00 = N0.getOperand(0);
23038 // EXTLOAD has a better solution on AVX2,
23039 // it may be replaced with X86ISD::VSEXT node.
23040 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23041 if (!ISD::isNormalLoad(N00.getNode()))
23044 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23045 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23047 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23053 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23054 TargetLowering::DAGCombinerInfo &DCI,
23055 const X86Subtarget *Subtarget) {
23056 if (!DCI.isBeforeLegalizeOps())
23059 if (!Subtarget->hasFp256())
23062 EVT VT = N->getValueType(0);
23063 if (VT.isVector() && VT.getSizeInBits() == 256) {
23064 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23072 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23073 const X86Subtarget* Subtarget) {
23075 EVT VT = N->getValueType(0);
23077 // Let legalize expand this if it isn't a legal type yet.
23078 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23081 EVT ScalarVT = VT.getScalarType();
23082 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23083 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23086 SDValue A = N->getOperand(0);
23087 SDValue B = N->getOperand(1);
23088 SDValue C = N->getOperand(2);
23090 bool NegA = (A.getOpcode() == ISD::FNEG);
23091 bool NegB = (B.getOpcode() == ISD::FNEG);
23092 bool NegC = (C.getOpcode() == ISD::FNEG);
23094 // Negative multiplication when NegA xor NegB
23095 bool NegMul = (NegA != NegB);
23097 A = A.getOperand(0);
23099 B = B.getOperand(0);
23101 C = C.getOperand(0);
23105 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23107 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23109 return DAG.getNode(Opcode, dl, VT, A, B, C);
23112 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23113 TargetLowering::DAGCombinerInfo &DCI,
23114 const X86Subtarget *Subtarget) {
23115 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23116 // (and (i32 x86isd::setcc_carry), 1)
23117 // This eliminates the zext. This transformation is necessary because
23118 // ISD::SETCC is always legalized to i8.
23120 SDValue N0 = N->getOperand(0);
23121 EVT VT = N->getValueType(0);
23123 if (N0.getOpcode() == ISD::AND &&
23125 N0.getOperand(0).hasOneUse()) {
23126 SDValue N00 = N0.getOperand(0);
23127 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23128 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23129 if (!C || C->getZExtValue() != 1)
23131 return DAG.getNode(ISD::AND, dl, VT,
23132 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23133 N00.getOperand(0), N00.getOperand(1)),
23134 DAG.getConstant(1, VT));
23138 if (N0.getOpcode() == ISD::TRUNCATE &&
23140 N0.getOperand(0).hasOneUse()) {
23141 SDValue N00 = N0.getOperand(0);
23142 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23143 return DAG.getNode(ISD::AND, dl, VT,
23144 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23145 N00.getOperand(0), N00.getOperand(1)),
23146 DAG.getConstant(1, VT));
23149 if (VT.is256BitVector()) {
23150 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23158 // Optimize x == -y --> x+y == 0
23159 // x != -y --> x+y != 0
23160 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23161 const X86Subtarget* Subtarget) {
23162 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23163 SDValue LHS = N->getOperand(0);
23164 SDValue RHS = N->getOperand(1);
23165 EVT VT = N->getValueType(0);
23168 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23169 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23170 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23171 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23172 LHS.getValueType(), RHS, LHS.getOperand(1));
23173 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23174 addV, DAG.getConstant(0, addV.getValueType()), CC);
23176 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23177 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23178 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23179 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23180 RHS.getValueType(), LHS, RHS.getOperand(1));
23181 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23182 addV, DAG.getConstant(0, addV.getValueType()), CC);
23185 if (VT.getScalarType() == MVT::i1) {
23186 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23187 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23188 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23189 if (!IsSEXT0 && !IsVZero0)
23191 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23192 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23193 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23195 if (!IsSEXT1 && !IsVZero1)
23198 if (IsSEXT0 && IsVZero1) {
23199 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23200 if (CC == ISD::SETEQ)
23201 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23202 return LHS.getOperand(0);
23204 if (IsSEXT1 && IsVZero0) {
23205 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23206 if (CC == ISD::SETEQ)
23207 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23208 return RHS.getOperand(0);
23215 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23216 const X86Subtarget *Subtarget) {
23218 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23219 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23220 "X86insertps is only defined for v4x32");
23222 SDValue Ld = N->getOperand(1);
23223 if (MayFoldLoad(Ld)) {
23224 // Extract the countS bits from the immediate so we can get the proper
23225 // address when narrowing the vector load to a specific element.
23226 // When the second source op is a memory address, interps doesn't use
23227 // countS and just gets an f32 from that address.
23228 unsigned DestIndex =
23229 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23230 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23234 // Create this as a scalar to vector to match the instruction pattern.
23235 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23236 // countS bits are ignored when loading from memory on insertps, which
23237 // means we don't need to explicitly set them to 0.
23238 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23239 LoadScalarToVector, N->getOperand(2));
23242 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23243 // as "sbb reg,reg", since it can be extended without zext and produces
23244 // an all-ones bit which is more useful than 0/1 in some cases.
23245 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23248 return DAG.getNode(ISD::AND, DL, VT,
23249 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23250 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23251 DAG.getConstant(1, VT));
23252 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23253 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23254 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23255 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23258 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23259 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23260 TargetLowering::DAGCombinerInfo &DCI,
23261 const X86Subtarget *Subtarget) {
23263 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23264 SDValue EFLAGS = N->getOperand(1);
23266 if (CC == X86::COND_A) {
23267 // Try to convert COND_A into COND_B in an attempt to facilitate
23268 // materializing "setb reg".
23270 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23271 // cannot take an immediate as its first operand.
23273 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23274 EFLAGS.getValueType().isInteger() &&
23275 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23276 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23277 EFLAGS.getNode()->getVTList(),
23278 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23279 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23280 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23284 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23285 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23287 if (CC == X86::COND_B)
23288 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23292 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23293 if (Flags.getNode()) {
23294 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23295 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23301 // Optimize branch condition evaluation.
23303 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23304 TargetLowering::DAGCombinerInfo &DCI,
23305 const X86Subtarget *Subtarget) {
23307 SDValue Chain = N->getOperand(0);
23308 SDValue Dest = N->getOperand(1);
23309 SDValue EFLAGS = N->getOperand(3);
23310 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23314 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23315 if (Flags.getNode()) {
23316 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23317 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23324 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23325 SelectionDAG &DAG) {
23326 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23327 // optimize away operation when it's from a constant.
23329 // The general transformation is:
23330 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23331 // AND(VECTOR_CMP(x,y), constant2)
23332 // constant2 = UNARYOP(constant)
23334 // Early exit if this isn't a vector operation, the operand of the
23335 // unary operation isn't a bitwise AND, or if the sizes of the operations
23336 // aren't the same.
23337 EVT VT = N->getValueType(0);
23338 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23339 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23340 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23343 // Now check that the other operand of the AND is a constant. We could
23344 // make the transformation for non-constant splats as well, but it's unclear
23345 // that would be a benefit as it would not eliminate any operations, just
23346 // perform one more step in scalar code before moving to the vector unit.
23347 if (BuildVectorSDNode *BV =
23348 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23349 // Bail out if the vector isn't a constant.
23350 if (!BV->isConstant())
23353 // Everything checks out. Build up the new and improved node.
23355 EVT IntVT = BV->getValueType(0);
23356 // Create a new constant of the appropriate type for the transformed
23358 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23359 // The AND node needs bitcasts to/from an integer vector type around it.
23360 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23361 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23362 N->getOperand(0)->getOperand(0), MaskConst);
23363 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23370 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23371 const X86TargetLowering *XTLI) {
23372 // First try to optimize away the conversion entirely when it's
23373 // conditionally from a constant. Vectors only.
23374 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23375 if (Res != SDValue())
23378 // Now move on to more general possibilities.
23379 SDValue Op0 = N->getOperand(0);
23380 EVT InVT = Op0->getValueType(0);
23382 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23383 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23385 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23386 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23387 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23390 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23391 // a 32-bit target where SSE doesn't support i64->FP operations.
23392 if (Op0.getOpcode() == ISD::LOAD) {
23393 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23394 EVT VT = Ld->getValueType(0);
23395 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23396 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23397 !XTLI->getSubtarget()->is64Bit() &&
23399 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
23400 Ld->getChain(), Op0, DAG);
23401 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23408 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23409 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23410 X86TargetLowering::DAGCombinerInfo &DCI) {
23411 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23412 // the result is either zero or one (depending on the input carry bit).
23413 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23414 if (X86::isZeroNode(N->getOperand(0)) &&
23415 X86::isZeroNode(N->getOperand(1)) &&
23416 // We don't have a good way to replace an EFLAGS use, so only do this when
23418 SDValue(N, 1).use_empty()) {
23420 EVT VT = N->getValueType(0);
23421 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23422 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23423 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23424 DAG.getConstant(X86::COND_B,MVT::i8),
23426 DAG.getConstant(1, VT));
23427 return DCI.CombineTo(N, Res1, CarryOut);
23433 // fold (add Y, (sete X, 0)) -> adc 0, Y
23434 // (add Y, (setne X, 0)) -> sbb -1, Y
23435 // (sub (sete X, 0), Y) -> sbb 0, Y
23436 // (sub (setne X, 0), Y) -> adc -1, Y
23437 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23440 // Look through ZExts.
23441 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23442 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23445 SDValue SetCC = Ext.getOperand(0);
23446 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23449 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23450 if (CC != X86::COND_E && CC != X86::COND_NE)
23453 SDValue Cmp = SetCC.getOperand(1);
23454 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23455 !X86::isZeroNode(Cmp.getOperand(1)) ||
23456 !Cmp.getOperand(0).getValueType().isInteger())
23459 SDValue CmpOp0 = Cmp.getOperand(0);
23460 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23461 DAG.getConstant(1, CmpOp0.getValueType()));
23463 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23464 if (CC == X86::COND_NE)
23465 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23466 DL, OtherVal.getValueType(), OtherVal,
23467 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23468 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23469 DL, OtherVal.getValueType(), OtherVal,
23470 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23473 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23474 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23475 const X86Subtarget *Subtarget) {
23476 EVT VT = N->getValueType(0);
23477 SDValue Op0 = N->getOperand(0);
23478 SDValue Op1 = N->getOperand(1);
23480 // Try to synthesize horizontal adds from adds of shuffles.
23481 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23482 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23483 isHorizontalBinOp(Op0, Op1, true))
23484 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23486 return OptimizeConditionalInDecrement(N, DAG);
23489 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23490 const X86Subtarget *Subtarget) {
23491 SDValue Op0 = N->getOperand(0);
23492 SDValue Op1 = N->getOperand(1);
23494 // X86 can't encode an immediate LHS of a sub. See if we can push the
23495 // negation into a preceding instruction.
23496 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23497 // If the RHS of the sub is a XOR with one use and a constant, invert the
23498 // immediate. Then add one to the LHS of the sub so we can turn
23499 // X-Y -> X+~Y+1, saving one register.
23500 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23501 isa<ConstantSDNode>(Op1.getOperand(1))) {
23502 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23503 EVT VT = Op0.getValueType();
23504 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23506 DAG.getConstant(~XorC, VT));
23507 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23508 DAG.getConstant(C->getAPIntValue()+1, VT));
23512 // Try to synthesize horizontal adds from adds of shuffles.
23513 EVT VT = N->getValueType(0);
23514 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23515 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23516 isHorizontalBinOp(Op0, Op1, true))
23517 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23519 return OptimizeConditionalInDecrement(N, DAG);
23522 /// performVZEXTCombine - Performs build vector combines
23523 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23524 TargetLowering::DAGCombinerInfo &DCI,
23525 const X86Subtarget *Subtarget) {
23526 // (vzext (bitcast (vzext (x)) -> (vzext x)
23527 SDValue In = N->getOperand(0);
23528 while (In.getOpcode() == ISD::BITCAST)
23529 In = In.getOperand(0);
23531 if (In.getOpcode() != X86ISD::VZEXT)
23534 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
23538 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23539 DAGCombinerInfo &DCI) const {
23540 SelectionDAG &DAG = DCI.DAG;
23541 switch (N->getOpcode()) {
23543 case ISD::EXTRACT_VECTOR_ELT:
23544 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23546 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23547 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23548 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23549 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23550 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23551 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23554 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23555 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23556 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23557 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23558 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23559 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23560 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23561 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23562 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23564 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23566 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23567 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23568 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23569 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23570 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23571 case ISD::ANY_EXTEND:
23572 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23573 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23574 case ISD::SIGN_EXTEND_INREG:
23575 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23576 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23577 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23578 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23579 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23580 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23581 case X86ISD::SHUFP: // Handle all target specific shuffles
23582 case X86ISD::PALIGNR:
23583 case X86ISD::UNPCKH:
23584 case X86ISD::UNPCKL:
23585 case X86ISD::MOVHLPS:
23586 case X86ISD::MOVLHPS:
23587 case X86ISD::PSHUFB:
23588 case X86ISD::PSHUFD:
23589 case X86ISD::PSHUFHW:
23590 case X86ISD::PSHUFLW:
23591 case X86ISD::MOVSS:
23592 case X86ISD::MOVSD:
23593 case X86ISD::VPERMILP:
23594 case X86ISD::VPERM2X128:
23595 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23596 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23597 case ISD::INTRINSIC_WO_CHAIN:
23598 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23599 case X86ISD::INSERTPS:
23600 return PerformINSERTPSCombine(N, DAG, Subtarget);
23601 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23607 /// isTypeDesirableForOp - Return true if the target has native support for
23608 /// the specified value type and it is 'desirable' to use the type for the
23609 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23610 /// instruction encodings are longer and some i16 instructions are slow.
23611 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23612 if (!isTypeLegal(VT))
23614 if (VT != MVT::i16)
23621 case ISD::SIGN_EXTEND:
23622 case ISD::ZERO_EXTEND:
23623 case ISD::ANY_EXTEND:
23636 /// IsDesirableToPromoteOp - This method query the target whether it is
23637 /// beneficial for dag combiner to promote the specified node. If true, it
23638 /// should return the desired promotion type by reference.
23639 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23640 EVT VT = Op.getValueType();
23641 if (VT != MVT::i16)
23644 bool Promote = false;
23645 bool Commute = false;
23646 switch (Op.getOpcode()) {
23649 LoadSDNode *LD = cast<LoadSDNode>(Op);
23650 // If the non-extending load has a single use and it's not live out, then it
23651 // might be folded.
23652 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23653 Op.hasOneUse()*/) {
23654 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23655 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23656 // The only case where we'd want to promote LOAD (rather then it being
23657 // promoted as an operand is when it's only use is liveout.
23658 if (UI->getOpcode() != ISD::CopyToReg)
23665 case ISD::SIGN_EXTEND:
23666 case ISD::ZERO_EXTEND:
23667 case ISD::ANY_EXTEND:
23672 SDValue N0 = Op.getOperand(0);
23673 // Look out for (store (shl (load), x)).
23674 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23687 SDValue N0 = Op.getOperand(0);
23688 SDValue N1 = Op.getOperand(1);
23689 if (!Commute && MayFoldLoad(N1))
23691 // Avoid disabling potential load folding opportunities.
23692 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23694 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
23704 //===----------------------------------------------------------------------===//
23705 // X86 Inline Assembly Support
23706 //===----------------------------------------------------------------------===//
23709 // Helper to match a string separated by whitespace.
23710 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
23711 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
23713 for (unsigned i = 0, e = args.size(); i != e; ++i) {
23714 StringRef piece(*args[i]);
23715 if (!s.startswith(piece)) // Check if the piece matches.
23718 s = s.substr(piece.size());
23719 StringRef::size_type pos = s.find_first_not_of(" \t");
23720 if (pos == 0) // We matched a prefix.
23728 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
23731 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
23733 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
23734 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
23735 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
23736 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
23738 if (AsmPieces.size() == 3)
23740 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
23747 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
23748 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
23750 std::string AsmStr = IA->getAsmString();
23752 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
23753 if (!Ty || Ty->getBitWidth() % 16 != 0)
23756 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
23757 SmallVector<StringRef, 4> AsmPieces;
23758 SplitString(AsmStr, AsmPieces, ";\n");
23760 switch (AsmPieces.size()) {
23761 default: return false;
23763 // FIXME: this should verify that we are targeting a 486 or better. If not,
23764 // we will turn this bswap into something that will be lowered to logical
23765 // ops instead of emitting the bswap asm. For now, we don't support 486 or
23766 // lower so don't worry about this.
23768 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
23769 matchAsm(AsmPieces[0], "bswapl", "$0") ||
23770 matchAsm(AsmPieces[0], "bswapq", "$0") ||
23771 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
23772 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
23773 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
23774 // No need to check constraints, nothing other than the equivalent of
23775 // "=r,0" would be valid here.
23776 return IntrinsicLowering::LowerToByteSwap(CI);
23779 // rorw $$8, ${0:w} --> llvm.bswap.i16
23780 if (CI->getType()->isIntegerTy(16) &&
23781 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23782 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
23783 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
23785 const std::string &ConstraintsStr = IA->getConstraintString();
23786 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23787 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23788 if (clobbersFlagRegisters(AsmPieces))
23789 return IntrinsicLowering::LowerToByteSwap(CI);
23793 if (CI->getType()->isIntegerTy(32) &&
23794 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23795 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
23796 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
23797 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
23799 const std::string &ConstraintsStr = IA->getConstraintString();
23800 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23801 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23802 if (clobbersFlagRegisters(AsmPieces))
23803 return IntrinsicLowering::LowerToByteSwap(CI);
23806 if (CI->getType()->isIntegerTy(64)) {
23807 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
23808 if (Constraints.size() >= 2 &&
23809 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
23810 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
23811 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
23812 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
23813 matchAsm(AsmPieces[1], "bswap", "%edx") &&
23814 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
23815 return IntrinsicLowering::LowerToByteSwap(CI);
23823 /// getConstraintType - Given a constraint letter, return the type of
23824 /// constraint it is for this target.
23825 X86TargetLowering::ConstraintType
23826 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
23827 if (Constraint.size() == 1) {
23828 switch (Constraint[0]) {
23839 return C_RegisterClass;
23863 return TargetLowering::getConstraintType(Constraint);
23866 /// Examine constraint type and operand type and determine a weight value.
23867 /// This object must already have been set up with the operand type
23868 /// and the current alternative constraint selected.
23869 TargetLowering::ConstraintWeight
23870 X86TargetLowering::getSingleConstraintMatchWeight(
23871 AsmOperandInfo &info, const char *constraint) const {
23872 ConstraintWeight weight = CW_Invalid;
23873 Value *CallOperandVal = info.CallOperandVal;
23874 // If we don't have a value, we can't do a match,
23875 // but allow it at the lowest weight.
23876 if (!CallOperandVal)
23878 Type *type = CallOperandVal->getType();
23879 // Look at the constraint type.
23880 switch (*constraint) {
23882 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
23893 if (CallOperandVal->getType()->isIntegerTy())
23894 weight = CW_SpecificReg;
23899 if (type->isFloatingPointTy())
23900 weight = CW_SpecificReg;
23903 if (type->isX86_MMXTy() && Subtarget->hasMMX())
23904 weight = CW_SpecificReg;
23908 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
23909 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
23910 weight = CW_Register;
23913 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
23914 if (C->getZExtValue() <= 31)
23915 weight = CW_Constant;
23919 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23920 if (C->getZExtValue() <= 63)
23921 weight = CW_Constant;
23925 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23926 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
23927 weight = CW_Constant;
23931 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23932 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
23933 weight = CW_Constant;
23937 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23938 if (C->getZExtValue() <= 3)
23939 weight = CW_Constant;
23943 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23944 if (C->getZExtValue() <= 0xff)
23945 weight = CW_Constant;
23950 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23951 weight = CW_Constant;
23955 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23956 if ((C->getSExtValue() >= -0x80000000LL) &&
23957 (C->getSExtValue() <= 0x7fffffffLL))
23958 weight = CW_Constant;
23962 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23963 if (C->getZExtValue() <= 0xffffffff)
23964 weight = CW_Constant;
23971 /// LowerXConstraint - try to replace an X constraint, which matches anything,
23972 /// with another that has more specific requirements based on the type of the
23973 /// corresponding operand.
23974 const char *X86TargetLowering::
23975 LowerXConstraint(EVT ConstraintVT) const {
23976 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
23977 // 'f' like normal targets.
23978 if (ConstraintVT.isFloatingPoint()) {
23979 if (Subtarget->hasSSE2())
23981 if (Subtarget->hasSSE1())
23985 return TargetLowering::LowerXConstraint(ConstraintVT);
23988 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
23989 /// vector. If it is invalid, don't add anything to Ops.
23990 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
23991 std::string &Constraint,
23992 std::vector<SDValue>&Ops,
23993 SelectionDAG &DAG) const {
23996 // Only support length 1 constraints for now.
23997 if (Constraint.length() > 1) return;
23999 char ConstraintLetter = Constraint[0];
24000 switch (ConstraintLetter) {
24003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24004 if (C->getZExtValue() <= 31) {
24005 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24011 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24012 if (C->getZExtValue() <= 63) {
24013 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24019 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24020 if (isInt<8>(C->getSExtValue())) {
24021 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24027 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24028 if (C->getZExtValue() <= 255) {
24029 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24035 // 32-bit signed value
24036 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24037 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24038 C->getSExtValue())) {
24039 // Widen to 64 bits here to get it sign extended.
24040 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24043 // FIXME gcc accepts some relocatable values here too, but only in certain
24044 // memory models; it's complicated.
24049 // 32-bit unsigned value
24050 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24051 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24052 C->getZExtValue())) {
24053 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24057 // FIXME gcc accepts some relocatable values here too, but only in certain
24058 // memory models; it's complicated.
24062 // Literal immediates are always ok.
24063 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24064 // Widen to 64 bits here to get it sign extended.
24065 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24069 // In any sort of PIC mode addresses need to be computed at runtime by
24070 // adding in a register or some sort of table lookup. These can't
24071 // be used as immediates.
24072 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24075 // If we are in non-pic codegen mode, we allow the address of a global (with
24076 // an optional displacement) to be used with 'i'.
24077 GlobalAddressSDNode *GA = nullptr;
24078 int64_t Offset = 0;
24080 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24082 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24083 Offset += GA->getOffset();
24085 } else if (Op.getOpcode() == ISD::ADD) {
24086 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24087 Offset += C->getZExtValue();
24088 Op = Op.getOperand(0);
24091 } else if (Op.getOpcode() == ISD::SUB) {
24092 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24093 Offset += -C->getZExtValue();
24094 Op = Op.getOperand(0);
24099 // Otherwise, this isn't something we can handle, reject it.
24103 const GlobalValue *GV = GA->getGlobal();
24104 // If we require an extra load to get this address, as in PIC mode, we
24105 // can't accept it.
24106 if (isGlobalStubReference(
24107 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24110 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24111 GA->getValueType(0), Offset);
24116 if (Result.getNode()) {
24117 Ops.push_back(Result);
24120 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24123 std::pair<unsigned, const TargetRegisterClass*>
24124 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24126 // First, see if this is a constraint that directly corresponds to an LLVM
24128 if (Constraint.size() == 1) {
24129 // GCC Constraint Letters
24130 switch (Constraint[0]) {
24132 // TODO: Slight differences here in allocation order and leaving
24133 // RIP in the class. Do they matter any more here than they do
24134 // in the normal allocation?
24135 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24136 if (Subtarget->is64Bit()) {
24137 if (VT == MVT::i32 || VT == MVT::f32)
24138 return std::make_pair(0U, &X86::GR32RegClass);
24139 if (VT == MVT::i16)
24140 return std::make_pair(0U, &X86::GR16RegClass);
24141 if (VT == MVT::i8 || VT == MVT::i1)
24142 return std::make_pair(0U, &X86::GR8RegClass);
24143 if (VT == MVT::i64 || VT == MVT::f64)
24144 return std::make_pair(0U, &X86::GR64RegClass);
24147 // 32-bit fallthrough
24148 case 'Q': // Q_REGS
24149 if (VT == MVT::i32 || VT == MVT::f32)
24150 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24151 if (VT == MVT::i16)
24152 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24153 if (VT == MVT::i8 || VT == MVT::i1)
24154 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24155 if (VT == MVT::i64)
24156 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24158 case 'r': // GENERAL_REGS
24159 case 'l': // INDEX_REGS
24160 if (VT == MVT::i8 || VT == MVT::i1)
24161 return std::make_pair(0U, &X86::GR8RegClass);
24162 if (VT == MVT::i16)
24163 return std::make_pair(0U, &X86::GR16RegClass);
24164 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24165 return std::make_pair(0U, &X86::GR32RegClass);
24166 return std::make_pair(0U, &X86::GR64RegClass);
24167 case 'R': // LEGACY_REGS
24168 if (VT == MVT::i8 || VT == MVT::i1)
24169 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24170 if (VT == MVT::i16)
24171 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24172 if (VT == MVT::i32 || !Subtarget->is64Bit())
24173 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24174 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24175 case 'f': // FP Stack registers.
24176 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24177 // value to the correct fpstack register class.
24178 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24179 return std::make_pair(0U, &X86::RFP32RegClass);
24180 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24181 return std::make_pair(0U, &X86::RFP64RegClass);
24182 return std::make_pair(0U, &X86::RFP80RegClass);
24183 case 'y': // MMX_REGS if MMX allowed.
24184 if (!Subtarget->hasMMX()) break;
24185 return std::make_pair(0U, &X86::VR64RegClass);
24186 case 'Y': // SSE_REGS if SSE2 allowed
24187 if (!Subtarget->hasSSE2()) break;
24189 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24190 if (!Subtarget->hasSSE1()) break;
24192 switch (VT.SimpleTy) {
24194 // Scalar SSE types.
24197 return std::make_pair(0U, &X86::FR32RegClass);
24200 return std::make_pair(0U, &X86::FR64RegClass);
24208 return std::make_pair(0U, &X86::VR128RegClass);
24216 return std::make_pair(0U, &X86::VR256RegClass);
24221 return std::make_pair(0U, &X86::VR512RegClass);
24227 // Use the default implementation in TargetLowering to convert the register
24228 // constraint into a member of a register class.
24229 std::pair<unsigned, const TargetRegisterClass*> Res;
24230 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24232 // Not found as a standard register?
24234 // Map st(0) -> st(7) -> ST0
24235 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24236 tolower(Constraint[1]) == 's' &&
24237 tolower(Constraint[2]) == 't' &&
24238 Constraint[3] == '(' &&
24239 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24240 Constraint[5] == ')' &&
24241 Constraint[6] == '}') {
24243 Res.first = X86::FP0+Constraint[4]-'0';
24244 Res.second = &X86::RFP80RegClass;
24248 // GCC allows "st(0)" to be called just plain "st".
24249 if (StringRef("{st}").equals_lower(Constraint)) {
24250 Res.first = X86::FP0;
24251 Res.second = &X86::RFP80RegClass;
24256 if (StringRef("{flags}").equals_lower(Constraint)) {
24257 Res.first = X86::EFLAGS;
24258 Res.second = &X86::CCRRegClass;
24262 // 'A' means EAX + EDX.
24263 if (Constraint == "A") {
24264 Res.first = X86::EAX;
24265 Res.second = &X86::GR32_ADRegClass;
24271 // Otherwise, check to see if this is a register class of the wrong value
24272 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24273 // turn into {ax},{dx}.
24274 if (Res.second->hasType(VT))
24275 return Res; // Correct type already, nothing to do.
24277 // All of the single-register GCC register classes map their values onto
24278 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24279 // really want an 8-bit or 32-bit register, map to the appropriate register
24280 // class and return the appropriate register.
24281 if (Res.second == &X86::GR16RegClass) {
24282 if (VT == MVT::i8 || VT == MVT::i1) {
24283 unsigned DestReg = 0;
24284 switch (Res.first) {
24286 case X86::AX: DestReg = X86::AL; break;
24287 case X86::DX: DestReg = X86::DL; break;
24288 case X86::CX: DestReg = X86::CL; break;
24289 case X86::BX: DestReg = X86::BL; break;
24292 Res.first = DestReg;
24293 Res.second = &X86::GR8RegClass;
24295 } else if (VT == MVT::i32 || VT == MVT::f32) {
24296 unsigned DestReg = 0;
24297 switch (Res.first) {
24299 case X86::AX: DestReg = X86::EAX; break;
24300 case X86::DX: DestReg = X86::EDX; break;
24301 case X86::CX: DestReg = X86::ECX; break;
24302 case X86::BX: DestReg = X86::EBX; break;
24303 case X86::SI: DestReg = X86::ESI; break;
24304 case X86::DI: DestReg = X86::EDI; break;
24305 case X86::BP: DestReg = X86::EBP; break;
24306 case X86::SP: DestReg = X86::ESP; break;
24309 Res.first = DestReg;
24310 Res.second = &X86::GR32RegClass;
24312 } else if (VT == MVT::i64 || VT == MVT::f64) {
24313 unsigned DestReg = 0;
24314 switch (Res.first) {
24316 case X86::AX: DestReg = X86::RAX; break;
24317 case X86::DX: DestReg = X86::RDX; break;
24318 case X86::CX: DestReg = X86::RCX; break;
24319 case X86::BX: DestReg = X86::RBX; break;
24320 case X86::SI: DestReg = X86::RSI; break;
24321 case X86::DI: DestReg = X86::RDI; break;
24322 case X86::BP: DestReg = X86::RBP; break;
24323 case X86::SP: DestReg = X86::RSP; break;
24326 Res.first = DestReg;
24327 Res.second = &X86::GR64RegClass;
24330 } else if (Res.second == &X86::FR32RegClass ||
24331 Res.second == &X86::FR64RegClass ||
24332 Res.second == &X86::VR128RegClass ||
24333 Res.second == &X86::VR256RegClass ||
24334 Res.second == &X86::FR32XRegClass ||
24335 Res.second == &X86::FR64XRegClass ||
24336 Res.second == &X86::VR128XRegClass ||
24337 Res.second == &X86::VR256XRegClass ||
24338 Res.second == &X86::VR512RegClass) {
24339 // Handle references to XMM physical registers that got mapped into the
24340 // wrong class. This can happen with constraints like {xmm0} where the
24341 // target independent register mapper will just pick the first match it can
24342 // find, ignoring the required type.
24344 if (VT == MVT::f32 || VT == MVT::i32)
24345 Res.second = &X86::FR32RegClass;
24346 else if (VT == MVT::f64 || VT == MVT::i64)
24347 Res.second = &X86::FR64RegClass;
24348 else if (X86::VR128RegClass.hasType(VT))
24349 Res.second = &X86::VR128RegClass;
24350 else if (X86::VR256RegClass.hasType(VT))
24351 Res.second = &X86::VR256RegClass;
24352 else if (X86::VR512RegClass.hasType(VT))
24353 Res.second = &X86::VR512RegClass;
24359 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24361 // Scaling factors are not free at all.
24362 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24363 // will take 2 allocations in the out of order engine instead of 1
24364 // for plain addressing mode, i.e. inst (reg1).
24366 // vaddps (%rsi,%drx), %ymm0, %ymm1
24367 // Requires two allocations (one for the load, one for the computation)
24369 // vaddps (%rsi), %ymm0, %ymm1
24370 // Requires just 1 allocation, i.e., freeing allocations for other operations
24371 // and having less micro operations to execute.
24373 // For some X86 architectures, this is even worse because for instance for
24374 // stores, the complex addressing mode forces the instruction to use the
24375 // "load" ports instead of the dedicated "store" port.
24376 // E.g., on Haswell:
24377 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24378 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24379 if (isLegalAddressingMode(AM, Ty))
24380 // Scale represents reg2 * scale, thus account for 1
24381 // as soon as we use a second register.
24382 return AM.Scale != 0;
24386 bool X86TargetLowering::isTargetFTOL() const {
24387 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();