1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::BLENDI:
3543 case X86ISD::PSHUFB:
3544 case X86ISD::PSHUFD:
3545 case X86ISD::PSHUFHW:
3546 case X86ISD::PSHUFLW:
3548 case X86ISD::PALIGNR:
3549 case X86ISD::MOVLHPS:
3550 case X86ISD::MOVLHPD:
3551 case X86ISD::MOVHLPS:
3552 case X86ISD::MOVLPS:
3553 case X86ISD::MOVLPD:
3554 case X86ISD::MOVSHDUP:
3555 case X86ISD::MOVSLDUP:
3556 case X86ISD::MOVDDUP:
3559 case X86ISD::UNPCKL:
3560 case X86ISD::UNPCKH:
3561 case X86ISD::VPERMILPI:
3562 case X86ISD::VPERM2X128:
3563 case X86ISD::VPERMI:
3568 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3569 SDValue V1, SelectionDAG &DAG) {
3571 default: llvm_unreachable("Unknown x86 shuffle node");
3572 case X86ISD::MOVSHDUP:
3573 case X86ISD::MOVSLDUP:
3574 case X86ISD::MOVDDUP:
3575 return DAG.getNode(Opc, dl, VT, V1);
3579 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3580 SDValue V1, unsigned TargetMask,
3581 SelectionDAG &DAG) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::PSHUFD:
3585 case X86ISD::PSHUFHW:
3586 case X86ISD::PSHUFLW:
3587 case X86ISD::VPERMILPI:
3588 case X86ISD::VPERMI:
3589 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3593 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3594 SDValue V1, SDValue V2, unsigned TargetMask,
3595 SelectionDAG &DAG) {
3597 default: llvm_unreachable("Unknown x86 shuffle node");
3598 case X86ISD::PALIGNR:
3599 case X86ISD::VALIGN:
3601 case X86ISD::VPERM2X128:
3602 return DAG.getNode(Opc, dl, VT, V1, V2,
3603 DAG.getConstant(TargetMask, MVT::i8));
3607 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3608 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3610 default: llvm_unreachable("Unknown x86 shuffle node");
3611 case X86ISD::MOVLHPS:
3612 case X86ISD::MOVLHPD:
3613 case X86ISD::MOVHLPS:
3614 case X86ISD::MOVLPS:
3615 case X86ISD::MOVLPD:
3618 case X86ISD::UNPCKL:
3619 case X86ISD::UNPCKH:
3620 return DAG.getNode(Opc, dl, VT, V1, V2);
3624 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3625 MachineFunction &MF = DAG.getMachineFunction();
3626 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3627 DAG.getSubtarget().getRegisterInfo());
3628 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3629 int ReturnAddrIndex = FuncInfo->getRAIndex();
3631 if (ReturnAddrIndex == 0) {
3632 // Set up a frame object for the return address.
3633 unsigned SlotSize = RegInfo->getSlotSize();
3634 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3637 FuncInfo->setRAIndex(ReturnAddrIndex);
3640 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3643 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3644 bool hasSymbolicDisplacement) {
3645 // Offset should fit into 32 bit immediate field.
3646 if (!isInt<32>(Offset))
3649 // If we don't have a symbolic displacement - we don't have any extra
3651 if (!hasSymbolicDisplacement)
3654 // FIXME: Some tweaks might be needed for medium code model.
3655 if (M != CodeModel::Small && M != CodeModel::Kernel)
3658 // For small code model we assume that latest object is 16MB before end of 31
3659 // bits boundary. We may also accept pretty large negative constants knowing
3660 // that all objects are in the positive half of address space.
3661 if (M == CodeModel::Small && Offset < 16*1024*1024)
3664 // For kernel code model we know that all object resist in the negative half
3665 // of 32bits address space. We may not accept negative offsets, since they may
3666 // be just off and we may accept pretty large positive ones.
3667 if (M == CodeModel::Kernel && Offset > 0)
3673 /// isCalleePop - Determines whether the callee is required to pop its
3674 /// own arguments. Callee pop is necessary to support tail calls.
3675 bool X86::isCalleePop(CallingConv::ID CallingConv,
3676 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3677 switch (CallingConv) {
3680 case CallingConv::X86_StdCall:
3681 case CallingConv::X86_FastCall:
3682 case CallingConv::X86_ThisCall:
3684 case CallingConv::Fast:
3685 case CallingConv::GHC:
3686 case CallingConv::HiPE:
3693 /// \brief Return true if the condition is an unsigned comparison operation.
3694 static bool isX86CCUnsigned(unsigned X86CC) {
3696 default: llvm_unreachable("Invalid integer condition!");
3697 case X86::COND_E: return true;
3698 case X86::COND_G: return false;
3699 case X86::COND_GE: return false;
3700 case X86::COND_L: return false;
3701 case X86::COND_LE: return false;
3702 case X86::COND_NE: return true;
3703 case X86::COND_B: return true;
3704 case X86::COND_A: return true;
3705 case X86::COND_BE: return true;
3706 case X86::COND_AE: return true;
3708 llvm_unreachable("covered switch fell through?!");
3711 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3712 /// specific condition code, returning the condition code and the LHS/RHS of the
3713 /// comparison to make.
3714 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3715 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3718 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3719 // X > -1 -> X == 0, jump !sign.
3720 RHS = DAG.getConstant(0, RHS.getValueType());
3721 return X86::COND_NS;
3723 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3724 // X < 0 -> X == 0, jump on sign.
3727 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3729 RHS = DAG.getConstant(0, RHS.getValueType());
3730 return X86::COND_LE;
3734 switch (SetCCOpcode) {
3735 default: llvm_unreachable("Invalid integer condition!");
3736 case ISD::SETEQ: return X86::COND_E;
3737 case ISD::SETGT: return X86::COND_G;
3738 case ISD::SETGE: return X86::COND_GE;
3739 case ISD::SETLT: return X86::COND_L;
3740 case ISD::SETLE: return X86::COND_LE;
3741 case ISD::SETNE: return X86::COND_NE;
3742 case ISD::SETULT: return X86::COND_B;
3743 case ISD::SETUGT: return X86::COND_A;
3744 case ISD::SETULE: return X86::COND_BE;
3745 case ISD::SETUGE: return X86::COND_AE;
3749 // First determine if it is required or is profitable to flip the operands.
3751 // If LHS is a foldable load, but RHS is not, flip the condition.
3752 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3753 !ISD::isNON_EXTLoad(RHS.getNode())) {
3754 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3755 std::swap(LHS, RHS);
3758 switch (SetCCOpcode) {
3764 std::swap(LHS, RHS);
3768 // On a floating point condition, the flags are set as follows:
3770 // 0 | 0 | 0 | X > Y
3771 // 0 | 0 | 1 | X < Y
3772 // 1 | 0 | 0 | X == Y
3773 // 1 | 1 | 1 | unordered
3774 switch (SetCCOpcode) {
3775 default: llvm_unreachable("Condcode should be pre-legalized away");
3777 case ISD::SETEQ: return X86::COND_E;
3778 case ISD::SETOLT: // flipped
3780 case ISD::SETGT: return X86::COND_A;
3781 case ISD::SETOLE: // flipped
3783 case ISD::SETGE: return X86::COND_AE;
3784 case ISD::SETUGT: // flipped
3786 case ISD::SETLT: return X86::COND_B;
3787 case ISD::SETUGE: // flipped
3789 case ISD::SETLE: return X86::COND_BE;
3791 case ISD::SETNE: return X86::COND_NE;
3792 case ISD::SETUO: return X86::COND_P;
3793 case ISD::SETO: return X86::COND_NP;
3795 case ISD::SETUNE: return X86::COND_INVALID;
3799 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3800 /// code. Current x86 isa includes the following FP cmov instructions:
3801 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3802 static bool hasFPCMov(unsigned X86CC) {
3818 /// isFPImmLegal - Returns true if the target can instruction select the
3819 /// specified FP immediate natively. If false, the legalizer will
3820 /// materialize the FP immediate as a load from a constant pool.
3821 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3822 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3823 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3829 /// \brief Returns true if it is beneficial to convert a load of a constant
3830 /// to just the constant itself.
3831 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3833 assert(Ty->isIntegerTy());
3835 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3836 if (BitSize == 0 || BitSize > 64)
3841 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3842 /// the specified range (L, H].
3843 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3844 return (Val < 0) || (Val >= Low && Val < Hi);
3847 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3848 /// specified value.
3849 static bool isUndefOrEqual(int Val, int CmpVal) {
3850 return (Val < 0 || Val == CmpVal);
3853 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3854 /// from position Pos and ending in Pos+Size, falls within the specified
3855 /// sequential range (L, L+Pos]. or is undef.
3856 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3857 unsigned Pos, unsigned Size, int Low) {
3858 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3859 if (!isUndefOrEqual(Mask[i], Low))
3864 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3865 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3866 /// the second operand.
3867 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3868 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3869 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3870 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3871 return (Mask[0] < 2 && Mask[1] < 2);
3875 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3876 /// is suitable for input to PSHUFHW.
3877 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3878 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3881 // Lower quadword copied in order or undef.
3882 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3885 // Upper quadword shuffled.
3886 for (unsigned i = 4; i != 8; ++i)
3887 if (!isUndefOrInRange(Mask[i], 4, 8))
3890 if (VT == MVT::v16i16) {
3891 // Lower quadword copied in order or undef.
3892 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3895 // Upper quadword shuffled.
3896 for (unsigned i = 12; i != 16; ++i)
3897 if (!isUndefOrInRange(Mask[i], 12, 16))
3904 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3905 /// is suitable for input to PSHUFLW.
3906 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3907 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3910 // Upper quadword copied in order.
3911 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3914 // Lower quadword shuffled.
3915 for (unsigned i = 0; i != 4; ++i)
3916 if (!isUndefOrInRange(Mask[i], 0, 4))
3919 if (VT == MVT::v16i16) {
3920 // Upper quadword copied in order.
3921 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3924 // Lower quadword shuffled.
3925 for (unsigned i = 8; i != 12; ++i)
3926 if (!isUndefOrInRange(Mask[i], 8, 12))
3933 /// \brief Return true if the mask specifies a shuffle of elements that is
3934 /// suitable for input to intralane (palignr) or interlane (valign) vector
3936 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3937 unsigned NumElts = VT.getVectorNumElements();
3938 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3939 unsigned NumLaneElts = NumElts/NumLanes;
3941 // Do not handle 64-bit element shuffles with palignr.
3942 if (NumLaneElts == 2)
3945 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3947 for (i = 0; i != NumLaneElts; ++i) {
3952 // Lane is all undef, go to next lane
3953 if (i == NumLaneElts)
3956 int Start = Mask[i+l];
3958 // Make sure its in this lane in one of the sources
3959 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3960 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3963 // If not lane 0, then we must match lane 0
3964 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3967 // Correct second source to be contiguous with first source
3968 if (Start >= (int)NumElts)
3969 Start -= NumElts - NumLaneElts;
3971 // Make sure we're shifting in the right direction.
3972 if (Start <= (int)(i+l))
3977 // Check the rest of the elements to see if they are consecutive.
3978 for (++i; i != NumLaneElts; ++i) {
3979 int Idx = Mask[i+l];
3981 // Make sure its in this lane
3982 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3983 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3986 // If not lane 0, then we must match lane 0
3987 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3990 if (Idx >= (int)NumElts)
3991 Idx -= NumElts - NumLaneElts;
3993 if (!isUndefOrEqual(Idx, Start+i))
4002 /// \brief Return true if the node specifies a shuffle of elements that is
4003 /// suitable for input to PALIGNR.
4004 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4005 const X86Subtarget *Subtarget) {
4006 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4007 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4008 VT.is512BitVector())
4009 // FIXME: Add AVX512BW.
4012 return isAlignrMask(Mask, VT, false);
4015 /// \brief Return true if the node specifies a shuffle of elements that is
4016 /// suitable for input to VALIGN.
4017 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4018 const X86Subtarget *Subtarget) {
4019 // FIXME: Add AVX512VL.
4020 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4022 return isAlignrMask(Mask, VT, true);
4025 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4026 /// the two vector operands have swapped position.
4027 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4028 unsigned NumElems) {
4029 for (unsigned i = 0; i != NumElems; ++i) {
4033 else if (idx < (int)NumElems)
4034 Mask[i] = idx + NumElems;
4036 Mask[i] = idx - NumElems;
4040 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4041 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4042 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4043 /// reverse of what x86 shuffles want.
4044 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4046 unsigned NumElems = VT.getVectorNumElements();
4047 unsigned NumLanes = VT.getSizeInBits()/128;
4048 unsigned NumLaneElems = NumElems/NumLanes;
4050 if (NumLaneElems != 2 && NumLaneElems != 4)
4053 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4054 bool symetricMaskRequired =
4055 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4057 // VSHUFPSY divides the resulting vector into 4 chunks.
4058 // The sources are also splitted into 4 chunks, and each destination
4059 // chunk must come from a different source chunk.
4061 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4062 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4064 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4065 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4067 // VSHUFPDY divides the resulting vector into 4 chunks.
4068 // The sources are also splitted into 4 chunks, and each destination
4069 // chunk must come from a different source chunk.
4071 // SRC1 => X3 X2 X1 X0
4072 // SRC2 => Y3 Y2 Y1 Y0
4074 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4076 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4077 unsigned HalfLaneElems = NumLaneElems/2;
4078 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4079 for (unsigned i = 0; i != NumLaneElems; ++i) {
4080 int Idx = Mask[i+l];
4081 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4082 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4084 // For VSHUFPSY, the mask of the second half must be the same as the
4085 // first but with the appropriate offsets. This works in the same way as
4086 // VPERMILPS works with masks.
4087 if (!symetricMaskRequired || Idx < 0)
4089 if (MaskVal[i] < 0) {
4090 MaskVal[i] = Idx - l;
4093 if ((signed)(Idx - l) != MaskVal[i])
4101 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4102 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4103 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4104 if (!VT.is128BitVector())
4107 unsigned NumElems = VT.getVectorNumElements();
4112 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4113 return isUndefOrEqual(Mask[0], 6) &&
4114 isUndefOrEqual(Mask[1], 7) &&
4115 isUndefOrEqual(Mask[2], 2) &&
4116 isUndefOrEqual(Mask[3], 3);
4119 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4120 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4122 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4123 if (!VT.is128BitVector())
4126 unsigned NumElems = VT.getVectorNumElements();
4131 return isUndefOrEqual(Mask[0], 2) &&
4132 isUndefOrEqual(Mask[1], 3) &&
4133 isUndefOrEqual(Mask[2], 2) &&
4134 isUndefOrEqual(Mask[3], 3);
4137 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4138 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4139 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4140 if (!VT.is128BitVector())
4143 unsigned NumElems = VT.getVectorNumElements();
4145 if (NumElems != 2 && NumElems != 4)
4148 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4149 if (!isUndefOrEqual(Mask[i], i + NumElems))
4152 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4153 if (!isUndefOrEqual(Mask[i], i))
4159 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4160 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4161 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4162 if (!VT.is128BitVector())
4165 unsigned NumElems = VT.getVectorNumElements();
4167 if (NumElems != 2 && NumElems != 4)
4170 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i))
4174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4181 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4182 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4183 /// i. e: If all but one element come from the same vector.
4184 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4185 // TODO: Deal with AVX's VINSERTPS
4186 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4189 unsigned CorrectPosV1 = 0;
4190 unsigned CorrectPosV2 = 0;
4191 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4192 if (Mask[i] == -1) {
4200 else if (Mask[i] == i + 4)
4204 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4205 // We have 3 elements (undefs count as elements from any vector) from one
4206 // vector, and one from another.
4213 // Some special combinations that can be optimized.
4216 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4217 SelectionDAG &DAG) {
4218 MVT VT = SVOp->getSimpleValueType(0);
4221 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4224 ArrayRef<int> Mask = SVOp->getMask();
4226 // These are the special masks that may be optimized.
4227 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4228 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4229 bool MatchEvenMask = true;
4230 bool MatchOddMask = true;
4231 for (int i=0; i<8; ++i) {
4232 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4233 MatchEvenMask = false;
4234 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4235 MatchOddMask = false;
4238 if (!MatchEvenMask && !MatchOddMask)
4241 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4243 SDValue Op0 = SVOp->getOperand(0);
4244 SDValue Op1 = SVOp->getOperand(1);
4246 if (MatchEvenMask) {
4247 // Shift the second operand right to 32 bits.
4248 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4249 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4251 // Shift the first operand left to 32 bits.
4252 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4253 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4255 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4256 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4259 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4260 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4261 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4262 bool HasInt256, bool V2IsSplat = false) {
4264 assert(VT.getSizeInBits() >= 128 &&
4265 "Unsupported vector type for unpckl");
4267 unsigned NumElts = VT.getVectorNumElements();
4268 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4269 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4272 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4273 "Unsupported vector type for unpckh");
4275 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned NumLaneElts = NumElts/NumLanes;
4279 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4280 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4281 int BitI = Mask[l+i];
4282 int BitI1 = Mask[l+i+1];
4283 if (!isUndefOrEqual(BitI, j))
4286 if (!isUndefOrEqual(BitI1, NumElts))
4289 if (!isUndefOrEqual(BitI1, j + NumElts))
4298 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4299 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4300 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4301 bool HasInt256, bool V2IsSplat = false) {
4302 assert(VT.getSizeInBits() >= 128 &&
4303 "Unsupported vector type for unpckh");
4305 unsigned NumElts = VT.getVectorNumElements();
4306 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4307 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4310 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4311 "Unsupported vector type for unpckh");
4313 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4314 unsigned NumLanes = VT.getSizeInBits()/128;
4315 unsigned NumLaneElts = NumElts/NumLanes;
4317 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4318 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4319 int BitI = Mask[l+i];
4320 int BitI1 = Mask[l+i+1];
4321 if (!isUndefOrEqual(BitI, j))
4324 if (isUndefOrEqual(BitI1, NumElts))
4327 if (!isUndefOrEqual(BitI1, j+NumElts))
4335 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4336 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4338 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4339 unsigned NumElts = VT.getVectorNumElements();
4340 bool Is256BitVec = VT.is256BitVector();
4342 if (VT.is512BitVector())
4344 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4345 "Unsupported vector type for unpckh");
4347 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4348 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4351 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4352 // FIXME: Need a better way to get rid of this, there's no latency difference
4353 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4354 // the former later. We should also remove the "_undef" special mask.
4355 if (NumElts == 4 && Is256BitVec)
4358 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4359 // independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4368 if (!isUndefOrEqual(BitI, j))
4370 if (!isUndefOrEqual(BitI1, j))
4378 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4379 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4381 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4382 unsigned NumElts = VT.getVectorNumElements();
4384 if (VT.is512BitVector())
4387 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4388 "Unsupported vector type for unpckh");
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4394 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4395 // independently on 128-bit lanes.
4396 unsigned NumLanes = VT.getSizeInBits()/128;
4397 unsigned NumLaneElts = NumElts/NumLanes;
4399 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4400 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4401 int BitI = Mask[l+i];
4402 int BitI1 = Mask[l+i+1];
4403 if (!isUndefOrEqual(BitI, j))
4405 if (!isUndefOrEqual(BitI1, j))
4412 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4413 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4414 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4415 if (!VT.is512BitVector())
4418 unsigned NumElts = VT.getVectorNumElements();
4419 unsigned HalfSize = NumElts/2;
4420 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4421 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4435 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4436 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4437 /// MOVSD, and MOVD, i.e. setting the lowest element.
4438 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4439 if (VT.getVectorElementType().getSizeInBits() < 32)
4441 if (!VT.is128BitVector())
4444 unsigned NumElts = VT.getVectorNumElements();
4446 if (!isUndefOrEqual(Mask[0], NumElts))
4449 for (unsigned i = 1; i != NumElts; ++i)
4450 if (!isUndefOrEqual(Mask[i], i))
4456 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4457 /// as permutations between 128-bit chunks or halves. As an example: this
4459 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4460 /// The first half comes from the second half of V1 and the second half from the
4461 /// the second half of V2.
4462 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4463 if (!HasFp256 || !VT.is256BitVector())
4466 // The shuffle result is divided into half A and half B. In total the two
4467 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4468 // B must come from C, D, E or F.
4469 unsigned HalfSize = VT.getVectorNumElements()/2;
4470 bool MatchA = false, MatchB = false;
4472 // Check if A comes from one of C, D, E, F.
4473 for (unsigned Half = 0; Half != 4; ++Half) {
4474 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4480 // Check if B comes from one of C, D, E, F.
4481 for (unsigned Half = 0; Half != 4; ++Half) {
4482 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4488 return MatchA && MatchB;
4491 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4493 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4494 MVT VT = SVOp->getSimpleValueType(0);
4496 unsigned HalfSize = VT.getVectorNumElements()/2;
4498 unsigned FstHalf = 0, SndHalf = 0;
4499 for (unsigned i = 0; i < HalfSize; ++i) {
4500 if (SVOp->getMaskElt(i) > 0) {
4501 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4505 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4512 return (FstHalf | (SndHalf << 4));
4515 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4516 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4517 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4521 unsigned NumElts = VT.getVectorNumElements();
4523 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4524 for (unsigned i = 0; i != NumElts; ++i) {
4527 Imm8 |= Mask[i] << (i*2);
4532 unsigned LaneSize = 4;
4533 SmallVector<int, 4> MaskVal(LaneSize, -1);
4535 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4536 for (unsigned i = 0; i != LaneSize; ++i) {
4537 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4541 if (MaskVal[i] < 0) {
4542 MaskVal[i] = Mask[i+l] - l;
4543 Imm8 |= MaskVal[i] << (i*2);
4546 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4553 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4554 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4555 /// Note that VPERMIL mask matching is different depending whether theunderlying
4556 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4557 /// to the same elements of the low, but to the higher half of the source.
4558 /// In VPERMILPD the two lanes could be shuffled independently of each other
4559 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4560 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4561 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4562 if (VT.getSizeInBits() < 256 || EltSize < 32)
4564 bool symetricMaskRequired = (EltSize == 32);
4565 unsigned NumElts = VT.getVectorNumElements();
4567 unsigned NumLanes = VT.getSizeInBits()/128;
4568 unsigned LaneSize = NumElts/NumLanes;
4569 // 2 or 4 elements in one lane
4571 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4572 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4573 for (unsigned i = 0; i != LaneSize; ++i) {
4574 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4576 if (symetricMaskRequired) {
4577 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4578 ExpectedMaskVal[i] = Mask[i+l] - l;
4581 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4589 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4590 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4591 /// element of vector 2 and the other elements to come from vector 1 in order.
4592 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4593 bool V2IsSplat = false, bool V2IsUndef = false) {
4594 if (!VT.is128BitVector())
4597 unsigned NumOps = VT.getVectorNumElements();
4598 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4601 if (!isUndefOrEqual(Mask[0], 0))
4604 for (unsigned i = 1; i != NumOps; ++i)
4605 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4606 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4607 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4613 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4614 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4615 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4616 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4617 const X86Subtarget *Subtarget) {
4618 if (!Subtarget->hasSSE3())
4621 unsigned NumElems = VT.getVectorNumElements();
4623 if ((VT.is128BitVector() && NumElems != 4) ||
4624 (VT.is256BitVector() && NumElems != 8) ||
4625 (VT.is512BitVector() && NumElems != 16))
4628 // "i+1" is the value the indexed mask element must have
4629 for (unsigned i = 0; i != NumElems; i += 2)
4630 if (!isUndefOrEqual(Mask[i], i+1) ||
4631 !isUndefOrEqual(Mask[i+1], i+1))
4637 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4639 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4640 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4641 const X86Subtarget *Subtarget) {
4642 if (!Subtarget->hasSSE3())
4645 unsigned NumElems = VT.getVectorNumElements();
4647 if ((VT.is128BitVector() && NumElems != 4) ||
4648 (VT.is256BitVector() && NumElems != 8) ||
4649 (VT.is512BitVector() && NumElems != 16))
4652 // "i" is the value the indexed mask element must have
4653 for (unsigned i = 0; i != NumElems; i += 2)
4654 if (!isUndefOrEqual(Mask[i], i) ||
4655 !isUndefOrEqual(Mask[i+1], i))
4661 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4662 /// specifies a shuffle of elements that is suitable for input to 256-bit
4663 /// version of MOVDDUP.
4664 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4665 if (!HasFp256 || !VT.is256BitVector())
4668 unsigned NumElts = VT.getVectorNumElements();
4672 for (unsigned i = 0; i != NumElts/2; ++i)
4673 if (!isUndefOrEqual(Mask[i], 0))
4675 for (unsigned i = NumElts/2; i != NumElts; ++i)
4676 if (!isUndefOrEqual(Mask[i], NumElts/2))
4681 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4682 /// specifies a shuffle of elements that is suitable for input to 128-bit
4683 /// version of MOVDDUP.
4684 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4685 if (!VT.is128BitVector())
4688 unsigned e = VT.getVectorNumElements() / 2;
4689 for (unsigned i = 0; i != e; ++i)
4690 if (!isUndefOrEqual(Mask[i], i))
4692 for (unsigned i = 0; i != e; ++i)
4693 if (!isUndefOrEqual(Mask[e+i], i))
4698 /// isVEXTRACTIndex - Return true if the specified
4699 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4700 /// suitable for instruction that extract 128 or 256 bit vectors
4701 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4702 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4703 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4706 // The index should be aligned on a vecWidth-bit boundary.
4708 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4710 MVT VT = N->getSimpleValueType(0);
4711 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4712 bool Result = (Index * ElSize) % vecWidth == 0;
4717 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4718 /// operand specifies a subvector insert that is suitable for input to
4719 /// insertion of 128 or 256-bit subvectors
4720 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4721 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4722 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4724 // The index should be aligned on a vecWidth-bit boundary.
4726 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4728 MVT VT = N->getSimpleValueType(0);
4729 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4730 bool Result = (Index * ElSize) % vecWidth == 0;
4735 bool X86::isVINSERT128Index(SDNode *N) {
4736 return isVINSERTIndex(N, 128);
4739 bool X86::isVINSERT256Index(SDNode *N) {
4740 return isVINSERTIndex(N, 256);
4743 bool X86::isVEXTRACT128Index(SDNode *N) {
4744 return isVEXTRACTIndex(N, 128);
4747 bool X86::isVEXTRACT256Index(SDNode *N) {
4748 return isVEXTRACTIndex(N, 256);
4751 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4752 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4753 /// Handles 128-bit and 256-bit.
4754 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4755 MVT VT = N->getSimpleValueType(0);
4757 assert((VT.getSizeInBits() >= 128) &&
4758 "Unsupported vector type for PSHUF/SHUFP");
4760 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4761 // independently on 128-bit lanes.
4762 unsigned NumElts = VT.getVectorNumElements();
4763 unsigned NumLanes = VT.getSizeInBits()/128;
4764 unsigned NumLaneElts = NumElts/NumLanes;
4766 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4767 "Only supports 2, 4 or 8 elements per lane");
4769 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4771 for (unsigned i = 0; i != NumElts; ++i) {
4772 int Elt = N->getMaskElt(i);
4773 if (Elt < 0) continue;
4774 Elt &= NumLaneElts - 1;
4775 unsigned ShAmt = (i << Shift) % 8;
4776 Mask |= Elt << ShAmt;
4782 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4783 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4784 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4785 MVT VT = N->getSimpleValueType(0);
4787 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4788 "Unsupported vector type for PSHUFHW");
4790 unsigned NumElts = VT.getVectorNumElements();
4793 for (unsigned l = 0; l != NumElts; l += 8) {
4794 // 8 nodes per lane, but we only care about the last 4.
4795 for (unsigned i = 0; i < 4; ++i) {
4796 int Elt = N->getMaskElt(l+i+4);
4797 if (Elt < 0) continue;
4798 Elt &= 0x3; // only 2-bits.
4799 Mask |= Elt << (i * 2);
4806 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4807 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4808 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4809 MVT VT = N->getSimpleValueType(0);
4811 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4812 "Unsupported vector type for PSHUFHW");
4814 unsigned NumElts = VT.getVectorNumElements();
4817 for (unsigned l = 0; l != NumElts; l += 8) {
4818 // 8 nodes per lane, but we only care about the first 4.
4819 for (unsigned i = 0; i < 4; ++i) {
4820 int Elt = N->getMaskElt(l+i);
4821 if (Elt < 0) continue;
4822 Elt &= 0x3; // only 2-bits
4823 Mask |= Elt << (i * 2);
4830 /// \brief Return the appropriate immediate to shuffle the specified
4831 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4832 /// VALIGN (if Interlane is true) instructions.
4833 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4835 MVT VT = SVOp->getSimpleValueType(0);
4836 unsigned EltSize = InterLane ? 1 :
4837 VT.getVectorElementType().getSizeInBits() >> 3;
4839 unsigned NumElts = VT.getVectorNumElements();
4840 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4841 unsigned NumLaneElts = NumElts/NumLanes;
4845 for (i = 0; i != NumElts; ++i) {
4846 Val = SVOp->getMaskElt(i);
4850 if (Val >= (int)NumElts)
4851 Val -= NumElts - NumLaneElts;
4853 assert(Val - i > 0 && "PALIGNR imm should be positive");
4854 return (Val - i) * EltSize;
4857 /// \brief Return the appropriate immediate to shuffle the specified
4858 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4859 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4860 return getShuffleAlignrImmediate(SVOp, false);
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4865 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, true);
4870 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4871 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4872 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4873 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4876 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4878 MVT VecVT = N->getOperand(0).getSimpleValueType();
4879 MVT ElVT = VecVT.getVectorElementType();
4881 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4882 return Index / NumElemsPerChunk;
4885 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4886 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4887 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4888 llvm_unreachable("Illegal insert subvector for VINSERT");
4891 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4893 MVT VecVT = N->getSimpleValueType(0);
4894 MVT ElVT = VecVT.getVectorElementType();
4896 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4897 return Index / NumElemsPerChunk;
4900 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4901 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4902 /// and VINSERTI128 instructions.
4903 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4904 return getExtractVEXTRACTImmediate(N, 128);
4907 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4909 /// and VINSERTI64x4 instructions.
4910 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 256);
4914 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4915 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4918 return getInsertVINSERTImmediate(N, 128);
4921 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 256);
4928 /// isZero - Returns true if Elt is a constant integer zero
4929 static bool isZero(SDValue V) {
4930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4931 return C && C->isNullValue();
4934 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4936 bool X86::isZeroNode(SDValue Elt) {
4939 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4940 return CFP->getValueAPF().isPosZero();
4944 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4945 /// match movhlps. The lower half elements should come from upper half of
4946 /// V1 (and in order), and the upper half elements should come from the upper
4947 /// half of V2 (and in order).
4948 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4949 if (!VT.is128BitVector())
4951 if (VT.getVectorNumElements() != 4)
4953 for (unsigned i = 0, e = 2; i != e; ++i)
4954 if (!isUndefOrEqual(Mask[i], i+2))
4956 for (unsigned i = 2; i != 4; ++i)
4957 if (!isUndefOrEqual(Mask[i], i+4))
4962 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4963 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4965 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4966 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4968 N = N->getOperand(0).getNode();
4969 if (!ISD::isNON_EXTLoad(N))
4972 *LD = cast<LoadSDNode>(N);
4976 // Test whether the given value is a vector value which will be legalized
4978 static bool WillBeConstantPoolLoad(SDNode *N) {
4979 if (N->getOpcode() != ISD::BUILD_VECTOR)
4982 // Check for any non-constant elements.
4983 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4984 switch (N->getOperand(i).getNode()->getOpcode()) {
4986 case ISD::ConstantFP:
4993 // Vectors of all-zeros and all-ones are materialized with special
4994 // instructions rather than being loaded.
4995 return !ISD::isBuildVectorAllZeros(N) &&
4996 !ISD::isBuildVectorAllOnes(N);
4999 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5000 /// match movlp{s|d}. The lower half elements should come from lower half of
5001 /// V1 (and in order), and the upper half elements should come from the upper
5002 /// half of V2 (and in order). And since V1 will become the source of the
5003 /// MOVLP, it must be either a vector load or a scalar load to vector.
5004 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5005 ArrayRef<int> Mask, MVT VT) {
5006 if (!VT.is128BitVector())
5009 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5011 // Is V2 is a vector load, don't do this transformation. We will try to use
5012 // load folding shufps op.
5013 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5016 unsigned NumElems = VT.getVectorNumElements();
5018 if (NumElems != 2 && NumElems != 4)
5020 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5021 if (!isUndefOrEqual(Mask[i], i))
5023 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5024 if (!isUndefOrEqual(Mask[i], i+NumElems))
5029 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5030 /// to an zero vector.
5031 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5032 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5033 SDValue V1 = N->getOperand(0);
5034 SDValue V2 = N->getOperand(1);
5035 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5036 for (unsigned i = 0; i != NumElems; ++i) {
5037 int Idx = N->getMaskElt(i);
5038 if (Idx >= (int)NumElems) {
5039 unsigned Opc = V2.getOpcode();
5040 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5042 if (Opc != ISD::BUILD_VECTOR ||
5043 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5045 } else if (Idx >= 0) {
5046 unsigned Opc = V1.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V1.getOperand(Idx)))
5057 /// getZeroVector - Returns a vector of specified type with all zero elements.
5059 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5060 SelectionDAG &DAG, SDLoc dl) {
5061 assert(VT.isVector() && "Expected a vector type");
5063 // Always build SSE zero vectors as <4 x i32> bitcasted
5064 // to their dest type. This ensures they get CSE'd.
5066 if (VT.is128BitVector()) { // SSE
5067 if (Subtarget->hasSSE2()) { // SSE2
5068 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5071 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5074 } else if (VT.is256BitVector()) { // AVX
5075 if (Subtarget->hasInt256()) { // AVX2
5076 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5077 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5080 // 256-bit logic and arithmetic instructions in AVX are all
5081 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5082 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5086 } else if (VT.is512BitVector()) { // AVX-512
5087 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5088 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5089 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5091 } else if (VT.getScalarType() == MVT::i1) {
5092 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5093 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5094 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5095 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5097 llvm_unreachable("Unexpected vector type");
5099 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5102 /// getOnesVector - Returns a vector of specified type with all bits set.
5103 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5104 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5105 /// Then bitcast to their original type, ensuring they get CSE'd.
5106 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5108 assert(VT.isVector() && "Expected a vector type");
5110 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5112 if (VT.is256BitVector()) {
5113 if (HasInt256) { // AVX2
5114 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5115 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5117 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5118 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5120 } else if (VT.is128BitVector()) {
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5123 llvm_unreachable("Unexpected vector type");
5125 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5128 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5129 /// that point to V2 points to its first element.
5130 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5131 for (unsigned i = 0; i != NumElems; ++i) {
5132 if (Mask[i] > (int)NumElems) {
5138 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5139 /// operation of specified width.
5140 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5142 unsigned NumElems = VT.getVectorNumElements();
5143 SmallVector<int, 8> Mask;
5144 Mask.push_back(NumElems);
5145 for (unsigned i = 1; i != NumElems; ++i)
5147 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5150 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5151 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5153 unsigned NumElems = VT.getVectorNumElements();
5154 SmallVector<int, 8> Mask;
5155 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5157 Mask.push_back(i + NumElems);
5159 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5162 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5163 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5165 unsigned NumElems = VT.getVectorNumElements();
5166 SmallVector<int, 8> Mask;
5167 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5168 Mask.push_back(i + Half);
5169 Mask.push_back(i + NumElems + Half);
5171 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5174 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5175 // a generic shuffle instruction because the target has no such instructions.
5176 // Generate shuffles which repeat i16 and i8 several times until they can be
5177 // represented by v4f32 and then be manipulated by target suported shuffles.
5178 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5179 MVT VT = V.getSimpleValueType();
5180 int NumElems = VT.getVectorNumElements();
5183 while (NumElems > 4) {
5184 if (EltNo < NumElems/2) {
5185 V = getUnpackl(DAG, dl, VT, V, V);
5187 V = getUnpackh(DAG, dl, VT, V, V);
5188 EltNo -= NumElems/2;
5195 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5196 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5197 MVT VT = V.getSimpleValueType();
5200 if (VT.is128BitVector()) {
5201 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5202 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5203 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5205 } else if (VT.is256BitVector()) {
5206 // To use VPERMILPS to splat scalars, the second half of indicies must
5207 // refer to the higher part, which is a duplication of the lower one,
5208 // because VPERMILPS can only handle in-lane permutations.
5209 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5210 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5212 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5213 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5216 llvm_unreachable("Vector size not supported");
5218 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5221 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5222 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5223 MVT SrcVT = SV->getSimpleValueType(0);
5224 SDValue V1 = SV->getOperand(0);
5227 int EltNo = SV->getSplatIndex();
5228 int NumElems = SrcVT.getVectorNumElements();
5229 bool Is256BitVec = SrcVT.is256BitVector();
5231 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5232 "Unknown how to promote splat for type");
5234 // Extract the 128-bit part containing the splat element and update
5235 // the splat element index when it refers to the higher register.
5237 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5238 if (EltNo >= NumElems/2)
5239 EltNo -= NumElems/2;
5242 // All i16 and i8 vector types can't be used directly by a generic shuffle
5243 // instruction because the target has no such instruction. Generate shuffles
5244 // which repeat i16 and i8 several times until they fit in i32, and then can
5245 // be manipulated by target suported shuffles.
5246 MVT EltVT = SrcVT.getVectorElementType();
5247 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5248 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5250 // Recreate the 256-bit vector and place the same 128-bit vector
5251 // into the low and high part. This is necessary because we want
5252 // to use VPERM* to shuffle the vectors
5254 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5257 return getLegalSplat(DAG, V1, EltNo);
5260 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5261 /// vector of zero or undef vector. This produces a shuffle where the low
5262 /// element of V2 is swizzled into the zero/undef vector, landing at element
5263 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5264 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5266 const X86Subtarget *Subtarget,
5267 SelectionDAG &DAG) {
5268 MVT VT = V2.getSimpleValueType();
5270 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5271 unsigned NumElems = VT.getVectorNumElements();
5272 SmallVector<int, 16> MaskVec;
5273 for (unsigned i = 0; i != NumElems; ++i)
5274 // If this is the insertion idx, put the low elt of V2 here.
5275 MaskVec.push_back(i == Idx ? NumElems : i);
5276 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5279 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5280 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5281 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5282 /// shuffles which use a single input multiple times, and in those cases it will
5283 /// adjust the mask to only have indices within that single input.
5284 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5285 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5286 unsigned NumElems = VT.getVectorNumElements();
5290 bool IsFakeUnary = false;
5291 switch(N->getOpcode()) {
5292 case X86ISD::BLENDI:
5293 ImmN = N->getOperand(N->getNumOperands()-1);
5294 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5297 ImmN = N->getOperand(N->getNumOperands()-1);
5298 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5299 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5301 case X86ISD::UNPCKH:
5302 DecodeUNPCKHMask(VT, Mask);
5303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5305 case X86ISD::UNPCKL:
5306 DecodeUNPCKLMask(VT, Mask);
5307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5309 case X86ISD::MOVHLPS:
5310 DecodeMOVHLPSMask(NumElems, Mask);
5311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5313 case X86ISD::MOVLHPS:
5314 DecodeMOVLHPSMask(NumElems, Mask);
5315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 case X86ISD::PALIGNR:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5321 case X86ISD::PSHUFD:
5322 case X86ISD::VPERMILPI:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFHW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFLW:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 case X86ISD::PSHUFB: {
5339 SDValue MaskNode = N->getOperand(1);
5340 while (MaskNode->getOpcode() == ISD::BITCAST)
5341 MaskNode = MaskNode->getOperand(0);
5343 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5344 // If we have a build-vector, then things are easy.
5345 EVT VT = MaskNode.getValueType();
5346 assert(VT.isVector() &&
5347 "Can't produce a non-vector with a build_vector!");
5348 if (!VT.isInteger())
5351 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5353 SmallVector<uint64_t, 32> RawMask;
5354 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5355 SDValue Op = MaskNode->getOperand(i);
5356 if (Op->getOpcode() == ISD::UNDEF) {
5357 RawMask.push_back((uint64_t)SM_SentinelUndef);
5360 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5363 APInt MaskElement = CN->getAPIntValue();
5365 // We now have to decode the element which could be any integer size and
5366 // extract each byte of it.
5367 for (int j = 0; j < NumBytesPerElement; ++j) {
5368 // Note that this is x86 and so always little endian: the low byte is
5369 // the first byte of the mask.
5370 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5371 MaskElement = MaskElement.lshr(8);
5374 DecodePSHUFBMask(RawMask, Mask);
5378 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5382 SDValue Ptr = MaskLoad->getBasePtr();
5383 if (Ptr->getOpcode() == X86ISD::Wrapper)
5384 Ptr = Ptr->getOperand(0);
5386 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5387 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5390 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5391 // FIXME: Support AVX-512 here.
5392 Type *Ty = C->getType();
5393 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5394 Ty->getVectorNumElements() != 32))
5397 DecodePSHUFBMask(C, Mask);
5403 case X86ISD::VPERMI:
5404 ImmN = N->getOperand(N->getNumOperands()-1);
5405 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5409 case X86ISD::MOVSD: {
5410 // The index 0 always comes from the first element of the second source,
5411 // this is why MOVSS and MOVSD are used in the first place. The other
5412 // elements come from the other positions of the first source vector
5413 Mask.push_back(NumElems);
5414 for (unsigned i = 1; i != NumElems; ++i) {
5419 case X86ISD::VPERM2X128:
5420 ImmN = N->getOperand(N->getNumOperands()-1);
5421 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5422 if (Mask.empty()) return false;
5424 case X86ISD::MOVSLDUP:
5425 DecodeMOVSLDUPMask(VT, Mask);
5427 case X86ISD::MOVSHDUP:
5428 DecodeMOVSHDUPMask(VT, Mask);
5430 case X86ISD::MOVDDUP:
5431 case X86ISD::MOVLHPD:
5432 case X86ISD::MOVLPD:
5433 case X86ISD::MOVLPS:
5434 // Not yet implemented
5436 default: llvm_unreachable("unknown target shuffle node");
5439 // If we have a fake unary shuffle, the shuffle mask is spread across two
5440 // inputs that are actually the same node. Re-map the mask to always point
5441 // into the first input.
5444 if (M >= (int)Mask.size())
5450 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5451 /// element of the result of the vector shuffle.
5452 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5455 return SDValue(); // Limit search depth.
5457 SDValue V = SDValue(N, 0);
5458 EVT VT = V.getValueType();
5459 unsigned Opcode = V.getOpcode();
5461 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5462 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5463 int Elt = SV->getMaskElt(Index);
5466 return DAG.getUNDEF(VT.getVectorElementType());
5468 unsigned NumElems = VT.getVectorNumElements();
5469 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5470 : SV->getOperand(1);
5471 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5474 // Recurse into target specific vector shuffles to find scalars.
5475 if (isTargetShuffle(Opcode)) {
5476 MVT ShufVT = V.getSimpleValueType();
5477 unsigned NumElems = ShufVT.getVectorNumElements();
5478 SmallVector<int, 16> ShuffleMask;
5481 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5484 int Elt = ShuffleMask[Index];
5486 return DAG.getUNDEF(ShufVT.getVectorElementType());
5488 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5490 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5494 // Actual nodes that may contain scalar elements
5495 if (Opcode == ISD::BITCAST) {
5496 V = V.getOperand(0);
5497 EVT SrcVT = V.getValueType();
5498 unsigned NumElems = VT.getVectorNumElements();
5500 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5504 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5505 return (Index == 0) ? V.getOperand(0)
5506 : DAG.getUNDEF(VT.getVectorElementType());
5508 if (V.getOpcode() == ISD::BUILD_VECTOR)
5509 return V.getOperand(Index);
5514 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5515 /// shuffle operation which come from a consecutively from a zero. The
5516 /// search can start in two different directions, from left or right.
5517 /// We count undefs as zeros until PreferredNum is reached.
5518 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5519 unsigned NumElems, bool ZerosFromLeft,
5521 unsigned PreferredNum = -1U) {
5522 unsigned NumZeros = 0;
5523 for (unsigned i = 0; i != NumElems; ++i) {
5524 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5525 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5529 if (X86::isZeroNode(Elt))
5531 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5532 NumZeros = std::min(NumZeros + 1, PreferredNum);
5540 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5541 /// correspond consecutively to elements from one of the vector operands,
5542 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5544 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5545 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5546 unsigned NumElems, unsigned &OpNum) {
5547 bool SeenV1 = false;
5548 bool SeenV2 = false;
5550 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5551 int Idx = SVOp->getMaskElt(i);
5552 // Ignore undef indicies
5556 if (Idx < (int)NumElems)
5561 // Only accept consecutive elements from the same vector
5562 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5566 OpNum = SeenV1 ? 0 : 1;
5570 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5571 /// logical left shift of a vector.
5572 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5573 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5575 SVOp->getSimpleValueType(0).getVectorNumElements();
5576 unsigned NumZeros = getNumOfConsecutiveZeros(
5577 SVOp, NumElems, false /* check zeros from right */, DAG,
5578 SVOp->getMaskElt(0));
5584 // Considering the elements in the mask that are not consecutive zeros,
5585 // check if they consecutively come from only one of the source vectors.
5587 // V1 = {X, A, B, C} 0
5589 // vector_shuffle V1, V2 <1, 2, 3, X>
5591 if (!isShuffleMaskConsecutive(SVOp,
5592 0, // Mask Start Index
5593 NumElems-NumZeros, // Mask End Index(exclusive)
5594 NumZeros, // Where to start looking in the src vector
5595 NumElems, // Number of elements in vector
5596 OpSrc)) // Which source operand ?
5601 ShVal = SVOp->getOperand(OpSrc);
5605 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5606 /// logical left shift of a vector.
5607 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5608 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5610 SVOp->getSimpleValueType(0).getVectorNumElements();
5611 unsigned NumZeros = getNumOfConsecutiveZeros(
5612 SVOp, NumElems, true /* check zeros from left */, DAG,
5613 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5619 // Considering the elements in the mask that are not consecutive zeros,
5620 // check if they consecutively come from only one of the source vectors.
5622 // 0 { A, B, X, X } = V2
5624 // vector_shuffle V1, V2 <X, X, 4, 5>
5626 if (!isShuffleMaskConsecutive(SVOp,
5627 NumZeros, // Mask Start Index
5628 NumElems, // Mask End Index(exclusive)
5629 0, // Where to start looking in the src vector
5630 NumElems, // Number of elements in vector
5631 OpSrc)) // Which source operand ?
5636 ShVal = SVOp->getOperand(OpSrc);
5640 /// isVectorShift - Returns true if the shuffle can be implemented as a
5641 /// logical left or right shift of a vector.
5642 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5643 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5644 // Although the logic below support any bitwidth size, there are no
5645 // shift instructions which handle more than 128-bit vectors.
5646 if (!SVOp->getSimpleValueType(0).is128BitVector())
5649 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5650 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5656 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5658 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5659 unsigned NumNonZero, unsigned NumZero,
5661 const X86Subtarget* Subtarget,
5662 const TargetLowering &TLI) {
5669 for (unsigned i = 0; i < 16; ++i) {
5670 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5671 if (ThisIsNonZero && First) {
5673 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5675 V = DAG.getUNDEF(MVT::v8i16);
5680 SDValue ThisElt, LastElt;
5681 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5682 if (LastIsNonZero) {
5683 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5684 MVT::i16, Op.getOperand(i-1));
5686 if (ThisIsNonZero) {
5687 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5688 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5689 ThisElt, DAG.getConstant(8, MVT::i8));
5691 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5695 if (ThisElt.getNode())
5696 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5697 DAG.getIntPtrConstant(i/2));
5701 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5704 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5706 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5707 unsigned NumNonZero, unsigned NumZero,
5709 const X86Subtarget* Subtarget,
5710 const TargetLowering &TLI) {
5717 for (unsigned i = 0; i < 8; ++i) {
5718 bool isNonZero = (NonZeros & (1 << i)) != 0;
5722 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5724 V = DAG.getUNDEF(MVT::v8i16);
5727 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5728 MVT::v8i16, V, Op.getOperand(i),
5729 DAG.getIntPtrConstant(i));
5736 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5737 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5738 unsigned NonZeros, unsigned NumNonZero,
5739 unsigned NumZero, SelectionDAG &DAG,
5740 const X86Subtarget *Subtarget,
5741 const TargetLowering &TLI) {
5742 // We know there's at least one non-zero element
5743 unsigned FirstNonZeroIdx = 0;
5744 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5745 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5746 X86::isZeroNode(FirstNonZero)) {
5748 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5751 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5752 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5755 SDValue V = FirstNonZero.getOperand(0);
5756 MVT VVT = V.getSimpleValueType();
5757 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5760 unsigned FirstNonZeroDst =
5761 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5762 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5763 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5764 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5766 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5767 SDValue Elem = Op.getOperand(Idx);
5768 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5771 // TODO: What else can be here? Deal with it.
5772 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5775 // TODO: Some optimizations are still possible here
5776 // ex: Getting one element from a vector, and the rest from another.
5777 if (Elem.getOperand(0) != V)
5780 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5783 else if (IncorrectIdx == -1U) {
5787 // There was already one element with an incorrect index.
5788 // We can't optimize this case to an insertps.
5792 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5794 EVT VT = Op.getSimpleValueType();
5795 unsigned ElementMoveMask = 0;
5796 if (IncorrectIdx == -1U)
5797 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5799 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5801 SDValue InsertpsMask =
5802 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5803 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5809 /// getVShift - Return a vector logical shift node.
5811 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5812 unsigned NumBits, SelectionDAG &DAG,
5813 const TargetLowering &TLI, SDLoc dl) {
5814 assert(VT.is128BitVector() && "Unknown type for VShift");
5815 EVT ShVT = MVT::v2i64;
5816 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5817 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5818 return DAG.getNode(ISD::BITCAST, dl, VT,
5819 DAG.getNode(Opc, dl, ShVT, SrcOp,
5820 DAG.getConstant(NumBits,
5821 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5825 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5827 // Check if the scalar load can be widened into a vector load. And if
5828 // the address is "base + cst" see if the cst can be "absorbed" into
5829 // the shuffle mask.
5830 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5831 SDValue Ptr = LD->getBasePtr();
5832 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5834 EVT PVT = LD->getValueType(0);
5835 if (PVT != MVT::i32 && PVT != MVT::f32)
5840 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5841 FI = FINode->getIndex();
5843 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5844 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5845 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5846 Offset = Ptr.getConstantOperandVal(1);
5847 Ptr = Ptr.getOperand(0);
5852 // FIXME: 256-bit vector instructions don't require a strict alignment,
5853 // improve this code to support it better.
5854 unsigned RequiredAlign = VT.getSizeInBits()/8;
5855 SDValue Chain = LD->getChain();
5856 // Make sure the stack object alignment is at least 16 or 32.
5857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5858 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5859 if (MFI->isFixedObjectIndex(FI)) {
5860 // Can't change the alignment. FIXME: It's possible to compute
5861 // the exact stack offset and reference FI + adjust offset instead.
5862 // If someone *really* cares about this. That's the way to implement it.
5865 MFI->setObjectAlignment(FI, RequiredAlign);
5869 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5870 // Ptr + (Offset & ~15).
5873 if ((Offset % RequiredAlign) & 3)
5875 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5877 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5878 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5880 int EltNo = (Offset - StartOffset) >> 2;
5881 unsigned NumElems = VT.getVectorNumElements();
5883 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5884 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5885 LD->getPointerInfo().getWithOffset(StartOffset),
5886 false, false, false, 0);
5888 SmallVector<int, 8> Mask;
5889 for (unsigned i = 0; i != NumElems; ++i)
5890 Mask.push_back(EltNo);
5892 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5898 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5899 /// vector of type 'VT', see if the elements can be replaced by a single large
5900 /// load which has the same value as a build_vector whose operands are 'elts'.
5902 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5904 /// FIXME: we'd also like to handle the case where the last elements are zero
5905 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5906 /// There's even a handy isZeroNode for that purpose.
5907 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5908 SDLoc &DL, SelectionDAG &DAG,
5909 bool isAfterLegalize) {
5910 EVT EltVT = VT.getVectorElementType();
5911 unsigned NumElems = Elts.size();
5913 LoadSDNode *LDBase = nullptr;
5914 unsigned LastLoadedElt = -1U;
5916 // For each element in the initializer, see if we've found a load or an undef.
5917 // If we don't find an initial load element, or later load elements are
5918 // non-consecutive, bail out.
5919 for (unsigned i = 0; i < NumElems; ++i) {
5920 SDValue Elt = Elts[i];
5922 if (!Elt.getNode() ||
5923 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5926 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5928 LDBase = cast<LoadSDNode>(Elt.getNode());
5932 if (Elt.getOpcode() == ISD::UNDEF)
5935 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5936 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5941 // If we have found an entire vector of loads and undefs, then return a large
5942 // load of the entire vector width starting at the base pointer. If we found
5943 // consecutive loads for the low half, generate a vzext_load node.
5944 if (LastLoadedElt == NumElems - 1) {
5946 if (isAfterLegalize &&
5947 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5950 SDValue NewLd = SDValue();
5952 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5953 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5954 LDBase->getPointerInfo(),
5955 LDBase->isVolatile(), LDBase->isNonTemporal(),
5956 LDBase->isInvariant(), 0);
5957 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5958 LDBase->getPointerInfo(),
5959 LDBase->isVolatile(), LDBase->isNonTemporal(),
5960 LDBase->isInvariant(), LDBase->getAlignment());
5962 if (LDBase->hasAnyUseOfValue(1)) {
5963 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5965 SDValue(NewLd.getNode(), 1));
5966 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5967 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5968 SDValue(NewLd.getNode(), 1));
5973 if (NumElems == 4 && LastLoadedElt == 1 &&
5974 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5975 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5976 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5978 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5979 LDBase->getPointerInfo(),
5980 LDBase->getAlignment(),
5981 false/*isVolatile*/, true/*ReadMem*/,
5984 // Make sure the newly-created LOAD is in the same position as LDBase in
5985 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5986 // update uses of LDBase's output chain to use the TokenFactor.
5987 if (LDBase->hasAnyUseOfValue(1)) {
5988 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5989 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5990 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5991 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5992 SDValue(ResNode.getNode(), 1));
5995 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6000 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6001 /// to generate a splat value for the following cases:
6002 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6003 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6004 /// a scalar load, or a constant.
6005 /// The VBROADCAST node is returned when a pattern is found,
6006 /// or SDValue() otherwise.
6007 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6008 SelectionDAG &DAG) {
6009 // VBROADCAST requires AVX.
6010 // TODO: Splats could be generated for non-AVX CPUs using SSE
6011 // instructions, but there's less potential gain for only 128-bit vectors.
6012 if (!Subtarget->hasAVX())
6015 MVT VT = Op.getSimpleValueType();
6018 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6019 "Unsupported vector type for broadcast.");
6024 switch (Op.getOpcode()) {
6026 // Unknown pattern found.
6029 case ISD::BUILD_VECTOR: {
6030 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6031 BitVector UndefElements;
6032 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6034 // We need a splat of a single value to use broadcast, and it doesn't
6035 // make any sense if the value is only in one element of the vector.
6036 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6040 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6041 Ld.getOpcode() == ISD::ConstantFP);
6043 // Make sure that all of the users of a non-constant load are from the
6044 // BUILD_VECTOR node.
6045 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6050 case ISD::VECTOR_SHUFFLE: {
6051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6053 // Shuffles must have a splat mask where the first element is
6055 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6058 SDValue Sc = Op.getOperand(0);
6059 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6060 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6062 if (!Subtarget->hasInt256())
6065 // Use the register form of the broadcast instruction available on AVX2.
6066 if (VT.getSizeInBits() >= 256)
6067 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6071 Ld = Sc.getOperand(0);
6072 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6073 Ld.getOpcode() == ISD::ConstantFP);
6075 // The scalar_to_vector node and the suspected
6076 // load node must have exactly one user.
6077 // Constants may have multiple users.
6079 // AVX-512 has register version of the broadcast
6080 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6081 Ld.getValueType().getSizeInBits() >= 32;
6082 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6089 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6090 bool IsGE256 = (VT.getSizeInBits() >= 256);
6092 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6093 // instruction to save 8 or more bytes of constant pool data.
6094 // TODO: If multiple splats are generated to load the same constant,
6095 // it may be detrimental to overall size. There needs to be a way to detect
6096 // that condition to know if this is truly a size win.
6097 const Function *F = DAG.getMachineFunction().getFunction();
6098 bool OptForSize = F->getAttributes().
6099 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6101 // Handle broadcasting a single constant scalar from the constant pool
6103 // On Sandybridge (no AVX2), it is still better to load a constant vector
6104 // from the constant pool and not to broadcast it from a scalar.
6105 // But override that restriction when optimizing for size.
6106 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6107 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6108 EVT CVT = Ld.getValueType();
6109 assert(!CVT.isVector() && "Must not broadcast a vector type");
6111 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6112 // For size optimization, also splat v2f64 and v2i64, and for size opt
6113 // with AVX2, also splat i8 and i16.
6114 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6115 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6116 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6117 const Constant *C = nullptr;
6118 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6119 C = CI->getConstantIntValue();
6120 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6121 C = CF->getConstantFPValue();
6123 assert(C && "Invalid constant type");
6125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6126 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6127 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6128 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6129 MachinePointerInfo::getConstantPool(),
6130 false, false, false, Alignment);
6132 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6136 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6138 // Handle AVX2 in-register broadcasts.
6139 if (!IsLoad && Subtarget->hasInt256() &&
6140 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6141 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6143 // The scalar source must be a normal load.
6147 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6148 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6150 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6151 // double since there is no vbroadcastsd xmm
6152 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6153 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6154 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6157 // Unsupported broadcast.
6161 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6162 /// underlying vector and index.
6164 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6166 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6168 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6169 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6172 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6174 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6176 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6177 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6180 // In this case the vector is the extract_subvector expression and the index
6181 // is 2, as specified by the shuffle.
6182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6183 SDValue ShuffleVec = SVOp->getOperand(0);
6184 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6185 assert(ShuffleVecVT.getVectorElementType() ==
6186 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6188 int ShuffleIdx = SVOp->getMaskElt(Idx);
6189 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6190 ExtractedFromVec = ShuffleVec;
6196 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6197 MVT VT = Op.getSimpleValueType();
6199 // Skip if insert_vec_elt is not supported.
6200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6201 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6205 unsigned NumElems = Op.getNumOperands();
6209 SmallVector<unsigned, 4> InsertIndices;
6210 SmallVector<int, 8> Mask(NumElems, -1);
6212 for (unsigned i = 0; i != NumElems; ++i) {
6213 unsigned Opc = Op.getOperand(i).getOpcode();
6215 if (Opc == ISD::UNDEF)
6218 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6219 // Quit if more than 1 elements need inserting.
6220 if (InsertIndices.size() > 1)
6223 InsertIndices.push_back(i);
6227 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6228 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6229 // Quit if non-constant index.
6230 if (!isa<ConstantSDNode>(ExtIdx))
6232 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6234 // Quit if extracted from vector of different type.
6235 if (ExtractedFromVec.getValueType() != VT)
6238 if (!VecIn1.getNode())
6239 VecIn1 = ExtractedFromVec;
6240 else if (VecIn1 != ExtractedFromVec) {
6241 if (!VecIn2.getNode())
6242 VecIn2 = ExtractedFromVec;
6243 else if (VecIn2 != ExtractedFromVec)
6244 // Quit if more than 2 vectors to shuffle
6248 if (ExtractedFromVec == VecIn1)
6250 else if (ExtractedFromVec == VecIn2)
6251 Mask[i] = Idx + NumElems;
6254 if (!VecIn1.getNode())
6257 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6258 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6259 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6260 unsigned Idx = InsertIndices[i];
6261 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6262 DAG.getIntPtrConstant(Idx));
6268 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6270 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6272 MVT VT = Op.getSimpleValueType();
6273 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6274 "Unexpected type in LowerBUILD_VECTORvXi1!");
6277 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6278 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6279 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6280 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6283 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6284 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6285 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6289 bool AllContants = true;
6290 uint64_t Immediate = 0;
6291 int NonConstIdx = -1;
6292 bool IsSplat = true;
6293 unsigned NumNonConsts = 0;
6294 unsigned NumConsts = 0;
6295 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6296 SDValue In = Op.getOperand(idx);
6297 if (In.getOpcode() == ISD::UNDEF)
6299 if (!isa<ConstantSDNode>(In)) {
6300 AllContants = false;
6306 if (cast<ConstantSDNode>(In)->getZExtValue())
6307 Immediate |= (1ULL << idx);
6309 if (In != Op.getOperand(0))
6314 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6315 DAG.getConstant(Immediate, MVT::i16));
6316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6317 DAG.getIntPtrConstant(0));
6320 if (NumNonConsts == 1 && NonConstIdx != 0) {
6323 SDValue VecAsImm = DAG.getConstant(Immediate,
6324 MVT::getIntegerVT(VT.getSizeInBits()));
6325 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6328 DstVec = DAG.getUNDEF(VT);
6329 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6330 Op.getOperand(NonConstIdx),
6331 DAG.getIntPtrConstant(NonConstIdx));
6333 if (!IsSplat && (NonConstIdx != 0))
6334 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6335 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6338 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6339 DAG.getConstant(-1, SelectVT),
6340 DAG.getConstant(0, SelectVT));
6342 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6343 DAG.getConstant((Immediate | 1), SelectVT),
6344 DAG.getConstant(Immediate, SelectVT));
6345 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6348 /// \brief Return true if \p N implements a horizontal binop and return the
6349 /// operands for the horizontal binop into V0 and V1.
6351 /// This is a helper function of PerformBUILD_VECTORCombine.
6352 /// This function checks that the build_vector \p N in input implements a
6353 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6354 /// operation to match.
6355 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6356 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6357 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6360 /// This function only analyzes elements of \p N whose indices are
6361 /// in range [BaseIdx, LastIdx).
6362 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6364 unsigned BaseIdx, unsigned LastIdx,
6365 SDValue &V0, SDValue &V1) {
6366 EVT VT = N->getValueType(0);
6368 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6369 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6370 "Invalid Vector in input!");
6372 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6373 bool CanFold = true;
6374 unsigned ExpectedVExtractIdx = BaseIdx;
6375 unsigned NumElts = LastIdx - BaseIdx;
6376 V0 = DAG.getUNDEF(VT);
6377 V1 = DAG.getUNDEF(VT);
6379 // Check if N implements a horizontal binop.
6380 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6381 SDValue Op = N->getOperand(i + BaseIdx);
6384 if (Op->getOpcode() == ISD::UNDEF) {
6385 // Update the expected vector extract index.
6386 if (i * 2 == NumElts)
6387 ExpectedVExtractIdx = BaseIdx;
6388 ExpectedVExtractIdx += 2;
6392 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6397 SDValue Op0 = Op.getOperand(0);
6398 SDValue Op1 = Op.getOperand(1);
6400 // Try to match the following pattern:
6401 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6402 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6403 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op0.getOperand(0) == Op1.getOperand(0) &&
6405 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6406 isa<ConstantSDNode>(Op1.getOperand(1)));
6410 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6411 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6413 if (i * 2 < NumElts) {
6414 if (V0.getOpcode() == ISD::UNDEF)
6415 V0 = Op0.getOperand(0);
6417 if (V1.getOpcode() == ISD::UNDEF)
6418 V1 = Op0.getOperand(0);
6419 if (i * 2 == NumElts)
6420 ExpectedVExtractIdx = BaseIdx;
6423 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6424 if (I0 == ExpectedVExtractIdx)
6425 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6426 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6427 // Try to match the following dag sequence:
6428 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6429 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6433 ExpectedVExtractIdx += 2;
6439 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6440 /// a concat_vector.
6442 /// This is a helper function of PerformBUILD_VECTORCombine.
6443 /// This function expects two 256-bit vectors called V0 and V1.
6444 /// At first, each vector is split into two separate 128-bit vectors.
6445 /// Then, the resulting 128-bit vectors are used to implement two
6446 /// horizontal binary operations.
6448 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6450 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6451 /// the two new horizontal binop.
6452 /// When Mode is set, the first horizontal binop dag node would take as input
6453 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6454 /// horizontal binop dag node would take as input the lower 128-bit of V1
6455 /// and the upper 128-bit of V1.
6457 /// HADD V0_LO, V0_HI
6458 /// HADD V1_LO, V1_HI
6460 /// Otherwise, the first horizontal binop dag node takes as input the lower
6461 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6462 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6464 /// HADD V0_LO, V1_LO
6465 /// HADD V0_HI, V1_HI
6467 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6468 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6469 /// the upper 128-bits of the result.
6470 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6471 SDLoc DL, SelectionDAG &DAG,
6472 unsigned X86Opcode, bool Mode,
6473 bool isUndefLO, bool isUndefHI) {
6474 EVT VT = V0.getValueType();
6475 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6476 "Invalid nodes in input!");
6478 unsigned NumElts = VT.getVectorNumElements();
6479 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6480 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6481 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6482 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6483 EVT NewVT = V0_LO.getValueType();
6485 SDValue LO = DAG.getUNDEF(NewVT);
6486 SDValue HI = DAG.getUNDEF(NewVT);
6489 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6490 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6491 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6492 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6493 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6495 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6496 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6497 V1_LO->getOpcode() != ISD::UNDEF))
6498 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6500 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6501 V1_HI->getOpcode() != ISD::UNDEF))
6502 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6505 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6508 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6509 /// sequence of 'vadd + vsub + blendi'.
6510 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6511 const X86Subtarget *Subtarget) {
6513 EVT VT = BV->getValueType(0);
6514 unsigned NumElts = VT.getVectorNumElements();
6515 SDValue InVec0 = DAG.getUNDEF(VT);
6516 SDValue InVec1 = DAG.getUNDEF(VT);
6518 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6519 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6521 // Odd-numbered elements in the input build vector are obtained from
6522 // adding two integer/float elements.
6523 // Even-numbered elements in the input build vector are obtained from
6524 // subtracting two integer/float elements.
6525 unsigned ExpectedOpcode = ISD::FSUB;
6526 unsigned NextExpectedOpcode = ISD::FADD;
6527 bool AddFound = false;
6528 bool SubFound = false;
6530 for (unsigned i = 0, e = NumElts; i != e; i++) {
6531 SDValue Op = BV->getOperand(i);
6533 // Skip 'undef' values.
6534 unsigned Opcode = Op.getOpcode();
6535 if (Opcode == ISD::UNDEF) {
6536 std::swap(ExpectedOpcode, NextExpectedOpcode);
6540 // Early exit if we found an unexpected opcode.
6541 if (Opcode != ExpectedOpcode)
6544 SDValue Op0 = Op.getOperand(0);
6545 SDValue Op1 = Op.getOperand(1);
6547 // Try to match the following pattern:
6548 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6549 // Early exit if we cannot match that sequence.
6550 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6551 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6553 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6554 Op0.getOperand(1) != Op1.getOperand(1))
6557 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6561 // We found a valid add/sub node. Update the information accordingly.
6567 // Update InVec0 and InVec1.
6568 if (InVec0.getOpcode() == ISD::UNDEF)
6569 InVec0 = Op0.getOperand(0);
6570 if (InVec1.getOpcode() == ISD::UNDEF)
6571 InVec1 = Op1.getOperand(0);
6573 // Make sure that operands in input to each add/sub node always
6574 // come from a same pair of vectors.
6575 if (InVec0 != Op0.getOperand(0)) {
6576 if (ExpectedOpcode == ISD::FSUB)
6579 // FADD is commutable. Try to commute the operands
6580 // and then test again.
6581 std::swap(Op0, Op1);
6582 if (InVec0 != Op0.getOperand(0))
6586 if (InVec1 != Op1.getOperand(0))
6589 // Update the pair of expected opcodes.
6590 std::swap(ExpectedOpcode, NextExpectedOpcode);
6593 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6594 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6595 InVec1.getOpcode() != ISD::UNDEF)
6596 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6601 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6602 const X86Subtarget *Subtarget) {
6604 EVT VT = N->getValueType(0);
6605 unsigned NumElts = VT.getVectorNumElements();
6606 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6607 SDValue InVec0, InVec1;
6609 // Try to match an ADDSUB.
6610 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6611 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6612 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6613 if (Value.getNode())
6617 // Try to match horizontal ADD/SUB.
6618 unsigned NumUndefsLO = 0;
6619 unsigned NumUndefsHI = 0;
6620 unsigned Half = NumElts/2;
6622 // Count the number of UNDEF operands in the build_vector in input.
6623 for (unsigned i = 0, e = Half; i != e; ++i)
6624 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6627 for (unsigned i = Half, e = NumElts; i != e; ++i)
6628 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6631 // Early exit if this is either a build_vector of all UNDEFs or all the
6632 // operands but one are UNDEF.
6633 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6636 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6637 // Try to match an SSE3 float HADD/HSUB.
6638 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6641 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6642 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6643 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6644 // Try to match an SSSE3 integer HADD/HSUB.
6645 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6646 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6648 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6652 if (!Subtarget->hasAVX())
6655 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6656 // Try to match an AVX horizontal add/sub of packed single/double
6657 // precision floating point values from 256-bit vectors.
6658 SDValue InVec2, InVec3;
6659 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6660 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6661 ((InVec0.getOpcode() == ISD::UNDEF ||
6662 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6663 ((InVec1.getOpcode() == ISD::UNDEF ||
6664 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6665 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6667 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6668 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6669 ((InVec0.getOpcode() == ISD::UNDEF ||
6670 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6671 ((InVec1.getOpcode() == ISD::UNDEF ||
6672 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6673 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6674 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6675 // Try to match an AVX2 horizontal add/sub of signed integers.
6676 SDValue InVec2, InVec3;
6678 bool CanFold = true;
6680 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6681 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6682 ((InVec0.getOpcode() == ISD::UNDEF ||
6683 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6684 ((InVec1.getOpcode() == ISD::UNDEF ||
6685 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6686 X86Opcode = X86ISD::HADD;
6687 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6688 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6689 ((InVec0.getOpcode() == ISD::UNDEF ||
6690 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6691 ((InVec1.getOpcode() == ISD::UNDEF ||
6692 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6693 X86Opcode = X86ISD::HSUB;
6698 // Fold this build_vector into a single horizontal add/sub.
6699 // Do this only if the target has AVX2.
6700 if (Subtarget->hasAVX2())
6701 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6703 // Do not try to expand this build_vector into a pair of horizontal
6704 // add/sub if we can emit a pair of scalar add/sub.
6705 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6708 // Convert this build_vector into a pair of horizontal binop followed by
6710 bool isUndefLO = NumUndefsLO == Half;
6711 bool isUndefHI = NumUndefsHI == Half;
6712 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6713 isUndefLO, isUndefHI);
6717 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6718 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6721 X86Opcode = X86ISD::HADD;
6722 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6723 X86Opcode = X86ISD::HSUB;
6724 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6725 X86Opcode = X86ISD::FHADD;
6726 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6727 X86Opcode = X86ISD::FHSUB;
6731 // Don't try to expand this build_vector into a pair of horizontal add/sub
6732 // if we can simply emit a pair of scalar add/sub.
6733 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6736 // Convert this build_vector into two horizontal add/sub followed by
6738 bool isUndefLO = NumUndefsLO == Half;
6739 bool isUndefHI = NumUndefsHI == Half;
6740 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6741 isUndefLO, isUndefHI);
6748 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6751 MVT VT = Op.getSimpleValueType();
6752 MVT ExtVT = VT.getVectorElementType();
6753 unsigned NumElems = Op.getNumOperands();
6755 // Generate vectors for predicate vectors.
6756 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6757 return LowerBUILD_VECTORvXi1(Op, DAG);
6759 // Vectors containing all zeros can be matched by pxor and xorps later
6760 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6761 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6762 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6763 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6766 return getZeroVector(VT, Subtarget, DAG, dl);
6769 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6770 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6771 // vpcmpeqd on 256-bit vectors.
6772 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6773 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6776 if (!VT.is512BitVector())
6777 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6780 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6781 if (Broadcast.getNode())
6784 unsigned EVTBits = ExtVT.getSizeInBits();
6786 unsigned NumZero = 0;
6787 unsigned NumNonZero = 0;
6788 unsigned NonZeros = 0;
6789 bool IsAllConstants = true;
6790 SmallSet<SDValue, 8> Values;
6791 for (unsigned i = 0; i < NumElems; ++i) {
6792 SDValue Elt = Op.getOperand(i);
6793 if (Elt.getOpcode() == ISD::UNDEF)
6796 if (Elt.getOpcode() != ISD::Constant &&
6797 Elt.getOpcode() != ISD::ConstantFP)
6798 IsAllConstants = false;
6799 if (X86::isZeroNode(Elt))
6802 NonZeros |= (1 << i);
6807 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6808 if (NumNonZero == 0)
6809 return DAG.getUNDEF(VT);
6811 // Special case for single non-zero, non-undef, element.
6812 if (NumNonZero == 1) {
6813 unsigned Idx = countTrailingZeros(NonZeros);
6814 SDValue Item = Op.getOperand(Idx);
6816 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6817 // the value are obviously zero, truncate the value to i32 and do the
6818 // insertion that way. Only do this if the value is non-constant or if the
6819 // value is a constant being inserted into element 0. It is cheaper to do
6820 // a constant pool load than it is to do a movd + shuffle.
6821 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6822 (!IsAllConstants || Idx == 0)) {
6823 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6825 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6826 EVT VecVT = MVT::v4i32;
6827 unsigned VecElts = 4;
6829 // Truncate the value (which may itself be a constant) to i32, and
6830 // convert it to a vector with movd (S2V+shuffle to zero extend).
6831 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6832 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6834 // If using the new shuffle lowering, just directly insert this.
6835 if (ExperimentalVectorShuffleLowering)
6837 ISD::BITCAST, dl, VT,
6838 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6840 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6842 // Now we have our 32-bit value zero extended in the low element of
6843 // a vector. If Idx != 0, swizzle it into place.
6845 SmallVector<int, 4> Mask;
6846 Mask.push_back(Idx);
6847 for (unsigned i = 1; i != VecElts; ++i)
6849 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6852 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6856 // If we have a constant or non-constant insertion into the low element of
6857 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6858 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6859 // depending on what the source datatype is.
6862 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6864 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6865 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6866 if (VT.is256BitVector() || VT.is512BitVector()) {
6867 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6868 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6869 Item, DAG.getIntPtrConstant(0));
6871 assert(VT.is128BitVector() && "Expected an SSE value type!");
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6873 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6874 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6877 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6878 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6879 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6880 if (VT.is256BitVector()) {
6881 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6882 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6884 assert(VT.is128BitVector() && "Expected an SSE value type!");
6885 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6887 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6891 // Is it a vector logical left shift?
6892 if (NumElems == 2 && Idx == 1 &&
6893 X86::isZeroNode(Op.getOperand(0)) &&
6894 !X86::isZeroNode(Op.getOperand(1))) {
6895 unsigned NumBits = VT.getSizeInBits();
6896 return getVShift(true, VT,
6897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6898 VT, Op.getOperand(1)),
6899 NumBits/2, DAG, *this, dl);
6902 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6905 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6906 // is a non-constant being inserted into an element other than the low one,
6907 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6908 // movd/movss) to move this into the low element, then shuffle it into
6910 if (EVTBits == 32) {
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // If using the new shuffle lowering, just directly insert this.
6914 if (ExperimentalVectorShuffleLowering)
6915 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6917 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6918 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6919 SmallVector<int, 8> MaskVec;
6920 for (unsigned i = 0; i != NumElems; ++i)
6921 MaskVec.push_back(i == Idx ? 0 : 1);
6922 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6926 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6927 if (Values.size() == 1) {
6928 if (EVTBits == 32) {
6929 // Instead of a shuffle like this:
6930 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6931 // Check if it's possible to issue this instead.
6932 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6933 unsigned Idx = countTrailingZeros(NonZeros);
6934 SDValue Item = Op.getOperand(Idx);
6935 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6936 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6941 // A vector full of immediates; various special cases are already
6942 // handled, so this is best done with a single constant-pool load.
6946 // For AVX-length vectors, build the individual 128-bit pieces and use
6947 // shuffles to put them in place.
6948 if (VT.is256BitVector() || VT.is512BitVector()) {
6949 SmallVector<SDValue, 64> V;
6950 for (unsigned i = 0; i != NumElems; ++i)
6951 V.push_back(Op.getOperand(i));
6953 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6955 // Build both the lower and upper subvector.
6956 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6957 makeArrayRef(&V[0], NumElems/2));
6958 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6959 makeArrayRef(&V[NumElems / 2], NumElems/2));
6961 // Recreate the wider vector with the lower and upper part.
6962 if (VT.is256BitVector())
6963 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6964 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6967 // Let legalizer expand 2-wide build_vectors.
6968 if (EVTBits == 64) {
6969 if (NumNonZero == 1) {
6970 // One half is zero or undef.
6971 unsigned Idx = countTrailingZeros(NonZeros);
6972 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6973 Op.getOperand(Idx));
6974 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6979 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6980 if (EVTBits == 8 && NumElems == 16) {
6981 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6983 if (V.getNode()) return V;
6986 if (EVTBits == 16 && NumElems == 8) {
6987 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6989 if (V.getNode()) return V;
6992 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6993 if (EVTBits == 32 && NumElems == 4) {
6994 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6995 NumZero, DAG, Subtarget, *this);
7000 // If element VT is == 32 bits, turn it into a number of shuffles.
7001 SmallVector<SDValue, 8> V(NumElems);
7002 if (NumElems == 4 && NumZero > 0) {
7003 for (unsigned i = 0; i < 4; ++i) {
7004 bool isZero = !(NonZeros & (1 << i));
7006 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7008 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7011 for (unsigned i = 0; i < 2; ++i) {
7012 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7015 V[i] = V[i*2]; // Must be a zero vector.
7018 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7021 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7024 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7029 bool Reverse1 = (NonZeros & 0x3) == 2;
7030 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7034 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7035 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7037 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7040 if (Values.size() > 1 && VT.is128BitVector()) {
7041 // Check for a build vector of consecutive loads.
7042 for (unsigned i = 0; i < NumElems; ++i)
7043 V[i] = Op.getOperand(i);
7045 // Check for elements which are consecutive loads.
7046 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7050 // Check for a build vector from mostly shuffle plus few inserting.
7051 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7055 // For SSE 4.1, use insertps to put the high elements into the low element.
7056 if (getSubtarget()->hasSSE41()) {
7058 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7059 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7061 Result = DAG.getUNDEF(VT);
7063 for (unsigned i = 1; i < NumElems; ++i) {
7064 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7065 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7066 Op.getOperand(i), DAG.getIntPtrConstant(i));
7071 // Otherwise, expand into a number of unpckl*, start by extending each of
7072 // our (non-undef) elements to the full vector width with the element in the
7073 // bottom slot of the vector (which generates no code for SSE).
7074 for (unsigned i = 0; i < NumElems; ++i) {
7075 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7076 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7078 V[i] = DAG.getUNDEF(VT);
7081 // Next, we iteratively mix elements, e.g. for v4f32:
7082 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7083 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7084 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7085 unsigned EltStride = NumElems >> 1;
7086 while (EltStride != 0) {
7087 for (unsigned i = 0; i < EltStride; ++i) {
7088 // If V[i+EltStride] is undef and this is the first round of mixing,
7089 // then it is safe to just drop this shuffle: V[i] is already in the
7090 // right place, the one element (since it's the first round) being
7091 // inserted as undef can be dropped. This isn't safe for successive
7092 // rounds because they will permute elements within both vectors.
7093 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7094 EltStride == NumElems/2)
7097 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7106 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7107 // to create 256-bit vectors from two other 128-bit ones.
7108 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7110 MVT ResVT = Op.getSimpleValueType();
7112 assert((ResVT.is256BitVector() ||
7113 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7115 SDValue V1 = Op.getOperand(0);
7116 SDValue V2 = Op.getOperand(1);
7117 unsigned NumElems = ResVT.getVectorNumElements();
7118 if(ResVT.is256BitVector())
7119 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7121 if (Op.getNumOperands() == 4) {
7122 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7123 ResVT.getVectorNumElements()/2);
7124 SDValue V3 = Op.getOperand(2);
7125 SDValue V4 = Op.getOperand(3);
7126 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7127 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7129 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7132 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7133 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7134 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7135 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7136 Op.getNumOperands() == 4)));
7138 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7139 // from two other 128-bit ones.
7141 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7142 return LowerAVXCONCAT_VECTORS(Op, DAG);
7146 //===----------------------------------------------------------------------===//
7147 // Vector shuffle lowering
7149 // This is an experimental code path for lowering vector shuffles on x86. It is
7150 // designed to handle arbitrary vector shuffles and blends, gracefully
7151 // degrading performance as necessary. It works hard to recognize idiomatic
7152 // shuffles and lower them to optimal instruction patterns without leaving
7153 // a framework that allows reasonably efficient handling of all vector shuffle
7155 //===----------------------------------------------------------------------===//
7157 /// \brief Tiny helper function to identify a no-op mask.
7159 /// This is a somewhat boring predicate function. It checks whether the mask
7160 /// array input, which is assumed to be a single-input shuffle mask of the kind
7161 /// used by the X86 shuffle instructions (not a fully general
7162 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7163 /// in-place shuffle are 'no-op's.
7164 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7165 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7166 if (Mask[i] != -1 && Mask[i] != i)
7171 /// \brief Helper function to classify a mask as a single-input mask.
7173 /// This isn't a generic single-input test because in the vector shuffle
7174 /// lowering we canonicalize single inputs to be the first input operand. This
7175 /// means we can more quickly test for a single input by only checking whether
7176 /// an input from the second operand exists. We also assume that the size of
7177 /// mask corresponds to the size of the input vectors which isn't true in the
7178 /// fully general case.
7179 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7181 if (M >= (int)Mask.size())
7186 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7187 // 2013 will allow us to use it as a non-type template parameter.
7190 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7192 /// See its documentation for details.
7193 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7194 if (Mask.size() != Args.size())
7196 for (int i = 0, e = Mask.size(); i < e; ++i) {
7197 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7198 if (Mask[i] != -1 && Mask[i] != *Args[i])
7206 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7209 /// This is a fast way to test a shuffle mask against a fixed pattern:
7211 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7213 /// It returns true if the mask is exactly as wide as the argument list, and
7214 /// each element of the mask is either -1 (signifying undef) or the value given
7215 /// in the argument.
7216 static const VariadicFunction1<
7217 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7219 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7221 /// This helper function produces an 8-bit shuffle immediate corresponding to
7222 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7223 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7226 /// NB: We rely heavily on "undef" masks preserving the input lane.
7227 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7228 SelectionDAG &DAG) {
7229 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7230 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7231 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7232 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7233 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7236 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7237 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7238 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7239 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7240 return DAG.getConstant(Imm, MVT::i8);
7243 /// \brief Try to emit a blend instruction for a shuffle.
7245 /// This doesn't do any checks for the availability of instructions for blending
7246 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7247 /// be matched in the backend with the type given. What it does check for is
7248 /// that the shuffle mask is in fact a blend.
7249 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7250 SDValue V2, ArrayRef<int> Mask,
7251 const X86Subtarget *Subtarget,
7252 SelectionDAG &DAG) {
7254 unsigned BlendMask = 0;
7255 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7256 if (Mask[i] >= Size) {
7257 if (Mask[i] != i + Size)
7258 return SDValue(); // Shuffled V2 input!
7259 BlendMask |= 1u << i;
7262 if (Mask[i] >= 0 && Mask[i] != i)
7263 return SDValue(); // Shuffled V1 input!
7265 switch (VT.SimpleTy) {
7270 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7271 DAG.getConstant(BlendMask, MVT::i8));
7275 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7276 // that instruction.
7277 if (Subtarget->hasAVX2()) {
7278 int Scale = 4 / VT.getVectorNumElements();
7280 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7281 if (Mask[i] >= Size)
7282 for (int j = 0; j < Scale; ++j)
7283 BlendMask |= 1u << (i * Scale + j);
7285 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7286 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7287 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7288 return DAG.getNode(ISD::BITCAST, DL, VT,
7289 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7290 DAG.getConstant(BlendMask, MVT::i8)));
7294 // For integer shuffles we need to expand the mask and cast the inputs to
7295 // v8i16s prior to blending.
7296 int Scale = 8 / VT.getVectorNumElements();
7298 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7299 if (Mask[i] >= Size)
7300 for (int j = 0; j < Scale; ++j)
7301 BlendMask |= 1u << (i * Scale + j);
7303 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7304 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7305 return DAG.getNode(ISD::BITCAST, DL, VT,
7306 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7307 DAG.getConstant(BlendMask, MVT::i8)));
7311 llvm_unreachable("Not a supported integer vector type!");
7315 /// \brief Try to lower a vector shuffle as a byte rotation.
7317 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7318 /// byte-rotation of a the concatentation of two vectors. This routine will
7319 /// try to generically lower a vector shuffle through such an instruction. It
7320 /// does not check for the availability of PALIGNR-based lowerings, only the
7321 /// applicability of this strategy to the given mask. This matches shuffle
7322 /// vectors that look like:
7324 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7326 /// Essentially it concatenates V1 and V2, shifts right by some number of
7327 /// elements, and takes the low elements as the result. Note that while this is
7328 /// specified as a *right shift* because x86 is little-endian, it is a *left
7329 /// rotate* of the vector lanes.
7331 /// Note that this only handles 128-bit vector widths currently.
7332 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7335 SelectionDAG &DAG) {
7336 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7338 // We need to detect various ways of spelling a rotation:
7339 // [11, 12, 13, 14, 15, 0, 1, 2]
7340 // [-1, 12, 13, 14, -1, -1, 1, -1]
7341 // [-1, -1, -1, -1, -1, -1, 1, 2]
7342 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7343 // [-1, 4, 5, 6, -1, -1, 9, -1]
7344 // [-1, 4, 5, 6, -1, -1, -1, -1]
7347 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7350 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7352 // Based on the mod-Size value of this mask element determine where
7353 // a rotated vector would have started.
7354 int StartIdx = i - (Mask[i] % Size);
7356 // The identity rotation isn't interesting, stop.
7359 // If we found the tail of a vector the rotation must be the missing
7360 // front. If we found the head of a vector, it must be how much of the head.
7361 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7364 Rotation = CandidateRotation;
7365 else if (Rotation != CandidateRotation)
7366 // The rotations don't match, so we can't match this mask.
7369 // Compute which value this mask is pointing at.
7370 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7372 // Compute which of the two target values this index should be assigned to.
7373 // This reflects whether the high elements are remaining or the low elements
7375 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7377 // Either set up this value if we've not encountered it before, or check
7378 // that it remains consistent.
7381 else if (TargetV != MaskV)
7382 // This may be a rotation, but it pulls from the inputs in some
7383 // unsupported interleaving.
7387 // Check that we successfully analyzed the mask, and normalize the results.
7388 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7389 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7395 // Cast the inputs to v16i8 to match PALIGNR.
7396 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7397 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7399 assert(VT.getSizeInBits() == 128 &&
7400 "Rotate-based lowering only supports 128-bit lowering!");
7401 assert(Mask.size() <= 16 &&
7402 "Can shuffle at most 16 bytes in a 128-bit vector!");
7403 // The actual rotate instruction rotates bytes, so we need to scale the
7404 // rotation based on how many bytes are in the vector.
7405 int Scale = 16 / Mask.size();
7407 return DAG.getNode(ISD::BITCAST, DL, VT,
7408 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7409 DAG.getConstant(Rotation * Scale, MVT::i8)));
7412 /// \brief Compute whether each element of a shuffle is zeroable.
7414 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7415 /// Either it is an undef element in the shuffle mask, the element of the input
7416 /// referenced is undef, or the element of the input referenced is known to be
7417 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7418 /// as many lanes with this technique as possible to simplify the remaining
7420 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7421 SDValue V1, SDValue V2) {
7422 SmallBitVector Zeroable(Mask.size(), false);
7424 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7425 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7427 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7429 // Handle the easy cases.
7430 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7435 // If this is an index into a build_vector node, dig out the input value and
7437 SDValue V = M < Size ? V1 : V2;
7438 if (V.getOpcode() != ISD::BUILD_VECTOR)
7441 SDValue Input = V.getOperand(M % Size);
7442 // The UNDEF opcode check really should be dead code here, but not quite
7443 // worth asserting on (it isn't invalid, just unexpected).
7444 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7451 /// \brief Lower a vector shuffle as a zero or any extension.
7453 /// Given a specific number of elements, element bit width, and extension
7454 /// stride, produce either a zero or any extension based on the available
7455 /// features of the subtarget.
7456 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7457 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7458 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7459 assert(Scale > 1 && "Need a scale to extend.");
7460 int EltBits = VT.getSizeInBits() / NumElements;
7461 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7462 "Only 8, 16, and 32 bit elements can be extended.");
7463 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7465 // Found a valid zext mask! Try various lowering strategies based on the
7466 // input type and available ISA extensions.
7467 if (Subtarget->hasSSE41()) {
7468 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7469 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7470 NumElements / Scale);
7471 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7472 return DAG.getNode(ISD::BITCAST, DL, VT,
7473 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7476 // For any extends we can cheat for larger element sizes and use shuffle
7477 // instructions that can fold with a load and/or copy.
7478 if (AnyExt && EltBits == 32) {
7479 int PSHUFDMask[4] = {0, -1, 1, -1};
7481 ISD::BITCAST, DL, VT,
7482 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7483 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7484 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7486 if (AnyExt && EltBits == 16 && Scale > 2) {
7487 int PSHUFDMask[4] = {0, -1, 0, -1};
7488 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7489 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7490 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7491 int PSHUFHWMask[4] = {1, -1, -1, -1};
7493 ISD::BITCAST, DL, VT,
7494 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7495 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7496 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7499 // If this would require more than 2 unpack instructions to expand, use
7500 // pshufb when available. We can only use more than 2 unpack instructions
7501 // when zero extending i8 elements which also makes it easier to use pshufb.
7502 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7503 assert(NumElements == 16 && "Unexpected byte vector width!");
7504 SDValue PSHUFBMask[16];
7505 for (int i = 0; i < 16; ++i)
7507 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7508 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7509 return DAG.getNode(ISD::BITCAST, DL, VT,
7510 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7511 DAG.getNode(ISD::BUILD_VECTOR, DL,
7512 MVT::v16i8, PSHUFBMask)));
7515 // Otherwise emit a sequence of unpacks.
7517 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7518 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7519 : getZeroVector(InputVT, Subtarget, DAG, DL);
7520 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7521 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7525 } while (Scale > 1);
7526 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7529 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7531 /// This routine will try to do everything in its power to cleverly lower
7532 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7533 /// check for the profitability of this lowering, it tries to aggressively
7534 /// match this pattern. It will use all of the micro-architectural details it
7535 /// can to emit an efficient lowering. It handles both blends with all-zero
7536 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7537 /// masking out later).
7539 /// The reason we have dedicated lowering for zext-style shuffles is that they
7540 /// are both incredibly common and often quite performance sensitive.
7541 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7542 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7543 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7544 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7546 int Bits = VT.getSizeInBits();
7547 int NumElements = Mask.size();
7549 // Define a helper function to check a particular ext-scale and lower to it if
7551 auto Lower = [&](int Scale) -> SDValue {
7554 for (int i = 0; i < NumElements; ++i) {
7556 continue; // Valid anywhere but doesn't tell us anything.
7557 if (i % Scale != 0) {
7558 // Each of the extend elements needs to be zeroable.
7562 // We no lorger are in the anyext case.
7567 // Each of the base elements needs to be consecutive indices into the
7568 // same input vector.
7569 SDValue V = Mask[i] < NumElements ? V1 : V2;
7572 else if (InputV != V)
7573 return SDValue(); // Flip-flopping inputs.
7575 if (Mask[i] % NumElements != i / Scale)
7576 return SDValue(); // Non-consecutive strided elemenst.
7579 // If we fail to find an input, we have a zero-shuffle which should always
7580 // have already been handled.
7581 // FIXME: Maybe handle this here in case during blending we end up with one?
7585 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7586 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7589 // The widest scale possible for extending is to a 64-bit integer.
7590 assert(Bits % 64 == 0 &&
7591 "The number of bits in a vector must be divisible by 64 on x86!");
7592 int NumExtElements = Bits / 64;
7594 // Each iteration, try extending the elements half as much, but into twice as
7596 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7597 assert(NumElements % NumExtElements == 0 &&
7598 "The input vector size must be divisble by the extended size.");
7599 if (SDValue V = Lower(NumElements / NumExtElements))
7603 // No viable ext lowering found.
7607 /// \brief Try to lower insertion of a single element into a zero vector.
7609 /// This is a common pattern that we have especially efficient patterns to lower
7610 /// across all subtarget feature sets.
7611 static SDValue lowerVectorShuffleAsElementInsertion(
7612 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7613 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7614 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7616 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7617 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7619 if (Mask.size() == 2) {
7620 if (!Zeroable[V2Index ^ 1]) {
7621 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7622 // with 2 to flip from {2,3} to {0,1} and vice versa.
7623 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7624 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7625 if (Zeroable[V2Index])
7626 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7632 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7633 if (i != V2Index && !Zeroable[i])
7634 return SDValue(); // Not inserting into a zero vector.
7637 // Step over any bitcasts on either input so we can scan the actual
7638 // BUILD_VECTOR nodes.
7639 while (V1.getOpcode() == ISD::BITCAST)
7640 V1 = V1.getOperand(0);
7641 while (V2.getOpcode() == ISD::BITCAST)
7642 V2 = V2.getOperand(0);
7644 // Check for a single input from a SCALAR_TO_VECTOR node.
7645 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7646 // all the smarts here sunk into that routine. However, the current
7647 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7648 // vector shuffle lowering is dead.
7649 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7650 Mask[V2Index] == (int)Mask.size()) ||
7651 V2.getOpcode() == ISD::BUILD_VECTOR))
7654 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7656 // First, we need to zext the scalar if it is smaller than an i32.
7658 MVT EltVT = VT.getVectorElementType();
7659 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7660 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7661 // Zero-extend directly to i32.
7663 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7666 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7667 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7669 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7672 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7673 // the desired position. Otherwise it is more efficient to do a vector
7674 // shift left. We know that we can do a vector shift left because all
7675 // the inputs are zero.
7676 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7677 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7678 V2Shuffle[V2Index] = 0;
7679 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7681 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7683 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7685 V2Index * EltVT.getSizeInBits(),
7686 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7687 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7693 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7695 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7696 /// support for floating point shuffles but not integer shuffles. These
7697 /// instructions will incur a domain crossing penalty on some chips though so
7698 /// it is better to avoid lowering through this for integer vectors where
7700 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7701 const X86Subtarget *Subtarget,
7702 SelectionDAG &DAG) {
7704 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7705 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7706 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7707 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7708 ArrayRef<int> Mask = SVOp->getMask();
7709 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7711 if (isSingleInputShuffleMask(Mask)) {
7712 // Straight shuffle of a single input vector. Simulate this by using the
7713 // single input as both of the "inputs" to this instruction..
7714 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7716 if (Subtarget->hasAVX()) {
7717 // If we have AVX, we can use VPERMILPS which will allow folding a load
7718 // into the shuffle.
7719 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7720 DAG.getConstant(SHUFPDMask, MVT::i8));
7723 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7724 DAG.getConstant(SHUFPDMask, MVT::i8));
7726 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7727 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7729 // Use dedicated unpack instructions for masks that match their pattern.
7730 if (isShuffleEquivalent(Mask, 0, 2))
7731 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7732 if (isShuffleEquivalent(Mask, 1, 3))
7733 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7735 // If we have a single input, insert that into V1 if we can do so cheaply.
7736 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7737 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7738 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7741 if (Subtarget->hasSSE41())
7742 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7746 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7747 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7748 DAG.getConstant(SHUFPDMask, MVT::i8));
7751 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7753 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7754 /// the integer unit to minimize domain crossing penalties. However, for blends
7755 /// it falls back to the floating point shuffle operation with appropriate bit
7757 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7758 const X86Subtarget *Subtarget,
7759 SelectionDAG &DAG) {
7761 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7762 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7763 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7764 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7765 ArrayRef<int> Mask = SVOp->getMask();
7766 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7768 if (isSingleInputShuffleMask(Mask)) {
7769 // Straight shuffle of a single input vector. For everything from SSE2
7770 // onward this has a single fast instruction with no scary immediates.
7771 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7772 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7773 int WidenedMask[4] = {
7774 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7775 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7777 ISD::BITCAST, DL, MVT::v2i64,
7778 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7779 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7782 // Use dedicated unpack instructions for masks that match their pattern.
7783 if (isShuffleEquivalent(Mask, 0, 2))
7784 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7785 if (isShuffleEquivalent(Mask, 1, 3))
7786 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7788 // If we have a single input from V2 insert that into V1 if we can do so
7790 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7791 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7792 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7795 if (Subtarget->hasSSE41())
7796 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7800 // Try to use rotation instructions if available.
7801 if (Subtarget->hasSSSE3())
7802 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7803 DL, MVT::v2i64, V1, V2, Mask, DAG))
7806 // We implement this with SHUFPD which is pretty lame because it will likely
7807 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7808 // However, all the alternatives are still more cycles and newer chips don't
7809 // have this problem. It would be really nice if x86 had better shuffles here.
7810 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7811 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7812 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7813 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7816 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7818 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7819 /// It makes no assumptions about whether this is the *best* lowering, it simply
7821 static SDValue lowerVectorShuffleWithSHUPFS(SDLoc DL, MVT VT,
7822 ArrayRef<int> Mask, SDValue V1,
7823 SDValue V2, SelectionDAG &DAG) {
7824 SDValue LowV = V1, HighV = V2;
7825 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7828 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7830 if (NumV2Elements == 1) {
7832 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7835 // Compute the index adjacent to V2Index and in the same half by toggling
7837 int V2AdjIndex = V2Index ^ 1;
7839 if (Mask[V2AdjIndex] == -1) {
7840 // Handles all the cases where we have a single V2 element and an undef.
7841 // This will only ever happen in the high lanes because we commute the
7842 // vector otherwise.
7844 std::swap(LowV, HighV);
7845 NewMask[V2Index] -= 4;
7847 // Handle the case where the V2 element ends up adjacent to a V1 element.
7848 // To make this work, blend them together as the first step.
7849 int V1Index = V2AdjIndex;
7850 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7851 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7852 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7854 // Now proceed to reconstruct the final blend as we have the necessary
7855 // high or low half formed.
7862 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7863 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7865 } else if (NumV2Elements == 2) {
7866 if (Mask[0] < 4 && Mask[1] < 4) {
7867 // Handle the easy case where we have V1 in the low lanes and V2 in the
7868 // high lanes. We never see this reversed because we sort the shuffle.
7872 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7873 // trying to place elements directly, just blend them and set up the final
7874 // shuffle to place them.
7876 // The first two blend mask elements are for V1, the second two are for
7878 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7879 Mask[2] < 4 ? Mask[2] : Mask[3],
7880 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7881 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7882 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7883 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7885 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7888 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7889 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7890 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7891 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7894 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7895 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7898 /// \brief Lower 4-lane 32-bit floating point shuffles.
7900 /// Uses instructions exclusively from the floating point unit to minimize
7901 /// domain crossing penalties, as these are sufficient to implement all v4f32
7903 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7904 const X86Subtarget *Subtarget,
7905 SelectionDAG &DAG) {
7907 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7908 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7909 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7910 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7911 ArrayRef<int> Mask = SVOp->getMask();
7912 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7915 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7917 if (NumV2Elements == 0) {
7918 if (Subtarget->hasAVX()) {
7919 // If we have AVX, we can use VPERMILPS which will allow folding a load
7920 // into the shuffle.
7921 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7922 getV4X86ShuffleImm8ForMask(Mask, DAG));
7925 // Otherwise, use a straight shuffle of a single input vector. We pass the
7926 // input vector to both operands to simulate this with a SHUFPS.
7927 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7928 getV4X86ShuffleImm8ForMask(Mask, DAG));
7931 // Use dedicated unpack instructions for masks that match their pattern.
7932 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7933 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7934 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7935 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7937 // There are special ways we can lower some single-element blends. However, we
7938 // have custom ways we can lower more complex single-element blends below that
7939 // we defer to if both this and BLENDPS fail to match, so restrict this to
7940 // when the V2 input is targeting element 0 of the mask -- that is the fast
7942 if (NumV2Elements == 1 && Mask[0] >= 4)
7943 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
7944 Mask, Subtarget, DAG))
7947 if (Subtarget->hasSSE41())
7948 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7952 // Check for whether we can use INSERTPS to perform the blend. We only use
7953 // INSERTPS when the V1 elements are already in the correct locations
7954 // because otherwise we can just always use two SHUFPS instructions which
7955 // are much smaller to encode than a SHUFPS and an INSERTPS.
7956 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
7958 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7961 // When using INSERTPS we can zero any lane of the destination. Collect
7962 // the zero inputs into a mask and drop them from the lanes of V1 which
7963 // actually need to be present as inputs to the INSERTPS.
7964 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7966 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
7967 bool InsertNeedsShuffle = false;
7969 for (int i = 0; i < 4; ++i)
7973 } else if (Mask[i] != i) {
7974 InsertNeedsShuffle = true;
7979 // We don't want to use INSERTPS or other insertion techniques if it will
7980 // require shuffling anyways.
7981 if (!InsertNeedsShuffle) {
7982 // If all of V1 is zeroable, replace it with undef.
7983 if ((ZMask | 1 << V2Index) == 0xF)
7984 V1 = DAG.getUNDEF(MVT::v4f32);
7986 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
7987 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7989 // Insert the V2 element into the desired position.
7990 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7991 DAG.getConstant(InsertPSMask, MVT::i8));
7995 // Otherwise fall back to a SHUFPS lowering strategy.
7996 return lowerVectorShuffleWithSHUPFS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7999 /// \brief Lower 4-lane i32 vector shuffles.
8001 /// We try to handle these with integer-domain shuffles where we can, but for
8002 /// blends we use the floating point domain blend instructions.
8003 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8004 const X86Subtarget *Subtarget,
8005 SelectionDAG &DAG) {
8007 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8008 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8009 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8010 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8011 ArrayRef<int> Mask = SVOp->getMask();
8012 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8015 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8017 if (NumV2Elements == 0) {
8018 // Straight shuffle of a single input vector. For everything from SSE2
8019 // onward this has a single fast instruction with no scary immediates.
8020 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8021 // but we aren't actually going to use the UNPCK instruction because doing
8022 // so prevents folding a load into this instruction or making a copy.
8023 const int UnpackLoMask[] = {0, 0, 1, 1};
8024 const int UnpackHiMask[] = {2, 2, 3, 3};
8025 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8026 Mask = UnpackLoMask;
8027 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8028 Mask = UnpackHiMask;
8030 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8031 getV4X86ShuffleImm8ForMask(Mask, DAG));
8034 // Whenever we can lower this as a zext, that instruction is strictly faster
8035 // than any alternative.
8036 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8037 Mask, Subtarget, DAG))
8040 // Use dedicated unpack instructions for masks that match their pattern.
8041 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8042 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8043 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8044 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8046 // There are special ways we can lower some single-element blends.
8047 if (NumV2Elements == 1)
8048 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8049 Mask, Subtarget, DAG))
8052 if (Subtarget->hasSSE41())
8053 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8057 // Try to use rotation instructions if available.
8058 if (Subtarget->hasSSSE3())
8059 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8060 DL, MVT::v4i32, V1, V2, Mask, DAG))
8063 // We implement this with SHUFPS because it can blend from two vectors.
8064 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8065 // up the inputs, bypassing domain shift penalties that we would encur if we
8066 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8068 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8069 DAG.getVectorShuffle(
8071 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8072 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8075 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8076 /// shuffle lowering, and the most complex part.
8078 /// The lowering strategy is to try to form pairs of input lanes which are
8079 /// targeted at the same half of the final vector, and then use a dword shuffle
8080 /// to place them onto the right half, and finally unpack the paired lanes into
8081 /// their final position.
8083 /// The exact breakdown of how to form these dword pairs and align them on the
8084 /// correct sides is really tricky. See the comments within the function for
8085 /// more of the details.
8086 static SDValue lowerV8I16SingleInputVectorShuffle(
8087 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8088 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8089 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8090 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8091 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8093 SmallVector<int, 4> LoInputs;
8094 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8095 [](int M) { return M >= 0; });
8096 std::sort(LoInputs.begin(), LoInputs.end());
8097 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8098 SmallVector<int, 4> HiInputs;
8099 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8100 [](int M) { return M >= 0; });
8101 std::sort(HiInputs.begin(), HiInputs.end());
8102 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8104 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8105 int NumHToL = LoInputs.size() - NumLToL;
8107 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8108 int NumHToH = HiInputs.size() - NumLToH;
8109 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8110 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8111 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8112 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8114 // Use dedicated unpack instructions for masks that match their pattern.
8115 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8116 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8117 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8118 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8120 // Try to use rotation instructions if available.
8121 if (Subtarget->hasSSSE3())
8122 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8123 DL, MVT::v8i16, V, V, Mask, DAG))
8126 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8127 // such inputs we can swap two of the dwords across the half mark and end up
8128 // with <=2 inputs to each half in each half. Once there, we can fall through
8129 // to the generic code below. For example:
8131 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8132 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8134 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8135 // and an existing 2-into-2 on the other half. In this case we may have to
8136 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8137 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8138 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8139 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8140 // half than the one we target for fixing) will be fixed when we re-enter this
8141 // path. We will also combine away any sequence of PSHUFD instructions that
8142 // result into a single instruction. Here is an example of the tricky case:
8144 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8145 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8147 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8149 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8150 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8152 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8153 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8155 // The result is fine to be handled by the generic logic.
8156 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8157 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8158 int AOffset, int BOffset) {
8159 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8160 "Must call this with A having 3 or 1 inputs from the A half.");
8161 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8162 "Must call this with B having 1 or 3 inputs from the B half.");
8163 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8164 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8166 // Compute the index of dword with only one word among the three inputs in
8167 // a half by taking the sum of the half with three inputs and subtracting
8168 // the sum of the actual three inputs. The difference is the remaining
8171 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8172 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8173 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8174 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8175 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8176 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8177 int TripleNonInputIdx =
8178 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8179 TripleDWord = TripleNonInputIdx / 2;
8181 // We use xor with one to compute the adjacent DWord to whichever one the
8183 OneInputDWord = (OneInput / 2) ^ 1;
8185 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8186 // and BToA inputs. If there is also such a problem with the BToB and AToB
8187 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8188 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8189 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8190 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8191 // Compute how many inputs will be flipped by swapping these DWords. We
8193 // to balance this to ensure we don't form a 3-1 shuffle in the other
8195 int NumFlippedAToBInputs =
8196 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8197 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8198 int NumFlippedBToBInputs =
8199 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8200 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8201 if ((NumFlippedAToBInputs == 1 &&
8202 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8203 (NumFlippedBToBInputs == 1 &&
8204 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8205 // We choose whether to fix the A half or B half based on whether that
8206 // half has zero flipped inputs. At zero, we may not be able to fix it
8207 // with that half. We also bias towards fixing the B half because that
8208 // will more commonly be the high half, and we have to bias one way.
8209 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8210 ArrayRef<int> Inputs) {
8211 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8212 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8213 PinnedIdx ^ 1) != Inputs.end();
8214 // Determine whether the free index is in the flipped dword or the
8215 // unflipped dword based on where the pinned index is. We use this bit
8216 // in an xor to conditionally select the adjacent dword.
8217 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8218 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8219 FixFreeIdx) != Inputs.end();
8220 if (IsFixIdxInput == IsFixFreeIdxInput)
8222 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8223 FixFreeIdx) != Inputs.end();
8224 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8225 "We need to be changing the number of flipped inputs!");
8226 int PSHUFHalfMask[] = {0, 1, 2, 3};
8227 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8228 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8230 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8233 if (M != -1 && M == FixIdx)
8235 else if (M != -1 && M == FixFreeIdx)
8238 if (NumFlippedBToBInputs != 0) {
8240 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8241 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8243 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8245 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8246 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8251 int PSHUFDMask[] = {0, 1, 2, 3};
8252 PSHUFDMask[ADWord] = BDWord;
8253 PSHUFDMask[BDWord] = ADWord;
8254 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8255 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8256 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8257 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8259 // Adjust the mask to match the new locations of A and B.
8261 if (M != -1 && M/2 == ADWord)
8262 M = 2 * BDWord + M % 2;
8263 else if (M != -1 && M/2 == BDWord)
8264 M = 2 * ADWord + M % 2;
8266 // Recurse back into this routine to re-compute state now that this isn't
8267 // a 3 and 1 problem.
8268 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8271 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8272 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8273 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8274 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8276 // At this point there are at most two inputs to the low and high halves from
8277 // each half. That means the inputs can always be grouped into dwords and
8278 // those dwords can then be moved to the correct half with a dword shuffle.
8279 // We use at most one low and one high word shuffle to collect these paired
8280 // inputs into dwords, and finally a dword shuffle to place them.
8281 int PSHUFLMask[4] = {-1, -1, -1, -1};
8282 int PSHUFHMask[4] = {-1, -1, -1, -1};
8283 int PSHUFDMask[4] = {-1, -1, -1, -1};
8285 // First fix the masks for all the inputs that are staying in their
8286 // original halves. This will then dictate the targets of the cross-half
8288 auto fixInPlaceInputs =
8289 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8290 MutableArrayRef<int> SourceHalfMask,
8291 MutableArrayRef<int> HalfMask, int HalfOffset) {
8292 if (InPlaceInputs.empty())
8294 if (InPlaceInputs.size() == 1) {
8295 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8296 InPlaceInputs[0] - HalfOffset;
8297 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8300 if (IncomingInputs.empty()) {
8301 // Just fix all of the in place inputs.
8302 for (int Input : InPlaceInputs) {
8303 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8304 PSHUFDMask[Input / 2] = Input / 2;
8309 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8310 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8311 InPlaceInputs[0] - HalfOffset;
8312 // Put the second input next to the first so that they are packed into
8313 // a dword. We find the adjacent index by toggling the low bit.
8314 int AdjIndex = InPlaceInputs[0] ^ 1;
8315 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8316 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8317 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8319 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8320 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8322 // Now gather the cross-half inputs and place them into a free dword of
8323 // their target half.
8324 // FIXME: This operation could almost certainly be simplified dramatically to
8325 // look more like the 3-1 fixing operation.
8326 auto moveInputsToRightHalf = [&PSHUFDMask](
8327 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8328 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8329 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8331 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8332 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8334 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8336 int LowWord = Word & ~1;
8337 int HighWord = Word | 1;
8338 return isWordClobbered(SourceHalfMask, LowWord) ||
8339 isWordClobbered(SourceHalfMask, HighWord);
8342 if (IncomingInputs.empty())
8345 if (ExistingInputs.empty()) {
8346 // Map any dwords with inputs from them into the right half.
8347 for (int Input : IncomingInputs) {
8348 // If the source half mask maps over the inputs, turn those into
8349 // swaps and use the swapped lane.
8350 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8351 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8352 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8353 Input - SourceOffset;
8354 // We have to swap the uses in our half mask in one sweep.
8355 for (int &M : HalfMask)
8356 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8358 else if (M == Input)
8359 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8361 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8362 Input - SourceOffset &&
8363 "Previous placement doesn't match!");
8365 // Note that this correctly re-maps both when we do a swap and when
8366 // we observe the other side of the swap above. We rely on that to
8367 // avoid swapping the members of the input list directly.
8368 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8371 // Map the input's dword into the correct half.
8372 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8373 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8375 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8377 "Previous placement doesn't match!");
8380 // And just directly shift any other-half mask elements to be same-half
8381 // as we will have mirrored the dword containing the element into the
8382 // same position within that half.
8383 for (int &M : HalfMask)
8384 if (M >= SourceOffset && M < SourceOffset + 4) {
8385 M = M - SourceOffset + DestOffset;
8386 assert(M >= 0 && "This should never wrap below zero!");
8391 // Ensure we have the input in a viable dword of its current half. This
8392 // is particularly tricky because the original position may be clobbered
8393 // by inputs being moved and *staying* in that half.
8394 if (IncomingInputs.size() == 1) {
8395 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8396 int InputFixed = std::find(std::begin(SourceHalfMask),
8397 std::end(SourceHalfMask), -1) -
8398 std::begin(SourceHalfMask) + SourceOffset;
8399 SourceHalfMask[InputFixed - SourceOffset] =
8400 IncomingInputs[0] - SourceOffset;
8401 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8403 IncomingInputs[0] = InputFixed;
8405 } else if (IncomingInputs.size() == 2) {
8406 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8407 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8408 // We have two non-adjacent or clobbered inputs we need to extract from
8409 // the source half. To do this, we need to map them into some adjacent
8410 // dword slot in the source mask.
8411 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8412 IncomingInputs[1] - SourceOffset};
8414 // If there is a free slot in the source half mask adjacent to one of
8415 // the inputs, place the other input in it. We use (Index XOR 1) to
8416 // compute an adjacent index.
8417 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8418 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8419 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8420 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8421 InputsFixed[1] = InputsFixed[0] ^ 1;
8422 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8423 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8424 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8425 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8426 InputsFixed[0] = InputsFixed[1] ^ 1;
8427 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8428 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8429 // The two inputs are in the same DWord but it is clobbered and the
8430 // adjacent DWord isn't used at all. Move both inputs to the free
8432 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8433 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8434 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8435 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8437 // The only way we hit this point is if there is no clobbering
8438 // (because there are no off-half inputs to this half) and there is no
8439 // free slot adjacent to one of the inputs. In this case, we have to
8440 // swap an input with a non-input.
8441 for (int i = 0; i < 4; ++i)
8442 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8443 "We can't handle any clobbers here!");
8444 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8445 "Cannot have adjacent inputs here!");
8447 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8448 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8450 // We also have to update the final source mask in this case because
8451 // it may need to undo the above swap.
8452 for (int &M : FinalSourceHalfMask)
8453 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8454 M = InputsFixed[1] + SourceOffset;
8455 else if (M == InputsFixed[1] + SourceOffset)
8456 M = (InputsFixed[0] ^ 1) + SourceOffset;
8458 InputsFixed[1] = InputsFixed[0] ^ 1;
8461 // Point everything at the fixed inputs.
8462 for (int &M : HalfMask)
8463 if (M == IncomingInputs[0])
8464 M = InputsFixed[0] + SourceOffset;
8465 else if (M == IncomingInputs[1])
8466 M = InputsFixed[1] + SourceOffset;
8468 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8469 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8472 llvm_unreachable("Unhandled input size!");
8475 // Now hoist the DWord down to the right half.
8476 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8477 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8478 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8479 for (int &M : HalfMask)
8480 for (int Input : IncomingInputs)
8482 M = FreeDWord * 2 + Input % 2;
8484 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8485 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8486 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8487 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8489 // Now enact all the shuffles we've computed to move the inputs into their
8491 if (!isNoopShuffleMask(PSHUFLMask))
8492 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8493 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8494 if (!isNoopShuffleMask(PSHUFHMask))
8495 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8496 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8497 if (!isNoopShuffleMask(PSHUFDMask))
8498 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8499 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8500 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8501 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8503 // At this point, each half should contain all its inputs, and we can then
8504 // just shuffle them into their final position.
8505 assert(std::count_if(LoMask.begin(), LoMask.end(),
8506 [](int M) { return M >= 4; }) == 0 &&
8507 "Failed to lift all the high half inputs to the low mask!");
8508 assert(std::count_if(HiMask.begin(), HiMask.end(),
8509 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8510 "Failed to lift all the low half inputs to the high mask!");
8512 // Do a half shuffle for the low mask.
8513 if (!isNoopShuffleMask(LoMask))
8514 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8515 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8517 // Do a half shuffle with the high mask after shifting its values down.
8518 for (int &M : HiMask)
8521 if (!isNoopShuffleMask(HiMask))
8522 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8523 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8528 /// \brief Detect whether the mask pattern should be lowered through
8531 /// This essentially tests whether viewing the mask as an interleaving of two
8532 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8533 /// lowering it through interleaving is a significantly better strategy.
8534 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8535 int NumEvenInputs[2] = {0, 0};
8536 int NumOddInputs[2] = {0, 0};
8537 int NumLoInputs[2] = {0, 0};
8538 int NumHiInputs[2] = {0, 0};
8539 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8543 int InputIdx = Mask[i] >= Size;
8546 ++NumLoInputs[InputIdx];
8548 ++NumHiInputs[InputIdx];
8551 ++NumEvenInputs[InputIdx];
8553 ++NumOddInputs[InputIdx];
8556 // The minimum number of cross-input results for both the interleaved and
8557 // split cases. If interleaving results in fewer cross-input results, return
8559 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8560 NumEvenInputs[0] + NumOddInputs[1]);
8561 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8562 NumLoInputs[0] + NumHiInputs[1]);
8563 return InterleavedCrosses < SplitCrosses;
8566 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8568 /// This strategy only works when the inputs from each vector fit into a single
8569 /// half of that vector, and generally there are not so many inputs as to leave
8570 /// the in-place shuffles required highly constrained (and thus expensive). It
8571 /// shifts all the inputs into a single side of both input vectors and then
8572 /// uses an unpack to interleave these inputs in a single vector. At that
8573 /// point, we will fall back on the generic single input shuffle lowering.
8574 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8576 MutableArrayRef<int> Mask,
8577 const X86Subtarget *Subtarget,
8578 SelectionDAG &DAG) {
8579 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8580 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8581 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8582 for (int i = 0; i < 8; ++i)
8583 if (Mask[i] >= 0 && Mask[i] < 4)
8584 LoV1Inputs.push_back(i);
8585 else if (Mask[i] >= 4 && Mask[i] < 8)
8586 HiV1Inputs.push_back(i);
8587 else if (Mask[i] >= 8 && Mask[i] < 12)
8588 LoV2Inputs.push_back(i);
8589 else if (Mask[i] >= 12)
8590 HiV2Inputs.push_back(i);
8592 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8593 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8596 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8597 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8598 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8600 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8601 HiV1Inputs.size() + HiV2Inputs.size();
8603 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8604 ArrayRef<int> HiInputs, bool MoveToLo,
8606 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8607 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8608 if (BadInputs.empty())
8611 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8612 int MoveOffset = MoveToLo ? 0 : 4;
8614 if (GoodInputs.empty()) {
8615 for (int BadInput : BadInputs) {
8616 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8617 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8620 if (GoodInputs.size() == 2) {
8621 // If the low inputs are spread across two dwords, pack them into
8623 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8624 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8625 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8626 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8628 // Otherwise pin the good inputs.
8629 for (int GoodInput : GoodInputs)
8630 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8633 if (BadInputs.size() == 2) {
8634 // If we have two bad inputs then there may be either one or two good
8635 // inputs fixed in place. Find a fixed input, and then find the *other*
8636 // two adjacent indices by using modular arithmetic.
8638 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8639 [](int M) { return M >= 0; }) -
8640 std::begin(MoveMask);
8642 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8643 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8644 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8645 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8646 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8647 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8648 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8650 assert(BadInputs.size() == 1 && "All sizes handled");
8651 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8652 std::end(MoveMask), -1) -
8653 std::begin(MoveMask);
8654 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8655 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8659 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8662 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8664 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8667 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8668 // cross-half traffic in the final shuffle.
8670 // Munge the mask to be a single-input mask after the unpack merges the
8674 M = 2 * (M % 4) + (M / 8);
8676 return DAG.getVectorShuffle(
8677 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8678 DL, MVT::v8i16, V1, V2),
8679 DAG.getUNDEF(MVT::v8i16), Mask);
8682 /// \brief Generic lowering of 8-lane i16 shuffles.
8684 /// This handles both single-input shuffles and combined shuffle/blends with
8685 /// two inputs. The single input shuffles are immediately delegated to
8686 /// a dedicated lowering routine.
8688 /// The blends are lowered in one of three fundamental ways. If there are few
8689 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8690 /// of the input is significantly cheaper when lowered as an interleaving of
8691 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8692 /// halves of the inputs separately (making them have relatively few inputs)
8693 /// and then concatenate them.
8694 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8695 const X86Subtarget *Subtarget,
8696 SelectionDAG &DAG) {
8698 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8699 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8700 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8701 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8702 ArrayRef<int> OrigMask = SVOp->getMask();
8703 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8704 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8705 MutableArrayRef<int> Mask(MaskStorage);
8707 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8709 // Whenever we can lower this as a zext, that instruction is strictly faster
8710 // than any alternative.
8711 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8712 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8715 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8716 auto isV2 = [](int M) { return M >= 8; };
8718 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8719 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8721 if (NumV2Inputs == 0)
8722 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8724 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8725 "to be V1-input shuffles.");
8727 // There are special ways we can lower some single-element blends.
8728 if (NumV2Inputs == 1)
8729 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8730 Mask, Subtarget, DAG))
8733 if (Subtarget->hasSSE41())
8734 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8738 // Try to use rotation instructions if available.
8739 if (Subtarget->hasSSSE3())
8740 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8743 if (NumV1Inputs + NumV2Inputs <= 4)
8744 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8746 // Check whether an interleaving lowering is likely to be more efficient.
8747 // This isn't perfect but it is a strong heuristic that tends to work well on
8748 // the kinds of shuffles that show up in practice.
8750 // FIXME: Handle 1x, 2x, and 4x interleaving.
8751 if (shouldLowerAsInterleaving(Mask)) {
8752 // FIXME: Figure out whether we should pack these into the low or high
8755 int EMask[8], OMask[8];
8756 for (int i = 0; i < 4; ++i) {
8757 EMask[i] = Mask[2*i];
8758 OMask[i] = Mask[2*i + 1];
8763 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8764 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8766 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8769 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8770 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8772 for (int i = 0; i < 4; ++i) {
8773 LoBlendMask[i] = Mask[i];
8774 HiBlendMask[i] = Mask[i + 4];
8777 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8778 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8779 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8780 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8782 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8783 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8786 /// \brief Check whether a compaction lowering can be done by dropping even
8787 /// elements and compute how many times even elements must be dropped.
8789 /// This handles shuffles which take every Nth element where N is a power of
8790 /// two. Example shuffle masks:
8792 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8793 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8794 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8795 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8796 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8797 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8799 /// Any of these lanes can of course be undef.
8801 /// This routine only supports N <= 3.
8802 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8805 /// \returns N above, or the number of times even elements must be dropped if
8806 /// there is such a number. Otherwise returns zero.
8807 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8808 // Figure out whether we're looping over two inputs or just one.
8809 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8811 // The modulus for the shuffle vector entries is based on whether this is
8812 // a single input or not.
8813 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8814 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8815 "We should only be called with masks with a power-of-2 size!");
8817 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8819 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8820 // and 2^3 simultaneously. This is because we may have ambiguity with
8821 // partially undef inputs.
8822 bool ViableForN[3] = {true, true, true};
8824 for (int i = 0, e = Mask.size(); i < e; ++i) {
8825 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8830 bool IsAnyViable = false;
8831 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8832 if (ViableForN[j]) {
8835 // The shuffle mask must be equal to (i * 2^N) % M.
8836 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8839 ViableForN[j] = false;
8841 // Early exit if we exhaust the possible powers of two.
8846 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8850 // Return 0 as there is no viable power of two.
8854 /// \brief Generic lowering of v16i8 shuffles.
8856 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8857 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8858 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8859 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8861 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8862 const X86Subtarget *Subtarget,
8863 SelectionDAG &DAG) {
8865 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8866 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8867 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8868 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8869 ArrayRef<int> OrigMask = SVOp->getMask();
8870 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8872 // Try to use rotation instructions if available.
8873 if (Subtarget->hasSSSE3())
8874 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
8878 // Try to use a zext lowering.
8879 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8880 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
8883 int MaskStorage[16] = {
8884 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8885 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8886 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8887 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8888 MutableArrayRef<int> Mask(MaskStorage);
8889 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8890 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8893 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8895 // For single-input shuffles, there are some nicer lowering tricks we can use.
8896 if (NumV2Elements == 0) {
8897 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8898 // Notably, this handles splat and partial-splat shuffles more efficiently.
8899 // However, it only makes sense if the pre-duplication shuffle simplifies
8900 // things significantly. Currently, this means we need to be able to
8901 // express the pre-duplication shuffle as an i16 shuffle.
8903 // FIXME: We should check for other patterns which can be widened into an
8904 // i16 shuffle as well.
8905 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8906 for (int i = 0; i < 16; i += 2)
8907 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8912 auto tryToWidenViaDuplication = [&]() -> SDValue {
8913 if (!canWidenViaDuplication(Mask))
8915 SmallVector<int, 4> LoInputs;
8916 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8917 [](int M) { return M >= 0 && M < 8; });
8918 std::sort(LoInputs.begin(), LoInputs.end());
8919 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8921 SmallVector<int, 4> HiInputs;
8922 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8923 [](int M) { return M >= 8; });
8924 std::sort(HiInputs.begin(), HiInputs.end());
8925 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8928 bool TargetLo = LoInputs.size() >= HiInputs.size();
8929 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8930 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8932 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8933 SmallDenseMap<int, int, 8> LaneMap;
8934 for (int I : InPlaceInputs) {
8935 PreDupI16Shuffle[I/2] = I/2;
8938 int j = TargetLo ? 0 : 4, je = j + 4;
8939 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8940 // Check if j is already a shuffle of this input. This happens when
8941 // there are two adjacent bytes after we move the low one.
8942 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8943 // If we haven't yet mapped the input, search for a slot into which
8945 while (j < je && PreDupI16Shuffle[j] != -1)
8949 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8952 // Map this input with the i16 shuffle.
8953 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8956 // Update the lane map based on the mapping we ended up with.
8957 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8960 ISD::BITCAST, DL, MVT::v16i8,
8961 DAG.getVectorShuffle(MVT::v8i16, DL,
8962 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8963 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8965 // Unpack the bytes to form the i16s that will be shuffled into place.
8966 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8967 MVT::v16i8, V1, V1);
8969 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8970 for (int i = 0; i < 16; i += 2) {
8972 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8973 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8976 ISD::BITCAST, DL, MVT::v16i8,
8977 DAG.getVectorShuffle(MVT::v8i16, DL,
8978 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8979 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8981 if (SDValue V = tryToWidenViaDuplication())
8985 // Check whether an interleaving lowering is likely to be more efficient.
8986 // This isn't perfect but it is a strong heuristic that tends to work well on
8987 // the kinds of shuffles that show up in practice.
8989 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8990 if (shouldLowerAsInterleaving(Mask)) {
8991 // FIXME: Figure out whether we should pack these into the low or high
8994 int EMask[16], OMask[16];
8995 for (int i = 0; i < 8; ++i) {
8996 EMask[i] = Mask[2*i];
8997 OMask[i] = Mask[2*i + 1];
9002 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9003 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9005 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9008 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9009 // with PSHUFB. It is important to do this before we attempt to generate any
9010 // blends but after all of the single-input lowerings. If the single input
9011 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9012 // want to preserve that and we can DAG combine any longer sequences into
9013 // a PSHUFB in the end. But once we start blending from multiple inputs,
9014 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9015 // and there are *very* few patterns that would actually be faster than the
9016 // PSHUFB approach because of its ability to zero lanes.
9018 // FIXME: The only exceptions to the above are blends which are exact
9019 // interleavings with direct instructions supporting them. We currently don't
9020 // handle those well here.
9021 if (Subtarget->hasSSSE3()) {
9024 for (int i = 0; i < 16; ++i)
9025 if (Mask[i] == -1) {
9026 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9028 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9030 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9032 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9033 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9034 if (isSingleInputShuffleMask(Mask))
9035 return V1; // Single inputs are easy.
9037 // Otherwise, blend the two.
9038 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9039 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9040 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9043 // There are special ways we can lower some single-element blends.
9044 if (NumV2Elements == 1)
9045 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9046 Mask, Subtarget, DAG))
9049 // Check whether a compaction lowering can be done. This handles shuffles
9050 // which take every Nth element for some even N. See the helper function for
9053 // We special case these as they can be particularly efficiently handled with
9054 // the PACKUSB instruction on x86 and they show up in common patterns of
9055 // rearranging bytes to truncate wide elements.
9056 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9057 // NumEvenDrops is the power of two stride of the elements. Another way of
9058 // thinking about it is that we need to drop the even elements this many
9059 // times to get the original input.
9060 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9062 // First we need to zero all the dropped bytes.
9063 assert(NumEvenDrops <= 3 &&
9064 "No support for dropping even elements more than 3 times.");
9065 // We use the mask type to pick which bytes are preserved based on how many
9066 // elements are dropped.
9067 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9068 SDValue ByteClearMask =
9069 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9070 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9071 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9073 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9075 // Now pack things back together.
9076 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9077 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9078 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9079 for (int i = 1; i < NumEvenDrops; ++i) {
9080 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9081 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9087 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9088 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9089 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9090 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9092 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9093 MutableArrayRef<int> V1HalfBlendMask,
9094 MutableArrayRef<int> V2HalfBlendMask) {
9095 for (int i = 0; i < 8; ++i)
9096 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9097 V1HalfBlendMask[i] = HalfMask[i];
9099 } else if (HalfMask[i] >= 16) {
9100 V2HalfBlendMask[i] = HalfMask[i] - 16;
9101 HalfMask[i] = i + 8;
9104 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9105 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9107 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9109 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9110 MutableArrayRef<int> HiBlendMask) {
9112 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9113 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9115 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9116 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9117 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9118 [](int M) { return M >= 0 && M % 2 == 1; })) {
9119 // Use a mask to drop the high bytes.
9120 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9121 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9122 DAG.getConstant(0x00FF, MVT::v8i16));
9124 // This will be a single vector shuffle instead of a blend so nuke V2.
9125 V2 = DAG.getUNDEF(MVT::v8i16);
9127 // Squash the masks to point directly into V1.
9128 for (int &M : LoBlendMask)
9131 for (int &M : HiBlendMask)
9135 // Otherwise just unpack the low half of V into V1 and the high half into
9136 // V2 so that we can blend them as i16s.
9137 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9138 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9139 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9140 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9143 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9144 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9145 return std::make_pair(BlendedLo, BlendedHi);
9147 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9148 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9149 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9151 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9152 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9154 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9157 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9159 /// This routine breaks down the specific type of 128-bit shuffle and
9160 /// dispatches to the lowering routines accordingly.
9161 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9162 MVT VT, const X86Subtarget *Subtarget,
9163 SelectionDAG &DAG) {
9164 switch (VT.SimpleTy) {
9166 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9168 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9170 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9172 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9174 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9176 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9179 llvm_unreachable("Unimplemented!");
9183 /// \brief Test whether there are elements crossing 128-bit lanes in this
9186 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
9187 /// and we routinely test for these.
9188 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
9189 int LaneSize = 128 / VT.getScalarSizeInBits();
9190 int Size = Mask.size();
9191 for (int i = 0; i < Size; ++i)
9192 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9197 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
9199 /// This checks a shuffle mask to see if it is performing the same
9200 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
9201 /// that it is also not lane-crossing.
9202 static bool is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask) {
9203 int LaneSize = 128 / VT.getScalarSizeInBits();
9204 int Size = Mask.size();
9205 for (int i = LaneSize; i < Size; ++i)
9206 if (Mask[i] >= 0 && Mask[i] != (Mask[i % LaneSize] + (i / LaneSize) * LaneSize))
9211 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9214 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9215 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9216 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9217 /// we encode the logic here for specific shuffle lowering routines to bail to
9218 /// when they exhaust the features avaible to more directly handle the shuffle.
9219 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
9221 const X86Subtarget *Subtarget,
9222 SelectionDAG &DAG) {
9224 MVT VT = Op.getSimpleValueType();
9225 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9226 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9227 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9228 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9229 ArrayRef<int> Mask = SVOp->getMask();
9231 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9232 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9234 int NumElements = VT.getVectorNumElements();
9235 int SplitNumElements = NumElements / 2;
9236 MVT ScalarVT = VT.getScalarType();
9237 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9239 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9240 DAG.getIntPtrConstant(0));
9241 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9242 DAG.getIntPtrConstant(SplitNumElements));
9243 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9244 DAG.getIntPtrConstant(0));
9245 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9246 DAG.getIntPtrConstant(SplitNumElements));
9248 // Now create two 4-way blends of these half-width vectors.
9249 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9250 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9251 for (int i = 0; i < SplitNumElements; ++i) {
9252 int M = HalfMask[i];
9253 if (M >= NumElements) {
9254 V2BlendMask.push_back(M - NumElements);
9255 V1BlendMask.push_back(-1);
9256 BlendMask.push_back(SplitNumElements + i);
9257 } else if (M >= 0) {
9258 V2BlendMask.push_back(-1);
9259 V1BlendMask.push_back(M);
9260 BlendMask.push_back(i);
9262 V2BlendMask.push_back(-1);
9263 V1BlendMask.push_back(-1);
9264 BlendMask.push_back(-1);
9267 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9268 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9269 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9271 SDValue Lo = HalfBlend(LoMask);
9272 SDValue Hi = HalfBlend(HiMask);
9273 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9276 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9278 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9279 /// isn't available.
9280 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9281 const X86Subtarget *Subtarget,
9282 SelectionDAG &DAG) {
9284 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9285 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9286 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9287 ArrayRef<int> Mask = SVOp->getMask();
9288 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9290 if (is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask))
9291 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9293 if (isSingleInputShuffleMask(Mask)) {
9294 // Non-half-crossing single input shuffles can be lowerid with an
9295 // interleaved permutation.
9296 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9297 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9298 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9299 DAG.getConstant(VPERMILPMask, MVT::i8));
9302 // X86 has dedicated unpack instructions that can handle specific blend
9303 // operations: UNPCKH and UNPCKL.
9304 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9305 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9306 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9307 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9309 // If we have a single input to the zero element, insert that into V1 if we
9310 // can do so cheaply.
9312 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9313 if (NumV2Elements == 1 && Mask[0] >= 4)
9314 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9315 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9318 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9322 // Check if the blend happens to exactly fit that of SHUFPD.
9323 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
9324 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
9325 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9326 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9327 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9328 DAG.getConstant(SHUFPDMask, MVT::i8));
9330 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
9331 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
9332 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9333 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9334 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9335 DAG.getConstant(SHUFPDMask, MVT::i8));
9338 // Shuffle the input elements into the desired positions in V1 and V2 and
9339 // blend them together.
9340 int V1Mask[] = {-1, -1, -1, -1};
9341 int V2Mask[] = {-1, -1, -1, -1};
9342 for (int i = 0; i < 4; ++i)
9343 if (Mask[i] >= 0 && Mask[i] < 4)
9344 V1Mask[i] = Mask[i];
9345 else if (Mask[i] >= 4)
9346 V2Mask[i] = Mask[i] - 4;
9348 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
9349 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
9351 unsigned BlendMask = 0;
9352 for (int i = 0; i < 4; ++i)
9354 BlendMask |= 1 << i;
9356 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
9357 DAG.getConstant(BlendMask, MVT::i8));
9360 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9362 /// This routine is only called when we have AVX2 and thus a reasonable
9363 /// instruction set for v4i64 shuffling..
9364 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9365 const X86Subtarget *Subtarget,
9366 SelectionDAG &DAG) {
9368 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9369 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9371 ArrayRef<int> Mask = SVOp->getMask();
9372 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9373 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9375 // FIXME: Actually implement this using AVX2!!!
9376 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
9377 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
9378 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
9379 DAG.getVectorShuffle(MVT::v4f64, DL, V1, V2, Mask));
9382 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9384 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9385 /// isn't available.
9386 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9387 const X86Subtarget *Subtarget,
9388 SelectionDAG &DAG) {
9390 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9391 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9392 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9393 ArrayRef<int> Mask = SVOp->getMask();
9394 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9396 if (is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9397 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9399 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9403 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9404 // options to efficiently lower the shuffle.
9405 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask)) {
9406 ArrayRef<int> LoMask = Mask.slice(0, 4);
9407 if (isSingleInputShuffleMask(Mask))
9408 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9409 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9411 // Use dedicated unpack instructions for masks that match their pattern.
9412 if (isShuffleEquivalent(LoMask, 0, 8, 1, 9))
9413 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9414 if (isShuffleEquivalent(LoMask, 2, 10, 3, 11))
9415 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9417 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9418 // have already handled any direct blends.
9419 int SHUFPSMask[] = {Mask[0], Mask[1], Mask[2], Mask[3]};
9420 for (int &M : SHUFPSMask)
9423 return lowerVectorShuffleWithSHUPFS(DL, MVT::v8f32, SHUFPSMask, V1, V2, DAG);
9426 // If we have a single input shuffle with different shuffle patterns in the
9427 // two 128-bit lanes use the variable mask to VPERMILPS.
9428 if (isSingleInputShuffleMask(Mask)) {
9429 SDValue VPermMask[8];
9430 for (int i = 0; i < 8; ++i)
9431 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9432 : DAG.getConstant(Mask[i], MVT::i32);
9434 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9435 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9438 // Shuffle the input elements into the desired positions in V1 and V2 and
9439 // blend them together.
9440 int V1Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9441 int V2Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9442 unsigned BlendMask = 0;
9443 for (int i = 0; i < 8; ++i)
9444 if (Mask[i] >= 0 && Mask[i] < 8) {
9445 V1Mask[i] = Mask[i];
9446 } else if (Mask[i] >= 8) {
9447 V2Mask[i] = Mask[i] - 8;
9448 BlendMask |= 1 << i;
9451 V1 = DAG.getVectorShuffle(MVT::v8f32, DL, V1, DAG.getUNDEF(MVT::v8f32), V1Mask);
9452 V2 = DAG.getVectorShuffle(MVT::v8f32, DL, V2, DAG.getUNDEF(MVT::v8f32), V2Mask);
9454 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v8f32, V1, V2,
9455 DAG.getConstant(BlendMask, MVT::i8));
9458 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9460 /// This routine is only called when we have AVX2 and thus a reasonable
9461 /// instruction set for v8i32 shuffling..
9462 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9463 const X86Subtarget *Subtarget,
9464 SelectionDAG &DAG) {
9466 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9467 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9468 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9469 ArrayRef<int> Mask = SVOp->getMask();
9470 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9471 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9473 // FIXME: Actually implement this using AVX2!!!
9474 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8f32, V1);
9475 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8f32, V2);
9476 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i32,
9477 DAG.getVectorShuffle(MVT::v8f32, DL, V1, V2, Mask));
9480 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9482 /// This routine is only called when we have AVX2 and thus a reasonable
9483 /// instruction set for v16i16 shuffling..
9484 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9485 const X86Subtarget *Subtarget,
9486 SelectionDAG &DAG) {
9488 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9489 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9490 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9491 ArrayRef<int> Mask = SVOp->getMask();
9492 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9493 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9495 // FIXME: Actually implement this using AVX2!!!
9497 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9500 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9502 /// This routine is only called when we have AVX2 and thus a reasonable
9503 /// instruction set for v32i8 shuffling..
9504 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9505 const X86Subtarget *Subtarget,
9506 SelectionDAG &DAG) {
9508 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9509 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9510 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9511 ArrayRef<int> Mask = SVOp->getMask();
9512 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9513 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9515 // FIXME: Actually implement this using AVX2!!!
9517 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9520 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9522 /// This routine either breaks down the specific type of a 256-bit x86 vector
9523 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9524 /// together based on the available instructions.
9525 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9526 MVT VT, const X86Subtarget *Subtarget,
9527 SelectionDAG &DAG) {
9529 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9530 ArrayRef<int> Mask = SVOp->getMask();
9532 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9533 // check for those subtargets here and avoid much of the subtarget querying in
9534 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9535 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9536 // floating point types there eventually, just immediately cast everything to
9537 // a float and operate entirely in that domain.
9538 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9539 int ElementBits = VT.getScalarSizeInBits();
9540 if (ElementBits < 32)
9541 // No floating point type available, decompose into 128-bit vectors.
9542 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9544 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9545 VT.getVectorNumElements());
9546 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9547 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9548 return DAG.getNode(ISD::BITCAST, DL, VT,
9549 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9552 switch (VT.SimpleTy) {
9554 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9556 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9558 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9560 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9562 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9564 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9567 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9571 /// \brief Tiny helper function to test whether a shuffle mask could be
9572 /// simplified by widening the elements being shuffled.
9573 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9574 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9575 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9576 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9577 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9583 /// \brief Top-level lowering for x86 vector shuffles.
9585 /// This handles decomposition, canonicalization, and lowering of all x86
9586 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9587 /// above in helper routines. The canonicalization attempts to widen shuffles
9588 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9589 /// s.t. only one of the two inputs needs to be tested, etc.
9590 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9591 SelectionDAG &DAG) {
9592 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9593 ArrayRef<int> Mask = SVOp->getMask();
9594 SDValue V1 = Op.getOperand(0);
9595 SDValue V2 = Op.getOperand(1);
9596 MVT VT = Op.getSimpleValueType();
9597 int NumElements = VT.getVectorNumElements();
9600 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9602 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9603 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9604 if (V1IsUndef && V2IsUndef)
9605 return DAG.getUNDEF(VT);
9607 // When we create a shuffle node we put the UNDEF node to second operand,
9608 // but in some cases the first operand may be transformed to UNDEF.
9609 // In this case we should just commute the node.
9611 return DAG.getCommutedVectorShuffle(*SVOp);
9613 // Check for non-undef masks pointing at an undef vector and make the masks
9614 // undef as well. This makes it easier to match the shuffle based solely on
9618 if (M >= NumElements) {
9619 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9620 for (int &M : NewMask)
9621 if (M >= NumElements)
9623 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9626 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9627 // lanes but wider integers. We cap this to not form integers larger than i64
9628 // but it might be interesting to form i128 integers to handle flipping the
9629 // low and high halves of AVX 256-bit vectors.
9630 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9631 canWidenShuffleElements(Mask)) {
9632 SmallVector<int, 8> NewMask;
9633 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9634 NewMask.push_back(Mask[i] != -1
9636 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9638 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9639 VT.getVectorNumElements() / 2);
9640 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9641 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9642 return DAG.getNode(ISD::BITCAST, dl, VT,
9643 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9646 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9647 for (int M : SVOp->getMask())
9650 else if (M < NumElements)
9655 // Commute the shuffle as needed such that more elements come from V1 than
9656 // V2. This allows us to match the shuffle pattern strictly on how many
9657 // elements come from V1 without handling the symmetric cases.
9658 if (NumV2Elements > NumV1Elements)
9659 return DAG.getCommutedVectorShuffle(*SVOp);
9661 // When the number of V1 and V2 elements are the same, try to minimize the
9662 // number of uses of V2 in the low half of the vector. When that is tied,
9663 // ensure that the sum of indices for V1 is equal to or lower than the sum
9665 if (NumV1Elements == NumV2Elements) {
9666 int LowV1Elements = 0, LowV2Elements = 0;
9667 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9668 if (M >= NumElements)
9672 if (LowV2Elements > LowV1Elements)
9673 return DAG.getCommutedVectorShuffle(*SVOp);
9675 int SumV1Indices = 0, SumV2Indices = 0;
9676 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
9677 if (SVOp->getMask()[i] >= NumElements)
9679 else if (SVOp->getMask()[i] >= 0)
9681 if (SumV2Indices < SumV1Indices)
9682 return DAG.getCommutedVectorShuffle(*SVOp);
9685 // For each vector width, delegate to a specialized lowering routine.
9686 if (VT.getSizeInBits() == 128)
9687 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9689 if (VT.getSizeInBits() == 256)
9690 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9692 llvm_unreachable("Unimplemented!");
9696 //===----------------------------------------------------------------------===//
9697 // Legacy vector shuffle lowering
9699 // This code is the legacy code handling vector shuffles until the above
9700 // replaces its functionality and performance.
9701 //===----------------------------------------------------------------------===//
9703 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9704 bool hasInt256, unsigned *MaskOut = nullptr) {
9705 MVT EltVT = VT.getVectorElementType();
9707 // There is no blend with immediate in AVX-512.
9708 if (VT.is512BitVector())
9711 if (!hasSSE41 || EltVT == MVT::i8)
9713 if (!hasInt256 && VT == MVT::v16i16)
9716 unsigned MaskValue = 0;
9717 unsigned NumElems = VT.getVectorNumElements();
9718 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9719 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9720 unsigned NumElemsInLane = NumElems / NumLanes;
9722 // Blend for v16i16 should be symetric for the both lanes.
9723 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9725 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9726 int EltIdx = MaskVals[i];
9728 if ((EltIdx < 0 || EltIdx == (int)i) &&
9729 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9732 if (((unsigned)EltIdx == (i + NumElems)) &&
9733 (SndLaneEltIdx < 0 ||
9734 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9735 MaskValue |= (1 << i);
9741 *MaskOut = MaskValue;
9745 // Try to lower a shuffle node into a simple blend instruction.
9746 // This function assumes isBlendMask returns true for this
9747 // SuffleVectorSDNode
9748 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9750 const X86Subtarget *Subtarget,
9751 SelectionDAG &DAG) {
9752 MVT VT = SVOp->getSimpleValueType(0);
9753 MVT EltVT = VT.getVectorElementType();
9754 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9755 Subtarget->hasInt256() && "Trying to lower a "
9756 "VECTOR_SHUFFLE to a Blend but "
9757 "with the wrong mask"));
9758 SDValue V1 = SVOp->getOperand(0);
9759 SDValue V2 = SVOp->getOperand(1);
9761 unsigned NumElems = VT.getVectorNumElements();
9763 // Convert i32 vectors to floating point if it is not AVX2.
9764 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9766 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9767 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9769 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
9770 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
9773 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
9774 DAG.getConstant(MaskValue, MVT::i32));
9775 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9778 /// In vector type \p VT, return true if the element at index \p InputIdx
9779 /// falls on a different 128-bit lane than \p OutputIdx.
9780 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
9781 unsigned OutputIdx) {
9782 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
9783 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
9786 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
9787 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
9788 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
9789 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
9791 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
9792 SelectionDAG &DAG) {
9793 MVT VT = V1.getSimpleValueType();
9794 assert(VT.is128BitVector() || VT.is256BitVector());
9796 MVT EltVT = VT.getVectorElementType();
9797 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
9798 unsigned NumElts = VT.getVectorNumElements();
9800 SmallVector<SDValue, 32> PshufbMask;
9801 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
9802 int InputIdx = MaskVals[OutputIdx];
9803 unsigned InputByteIdx;
9805 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
9806 InputByteIdx = 0x80;
9808 // Cross lane is not allowed.
9809 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
9811 InputByteIdx = InputIdx * EltSizeInBytes;
9812 // Index is an byte offset within the 128-bit lane.
9813 InputByteIdx &= 0xf;
9816 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
9817 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
9818 if (InputByteIdx != 0x80)
9823 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
9825 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
9826 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
9827 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
9830 // v8i16 shuffles - Prefer shuffles in the following order:
9831 // 1. [all] pshuflw, pshufhw, optional move
9832 // 2. [ssse3] 1 x pshufb
9833 // 3. [ssse3] 2 x pshufb + 1 x por
9834 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
9836 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
9837 SelectionDAG &DAG) {
9838 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9839 SDValue V1 = SVOp->getOperand(0);
9840 SDValue V2 = SVOp->getOperand(1);
9842 SmallVector<int, 8> MaskVals;
9844 // Determine if more than 1 of the words in each of the low and high quadwords
9845 // of the result come from the same quadword of one of the two inputs. Undef
9846 // mask values count as coming from any quadword, for better codegen.
9848 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
9849 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
9850 unsigned LoQuad[] = { 0, 0, 0, 0 };
9851 unsigned HiQuad[] = { 0, 0, 0, 0 };
9852 // Indices of quads used.
9853 std::bitset<4> InputQuads;
9854 for (unsigned i = 0; i < 8; ++i) {
9855 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
9856 int EltIdx = SVOp->getMaskElt(i);
9857 MaskVals.push_back(EltIdx);
9866 InputQuads.set(EltIdx / 4);
9869 int BestLoQuad = -1;
9870 unsigned MaxQuad = 1;
9871 for (unsigned i = 0; i < 4; ++i) {
9872 if (LoQuad[i] > MaxQuad) {
9874 MaxQuad = LoQuad[i];
9878 int BestHiQuad = -1;
9880 for (unsigned i = 0; i < 4; ++i) {
9881 if (HiQuad[i] > MaxQuad) {
9883 MaxQuad = HiQuad[i];
9887 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
9888 // of the two input vectors, shuffle them into one input vector so only a
9889 // single pshufb instruction is necessary. If there are more than 2 input
9890 // quads, disable the next transformation since it does not help SSSE3.
9891 bool V1Used = InputQuads[0] || InputQuads[1];
9892 bool V2Used = InputQuads[2] || InputQuads[3];
9893 if (Subtarget->hasSSSE3()) {
9894 if (InputQuads.count() == 2 && V1Used && V2Used) {
9895 BestLoQuad = InputQuads[0] ? 0 : 1;
9896 BestHiQuad = InputQuads[2] ? 2 : 3;
9898 if (InputQuads.count() > 2) {
9904 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
9905 // the shuffle mask. If a quad is scored as -1, that means that it contains
9906 // words from all 4 input quadwords.
9908 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
9910 BestLoQuad < 0 ? 0 : BestLoQuad,
9911 BestHiQuad < 0 ? 1 : BestHiQuad
9913 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
9914 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
9915 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
9916 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
9918 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
9919 // source words for the shuffle, to aid later transformations.
9920 bool AllWordsInNewV = true;
9921 bool InOrder[2] = { true, true };
9922 for (unsigned i = 0; i != 8; ++i) {
9923 int idx = MaskVals[i];
9925 InOrder[i/4] = false;
9926 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
9928 AllWordsInNewV = false;
9932 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
9933 if (AllWordsInNewV) {
9934 for (int i = 0; i != 8; ++i) {
9935 int idx = MaskVals[i];
9938 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
9939 if ((idx != i) && idx < 4)
9941 if ((idx != i) && idx > 3)
9950 // If we've eliminated the use of V2, and the new mask is a pshuflw or
9951 // pshufhw, that's as cheap as it gets. Return the new shuffle.
9952 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
9953 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
9954 unsigned TargetMask = 0;
9955 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
9956 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
9957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9958 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
9959 getShufflePSHUFLWImmediate(SVOp);
9960 V1 = NewV.getOperand(0);
9961 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
9965 // Promote splats to a larger type which usually leads to more efficient code.
9966 // FIXME: Is this true if pshufb is available?
9967 if (SVOp->isSplat())
9968 return PromoteSplat(SVOp, DAG);
9970 // If we have SSSE3, and all words of the result are from 1 input vector,
9971 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
9972 // is present, fall back to case 4.
9973 if (Subtarget->hasSSSE3()) {
9974 SmallVector<SDValue,16> pshufbMask;
9976 // If we have elements from both input vectors, set the high bit of the
9977 // shuffle mask element to zero out elements that come from V2 in the V1
9978 // mask, and elements that come from V1 in the V2 mask, so that the two
9979 // results can be OR'd together.
9980 bool TwoInputs = V1Used && V2Used;
9981 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
9983 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9985 // Calculate the shuffle mask for the second input, shuffle it, and
9986 // OR it with the first shuffled input.
9987 CommuteVectorShuffleMask(MaskVals, 8);
9988 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
9989 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9990 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9993 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
9994 // and update MaskVals with new element order.
9995 std::bitset<8> InOrder;
9996 if (BestLoQuad >= 0) {
9997 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
9998 for (int i = 0; i != 4; ++i) {
9999 int idx = MaskVals[i];
10002 } else if ((idx / 4) == BestLoQuad) {
10003 MaskV[i] = idx & 3;
10007 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10010 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10011 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10012 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10013 NewV.getOperand(0),
10014 getShufflePSHUFLWImmediate(SVOp), DAG);
10018 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10019 // and update MaskVals with the new element order.
10020 if (BestHiQuad >= 0) {
10021 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10022 for (unsigned i = 4; i != 8; ++i) {
10023 int idx = MaskVals[i];
10026 } else if ((idx / 4) == BestHiQuad) {
10027 MaskV[i] = (idx & 3) + 4;
10031 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10034 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10035 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10036 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10037 NewV.getOperand(0),
10038 getShufflePSHUFHWImmediate(SVOp), DAG);
10042 // In case BestHi & BestLo were both -1, which means each quadword has a word
10043 // from each of the four input quadwords, calculate the InOrder bitvector now
10044 // before falling through to the insert/extract cleanup.
10045 if (BestLoQuad == -1 && BestHiQuad == -1) {
10047 for (int i = 0; i != 8; ++i)
10048 if (MaskVals[i] < 0 || MaskVals[i] == i)
10052 // The other elements are put in the right place using pextrw and pinsrw.
10053 for (unsigned i = 0; i != 8; ++i) {
10056 int EltIdx = MaskVals[i];
10059 SDValue ExtOp = (EltIdx < 8) ?
10060 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10061 DAG.getIntPtrConstant(EltIdx)) :
10062 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10063 DAG.getIntPtrConstant(EltIdx - 8));
10064 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10065 DAG.getIntPtrConstant(i));
10070 /// \brief v16i16 shuffles
10072 /// FIXME: We only support generation of a single pshufb currently. We can
10073 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10074 /// well (e.g 2 x pshufb + 1 x por).
10076 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10077 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10078 SDValue V1 = SVOp->getOperand(0);
10079 SDValue V2 = SVOp->getOperand(1);
10082 if (V2.getOpcode() != ISD::UNDEF)
10085 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10086 return getPSHUFB(MaskVals, V1, dl, DAG);
10089 // v16i8 shuffles - Prefer shuffles in the following order:
10090 // 1. [ssse3] 1 x pshufb
10091 // 2. [ssse3] 2 x pshufb + 1 x por
10092 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10093 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10094 const X86Subtarget* Subtarget,
10095 SelectionDAG &DAG) {
10096 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10097 SDValue V1 = SVOp->getOperand(0);
10098 SDValue V2 = SVOp->getOperand(1);
10100 ArrayRef<int> MaskVals = SVOp->getMask();
10102 // Promote splats to a larger type which usually leads to more efficient code.
10103 // FIXME: Is this true if pshufb is available?
10104 if (SVOp->isSplat())
10105 return PromoteSplat(SVOp, DAG);
10107 // If we have SSSE3, case 1 is generated when all result bytes come from
10108 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10109 // present, fall back to case 3.
10111 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10112 if (Subtarget->hasSSSE3()) {
10113 SmallVector<SDValue,16> pshufbMask;
10115 // If all result elements are from one input vector, then only translate
10116 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10118 // Otherwise, we have elements from both input vectors, and must zero out
10119 // elements that come from V2 in the first mask, and V1 in the second mask
10120 // so that we can OR them together.
10121 for (unsigned i = 0; i != 16; ++i) {
10122 int EltIdx = MaskVals[i];
10123 if (EltIdx < 0 || EltIdx >= 16)
10125 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10127 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10128 DAG.getNode(ISD::BUILD_VECTOR, dl,
10129 MVT::v16i8, pshufbMask));
10131 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10132 // the 2nd operand if it's undefined or zero.
10133 if (V2.getOpcode() == ISD::UNDEF ||
10134 ISD::isBuildVectorAllZeros(V2.getNode()))
10137 // Calculate the shuffle mask for the second input, shuffle it, and
10138 // OR it with the first shuffled input.
10139 pshufbMask.clear();
10140 for (unsigned i = 0; i != 16; ++i) {
10141 int EltIdx = MaskVals[i];
10142 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10143 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10145 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10146 DAG.getNode(ISD::BUILD_VECTOR, dl,
10147 MVT::v16i8, pshufbMask));
10148 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10151 // No SSSE3 - Calculate in place words and then fix all out of place words
10152 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10153 // the 16 different words that comprise the two doublequadword input vectors.
10154 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10155 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10157 for (int i = 0; i != 8; ++i) {
10158 int Elt0 = MaskVals[i*2];
10159 int Elt1 = MaskVals[i*2+1];
10161 // This word of the result is all undef, skip it.
10162 if (Elt0 < 0 && Elt1 < 0)
10165 // This word of the result is already in the correct place, skip it.
10166 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10169 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10170 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10173 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10174 // using a single extract together, load it and store it.
10175 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10176 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10177 DAG.getIntPtrConstant(Elt1 / 2));
10178 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10179 DAG.getIntPtrConstant(i));
10183 // If Elt1 is defined, extract it from the appropriate source. If the
10184 // source byte is not also odd, shift the extracted word left 8 bits
10185 // otherwise clear the bottom 8 bits if we need to do an or.
10187 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10188 DAG.getIntPtrConstant(Elt1 / 2));
10189 if ((Elt1 & 1) == 0)
10190 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10192 TLI.getShiftAmountTy(InsElt.getValueType())));
10193 else if (Elt0 >= 0)
10194 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10195 DAG.getConstant(0xFF00, MVT::i16));
10197 // If Elt0 is defined, extract it from the appropriate source. If the
10198 // source byte is not also even, shift the extracted word right 8 bits. If
10199 // Elt1 was also defined, OR the extracted values together before
10200 // inserting them in the result.
10202 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10203 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10204 if ((Elt0 & 1) != 0)
10205 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10207 TLI.getShiftAmountTy(InsElt0.getValueType())));
10208 else if (Elt1 >= 0)
10209 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10210 DAG.getConstant(0x00FF, MVT::i16));
10211 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10214 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10215 DAG.getIntPtrConstant(i));
10217 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10220 // v32i8 shuffles - Translate to VPSHUFB if possible.
10222 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10223 const X86Subtarget *Subtarget,
10224 SelectionDAG &DAG) {
10225 MVT VT = SVOp->getSimpleValueType(0);
10226 SDValue V1 = SVOp->getOperand(0);
10227 SDValue V2 = SVOp->getOperand(1);
10229 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10231 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10232 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10233 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10235 // VPSHUFB may be generated if
10236 // (1) one of input vector is undefined or zeroinitializer.
10237 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10238 // And (2) the mask indexes don't cross the 128-bit lane.
10239 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10240 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10243 if (V1IsAllZero && !V2IsAllZero) {
10244 CommuteVectorShuffleMask(MaskVals, 32);
10247 return getPSHUFB(MaskVals, V1, dl, DAG);
10250 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10251 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10252 /// done when every pair / quad of shuffle mask elements point to elements in
10253 /// the right sequence. e.g.
10254 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10256 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10257 SelectionDAG &DAG) {
10258 MVT VT = SVOp->getSimpleValueType(0);
10260 unsigned NumElems = VT.getVectorNumElements();
10263 switch (VT.SimpleTy) {
10264 default: llvm_unreachable("Unexpected!");
10267 return SDValue(SVOp, 0);
10268 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10269 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10270 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10271 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10272 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10273 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10276 SmallVector<int, 8> MaskVec;
10277 for (unsigned i = 0; i != NumElems; i += Scale) {
10279 for (unsigned j = 0; j != Scale; ++j) {
10280 int EltIdx = SVOp->getMaskElt(i+j);
10284 StartIdx = (EltIdx / Scale);
10285 if (EltIdx != (int)(StartIdx*Scale + j))
10288 MaskVec.push_back(StartIdx);
10291 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10292 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10293 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10296 /// getVZextMovL - Return a zero-extending vector move low node.
10298 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10299 SDValue SrcOp, SelectionDAG &DAG,
10300 const X86Subtarget *Subtarget, SDLoc dl) {
10301 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10302 LoadSDNode *LD = nullptr;
10303 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10304 LD = dyn_cast<LoadSDNode>(SrcOp);
10306 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10308 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10309 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10310 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10311 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10312 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10314 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10315 return DAG.getNode(ISD::BITCAST, dl, VT,
10316 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10317 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10319 SrcOp.getOperand(0)
10325 return DAG.getNode(ISD::BITCAST, dl, VT,
10326 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10327 DAG.getNode(ISD::BITCAST, dl,
10331 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10332 /// which could not be matched by any known target speficic shuffle
10334 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10336 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10337 if (NewOp.getNode())
10340 MVT VT = SVOp->getSimpleValueType(0);
10342 unsigned NumElems = VT.getVectorNumElements();
10343 unsigned NumLaneElems = NumElems / 2;
10346 MVT EltVT = VT.getVectorElementType();
10347 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10350 SmallVector<int, 16> Mask;
10351 for (unsigned l = 0; l < 2; ++l) {
10352 // Build a shuffle mask for the output, discovering on the fly which
10353 // input vectors to use as shuffle operands (recorded in InputUsed).
10354 // If building a suitable shuffle vector proves too hard, then bail
10355 // out with UseBuildVector set.
10356 bool UseBuildVector = false;
10357 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10358 unsigned LaneStart = l * NumLaneElems;
10359 for (unsigned i = 0; i != NumLaneElems; ++i) {
10360 // The mask element. This indexes into the input.
10361 int Idx = SVOp->getMaskElt(i+LaneStart);
10363 // the mask element does not index into any input vector.
10364 Mask.push_back(-1);
10368 // The input vector this mask element indexes into.
10369 int Input = Idx / NumLaneElems;
10371 // Turn the index into an offset from the start of the input vector.
10372 Idx -= Input * NumLaneElems;
10374 // Find or create a shuffle vector operand to hold this input.
10376 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10377 if (InputUsed[OpNo] == Input)
10378 // This input vector is already an operand.
10380 if (InputUsed[OpNo] < 0) {
10381 // Create a new operand for this input vector.
10382 InputUsed[OpNo] = Input;
10387 if (OpNo >= array_lengthof(InputUsed)) {
10388 // More than two input vectors used! Give up on trying to create a
10389 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10390 UseBuildVector = true;
10394 // Add the mask index for the new shuffle vector.
10395 Mask.push_back(Idx + OpNo * NumLaneElems);
10398 if (UseBuildVector) {
10399 SmallVector<SDValue, 16> SVOps;
10400 for (unsigned i = 0; i != NumLaneElems; ++i) {
10401 // The mask element. This indexes into the input.
10402 int Idx = SVOp->getMaskElt(i+LaneStart);
10404 SVOps.push_back(DAG.getUNDEF(EltVT));
10408 // The input vector this mask element indexes into.
10409 int Input = Idx / NumElems;
10411 // Turn the index into an offset from the start of the input vector.
10412 Idx -= Input * NumElems;
10414 // Extract the vector element by hand.
10415 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10416 SVOp->getOperand(Input),
10417 DAG.getIntPtrConstant(Idx)));
10420 // Construct the output using a BUILD_VECTOR.
10421 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10422 } else if (InputUsed[0] < 0) {
10423 // No input vectors were used! The result is undefined.
10424 Output[l] = DAG.getUNDEF(NVT);
10426 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10427 (InputUsed[0] % 2) * NumLaneElems,
10429 // If only one input was used, use an undefined vector for the other.
10430 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10431 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10432 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10433 // At least one input vector was used. Create a new shuffle vector.
10434 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10440 // Concatenate the result back
10441 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10444 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10445 /// 4 elements, and match them with several different shuffle types.
10447 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10448 SDValue V1 = SVOp->getOperand(0);
10449 SDValue V2 = SVOp->getOperand(1);
10451 MVT VT = SVOp->getSimpleValueType(0);
10453 assert(VT.is128BitVector() && "Unsupported vector size");
10455 std::pair<int, int> Locs[4];
10456 int Mask1[] = { -1, -1, -1, -1 };
10457 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10459 unsigned NumHi = 0;
10460 unsigned NumLo = 0;
10461 for (unsigned i = 0; i != 4; ++i) {
10462 int Idx = PermMask[i];
10464 Locs[i] = std::make_pair(-1, -1);
10466 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10468 Locs[i] = std::make_pair(0, NumLo);
10469 Mask1[NumLo] = Idx;
10472 Locs[i] = std::make_pair(1, NumHi);
10474 Mask1[2+NumHi] = Idx;
10480 if (NumLo <= 2 && NumHi <= 2) {
10481 // If no more than two elements come from either vector. This can be
10482 // implemented with two shuffles. First shuffle gather the elements.
10483 // The second shuffle, which takes the first shuffle as both of its
10484 // vector operands, put the elements into the right order.
10485 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10487 int Mask2[] = { -1, -1, -1, -1 };
10489 for (unsigned i = 0; i != 4; ++i)
10490 if (Locs[i].first != -1) {
10491 unsigned Idx = (i < 2) ? 0 : 4;
10492 Idx += Locs[i].first * 2 + Locs[i].second;
10496 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10499 if (NumLo == 3 || NumHi == 3) {
10500 // Otherwise, we must have three elements from one vector, call it X, and
10501 // one element from the other, call it Y. First, use a shufps to build an
10502 // intermediate vector with the one element from Y and the element from X
10503 // that will be in the same half in the final destination (the indexes don't
10504 // matter). Then, use a shufps to build the final vector, taking the half
10505 // containing the element from Y from the intermediate, and the other half
10508 // Normalize it so the 3 elements come from V1.
10509 CommuteVectorShuffleMask(PermMask, 4);
10513 // Find the element from V2.
10515 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10516 int Val = PermMask[HiIndex];
10523 Mask1[0] = PermMask[HiIndex];
10525 Mask1[2] = PermMask[HiIndex^1];
10527 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10529 if (HiIndex >= 2) {
10530 Mask1[0] = PermMask[0];
10531 Mask1[1] = PermMask[1];
10532 Mask1[2] = HiIndex & 1 ? 6 : 4;
10533 Mask1[3] = HiIndex & 1 ? 4 : 6;
10534 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10537 Mask1[0] = HiIndex & 1 ? 2 : 0;
10538 Mask1[1] = HiIndex & 1 ? 0 : 2;
10539 Mask1[2] = PermMask[2];
10540 Mask1[3] = PermMask[3];
10545 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10548 // Break it into (shuffle shuffle_hi, shuffle_lo).
10549 int LoMask[] = { -1, -1, -1, -1 };
10550 int HiMask[] = { -1, -1, -1, -1 };
10552 int *MaskPtr = LoMask;
10553 unsigned MaskIdx = 0;
10554 unsigned LoIdx = 0;
10555 unsigned HiIdx = 2;
10556 for (unsigned i = 0; i != 4; ++i) {
10563 int Idx = PermMask[i];
10565 Locs[i] = std::make_pair(-1, -1);
10566 } else if (Idx < 4) {
10567 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10568 MaskPtr[LoIdx] = Idx;
10571 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10572 MaskPtr[HiIdx] = Idx;
10577 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10578 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10579 int MaskOps[] = { -1, -1, -1, -1 };
10580 for (unsigned i = 0; i != 4; ++i)
10581 if (Locs[i].first != -1)
10582 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10583 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10586 static bool MayFoldVectorLoad(SDValue V) {
10587 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10588 V = V.getOperand(0);
10590 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10591 V = V.getOperand(0);
10592 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10593 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10594 // BUILD_VECTOR (load), undef
10595 V = V.getOperand(0);
10597 return MayFoldLoad(V);
10601 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10602 MVT VT = Op.getSimpleValueType();
10604 // Canonizalize to v2f64.
10605 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10606 return DAG.getNode(ISD::BITCAST, dl, VT,
10607 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10612 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10614 SDValue V1 = Op.getOperand(0);
10615 SDValue V2 = Op.getOperand(1);
10616 MVT VT = Op.getSimpleValueType();
10618 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10620 if (HasSSE2 && VT == MVT::v2f64)
10621 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10623 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10624 return DAG.getNode(ISD::BITCAST, dl, VT,
10625 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10626 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10627 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10631 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10632 SDValue V1 = Op.getOperand(0);
10633 SDValue V2 = Op.getOperand(1);
10634 MVT VT = Op.getSimpleValueType();
10636 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10637 "unsupported shuffle type");
10639 if (V2.getOpcode() == ISD::UNDEF)
10643 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10647 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10648 SDValue V1 = Op.getOperand(0);
10649 SDValue V2 = Op.getOperand(1);
10650 MVT VT = Op.getSimpleValueType();
10651 unsigned NumElems = VT.getVectorNumElements();
10653 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10654 // operand of these instructions is only memory, so check if there's a
10655 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10657 bool CanFoldLoad = false;
10659 // Trivial case, when V2 comes from a load.
10660 if (MayFoldVectorLoad(V2))
10661 CanFoldLoad = true;
10663 // When V1 is a load, it can be folded later into a store in isel, example:
10664 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10666 // (MOVLPSmr addr:$src1, VR128:$src2)
10667 // So, recognize this potential and also use MOVLPS or MOVLPD
10668 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10669 CanFoldLoad = true;
10671 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10673 if (HasSSE2 && NumElems == 2)
10674 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10677 // If we don't care about the second element, proceed to use movss.
10678 if (SVOp->getMaskElt(1) != -1)
10679 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10682 // movl and movlp will both match v2i64, but v2i64 is never matched by
10683 // movl earlier because we make it strict to avoid messing with the movlp load
10684 // folding logic (see the code above getMOVLP call). Match it here then,
10685 // this is horrible, but will stay like this until we move all shuffle
10686 // matching to x86 specific nodes. Note that for the 1st condition all
10687 // types are matched with movsd.
10689 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10690 // as to remove this logic from here, as much as possible
10691 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10692 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10693 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10696 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10698 // Invert the operand order and use SHUFPS to match it.
10699 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10700 getShuffleSHUFImmediate(SVOp), DAG);
10703 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10704 SelectionDAG &DAG) {
10706 MVT VT = Load->getSimpleValueType(0);
10707 MVT EVT = VT.getVectorElementType();
10708 SDValue Addr = Load->getOperand(1);
10709 SDValue NewAddr = DAG.getNode(
10710 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10711 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10714 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10715 DAG.getMachineFunction().getMachineMemOperand(
10716 Load->getMemOperand(), 0, EVT.getStoreSize()));
10720 // It is only safe to call this function if isINSERTPSMask is true for
10721 // this shufflevector mask.
10722 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10723 SelectionDAG &DAG) {
10724 // Generate an insertps instruction when inserting an f32 from memory onto a
10725 // v4f32 or when copying a member from one v4f32 to another.
10726 // We also use it for transferring i32 from one register to another,
10727 // since it simply copies the same bits.
10728 // If we're transferring an i32 from memory to a specific element in a
10729 // register, we output a generic DAG that will match the PINSRD
10731 MVT VT = SVOp->getSimpleValueType(0);
10732 MVT EVT = VT.getVectorElementType();
10733 SDValue V1 = SVOp->getOperand(0);
10734 SDValue V2 = SVOp->getOperand(1);
10735 auto Mask = SVOp->getMask();
10736 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10737 "unsupported vector type for insertps/pinsrd");
10739 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10740 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10741 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10745 unsigned DestIndex;
10749 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10752 // If we have 1 element from each vector, we have to check if we're
10753 // changing V1's element's place. If so, we're done. Otherwise, we
10754 // should assume we're changing V2's element's place and behave
10756 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10757 assert(DestIndex <= INT32_MAX && "truncated destination index");
10758 if (FromV1 == FromV2 &&
10759 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
10763 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10766 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
10767 "More than one element from V1 and from V2, or no elements from one "
10768 "of the vectors. This case should not have returned true from "
10773 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10776 // Get an index into the source vector in the range [0,4) (the mask is
10777 // in the range [0,8) because it can address V1 and V2)
10778 unsigned SrcIndex = Mask[DestIndex] % 4;
10779 if (MayFoldLoad(From)) {
10780 // Trivial case, when From comes from a load and is only used by the
10781 // shuffle. Make it use insertps from the vector that we need from that
10784 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
10785 if (!NewLoad.getNode())
10788 if (EVT == MVT::f32) {
10789 // Create this as a scalar to vector to match the instruction pattern.
10790 SDValue LoadScalarToVector =
10791 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
10792 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
10793 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
10795 } else { // EVT == MVT::i32
10796 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
10797 // instruction, to match the PINSRD instruction, which loads an i32 to a
10798 // certain vector element.
10799 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
10800 DAG.getConstant(DestIndex, MVT::i32));
10804 // Vector-element-to-vector
10805 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
10806 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
10809 // Reduce a vector shuffle to zext.
10810 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
10811 SelectionDAG &DAG) {
10812 // PMOVZX is only available from SSE41.
10813 if (!Subtarget->hasSSE41())
10816 MVT VT = Op.getSimpleValueType();
10818 // Only AVX2 support 256-bit vector integer extending.
10819 if (!Subtarget->hasInt256() && VT.is256BitVector())
10822 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10824 SDValue V1 = Op.getOperand(0);
10825 SDValue V2 = Op.getOperand(1);
10826 unsigned NumElems = VT.getVectorNumElements();
10828 // Extending is an unary operation and the element type of the source vector
10829 // won't be equal to or larger than i64.
10830 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
10831 VT.getVectorElementType() == MVT::i64)
10834 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
10835 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
10836 while ((1U << Shift) < NumElems) {
10837 if (SVOp->getMaskElt(1U << Shift) == 1)
10840 // The maximal ratio is 8, i.e. from i8 to i64.
10845 // Check the shuffle mask.
10846 unsigned Mask = (1U << Shift) - 1;
10847 for (unsigned i = 0; i != NumElems; ++i) {
10848 int EltIdx = SVOp->getMaskElt(i);
10849 if ((i & Mask) != 0 && EltIdx != -1)
10851 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
10855 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
10856 MVT NeVT = MVT::getIntegerVT(NBits);
10857 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
10859 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
10862 // Simplify the operand as it's prepared to be fed into shuffle.
10863 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
10864 if (V1.getOpcode() == ISD::BITCAST &&
10865 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
10866 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
10867 V1.getOperand(0).getOperand(0)
10868 .getSimpleValueType().getSizeInBits() == SignificantBits) {
10869 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
10870 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
10871 ConstantSDNode *CIdx =
10872 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
10873 // If it's foldable, i.e. normal load with single use, we will let code
10874 // selection to fold it. Otherwise, we will short the conversion sequence.
10875 if (CIdx && CIdx->getZExtValue() == 0 &&
10876 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
10877 MVT FullVT = V.getSimpleValueType();
10878 MVT V1VT = V1.getSimpleValueType();
10879 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
10880 // The "ext_vec_elt" node is wider than the result node.
10881 // In this case we should extract subvector from V.
10882 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
10883 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
10884 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
10885 FullVT.getVectorNumElements()/Ratio);
10886 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
10887 DAG.getIntPtrConstant(0));
10889 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
10893 return DAG.getNode(ISD::BITCAST, DL, VT,
10894 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
10897 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10898 SelectionDAG &DAG) {
10899 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10900 MVT VT = Op.getSimpleValueType();
10902 SDValue V1 = Op.getOperand(0);
10903 SDValue V2 = Op.getOperand(1);
10905 if (isZeroShuffle(SVOp))
10906 return getZeroVector(VT, Subtarget, DAG, dl);
10908 // Handle splat operations
10909 if (SVOp->isSplat()) {
10910 // Use vbroadcast whenever the splat comes from a foldable load
10911 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
10912 if (Broadcast.getNode())
10916 // Check integer expanding shuffles.
10917 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
10918 if (NewOp.getNode())
10921 // If the shuffle can be profitably rewritten as a narrower shuffle, then
10923 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
10924 VT == MVT::v32i8) {
10925 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10926 if (NewOp.getNode())
10927 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
10928 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
10929 // FIXME: Figure out a cleaner way to do this.
10930 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
10931 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10932 if (NewOp.getNode()) {
10933 MVT NewVT = NewOp.getSimpleValueType();
10934 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
10935 NewVT, true, false))
10936 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
10939 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
10940 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10941 if (NewOp.getNode()) {
10942 MVT NewVT = NewOp.getSimpleValueType();
10943 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
10944 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
10953 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
10954 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10955 SDValue V1 = Op.getOperand(0);
10956 SDValue V2 = Op.getOperand(1);
10957 MVT VT = Op.getSimpleValueType();
10959 unsigned NumElems = VT.getVectorNumElements();
10960 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10961 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10962 bool V1IsSplat = false;
10963 bool V2IsSplat = false;
10964 bool HasSSE2 = Subtarget->hasSSE2();
10965 bool HasFp256 = Subtarget->hasFp256();
10966 bool HasInt256 = Subtarget->hasInt256();
10967 MachineFunction &MF = DAG.getMachineFunction();
10968 bool OptForSize = MF.getFunction()->getAttributes().
10969 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
10971 // Check if we should use the experimental vector shuffle lowering. If so,
10972 // delegate completely to that code path.
10973 if (ExperimentalVectorShuffleLowering)
10974 return lowerVectorShuffle(Op, Subtarget, DAG);
10976 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10978 if (V1IsUndef && V2IsUndef)
10979 return DAG.getUNDEF(VT);
10981 // When we create a shuffle node we put the UNDEF node to second operand,
10982 // but in some cases the first operand may be transformed to UNDEF.
10983 // In this case we should just commute the node.
10985 return DAG.getCommutedVectorShuffle(*SVOp);
10987 // Vector shuffle lowering takes 3 steps:
10989 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
10990 // narrowing and commutation of operands should be handled.
10991 // 2) Matching of shuffles with known shuffle masks to x86 target specific
10993 // 3) Rewriting of unmatched masks into new generic shuffle operations,
10994 // so the shuffle can be broken into other shuffles and the legalizer can
10995 // try the lowering again.
10997 // The general idea is that no vector_shuffle operation should be left to
10998 // be matched during isel, all of them must be converted to a target specific
11001 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11002 // narrowing and commutation of operands should be handled. The actual code
11003 // doesn't include all of those, work in progress...
11004 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11005 if (NewOp.getNode())
11008 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11010 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11011 // unpckh_undef). Only use pshufd if speed is more important than size.
11012 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11013 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11014 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11015 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11017 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11018 V2IsUndef && MayFoldVectorLoad(V1))
11019 return getMOVDDup(Op, dl, V1, DAG);
11021 if (isMOVHLPS_v_undef_Mask(M, VT))
11022 return getMOVHighToLow(Op, dl, DAG);
11024 // Use to match splats
11025 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11026 (VT == MVT::v2f64 || VT == MVT::v2i64))
11027 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11029 if (isPSHUFDMask(M, VT)) {
11030 // The actual implementation will match the mask in the if above and then
11031 // during isel it can match several different instructions, not only pshufd
11032 // as its name says, sad but true, emulate the behavior for now...
11033 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11034 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11036 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11038 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11039 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11041 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11042 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11045 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11049 if (isPALIGNRMask(M, VT, Subtarget))
11050 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11051 getShufflePALIGNRImmediate(SVOp),
11054 if (isVALIGNMask(M, VT, Subtarget))
11055 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11056 getShuffleVALIGNImmediate(SVOp),
11059 // Check if this can be converted into a logical shift.
11060 bool isLeft = false;
11061 unsigned ShAmt = 0;
11063 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11064 if (isShift && ShVal.hasOneUse()) {
11065 // If the shifted value has multiple uses, it may be cheaper to use
11066 // v_set0 + movlhps or movhlps, etc.
11067 MVT EltVT = VT.getVectorElementType();
11068 ShAmt *= EltVT.getSizeInBits();
11069 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11072 if (isMOVLMask(M, VT)) {
11073 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11074 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11075 if (!isMOVLPMask(M, VT)) {
11076 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11077 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11079 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11080 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11084 // FIXME: fold these into legal mask.
11085 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11086 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11088 if (isMOVHLPSMask(M, VT))
11089 return getMOVHighToLow(Op, dl, DAG);
11091 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11092 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11094 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11095 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11097 if (isMOVLPMask(M, VT))
11098 return getMOVLP(Op, dl, DAG, HasSSE2);
11100 if (ShouldXformToMOVHLPS(M, VT) ||
11101 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11102 return DAG.getCommutedVectorShuffle(*SVOp);
11105 // No better options. Use a vshldq / vsrldq.
11106 MVT EltVT = VT.getVectorElementType();
11107 ShAmt *= EltVT.getSizeInBits();
11108 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11111 bool Commuted = false;
11112 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11113 // 1,1,1,1 -> v8i16 though.
11114 BitVector UndefElements;
11115 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11116 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11118 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11119 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11122 // Canonicalize the splat or undef, if present, to be on the RHS.
11123 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11124 CommuteVectorShuffleMask(M, NumElems);
11126 std::swap(V1IsSplat, V2IsSplat);
11130 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11131 // Shuffling low element of v1 into undef, just return v1.
11134 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11135 // the instruction selector will not match, so get a canonical MOVL with
11136 // swapped operands to undo the commute.
11137 return getMOVL(DAG, dl, VT, V2, V1);
11140 if (isUNPCKLMask(M, VT, HasInt256))
11141 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11143 if (isUNPCKHMask(M, VT, HasInt256))
11144 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11147 // Normalize mask so all entries that point to V2 points to its first
11148 // element then try to match unpck{h|l} again. If match, return a
11149 // new vector_shuffle with the corrected mask.p
11150 SmallVector<int, 8> NewMask(M.begin(), M.end());
11151 NormalizeMask(NewMask, NumElems);
11152 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11153 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11154 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11155 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11159 // Commute is back and try unpck* again.
11160 // FIXME: this seems wrong.
11161 CommuteVectorShuffleMask(M, NumElems);
11163 std::swap(V1IsSplat, V2IsSplat);
11165 if (isUNPCKLMask(M, VT, HasInt256))
11166 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11168 if (isUNPCKHMask(M, VT, HasInt256))
11169 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11172 // Normalize the node to match x86 shuffle ops if needed
11173 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11174 return DAG.getCommutedVectorShuffle(*SVOp);
11176 // The checks below are all present in isShuffleMaskLegal, but they are
11177 // inlined here right now to enable us to directly emit target specific
11178 // nodes, and remove one by one until they don't return Op anymore.
11180 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11181 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11182 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11183 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11186 if (isPSHUFHWMask(M, VT, HasInt256))
11187 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11188 getShufflePSHUFHWImmediate(SVOp),
11191 if (isPSHUFLWMask(M, VT, HasInt256))
11192 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11193 getShufflePSHUFLWImmediate(SVOp),
11196 unsigned MaskValue;
11197 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11199 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11201 if (isSHUFPMask(M, VT))
11202 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11203 getShuffleSHUFImmediate(SVOp), DAG);
11205 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11206 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11207 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11208 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11210 //===--------------------------------------------------------------------===//
11211 // Generate target specific nodes for 128 or 256-bit shuffles only
11212 // supported in the AVX instruction set.
11215 // Handle VMOVDDUPY permutations
11216 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11217 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11219 // Handle VPERMILPS/D* permutations
11220 if (isVPERMILPMask(M, VT)) {
11221 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11222 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11223 getShuffleSHUFImmediate(SVOp), DAG);
11224 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11225 getShuffleSHUFImmediate(SVOp), DAG);
11229 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11230 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11231 Idx*(NumElems/2), DAG, dl);
11233 // Handle VPERM2F128/VPERM2I128 permutations
11234 if (isVPERM2X128Mask(M, VT, HasFp256))
11235 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11236 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11238 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11239 return getINSERTPS(SVOp, dl, DAG);
11242 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11243 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11245 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11246 VT.is512BitVector()) {
11247 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11248 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11249 SmallVector<SDValue, 16> permclMask;
11250 for (unsigned i = 0; i != NumElems; ++i) {
11251 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11254 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11256 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11257 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11258 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11259 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11260 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11263 //===--------------------------------------------------------------------===//
11264 // Since no target specific shuffle was selected for this generic one,
11265 // lower it into other known shuffles. FIXME: this isn't true yet, but
11266 // this is the plan.
11269 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11270 if (VT == MVT::v8i16) {
11271 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11272 if (NewOp.getNode())
11276 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11277 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11278 if (NewOp.getNode())
11282 if (VT == MVT::v16i8) {
11283 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11284 if (NewOp.getNode())
11288 if (VT == MVT::v32i8) {
11289 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11290 if (NewOp.getNode())
11294 // Handle all 128-bit wide vectors with 4 elements, and match them with
11295 // several different shuffle types.
11296 if (NumElems == 4 && VT.is128BitVector())
11297 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11299 // Handle general 256-bit shuffles
11300 if (VT.is256BitVector())
11301 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11306 // This function assumes its argument is a BUILD_VECTOR of constants or
11307 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11309 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11310 unsigned &MaskValue) {
11312 unsigned NumElems = BuildVector->getNumOperands();
11313 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11314 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11315 unsigned NumElemsInLane = NumElems / NumLanes;
11317 // Blend for v16i16 should be symetric for the both lanes.
11318 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11319 SDValue EltCond = BuildVector->getOperand(i);
11320 SDValue SndLaneEltCond =
11321 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11323 int Lane1Cond = -1, Lane2Cond = -1;
11324 if (isa<ConstantSDNode>(EltCond))
11325 Lane1Cond = !isZero(EltCond);
11326 if (isa<ConstantSDNode>(SndLaneEltCond))
11327 Lane2Cond = !isZero(SndLaneEltCond);
11329 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11330 // Lane1Cond != 0, means we want the first argument.
11331 // Lane1Cond == 0, means we want the second argument.
11332 // The encoding of this argument is 0 for the first argument, 1
11333 // for the second. Therefore, invert the condition.
11334 MaskValue |= !Lane1Cond << i;
11335 else if (Lane1Cond < 0)
11336 MaskValue |= !Lane2Cond << i;
11343 // Try to lower a vselect node into a simple blend instruction.
11344 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11345 SelectionDAG &DAG) {
11346 SDValue Cond = Op.getOperand(0);
11347 SDValue LHS = Op.getOperand(1);
11348 SDValue RHS = Op.getOperand(2);
11350 MVT VT = Op.getSimpleValueType();
11351 MVT EltVT = VT.getVectorElementType();
11352 unsigned NumElems = VT.getVectorNumElements();
11354 // There is no blend with immediate in AVX-512.
11355 if (VT.is512BitVector())
11358 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11360 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11363 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11366 // Check the mask for BLEND and build the value.
11367 unsigned MaskValue = 0;
11368 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11371 // Convert i32 vectors to floating point if it is not AVX2.
11372 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11374 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11375 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11377 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11378 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11381 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11382 DAG.getConstant(MaskValue, MVT::i32));
11383 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11386 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11387 // A vselect where all conditions and data are constants can be optimized into
11388 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11389 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11390 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11391 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11394 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11395 if (BlendOp.getNode())
11398 // Some types for vselect were previously set to Expand, not Legal or
11399 // Custom. Return an empty SDValue so we fall-through to Expand, after
11400 // the Custom lowering phase.
11401 MVT VT = Op.getSimpleValueType();
11402 switch (VT.SimpleTy) {
11407 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11412 // We couldn't create a "Blend with immediate" node.
11413 // This node should still be legal, but we'll have to emit a blendv*
11418 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11419 MVT VT = Op.getSimpleValueType();
11422 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11425 if (VT.getSizeInBits() == 8) {
11426 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11427 Op.getOperand(0), Op.getOperand(1));
11428 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11429 DAG.getValueType(VT));
11430 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11433 if (VT.getSizeInBits() == 16) {
11434 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11435 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11437 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11438 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11439 DAG.getNode(ISD::BITCAST, dl,
11442 Op.getOperand(1)));
11443 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11444 Op.getOperand(0), Op.getOperand(1));
11445 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11446 DAG.getValueType(VT));
11447 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11450 if (VT == MVT::f32) {
11451 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11452 // the result back to FR32 register. It's only worth matching if the
11453 // result has a single use which is a store or a bitcast to i32. And in
11454 // the case of a store, it's not worth it if the index is a constant 0,
11455 // because a MOVSSmr can be used instead, which is smaller and faster.
11456 if (!Op.hasOneUse())
11458 SDNode *User = *Op.getNode()->use_begin();
11459 if ((User->getOpcode() != ISD::STORE ||
11460 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11461 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11462 (User->getOpcode() != ISD::BITCAST ||
11463 User->getValueType(0) != MVT::i32))
11465 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11466 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11469 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11472 if (VT == MVT::i32 || VT == MVT::i64) {
11473 // ExtractPS/pextrq works with constant index.
11474 if (isa<ConstantSDNode>(Op.getOperand(1)))
11480 /// Extract one bit from mask vector, like v16i1 or v8i1.
11481 /// AVX-512 feature.
11483 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11484 SDValue Vec = Op.getOperand(0);
11486 MVT VecVT = Vec.getSimpleValueType();
11487 SDValue Idx = Op.getOperand(1);
11488 MVT EltVT = Op.getSimpleValueType();
11490 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11492 // variable index can't be handled in mask registers,
11493 // extend vector to VR512
11494 if (!isa<ConstantSDNode>(Idx)) {
11495 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11496 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11497 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11498 ExtVT.getVectorElementType(), Ext, Idx);
11499 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11502 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11503 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11504 unsigned MaxSift = rc->getSize()*8 - 1;
11505 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11506 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11507 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11508 DAG.getConstant(MaxSift, MVT::i8));
11509 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11510 DAG.getIntPtrConstant(0));
11514 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11515 SelectionDAG &DAG) const {
11517 SDValue Vec = Op.getOperand(0);
11518 MVT VecVT = Vec.getSimpleValueType();
11519 SDValue Idx = Op.getOperand(1);
11521 if (Op.getSimpleValueType() == MVT::i1)
11522 return ExtractBitFromMaskVector(Op, DAG);
11524 if (!isa<ConstantSDNode>(Idx)) {
11525 if (VecVT.is512BitVector() ||
11526 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11527 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11530 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11531 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11532 MaskEltVT.getSizeInBits());
11534 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11535 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11536 getZeroVector(MaskVT, Subtarget, DAG, dl),
11537 Idx, DAG.getConstant(0, getPointerTy()));
11538 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11539 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11540 Perm, DAG.getConstant(0, getPointerTy()));
11545 // If this is a 256-bit vector result, first extract the 128-bit vector and
11546 // then extract the element from the 128-bit vector.
11547 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11549 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11550 // Get the 128-bit vector.
11551 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11552 MVT EltVT = VecVT.getVectorElementType();
11554 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11556 //if (IdxVal >= NumElems/2)
11557 // IdxVal -= NumElems/2;
11558 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11559 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11560 DAG.getConstant(IdxVal, MVT::i32));
11563 assert(VecVT.is128BitVector() && "Unexpected vector length");
11565 if (Subtarget->hasSSE41()) {
11566 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11571 MVT VT = Op.getSimpleValueType();
11572 // TODO: handle v16i8.
11573 if (VT.getSizeInBits() == 16) {
11574 SDValue Vec = Op.getOperand(0);
11575 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11577 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11578 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11579 DAG.getNode(ISD::BITCAST, dl,
11581 Op.getOperand(1)));
11582 // Transform it so it match pextrw which produces a 32-bit result.
11583 MVT EltVT = MVT::i32;
11584 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11585 Op.getOperand(0), Op.getOperand(1));
11586 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11587 DAG.getValueType(VT));
11588 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11591 if (VT.getSizeInBits() == 32) {
11592 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11596 // SHUFPS the element to the lowest double word, then movss.
11597 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11598 MVT VVT = Op.getOperand(0).getSimpleValueType();
11599 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11600 DAG.getUNDEF(VVT), Mask);
11601 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11602 DAG.getIntPtrConstant(0));
11605 if (VT.getSizeInBits() == 64) {
11606 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11607 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11608 // to match extract_elt for f64.
11609 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11613 // UNPCKHPD the element to the lowest double word, then movsd.
11614 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11615 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11616 int Mask[2] = { 1, -1 };
11617 MVT VVT = Op.getOperand(0).getSimpleValueType();
11618 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11619 DAG.getUNDEF(VVT), Mask);
11620 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11621 DAG.getIntPtrConstant(0));
11627 /// Insert one bit to mask vector, like v16i1 or v8i1.
11628 /// AVX-512 feature.
11630 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11632 SDValue Vec = Op.getOperand(0);
11633 SDValue Elt = Op.getOperand(1);
11634 SDValue Idx = Op.getOperand(2);
11635 MVT VecVT = Vec.getSimpleValueType();
11637 if (!isa<ConstantSDNode>(Idx)) {
11638 // Non constant index. Extend source and destination,
11639 // insert element and then truncate the result.
11640 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11641 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11642 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11643 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11644 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11645 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11648 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11649 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11650 if (Vec.getOpcode() == ISD::UNDEF)
11651 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11652 DAG.getConstant(IdxVal, MVT::i8));
11653 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11654 unsigned MaxSift = rc->getSize()*8 - 1;
11655 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11656 DAG.getConstant(MaxSift, MVT::i8));
11657 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11658 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11659 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11662 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11663 SelectionDAG &DAG) const {
11664 MVT VT = Op.getSimpleValueType();
11665 MVT EltVT = VT.getVectorElementType();
11667 if (EltVT == MVT::i1)
11668 return InsertBitToMaskVector(Op, DAG);
11671 SDValue N0 = Op.getOperand(0);
11672 SDValue N1 = Op.getOperand(1);
11673 SDValue N2 = Op.getOperand(2);
11674 if (!isa<ConstantSDNode>(N2))
11676 auto *N2C = cast<ConstantSDNode>(N2);
11677 unsigned IdxVal = N2C->getZExtValue();
11679 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11680 // into that, and then insert the subvector back into the result.
11681 if (VT.is256BitVector() || VT.is512BitVector()) {
11682 // Get the desired 128-bit vector half.
11683 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11685 // Insert the element into the desired half.
11686 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11687 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11689 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11690 DAG.getConstant(IdxIn128, MVT::i32));
11692 // Insert the changed part back to the 256-bit vector
11693 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11695 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11697 if (Subtarget->hasSSE41()) {
11698 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11700 if (VT == MVT::v8i16) {
11701 Opc = X86ISD::PINSRW;
11703 assert(VT == MVT::v16i8);
11704 Opc = X86ISD::PINSRB;
11707 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11709 if (N1.getValueType() != MVT::i32)
11710 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11711 if (N2.getValueType() != MVT::i32)
11712 N2 = DAG.getIntPtrConstant(IdxVal);
11713 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11716 if (EltVT == MVT::f32) {
11717 // Bits [7:6] of the constant are the source select. This will always be
11718 // zero here. The DAG Combiner may combine an extract_elt index into
11720 // bits. For example (insert (extract, 3), 2) could be matched by
11722 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11723 // Bits [5:4] of the constant are the destination select. This is the
11724 // value of the incoming immediate.
11725 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11726 // combine either bitwise AND or insert of float 0.0 to set these bits.
11727 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11728 // Create this as a scalar to vector..
11729 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11730 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11733 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11734 // PINSR* works with constant index.
11739 if (EltVT == MVT::i8)
11742 if (EltVT.getSizeInBits() == 16) {
11743 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11744 // as its second argument.
11745 if (N1.getValueType() != MVT::i32)
11746 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11747 if (N2.getValueType() != MVT::i32)
11748 N2 = DAG.getIntPtrConstant(IdxVal);
11749 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11754 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11756 MVT OpVT = Op.getSimpleValueType();
11758 // If this is a 256-bit vector result, first insert into a 128-bit
11759 // vector and then insert into the 256-bit vector.
11760 if (!OpVT.is128BitVector()) {
11761 // Insert into a 128-bit vector.
11762 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11763 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11764 OpVT.getVectorNumElements() / SizeFactor);
11766 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11768 // Insert the 128-bit vector.
11769 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11772 if (OpVT == MVT::v1i64 &&
11773 Op.getOperand(0).getValueType() == MVT::i64)
11774 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11776 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11777 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11778 return DAG.getNode(ISD::BITCAST, dl, OpVT,
11779 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
11782 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11783 // a simple subregister reference or explicit instructions to grab
11784 // upper bits of a vector.
11785 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11786 SelectionDAG &DAG) {
11788 SDValue In = Op.getOperand(0);
11789 SDValue Idx = Op.getOperand(1);
11790 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11791 MVT ResVT = Op.getSimpleValueType();
11792 MVT InVT = In.getSimpleValueType();
11794 if (Subtarget->hasFp256()) {
11795 if (ResVT.is128BitVector() &&
11796 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11797 isa<ConstantSDNode>(Idx)) {
11798 return Extract128BitVector(In, IdxVal, DAG, dl);
11800 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11801 isa<ConstantSDNode>(Idx)) {
11802 return Extract256BitVector(In, IdxVal, DAG, dl);
11808 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11809 // simple superregister reference or explicit instructions to insert
11810 // the upper bits of a vector.
11811 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11812 SelectionDAG &DAG) {
11813 if (Subtarget->hasFp256()) {
11814 SDLoc dl(Op.getNode());
11815 SDValue Vec = Op.getNode()->getOperand(0);
11816 SDValue SubVec = Op.getNode()->getOperand(1);
11817 SDValue Idx = Op.getNode()->getOperand(2);
11819 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
11820 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
11821 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
11822 isa<ConstantSDNode>(Idx)) {
11823 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11824 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11827 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
11828 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
11829 isa<ConstantSDNode>(Idx)) {
11830 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11831 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11837 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11838 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11839 // one of the above mentioned nodes. It has to be wrapped because otherwise
11840 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11841 // be used to form addressing mode. These wrapped nodes will be selected
11844 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11845 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11847 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11848 // global base reg.
11849 unsigned char OpFlag = 0;
11850 unsigned WrapperKind = X86ISD::Wrapper;
11851 CodeModel::Model M = DAG.getTarget().getCodeModel();
11853 if (Subtarget->isPICStyleRIPRel() &&
11854 (M == CodeModel::Small || M == CodeModel::Kernel))
11855 WrapperKind = X86ISD::WrapperRIP;
11856 else if (Subtarget->isPICStyleGOT())
11857 OpFlag = X86II::MO_GOTOFF;
11858 else if (Subtarget->isPICStyleStubPIC())
11859 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11861 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11862 CP->getAlignment(),
11863 CP->getOffset(), OpFlag);
11865 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11866 // With PIC, the address is actually $g + Offset.
11868 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11869 DAG.getNode(X86ISD::GlobalBaseReg,
11870 SDLoc(), getPointerTy()),
11877 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11878 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11880 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11881 // global base reg.
11882 unsigned char OpFlag = 0;
11883 unsigned WrapperKind = X86ISD::Wrapper;
11884 CodeModel::Model M = DAG.getTarget().getCodeModel();
11886 if (Subtarget->isPICStyleRIPRel() &&
11887 (M == CodeModel::Small || M == CodeModel::Kernel))
11888 WrapperKind = X86ISD::WrapperRIP;
11889 else if (Subtarget->isPICStyleGOT())
11890 OpFlag = X86II::MO_GOTOFF;
11891 else if (Subtarget->isPICStyleStubPIC())
11892 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11894 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11897 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11899 // With PIC, the address is actually $g + Offset.
11901 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11902 DAG.getNode(X86ISD::GlobalBaseReg,
11903 SDLoc(), getPointerTy()),
11910 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11911 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11913 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11914 // global base reg.
11915 unsigned char OpFlag = 0;
11916 unsigned WrapperKind = X86ISD::Wrapper;
11917 CodeModel::Model M = DAG.getTarget().getCodeModel();
11919 if (Subtarget->isPICStyleRIPRel() &&
11920 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11921 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11922 OpFlag = X86II::MO_GOTPCREL;
11923 WrapperKind = X86ISD::WrapperRIP;
11924 } else if (Subtarget->isPICStyleGOT()) {
11925 OpFlag = X86II::MO_GOT;
11926 } else if (Subtarget->isPICStyleStubPIC()) {
11927 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11928 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11929 OpFlag = X86II::MO_DARWIN_NONLAZY;
11932 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11935 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11937 // With PIC, the address is actually $g + Offset.
11938 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11939 !Subtarget->is64Bit()) {
11940 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11941 DAG.getNode(X86ISD::GlobalBaseReg,
11942 SDLoc(), getPointerTy()),
11946 // For symbols that require a load from a stub to get the address, emit the
11948 if (isGlobalStubReference(OpFlag))
11949 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11950 MachinePointerInfo::getGOT(), false, false, false, 0);
11956 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11957 // Create the TargetBlockAddressAddress node.
11958 unsigned char OpFlags =
11959 Subtarget->ClassifyBlockAddressReference();
11960 CodeModel::Model M = DAG.getTarget().getCodeModel();
11961 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11962 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11964 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11967 if (Subtarget->isPICStyleRIPRel() &&
11968 (M == CodeModel::Small || M == CodeModel::Kernel))
11969 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11971 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11973 // With PIC, the address is actually $g + Offset.
11974 if (isGlobalRelativeToPICBase(OpFlags)) {
11975 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11976 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11984 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11985 int64_t Offset, SelectionDAG &DAG) const {
11986 // Create the TargetGlobalAddress node, folding in the constant
11987 // offset if it is legal.
11988 unsigned char OpFlags =
11989 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11990 CodeModel::Model M = DAG.getTarget().getCodeModel();
11992 if (OpFlags == X86II::MO_NO_FLAG &&
11993 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11994 // A direct static reference to a global.
11995 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11998 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12001 if (Subtarget->isPICStyleRIPRel() &&
12002 (M == CodeModel::Small || M == CodeModel::Kernel))
12003 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12005 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12007 // With PIC, the address is actually $g + Offset.
12008 if (isGlobalRelativeToPICBase(OpFlags)) {
12009 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12010 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12014 // For globals that require a load from a stub to get the address, emit the
12016 if (isGlobalStubReference(OpFlags))
12017 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12018 MachinePointerInfo::getGOT(), false, false, false, 0);
12020 // If there was a non-zero offset that we didn't fold, create an explicit
12021 // addition for it.
12023 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12024 DAG.getConstant(Offset, getPointerTy()));
12030 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12031 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12032 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12033 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12037 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12038 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12039 unsigned char OperandFlags, bool LocalDynamic = false) {
12040 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12041 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12043 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12044 GA->getValueType(0),
12048 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12052 SDValue Ops[] = { Chain, TGA, *InFlag };
12053 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12055 SDValue Ops[] = { Chain, TGA };
12056 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12059 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12060 MFI->setAdjustsStack(true);
12062 SDValue Flag = Chain.getValue(1);
12063 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12066 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12068 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12071 SDLoc dl(GA); // ? function entry point might be better
12072 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12073 DAG.getNode(X86ISD::GlobalBaseReg,
12074 SDLoc(), PtrVT), InFlag);
12075 InFlag = Chain.getValue(1);
12077 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12080 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12082 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12084 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12085 X86::RAX, X86II::MO_TLSGD);
12088 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12094 // Get the start address of the TLS block for this module.
12095 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12096 .getInfo<X86MachineFunctionInfo>();
12097 MFI->incNumLocalDynamicTLSAccesses();
12101 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12102 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12105 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12106 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12107 InFlag = Chain.getValue(1);
12108 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12109 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12112 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12116 unsigned char OperandFlags = X86II::MO_DTPOFF;
12117 unsigned WrapperKind = X86ISD::Wrapper;
12118 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12119 GA->getValueType(0),
12120 GA->getOffset(), OperandFlags);
12121 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12123 // Add x@dtpoff with the base.
12124 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12127 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12128 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12129 const EVT PtrVT, TLSModel::Model model,
12130 bool is64Bit, bool isPIC) {
12133 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12134 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12135 is64Bit ? 257 : 256));
12137 SDValue ThreadPointer =
12138 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12139 MachinePointerInfo(Ptr), false, false, false, 0);
12141 unsigned char OperandFlags = 0;
12142 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12144 unsigned WrapperKind = X86ISD::Wrapper;
12145 if (model == TLSModel::LocalExec) {
12146 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12147 } else if (model == TLSModel::InitialExec) {
12149 OperandFlags = X86II::MO_GOTTPOFF;
12150 WrapperKind = X86ISD::WrapperRIP;
12152 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12155 llvm_unreachable("Unexpected model");
12158 // emit "addl x@ntpoff,%eax" (local exec)
12159 // or "addl x@indntpoff,%eax" (initial exec)
12160 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12162 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12163 GA->getOffset(), OperandFlags);
12164 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12166 if (model == TLSModel::InitialExec) {
12167 if (isPIC && !is64Bit) {
12168 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12169 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12173 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12174 MachinePointerInfo::getGOT(), false, false, false, 0);
12177 // The address of the thread local variable is the add of the thread
12178 // pointer with the offset of the variable.
12179 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12183 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12185 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12186 const GlobalValue *GV = GA->getGlobal();
12188 if (Subtarget->isTargetELF()) {
12189 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12192 case TLSModel::GeneralDynamic:
12193 if (Subtarget->is64Bit())
12194 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12195 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12196 case TLSModel::LocalDynamic:
12197 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12198 Subtarget->is64Bit());
12199 case TLSModel::InitialExec:
12200 case TLSModel::LocalExec:
12201 return LowerToTLSExecModel(
12202 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12203 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12205 llvm_unreachable("Unknown TLS model.");
12208 if (Subtarget->isTargetDarwin()) {
12209 // Darwin only has one model of TLS. Lower to that.
12210 unsigned char OpFlag = 0;
12211 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12212 X86ISD::WrapperRIP : X86ISD::Wrapper;
12214 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12215 // global base reg.
12216 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12217 !Subtarget->is64Bit();
12219 OpFlag = X86II::MO_TLVP_PIC_BASE;
12221 OpFlag = X86II::MO_TLVP;
12223 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12224 GA->getValueType(0),
12225 GA->getOffset(), OpFlag);
12226 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12228 // With PIC32, the address is actually $g + Offset.
12230 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12231 DAG.getNode(X86ISD::GlobalBaseReg,
12232 SDLoc(), getPointerTy()),
12235 // Lowering the machine isd will make sure everything is in the right
12237 SDValue Chain = DAG.getEntryNode();
12238 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12239 SDValue Args[] = { Chain, Offset };
12240 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12242 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12243 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12244 MFI->setAdjustsStack(true);
12246 // And our return value (tls address) is in the standard call return value
12248 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12249 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12250 Chain.getValue(1));
12253 if (Subtarget->isTargetKnownWindowsMSVC() ||
12254 Subtarget->isTargetWindowsGNU()) {
12255 // Just use the implicit TLS architecture
12256 // Need to generate someting similar to:
12257 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12259 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12260 // mov rcx, qword [rdx+rcx*8]
12261 // mov eax, .tls$:tlsvar
12262 // [rax+rcx] contains the address
12263 // Windows 64bit: gs:0x58
12264 // Windows 32bit: fs:__tls_array
12267 SDValue Chain = DAG.getEntryNode();
12269 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12270 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12271 // use its literal value of 0x2C.
12272 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12273 ? Type::getInt8PtrTy(*DAG.getContext(),
12275 : Type::getInt32PtrTy(*DAG.getContext(),
12279 Subtarget->is64Bit()
12280 ? DAG.getIntPtrConstant(0x58)
12281 : (Subtarget->isTargetWindowsGNU()
12282 ? DAG.getIntPtrConstant(0x2C)
12283 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12285 SDValue ThreadPointer =
12286 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12287 MachinePointerInfo(Ptr), false, false, false, 0);
12289 // Load the _tls_index variable
12290 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12291 if (Subtarget->is64Bit())
12292 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12293 IDX, MachinePointerInfo(), MVT::i32,
12294 false, false, false, 0);
12296 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12297 false, false, false, 0);
12299 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12301 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12303 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12304 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12305 false, false, false, 0);
12307 // Get the offset of start of .tls section
12308 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12309 GA->getValueType(0),
12310 GA->getOffset(), X86II::MO_SECREL);
12311 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12313 // The address of the thread local variable is the add of the thread
12314 // pointer with the offset of the variable.
12315 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12318 llvm_unreachable("TLS not implemented for this target.");
12321 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12322 /// and take a 2 x i32 value to shift plus a shift amount.
12323 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12324 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12325 MVT VT = Op.getSimpleValueType();
12326 unsigned VTBits = VT.getSizeInBits();
12328 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12329 SDValue ShOpLo = Op.getOperand(0);
12330 SDValue ShOpHi = Op.getOperand(1);
12331 SDValue ShAmt = Op.getOperand(2);
12332 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12333 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12335 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12336 DAG.getConstant(VTBits - 1, MVT::i8));
12337 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12338 DAG.getConstant(VTBits - 1, MVT::i8))
12339 : DAG.getConstant(0, VT);
12341 SDValue Tmp2, Tmp3;
12342 if (Op.getOpcode() == ISD::SHL_PARTS) {
12343 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12344 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12346 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12347 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12350 // If the shift amount is larger or equal than the width of a part we can't
12351 // rely on the results of shld/shrd. Insert a test and select the appropriate
12352 // values for large shift amounts.
12353 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12354 DAG.getConstant(VTBits, MVT::i8));
12355 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12356 AndNode, DAG.getConstant(0, MVT::i8));
12359 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12360 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12361 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12363 if (Op.getOpcode() == ISD::SHL_PARTS) {
12364 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12365 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12367 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12368 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12371 SDValue Ops[2] = { Lo, Hi };
12372 return DAG.getMergeValues(Ops, dl);
12375 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12376 SelectionDAG &DAG) const {
12377 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12379 if (SrcVT.isVector())
12382 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12383 "Unknown SINT_TO_FP to lower!");
12385 // These are really Legal; return the operand so the caller accepts it as
12387 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12389 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12390 Subtarget->is64Bit()) {
12395 unsigned Size = SrcVT.getSizeInBits()/8;
12396 MachineFunction &MF = DAG.getMachineFunction();
12397 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12398 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12399 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12401 MachinePointerInfo::getFixedStack(SSFI),
12403 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12406 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12408 SelectionDAG &DAG) const {
12412 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12414 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12416 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12418 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12420 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12421 MachineMemOperand *MMO;
12423 int SSFI = FI->getIndex();
12425 DAG.getMachineFunction()
12426 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12427 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12429 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12430 StackSlot = StackSlot.getOperand(1);
12432 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12433 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12435 Tys, Ops, SrcVT, MMO);
12438 Chain = Result.getValue(1);
12439 SDValue InFlag = Result.getValue(2);
12441 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12442 // shouldn't be necessary except that RFP cannot be live across
12443 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12444 MachineFunction &MF = DAG.getMachineFunction();
12445 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12446 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12447 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12448 Tys = DAG.getVTList(MVT::Other);
12450 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12452 MachineMemOperand *MMO =
12453 DAG.getMachineFunction()
12454 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12455 MachineMemOperand::MOStore, SSFISize, SSFISize);
12457 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12458 Ops, Op.getValueType(), MMO);
12459 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12460 MachinePointerInfo::getFixedStack(SSFI),
12461 false, false, false, 0);
12467 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12468 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12469 SelectionDAG &DAG) const {
12470 // This algorithm is not obvious. Here it is what we're trying to output:
12473 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12474 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12476 haddpd %xmm0, %xmm0
12478 pshufd $0x4e, %xmm0, %xmm1
12484 LLVMContext *Context = DAG.getContext();
12486 // Build some magic constants.
12487 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12488 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12489 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12491 SmallVector<Constant*,2> CV1;
12493 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12494 APInt(64, 0x4330000000000000ULL))));
12496 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12497 APInt(64, 0x4530000000000000ULL))));
12498 Constant *C1 = ConstantVector::get(CV1);
12499 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12501 // Load the 64-bit value into an XMM register.
12502 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12504 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12505 MachinePointerInfo::getConstantPool(),
12506 false, false, false, 16);
12507 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12508 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12511 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12512 MachinePointerInfo::getConstantPool(),
12513 false, false, false, 16);
12514 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12515 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12518 if (Subtarget->hasSSE3()) {
12519 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12520 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12522 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12523 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12525 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12526 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12530 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12531 DAG.getIntPtrConstant(0));
12534 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12535 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12536 SelectionDAG &DAG) const {
12538 // FP constant to bias correct the final result.
12539 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12542 // Load the 32-bit value into an XMM register.
12543 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12546 // Zero out the upper parts of the register.
12547 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12549 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12550 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12551 DAG.getIntPtrConstant(0));
12553 // Or the load with the bias.
12554 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12555 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12556 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12557 MVT::v2f64, Load)),
12558 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12559 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12560 MVT::v2f64, Bias)));
12561 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12562 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12563 DAG.getIntPtrConstant(0));
12565 // Subtract the bias.
12566 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12568 // Handle final rounding.
12569 EVT DestVT = Op.getValueType();
12571 if (DestVT.bitsLT(MVT::f64))
12572 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12573 DAG.getIntPtrConstant(0));
12574 if (DestVT.bitsGT(MVT::f64))
12575 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12577 // Handle final rounding.
12581 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12582 SelectionDAG &DAG) const {
12583 SDValue N0 = Op.getOperand(0);
12584 MVT SVT = N0.getSimpleValueType();
12587 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12588 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12589 "Custom UINT_TO_FP is not supported!");
12591 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12592 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12593 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12596 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12597 SelectionDAG &DAG) const {
12598 SDValue N0 = Op.getOperand(0);
12601 if (Op.getValueType().isVector())
12602 return lowerUINT_TO_FP_vec(Op, DAG);
12604 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12605 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12606 // the optimization here.
12607 if (DAG.SignBitIsZero(N0))
12608 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12610 MVT SrcVT = N0.getSimpleValueType();
12611 MVT DstVT = Op.getSimpleValueType();
12612 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12613 return LowerUINT_TO_FP_i64(Op, DAG);
12614 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12615 return LowerUINT_TO_FP_i32(Op, DAG);
12616 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12619 // Make a 64-bit buffer, and use it to build an FILD.
12620 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12621 if (SrcVT == MVT::i32) {
12622 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12623 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12624 getPointerTy(), StackSlot, WordOff);
12625 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12626 StackSlot, MachinePointerInfo(),
12628 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12629 OffsetSlot, MachinePointerInfo(),
12631 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12635 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12636 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12637 StackSlot, MachinePointerInfo(),
12639 // For i64 source, we need to add the appropriate power of 2 if the input
12640 // was negative. This is the same as the optimization in
12641 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12642 // we must be careful to do the computation in x87 extended precision, not
12643 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12644 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12645 MachineMemOperand *MMO =
12646 DAG.getMachineFunction()
12647 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12648 MachineMemOperand::MOLoad, 8, 8);
12650 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12651 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12652 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12655 APInt FF(32, 0x5F800000ULL);
12657 // Check whether the sign bit is set.
12658 SDValue SignSet = DAG.getSetCC(dl,
12659 getSetCCResultType(*DAG.getContext(), MVT::i64),
12660 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12663 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12664 SDValue FudgePtr = DAG.getConstantPool(
12665 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12668 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12669 SDValue Zero = DAG.getIntPtrConstant(0);
12670 SDValue Four = DAG.getIntPtrConstant(4);
12671 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12673 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12675 // Load the value out, extending it from f32 to f80.
12676 // FIXME: Avoid the extend by constructing the right constant pool?
12677 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12678 FudgePtr, MachinePointerInfo::getConstantPool(),
12679 MVT::f32, false, false, false, 4);
12680 // Extend everything to 80 bits to force it to be done on x87.
12681 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12682 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12685 std::pair<SDValue,SDValue>
12686 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12687 bool IsSigned, bool IsReplace) const {
12690 EVT DstTy = Op.getValueType();
12692 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12693 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12697 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12698 DstTy.getSimpleVT() >= MVT::i16 &&
12699 "Unknown FP_TO_INT to lower!");
12701 // These are really Legal.
12702 if (DstTy == MVT::i32 &&
12703 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12704 return std::make_pair(SDValue(), SDValue());
12705 if (Subtarget->is64Bit() &&
12706 DstTy == MVT::i64 &&
12707 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12708 return std::make_pair(SDValue(), SDValue());
12710 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12711 // stack slot, or into the FTOL runtime function.
12712 MachineFunction &MF = DAG.getMachineFunction();
12713 unsigned MemSize = DstTy.getSizeInBits()/8;
12714 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12715 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12718 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12719 Opc = X86ISD::WIN_FTOL;
12721 switch (DstTy.getSimpleVT().SimpleTy) {
12722 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12723 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12724 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12725 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12728 SDValue Chain = DAG.getEntryNode();
12729 SDValue Value = Op.getOperand(0);
12730 EVT TheVT = Op.getOperand(0).getValueType();
12731 // FIXME This causes a redundant load/store if the SSE-class value is already
12732 // in memory, such as if it is on the callstack.
12733 if (isScalarFPTypeInSSEReg(TheVT)) {
12734 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12735 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12736 MachinePointerInfo::getFixedStack(SSFI),
12738 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12740 Chain, StackSlot, DAG.getValueType(TheVT)
12743 MachineMemOperand *MMO =
12744 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12745 MachineMemOperand::MOLoad, MemSize, MemSize);
12746 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12747 Chain = Value.getValue(1);
12748 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12749 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12752 MachineMemOperand *MMO =
12753 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12754 MachineMemOperand::MOStore, MemSize, MemSize);
12756 if (Opc != X86ISD::WIN_FTOL) {
12757 // Build the FP_TO_INT*_IN_MEM
12758 SDValue Ops[] = { Chain, Value, StackSlot };
12759 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12761 return std::make_pair(FIST, StackSlot);
12763 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12764 DAG.getVTList(MVT::Other, MVT::Glue),
12766 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12767 MVT::i32, ftol.getValue(1));
12768 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12769 MVT::i32, eax.getValue(2));
12770 SDValue Ops[] = { eax, edx };
12771 SDValue pair = IsReplace
12772 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12773 : DAG.getMergeValues(Ops, DL);
12774 return std::make_pair(pair, SDValue());
12778 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12779 const X86Subtarget *Subtarget) {
12780 MVT VT = Op->getSimpleValueType(0);
12781 SDValue In = Op->getOperand(0);
12782 MVT InVT = In.getSimpleValueType();
12785 // Optimize vectors in AVX mode:
12788 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12789 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12790 // Concat upper and lower parts.
12793 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12794 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12795 // Concat upper and lower parts.
12798 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12799 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12800 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12803 if (Subtarget->hasInt256())
12804 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12806 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12807 SDValue Undef = DAG.getUNDEF(InVT);
12808 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12809 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12810 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12812 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12813 VT.getVectorNumElements()/2);
12815 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12816 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12818 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12821 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12822 SelectionDAG &DAG) {
12823 MVT VT = Op->getSimpleValueType(0);
12824 SDValue In = Op->getOperand(0);
12825 MVT InVT = In.getSimpleValueType();
12827 unsigned int NumElts = VT.getVectorNumElements();
12828 if (NumElts != 8 && NumElts != 16)
12831 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12832 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12834 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
12835 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12836 // Now we have only mask extension
12837 assert(InVT.getVectorElementType() == MVT::i1);
12838 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
12839 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12840 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12841 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12842 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12843 MachinePointerInfo::getConstantPool(),
12844 false, false, false, Alignment);
12846 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
12847 if (VT.is512BitVector())
12849 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12852 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12853 SelectionDAG &DAG) {
12854 if (Subtarget->hasFp256()) {
12855 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12863 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12864 SelectionDAG &DAG) {
12866 MVT VT = Op.getSimpleValueType();
12867 SDValue In = Op.getOperand(0);
12868 MVT SVT = In.getSimpleValueType();
12870 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12871 return LowerZERO_EXTEND_AVX512(Op, DAG);
12873 if (Subtarget->hasFp256()) {
12874 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12879 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12880 VT.getVectorNumElements() != SVT.getVectorNumElements());
12884 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12886 MVT VT = Op.getSimpleValueType();
12887 SDValue In = Op.getOperand(0);
12888 MVT InVT = In.getSimpleValueType();
12890 if (VT == MVT::i1) {
12891 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12892 "Invalid scalar TRUNCATE operation");
12893 if (InVT.getSizeInBits() >= 32)
12895 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12896 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12898 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12899 "Invalid TRUNCATE operation");
12901 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12902 if (VT.getVectorElementType().getSizeInBits() >=8)
12903 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12905 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12906 unsigned NumElts = InVT.getVectorNumElements();
12907 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12908 if (InVT.getSizeInBits() < 512) {
12909 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12910 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12914 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12915 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12916 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12917 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12918 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12919 MachinePointerInfo::getConstantPool(),
12920 false, false, false, Alignment);
12921 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12922 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12923 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12926 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12927 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12928 if (Subtarget->hasInt256()) {
12929 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12930 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12931 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12933 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12934 DAG.getIntPtrConstant(0));
12937 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12938 DAG.getIntPtrConstant(0));
12939 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12940 DAG.getIntPtrConstant(2));
12941 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12942 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12943 static const int ShufMask[] = {0, 2, 4, 6};
12944 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12947 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12948 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12949 if (Subtarget->hasInt256()) {
12950 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12952 SmallVector<SDValue,32> pshufbMask;
12953 for (unsigned i = 0; i < 2; ++i) {
12954 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12955 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12956 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12957 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12958 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12959 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12960 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12961 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12962 for (unsigned j = 0; j < 8; ++j)
12963 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12965 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12966 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12967 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12969 static const int ShufMask[] = {0, 2, -1, -1};
12970 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12972 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12973 DAG.getIntPtrConstant(0));
12974 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12977 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12978 DAG.getIntPtrConstant(0));
12980 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12981 DAG.getIntPtrConstant(4));
12983 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12984 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12986 // The PSHUFB mask:
12987 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12988 -1, -1, -1, -1, -1, -1, -1, -1};
12990 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12991 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12992 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12994 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12995 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12997 // The MOVLHPS Mask:
12998 static const int ShufMask2[] = {0, 1, 4, 5};
12999 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13000 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13003 // Handle truncation of V256 to V128 using shuffles.
13004 if (!VT.is128BitVector() || !InVT.is256BitVector())
13007 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13009 unsigned NumElems = VT.getVectorNumElements();
13010 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13012 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13013 // Prepare truncation shuffle mask
13014 for (unsigned i = 0; i != NumElems; ++i)
13015 MaskVec[i] = i * 2;
13016 SDValue V = DAG.getVectorShuffle(NVT, DL,
13017 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13018 DAG.getUNDEF(NVT), &MaskVec[0]);
13019 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13020 DAG.getIntPtrConstant(0));
13023 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13024 SelectionDAG &DAG) const {
13025 assert(!Op.getSimpleValueType().isVector());
13027 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13028 /*IsSigned=*/ true, /*IsReplace=*/ false);
13029 SDValue FIST = Vals.first, StackSlot = Vals.second;
13030 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13031 if (!FIST.getNode()) return Op;
13033 if (StackSlot.getNode())
13034 // Load the result.
13035 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13036 FIST, StackSlot, MachinePointerInfo(),
13037 false, false, false, 0);
13039 // The node is the result.
13043 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13044 SelectionDAG &DAG) const {
13045 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13046 /*IsSigned=*/ false, /*IsReplace=*/ false);
13047 SDValue FIST = Vals.first, StackSlot = Vals.second;
13048 assert(FIST.getNode() && "Unexpected failure");
13050 if (StackSlot.getNode())
13051 // Load the result.
13052 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13053 FIST, StackSlot, MachinePointerInfo(),
13054 false, false, false, 0);
13056 // The node is the result.
13060 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13062 MVT VT = Op.getSimpleValueType();
13063 SDValue In = Op.getOperand(0);
13064 MVT SVT = In.getSimpleValueType();
13066 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13068 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13069 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13070 In, DAG.getUNDEF(SVT)));
13073 // The only differences between FABS and FNEG are the mask and the logic op.
13074 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13075 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13076 "Wrong opcode for lowering FABS or FNEG.");
13078 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13080 MVT VT = Op.getSimpleValueType();
13081 // Assume scalar op for initialization; update for vector if needed.
13082 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13083 // generate a 16-byte vector constant and logic op even for the scalar case.
13084 // Using a 16-byte mask allows folding the load of the mask with
13085 // the logic op, so it can save (~4 bytes) on code size.
13087 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13088 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13089 // decide if we should generate a 16-byte constant mask when we only need 4 or
13090 // 8 bytes for the scalar case.
13091 if (VT.isVector()) {
13092 EltVT = VT.getVectorElementType();
13093 NumElts = VT.getVectorNumElements();
13096 unsigned EltBits = EltVT.getSizeInBits();
13097 LLVMContext *Context = DAG.getContext();
13098 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13100 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13101 Constant *C = ConstantInt::get(*Context, MaskElt);
13102 C = ConstantVector::getSplat(NumElts, C);
13103 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13104 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13105 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13106 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13107 MachinePointerInfo::getConstantPool(),
13108 false, false, false, Alignment);
13110 if (VT.isVector()) {
13111 // For a vector, cast operands to a vector type, perform the logic op,
13112 // and cast the result back to the original value type.
13113 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13114 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13115 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13116 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13117 return DAG.getNode(ISD::BITCAST, dl, VT,
13118 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13120 // If not vector, then scalar.
13121 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13122 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13125 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13127 LLVMContext *Context = DAG.getContext();
13128 SDValue Op0 = Op.getOperand(0);
13129 SDValue Op1 = Op.getOperand(1);
13131 MVT VT = Op.getSimpleValueType();
13132 MVT SrcVT = Op1.getSimpleValueType();
13134 // If second operand is smaller, extend it first.
13135 if (SrcVT.bitsLT(VT)) {
13136 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13139 // And if it is bigger, shrink it first.
13140 if (SrcVT.bitsGT(VT)) {
13141 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13145 // At this point the operands and the result should have the same
13146 // type, and that won't be f80 since that is not custom lowered.
13148 // First get the sign bit of second operand.
13149 SmallVector<Constant*,4> CV;
13150 if (SrcVT == MVT::f64) {
13151 const fltSemantics &Sem = APFloat::IEEEdouble;
13152 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13153 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13155 const fltSemantics &Sem = APFloat::IEEEsingle;
13156 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13157 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13158 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13159 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13161 Constant *C = ConstantVector::get(CV);
13162 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13163 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13164 MachinePointerInfo::getConstantPool(),
13165 false, false, false, 16);
13166 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13168 // Shift sign bit right or left if the two operands have different types.
13169 if (SrcVT.bitsGT(VT)) {
13170 // Op0 is MVT::f32, Op1 is MVT::f64.
13171 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13172 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13173 DAG.getConstant(32, MVT::i32));
13174 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13175 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13176 DAG.getIntPtrConstant(0));
13179 // Clear first operand sign bit.
13181 if (VT == MVT::f64) {
13182 const fltSemantics &Sem = APFloat::IEEEdouble;
13183 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13184 APInt(64, ~(1ULL << 63)))));
13185 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13187 const fltSemantics &Sem = APFloat::IEEEsingle;
13188 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13189 APInt(32, ~(1U << 31)))));
13190 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13191 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13192 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13194 C = ConstantVector::get(CV);
13195 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13196 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13197 MachinePointerInfo::getConstantPool(),
13198 false, false, false, 16);
13199 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13201 // Or the value with the sign bit.
13202 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13205 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13206 SDValue N0 = Op.getOperand(0);
13208 MVT VT = Op.getSimpleValueType();
13210 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13211 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13212 DAG.getConstant(1, VT));
13213 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13216 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13218 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13219 SelectionDAG &DAG) {
13220 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13222 if (!Subtarget->hasSSE41())
13225 if (!Op->hasOneUse())
13228 SDNode *N = Op.getNode();
13231 SmallVector<SDValue, 8> Opnds;
13232 DenseMap<SDValue, unsigned> VecInMap;
13233 SmallVector<SDValue, 8> VecIns;
13234 EVT VT = MVT::Other;
13236 // Recognize a special case where a vector is casted into wide integer to
13238 Opnds.push_back(N->getOperand(0));
13239 Opnds.push_back(N->getOperand(1));
13241 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13242 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13243 // BFS traverse all OR'd operands.
13244 if (I->getOpcode() == ISD::OR) {
13245 Opnds.push_back(I->getOperand(0));
13246 Opnds.push_back(I->getOperand(1));
13247 // Re-evaluate the number of nodes to be traversed.
13248 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13252 // Quit if a non-EXTRACT_VECTOR_ELT
13253 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13256 // Quit if without a constant index.
13257 SDValue Idx = I->getOperand(1);
13258 if (!isa<ConstantSDNode>(Idx))
13261 SDValue ExtractedFromVec = I->getOperand(0);
13262 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13263 if (M == VecInMap.end()) {
13264 VT = ExtractedFromVec.getValueType();
13265 // Quit if not 128/256-bit vector.
13266 if (!VT.is128BitVector() && !VT.is256BitVector())
13268 // Quit if not the same type.
13269 if (VecInMap.begin() != VecInMap.end() &&
13270 VT != VecInMap.begin()->first.getValueType())
13272 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13273 VecIns.push_back(ExtractedFromVec);
13275 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13278 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13279 "Not extracted from 128-/256-bit vector.");
13281 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13283 for (DenseMap<SDValue, unsigned>::const_iterator
13284 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13285 // Quit if not all elements are used.
13286 if (I->second != FullMask)
13290 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13292 // Cast all vectors into TestVT for PTEST.
13293 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13294 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13296 // If more than one full vectors are evaluated, OR them first before PTEST.
13297 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13298 // Each iteration will OR 2 nodes and append the result until there is only
13299 // 1 node left, i.e. the final OR'd value of all vectors.
13300 SDValue LHS = VecIns[Slot];
13301 SDValue RHS = VecIns[Slot + 1];
13302 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13305 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13306 VecIns.back(), VecIns.back());
13309 /// \brief return true if \c Op has a use that doesn't just read flags.
13310 static bool hasNonFlagsUse(SDValue Op) {
13311 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13313 SDNode *User = *UI;
13314 unsigned UOpNo = UI.getOperandNo();
13315 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13316 // Look pass truncate.
13317 UOpNo = User->use_begin().getOperandNo();
13318 User = *User->use_begin();
13321 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13322 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13328 /// Emit nodes that will be selected as "test Op0,Op0", or something
13330 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13331 SelectionDAG &DAG) const {
13332 if (Op.getValueType() == MVT::i1)
13333 // KORTEST instruction should be selected
13334 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13335 DAG.getConstant(0, Op.getValueType()));
13337 // CF and OF aren't always set the way we want. Determine which
13338 // of these we need.
13339 bool NeedCF = false;
13340 bool NeedOF = false;
13343 case X86::COND_A: case X86::COND_AE:
13344 case X86::COND_B: case X86::COND_BE:
13347 case X86::COND_G: case X86::COND_GE:
13348 case X86::COND_L: case X86::COND_LE:
13349 case X86::COND_O: case X86::COND_NO: {
13350 // Check if we really need to set the
13351 // Overflow flag. If NoSignedWrap is present
13352 // that is not actually needed.
13353 switch (Op->getOpcode()) {
13358 const BinaryWithFlagsSDNode *BinNode =
13359 cast<BinaryWithFlagsSDNode>(Op.getNode());
13360 if (BinNode->hasNoSignedWrap())
13370 // See if we can use the EFLAGS value from the operand instead of
13371 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13372 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13373 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13374 // Emit a CMP with 0, which is the TEST pattern.
13375 //if (Op.getValueType() == MVT::i1)
13376 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13377 // DAG.getConstant(0, MVT::i1));
13378 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13379 DAG.getConstant(0, Op.getValueType()));
13381 unsigned Opcode = 0;
13382 unsigned NumOperands = 0;
13384 // Truncate operations may prevent the merge of the SETCC instruction
13385 // and the arithmetic instruction before it. Attempt to truncate the operands
13386 // of the arithmetic instruction and use a reduced bit-width instruction.
13387 bool NeedTruncation = false;
13388 SDValue ArithOp = Op;
13389 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13390 SDValue Arith = Op->getOperand(0);
13391 // Both the trunc and the arithmetic op need to have one user each.
13392 if (Arith->hasOneUse())
13393 switch (Arith.getOpcode()) {
13400 NeedTruncation = true;
13406 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13407 // which may be the result of a CAST. We use the variable 'Op', which is the
13408 // non-casted variable when we check for possible users.
13409 switch (ArithOp.getOpcode()) {
13411 // Due to an isel shortcoming, be conservative if this add is likely to be
13412 // selected as part of a load-modify-store instruction. When the root node
13413 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13414 // uses of other nodes in the match, such as the ADD in this case. This
13415 // leads to the ADD being left around and reselected, with the result being
13416 // two adds in the output. Alas, even if none our users are stores, that
13417 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13418 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13419 // climbing the DAG back to the root, and it doesn't seem to be worth the
13421 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13422 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13423 if (UI->getOpcode() != ISD::CopyToReg &&
13424 UI->getOpcode() != ISD::SETCC &&
13425 UI->getOpcode() != ISD::STORE)
13428 if (ConstantSDNode *C =
13429 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13430 // An add of one will be selected as an INC.
13431 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13432 Opcode = X86ISD::INC;
13437 // An add of negative one (subtract of one) will be selected as a DEC.
13438 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13439 Opcode = X86ISD::DEC;
13445 // Otherwise use a regular EFLAGS-setting add.
13446 Opcode = X86ISD::ADD;
13451 // If we have a constant logical shift that's only used in a comparison
13452 // against zero turn it into an equivalent AND. This allows turning it into
13453 // a TEST instruction later.
13454 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13455 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13456 EVT VT = Op.getValueType();
13457 unsigned BitWidth = VT.getSizeInBits();
13458 unsigned ShAmt = Op->getConstantOperandVal(1);
13459 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13461 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13462 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13463 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13464 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13466 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13467 DAG.getConstant(Mask, VT));
13468 DAG.ReplaceAllUsesWith(Op, New);
13474 // If the primary and result isn't used, don't bother using X86ISD::AND,
13475 // because a TEST instruction will be better.
13476 if (!hasNonFlagsUse(Op))
13482 // Due to the ISEL shortcoming noted above, be conservative if this op is
13483 // likely to be selected as part of a load-modify-store instruction.
13484 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13485 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13486 if (UI->getOpcode() == ISD::STORE)
13489 // Otherwise use a regular EFLAGS-setting instruction.
13490 switch (ArithOp.getOpcode()) {
13491 default: llvm_unreachable("unexpected operator!");
13492 case ISD::SUB: Opcode = X86ISD::SUB; break;
13493 case ISD::XOR: Opcode = X86ISD::XOR; break;
13494 case ISD::AND: Opcode = X86ISD::AND; break;
13496 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13497 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13498 if (EFLAGS.getNode())
13501 Opcode = X86ISD::OR;
13515 return SDValue(Op.getNode(), 1);
13521 // If we found that truncation is beneficial, perform the truncation and
13523 if (NeedTruncation) {
13524 EVT VT = Op.getValueType();
13525 SDValue WideVal = Op->getOperand(0);
13526 EVT WideVT = WideVal.getValueType();
13527 unsigned ConvertedOp = 0;
13528 // Use a target machine opcode to prevent further DAGCombine
13529 // optimizations that may separate the arithmetic operations
13530 // from the setcc node.
13531 switch (WideVal.getOpcode()) {
13533 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13534 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13535 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13536 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13537 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13541 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13542 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13543 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13544 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13545 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13551 // Emit a CMP with 0, which is the TEST pattern.
13552 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13553 DAG.getConstant(0, Op.getValueType()));
13555 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13556 SmallVector<SDValue, 4> Ops;
13557 for (unsigned i = 0; i != NumOperands; ++i)
13558 Ops.push_back(Op.getOperand(i));
13560 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13561 DAG.ReplaceAllUsesWith(Op, New);
13562 return SDValue(New.getNode(), 1);
13565 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13567 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13568 SDLoc dl, SelectionDAG &DAG) const {
13569 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13570 if (C->getAPIntValue() == 0)
13571 return EmitTest(Op0, X86CC, dl, DAG);
13573 if (Op0.getValueType() == MVT::i1)
13574 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13577 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13578 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13579 // Do the comparison at i32 if it's smaller, besides the Atom case.
13580 // This avoids subregister aliasing issues. Keep the smaller reference
13581 // if we're optimizing for size, however, as that'll allow better folding
13582 // of memory operations.
13583 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13584 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13585 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13586 !Subtarget->isAtom()) {
13587 unsigned ExtendOp =
13588 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13589 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13590 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13592 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13593 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13594 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13596 return SDValue(Sub.getNode(), 1);
13598 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13601 /// Convert a comparison if required by the subtarget.
13602 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13603 SelectionDAG &DAG) const {
13604 // If the subtarget does not support the FUCOMI instruction, floating-point
13605 // comparisons have to be converted.
13606 if (Subtarget->hasCMov() ||
13607 Cmp.getOpcode() != X86ISD::CMP ||
13608 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13609 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13612 // The instruction selector will select an FUCOM instruction instead of
13613 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13614 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13615 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13617 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13618 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13619 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13620 DAG.getConstant(8, MVT::i8));
13621 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13622 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13625 static bool isAllOnes(SDValue V) {
13626 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13627 return C && C->isAllOnesValue();
13630 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13631 /// if it's possible.
13632 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13633 SDLoc dl, SelectionDAG &DAG) const {
13634 SDValue Op0 = And.getOperand(0);
13635 SDValue Op1 = And.getOperand(1);
13636 if (Op0.getOpcode() == ISD::TRUNCATE)
13637 Op0 = Op0.getOperand(0);
13638 if (Op1.getOpcode() == ISD::TRUNCATE)
13639 Op1 = Op1.getOperand(0);
13642 if (Op1.getOpcode() == ISD::SHL)
13643 std::swap(Op0, Op1);
13644 if (Op0.getOpcode() == ISD::SHL) {
13645 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13646 if (And00C->getZExtValue() == 1) {
13647 // If we looked past a truncate, check that it's only truncating away
13649 unsigned BitWidth = Op0.getValueSizeInBits();
13650 unsigned AndBitWidth = And.getValueSizeInBits();
13651 if (BitWidth > AndBitWidth) {
13653 DAG.computeKnownBits(Op0, Zeros, Ones);
13654 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13658 RHS = Op0.getOperand(1);
13660 } else if (Op1.getOpcode() == ISD::Constant) {
13661 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13662 uint64_t AndRHSVal = AndRHS->getZExtValue();
13663 SDValue AndLHS = Op0;
13665 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13666 LHS = AndLHS.getOperand(0);
13667 RHS = AndLHS.getOperand(1);
13670 // Use BT if the immediate can't be encoded in a TEST instruction.
13671 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13673 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13677 if (LHS.getNode()) {
13678 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13679 // instruction. Since the shift amount is in-range-or-undefined, we know
13680 // that doing a bittest on the i32 value is ok. We extend to i32 because
13681 // the encoding for the i16 version is larger than the i32 version.
13682 // Also promote i16 to i32 for performance / code size reason.
13683 if (LHS.getValueType() == MVT::i8 ||
13684 LHS.getValueType() == MVT::i16)
13685 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13687 // If the operand types disagree, extend the shift amount to match. Since
13688 // BT ignores high bits (like shifts) we can use anyextend.
13689 if (LHS.getValueType() != RHS.getValueType())
13690 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13692 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13693 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13694 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13695 DAG.getConstant(Cond, MVT::i8), BT);
13701 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13703 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13708 // SSE Condition code mapping:
13717 switch (SetCCOpcode) {
13718 default: llvm_unreachable("Unexpected SETCC condition");
13720 case ISD::SETEQ: SSECC = 0; break;
13722 case ISD::SETGT: Swap = true; // Fallthrough
13724 case ISD::SETOLT: SSECC = 1; break;
13726 case ISD::SETGE: Swap = true; // Fallthrough
13728 case ISD::SETOLE: SSECC = 2; break;
13729 case ISD::SETUO: SSECC = 3; break;
13731 case ISD::SETNE: SSECC = 4; break;
13732 case ISD::SETULE: Swap = true; // Fallthrough
13733 case ISD::SETUGE: SSECC = 5; break;
13734 case ISD::SETULT: Swap = true; // Fallthrough
13735 case ISD::SETUGT: SSECC = 6; break;
13736 case ISD::SETO: SSECC = 7; break;
13738 case ISD::SETONE: SSECC = 8; break;
13741 std::swap(Op0, Op1);
13746 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13747 // ones, and then concatenate the result back.
13748 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13749 MVT VT = Op.getSimpleValueType();
13751 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13752 "Unsupported value type for operation");
13754 unsigned NumElems = VT.getVectorNumElements();
13756 SDValue CC = Op.getOperand(2);
13758 // Extract the LHS vectors
13759 SDValue LHS = Op.getOperand(0);
13760 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13761 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13763 // Extract the RHS vectors
13764 SDValue RHS = Op.getOperand(1);
13765 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13766 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13768 // Issue the operation on the smaller types and concatenate the result back
13769 MVT EltVT = VT.getVectorElementType();
13770 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13771 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13772 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13773 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13776 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13777 const X86Subtarget *Subtarget) {
13778 SDValue Op0 = Op.getOperand(0);
13779 SDValue Op1 = Op.getOperand(1);
13780 SDValue CC = Op.getOperand(2);
13781 MVT VT = Op.getSimpleValueType();
13784 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13785 Op.getValueType().getScalarType() == MVT::i1 &&
13786 "Cannot set masked compare for this operation");
13788 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13790 bool Unsigned = false;
13793 switch (SetCCOpcode) {
13794 default: llvm_unreachable("Unexpected SETCC condition");
13795 case ISD::SETNE: SSECC = 4; break;
13796 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13797 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13798 case ISD::SETLT: Swap = true; //fall-through
13799 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13800 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13801 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13802 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13803 case ISD::SETULE: Unsigned = true; //fall-through
13804 case ISD::SETLE: SSECC = 2; break;
13808 std::swap(Op0, Op1);
13810 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13811 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13812 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13813 DAG.getConstant(SSECC, MVT::i8));
13816 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13817 /// operand \p Op1. If non-trivial (for example because it's not constant)
13818 /// return an empty value.
13819 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13821 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13825 MVT VT = Op1.getSimpleValueType();
13826 MVT EVT = VT.getVectorElementType();
13827 unsigned n = VT.getVectorNumElements();
13828 SmallVector<SDValue, 8> ULTOp1;
13830 for (unsigned i = 0; i < n; ++i) {
13831 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13832 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13835 // Avoid underflow.
13836 APInt Val = Elt->getAPIntValue();
13840 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13843 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13846 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13847 SelectionDAG &DAG) {
13848 SDValue Op0 = Op.getOperand(0);
13849 SDValue Op1 = Op.getOperand(1);
13850 SDValue CC = Op.getOperand(2);
13851 MVT VT = Op.getSimpleValueType();
13852 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13853 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13858 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13859 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13862 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13863 unsigned Opc = X86ISD::CMPP;
13864 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13865 assert(VT.getVectorNumElements() <= 16);
13866 Opc = X86ISD::CMPM;
13868 // In the two special cases we can't handle, emit two comparisons.
13871 unsigned CombineOpc;
13872 if (SetCCOpcode == ISD::SETUEQ) {
13873 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13875 assert(SetCCOpcode == ISD::SETONE);
13876 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13879 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13880 DAG.getConstant(CC0, MVT::i8));
13881 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13882 DAG.getConstant(CC1, MVT::i8));
13883 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13885 // Handle all other FP comparisons here.
13886 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13887 DAG.getConstant(SSECC, MVT::i8));
13890 // Break 256-bit integer vector compare into smaller ones.
13891 if (VT.is256BitVector() && !Subtarget->hasInt256())
13892 return Lower256IntVSETCC(Op, DAG);
13894 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13895 EVT OpVT = Op1.getValueType();
13896 if (Subtarget->hasAVX512()) {
13897 if (Op1.getValueType().is512BitVector() ||
13898 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13899 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13900 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13902 // In AVX-512 architecture setcc returns mask with i1 elements,
13903 // But there is no compare instruction for i8 and i16 elements in KNL.
13904 // We are not talking about 512-bit operands in this case, these
13905 // types are illegal.
13907 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13908 OpVT.getVectorElementType().getSizeInBits() >= 8))
13909 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13910 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13913 // We are handling one of the integer comparisons here. Since SSE only has
13914 // GT and EQ comparisons for integer, swapping operands and multiple
13915 // operations may be required for some comparisons.
13917 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13918 bool Subus = false;
13920 switch (SetCCOpcode) {
13921 default: llvm_unreachable("Unexpected SETCC condition");
13922 case ISD::SETNE: Invert = true;
13923 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13924 case ISD::SETLT: Swap = true;
13925 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13926 case ISD::SETGE: Swap = true;
13927 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13928 Invert = true; break;
13929 case ISD::SETULT: Swap = true;
13930 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13931 FlipSigns = true; break;
13932 case ISD::SETUGE: Swap = true;
13933 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13934 FlipSigns = true; Invert = true; break;
13937 // Special case: Use min/max operations for SETULE/SETUGE
13938 MVT VET = VT.getVectorElementType();
13940 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13941 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13944 switch (SetCCOpcode) {
13946 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13947 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13950 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13953 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13954 if (!MinMax && hasSubus) {
13955 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13957 // t = psubus Op0, Op1
13958 // pcmpeq t, <0..0>
13959 switch (SetCCOpcode) {
13961 case ISD::SETULT: {
13962 // If the comparison is against a constant we can turn this into a
13963 // setule. With psubus, setule does not require a swap. This is
13964 // beneficial because the constant in the register is no longer
13965 // destructed as the destination so it can be hoisted out of a loop.
13966 // Only do this pre-AVX since vpcmp* is no longer destructive.
13967 if (Subtarget->hasAVX())
13969 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13970 if (ULEOp1.getNode()) {
13972 Subus = true; Invert = false; Swap = false;
13976 // Psubus is better than flip-sign because it requires no inversion.
13977 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13978 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13982 Opc = X86ISD::SUBUS;
13988 std::swap(Op0, Op1);
13990 // Check that the operation in question is available (most are plain SSE2,
13991 // but PCMPGTQ and PCMPEQQ have different requirements).
13992 if (VT == MVT::v2i64) {
13993 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13994 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13996 // First cast everything to the right type.
13997 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13998 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14000 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14001 // bits of the inputs before performing those operations. The lower
14002 // compare is always unsigned.
14005 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14007 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14008 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14009 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14010 Sign, Zero, Sign, Zero);
14012 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14013 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14015 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14016 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14017 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14019 // Create masks for only the low parts/high parts of the 64 bit integers.
14020 static const int MaskHi[] = { 1, 1, 3, 3 };
14021 static const int MaskLo[] = { 0, 0, 2, 2 };
14022 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14023 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14024 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14026 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14027 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14030 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14032 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14035 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14036 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14037 // pcmpeqd + pshufd + pand.
14038 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14040 // First cast everything to the right type.
14041 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14042 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14045 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14047 // Make sure the lower and upper halves are both all-ones.
14048 static const int Mask[] = { 1, 0, 3, 2 };
14049 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14050 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14053 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14055 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14059 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14060 // bits of the inputs before performing those operations.
14062 EVT EltVT = VT.getVectorElementType();
14063 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14064 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14065 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14068 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14070 // If the logical-not of the result is required, perform that now.
14072 Result = DAG.getNOT(dl, Result, VT);
14075 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14078 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14079 getZeroVector(VT, Subtarget, DAG, dl));
14084 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14086 MVT VT = Op.getSimpleValueType();
14088 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14090 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14091 && "SetCC type must be 8-bit or 1-bit integer");
14092 SDValue Op0 = Op.getOperand(0);
14093 SDValue Op1 = Op.getOperand(1);
14095 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14097 // Optimize to BT if possible.
14098 // Lower (X & (1 << N)) == 0 to BT(X, N).
14099 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14100 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14101 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14102 Op1.getOpcode() == ISD::Constant &&
14103 cast<ConstantSDNode>(Op1)->isNullValue() &&
14104 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14105 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14106 if (NewSetCC.getNode())
14110 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14112 if (Op1.getOpcode() == ISD::Constant &&
14113 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14114 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14115 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14117 // If the input is a setcc, then reuse the input setcc or use a new one with
14118 // the inverted condition.
14119 if (Op0.getOpcode() == X86ISD::SETCC) {
14120 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14121 bool Invert = (CC == ISD::SETNE) ^
14122 cast<ConstantSDNode>(Op1)->isNullValue();
14126 CCode = X86::GetOppositeBranchCondition(CCode);
14127 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14128 DAG.getConstant(CCode, MVT::i8),
14129 Op0.getOperand(1));
14131 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14135 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14136 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14137 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14139 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14140 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14143 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14144 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14145 if (X86CC == X86::COND_INVALID)
14148 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14149 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14150 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14151 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14153 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14157 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14158 static bool isX86LogicalCmp(SDValue Op) {
14159 unsigned Opc = Op.getNode()->getOpcode();
14160 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14161 Opc == X86ISD::SAHF)
14163 if (Op.getResNo() == 1 &&
14164 (Opc == X86ISD::ADD ||
14165 Opc == X86ISD::SUB ||
14166 Opc == X86ISD::ADC ||
14167 Opc == X86ISD::SBB ||
14168 Opc == X86ISD::SMUL ||
14169 Opc == X86ISD::UMUL ||
14170 Opc == X86ISD::INC ||
14171 Opc == X86ISD::DEC ||
14172 Opc == X86ISD::OR ||
14173 Opc == X86ISD::XOR ||
14174 Opc == X86ISD::AND))
14177 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14183 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14184 if (V.getOpcode() != ISD::TRUNCATE)
14187 SDValue VOp0 = V.getOperand(0);
14188 unsigned InBits = VOp0.getValueSizeInBits();
14189 unsigned Bits = V.getValueSizeInBits();
14190 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14193 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14194 bool addTest = true;
14195 SDValue Cond = Op.getOperand(0);
14196 SDValue Op1 = Op.getOperand(1);
14197 SDValue Op2 = Op.getOperand(2);
14199 EVT VT = Op1.getValueType();
14202 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14203 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14204 // sequence later on.
14205 if (Cond.getOpcode() == ISD::SETCC &&
14206 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14207 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14208 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14209 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14210 int SSECC = translateX86FSETCC(
14211 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14214 if (Subtarget->hasAVX512()) {
14215 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14216 DAG.getConstant(SSECC, MVT::i8));
14217 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14219 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14220 DAG.getConstant(SSECC, MVT::i8));
14221 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14222 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14223 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14227 if (Cond.getOpcode() == ISD::SETCC) {
14228 SDValue NewCond = LowerSETCC(Cond, DAG);
14229 if (NewCond.getNode())
14233 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14234 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14235 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14236 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14237 if (Cond.getOpcode() == X86ISD::SETCC &&
14238 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14239 isZero(Cond.getOperand(1).getOperand(1))) {
14240 SDValue Cmp = Cond.getOperand(1);
14242 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14244 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14245 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14246 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14248 SDValue CmpOp0 = Cmp.getOperand(0);
14249 // Apply further optimizations for special cases
14250 // (select (x != 0), -1, 0) -> neg & sbb
14251 // (select (x == 0), 0, -1) -> neg & sbb
14252 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14253 if (YC->isNullValue() &&
14254 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14255 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14256 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14257 DAG.getConstant(0, CmpOp0.getValueType()),
14259 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14260 DAG.getConstant(X86::COND_B, MVT::i8),
14261 SDValue(Neg.getNode(), 1));
14265 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14266 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14267 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14269 SDValue Res = // Res = 0 or -1.
14270 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14271 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14273 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14274 Res = DAG.getNOT(DL, Res, Res.getValueType());
14276 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14277 if (!N2C || !N2C->isNullValue())
14278 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14283 // Look past (and (setcc_carry (cmp ...)), 1).
14284 if (Cond.getOpcode() == ISD::AND &&
14285 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14286 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14287 if (C && C->getAPIntValue() == 1)
14288 Cond = Cond.getOperand(0);
14291 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14292 // setting operand in place of the X86ISD::SETCC.
14293 unsigned CondOpcode = Cond.getOpcode();
14294 if (CondOpcode == X86ISD::SETCC ||
14295 CondOpcode == X86ISD::SETCC_CARRY) {
14296 CC = Cond.getOperand(0);
14298 SDValue Cmp = Cond.getOperand(1);
14299 unsigned Opc = Cmp.getOpcode();
14300 MVT VT = Op.getSimpleValueType();
14302 bool IllegalFPCMov = false;
14303 if (VT.isFloatingPoint() && !VT.isVector() &&
14304 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14305 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14307 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14308 Opc == X86ISD::BT) { // FIXME
14312 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14313 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14314 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14315 Cond.getOperand(0).getValueType() != MVT::i8)) {
14316 SDValue LHS = Cond.getOperand(0);
14317 SDValue RHS = Cond.getOperand(1);
14318 unsigned X86Opcode;
14321 switch (CondOpcode) {
14322 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14323 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14324 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14325 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14326 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14327 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14328 default: llvm_unreachable("unexpected overflowing operator");
14330 if (CondOpcode == ISD::UMULO)
14331 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14334 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14336 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14338 if (CondOpcode == ISD::UMULO)
14339 Cond = X86Op.getValue(2);
14341 Cond = X86Op.getValue(1);
14343 CC = DAG.getConstant(X86Cond, MVT::i8);
14348 // Look pass the truncate if the high bits are known zero.
14349 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14350 Cond = Cond.getOperand(0);
14352 // We know the result of AND is compared against zero. Try to match
14354 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14355 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14356 if (NewSetCC.getNode()) {
14357 CC = NewSetCC.getOperand(0);
14358 Cond = NewSetCC.getOperand(1);
14365 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14366 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14369 // a < b ? -1 : 0 -> RES = ~setcc_carry
14370 // a < b ? 0 : -1 -> RES = setcc_carry
14371 // a >= b ? -1 : 0 -> RES = setcc_carry
14372 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14373 if (Cond.getOpcode() == X86ISD::SUB) {
14374 Cond = ConvertCmpIfNecessary(Cond, DAG);
14375 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14377 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14378 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14379 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14380 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14381 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14382 return DAG.getNOT(DL, Res, Res.getValueType());
14387 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14388 // widen the cmov and push the truncate through. This avoids introducing a new
14389 // branch during isel and doesn't add any extensions.
14390 if (Op.getValueType() == MVT::i8 &&
14391 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14392 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14393 if (T1.getValueType() == T2.getValueType() &&
14394 // Blacklist CopyFromReg to avoid partial register stalls.
14395 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14396 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14397 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14398 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14402 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14403 // condition is true.
14404 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14405 SDValue Ops[] = { Op2, Op1, CC, Cond };
14406 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14409 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14410 MVT VT = Op->getSimpleValueType(0);
14411 SDValue In = Op->getOperand(0);
14412 MVT InVT = In.getSimpleValueType();
14415 unsigned int NumElts = VT.getVectorNumElements();
14416 if (NumElts != 8 && NumElts != 16)
14419 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14420 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14422 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14423 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14425 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14426 Constant *C = ConstantInt::get(*DAG.getContext(),
14427 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14429 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14430 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14431 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14432 MachinePointerInfo::getConstantPool(),
14433 false, false, false, Alignment);
14434 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14435 if (VT.is512BitVector())
14437 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14440 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14441 SelectionDAG &DAG) {
14442 MVT VT = Op->getSimpleValueType(0);
14443 SDValue In = Op->getOperand(0);
14444 MVT InVT = In.getSimpleValueType();
14447 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14448 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14450 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14451 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14452 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14455 if (Subtarget->hasInt256())
14456 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14458 // Optimize vectors in AVX mode
14459 // Sign extend v8i16 to v8i32 and
14462 // Divide input vector into two parts
14463 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14464 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14465 // concat the vectors to original VT
14467 unsigned NumElems = InVT.getVectorNumElements();
14468 SDValue Undef = DAG.getUNDEF(InVT);
14470 SmallVector<int,8> ShufMask1(NumElems, -1);
14471 for (unsigned i = 0; i != NumElems/2; ++i)
14474 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14476 SmallVector<int,8> ShufMask2(NumElems, -1);
14477 for (unsigned i = 0; i != NumElems/2; ++i)
14478 ShufMask2[i] = i + NumElems/2;
14480 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14482 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14483 VT.getVectorNumElements()/2);
14485 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14486 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14488 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14491 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14492 // may emit an illegal shuffle but the expansion is still better than scalar
14493 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14494 // we'll emit a shuffle and a arithmetic shift.
14495 // TODO: It is possible to support ZExt by zeroing the undef values during
14496 // the shuffle phase or after the shuffle.
14497 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14498 SelectionDAG &DAG) {
14499 MVT RegVT = Op.getSimpleValueType();
14500 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14501 assert(RegVT.isInteger() &&
14502 "We only custom lower integer vector sext loads.");
14504 // Nothing useful we can do without SSE2 shuffles.
14505 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14507 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14509 EVT MemVT = Ld->getMemoryVT();
14510 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14511 unsigned RegSz = RegVT.getSizeInBits();
14513 ISD::LoadExtType Ext = Ld->getExtensionType();
14515 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14516 && "Only anyext and sext are currently implemented.");
14517 assert(MemVT != RegVT && "Cannot extend to the same type");
14518 assert(MemVT.isVector() && "Must load a vector from memory");
14520 unsigned NumElems = RegVT.getVectorNumElements();
14521 unsigned MemSz = MemVT.getSizeInBits();
14522 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14524 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14525 // The only way in which we have a legal 256-bit vector result but not the
14526 // integer 256-bit operations needed to directly lower a sextload is if we
14527 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14528 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14529 // correctly legalized. We do this late to allow the canonical form of
14530 // sextload to persist throughout the rest of the DAG combiner -- it wants
14531 // to fold together any extensions it can, and so will fuse a sign_extend
14532 // of an sextload into a sextload targeting a wider value.
14534 if (MemSz == 128) {
14535 // Just switch this to a normal load.
14536 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14537 "it must be a legal 128-bit vector "
14539 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14540 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14541 Ld->isInvariant(), Ld->getAlignment());
14543 assert(MemSz < 128 &&
14544 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14545 // Do an sext load to a 128-bit vector type. We want to use the same
14546 // number of elements, but elements half as wide. This will end up being
14547 // recursively lowered by this routine, but will succeed as we definitely
14548 // have all the necessary features if we're using AVX1.
14550 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14551 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14553 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14554 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14555 Ld->isNonTemporal(), Ld->isInvariant(),
14556 Ld->getAlignment());
14559 // Replace chain users with the new chain.
14560 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14561 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14563 // Finally, do a normal sign-extend to the desired register.
14564 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14567 // All sizes must be a power of two.
14568 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14569 "Non-power-of-two elements are not custom lowered!");
14571 // Attempt to load the original value using scalar loads.
14572 // Find the largest scalar type that divides the total loaded size.
14573 MVT SclrLoadTy = MVT::i8;
14574 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14575 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14576 MVT Tp = (MVT::SimpleValueType)tp;
14577 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14582 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14583 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14585 SclrLoadTy = MVT::f64;
14587 // Calculate the number of scalar loads that we need to perform
14588 // in order to load our vector from memory.
14589 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14591 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14592 "Can only lower sext loads with a single scalar load!");
14594 unsigned loadRegZize = RegSz;
14595 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14598 // Represent our vector as a sequence of elements which are the
14599 // largest scalar that we can load.
14600 EVT LoadUnitVecVT = EVT::getVectorVT(
14601 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14603 // Represent the data using the same element type that is stored in
14604 // memory. In practice, we ''widen'' MemVT.
14606 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14607 loadRegZize / MemVT.getScalarType().getSizeInBits());
14609 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14610 "Invalid vector type");
14612 // We can't shuffle using an illegal type.
14613 assert(TLI.isTypeLegal(WideVecVT) &&
14614 "We only lower types that form legal widened vector types");
14616 SmallVector<SDValue, 8> Chains;
14617 SDValue Ptr = Ld->getBasePtr();
14618 SDValue Increment =
14619 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14620 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14622 for (unsigned i = 0; i < NumLoads; ++i) {
14623 // Perform a single load.
14624 SDValue ScalarLoad =
14625 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14626 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14627 Ld->getAlignment());
14628 Chains.push_back(ScalarLoad.getValue(1));
14629 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14630 // another round of DAGCombining.
14632 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14634 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14635 ScalarLoad, DAG.getIntPtrConstant(i));
14637 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14640 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14642 // Bitcast the loaded value to a vector of the original element type, in
14643 // the size of the target vector type.
14644 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14645 unsigned SizeRatio = RegSz / MemSz;
14647 if (Ext == ISD::SEXTLOAD) {
14648 // If we have SSE4.1, we can directly emit a VSEXT node.
14649 if (Subtarget->hasSSE41()) {
14650 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14651 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14655 // Otherwise we'll shuffle the small elements in the high bits of the
14656 // larger type and perform an arithmetic shift. If the shift is not legal
14657 // it's better to scalarize.
14658 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14659 "We can't implement a sext load without an arithmetic right shift!");
14661 // Redistribute the loaded elements into the different locations.
14662 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14663 for (unsigned i = 0; i != NumElems; ++i)
14664 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14666 SDValue Shuff = DAG.getVectorShuffle(
14667 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14669 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14671 // Build the arithmetic shift.
14672 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14673 MemVT.getVectorElementType().getSizeInBits();
14675 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14677 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14681 // Redistribute the loaded elements into the different locations.
14682 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14683 for (unsigned i = 0; i != NumElems; ++i)
14684 ShuffleVec[i * SizeRatio] = i;
14686 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14687 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14689 // Bitcast to the requested type.
14690 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14691 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14695 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14696 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14697 // from the AND / OR.
14698 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14699 Opc = Op.getOpcode();
14700 if (Opc != ISD::OR && Opc != ISD::AND)
14702 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14703 Op.getOperand(0).hasOneUse() &&
14704 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14705 Op.getOperand(1).hasOneUse());
14708 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14709 // 1 and that the SETCC node has a single use.
14710 static bool isXor1OfSetCC(SDValue Op) {
14711 if (Op.getOpcode() != ISD::XOR)
14713 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14714 if (N1C && N1C->getAPIntValue() == 1) {
14715 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14716 Op.getOperand(0).hasOneUse();
14721 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14722 bool addTest = true;
14723 SDValue Chain = Op.getOperand(0);
14724 SDValue Cond = Op.getOperand(1);
14725 SDValue Dest = Op.getOperand(2);
14728 bool Inverted = false;
14730 if (Cond.getOpcode() == ISD::SETCC) {
14731 // Check for setcc([su]{add,sub,mul}o == 0).
14732 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14733 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14734 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14735 Cond.getOperand(0).getResNo() == 1 &&
14736 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14737 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14738 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14739 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14740 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14741 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14743 Cond = Cond.getOperand(0);
14745 SDValue NewCond = LowerSETCC(Cond, DAG);
14746 if (NewCond.getNode())
14751 // FIXME: LowerXALUO doesn't handle these!!
14752 else if (Cond.getOpcode() == X86ISD::ADD ||
14753 Cond.getOpcode() == X86ISD::SUB ||
14754 Cond.getOpcode() == X86ISD::SMUL ||
14755 Cond.getOpcode() == X86ISD::UMUL)
14756 Cond = LowerXALUO(Cond, DAG);
14759 // Look pass (and (setcc_carry (cmp ...)), 1).
14760 if (Cond.getOpcode() == ISD::AND &&
14761 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14762 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14763 if (C && C->getAPIntValue() == 1)
14764 Cond = Cond.getOperand(0);
14767 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14768 // setting operand in place of the X86ISD::SETCC.
14769 unsigned CondOpcode = Cond.getOpcode();
14770 if (CondOpcode == X86ISD::SETCC ||
14771 CondOpcode == X86ISD::SETCC_CARRY) {
14772 CC = Cond.getOperand(0);
14774 SDValue Cmp = Cond.getOperand(1);
14775 unsigned Opc = Cmp.getOpcode();
14776 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14777 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14781 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14785 // These can only come from an arithmetic instruction with overflow,
14786 // e.g. SADDO, UADDO.
14787 Cond = Cond.getNode()->getOperand(1);
14793 CondOpcode = Cond.getOpcode();
14794 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14795 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14796 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14797 Cond.getOperand(0).getValueType() != MVT::i8)) {
14798 SDValue LHS = Cond.getOperand(0);
14799 SDValue RHS = Cond.getOperand(1);
14800 unsigned X86Opcode;
14803 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14804 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14806 switch (CondOpcode) {
14807 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14809 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14811 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14814 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14815 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14817 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14819 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14822 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14823 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14824 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14825 default: llvm_unreachable("unexpected overflowing operator");
14828 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14829 if (CondOpcode == ISD::UMULO)
14830 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14833 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14835 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14837 if (CondOpcode == ISD::UMULO)
14838 Cond = X86Op.getValue(2);
14840 Cond = X86Op.getValue(1);
14842 CC = DAG.getConstant(X86Cond, MVT::i8);
14846 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14847 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14848 if (CondOpc == ISD::OR) {
14849 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14850 // two branches instead of an explicit OR instruction with a
14852 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14853 isX86LogicalCmp(Cmp)) {
14854 CC = Cond.getOperand(0).getOperand(0);
14855 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14856 Chain, Dest, CC, Cmp);
14857 CC = Cond.getOperand(1).getOperand(0);
14861 } else { // ISD::AND
14862 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14863 // two branches instead of an explicit AND instruction with a
14864 // separate test. However, we only do this if this block doesn't
14865 // have a fall-through edge, because this requires an explicit
14866 // jmp when the condition is false.
14867 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14868 isX86LogicalCmp(Cmp) &&
14869 Op.getNode()->hasOneUse()) {
14870 X86::CondCode CCode =
14871 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14872 CCode = X86::GetOppositeBranchCondition(CCode);
14873 CC = DAG.getConstant(CCode, MVT::i8);
14874 SDNode *User = *Op.getNode()->use_begin();
14875 // Look for an unconditional branch following this conditional branch.
14876 // We need this because we need to reverse the successors in order
14877 // to implement FCMP_OEQ.
14878 if (User->getOpcode() == ISD::BR) {
14879 SDValue FalseBB = User->getOperand(1);
14881 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14882 assert(NewBR == User);
14886 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14887 Chain, Dest, CC, Cmp);
14888 X86::CondCode CCode =
14889 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14890 CCode = X86::GetOppositeBranchCondition(CCode);
14891 CC = DAG.getConstant(CCode, MVT::i8);
14897 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14898 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14899 // It should be transformed during dag combiner except when the condition
14900 // is set by a arithmetics with overflow node.
14901 X86::CondCode CCode =
14902 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14903 CCode = X86::GetOppositeBranchCondition(CCode);
14904 CC = DAG.getConstant(CCode, MVT::i8);
14905 Cond = Cond.getOperand(0).getOperand(1);
14907 } else if (Cond.getOpcode() == ISD::SETCC &&
14908 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14909 // For FCMP_OEQ, we can emit
14910 // two branches instead of an explicit AND instruction with a
14911 // separate test. However, we only do this if this block doesn't
14912 // have a fall-through edge, because this requires an explicit
14913 // jmp when the condition is false.
14914 if (Op.getNode()->hasOneUse()) {
14915 SDNode *User = *Op.getNode()->use_begin();
14916 // Look for an unconditional branch following this conditional branch.
14917 // We need this because we need to reverse the successors in order
14918 // to implement FCMP_OEQ.
14919 if (User->getOpcode() == ISD::BR) {
14920 SDValue FalseBB = User->getOperand(1);
14922 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14923 assert(NewBR == User);
14927 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14928 Cond.getOperand(0), Cond.getOperand(1));
14929 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14930 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14931 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14932 Chain, Dest, CC, Cmp);
14933 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14938 } else if (Cond.getOpcode() == ISD::SETCC &&
14939 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14940 // For FCMP_UNE, we can emit
14941 // two branches instead of an explicit AND instruction with a
14942 // separate test. However, we only do this if this block doesn't
14943 // have a fall-through edge, because this requires an explicit
14944 // jmp when the condition is false.
14945 if (Op.getNode()->hasOneUse()) {
14946 SDNode *User = *Op.getNode()->use_begin();
14947 // Look for an unconditional branch following this conditional branch.
14948 // We need this because we need to reverse the successors in order
14949 // to implement FCMP_UNE.
14950 if (User->getOpcode() == ISD::BR) {
14951 SDValue FalseBB = User->getOperand(1);
14953 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14954 assert(NewBR == User);
14957 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14958 Cond.getOperand(0), Cond.getOperand(1));
14959 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14960 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14961 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14962 Chain, Dest, CC, Cmp);
14963 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14973 // Look pass the truncate if the high bits are known zero.
14974 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14975 Cond = Cond.getOperand(0);
14977 // We know the result of AND is compared against zero. Try to match
14979 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14980 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14981 if (NewSetCC.getNode()) {
14982 CC = NewSetCC.getOperand(0);
14983 Cond = NewSetCC.getOperand(1);
14990 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14991 CC = DAG.getConstant(X86Cond, MVT::i8);
14992 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14994 Cond = ConvertCmpIfNecessary(Cond, DAG);
14995 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14996 Chain, Dest, CC, Cond);
14999 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15000 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15001 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15002 // that the guard pages used by the OS virtual memory manager are allocated in
15003 // correct sequence.
15005 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15006 SelectionDAG &DAG) const {
15007 MachineFunction &MF = DAG.getMachineFunction();
15008 bool SplitStack = MF.shouldSplitStack();
15009 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15014 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15015 SDNode* Node = Op.getNode();
15017 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15018 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15019 " not tell us which reg is the stack pointer!");
15020 EVT VT = Node->getValueType(0);
15021 SDValue Tmp1 = SDValue(Node, 0);
15022 SDValue Tmp2 = SDValue(Node, 1);
15023 SDValue Tmp3 = Node->getOperand(2);
15024 SDValue Chain = Tmp1.getOperand(0);
15026 // Chain the dynamic stack allocation so that it doesn't modify the stack
15027 // pointer when other instructions are using the stack.
15028 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15031 SDValue Size = Tmp2.getOperand(1);
15032 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15033 Chain = SP.getValue(1);
15034 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15035 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15036 unsigned StackAlign = TFI.getStackAlignment();
15037 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15038 if (Align > StackAlign)
15039 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15040 DAG.getConstant(-(uint64_t)Align, VT));
15041 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15043 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15044 DAG.getIntPtrConstant(0, true), SDValue(),
15047 SDValue Ops[2] = { Tmp1, Tmp2 };
15048 return DAG.getMergeValues(Ops, dl);
15052 SDValue Chain = Op.getOperand(0);
15053 SDValue Size = Op.getOperand(1);
15054 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15055 EVT VT = Op.getNode()->getValueType(0);
15057 bool Is64Bit = Subtarget->is64Bit();
15058 EVT SPTy = getPointerTy();
15061 MachineRegisterInfo &MRI = MF.getRegInfo();
15064 // The 64 bit implementation of segmented stacks needs to clobber both r10
15065 // r11. This makes it impossible to use it along with nested parameters.
15066 const Function *F = MF.getFunction();
15068 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15070 if (I->hasNestAttr())
15071 report_fatal_error("Cannot use segmented stacks with functions that "
15072 "have nested arguments.");
15075 const TargetRegisterClass *AddrRegClass =
15076 getRegClassFor(getPointerTy());
15077 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15078 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15079 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15080 DAG.getRegister(Vreg, SPTy));
15081 SDValue Ops1[2] = { Value, Chain };
15082 return DAG.getMergeValues(Ops1, dl);
15085 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15087 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15088 Flag = Chain.getValue(1);
15089 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15091 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15093 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15094 DAG.getSubtarget().getRegisterInfo());
15095 unsigned SPReg = RegInfo->getStackRegister();
15096 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15097 Chain = SP.getValue(1);
15100 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15101 DAG.getConstant(-(uint64_t)Align, VT));
15102 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15105 SDValue Ops1[2] = { SP, Chain };
15106 return DAG.getMergeValues(Ops1, dl);
15110 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15111 MachineFunction &MF = DAG.getMachineFunction();
15112 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15114 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15117 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15118 // vastart just stores the address of the VarArgsFrameIndex slot into the
15119 // memory location argument.
15120 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15122 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15123 MachinePointerInfo(SV), false, false, 0);
15127 // gp_offset (0 - 6 * 8)
15128 // fp_offset (48 - 48 + 8 * 16)
15129 // overflow_arg_area (point to parameters coming in memory).
15131 SmallVector<SDValue, 8> MemOps;
15132 SDValue FIN = Op.getOperand(1);
15134 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15135 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15137 FIN, MachinePointerInfo(SV), false, false, 0);
15138 MemOps.push_back(Store);
15141 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15142 FIN, DAG.getIntPtrConstant(4));
15143 Store = DAG.getStore(Op.getOperand(0), DL,
15144 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15146 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15147 MemOps.push_back(Store);
15149 // Store ptr to overflow_arg_area
15150 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15151 FIN, DAG.getIntPtrConstant(4));
15152 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15154 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15155 MachinePointerInfo(SV, 8),
15157 MemOps.push_back(Store);
15159 // Store ptr to reg_save_area.
15160 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15161 FIN, DAG.getIntPtrConstant(8));
15162 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15164 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15165 MachinePointerInfo(SV, 16), false, false, 0);
15166 MemOps.push_back(Store);
15167 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15170 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15171 assert(Subtarget->is64Bit() &&
15172 "LowerVAARG only handles 64-bit va_arg!");
15173 assert((Subtarget->isTargetLinux() ||
15174 Subtarget->isTargetDarwin()) &&
15175 "Unhandled target in LowerVAARG");
15176 assert(Op.getNode()->getNumOperands() == 4);
15177 SDValue Chain = Op.getOperand(0);
15178 SDValue SrcPtr = Op.getOperand(1);
15179 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15180 unsigned Align = Op.getConstantOperandVal(3);
15183 EVT ArgVT = Op.getNode()->getValueType(0);
15184 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15185 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15188 // Decide which area this value should be read from.
15189 // TODO: Implement the AMD64 ABI in its entirety. This simple
15190 // selection mechanism works only for the basic types.
15191 if (ArgVT == MVT::f80) {
15192 llvm_unreachable("va_arg for f80 not yet implemented");
15193 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15194 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15195 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15196 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15198 llvm_unreachable("Unhandled argument type in LowerVAARG");
15201 if (ArgMode == 2) {
15202 // Sanity Check: Make sure using fp_offset makes sense.
15203 assert(!DAG.getTarget().Options.UseSoftFloat &&
15204 !(DAG.getMachineFunction()
15205 .getFunction()->getAttributes()
15206 .hasAttribute(AttributeSet::FunctionIndex,
15207 Attribute::NoImplicitFloat)) &&
15208 Subtarget->hasSSE1());
15211 // Insert VAARG_64 node into the DAG
15212 // VAARG_64 returns two values: Variable Argument Address, Chain
15213 SmallVector<SDValue, 11> InstOps;
15214 InstOps.push_back(Chain);
15215 InstOps.push_back(SrcPtr);
15216 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15217 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15218 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15219 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15220 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15221 VTs, InstOps, MVT::i64,
15222 MachinePointerInfo(SV),
15224 /*Volatile=*/false,
15226 /*WriteMem=*/true);
15227 Chain = VAARG.getValue(1);
15229 // Load the next argument and return it
15230 return DAG.getLoad(ArgVT, dl,
15233 MachinePointerInfo(),
15234 false, false, false, 0);
15237 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15238 SelectionDAG &DAG) {
15239 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15240 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15241 SDValue Chain = Op.getOperand(0);
15242 SDValue DstPtr = Op.getOperand(1);
15243 SDValue SrcPtr = Op.getOperand(2);
15244 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15245 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15248 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15249 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15251 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15254 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15255 // amount is a constant. Takes immediate version of shift as input.
15256 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15257 SDValue SrcOp, uint64_t ShiftAmt,
15258 SelectionDAG &DAG) {
15259 MVT ElementType = VT.getVectorElementType();
15261 // Fold this packed shift into its first operand if ShiftAmt is 0.
15265 // Check for ShiftAmt >= element width
15266 if (ShiftAmt >= ElementType.getSizeInBits()) {
15267 if (Opc == X86ISD::VSRAI)
15268 ShiftAmt = ElementType.getSizeInBits() - 1;
15270 return DAG.getConstant(0, VT);
15273 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15274 && "Unknown target vector shift-by-constant node");
15276 // Fold this packed vector shift into a build vector if SrcOp is a
15277 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15278 if (VT == SrcOp.getSimpleValueType() &&
15279 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15280 SmallVector<SDValue, 8> Elts;
15281 unsigned NumElts = SrcOp->getNumOperands();
15282 ConstantSDNode *ND;
15285 default: llvm_unreachable(nullptr);
15286 case X86ISD::VSHLI:
15287 for (unsigned i=0; i!=NumElts; ++i) {
15288 SDValue CurrentOp = SrcOp->getOperand(i);
15289 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15290 Elts.push_back(CurrentOp);
15293 ND = cast<ConstantSDNode>(CurrentOp);
15294 const APInt &C = ND->getAPIntValue();
15295 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15298 case X86ISD::VSRLI:
15299 for (unsigned i=0; i!=NumElts; ++i) {
15300 SDValue CurrentOp = SrcOp->getOperand(i);
15301 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15302 Elts.push_back(CurrentOp);
15305 ND = cast<ConstantSDNode>(CurrentOp);
15306 const APInt &C = ND->getAPIntValue();
15307 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15310 case X86ISD::VSRAI:
15311 for (unsigned i=0; i!=NumElts; ++i) {
15312 SDValue CurrentOp = SrcOp->getOperand(i);
15313 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15314 Elts.push_back(CurrentOp);
15317 ND = cast<ConstantSDNode>(CurrentOp);
15318 const APInt &C = ND->getAPIntValue();
15319 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15324 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15327 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15330 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15331 // may or may not be a constant. Takes immediate version of shift as input.
15332 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15333 SDValue SrcOp, SDValue ShAmt,
15334 SelectionDAG &DAG) {
15335 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15337 // Catch shift-by-constant.
15338 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15339 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15340 CShAmt->getZExtValue(), DAG);
15342 // Change opcode to non-immediate version
15344 default: llvm_unreachable("Unknown target vector shift node");
15345 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15346 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15347 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15350 // Need to build a vector containing shift amount
15351 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15354 ShOps[1] = DAG.getConstant(0, MVT::i32);
15355 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15356 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15358 // The return type has to be a 128-bit type with the same element
15359 // type as the input type.
15360 MVT EltVT = VT.getVectorElementType();
15361 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15363 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15364 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15367 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15368 /// necessary casting for \p Mask when lowering masking intrinsics.
15369 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15370 SDValue PreservedSrc, SelectionDAG &DAG) {
15371 EVT VT = Op.getValueType();
15372 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15373 MVT::i1, VT.getVectorNumElements());
15376 assert(MaskVT.isSimple() && "invalid mask type");
15377 return DAG.getNode(ISD::VSELECT, dl, VT,
15378 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15382 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15384 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15385 case Intrinsic::x86_fma_vfmadd_ps:
15386 case Intrinsic::x86_fma_vfmadd_pd:
15387 case Intrinsic::x86_fma_vfmadd_ps_256:
15388 case Intrinsic::x86_fma_vfmadd_pd_256:
15389 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15390 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15391 return X86ISD::FMADD;
15392 case Intrinsic::x86_fma_vfmsub_ps:
15393 case Intrinsic::x86_fma_vfmsub_pd:
15394 case Intrinsic::x86_fma_vfmsub_ps_256:
15395 case Intrinsic::x86_fma_vfmsub_pd_256:
15396 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15397 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15398 return X86ISD::FMSUB;
15399 case Intrinsic::x86_fma_vfnmadd_ps:
15400 case Intrinsic::x86_fma_vfnmadd_pd:
15401 case Intrinsic::x86_fma_vfnmadd_ps_256:
15402 case Intrinsic::x86_fma_vfnmadd_pd_256:
15403 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15404 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15405 return X86ISD::FNMADD;
15406 case Intrinsic::x86_fma_vfnmsub_ps:
15407 case Intrinsic::x86_fma_vfnmsub_pd:
15408 case Intrinsic::x86_fma_vfnmsub_ps_256:
15409 case Intrinsic::x86_fma_vfnmsub_pd_256:
15410 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15411 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15412 return X86ISD::FNMSUB;
15413 case Intrinsic::x86_fma_vfmaddsub_ps:
15414 case Intrinsic::x86_fma_vfmaddsub_pd:
15415 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15416 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15417 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15418 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15419 return X86ISD::FMADDSUB;
15420 case Intrinsic::x86_fma_vfmsubadd_ps:
15421 case Intrinsic::x86_fma_vfmsubadd_pd:
15422 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15423 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15424 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15425 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15426 return X86ISD::FMSUBADD;
15430 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15432 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15434 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15436 switch(IntrData->Type) {
15437 case INTR_TYPE_1OP:
15438 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15439 case INTR_TYPE_2OP:
15440 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15442 case INTR_TYPE_3OP:
15443 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15444 Op.getOperand(2), Op.getOperand(3));
15445 case COMI: { // Comparison intrinsics
15446 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15447 SDValue LHS = Op.getOperand(1);
15448 SDValue RHS = Op.getOperand(2);
15449 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15450 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15451 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15452 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15453 DAG.getConstant(X86CC, MVT::i8), Cond);
15454 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15457 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15458 Op.getOperand(1), Op.getOperand(2), DAG);
15465 default: return SDValue(); // Don't custom lower most intrinsics.
15467 // Arithmetic intrinsics.
15468 case Intrinsic::x86_sse2_pmulu_dq:
15469 case Intrinsic::x86_avx2_pmulu_dq:
15470 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15471 Op.getOperand(1), Op.getOperand(2));
15473 case Intrinsic::x86_sse41_pmuldq:
15474 case Intrinsic::x86_avx2_pmul_dq:
15475 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15476 Op.getOperand(1), Op.getOperand(2));
15478 case Intrinsic::x86_sse2_pmulhu_w:
15479 case Intrinsic::x86_avx2_pmulhu_w:
15480 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15481 Op.getOperand(1), Op.getOperand(2));
15483 case Intrinsic::x86_sse2_pmulh_w:
15484 case Intrinsic::x86_avx2_pmulh_w:
15485 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15486 Op.getOperand(1), Op.getOperand(2));
15488 // SSE/SSE2/AVX floating point max/min intrinsics.
15489 case Intrinsic::x86_sse_max_ps:
15490 case Intrinsic::x86_sse2_max_pd:
15491 case Intrinsic::x86_avx_max_ps_256:
15492 case Intrinsic::x86_avx_max_pd_256:
15493 case Intrinsic::x86_sse_min_ps:
15494 case Intrinsic::x86_sse2_min_pd:
15495 case Intrinsic::x86_avx_min_ps_256:
15496 case Intrinsic::x86_avx_min_pd_256: {
15499 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15500 case Intrinsic::x86_sse_max_ps:
15501 case Intrinsic::x86_sse2_max_pd:
15502 case Intrinsic::x86_avx_max_ps_256:
15503 case Intrinsic::x86_avx_max_pd_256:
15504 Opcode = X86ISD::FMAX;
15506 case Intrinsic::x86_sse_min_ps:
15507 case Intrinsic::x86_sse2_min_pd:
15508 case Intrinsic::x86_avx_min_ps_256:
15509 case Intrinsic::x86_avx_min_pd_256:
15510 Opcode = X86ISD::FMIN;
15513 return DAG.getNode(Opcode, dl, Op.getValueType(),
15514 Op.getOperand(1), Op.getOperand(2));
15517 // AVX2 variable shift intrinsics
15518 case Intrinsic::x86_avx2_psllv_d:
15519 case Intrinsic::x86_avx2_psllv_q:
15520 case Intrinsic::x86_avx2_psllv_d_256:
15521 case Intrinsic::x86_avx2_psllv_q_256:
15522 case Intrinsic::x86_avx2_psrlv_d:
15523 case Intrinsic::x86_avx2_psrlv_q:
15524 case Intrinsic::x86_avx2_psrlv_d_256:
15525 case Intrinsic::x86_avx2_psrlv_q_256:
15526 case Intrinsic::x86_avx2_psrav_d:
15527 case Intrinsic::x86_avx2_psrav_d_256: {
15530 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15531 case Intrinsic::x86_avx2_psllv_d:
15532 case Intrinsic::x86_avx2_psllv_q:
15533 case Intrinsic::x86_avx2_psllv_d_256:
15534 case Intrinsic::x86_avx2_psllv_q_256:
15537 case Intrinsic::x86_avx2_psrlv_d:
15538 case Intrinsic::x86_avx2_psrlv_q:
15539 case Intrinsic::x86_avx2_psrlv_d_256:
15540 case Intrinsic::x86_avx2_psrlv_q_256:
15543 case Intrinsic::x86_avx2_psrav_d:
15544 case Intrinsic::x86_avx2_psrav_d_256:
15548 return DAG.getNode(Opcode, dl, Op.getValueType(),
15549 Op.getOperand(1), Op.getOperand(2));
15552 case Intrinsic::x86_sse2_packssdw_128:
15553 case Intrinsic::x86_sse2_packsswb_128:
15554 case Intrinsic::x86_avx2_packssdw:
15555 case Intrinsic::x86_avx2_packsswb:
15556 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15557 Op.getOperand(1), Op.getOperand(2));
15559 case Intrinsic::x86_sse2_packuswb_128:
15560 case Intrinsic::x86_sse41_packusdw:
15561 case Intrinsic::x86_avx2_packuswb:
15562 case Intrinsic::x86_avx2_packusdw:
15563 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15564 Op.getOperand(1), Op.getOperand(2));
15566 case Intrinsic::x86_ssse3_pshuf_b_128:
15567 case Intrinsic::x86_avx2_pshuf_b:
15568 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15569 Op.getOperand(1), Op.getOperand(2));
15571 case Intrinsic::x86_sse2_pshuf_d:
15572 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15573 Op.getOperand(1), Op.getOperand(2));
15575 case Intrinsic::x86_sse2_pshufl_w:
15576 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15577 Op.getOperand(1), Op.getOperand(2));
15579 case Intrinsic::x86_sse2_pshufh_w:
15580 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15581 Op.getOperand(1), Op.getOperand(2));
15583 case Intrinsic::x86_ssse3_psign_b_128:
15584 case Intrinsic::x86_ssse3_psign_w_128:
15585 case Intrinsic::x86_ssse3_psign_d_128:
15586 case Intrinsic::x86_avx2_psign_b:
15587 case Intrinsic::x86_avx2_psign_w:
15588 case Intrinsic::x86_avx2_psign_d:
15589 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15590 Op.getOperand(1), Op.getOperand(2));
15592 case Intrinsic::x86_avx2_permd:
15593 case Intrinsic::x86_avx2_permps:
15594 // Operands intentionally swapped. Mask is last operand to intrinsic,
15595 // but second operand for node/instruction.
15596 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15597 Op.getOperand(2), Op.getOperand(1));
15599 case Intrinsic::x86_avx512_mask_valign_q_512:
15600 case Intrinsic::x86_avx512_mask_valign_d_512:
15601 // Vector source operands are swapped.
15602 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15603 Op.getValueType(), Op.getOperand(2),
15606 Op.getOperand(5), Op.getOperand(4), DAG);
15608 // ptest and testp intrinsics. The intrinsic these come from are designed to
15609 // return an integer value, not just an instruction so lower it to the ptest
15610 // or testp pattern and a setcc for the result.
15611 case Intrinsic::x86_sse41_ptestz:
15612 case Intrinsic::x86_sse41_ptestc:
15613 case Intrinsic::x86_sse41_ptestnzc:
15614 case Intrinsic::x86_avx_ptestz_256:
15615 case Intrinsic::x86_avx_ptestc_256:
15616 case Intrinsic::x86_avx_ptestnzc_256:
15617 case Intrinsic::x86_avx_vtestz_ps:
15618 case Intrinsic::x86_avx_vtestc_ps:
15619 case Intrinsic::x86_avx_vtestnzc_ps:
15620 case Intrinsic::x86_avx_vtestz_pd:
15621 case Intrinsic::x86_avx_vtestc_pd:
15622 case Intrinsic::x86_avx_vtestnzc_pd:
15623 case Intrinsic::x86_avx_vtestz_ps_256:
15624 case Intrinsic::x86_avx_vtestc_ps_256:
15625 case Intrinsic::x86_avx_vtestnzc_ps_256:
15626 case Intrinsic::x86_avx_vtestz_pd_256:
15627 case Intrinsic::x86_avx_vtestc_pd_256:
15628 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15629 bool IsTestPacked = false;
15632 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15633 case Intrinsic::x86_avx_vtestz_ps:
15634 case Intrinsic::x86_avx_vtestz_pd:
15635 case Intrinsic::x86_avx_vtestz_ps_256:
15636 case Intrinsic::x86_avx_vtestz_pd_256:
15637 IsTestPacked = true; // Fallthrough
15638 case Intrinsic::x86_sse41_ptestz:
15639 case Intrinsic::x86_avx_ptestz_256:
15641 X86CC = X86::COND_E;
15643 case Intrinsic::x86_avx_vtestc_ps:
15644 case Intrinsic::x86_avx_vtestc_pd:
15645 case Intrinsic::x86_avx_vtestc_ps_256:
15646 case Intrinsic::x86_avx_vtestc_pd_256:
15647 IsTestPacked = true; // Fallthrough
15648 case Intrinsic::x86_sse41_ptestc:
15649 case Intrinsic::x86_avx_ptestc_256:
15651 X86CC = X86::COND_B;
15653 case Intrinsic::x86_avx_vtestnzc_ps:
15654 case Intrinsic::x86_avx_vtestnzc_pd:
15655 case Intrinsic::x86_avx_vtestnzc_ps_256:
15656 case Intrinsic::x86_avx_vtestnzc_pd_256:
15657 IsTestPacked = true; // Fallthrough
15658 case Intrinsic::x86_sse41_ptestnzc:
15659 case Intrinsic::x86_avx_ptestnzc_256:
15661 X86CC = X86::COND_A;
15665 SDValue LHS = Op.getOperand(1);
15666 SDValue RHS = Op.getOperand(2);
15667 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15668 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15669 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15670 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15671 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15673 case Intrinsic::x86_avx512_kortestz_w:
15674 case Intrinsic::x86_avx512_kortestc_w: {
15675 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15676 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15677 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15678 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15679 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15680 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15681 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15684 case Intrinsic::x86_sse42_pcmpistria128:
15685 case Intrinsic::x86_sse42_pcmpestria128:
15686 case Intrinsic::x86_sse42_pcmpistric128:
15687 case Intrinsic::x86_sse42_pcmpestric128:
15688 case Intrinsic::x86_sse42_pcmpistrio128:
15689 case Intrinsic::x86_sse42_pcmpestrio128:
15690 case Intrinsic::x86_sse42_pcmpistris128:
15691 case Intrinsic::x86_sse42_pcmpestris128:
15692 case Intrinsic::x86_sse42_pcmpistriz128:
15693 case Intrinsic::x86_sse42_pcmpestriz128: {
15697 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15698 case Intrinsic::x86_sse42_pcmpistria128:
15699 Opcode = X86ISD::PCMPISTRI;
15700 X86CC = X86::COND_A;
15702 case Intrinsic::x86_sse42_pcmpestria128:
15703 Opcode = X86ISD::PCMPESTRI;
15704 X86CC = X86::COND_A;
15706 case Intrinsic::x86_sse42_pcmpistric128:
15707 Opcode = X86ISD::PCMPISTRI;
15708 X86CC = X86::COND_B;
15710 case Intrinsic::x86_sse42_pcmpestric128:
15711 Opcode = X86ISD::PCMPESTRI;
15712 X86CC = X86::COND_B;
15714 case Intrinsic::x86_sse42_pcmpistrio128:
15715 Opcode = X86ISD::PCMPISTRI;
15716 X86CC = X86::COND_O;
15718 case Intrinsic::x86_sse42_pcmpestrio128:
15719 Opcode = X86ISD::PCMPESTRI;
15720 X86CC = X86::COND_O;
15722 case Intrinsic::x86_sse42_pcmpistris128:
15723 Opcode = X86ISD::PCMPISTRI;
15724 X86CC = X86::COND_S;
15726 case Intrinsic::x86_sse42_pcmpestris128:
15727 Opcode = X86ISD::PCMPESTRI;
15728 X86CC = X86::COND_S;
15730 case Intrinsic::x86_sse42_pcmpistriz128:
15731 Opcode = X86ISD::PCMPISTRI;
15732 X86CC = X86::COND_E;
15734 case Intrinsic::x86_sse42_pcmpestriz128:
15735 Opcode = X86ISD::PCMPESTRI;
15736 X86CC = X86::COND_E;
15739 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15740 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15741 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15742 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15743 DAG.getConstant(X86CC, MVT::i8),
15744 SDValue(PCMP.getNode(), 1));
15745 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15748 case Intrinsic::x86_sse42_pcmpistri128:
15749 case Intrinsic::x86_sse42_pcmpestri128: {
15751 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15752 Opcode = X86ISD::PCMPISTRI;
15754 Opcode = X86ISD::PCMPESTRI;
15756 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15757 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15758 return DAG.getNode(Opcode, dl, VTs, NewOps);
15761 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15762 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15763 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15764 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15765 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15766 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15767 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15768 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15769 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15770 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15771 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15772 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15773 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15774 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15775 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15776 dl, Op.getValueType(),
15780 Op.getOperand(4), Op.getOperand(1), DAG);
15785 case Intrinsic::x86_fma_vfmadd_ps:
15786 case Intrinsic::x86_fma_vfmadd_pd:
15787 case Intrinsic::x86_fma_vfmsub_ps:
15788 case Intrinsic::x86_fma_vfmsub_pd:
15789 case Intrinsic::x86_fma_vfnmadd_ps:
15790 case Intrinsic::x86_fma_vfnmadd_pd:
15791 case Intrinsic::x86_fma_vfnmsub_ps:
15792 case Intrinsic::x86_fma_vfnmsub_pd:
15793 case Intrinsic::x86_fma_vfmaddsub_ps:
15794 case Intrinsic::x86_fma_vfmaddsub_pd:
15795 case Intrinsic::x86_fma_vfmsubadd_ps:
15796 case Intrinsic::x86_fma_vfmsubadd_pd:
15797 case Intrinsic::x86_fma_vfmadd_ps_256:
15798 case Intrinsic::x86_fma_vfmadd_pd_256:
15799 case Intrinsic::x86_fma_vfmsub_ps_256:
15800 case Intrinsic::x86_fma_vfmsub_pd_256:
15801 case Intrinsic::x86_fma_vfnmadd_ps_256:
15802 case Intrinsic::x86_fma_vfnmadd_pd_256:
15803 case Intrinsic::x86_fma_vfnmsub_ps_256:
15804 case Intrinsic::x86_fma_vfnmsub_pd_256:
15805 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15806 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15807 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15808 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15809 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15810 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15814 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15815 SDValue Src, SDValue Mask, SDValue Base,
15816 SDValue Index, SDValue ScaleOp, SDValue Chain,
15817 const X86Subtarget * Subtarget) {
15819 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15820 assert(C && "Invalid scale type");
15821 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15822 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15823 Index.getSimpleValueType().getVectorNumElements());
15825 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15827 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15829 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15830 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15831 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15832 SDValue Segment = DAG.getRegister(0, MVT::i32);
15833 if (Src.getOpcode() == ISD::UNDEF)
15834 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15835 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15836 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15837 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15838 return DAG.getMergeValues(RetOps, dl);
15841 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15842 SDValue Src, SDValue Mask, SDValue Base,
15843 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15845 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15846 assert(C && "Invalid scale type");
15847 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15848 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15849 SDValue Segment = DAG.getRegister(0, MVT::i32);
15850 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15851 Index.getSimpleValueType().getVectorNumElements());
15853 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15855 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15857 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15858 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15859 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15860 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15861 return SDValue(Res, 1);
15864 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15865 SDValue Mask, SDValue Base, SDValue Index,
15866 SDValue ScaleOp, SDValue Chain) {
15868 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15869 assert(C && "Invalid scale type");
15870 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15871 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15872 SDValue Segment = DAG.getRegister(0, MVT::i32);
15874 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15876 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15878 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15880 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15881 //SDVTList VTs = DAG.getVTList(MVT::Other);
15882 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15883 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15884 return SDValue(Res, 0);
15887 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15888 // read performance monitor counters (x86_rdpmc).
15889 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15890 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15891 SmallVectorImpl<SDValue> &Results) {
15892 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15893 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15896 // The ECX register is used to select the index of the performance counter
15898 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15900 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15902 // Reads the content of a 64-bit performance counter and returns it in the
15903 // registers EDX:EAX.
15904 if (Subtarget->is64Bit()) {
15905 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15906 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15909 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15910 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15913 Chain = HI.getValue(1);
15915 if (Subtarget->is64Bit()) {
15916 // The EAX register is loaded with the low-order 32 bits. The EDX register
15917 // is loaded with the supported high-order bits of the counter.
15918 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15919 DAG.getConstant(32, MVT::i8));
15920 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15921 Results.push_back(Chain);
15925 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15926 SDValue Ops[] = { LO, HI };
15927 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15928 Results.push_back(Pair);
15929 Results.push_back(Chain);
15932 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15933 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15934 // also used to custom lower READCYCLECOUNTER nodes.
15935 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15936 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15937 SmallVectorImpl<SDValue> &Results) {
15938 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15939 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15942 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15943 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15944 // and the EAX register is loaded with the low-order 32 bits.
15945 if (Subtarget->is64Bit()) {
15946 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15947 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15950 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15951 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15954 SDValue Chain = HI.getValue(1);
15956 if (Opcode == X86ISD::RDTSCP_DAG) {
15957 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15959 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15960 // the ECX register. Add 'ecx' explicitly to the chain.
15961 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15963 // Explicitly store the content of ECX at the location passed in input
15964 // to the 'rdtscp' intrinsic.
15965 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15966 MachinePointerInfo(), false, false, 0);
15969 if (Subtarget->is64Bit()) {
15970 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15971 // the EAX register is loaded with the low-order 32 bits.
15972 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15973 DAG.getConstant(32, MVT::i8));
15974 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15975 Results.push_back(Chain);
15979 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15980 SDValue Ops[] = { LO, HI };
15981 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15982 Results.push_back(Pair);
15983 Results.push_back(Chain);
15986 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15987 SelectionDAG &DAG) {
15988 SmallVector<SDValue, 2> Results;
15990 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15992 return DAG.getMergeValues(Results, DL);
15996 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15997 SelectionDAG &DAG) {
15998 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16000 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16005 switch(IntrData->Type) {
16007 llvm_unreachable("Unknown Intrinsic Type");
16011 // Emit the node with the right value type.
16012 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16013 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16015 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16016 // Otherwise return the value from Rand, which is always 0, casted to i32.
16017 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16018 DAG.getConstant(1, Op->getValueType(1)),
16019 DAG.getConstant(X86::COND_B, MVT::i32),
16020 SDValue(Result.getNode(), 1) };
16021 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16022 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16025 // Return { result, isValid, chain }.
16026 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16027 SDValue(Result.getNode(), 2));
16030 //gather(v1, mask, index, base, scale);
16031 SDValue Chain = Op.getOperand(0);
16032 SDValue Src = Op.getOperand(2);
16033 SDValue Base = Op.getOperand(3);
16034 SDValue Index = Op.getOperand(4);
16035 SDValue Mask = Op.getOperand(5);
16036 SDValue Scale = Op.getOperand(6);
16037 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16041 //scatter(base, mask, index, v1, scale);
16042 SDValue Chain = Op.getOperand(0);
16043 SDValue Base = Op.getOperand(2);
16044 SDValue Mask = Op.getOperand(3);
16045 SDValue Index = Op.getOperand(4);
16046 SDValue Src = Op.getOperand(5);
16047 SDValue Scale = Op.getOperand(6);
16048 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16051 SDValue Hint = Op.getOperand(6);
16053 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16054 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16055 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16056 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16057 SDValue Chain = Op.getOperand(0);
16058 SDValue Mask = Op.getOperand(2);
16059 SDValue Index = Op.getOperand(3);
16060 SDValue Base = Op.getOperand(4);
16061 SDValue Scale = Op.getOperand(5);
16062 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16064 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16066 SmallVector<SDValue, 2> Results;
16067 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16068 return DAG.getMergeValues(Results, dl);
16070 // Read Performance Monitoring Counters.
16072 SmallVector<SDValue, 2> Results;
16073 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16074 return DAG.getMergeValues(Results, dl);
16076 // XTEST intrinsics.
16078 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16079 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16080 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16081 DAG.getConstant(X86::COND_NE, MVT::i8),
16083 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16084 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16085 Ret, SDValue(InTrans.getNode(), 1));
16089 SmallVector<SDValue, 2> Results;
16090 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16091 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16092 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16093 DAG.getConstant(-1, MVT::i8));
16094 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16095 Op.getOperand(4), GenCF.getValue(1));
16096 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16097 Op.getOperand(5), MachinePointerInfo(),
16099 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16100 DAG.getConstant(X86::COND_B, MVT::i8),
16102 Results.push_back(SetCC);
16103 Results.push_back(Store);
16104 return DAG.getMergeValues(Results, dl);
16109 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16110 SelectionDAG &DAG) const {
16111 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16112 MFI->setReturnAddressIsTaken(true);
16114 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16117 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16119 EVT PtrVT = getPointerTy();
16122 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16123 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16124 DAG.getSubtarget().getRegisterInfo());
16125 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16126 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16127 DAG.getNode(ISD::ADD, dl, PtrVT,
16128 FrameAddr, Offset),
16129 MachinePointerInfo(), false, false, false, 0);
16132 // Just load the return address.
16133 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16134 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16135 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16138 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16139 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16140 MFI->setFrameAddressIsTaken(true);
16142 EVT VT = Op.getValueType();
16143 SDLoc dl(Op); // FIXME probably not meaningful
16144 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16145 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16146 DAG.getSubtarget().getRegisterInfo());
16147 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16148 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16149 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16150 "Invalid Frame Register!");
16151 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16153 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16154 MachinePointerInfo(),
16155 false, false, false, 0);
16159 // FIXME? Maybe this could be a TableGen attribute on some registers and
16160 // this table could be generated automatically from RegInfo.
16161 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16163 unsigned Reg = StringSwitch<unsigned>(RegName)
16164 .Case("esp", X86::ESP)
16165 .Case("rsp", X86::RSP)
16169 report_fatal_error("Invalid register name global variable");
16172 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16173 SelectionDAG &DAG) const {
16174 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16175 DAG.getSubtarget().getRegisterInfo());
16176 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16179 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16180 SDValue Chain = Op.getOperand(0);
16181 SDValue Offset = Op.getOperand(1);
16182 SDValue Handler = Op.getOperand(2);
16185 EVT PtrVT = getPointerTy();
16186 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16187 DAG.getSubtarget().getRegisterInfo());
16188 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16189 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16190 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16191 "Invalid Frame Register!");
16192 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16193 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16195 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16196 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16197 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16198 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16200 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16202 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16203 DAG.getRegister(StoreAddrReg, PtrVT));
16206 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16207 SelectionDAG &DAG) const {
16209 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16210 DAG.getVTList(MVT::i32, MVT::Other),
16211 Op.getOperand(0), Op.getOperand(1));
16214 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16215 SelectionDAG &DAG) const {
16217 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16218 Op.getOperand(0), Op.getOperand(1));
16221 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16222 return Op.getOperand(0);
16225 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16226 SelectionDAG &DAG) const {
16227 SDValue Root = Op.getOperand(0);
16228 SDValue Trmp = Op.getOperand(1); // trampoline
16229 SDValue FPtr = Op.getOperand(2); // nested function
16230 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16233 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16234 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16236 if (Subtarget->is64Bit()) {
16237 SDValue OutChains[6];
16239 // Large code-model.
16240 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16241 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16243 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16244 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16246 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16248 // Load the pointer to the nested function into R11.
16249 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16250 SDValue Addr = Trmp;
16251 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16252 Addr, MachinePointerInfo(TrmpAddr),
16255 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16256 DAG.getConstant(2, MVT::i64));
16257 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16258 MachinePointerInfo(TrmpAddr, 2),
16261 // Load the 'nest' parameter value into R10.
16262 // R10 is specified in X86CallingConv.td
16263 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16264 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16265 DAG.getConstant(10, MVT::i64));
16266 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16267 Addr, MachinePointerInfo(TrmpAddr, 10),
16270 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16271 DAG.getConstant(12, MVT::i64));
16272 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16273 MachinePointerInfo(TrmpAddr, 12),
16276 // Jump to the nested function.
16277 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16278 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16279 DAG.getConstant(20, MVT::i64));
16280 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16281 Addr, MachinePointerInfo(TrmpAddr, 20),
16284 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16285 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16286 DAG.getConstant(22, MVT::i64));
16287 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16288 MachinePointerInfo(TrmpAddr, 22),
16291 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16293 const Function *Func =
16294 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16295 CallingConv::ID CC = Func->getCallingConv();
16300 llvm_unreachable("Unsupported calling convention");
16301 case CallingConv::C:
16302 case CallingConv::X86_StdCall: {
16303 // Pass 'nest' parameter in ECX.
16304 // Must be kept in sync with X86CallingConv.td
16305 NestReg = X86::ECX;
16307 // Check that ECX wasn't needed by an 'inreg' parameter.
16308 FunctionType *FTy = Func->getFunctionType();
16309 const AttributeSet &Attrs = Func->getAttributes();
16311 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16312 unsigned InRegCount = 0;
16315 for (FunctionType::param_iterator I = FTy->param_begin(),
16316 E = FTy->param_end(); I != E; ++I, ++Idx)
16317 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16318 // FIXME: should only count parameters that are lowered to integers.
16319 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16321 if (InRegCount > 2) {
16322 report_fatal_error("Nest register in use - reduce number of inreg"
16328 case CallingConv::X86_FastCall:
16329 case CallingConv::X86_ThisCall:
16330 case CallingConv::Fast:
16331 // Pass 'nest' parameter in EAX.
16332 // Must be kept in sync with X86CallingConv.td
16333 NestReg = X86::EAX;
16337 SDValue OutChains[4];
16338 SDValue Addr, Disp;
16340 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16341 DAG.getConstant(10, MVT::i32));
16342 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16344 // This is storing the opcode for MOV32ri.
16345 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16346 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16347 OutChains[0] = DAG.getStore(Root, dl,
16348 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16349 Trmp, MachinePointerInfo(TrmpAddr),
16352 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16353 DAG.getConstant(1, MVT::i32));
16354 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16355 MachinePointerInfo(TrmpAddr, 1),
16358 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16359 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16360 DAG.getConstant(5, MVT::i32));
16361 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16362 MachinePointerInfo(TrmpAddr, 5),
16365 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16366 DAG.getConstant(6, MVT::i32));
16367 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16368 MachinePointerInfo(TrmpAddr, 6),
16371 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16375 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16376 SelectionDAG &DAG) const {
16378 The rounding mode is in bits 11:10 of FPSR, and has the following
16380 00 Round to nearest
16385 FLT_ROUNDS, on the other hand, expects the following:
16392 To perform the conversion, we do:
16393 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16396 MachineFunction &MF = DAG.getMachineFunction();
16397 const TargetMachine &TM = MF.getTarget();
16398 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16399 unsigned StackAlignment = TFI.getStackAlignment();
16400 MVT VT = Op.getSimpleValueType();
16403 // Save FP Control Word to stack slot
16404 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16405 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16407 MachineMemOperand *MMO =
16408 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16409 MachineMemOperand::MOStore, 2, 2);
16411 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16412 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16413 DAG.getVTList(MVT::Other),
16414 Ops, MVT::i16, MMO);
16416 // Load FP Control Word from stack slot
16417 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16418 MachinePointerInfo(), false, false, false, 0);
16420 // Transform as necessary
16422 DAG.getNode(ISD::SRL, DL, MVT::i16,
16423 DAG.getNode(ISD::AND, DL, MVT::i16,
16424 CWD, DAG.getConstant(0x800, MVT::i16)),
16425 DAG.getConstant(11, MVT::i8));
16427 DAG.getNode(ISD::SRL, DL, MVT::i16,
16428 DAG.getNode(ISD::AND, DL, MVT::i16,
16429 CWD, DAG.getConstant(0x400, MVT::i16)),
16430 DAG.getConstant(9, MVT::i8));
16433 DAG.getNode(ISD::AND, DL, MVT::i16,
16434 DAG.getNode(ISD::ADD, DL, MVT::i16,
16435 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16436 DAG.getConstant(1, MVT::i16)),
16437 DAG.getConstant(3, MVT::i16));
16439 return DAG.getNode((VT.getSizeInBits() < 16 ?
16440 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16443 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16444 MVT VT = Op.getSimpleValueType();
16446 unsigned NumBits = VT.getSizeInBits();
16449 Op = Op.getOperand(0);
16450 if (VT == MVT::i8) {
16451 // Zero extend to i32 since there is not an i8 bsr.
16453 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16456 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16457 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16458 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16460 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16463 DAG.getConstant(NumBits+NumBits-1, OpVT),
16464 DAG.getConstant(X86::COND_E, MVT::i8),
16467 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16469 // Finally xor with NumBits-1.
16470 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16473 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16477 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16478 MVT VT = Op.getSimpleValueType();
16480 unsigned NumBits = VT.getSizeInBits();
16483 Op = Op.getOperand(0);
16484 if (VT == MVT::i8) {
16485 // Zero extend to i32 since there is not an i8 bsr.
16487 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16490 // Issue a bsr (scan bits in reverse).
16491 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16492 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16494 // And xor with NumBits-1.
16495 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16498 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16502 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16503 MVT VT = Op.getSimpleValueType();
16504 unsigned NumBits = VT.getSizeInBits();
16506 Op = Op.getOperand(0);
16508 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16509 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16510 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16512 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16515 DAG.getConstant(NumBits, VT),
16516 DAG.getConstant(X86::COND_E, MVT::i8),
16519 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16522 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16523 // ones, and then concatenate the result back.
16524 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16525 MVT VT = Op.getSimpleValueType();
16527 assert(VT.is256BitVector() && VT.isInteger() &&
16528 "Unsupported value type for operation");
16530 unsigned NumElems = VT.getVectorNumElements();
16533 // Extract the LHS vectors
16534 SDValue LHS = Op.getOperand(0);
16535 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16536 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16538 // Extract the RHS vectors
16539 SDValue RHS = Op.getOperand(1);
16540 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16541 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16543 MVT EltVT = VT.getVectorElementType();
16544 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16546 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16547 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16548 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16551 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16552 assert(Op.getSimpleValueType().is256BitVector() &&
16553 Op.getSimpleValueType().isInteger() &&
16554 "Only handle AVX 256-bit vector integer operation");
16555 return Lower256IntArith(Op, DAG);
16558 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16559 assert(Op.getSimpleValueType().is256BitVector() &&
16560 Op.getSimpleValueType().isInteger() &&
16561 "Only handle AVX 256-bit vector integer operation");
16562 return Lower256IntArith(Op, DAG);
16565 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16566 SelectionDAG &DAG) {
16568 MVT VT = Op.getSimpleValueType();
16570 // Decompose 256-bit ops into smaller 128-bit ops.
16571 if (VT.is256BitVector() && !Subtarget->hasInt256())
16572 return Lower256IntArith(Op, DAG);
16574 SDValue A = Op.getOperand(0);
16575 SDValue B = Op.getOperand(1);
16577 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16578 if (VT == MVT::v4i32) {
16579 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16580 "Should not custom lower when pmuldq is available!");
16582 // Extract the odd parts.
16583 static const int UnpackMask[] = { 1, -1, 3, -1 };
16584 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16585 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16587 // Multiply the even parts.
16588 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16589 // Now multiply odd parts.
16590 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16592 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16593 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16595 // Merge the two vectors back together with a shuffle. This expands into 2
16597 static const int ShufMask[] = { 0, 4, 2, 6 };
16598 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16601 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16602 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16604 // Ahi = psrlqi(a, 32);
16605 // Bhi = psrlqi(b, 32);
16607 // AloBlo = pmuludq(a, b);
16608 // AloBhi = pmuludq(a, Bhi);
16609 // AhiBlo = pmuludq(Ahi, b);
16611 // AloBhi = psllqi(AloBhi, 32);
16612 // AhiBlo = psllqi(AhiBlo, 32);
16613 // return AloBlo + AloBhi + AhiBlo;
16615 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16616 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16618 // Bit cast to 32-bit vectors for MULUDQ
16619 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16620 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16621 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16622 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16623 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16624 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16626 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16627 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16628 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16630 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16631 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16633 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16634 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16637 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16638 assert(Subtarget->isTargetWin64() && "Unexpected target");
16639 EVT VT = Op.getValueType();
16640 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16641 "Unexpected return type for lowering");
16645 switch (Op->getOpcode()) {
16646 default: llvm_unreachable("Unexpected request for libcall!");
16647 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16648 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16649 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16650 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16651 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16652 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16656 SDValue InChain = DAG.getEntryNode();
16658 TargetLowering::ArgListTy Args;
16659 TargetLowering::ArgListEntry Entry;
16660 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16661 EVT ArgVT = Op->getOperand(i).getValueType();
16662 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16663 "Unexpected argument type for lowering");
16664 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16665 Entry.Node = StackPtr;
16666 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16668 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16669 Entry.Ty = PointerType::get(ArgTy,0);
16670 Entry.isSExt = false;
16671 Entry.isZExt = false;
16672 Args.push_back(Entry);
16675 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16678 TargetLowering::CallLoweringInfo CLI(DAG);
16679 CLI.setDebugLoc(dl).setChain(InChain)
16680 .setCallee(getLibcallCallingConv(LC),
16681 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16682 Callee, std::move(Args), 0)
16683 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16685 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16686 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16689 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16690 SelectionDAG &DAG) {
16691 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16692 EVT VT = Op0.getValueType();
16695 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16696 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16698 // PMULxD operations multiply each even value (starting at 0) of LHS with
16699 // the related value of RHS and produce a widen result.
16700 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16701 // => <2 x i64> <ae|cg>
16703 // In other word, to have all the results, we need to perform two PMULxD:
16704 // 1. one with the even values.
16705 // 2. one with the odd values.
16706 // To achieve #2, with need to place the odd values at an even position.
16708 // Place the odd value at an even position (basically, shift all values 1
16709 // step to the left):
16710 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16711 // <a|b|c|d> => <b|undef|d|undef>
16712 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16713 // <e|f|g|h> => <f|undef|h|undef>
16714 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16716 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16718 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16719 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16721 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16722 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16723 // => <2 x i64> <ae|cg>
16724 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16725 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16726 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16727 // => <2 x i64> <bf|dh>
16728 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16729 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16731 // Shuffle it back into the right order.
16732 SDValue Highs, Lows;
16733 if (VT == MVT::v8i32) {
16734 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16735 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16736 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16737 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16739 const int HighMask[] = {1, 5, 3, 7};
16740 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16741 const int LowMask[] = {0, 4, 2, 6};
16742 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16745 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16746 // unsigned multiply.
16747 if (IsSigned && !Subtarget->hasSSE41()) {
16749 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16750 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16751 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16752 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16753 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16755 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16756 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16759 // The first result of MUL_LOHI is actually the low value, followed by the
16761 SDValue Ops[] = {Lows, Highs};
16762 return DAG.getMergeValues(Ops, dl);
16765 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16766 const X86Subtarget *Subtarget) {
16767 MVT VT = Op.getSimpleValueType();
16769 SDValue R = Op.getOperand(0);
16770 SDValue Amt = Op.getOperand(1);
16772 // Optimize shl/srl/sra with constant shift amount.
16773 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16774 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16775 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16777 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16778 (Subtarget->hasInt256() &&
16779 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16780 (Subtarget->hasAVX512() &&
16781 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16782 if (Op.getOpcode() == ISD::SHL)
16783 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16785 if (Op.getOpcode() == ISD::SRL)
16786 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16788 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16789 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16793 if (VT == MVT::v16i8) {
16794 if (Op.getOpcode() == ISD::SHL) {
16795 // Make a large shift.
16796 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16797 MVT::v8i16, R, ShiftAmt,
16799 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16800 // Zero out the rightmost bits.
16801 SmallVector<SDValue, 16> V(16,
16802 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16804 return DAG.getNode(ISD::AND, dl, VT, SHL,
16805 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16807 if (Op.getOpcode() == ISD::SRL) {
16808 // Make a large shift.
16809 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16810 MVT::v8i16, R, ShiftAmt,
16812 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16813 // Zero out the leftmost bits.
16814 SmallVector<SDValue, 16> V(16,
16815 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16817 return DAG.getNode(ISD::AND, dl, VT, SRL,
16818 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16820 if (Op.getOpcode() == ISD::SRA) {
16821 if (ShiftAmt == 7) {
16822 // R s>> 7 === R s< 0
16823 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16824 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16827 // R s>> a === ((R u>> a) ^ m) - m
16828 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16829 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16831 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16832 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16833 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16836 llvm_unreachable("Unknown shift opcode.");
16839 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16840 if (Op.getOpcode() == ISD::SHL) {
16841 // Make a large shift.
16842 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16843 MVT::v16i16, R, ShiftAmt,
16845 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16846 // Zero out the rightmost bits.
16847 SmallVector<SDValue, 32> V(32,
16848 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16850 return DAG.getNode(ISD::AND, dl, VT, SHL,
16851 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16853 if (Op.getOpcode() == ISD::SRL) {
16854 // Make a large shift.
16855 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16856 MVT::v16i16, R, ShiftAmt,
16858 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16859 // Zero out the leftmost bits.
16860 SmallVector<SDValue, 32> V(32,
16861 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16863 return DAG.getNode(ISD::AND, dl, VT, SRL,
16864 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16866 if (Op.getOpcode() == ISD::SRA) {
16867 if (ShiftAmt == 7) {
16868 // R s>> 7 === R s< 0
16869 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16870 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16873 // R s>> a === ((R u>> a) ^ m) - m
16874 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16875 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16877 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16878 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16879 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16882 llvm_unreachable("Unknown shift opcode.");
16887 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16888 if (!Subtarget->is64Bit() &&
16889 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16890 Amt.getOpcode() == ISD::BITCAST &&
16891 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16892 Amt = Amt.getOperand(0);
16893 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16894 VT.getVectorNumElements();
16895 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16896 uint64_t ShiftAmt = 0;
16897 for (unsigned i = 0; i != Ratio; ++i) {
16898 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16902 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16904 // Check remaining shift amounts.
16905 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16906 uint64_t ShAmt = 0;
16907 for (unsigned j = 0; j != Ratio; ++j) {
16908 ConstantSDNode *C =
16909 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16913 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16915 if (ShAmt != ShiftAmt)
16918 switch (Op.getOpcode()) {
16920 llvm_unreachable("Unknown shift opcode!");
16922 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16925 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16928 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16936 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16937 const X86Subtarget* Subtarget) {
16938 MVT VT = Op.getSimpleValueType();
16940 SDValue R = Op.getOperand(0);
16941 SDValue Amt = Op.getOperand(1);
16943 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16944 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16945 (Subtarget->hasInt256() &&
16946 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16947 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16948 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16950 EVT EltVT = VT.getVectorElementType();
16952 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16953 unsigned NumElts = VT.getVectorNumElements();
16955 for (i = 0; i != NumElts; ++i) {
16956 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16960 for (j = i; j != NumElts; ++j) {
16961 SDValue Arg = Amt.getOperand(j);
16962 if (Arg.getOpcode() == ISD::UNDEF) continue;
16963 if (Arg != Amt.getOperand(i))
16966 if (i != NumElts && j == NumElts)
16967 BaseShAmt = Amt.getOperand(i);
16969 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16970 Amt = Amt.getOperand(0);
16971 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16972 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16973 SDValue InVec = Amt.getOperand(0);
16974 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16975 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16977 for (; i != NumElts; ++i) {
16978 SDValue Arg = InVec.getOperand(i);
16979 if (Arg.getOpcode() == ISD::UNDEF) continue;
16983 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16984 if (ConstantSDNode *C =
16985 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16986 unsigned SplatIdx =
16987 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16988 if (C->getZExtValue() == SplatIdx)
16989 BaseShAmt = InVec.getOperand(1);
16992 if (!BaseShAmt.getNode())
16993 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16994 DAG.getIntPtrConstant(0));
16998 if (BaseShAmt.getNode()) {
16999 if (EltVT.bitsGT(MVT::i32))
17000 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17001 else if (EltVT.bitsLT(MVT::i32))
17002 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17004 switch (Op.getOpcode()) {
17006 llvm_unreachable("Unknown shift opcode!");
17008 switch (VT.SimpleTy) {
17009 default: return SDValue();
17018 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17021 switch (VT.SimpleTy) {
17022 default: return SDValue();
17029 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17032 switch (VT.SimpleTy) {
17033 default: return SDValue();
17042 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17048 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17049 if (!Subtarget->is64Bit() &&
17050 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17051 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17052 Amt.getOpcode() == ISD::BITCAST &&
17053 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17054 Amt = Amt.getOperand(0);
17055 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17056 VT.getVectorNumElements();
17057 std::vector<SDValue> Vals(Ratio);
17058 for (unsigned i = 0; i != Ratio; ++i)
17059 Vals[i] = Amt.getOperand(i);
17060 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17061 for (unsigned j = 0; j != Ratio; ++j)
17062 if (Vals[j] != Amt.getOperand(i + j))
17065 switch (Op.getOpcode()) {
17067 llvm_unreachable("Unknown shift opcode!");
17069 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17071 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17073 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17080 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17081 SelectionDAG &DAG) {
17082 MVT VT = Op.getSimpleValueType();
17084 SDValue R = Op.getOperand(0);
17085 SDValue Amt = Op.getOperand(1);
17088 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17089 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17091 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17095 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17099 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17101 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17102 if (Subtarget->hasInt256()) {
17103 if (Op.getOpcode() == ISD::SRL &&
17104 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17105 VT == MVT::v4i64 || VT == MVT::v8i32))
17107 if (Op.getOpcode() == ISD::SHL &&
17108 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17109 VT == MVT::v4i64 || VT == MVT::v8i32))
17111 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17115 // If possible, lower this packed shift into a vector multiply instead of
17116 // expanding it into a sequence of scalar shifts.
17117 // Do this only if the vector shift count is a constant build_vector.
17118 if (Op.getOpcode() == ISD::SHL &&
17119 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17120 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17121 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17122 SmallVector<SDValue, 8> Elts;
17123 EVT SVT = VT.getScalarType();
17124 unsigned SVTBits = SVT.getSizeInBits();
17125 const APInt &One = APInt(SVTBits, 1);
17126 unsigned NumElems = VT.getVectorNumElements();
17128 for (unsigned i=0; i !=NumElems; ++i) {
17129 SDValue Op = Amt->getOperand(i);
17130 if (Op->getOpcode() == ISD::UNDEF) {
17131 Elts.push_back(Op);
17135 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17136 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17137 uint64_t ShAmt = C.getZExtValue();
17138 if (ShAmt >= SVTBits) {
17139 Elts.push_back(DAG.getUNDEF(SVT));
17142 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17144 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17145 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17148 // Lower SHL with variable shift amount.
17149 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17150 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17152 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17153 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17154 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17155 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17158 // If possible, lower this shift as a sequence of two shifts by
17159 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17161 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17163 // Could be rewritten as:
17164 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17166 // The advantage is that the two shifts from the example would be
17167 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17168 // the vector shift into four scalar shifts plus four pairs of vector
17170 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17171 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17172 unsigned TargetOpcode = X86ISD::MOVSS;
17173 bool CanBeSimplified;
17174 // The splat value for the first packed shift (the 'X' from the example).
17175 SDValue Amt1 = Amt->getOperand(0);
17176 // The splat value for the second packed shift (the 'Y' from the example).
17177 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17178 Amt->getOperand(2);
17180 // See if it is possible to replace this node with a sequence of
17181 // two shifts followed by a MOVSS/MOVSD
17182 if (VT == MVT::v4i32) {
17183 // Check if it is legal to use a MOVSS.
17184 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17185 Amt2 == Amt->getOperand(3);
17186 if (!CanBeSimplified) {
17187 // Otherwise, check if we can still simplify this node using a MOVSD.
17188 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17189 Amt->getOperand(2) == Amt->getOperand(3);
17190 TargetOpcode = X86ISD::MOVSD;
17191 Amt2 = Amt->getOperand(2);
17194 // Do similar checks for the case where the machine value type
17196 CanBeSimplified = Amt1 == Amt->getOperand(1);
17197 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17198 CanBeSimplified = Amt2 == Amt->getOperand(i);
17200 if (!CanBeSimplified) {
17201 TargetOpcode = X86ISD::MOVSD;
17202 CanBeSimplified = true;
17203 Amt2 = Amt->getOperand(4);
17204 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17205 CanBeSimplified = Amt1 == Amt->getOperand(i);
17206 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17207 CanBeSimplified = Amt2 == Amt->getOperand(j);
17211 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17212 isa<ConstantSDNode>(Amt2)) {
17213 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17214 EVT CastVT = MVT::v4i32;
17216 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17217 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17219 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17220 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17221 if (TargetOpcode == X86ISD::MOVSD)
17222 CastVT = MVT::v2i64;
17223 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17224 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17225 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17227 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17231 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17232 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17235 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17236 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17238 // Turn 'a' into a mask suitable for VSELECT
17239 SDValue VSelM = DAG.getConstant(0x80, VT);
17240 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17241 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17243 SDValue CM1 = DAG.getConstant(0x0f, VT);
17244 SDValue CM2 = DAG.getConstant(0x3f, VT);
17246 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17247 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17248 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17249 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17250 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17253 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17254 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17255 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17257 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17258 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17259 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17260 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17261 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17264 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17265 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17266 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17268 // return VSELECT(r, r+r, a);
17269 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17270 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17274 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17275 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17276 // solution better.
17277 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17278 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17280 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17281 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17282 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17283 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17284 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17287 // Decompose 256-bit shifts into smaller 128-bit shifts.
17288 if (VT.is256BitVector()) {
17289 unsigned NumElems = VT.getVectorNumElements();
17290 MVT EltVT = VT.getVectorElementType();
17291 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17293 // Extract the two vectors
17294 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17295 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17297 // Recreate the shift amount vectors
17298 SDValue Amt1, Amt2;
17299 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17300 // Constant shift amount
17301 SmallVector<SDValue, 4> Amt1Csts;
17302 SmallVector<SDValue, 4> Amt2Csts;
17303 for (unsigned i = 0; i != NumElems/2; ++i)
17304 Amt1Csts.push_back(Amt->getOperand(i));
17305 for (unsigned i = NumElems/2; i != NumElems; ++i)
17306 Amt2Csts.push_back(Amt->getOperand(i));
17308 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17309 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17311 // Variable shift amount
17312 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17313 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17316 // Issue new vector shifts for the smaller types
17317 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17318 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17320 // Concatenate the result back
17321 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17327 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17328 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17329 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17330 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17331 // has only one use.
17332 SDNode *N = Op.getNode();
17333 SDValue LHS = N->getOperand(0);
17334 SDValue RHS = N->getOperand(1);
17335 unsigned BaseOp = 0;
17338 switch (Op.getOpcode()) {
17339 default: llvm_unreachable("Unknown ovf instruction!");
17341 // A subtract of one will be selected as a INC. Note that INC doesn't
17342 // set CF, so we can't do this for UADDO.
17343 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17345 BaseOp = X86ISD::INC;
17346 Cond = X86::COND_O;
17349 BaseOp = X86ISD::ADD;
17350 Cond = X86::COND_O;
17353 BaseOp = X86ISD::ADD;
17354 Cond = X86::COND_B;
17357 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17358 // set CF, so we can't do this for USUBO.
17359 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17361 BaseOp = X86ISD::DEC;
17362 Cond = X86::COND_O;
17365 BaseOp = X86ISD::SUB;
17366 Cond = X86::COND_O;
17369 BaseOp = X86ISD::SUB;
17370 Cond = X86::COND_B;
17373 BaseOp = X86ISD::SMUL;
17374 Cond = X86::COND_O;
17376 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17377 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17379 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17382 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17383 DAG.getConstant(X86::COND_O, MVT::i32),
17384 SDValue(Sum.getNode(), 2));
17386 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17390 // Also sets EFLAGS.
17391 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17392 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17395 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17396 DAG.getConstant(Cond, MVT::i32),
17397 SDValue(Sum.getNode(), 1));
17399 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17402 // Sign extension of the low part of vector elements. This may be used either
17403 // when sign extend instructions are not available or if the vector element
17404 // sizes already match the sign-extended size. If the vector elements are in
17405 // their pre-extended size and sign extend instructions are available, that will
17406 // be handled by LowerSIGN_EXTEND.
17407 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17408 SelectionDAG &DAG) const {
17410 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17411 MVT VT = Op.getSimpleValueType();
17413 if (!Subtarget->hasSSE2() || !VT.isVector())
17416 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17417 ExtraVT.getScalarType().getSizeInBits();
17419 switch (VT.SimpleTy) {
17420 default: return SDValue();
17423 if (!Subtarget->hasFp256())
17425 if (!Subtarget->hasInt256()) {
17426 // needs to be split
17427 unsigned NumElems = VT.getVectorNumElements();
17429 // Extract the LHS vectors
17430 SDValue LHS = Op.getOperand(0);
17431 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17432 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17434 MVT EltVT = VT.getVectorElementType();
17435 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17437 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17438 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17439 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17441 SDValue Extra = DAG.getValueType(ExtraVT);
17443 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17444 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17446 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17451 SDValue Op0 = Op.getOperand(0);
17453 // This is a sign extension of some low part of vector elements without
17454 // changing the size of the vector elements themselves:
17455 // Shift-Left + Shift-Right-Algebraic.
17456 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17458 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17464 /// Returns true if the operand type is exactly twice the native width, and
17465 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17466 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17467 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17468 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17469 const X86Subtarget &Subtarget =
17470 getTargetMachine().getSubtarget<X86Subtarget>();
17471 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17474 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17475 else if (OpWidth == 128)
17476 return Subtarget.hasCmpxchg16b();
17481 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17482 return needsCmpXchgNb(SI->getValueOperand()->getType());
17485 // Note: this turns large loads into lock cmpxchg8b/16b.
17486 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17487 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17488 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17489 return needsCmpXchgNb(PTy->getElementType());
17492 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17493 const X86Subtarget &Subtarget =
17494 getTargetMachine().getSubtarget<X86Subtarget>();
17495 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17496 const Type *MemType = AI->getType();
17498 // If the operand is too big, we must see if cmpxchg8/16b is available
17499 // and default to library calls otherwise.
17500 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17501 return needsCmpXchgNb(MemType);
17503 AtomicRMWInst::BinOp Op = AI->getOperation();
17506 llvm_unreachable("Unknown atomic operation");
17507 case AtomicRMWInst::Xchg:
17508 case AtomicRMWInst::Add:
17509 case AtomicRMWInst::Sub:
17510 // It's better to use xadd, xsub or xchg for these in all cases.
17512 case AtomicRMWInst::Or:
17513 case AtomicRMWInst::And:
17514 case AtomicRMWInst::Xor:
17515 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17516 // prefix to a normal instruction for these operations.
17517 return !AI->use_empty();
17518 case AtomicRMWInst::Nand:
17519 case AtomicRMWInst::Max:
17520 case AtomicRMWInst::Min:
17521 case AtomicRMWInst::UMax:
17522 case AtomicRMWInst::UMin:
17523 // These always require a non-trivial set of data operations on x86. We must
17524 // use a cmpxchg loop.
17529 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17530 SelectionDAG &DAG) {
17532 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17533 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17534 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17535 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17537 // The only fence that needs an instruction is a sequentially-consistent
17538 // cross-thread fence.
17539 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17540 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17541 // no-sse2). There isn't any reason to disable it if the target processor
17543 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
17544 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17546 SDValue Chain = Op.getOperand(0);
17547 SDValue Zero = DAG.getConstant(0, MVT::i32);
17549 DAG.getRegister(X86::ESP, MVT::i32), // Base
17550 DAG.getTargetConstant(1, MVT::i8), // Scale
17551 DAG.getRegister(0, MVT::i32), // Index
17552 DAG.getTargetConstant(0, MVT::i32), // Disp
17553 DAG.getRegister(0, MVT::i32), // Segment.
17557 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17558 return SDValue(Res, 0);
17561 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17562 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17565 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17566 SelectionDAG &DAG) {
17567 MVT T = Op.getSimpleValueType();
17571 switch(T.SimpleTy) {
17572 default: llvm_unreachable("Invalid value type!");
17573 case MVT::i8: Reg = X86::AL; size = 1; break;
17574 case MVT::i16: Reg = X86::AX; size = 2; break;
17575 case MVT::i32: Reg = X86::EAX; size = 4; break;
17577 assert(Subtarget->is64Bit() && "Node not type legal!");
17578 Reg = X86::RAX; size = 8;
17581 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17582 Op.getOperand(2), SDValue());
17583 SDValue Ops[] = { cpIn.getValue(0),
17586 DAG.getTargetConstant(size, MVT::i8),
17587 cpIn.getValue(1) };
17588 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17589 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17590 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17594 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17595 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17596 MVT::i32, cpOut.getValue(2));
17597 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17598 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17600 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17601 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17602 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17606 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17607 SelectionDAG &DAG) {
17608 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17609 MVT DstVT = Op.getSimpleValueType();
17611 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17612 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17613 if (DstVT != MVT::f64)
17614 // This conversion needs to be expanded.
17617 SDValue InVec = Op->getOperand(0);
17619 unsigned NumElts = SrcVT.getVectorNumElements();
17620 EVT SVT = SrcVT.getVectorElementType();
17622 // Widen the vector in input in the case of MVT::v2i32.
17623 // Example: from MVT::v2i32 to MVT::v4i32.
17624 SmallVector<SDValue, 16> Elts;
17625 for (unsigned i = 0, e = NumElts; i != e; ++i)
17626 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17627 DAG.getIntPtrConstant(i)));
17629 // Explicitly mark the extra elements as Undef.
17630 SDValue Undef = DAG.getUNDEF(SVT);
17631 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17632 Elts.push_back(Undef);
17634 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17635 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17636 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17637 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17638 DAG.getIntPtrConstant(0));
17641 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17642 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17643 assert((DstVT == MVT::i64 ||
17644 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17645 "Unexpected custom BITCAST");
17646 // i64 <=> MMX conversions are Legal.
17647 if (SrcVT==MVT::i64 && DstVT.isVector())
17649 if (DstVT==MVT::i64 && SrcVT.isVector())
17651 // MMX <=> MMX conversions are Legal.
17652 if (SrcVT.isVector() && DstVT.isVector())
17654 // All other conversions need to be expanded.
17658 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17659 SDNode *Node = Op.getNode();
17661 EVT T = Node->getValueType(0);
17662 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17663 DAG.getConstant(0, T), Node->getOperand(2));
17664 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17665 cast<AtomicSDNode>(Node)->getMemoryVT(),
17666 Node->getOperand(0),
17667 Node->getOperand(1), negOp,
17668 cast<AtomicSDNode>(Node)->getMemOperand(),
17669 cast<AtomicSDNode>(Node)->getOrdering(),
17670 cast<AtomicSDNode>(Node)->getSynchScope());
17673 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17674 SDNode *Node = Op.getNode();
17676 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17678 // Convert seq_cst store -> xchg
17679 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17680 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17681 // (The only way to get a 16-byte store is cmpxchg16b)
17682 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17683 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17684 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17685 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17686 cast<AtomicSDNode>(Node)->getMemoryVT(),
17687 Node->getOperand(0),
17688 Node->getOperand(1), Node->getOperand(2),
17689 cast<AtomicSDNode>(Node)->getMemOperand(),
17690 cast<AtomicSDNode>(Node)->getOrdering(),
17691 cast<AtomicSDNode>(Node)->getSynchScope());
17692 return Swap.getValue(1);
17694 // Other atomic stores have a simple pattern.
17698 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17699 EVT VT = Op.getNode()->getSimpleValueType(0);
17701 // Let legalize expand this if it isn't a legal type yet.
17702 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17705 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17708 bool ExtraOp = false;
17709 switch (Op.getOpcode()) {
17710 default: llvm_unreachable("Invalid code");
17711 case ISD::ADDC: Opc = X86ISD::ADD; break;
17712 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17713 case ISD::SUBC: Opc = X86ISD::SUB; break;
17714 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17718 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17720 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17721 Op.getOperand(1), Op.getOperand(2));
17724 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17725 SelectionDAG &DAG) {
17726 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17728 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17729 // which returns the values as { float, float } (in XMM0) or
17730 // { double, double } (which is returned in XMM0, XMM1).
17732 SDValue Arg = Op.getOperand(0);
17733 EVT ArgVT = Arg.getValueType();
17734 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17736 TargetLowering::ArgListTy Args;
17737 TargetLowering::ArgListEntry Entry;
17741 Entry.isSExt = false;
17742 Entry.isZExt = false;
17743 Args.push_back(Entry);
17745 bool isF64 = ArgVT == MVT::f64;
17746 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17747 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17748 // the results are returned via SRet in memory.
17749 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17750 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17751 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17753 Type *RetTy = isF64
17754 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17755 : (Type*)VectorType::get(ArgTy, 4);
17757 TargetLowering::CallLoweringInfo CLI(DAG);
17758 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17759 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17761 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17764 // Returned in xmm0 and xmm1.
17765 return CallResult.first;
17767 // Returned in bits 0:31 and 32:64 xmm0.
17768 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17769 CallResult.first, DAG.getIntPtrConstant(0));
17770 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17771 CallResult.first, DAG.getIntPtrConstant(1));
17772 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17773 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17776 /// LowerOperation - Provide custom lowering hooks for some operations.
17778 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17779 switch (Op.getOpcode()) {
17780 default: llvm_unreachable("Should not custom lower this!");
17781 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17782 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17783 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17784 return LowerCMP_SWAP(Op, Subtarget, DAG);
17785 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17786 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17787 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17788 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17789 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17790 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17791 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17792 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17793 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17794 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17795 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17796 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17797 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17798 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17799 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17800 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17801 case ISD::SHL_PARTS:
17802 case ISD::SRA_PARTS:
17803 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17804 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17805 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17806 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17807 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17808 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17809 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17810 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17811 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17812 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17813 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17815 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17816 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17817 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17818 case ISD::SETCC: return LowerSETCC(Op, DAG);
17819 case ISD::SELECT: return LowerSELECT(Op, DAG);
17820 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17821 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17822 case ISD::VASTART: return LowerVASTART(Op, DAG);
17823 case ISD::VAARG: return LowerVAARG(Op, DAG);
17824 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17825 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17826 case ISD::INTRINSIC_VOID:
17827 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17828 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17829 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17830 case ISD::FRAME_TO_ARGS_OFFSET:
17831 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17832 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17833 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17834 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17835 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17836 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17837 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17838 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17839 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17840 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17841 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17842 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17843 case ISD::UMUL_LOHI:
17844 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17847 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17853 case ISD::UMULO: return LowerXALUO(Op, DAG);
17854 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17855 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17859 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17860 case ISD::ADD: return LowerADD(Op, DAG);
17861 case ISD::SUB: return LowerSUB(Op, DAG);
17862 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17866 /// ReplaceNodeResults - Replace a node with an illegal result type
17867 /// with a new node built out of custom code.
17868 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17869 SmallVectorImpl<SDValue>&Results,
17870 SelectionDAG &DAG) const {
17872 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17873 switch (N->getOpcode()) {
17875 llvm_unreachable("Do not know how to custom type legalize this operation!");
17876 case ISD::SIGN_EXTEND_INREG:
17881 // We don't want to expand or promote these.
17888 case ISD::UDIVREM: {
17889 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17890 Results.push_back(V);
17893 case ISD::FP_TO_SINT:
17894 case ISD::FP_TO_UINT: {
17895 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17897 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17900 std::pair<SDValue,SDValue> Vals =
17901 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17902 SDValue FIST = Vals.first, StackSlot = Vals.second;
17903 if (FIST.getNode()) {
17904 EVT VT = N->getValueType(0);
17905 // Return a load from the stack slot.
17906 if (StackSlot.getNode())
17907 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17908 MachinePointerInfo(),
17909 false, false, false, 0));
17911 Results.push_back(FIST);
17915 case ISD::UINT_TO_FP: {
17916 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17917 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17918 N->getValueType(0) != MVT::v2f32)
17920 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17922 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17924 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17925 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17926 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17927 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17928 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17929 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17932 case ISD::FP_ROUND: {
17933 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17935 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17936 Results.push_back(V);
17939 case ISD::INTRINSIC_W_CHAIN: {
17940 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17942 default : llvm_unreachable("Do not know how to custom type "
17943 "legalize this intrinsic operation!");
17944 case Intrinsic::x86_rdtsc:
17945 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17947 case Intrinsic::x86_rdtscp:
17948 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17950 case Intrinsic::x86_rdpmc:
17951 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17954 case ISD::READCYCLECOUNTER: {
17955 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17958 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17959 EVT T = N->getValueType(0);
17960 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17961 bool Regs64bit = T == MVT::i128;
17962 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17963 SDValue cpInL, cpInH;
17964 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17965 DAG.getConstant(0, HalfT));
17966 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17967 DAG.getConstant(1, HalfT));
17968 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17969 Regs64bit ? X86::RAX : X86::EAX,
17971 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17972 Regs64bit ? X86::RDX : X86::EDX,
17973 cpInH, cpInL.getValue(1));
17974 SDValue swapInL, swapInH;
17975 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17976 DAG.getConstant(0, HalfT));
17977 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17978 DAG.getConstant(1, HalfT));
17979 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17980 Regs64bit ? X86::RBX : X86::EBX,
17981 swapInL, cpInH.getValue(1));
17982 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17983 Regs64bit ? X86::RCX : X86::ECX,
17984 swapInH, swapInL.getValue(1));
17985 SDValue Ops[] = { swapInH.getValue(0),
17987 swapInH.getValue(1) };
17988 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17989 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17990 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17991 X86ISD::LCMPXCHG8_DAG;
17992 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17993 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17994 Regs64bit ? X86::RAX : X86::EAX,
17995 HalfT, Result.getValue(1));
17996 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17997 Regs64bit ? X86::RDX : X86::EDX,
17998 HalfT, cpOutL.getValue(2));
17999 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18001 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18002 MVT::i32, cpOutH.getValue(2));
18004 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18005 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18006 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18008 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18009 Results.push_back(Success);
18010 Results.push_back(EFLAGS.getValue(1));
18013 case ISD::ATOMIC_SWAP:
18014 case ISD::ATOMIC_LOAD_ADD:
18015 case ISD::ATOMIC_LOAD_SUB:
18016 case ISD::ATOMIC_LOAD_AND:
18017 case ISD::ATOMIC_LOAD_OR:
18018 case ISD::ATOMIC_LOAD_XOR:
18019 case ISD::ATOMIC_LOAD_NAND:
18020 case ISD::ATOMIC_LOAD_MIN:
18021 case ISD::ATOMIC_LOAD_MAX:
18022 case ISD::ATOMIC_LOAD_UMIN:
18023 case ISD::ATOMIC_LOAD_UMAX:
18024 case ISD::ATOMIC_LOAD: {
18025 // Delegate to generic TypeLegalization. Situations we can really handle
18026 // should have already been dealt with by AtomicExpandPass.cpp.
18029 case ISD::BITCAST: {
18030 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18031 EVT DstVT = N->getValueType(0);
18032 EVT SrcVT = N->getOperand(0)->getValueType(0);
18034 if (SrcVT != MVT::f64 ||
18035 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18038 unsigned NumElts = DstVT.getVectorNumElements();
18039 EVT SVT = DstVT.getVectorElementType();
18040 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18041 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18042 MVT::v2f64, N->getOperand(0));
18043 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18045 if (ExperimentalVectorWideningLegalization) {
18046 // If we are legalizing vectors by widening, we already have the desired
18047 // legal vector type, just return it.
18048 Results.push_back(ToVecInt);
18052 SmallVector<SDValue, 8> Elts;
18053 for (unsigned i = 0, e = NumElts; i != e; ++i)
18054 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18055 ToVecInt, DAG.getIntPtrConstant(i)));
18057 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18062 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18064 default: return nullptr;
18065 case X86ISD::BSF: return "X86ISD::BSF";
18066 case X86ISD::BSR: return "X86ISD::BSR";
18067 case X86ISD::SHLD: return "X86ISD::SHLD";
18068 case X86ISD::SHRD: return "X86ISD::SHRD";
18069 case X86ISD::FAND: return "X86ISD::FAND";
18070 case X86ISD::FANDN: return "X86ISD::FANDN";
18071 case X86ISD::FOR: return "X86ISD::FOR";
18072 case X86ISD::FXOR: return "X86ISD::FXOR";
18073 case X86ISD::FSRL: return "X86ISD::FSRL";
18074 case X86ISD::FILD: return "X86ISD::FILD";
18075 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18076 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18077 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18078 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18079 case X86ISD::FLD: return "X86ISD::FLD";
18080 case X86ISD::FST: return "X86ISD::FST";
18081 case X86ISD::CALL: return "X86ISD::CALL";
18082 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18083 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18084 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18085 case X86ISD::BT: return "X86ISD::BT";
18086 case X86ISD::CMP: return "X86ISD::CMP";
18087 case X86ISD::COMI: return "X86ISD::COMI";
18088 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18089 case X86ISD::CMPM: return "X86ISD::CMPM";
18090 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18091 case X86ISD::SETCC: return "X86ISD::SETCC";
18092 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18093 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18094 case X86ISD::CMOV: return "X86ISD::CMOV";
18095 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18096 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18097 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18098 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18099 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18100 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18101 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18102 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18103 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18104 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18105 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18106 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18107 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18108 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18109 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18110 case X86ISD::BLENDV: return "X86ISD::BLENDV";
18111 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18112 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18113 case X86ISD::HADD: return "X86ISD::HADD";
18114 case X86ISD::HSUB: return "X86ISD::HSUB";
18115 case X86ISD::FHADD: return "X86ISD::FHADD";
18116 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18117 case X86ISD::UMAX: return "X86ISD::UMAX";
18118 case X86ISD::UMIN: return "X86ISD::UMIN";
18119 case X86ISD::SMAX: return "X86ISD::SMAX";
18120 case X86ISD::SMIN: return "X86ISD::SMIN";
18121 case X86ISD::FMAX: return "X86ISD::FMAX";
18122 case X86ISD::FMIN: return "X86ISD::FMIN";
18123 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18124 case X86ISD::FMINC: return "X86ISD::FMINC";
18125 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18126 case X86ISD::FRCP: return "X86ISD::FRCP";
18127 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18128 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18129 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18130 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18131 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18132 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18133 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18134 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18135 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18136 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18137 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18138 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18139 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18140 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18141 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18142 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18143 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18144 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18145 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18146 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18147 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18148 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18149 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18150 case X86ISD::VSHL: return "X86ISD::VSHL";
18151 case X86ISD::VSRL: return "X86ISD::VSRL";
18152 case X86ISD::VSRA: return "X86ISD::VSRA";
18153 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18154 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18155 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18156 case X86ISD::CMPP: return "X86ISD::CMPP";
18157 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18158 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18159 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18160 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18161 case X86ISD::ADD: return "X86ISD::ADD";
18162 case X86ISD::SUB: return "X86ISD::SUB";
18163 case X86ISD::ADC: return "X86ISD::ADC";
18164 case X86ISD::SBB: return "X86ISD::SBB";
18165 case X86ISD::SMUL: return "X86ISD::SMUL";
18166 case X86ISD::UMUL: return "X86ISD::UMUL";
18167 case X86ISD::INC: return "X86ISD::INC";
18168 case X86ISD::DEC: return "X86ISD::DEC";
18169 case X86ISD::OR: return "X86ISD::OR";
18170 case X86ISD::XOR: return "X86ISD::XOR";
18171 case X86ISD::AND: return "X86ISD::AND";
18172 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18173 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18174 case X86ISD::PTEST: return "X86ISD::PTEST";
18175 case X86ISD::TESTP: return "X86ISD::TESTP";
18176 case X86ISD::TESTM: return "X86ISD::TESTM";
18177 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18178 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18179 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18180 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18181 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18182 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18183 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18184 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18185 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18186 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18187 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18188 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18189 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18190 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18191 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18192 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18193 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18194 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18195 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18196 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18197 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18198 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18199 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18200 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18201 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18202 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18203 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18204 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18205 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18206 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18207 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18208 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18209 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18210 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18211 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18212 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18213 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18214 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18215 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18216 case X86ISD::SAHF: return "X86ISD::SAHF";
18217 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18218 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18219 case X86ISD::FMADD: return "X86ISD::FMADD";
18220 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18221 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18222 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18223 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18224 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18225 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18226 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18227 case X86ISD::XTEST: return "X86ISD::XTEST";
18231 // isLegalAddressingMode - Return true if the addressing mode represented
18232 // by AM is legal for this target, for a load/store of the specified type.
18233 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18235 // X86 supports extremely general addressing modes.
18236 CodeModel::Model M = getTargetMachine().getCodeModel();
18237 Reloc::Model R = getTargetMachine().getRelocationModel();
18239 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18240 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18245 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18247 // If a reference to this global requires an extra load, we can't fold it.
18248 if (isGlobalStubReference(GVFlags))
18251 // If BaseGV requires a register for the PIC base, we cannot also have a
18252 // BaseReg specified.
18253 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18256 // If lower 4G is not available, then we must use rip-relative addressing.
18257 if ((M != CodeModel::Small || R != Reloc::Static) &&
18258 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18262 switch (AM.Scale) {
18268 // These scales always work.
18273 // These scales are formed with basereg+scalereg. Only accept if there is
18278 default: // Other stuff never works.
18285 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18286 unsigned Bits = Ty->getScalarSizeInBits();
18288 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18289 // particularly cheaper than those without.
18293 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18294 // variable shifts just as cheap as scalar ones.
18295 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18298 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18299 // fully general vector.
18303 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18304 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18306 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18307 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18308 return NumBits1 > NumBits2;
18311 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18312 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18315 if (!isTypeLegal(EVT::getEVT(Ty1)))
18318 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18320 // Assuming the caller doesn't have a zeroext or signext return parameter,
18321 // truncation all the way down to i1 is valid.
18325 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18326 return isInt<32>(Imm);
18329 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18330 // Can also use sub to handle negated immediates.
18331 return isInt<32>(Imm);
18334 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18335 if (!VT1.isInteger() || !VT2.isInteger())
18337 unsigned NumBits1 = VT1.getSizeInBits();
18338 unsigned NumBits2 = VT2.getSizeInBits();
18339 return NumBits1 > NumBits2;
18342 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18343 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18344 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18347 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18348 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18349 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18352 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18353 EVT VT1 = Val.getValueType();
18354 if (isZExtFree(VT1, VT2))
18357 if (Val.getOpcode() != ISD::LOAD)
18360 if (!VT1.isSimple() || !VT1.isInteger() ||
18361 !VT2.isSimple() || !VT2.isInteger())
18364 switch (VT1.getSimpleVT().SimpleTy) {
18369 // X86 has 8, 16, and 32-bit zero-extending loads.
18377 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18378 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18381 VT = VT.getScalarType();
18383 if (!VT.isSimple())
18386 switch (VT.getSimpleVT().SimpleTy) {
18397 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18398 // i16 instructions are longer (0x66 prefix) and potentially slower.
18399 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18402 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18403 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18404 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18405 /// are assumed to be legal.
18407 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18409 if (!VT.isSimple())
18412 MVT SVT = VT.getSimpleVT();
18414 // Very little shuffling can be done for 64-bit vectors right now.
18415 if (VT.getSizeInBits() == 64)
18418 // If this is a single-input shuffle with no 128 bit lane crossings we can
18419 // lower it into pshufb.
18420 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18421 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18422 bool isLegal = true;
18423 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18424 if (M[I] >= (int)SVT.getVectorNumElements() ||
18425 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18434 // FIXME: blends, shifts.
18435 return (SVT.getVectorNumElements() == 2 ||
18436 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18437 isMOVLMask(M, SVT) ||
18438 isMOVHLPSMask(M, SVT) ||
18439 isSHUFPMask(M, SVT) ||
18440 isPSHUFDMask(M, SVT) ||
18441 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18442 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18443 isPALIGNRMask(M, SVT, Subtarget) ||
18444 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18445 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18446 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18447 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18448 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18452 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18454 if (!VT.isSimple())
18457 MVT SVT = VT.getSimpleVT();
18458 unsigned NumElts = SVT.getVectorNumElements();
18459 // FIXME: This collection of masks seems suspect.
18462 if (NumElts == 4 && SVT.is128BitVector()) {
18463 return (isMOVLMask(Mask, SVT) ||
18464 isCommutedMOVLMask(Mask, SVT, true) ||
18465 isSHUFPMask(Mask, SVT) ||
18466 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18471 //===----------------------------------------------------------------------===//
18472 // X86 Scheduler Hooks
18473 //===----------------------------------------------------------------------===//
18475 /// Utility function to emit xbegin specifying the start of an RTM region.
18476 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18477 const TargetInstrInfo *TII) {
18478 DebugLoc DL = MI->getDebugLoc();
18480 const BasicBlock *BB = MBB->getBasicBlock();
18481 MachineFunction::iterator I = MBB;
18484 // For the v = xbegin(), we generate
18495 MachineBasicBlock *thisMBB = MBB;
18496 MachineFunction *MF = MBB->getParent();
18497 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18498 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18499 MF->insert(I, mainMBB);
18500 MF->insert(I, sinkMBB);
18502 // Transfer the remainder of BB and its successor edges to sinkMBB.
18503 sinkMBB->splice(sinkMBB->begin(), MBB,
18504 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18505 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18509 // # fallthrough to mainMBB
18510 // # abortion to sinkMBB
18511 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18512 thisMBB->addSuccessor(mainMBB);
18513 thisMBB->addSuccessor(sinkMBB);
18517 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18518 mainMBB->addSuccessor(sinkMBB);
18521 // EAX is live into the sinkMBB
18522 sinkMBB->addLiveIn(X86::EAX);
18523 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18524 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18527 MI->eraseFromParent();
18531 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18532 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18533 // in the .td file.
18534 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18535 const TargetInstrInfo *TII) {
18537 switch (MI->getOpcode()) {
18538 default: llvm_unreachable("illegal opcode!");
18539 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18540 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18541 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18542 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18543 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18544 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18545 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18546 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18549 DebugLoc dl = MI->getDebugLoc();
18550 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18552 unsigned NumArgs = MI->getNumOperands();
18553 for (unsigned i = 1; i < NumArgs; ++i) {
18554 MachineOperand &Op = MI->getOperand(i);
18555 if (!(Op.isReg() && Op.isImplicit()))
18556 MIB.addOperand(Op);
18558 if (MI->hasOneMemOperand())
18559 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18561 BuildMI(*BB, MI, dl,
18562 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18563 .addReg(X86::XMM0);
18565 MI->eraseFromParent();
18569 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18570 // defs in an instruction pattern
18571 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18572 const TargetInstrInfo *TII) {
18574 switch (MI->getOpcode()) {
18575 default: llvm_unreachable("illegal opcode!");
18576 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18577 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18578 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18579 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18580 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18581 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18582 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18583 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18586 DebugLoc dl = MI->getDebugLoc();
18587 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18589 unsigned NumArgs = MI->getNumOperands(); // remove the results
18590 for (unsigned i = 1; i < NumArgs; ++i) {
18591 MachineOperand &Op = MI->getOperand(i);
18592 if (!(Op.isReg() && Op.isImplicit()))
18593 MIB.addOperand(Op);
18595 if (MI->hasOneMemOperand())
18596 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18598 BuildMI(*BB, MI, dl,
18599 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18602 MI->eraseFromParent();
18606 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18607 const TargetInstrInfo *TII,
18608 const X86Subtarget* Subtarget) {
18609 DebugLoc dl = MI->getDebugLoc();
18611 // Address into RAX/EAX, other two args into ECX, EDX.
18612 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18613 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18614 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18615 for (int i = 0; i < X86::AddrNumOperands; ++i)
18616 MIB.addOperand(MI->getOperand(i));
18618 unsigned ValOps = X86::AddrNumOperands;
18619 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18620 .addReg(MI->getOperand(ValOps).getReg());
18621 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18622 .addReg(MI->getOperand(ValOps+1).getReg());
18624 // The instruction doesn't actually take any operands though.
18625 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18627 MI->eraseFromParent(); // The pseudo is gone now.
18631 MachineBasicBlock *
18632 X86TargetLowering::EmitVAARG64WithCustomInserter(
18634 MachineBasicBlock *MBB) const {
18635 // Emit va_arg instruction on X86-64.
18637 // Operands to this pseudo-instruction:
18638 // 0 ) Output : destination address (reg)
18639 // 1-5) Input : va_list address (addr, i64mem)
18640 // 6 ) ArgSize : Size (in bytes) of vararg type
18641 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18642 // 8 ) Align : Alignment of type
18643 // 9 ) EFLAGS (implicit-def)
18645 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18646 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18648 unsigned DestReg = MI->getOperand(0).getReg();
18649 MachineOperand &Base = MI->getOperand(1);
18650 MachineOperand &Scale = MI->getOperand(2);
18651 MachineOperand &Index = MI->getOperand(3);
18652 MachineOperand &Disp = MI->getOperand(4);
18653 MachineOperand &Segment = MI->getOperand(5);
18654 unsigned ArgSize = MI->getOperand(6).getImm();
18655 unsigned ArgMode = MI->getOperand(7).getImm();
18656 unsigned Align = MI->getOperand(8).getImm();
18658 // Memory Reference
18659 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18660 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18661 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18663 // Machine Information
18664 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18665 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18666 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18667 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18668 DebugLoc DL = MI->getDebugLoc();
18670 // struct va_list {
18673 // i64 overflow_area (address)
18674 // i64 reg_save_area (address)
18676 // sizeof(va_list) = 24
18677 // alignment(va_list) = 8
18679 unsigned TotalNumIntRegs = 6;
18680 unsigned TotalNumXMMRegs = 8;
18681 bool UseGPOffset = (ArgMode == 1);
18682 bool UseFPOffset = (ArgMode == 2);
18683 unsigned MaxOffset = TotalNumIntRegs * 8 +
18684 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18686 /* Align ArgSize to a multiple of 8 */
18687 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18688 bool NeedsAlign = (Align > 8);
18690 MachineBasicBlock *thisMBB = MBB;
18691 MachineBasicBlock *overflowMBB;
18692 MachineBasicBlock *offsetMBB;
18693 MachineBasicBlock *endMBB;
18695 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18696 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18697 unsigned OffsetReg = 0;
18699 if (!UseGPOffset && !UseFPOffset) {
18700 // If we only pull from the overflow region, we don't create a branch.
18701 // We don't need to alter control flow.
18702 OffsetDestReg = 0; // unused
18703 OverflowDestReg = DestReg;
18705 offsetMBB = nullptr;
18706 overflowMBB = thisMBB;
18709 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18710 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18711 // If not, pull from overflow_area. (branch to overflowMBB)
18716 // offsetMBB overflowMBB
18721 // Registers for the PHI in endMBB
18722 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18723 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18725 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18726 MachineFunction *MF = MBB->getParent();
18727 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18728 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18729 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18731 MachineFunction::iterator MBBIter = MBB;
18734 // Insert the new basic blocks
18735 MF->insert(MBBIter, offsetMBB);
18736 MF->insert(MBBIter, overflowMBB);
18737 MF->insert(MBBIter, endMBB);
18739 // Transfer the remainder of MBB and its successor edges to endMBB.
18740 endMBB->splice(endMBB->begin(), thisMBB,
18741 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18742 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18744 // Make offsetMBB and overflowMBB successors of thisMBB
18745 thisMBB->addSuccessor(offsetMBB);
18746 thisMBB->addSuccessor(overflowMBB);
18748 // endMBB is a successor of both offsetMBB and overflowMBB
18749 offsetMBB->addSuccessor(endMBB);
18750 overflowMBB->addSuccessor(endMBB);
18752 // Load the offset value into a register
18753 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18754 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18758 .addDisp(Disp, UseFPOffset ? 4 : 0)
18759 .addOperand(Segment)
18760 .setMemRefs(MMOBegin, MMOEnd);
18762 // Check if there is enough room left to pull this argument.
18763 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18765 .addImm(MaxOffset + 8 - ArgSizeA8);
18767 // Branch to "overflowMBB" if offset >= max
18768 // Fall through to "offsetMBB" otherwise
18769 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18770 .addMBB(overflowMBB);
18773 // In offsetMBB, emit code to use the reg_save_area.
18775 assert(OffsetReg != 0);
18777 // Read the reg_save_area address.
18778 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18779 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18784 .addOperand(Segment)
18785 .setMemRefs(MMOBegin, MMOEnd);
18787 // Zero-extend the offset
18788 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18789 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18792 .addImm(X86::sub_32bit);
18794 // Add the offset to the reg_save_area to get the final address.
18795 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18796 .addReg(OffsetReg64)
18797 .addReg(RegSaveReg);
18799 // Compute the offset for the next argument
18800 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18801 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18803 .addImm(UseFPOffset ? 16 : 8);
18805 // Store it back into the va_list.
18806 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18810 .addDisp(Disp, UseFPOffset ? 4 : 0)
18811 .addOperand(Segment)
18812 .addReg(NextOffsetReg)
18813 .setMemRefs(MMOBegin, MMOEnd);
18816 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18821 // Emit code to use overflow area
18824 // Load the overflow_area address into a register.
18825 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18826 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18831 .addOperand(Segment)
18832 .setMemRefs(MMOBegin, MMOEnd);
18834 // If we need to align it, do so. Otherwise, just copy the address
18835 // to OverflowDestReg.
18837 // Align the overflow address
18838 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18839 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18841 // aligned_addr = (addr + (align-1)) & ~(align-1)
18842 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18843 .addReg(OverflowAddrReg)
18846 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18848 .addImm(~(uint64_t)(Align-1));
18850 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18851 .addReg(OverflowAddrReg);
18854 // Compute the next overflow address after this argument.
18855 // (the overflow address should be kept 8-byte aligned)
18856 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18857 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18858 .addReg(OverflowDestReg)
18859 .addImm(ArgSizeA8);
18861 // Store the new overflow address.
18862 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18867 .addOperand(Segment)
18868 .addReg(NextAddrReg)
18869 .setMemRefs(MMOBegin, MMOEnd);
18871 // If we branched, emit the PHI to the front of endMBB.
18873 BuildMI(*endMBB, endMBB->begin(), DL,
18874 TII->get(X86::PHI), DestReg)
18875 .addReg(OffsetDestReg).addMBB(offsetMBB)
18876 .addReg(OverflowDestReg).addMBB(overflowMBB);
18879 // Erase the pseudo instruction
18880 MI->eraseFromParent();
18885 MachineBasicBlock *
18886 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18888 MachineBasicBlock *MBB) const {
18889 // Emit code to save XMM registers to the stack. The ABI says that the
18890 // number of registers to save is given in %al, so it's theoretically
18891 // possible to do an indirect jump trick to avoid saving all of them,
18892 // however this code takes a simpler approach and just executes all
18893 // of the stores if %al is non-zero. It's less code, and it's probably
18894 // easier on the hardware branch predictor, and stores aren't all that
18895 // expensive anyway.
18897 // Create the new basic blocks. One block contains all the XMM stores,
18898 // and one block is the final destination regardless of whether any
18899 // stores were performed.
18900 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18901 MachineFunction *F = MBB->getParent();
18902 MachineFunction::iterator MBBIter = MBB;
18904 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18905 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18906 F->insert(MBBIter, XMMSaveMBB);
18907 F->insert(MBBIter, EndMBB);
18909 // Transfer the remainder of MBB and its successor edges to EndMBB.
18910 EndMBB->splice(EndMBB->begin(), MBB,
18911 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18912 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18914 // The original block will now fall through to the XMM save block.
18915 MBB->addSuccessor(XMMSaveMBB);
18916 // The XMMSaveMBB will fall through to the end block.
18917 XMMSaveMBB->addSuccessor(EndMBB);
18919 // Now add the instructions.
18920 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18921 DebugLoc DL = MI->getDebugLoc();
18923 unsigned CountReg = MI->getOperand(0).getReg();
18924 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18925 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18927 if (!Subtarget->isTargetWin64()) {
18928 // If %al is 0, branch around the XMM save block.
18929 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18930 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18931 MBB->addSuccessor(EndMBB);
18934 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18935 // that was just emitted, but clearly shouldn't be "saved".
18936 assert((MI->getNumOperands() <= 3 ||
18937 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18938 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18939 && "Expected last argument to be EFLAGS");
18940 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18941 // In the XMM save block, save all the XMM argument registers.
18942 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18943 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18944 MachineMemOperand *MMO =
18945 F->getMachineMemOperand(
18946 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18947 MachineMemOperand::MOStore,
18948 /*Size=*/16, /*Align=*/16);
18949 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18950 .addFrameIndex(RegSaveFrameIndex)
18951 .addImm(/*Scale=*/1)
18952 .addReg(/*IndexReg=*/0)
18953 .addImm(/*Disp=*/Offset)
18954 .addReg(/*Segment=*/0)
18955 .addReg(MI->getOperand(i).getReg())
18956 .addMemOperand(MMO);
18959 MI->eraseFromParent(); // The pseudo instruction is gone now.
18964 // The EFLAGS operand of SelectItr might be missing a kill marker
18965 // because there were multiple uses of EFLAGS, and ISel didn't know
18966 // which to mark. Figure out whether SelectItr should have had a
18967 // kill marker, and set it if it should. Returns the correct kill
18969 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18970 MachineBasicBlock* BB,
18971 const TargetRegisterInfo* TRI) {
18972 // Scan forward through BB for a use/def of EFLAGS.
18973 MachineBasicBlock::iterator miI(std::next(SelectItr));
18974 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18975 const MachineInstr& mi = *miI;
18976 if (mi.readsRegister(X86::EFLAGS))
18978 if (mi.definesRegister(X86::EFLAGS))
18979 break; // Should have kill-flag - update below.
18982 // If we hit the end of the block, check whether EFLAGS is live into a
18984 if (miI == BB->end()) {
18985 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18986 sEnd = BB->succ_end();
18987 sItr != sEnd; ++sItr) {
18988 MachineBasicBlock* succ = *sItr;
18989 if (succ->isLiveIn(X86::EFLAGS))
18994 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18995 // out. SelectMI should have a kill flag on EFLAGS.
18996 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19000 MachineBasicBlock *
19001 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19002 MachineBasicBlock *BB) const {
19003 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19004 DebugLoc DL = MI->getDebugLoc();
19006 // To "insert" a SELECT_CC instruction, we actually have to insert the
19007 // diamond control-flow pattern. The incoming instruction knows the
19008 // destination vreg to set, the condition code register to branch on, the
19009 // true/false values to select between, and a branch opcode to use.
19010 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19011 MachineFunction::iterator It = BB;
19017 // cmpTY ccX, r1, r2
19019 // fallthrough --> copy0MBB
19020 MachineBasicBlock *thisMBB = BB;
19021 MachineFunction *F = BB->getParent();
19022 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19023 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19024 F->insert(It, copy0MBB);
19025 F->insert(It, sinkMBB);
19027 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19028 // live into the sink and copy blocks.
19029 const TargetRegisterInfo *TRI =
19030 BB->getParent()->getSubtarget().getRegisterInfo();
19031 if (!MI->killsRegister(X86::EFLAGS) &&
19032 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19033 copy0MBB->addLiveIn(X86::EFLAGS);
19034 sinkMBB->addLiveIn(X86::EFLAGS);
19037 // Transfer the remainder of BB and its successor edges to sinkMBB.
19038 sinkMBB->splice(sinkMBB->begin(), BB,
19039 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19040 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19042 // Add the true and fallthrough blocks as its successors.
19043 BB->addSuccessor(copy0MBB);
19044 BB->addSuccessor(sinkMBB);
19046 // Create the conditional branch instruction.
19048 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19049 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19052 // %FalseValue = ...
19053 // # fallthrough to sinkMBB
19054 copy0MBB->addSuccessor(sinkMBB);
19057 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19059 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19060 TII->get(X86::PHI), MI->getOperand(0).getReg())
19061 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19062 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19064 MI->eraseFromParent(); // The pseudo instruction is gone now.
19068 MachineBasicBlock *
19069 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19070 MachineBasicBlock *BB) const {
19071 MachineFunction *MF = BB->getParent();
19072 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19073 DebugLoc DL = MI->getDebugLoc();
19074 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19076 assert(MF->shouldSplitStack());
19078 const bool Is64Bit = Subtarget->is64Bit();
19079 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19081 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19082 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19085 // ... [Till the alloca]
19086 // If stacklet is not large enough, jump to mallocMBB
19089 // Allocate by subtracting from RSP
19090 // Jump to continueMBB
19093 // Allocate by call to runtime
19097 // [rest of original BB]
19100 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19101 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19102 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19104 MachineRegisterInfo &MRI = MF->getRegInfo();
19105 const TargetRegisterClass *AddrRegClass =
19106 getRegClassFor(getPointerTy());
19108 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19109 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19110 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19111 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19112 sizeVReg = MI->getOperand(1).getReg(),
19113 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19115 MachineFunction::iterator MBBIter = BB;
19118 MF->insert(MBBIter, bumpMBB);
19119 MF->insert(MBBIter, mallocMBB);
19120 MF->insert(MBBIter, continueMBB);
19122 continueMBB->splice(continueMBB->begin(), BB,
19123 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19124 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19126 // Add code to the main basic block to check if the stack limit has been hit,
19127 // and if so, jump to mallocMBB otherwise to bumpMBB.
19128 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19129 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19130 .addReg(tmpSPVReg).addReg(sizeVReg);
19131 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19132 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19133 .addReg(SPLimitVReg);
19134 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19136 // bumpMBB simply decreases the stack pointer, since we know the current
19137 // stacklet has enough space.
19138 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19139 .addReg(SPLimitVReg);
19140 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19141 .addReg(SPLimitVReg);
19142 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19144 // Calls into a routine in libgcc to allocate more space from the heap.
19145 const uint32_t *RegMask = MF->getTarget()
19146 .getSubtargetImpl()
19147 ->getRegisterInfo()
19148 ->getCallPreservedMask(CallingConv::C);
19150 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19152 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19153 .addExternalSymbol("__morestack_allocate_stack_space")
19154 .addRegMask(RegMask)
19155 .addReg(X86::RDI, RegState::Implicit)
19156 .addReg(X86::RAX, RegState::ImplicitDefine);
19157 } else if (Is64Bit) {
19158 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19160 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19161 .addExternalSymbol("__morestack_allocate_stack_space")
19162 .addRegMask(RegMask)
19163 .addReg(X86::EDI, RegState::Implicit)
19164 .addReg(X86::EAX, RegState::ImplicitDefine);
19166 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19168 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19169 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19170 .addExternalSymbol("__morestack_allocate_stack_space")
19171 .addRegMask(RegMask)
19172 .addReg(X86::EAX, RegState::ImplicitDefine);
19176 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19179 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19180 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19181 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19183 // Set up the CFG correctly.
19184 BB->addSuccessor(bumpMBB);
19185 BB->addSuccessor(mallocMBB);
19186 mallocMBB->addSuccessor(continueMBB);
19187 bumpMBB->addSuccessor(continueMBB);
19189 // Take care of the PHI nodes.
19190 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19191 MI->getOperand(0).getReg())
19192 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19193 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19195 // Delete the original pseudo instruction.
19196 MI->eraseFromParent();
19199 return continueMBB;
19202 MachineBasicBlock *
19203 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19204 MachineBasicBlock *BB) const {
19205 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19206 DebugLoc DL = MI->getDebugLoc();
19208 assert(!Subtarget->isTargetMacho());
19210 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19211 // non-trivial part is impdef of ESP.
19213 if (Subtarget->isTargetWin64()) {
19214 if (Subtarget->isTargetCygMing()) {
19215 // ___chkstk(Mingw64):
19216 // Clobbers R10, R11, RAX and EFLAGS.
19218 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19219 .addExternalSymbol("___chkstk")
19220 .addReg(X86::RAX, RegState::Implicit)
19221 .addReg(X86::RSP, RegState::Implicit)
19222 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19223 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19224 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19226 // __chkstk(MSVCRT): does not update stack pointer.
19227 // Clobbers R10, R11 and EFLAGS.
19228 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19229 .addExternalSymbol("__chkstk")
19230 .addReg(X86::RAX, RegState::Implicit)
19231 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19232 // RAX has the offset to be subtracted from RSP.
19233 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19238 const char *StackProbeSymbol =
19239 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19241 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19242 .addExternalSymbol(StackProbeSymbol)
19243 .addReg(X86::EAX, RegState::Implicit)
19244 .addReg(X86::ESP, RegState::Implicit)
19245 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19246 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19247 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19250 MI->eraseFromParent(); // The pseudo instruction is gone now.
19254 MachineBasicBlock *
19255 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19256 MachineBasicBlock *BB) const {
19257 // This is pretty easy. We're taking the value that we received from
19258 // our load from the relocation, sticking it in either RDI (x86-64)
19259 // or EAX and doing an indirect call. The return value will then
19260 // be in the normal return register.
19261 MachineFunction *F = BB->getParent();
19262 const X86InstrInfo *TII =
19263 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19264 DebugLoc DL = MI->getDebugLoc();
19266 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19267 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19269 // Get a register mask for the lowered call.
19270 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19271 // proper register mask.
19272 const uint32_t *RegMask = F->getTarget()
19273 .getSubtargetImpl()
19274 ->getRegisterInfo()
19275 ->getCallPreservedMask(CallingConv::C);
19276 if (Subtarget->is64Bit()) {
19277 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19278 TII->get(X86::MOV64rm), X86::RDI)
19280 .addImm(0).addReg(0)
19281 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19282 MI->getOperand(3).getTargetFlags())
19284 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19285 addDirectMem(MIB, X86::RDI);
19286 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19287 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19288 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19289 TII->get(X86::MOV32rm), X86::EAX)
19291 .addImm(0).addReg(0)
19292 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19293 MI->getOperand(3).getTargetFlags())
19295 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19296 addDirectMem(MIB, X86::EAX);
19297 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19299 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19300 TII->get(X86::MOV32rm), X86::EAX)
19301 .addReg(TII->getGlobalBaseReg(F))
19302 .addImm(0).addReg(0)
19303 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19304 MI->getOperand(3).getTargetFlags())
19306 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19307 addDirectMem(MIB, X86::EAX);
19308 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19311 MI->eraseFromParent(); // The pseudo instruction is gone now.
19315 MachineBasicBlock *
19316 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19317 MachineBasicBlock *MBB) const {
19318 DebugLoc DL = MI->getDebugLoc();
19319 MachineFunction *MF = MBB->getParent();
19320 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19321 MachineRegisterInfo &MRI = MF->getRegInfo();
19323 const BasicBlock *BB = MBB->getBasicBlock();
19324 MachineFunction::iterator I = MBB;
19327 // Memory Reference
19328 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19329 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19332 unsigned MemOpndSlot = 0;
19334 unsigned CurOp = 0;
19336 DstReg = MI->getOperand(CurOp++).getReg();
19337 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19338 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19339 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19340 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19342 MemOpndSlot = CurOp;
19344 MVT PVT = getPointerTy();
19345 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19346 "Invalid Pointer Size!");
19348 // For v = setjmp(buf), we generate
19351 // buf[LabelOffset] = restoreMBB
19352 // SjLjSetup restoreMBB
19358 // v = phi(main, restore)
19363 MachineBasicBlock *thisMBB = MBB;
19364 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19365 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19366 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19367 MF->insert(I, mainMBB);
19368 MF->insert(I, sinkMBB);
19369 MF->push_back(restoreMBB);
19371 MachineInstrBuilder MIB;
19373 // Transfer the remainder of BB and its successor edges to sinkMBB.
19374 sinkMBB->splice(sinkMBB->begin(), MBB,
19375 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19376 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19379 unsigned PtrStoreOpc = 0;
19380 unsigned LabelReg = 0;
19381 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19382 Reloc::Model RM = MF->getTarget().getRelocationModel();
19383 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19384 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19386 // Prepare IP either in reg or imm.
19387 if (!UseImmLabel) {
19388 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19389 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19390 LabelReg = MRI.createVirtualRegister(PtrRC);
19391 if (Subtarget->is64Bit()) {
19392 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19396 .addMBB(restoreMBB)
19399 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19400 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19401 .addReg(XII->getGlobalBaseReg(MF))
19404 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19408 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19410 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19411 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19412 if (i == X86::AddrDisp)
19413 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19415 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19418 MIB.addReg(LabelReg);
19420 MIB.addMBB(restoreMBB);
19421 MIB.setMemRefs(MMOBegin, MMOEnd);
19423 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19424 .addMBB(restoreMBB);
19426 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19427 MF->getSubtarget().getRegisterInfo());
19428 MIB.addRegMask(RegInfo->getNoPreservedMask());
19429 thisMBB->addSuccessor(mainMBB);
19430 thisMBB->addSuccessor(restoreMBB);
19434 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19435 mainMBB->addSuccessor(sinkMBB);
19438 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19439 TII->get(X86::PHI), DstReg)
19440 .addReg(mainDstReg).addMBB(mainMBB)
19441 .addReg(restoreDstReg).addMBB(restoreMBB);
19444 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19445 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19446 restoreMBB->addSuccessor(sinkMBB);
19448 MI->eraseFromParent();
19452 MachineBasicBlock *
19453 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19454 MachineBasicBlock *MBB) const {
19455 DebugLoc DL = MI->getDebugLoc();
19456 MachineFunction *MF = MBB->getParent();
19457 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19458 MachineRegisterInfo &MRI = MF->getRegInfo();
19460 // Memory Reference
19461 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19462 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19464 MVT PVT = getPointerTy();
19465 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19466 "Invalid Pointer Size!");
19468 const TargetRegisterClass *RC =
19469 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19470 unsigned Tmp = MRI.createVirtualRegister(RC);
19471 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19472 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19473 MF->getSubtarget().getRegisterInfo());
19474 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19475 unsigned SP = RegInfo->getStackRegister();
19477 MachineInstrBuilder MIB;
19479 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19480 const int64_t SPOffset = 2 * PVT.getStoreSize();
19482 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19483 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19486 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19487 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19488 MIB.addOperand(MI->getOperand(i));
19489 MIB.setMemRefs(MMOBegin, MMOEnd);
19491 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19492 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19493 if (i == X86::AddrDisp)
19494 MIB.addDisp(MI->getOperand(i), LabelOffset);
19496 MIB.addOperand(MI->getOperand(i));
19498 MIB.setMemRefs(MMOBegin, MMOEnd);
19500 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19501 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19502 if (i == X86::AddrDisp)
19503 MIB.addDisp(MI->getOperand(i), SPOffset);
19505 MIB.addOperand(MI->getOperand(i));
19507 MIB.setMemRefs(MMOBegin, MMOEnd);
19509 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19511 MI->eraseFromParent();
19515 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19516 // accumulator loops. Writing back to the accumulator allows the coalescer
19517 // to remove extra copies in the loop.
19518 MachineBasicBlock *
19519 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19520 MachineBasicBlock *MBB) const {
19521 MachineOperand &AddendOp = MI->getOperand(3);
19523 // Bail out early if the addend isn't a register - we can't switch these.
19524 if (!AddendOp.isReg())
19527 MachineFunction &MF = *MBB->getParent();
19528 MachineRegisterInfo &MRI = MF.getRegInfo();
19530 // Check whether the addend is defined by a PHI:
19531 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19532 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19533 if (!AddendDef.isPHI())
19536 // Look for the following pattern:
19538 // %addend = phi [%entry, 0], [%loop, %result]
19540 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19544 // %addend = phi [%entry, 0], [%loop, %result]
19546 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19548 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19549 assert(AddendDef.getOperand(i).isReg());
19550 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19551 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19552 if (&PHISrcInst == MI) {
19553 // Found a matching instruction.
19554 unsigned NewFMAOpc = 0;
19555 switch (MI->getOpcode()) {
19556 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19557 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19558 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19559 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19560 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19561 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19562 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19563 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19564 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19565 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19566 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19567 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19568 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19569 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19570 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19571 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19572 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19573 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19574 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19575 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19576 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19577 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19578 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19579 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19580 default: llvm_unreachable("Unrecognized FMA variant.");
19583 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19584 MachineInstrBuilder MIB =
19585 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19586 .addOperand(MI->getOperand(0))
19587 .addOperand(MI->getOperand(3))
19588 .addOperand(MI->getOperand(2))
19589 .addOperand(MI->getOperand(1));
19590 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19591 MI->eraseFromParent();
19598 MachineBasicBlock *
19599 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19600 MachineBasicBlock *BB) const {
19601 switch (MI->getOpcode()) {
19602 default: llvm_unreachable("Unexpected instr type to insert");
19603 case X86::TAILJMPd64:
19604 case X86::TAILJMPr64:
19605 case X86::TAILJMPm64:
19606 llvm_unreachable("TAILJMP64 would not be touched here.");
19607 case X86::TCRETURNdi64:
19608 case X86::TCRETURNri64:
19609 case X86::TCRETURNmi64:
19611 case X86::WIN_ALLOCA:
19612 return EmitLoweredWinAlloca(MI, BB);
19613 case X86::SEG_ALLOCA_32:
19614 case X86::SEG_ALLOCA_64:
19615 return EmitLoweredSegAlloca(MI, BB);
19616 case X86::TLSCall_32:
19617 case X86::TLSCall_64:
19618 return EmitLoweredTLSCall(MI, BB);
19619 case X86::CMOV_GR8:
19620 case X86::CMOV_FR32:
19621 case X86::CMOV_FR64:
19622 case X86::CMOV_V4F32:
19623 case X86::CMOV_V2F64:
19624 case X86::CMOV_V2I64:
19625 case X86::CMOV_V8F32:
19626 case X86::CMOV_V4F64:
19627 case X86::CMOV_V4I64:
19628 case X86::CMOV_V16F32:
19629 case X86::CMOV_V8F64:
19630 case X86::CMOV_V8I64:
19631 case X86::CMOV_GR16:
19632 case X86::CMOV_GR32:
19633 case X86::CMOV_RFP32:
19634 case X86::CMOV_RFP64:
19635 case X86::CMOV_RFP80:
19636 return EmitLoweredSelect(MI, BB);
19638 case X86::FP32_TO_INT16_IN_MEM:
19639 case X86::FP32_TO_INT32_IN_MEM:
19640 case X86::FP32_TO_INT64_IN_MEM:
19641 case X86::FP64_TO_INT16_IN_MEM:
19642 case X86::FP64_TO_INT32_IN_MEM:
19643 case X86::FP64_TO_INT64_IN_MEM:
19644 case X86::FP80_TO_INT16_IN_MEM:
19645 case X86::FP80_TO_INT32_IN_MEM:
19646 case X86::FP80_TO_INT64_IN_MEM: {
19647 MachineFunction *F = BB->getParent();
19648 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19649 DebugLoc DL = MI->getDebugLoc();
19651 // Change the floating point control register to use "round towards zero"
19652 // mode when truncating to an integer value.
19653 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19654 addFrameReference(BuildMI(*BB, MI, DL,
19655 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19657 // Load the old value of the high byte of the control word...
19659 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19660 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19663 // Set the high part to be round to zero...
19664 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19667 // Reload the modified control word now...
19668 addFrameReference(BuildMI(*BB, MI, DL,
19669 TII->get(X86::FLDCW16m)), CWFrameIdx);
19671 // Restore the memory image of control word to original value
19672 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19675 // Get the X86 opcode to use.
19677 switch (MI->getOpcode()) {
19678 default: llvm_unreachable("illegal opcode!");
19679 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19680 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19681 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19682 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19683 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19684 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19685 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19686 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19687 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19691 MachineOperand &Op = MI->getOperand(0);
19693 AM.BaseType = X86AddressMode::RegBase;
19694 AM.Base.Reg = Op.getReg();
19696 AM.BaseType = X86AddressMode::FrameIndexBase;
19697 AM.Base.FrameIndex = Op.getIndex();
19699 Op = MI->getOperand(1);
19701 AM.Scale = Op.getImm();
19702 Op = MI->getOperand(2);
19704 AM.IndexReg = Op.getImm();
19705 Op = MI->getOperand(3);
19706 if (Op.isGlobal()) {
19707 AM.GV = Op.getGlobal();
19709 AM.Disp = Op.getImm();
19711 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19712 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19714 // Reload the original control word now.
19715 addFrameReference(BuildMI(*BB, MI, DL,
19716 TII->get(X86::FLDCW16m)), CWFrameIdx);
19718 MI->eraseFromParent(); // The pseudo instruction is gone now.
19721 // String/text processing lowering.
19722 case X86::PCMPISTRM128REG:
19723 case X86::VPCMPISTRM128REG:
19724 case X86::PCMPISTRM128MEM:
19725 case X86::VPCMPISTRM128MEM:
19726 case X86::PCMPESTRM128REG:
19727 case X86::VPCMPESTRM128REG:
19728 case X86::PCMPESTRM128MEM:
19729 case X86::VPCMPESTRM128MEM:
19730 assert(Subtarget->hasSSE42() &&
19731 "Target must have SSE4.2 or AVX features enabled");
19732 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19734 // String/text processing lowering.
19735 case X86::PCMPISTRIREG:
19736 case X86::VPCMPISTRIREG:
19737 case X86::PCMPISTRIMEM:
19738 case X86::VPCMPISTRIMEM:
19739 case X86::PCMPESTRIREG:
19740 case X86::VPCMPESTRIREG:
19741 case X86::PCMPESTRIMEM:
19742 case X86::VPCMPESTRIMEM:
19743 assert(Subtarget->hasSSE42() &&
19744 "Target must have SSE4.2 or AVX features enabled");
19745 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19747 // Thread synchronization.
19749 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19754 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19756 case X86::VASTART_SAVE_XMM_REGS:
19757 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19759 case X86::VAARG_64:
19760 return EmitVAARG64WithCustomInserter(MI, BB);
19762 case X86::EH_SjLj_SetJmp32:
19763 case X86::EH_SjLj_SetJmp64:
19764 return emitEHSjLjSetJmp(MI, BB);
19766 case X86::EH_SjLj_LongJmp32:
19767 case X86::EH_SjLj_LongJmp64:
19768 return emitEHSjLjLongJmp(MI, BB);
19770 case TargetOpcode::STACKMAP:
19771 case TargetOpcode::PATCHPOINT:
19772 return emitPatchPoint(MI, BB);
19774 case X86::VFMADDPDr213r:
19775 case X86::VFMADDPSr213r:
19776 case X86::VFMADDSDr213r:
19777 case X86::VFMADDSSr213r:
19778 case X86::VFMSUBPDr213r:
19779 case X86::VFMSUBPSr213r:
19780 case X86::VFMSUBSDr213r:
19781 case X86::VFMSUBSSr213r:
19782 case X86::VFNMADDPDr213r:
19783 case X86::VFNMADDPSr213r:
19784 case X86::VFNMADDSDr213r:
19785 case X86::VFNMADDSSr213r:
19786 case X86::VFNMSUBPDr213r:
19787 case X86::VFNMSUBPSr213r:
19788 case X86::VFNMSUBSDr213r:
19789 case X86::VFNMSUBSSr213r:
19790 case X86::VFMADDPDr213rY:
19791 case X86::VFMADDPSr213rY:
19792 case X86::VFMSUBPDr213rY:
19793 case X86::VFMSUBPSr213rY:
19794 case X86::VFNMADDPDr213rY:
19795 case X86::VFNMADDPSr213rY:
19796 case X86::VFNMSUBPDr213rY:
19797 case X86::VFNMSUBPSr213rY:
19798 return emitFMA3Instr(MI, BB);
19802 //===----------------------------------------------------------------------===//
19803 // X86 Optimization Hooks
19804 //===----------------------------------------------------------------------===//
19806 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19809 const SelectionDAG &DAG,
19810 unsigned Depth) const {
19811 unsigned BitWidth = KnownZero.getBitWidth();
19812 unsigned Opc = Op.getOpcode();
19813 assert((Opc >= ISD::BUILTIN_OP_END ||
19814 Opc == ISD::INTRINSIC_WO_CHAIN ||
19815 Opc == ISD::INTRINSIC_W_CHAIN ||
19816 Opc == ISD::INTRINSIC_VOID) &&
19817 "Should use MaskedValueIsZero if you don't know whether Op"
19818 " is a target node!");
19820 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19834 // These nodes' second result is a boolean.
19835 if (Op.getResNo() == 0)
19838 case X86ISD::SETCC:
19839 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19841 case ISD::INTRINSIC_WO_CHAIN: {
19842 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19843 unsigned NumLoBits = 0;
19846 case Intrinsic::x86_sse_movmsk_ps:
19847 case Intrinsic::x86_avx_movmsk_ps_256:
19848 case Intrinsic::x86_sse2_movmsk_pd:
19849 case Intrinsic::x86_avx_movmsk_pd_256:
19850 case Intrinsic::x86_mmx_pmovmskb:
19851 case Intrinsic::x86_sse2_pmovmskb_128:
19852 case Intrinsic::x86_avx2_pmovmskb: {
19853 // High bits of movmskp{s|d}, pmovmskb are known zero.
19855 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19856 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19857 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19858 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19859 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19860 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19861 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19862 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19864 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19873 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19875 const SelectionDAG &,
19876 unsigned Depth) const {
19877 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19878 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19879 return Op.getValueType().getScalarType().getSizeInBits();
19885 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19886 /// node is a GlobalAddress + offset.
19887 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19888 const GlobalValue* &GA,
19889 int64_t &Offset) const {
19890 if (N->getOpcode() == X86ISD::Wrapper) {
19891 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19892 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19893 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19897 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19900 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19901 /// same as extracting the high 128-bit part of 256-bit vector and then
19902 /// inserting the result into the low part of a new 256-bit vector
19903 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19904 EVT VT = SVOp->getValueType(0);
19905 unsigned NumElems = VT.getVectorNumElements();
19907 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19908 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19909 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19910 SVOp->getMaskElt(j) >= 0)
19916 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19917 /// same as extracting the low 128-bit part of 256-bit vector and then
19918 /// inserting the result into the high part of a new 256-bit vector
19919 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19920 EVT VT = SVOp->getValueType(0);
19921 unsigned NumElems = VT.getVectorNumElements();
19923 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19924 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19925 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19926 SVOp->getMaskElt(j) >= 0)
19932 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19933 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19934 TargetLowering::DAGCombinerInfo &DCI,
19935 const X86Subtarget* Subtarget) {
19937 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19938 SDValue V1 = SVOp->getOperand(0);
19939 SDValue V2 = SVOp->getOperand(1);
19940 EVT VT = SVOp->getValueType(0);
19941 unsigned NumElems = VT.getVectorNumElements();
19943 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19944 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19948 // V UNDEF BUILD_VECTOR UNDEF
19950 // CONCAT_VECTOR CONCAT_VECTOR
19953 // RESULT: V + zero extended
19955 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19956 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19957 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19960 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19963 // To match the shuffle mask, the first half of the mask should
19964 // be exactly the first vector, and all the rest a splat with the
19965 // first element of the second one.
19966 for (unsigned i = 0; i != NumElems/2; ++i)
19967 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19968 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19971 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19972 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19973 if (Ld->hasNUsesOfValue(1, 0)) {
19974 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19975 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19977 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19979 Ld->getPointerInfo(),
19980 Ld->getAlignment(),
19981 false/*isVolatile*/, true/*ReadMem*/,
19982 false/*WriteMem*/);
19984 // Make sure the newly-created LOAD is in the same position as Ld in
19985 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19986 // and update uses of Ld's output chain to use the TokenFactor.
19987 if (Ld->hasAnyUseOfValue(1)) {
19988 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19989 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19990 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19991 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19992 SDValue(ResNode.getNode(), 1));
19995 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19999 // Emit a zeroed vector and insert the desired subvector on its
20001 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20002 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20003 return DCI.CombineTo(N, InsV);
20006 //===--------------------------------------------------------------------===//
20007 // Combine some shuffles into subvector extracts and inserts:
20010 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20011 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20012 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20013 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20014 return DCI.CombineTo(N, InsV);
20017 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20018 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20019 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20020 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20021 return DCI.CombineTo(N, InsV);
20027 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20030 /// This is the leaf of the recursive combinine below. When we have found some
20031 /// chain of single-use x86 shuffle instructions and accumulated the combined
20032 /// shuffle mask represented by them, this will try to pattern match that mask
20033 /// into either a single instruction if there is a special purpose instruction
20034 /// for this operation, or into a PSHUFB instruction which is a fully general
20035 /// instruction but should only be used to replace chains over a certain depth.
20036 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20037 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20038 TargetLowering::DAGCombinerInfo &DCI,
20039 const X86Subtarget *Subtarget) {
20040 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20042 // Find the operand that enters the chain. Note that multiple uses are OK
20043 // here, we're not going to remove the operand we find.
20044 SDValue Input = Op.getOperand(0);
20045 while (Input.getOpcode() == ISD::BITCAST)
20046 Input = Input.getOperand(0);
20048 MVT VT = Input.getSimpleValueType();
20049 MVT RootVT = Root.getSimpleValueType();
20052 // Just remove no-op shuffle masks.
20053 if (Mask.size() == 1) {
20054 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20059 // Use the float domain if the operand type is a floating point type.
20060 bool FloatDomain = VT.isFloatingPoint();
20062 // For floating point shuffles, we don't have free copies in the shuffle
20063 // instructions or the ability to load as part of the instruction, so
20064 // canonicalize their shuffles to UNPCK or MOV variants.
20066 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20067 // vectors because it can have a load folded into it that UNPCK cannot. This
20068 // doesn't preclude something switching to the shorter encoding post-RA.
20070 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20071 bool Lo = Mask.equals(0, 0);
20074 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20075 // is no slower than UNPCKLPD but has the option to fold the input operand
20076 // into even an unaligned memory load.
20077 if (Lo && Subtarget->hasSSE3()) {
20078 Shuffle = X86ISD::MOVDDUP;
20079 ShuffleVT = MVT::v2f64;
20081 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20082 // than the UNPCK variants.
20083 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20084 ShuffleVT = MVT::v4f32;
20086 if (Depth == 1 && Root->getOpcode() == Shuffle)
20087 return false; // Nothing to do!
20088 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20089 DCI.AddToWorklist(Op.getNode());
20090 if (Shuffle == X86ISD::MOVDDUP)
20091 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20093 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20094 DCI.AddToWorklist(Op.getNode());
20095 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20099 if (Subtarget->hasSSE3() &&
20100 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20101 bool Lo = Mask.equals(0, 0, 2, 2);
20102 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20103 MVT ShuffleVT = MVT::v4f32;
20104 if (Depth == 1 && Root->getOpcode() == Shuffle)
20105 return false; // Nothing to do!
20106 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20107 DCI.AddToWorklist(Op.getNode());
20108 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20109 DCI.AddToWorklist(Op.getNode());
20110 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20114 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20115 bool Lo = Mask.equals(0, 0, 1, 1);
20116 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20117 MVT ShuffleVT = MVT::v4f32;
20118 if (Depth == 1 && Root->getOpcode() == Shuffle)
20119 return false; // Nothing to do!
20120 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20121 DCI.AddToWorklist(Op.getNode());
20122 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20123 DCI.AddToWorklist(Op.getNode());
20124 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20130 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20131 // variants as none of these have single-instruction variants that are
20132 // superior to the UNPCK formulation.
20133 if (!FloatDomain &&
20134 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20135 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20136 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20137 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20139 bool Lo = Mask[0] == 0;
20140 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20141 if (Depth == 1 && Root->getOpcode() == Shuffle)
20142 return false; // Nothing to do!
20144 switch (Mask.size()) {
20146 ShuffleVT = MVT::v8i16;
20149 ShuffleVT = MVT::v16i8;
20152 llvm_unreachable("Impossible mask size!");
20154 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20155 DCI.AddToWorklist(Op.getNode());
20156 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20157 DCI.AddToWorklist(Op.getNode());
20158 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20163 // Don't try to re-form single instruction chains under any circumstances now
20164 // that we've done encoding canonicalization for them.
20168 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20169 // can replace them with a single PSHUFB instruction profitably. Intel's
20170 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20171 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20172 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20173 SmallVector<SDValue, 16> PSHUFBMask;
20174 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20175 int Ratio = 16 / Mask.size();
20176 for (unsigned i = 0; i < 16; ++i) {
20177 if (Mask[i / Ratio] == SM_SentinelUndef) {
20178 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20181 int M = Mask[i / Ratio] != SM_SentinelZero
20182 ? Ratio * Mask[i / Ratio] + i % Ratio
20184 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20186 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20187 DCI.AddToWorklist(Op.getNode());
20188 SDValue PSHUFBMaskOp =
20189 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20190 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20191 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20192 DCI.AddToWorklist(Op.getNode());
20193 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20198 // Failed to find any combines.
20202 /// \brief Fully generic combining of x86 shuffle instructions.
20204 /// This should be the last combine run over the x86 shuffle instructions. Once
20205 /// they have been fully optimized, this will recursively consider all chains
20206 /// of single-use shuffle instructions, build a generic model of the cumulative
20207 /// shuffle operation, and check for simpler instructions which implement this
20208 /// operation. We use this primarily for two purposes:
20210 /// 1) Collapse generic shuffles to specialized single instructions when
20211 /// equivalent. In most cases, this is just an encoding size win, but
20212 /// sometimes we will collapse multiple generic shuffles into a single
20213 /// special-purpose shuffle.
20214 /// 2) Look for sequences of shuffle instructions with 3 or more total
20215 /// instructions, and replace them with the slightly more expensive SSSE3
20216 /// PSHUFB instruction if available. We do this as the last combining step
20217 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20218 /// a suitable short sequence of other instructions. The PHUFB will either
20219 /// use a register or have to read from memory and so is slightly (but only
20220 /// slightly) more expensive than the other shuffle instructions.
20222 /// Because this is inherently a quadratic operation (for each shuffle in
20223 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20224 /// This should never be an issue in practice as the shuffle lowering doesn't
20225 /// produce sequences of more than 8 instructions.
20227 /// FIXME: We will currently miss some cases where the redundant shuffling
20228 /// would simplify under the threshold for PSHUFB formation because of
20229 /// combine-ordering. To fix this, we should do the redundant instruction
20230 /// combining in this recursive walk.
20231 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20232 ArrayRef<int> RootMask,
20233 int Depth, bool HasPSHUFB,
20235 TargetLowering::DAGCombinerInfo &DCI,
20236 const X86Subtarget *Subtarget) {
20237 // Bound the depth of our recursive combine because this is ultimately
20238 // quadratic in nature.
20242 // Directly rip through bitcasts to find the underlying operand.
20243 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20244 Op = Op.getOperand(0);
20246 MVT VT = Op.getSimpleValueType();
20247 if (!VT.isVector())
20248 return false; // Bail if we hit a non-vector.
20249 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20250 // version should be added.
20251 if (VT.getSizeInBits() != 128)
20254 assert(Root.getSimpleValueType().isVector() &&
20255 "Shuffles operate on vector types!");
20256 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20257 "Can only combine shuffles of the same vector register size.");
20259 if (!isTargetShuffle(Op.getOpcode()))
20261 SmallVector<int, 16> OpMask;
20263 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20264 // We only can combine unary shuffles which we can decode the mask for.
20265 if (!HaveMask || !IsUnary)
20268 assert(VT.getVectorNumElements() == OpMask.size() &&
20269 "Different mask size from vector size!");
20270 assert(((RootMask.size() > OpMask.size() &&
20271 RootMask.size() % OpMask.size() == 0) ||
20272 (OpMask.size() > RootMask.size() &&
20273 OpMask.size() % RootMask.size() == 0) ||
20274 OpMask.size() == RootMask.size()) &&
20275 "The smaller number of elements must divide the larger.");
20276 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20277 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20278 assert(((RootRatio == 1 && OpRatio == 1) ||
20279 (RootRatio == 1) != (OpRatio == 1)) &&
20280 "Must not have a ratio for both incoming and op masks!");
20282 SmallVector<int, 16> Mask;
20283 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20285 // Merge this shuffle operation's mask into our accumulated mask. Note that
20286 // this shuffle's mask will be the first applied to the input, followed by the
20287 // root mask to get us all the way to the root value arrangement. The reason
20288 // for this order is that we are recursing up the operation chain.
20289 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20290 int RootIdx = i / RootRatio;
20291 if (RootMask[RootIdx] < 0) {
20292 // This is a zero or undef lane, we're done.
20293 Mask.push_back(RootMask[RootIdx]);
20297 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20298 int OpIdx = RootMaskedIdx / OpRatio;
20299 if (OpMask[OpIdx] < 0) {
20300 // The incoming lanes are zero or undef, it doesn't matter which ones we
20302 Mask.push_back(OpMask[OpIdx]);
20306 // Ok, we have non-zero lanes, map them through.
20307 Mask.push_back(OpMask[OpIdx] * OpRatio +
20308 RootMaskedIdx % OpRatio);
20311 // See if we can recurse into the operand to combine more things.
20312 switch (Op.getOpcode()) {
20313 case X86ISD::PSHUFB:
20315 case X86ISD::PSHUFD:
20316 case X86ISD::PSHUFHW:
20317 case X86ISD::PSHUFLW:
20318 if (Op.getOperand(0).hasOneUse() &&
20319 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20320 HasPSHUFB, DAG, DCI, Subtarget))
20324 case X86ISD::UNPCKL:
20325 case X86ISD::UNPCKH:
20326 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20327 // We can't check for single use, we have to check that this shuffle is the only user.
20328 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20329 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20330 HasPSHUFB, DAG, DCI, Subtarget))
20335 // Minor canonicalization of the accumulated shuffle mask to make it easier
20336 // to match below. All this does is detect masks with squential pairs of
20337 // elements, and shrink them to the half-width mask. It does this in a loop
20338 // so it will reduce the size of the mask to the minimal width mask which
20339 // performs an equivalent shuffle.
20340 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20341 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20342 Mask[i] = Mask[2 * i] / 2;
20343 Mask.resize(Mask.size() / 2);
20346 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20350 /// \brief Get the PSHUF-style mask from PSHUF node.
20352 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20353 /// PSHUF-style masks that can be reused with such instructions.
20354 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20355 SmallVector<int, 4> Mask;
20357 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20361 switch (N.getOpcode()) {
20362 case X86ISD::PSHUFD:
20364 case X86ISD::PSHUFLW:
20367 case X86ISD::PSHUFHW:
20368 Mask.erase(Mask.begin(), Mask.begin() + 4);
20369 for (int &M : Mask)
20373 llvm_unreachable("No valid shuffle instruction found!");
20377 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20379 /// We walk up the chain and look for a combinable shuffle, skipping over
20380 /// shuffles that we could hoist this shuffle's transformation past without
20381 /// altering anything.
20383 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20385 TargetLowering::DAGCombinerInfo &DCI) {
20386 assert(N.getOpcode() == X86ISD::PSHUFD &&
20387 "Called with something other than an x86 128-bit half shuffle!");
20390 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20391 // of the shuffles in the chain so that we can form a fresh chain to replace
20393 SmallVector<SDValue, 8> Chain;
20394 SDValue V = N.getOperand(0);
20395 for (; V.hasOneUse(); V = V.getOperand(0)) {
20396 switch (V.getOpcode()) {
20398 return SDValue(); // Nothing combined!
20401 // Skip bitcasts as we always know the type for the target specific
20405 case X86ISD::PSHUFD:
20406 // Found another dword shuffle.
20409 case X86ISD::PSHUFLW:
20410 // Check that the low words (being shuffled) are the identity in the
20411 // dword shuffle, and the high words are self-contained.
20412 if (Mask[0] != 0 || Mask[1] != 1 ||
20413 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20416 Chain.push_back(V);
20419 case X86ISD::PSHUFHW:
20420 // Check that the high words (being shuffled) are the identity in the
20421 // dword shuffle, and the low words are self-contained.
20422 if (Mask[2] != 2 || Mask[3] != 3 ||
20423 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20426 Chain.push_back(V);
20429 case X86ISD::UNPCKL:
20430 case X86ISD::UNPCKH:
20431 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20432 // shuffle into a preceding word shuffle.
20433 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20436 // Search for a half-shuffle which we can combine with.
20437 unsigned CombineOp =
20438 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20439 if (V.getOperand(0) != V.getOperand(1) ||
20440 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20442 Chain.push_back(V);
20443 V = V.getOperand(0);
20445 switch (V.getOpcode()) {
20447 return SDValue(); // Nothing to combine.
20449 case X86ISD::PSHUFLW:
20450 case X86ISD::PSHUFHW:
20451 if (V.getOpcode() == CombineOp)
20454 Chain.push_back(V);
20458 V = V.getOperand(0);
20462 } while (V.hasOneUse());
20465 // Break out of the loop if we break out of the switch.
20469 if (!V.hasOneUse())
20470 // We fell out of the loop without finding a viable combining instruction.
20473 // Merge this node's mask and our incoming mask.
20474 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20475 for (int &M : Mask)
20477 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20478 getV4X86ShuffleImm8ForMask(Mask, DAG));
20480 // Rebuild the chain around this new shuffle.
20481 while (!Chain.empty()) {
20482 SDValue W = Chain.pop_back_val();
20484 if (V.getValueType() != W.getOperand(0).getValueType())
20485 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20487 switch (W.getOpcode()) {
20489 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20491 case X86ISD::UNPCKL:
20492 case X86ISD::UNPCKH:
20493 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20496 case X86ISD::PSHUFD:
20497 case X86ISD::PSHUFLW:
20498 case X86ISD::PSHUFHW:
20499 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20503 if (V.getValueType() != N.getValueType())
20504 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20506 // Return the new chain to replace N.
20510 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20512 /// We walk up the chain, skipping shuffles of the other half and looking
20513 /// through shuffles which switch halves trying to find a shuffle of the same
20514 /// pair of dwords.
20515 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20517 TargetLowering::DAGCombinerInfo &DCI) {
20519 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20520 "Called with something other than an x86 128-bit half shuffle!");
20522 unsigned CombineOpcode = N.getOpcode();
20524 // Walk up a single-use chain looking for a combinable shuffle.
20525 SDValue V = N.getOperand(0);
20526 for (; V.hasOneUse(); V = V.getOperand(0)) {
20527 switch (V.getOpcode()) {
20529 return false; // Nothing combined!
20532 // Skip bitcasts as we always know the type for the target specific
20536 case X86ISD::PSHUFLW:
20537 case X86ISD::PSHUFHW:
20538 if (V.getOpcode() == CombineOpcode)
20541 // Other-half shuffles are no-ops.
20544 // Break out of the loop if we break out of the switch.
20548 if (!V.hasOneUse())
20549 // We fell out of the loop without finding a viable combining instruction.
20552 // Combine away the bottom node as its shuffle will be accumulated into
20553 // a preceding shuffle.
20554 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20556 // Record the old value.
20559 // Merge this node's mask and our incoming mask (adjusted to account for all
20560 // the pshufd instructions encountered).
20561 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20562 for (int &M : Mask)
20564 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20565 getV4X86ShuffleImm8ForMask(Mask, DAG));
20567 // Check that the shuffles didn't cancel each other out. If not, we need to
20568 // combine to the new one.
20570 // Replace the combinable shuffle with the combined one, updating all users
20571 // so that we re-evaluate the chain here.
20572 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20577 /// \brief Try to combine x86 target specific shuffles.
20578 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20579 TargetLowering::DAGCombinerInfo &DCI,
20580 const X86Subtarget *Subtarget) {
20582 MVT VT = N.getSimpleValueType();
20583 SmallVector<int, 4> Mask;
20585 switch (N.getOpcode()) {
20586 case X86ISD::PSHUFD:
20587 case X86ISD::PSHUFLW:
20588 case X86ISD::PSHUFHW:
20589 Mask = getPSHUFShuffleMask(N);
20590 assert(Mask.size() == 4);
20596 // Nuke no-op shuffles that show up after combining.
20597 if (isNoopShuffleMask(Mask))
20598 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20600 // Look for simplifications involving one or two shuffle instructions.
20601 SDValue V = N.getOperand(0);
20602 switch (N.getOpcode()) {
20605 case X86ISD::PSHUFLW:
20606 case X86ISD::PSHUFHW:
20607 assert(VT == MVT::v8i16);
20610 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20611 return SDValue(); // We combined away this shuffle, so we're done.
20613 // See if this reduces to a PSHUFD which is no more expensive and can
20614 // combine with more operations.
20615 if (canWidenShuffleElements(Mask)) {
20616 int DMask[] = {-1, -1, -1, -1};
20617 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20618 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20619 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20620 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20621 DCI.AddToWorklist(V.getNode());
20622 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20623 getV4X86ShuffleImm8ForMask(DMask, DAG));
20624 DCI.AddToWorklist(V.getNode());
20625 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20628 // Look for shuffle patterns which can be implemented as a single unpack.
20629 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20630 // only works when we have a PSHUFD followed by two half-shuffles.
20631 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20632 (V.getOpcode() == X86ISD::PSHUFLW ||
20633 V.getOpcode() == X86ISD::PSHUFHW) &&
20634 V.getOpcode() != N.getOpcode() &&
20636 SDValue D = V.getOperand(0);
20637 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20638 D = D.getOperand(0);
20639 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20640 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20641 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20642 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20643 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20645 for (int i = 0; i < 4; ++i) {
20646 WordMask[i + NOffset] = Mask[i] + NOffset;
20647 WordMask[i + VOffset] = VMask[i] + VOffset;
20649 // Map the word mask through the DWord mask.
20651 for (int i = 0; i < 8; ++i)
20652 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20653 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
20654 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
20655 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
20656 std::begin(UnpackLoMask)) ||
20657 std::equal(std::begin(MappedMask), std::end(MappedMask),
20658 std::begin(UnpackHiMask))) {
20659 // We can replace all three shuffles with an unpack.
20660 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
20661 DCI.AddToWorklist(V.getNode());
20662 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20664 DL, MVT::v8i16, V, V);
20671 case X86ISD::PSHUFD:
20672 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20681 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20683 /// We combine this directly on the abstract vector shuffle nodes so it is
20684 /// easier to generically match. We also insert dummy vector shuffle nodes for
20685 /// the operands which explicitly discard the lanes which are unused by this
20686 /// operation to try to flow through the rest of the combiner the fact that
20687 /// they're unused.
20688 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20690 EVT VT = N->getValueType(0);
20692 // We only handle target-independent shuffles.
20693 // FIXME: It would be easy and harmless to use the target shuffle mask
20694 // extraction tool to support more.
20695 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20698 auto *SVN = cast<ShuffleVectorSDNode>(N);
20699 ArrayRef<int> Mask = SVN->getMask();
20700 SDValue V1 = N->getOperand(0);
20701 SDValue V2 = N->getOperand(1);
20703 // We require the first shuffle operand to be the SUB node, and the second to
20704 // be the ADD node.
20705 // FIXME: We should support the commuted patterns.
20706 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20709 // If there are other uses of these operations we can't fold them.
20710 if (!V1->hasOneUse() || !V2->hasOneUse())
20713 // Ensure that both operations have the same operands. Note that we can
20714 // commute the FADD operands.
20715 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20716 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20717 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20720 // We're looking for blends between FADD and FSUB nodes. We insist on these
20721 // nodes being lined up in a specific expected pattern.
20722 if (!(isShuffleEquivalent(Mask, 0, 3) ||
20723 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
20724 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
20727 // Only specific types are legal at this point, assert so we notice if and
20728 // when these change.
20729 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20730 VT == MVT::v4f64) &&
20731 "Unknown vector type encountered!");
20733 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20736 /// PerformShuffleCombine - Performs several different shuffle combines.
20737 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20738 TargetLowering::DAGCombinerInfo &DCI,
20739 const X86Subtarget *Subtarget) {
20741 SDValue N0 = N->getOperand(0);
20742 SDValue N1 = N->getOperand(1);
20743 EVT VT = N->getValueType(0);
20745 // Don't create instructions with illegal types after legalize types has run.
20746 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20747 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20750 // If we have legalized the vector types, look for blends of FADD and FSUB
20751 // nodes that we can fuse into an ADDSUB node.
20752 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20753 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20756 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20757 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20758 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20759 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20761 // During Type Legalization, when promoting illegal vector types,
20762 // the backend might introduce new shuffle dag nodes and bitcasts.
20764 // This code performs the following transformation:
20765 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20766 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20768 // We do this only if both the bitcast and the BINOP dag nodes have
20769 // one use. Also, perform this transformation only if the new binary
20770 // operation is legal. This is to avoid introducing dag nodes that
20771 // potentially need to be further expanded (or custom lowered) into a
20772 // less optimal sequence of dag nodes.
20773 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20774 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20775 N0.getOpcode() == ISD::BITCAST) {
20776 SDValue BC0 = N0.getOperand(0);
20777 EVT SVT = BC0.getValueType();
20778 unsigned Opcode = BC0.getOpcode();
20779 unsigned NumElts = VT.getVectorNumElements();
20781 if (BC0.hasOneUse() && SVT.isVector() &&
20782 SVT.getVectorNumElements() * 2 == NumElts &&
20783 TLI.isOperationLegal(Opcode, VT)) {
20784 bool CanFold = false;
20796 unsigned SVTNumElts = SVT.getVectorNumElements();
20797 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20798 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20799 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20800 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20801 CanFold = SVOp->getMaskElt(i) < 0;
20804 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20805 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20806 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20807 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20812 // Only handle 128 wide vector from here on.
20813 if (!VT.is128BitVector())
20816 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20817 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20818 // consecutive, non-overlapping, and in the right order.
20819 SmallVector<SDValue, 16> Elts;
20820 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20821 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20823 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20827 if (isTargetShuffle(N->getOpcode())) {
20829 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20830 if (Shuffle.getNode())
20833 // Try recursively combining arbitrary sequences of x86 shuffle
20834 // instructions into higher-order shuffles. We do this after combining
20835 // specific PSHUF instruction sequences into their minimal form so that we
20836 // can evaluate how many specialized shuffle instructions are involved in
20837 // a particular chain.
20838 SmallVector<int, 1> NonceMask; // Just a placeholder.
20839 NonceMask.push_back(0);
20840 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20841 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20843 return SDValue(); // This routine will use CombineTo to replace N.
20849 /// PerformTruncateCombine - Converts truncate operation to
20850 /// a sequence of vector shuffle operations.
20851 /// It is possible when we truncate 256-bit vector to 128-bit vector
20852 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20853 TargetLowering::DAGCombinerInfo &DCI,
20854 const X86Subtarget *Subtarget) {
20858 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20859 /// specific shuffle of a load can be folded into a single element load.
20860 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20861 /// shuffles have been customed lowered so we need to handle those here.
20862 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20863 TargetLowering::DAGCombinerInfo &DCI) {
20864 if (DCI.isBeforeLegalizeOps())
20867 SDValue InVec = N->getOperand(0);
20868 SDValue EltNo = N->getOperand(1);
20870 if (!isa<ConstantSDNode>(EltNo))
20873 EVT VT = InVec.getValueType();
20875 if (InVec.getOpcode() == ISD::BITCAST) {
20876 // Don't duplicate a load with other uses.
20877 if (!InVec.hasOneUse())
20879 EVT BCVT = InVec.getOperand(0).getValueType();
20880 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
20882 InVec = InVec.getOperand(0);
20885 if (!isTargetShuffle(InVec.getOpcode()))
20888 // Don't duplicate a load with other uses.
20889 if (!InVec.hasOneUse())
20892 SmallVector<int, 16> ShuffleMask;
20894 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
20898 // Select the input vector, guarding against out of range extract vector.
20899 unsigned NumElems = VT.getVectorNumElements();
20900 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20901 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20902 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20903 : InVec.getOperand(1);
20905 // If inputs to shuffle are the same for both ops, then allow 2 uses
20906 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20908 if (LdNode.getOpcode() == ISD::BITCAST) {
20909 // Don't duplicate a load with other uses.
20910 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20913 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20914 LdNode = LdNode.getOperand(0);
20917 if (!ISD::isNormalLoad(LdNode.getNode()))
20920 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20922 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20925 EVT EltVT = N->getValueType(0);
20926 // If there's a bitcast before the shuffle, check if the load type and
20927 // alignment is valid.
20928 unsigned Align = LN0->getAlignment();
20929 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20930 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20931 EltVT.getTypeForEVT(*DAG.getContext()));
20933 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20936 // All checks match so transform back to vector_shuffle so that DAG combiner
20937 // can finish the job
20940 // Create shuffle node taking into account the case that its a unary shuffle
20941 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20942 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20943 InVec.getOperand(0), Shuffle,
20945 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20946 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20950 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20951 /// generation and convert it from being a bunch of shuffles and extracts
20952 /// to a simple store and scalar loads to extract the elements.
20953 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20954 TargetLowering::DAGCombinerInfo &DCI) {
20955 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20956 if (NewOp.getNode())
20959 SDValue InputVector = N->getOperand(0);
20961 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20962 // from mmx to v2i32 has a single usage.
20963 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20964 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20965 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20966 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20967 N->getValueType(0),
20968 InputVector.getNode()->getOperand(0));
20970 // Only operate on vectors of 4 elements, where the alternative shuffling
20971 // gets to be more expensive.
20972 if (InputVector.getValueType() != MVT::v4i32)
20975 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20976 // single use which is a sign-extend or zero-extend, and all elements are
20978 SmallVector<SDNode *, 4> Uses;
20979 unsigned ExtractedElements = 0;
20980 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20981 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20982 if (UI.getUse().getResNo() != InputVector.getResNo())
20985 SDNode *Extract = *UI;
20986 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20989 if (Extract->getValueType(0) != MVT::i32)
20991 if (!Extract->hasOneUse())
20993 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20994 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20996 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20999 // Record which element was extracted.
21000 ExtractedElements |=
21001 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21003 Uses.push_back(Extract);
21006 // If not all the elements were used, this may not be worthwhile.
21007 if (ExtractedElements != 15)
21010 // Ok, we've now decided to do the transformation.
21011 SDLoc dl(InputVector);
21013 // Store the value to a temporary stack slot.
21014 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21015 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21016 MachinePointerInfo(), false, false, 0);
21018 // Replace each use (extract) with a load of the appropriate element.
21019 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21020 UE = Uses.end(); UI != UE; ++UI) {
21021 SDNode *Extract = *UI;
21023 // cOMpute the element's address.
21024 SDValue Idx = Extract->getOperand(1);
21026 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21027 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21028 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21029 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21031 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21032 StackPtr, OffsetVal);
21034 // Load the scalar.
21035 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21036 ScalarAddr, MachinePointerInfo(),
21037 false, false, false, 0);
21039 // Replace the exact with the load.
21040 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21043 // The replacement was made in place; don't return anything.
21047 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21048 static std::pair<unsigned, bool>
21049 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21050 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21051 if (!VT.isVector())
21052 return std::make_pair(0, false);
21054 bool NeedSplit = false;
21055 switch (VT.getSimpleVT().SimpleTy) {
21056 default: return std::make_pair(0, false);
21060 if (!Subtarget->hasAVX2())
21062 if (!Subtarget->hasAVX())
21063 return std::make_pair(0, false);
21068 if (!Subtarget->hasSSE2())
21069 return std::make_pair(0, false);
21072 // SSE2 has only a small subset of the operations.
21073 bool hasUnsigned = Subtarget->hasSSE41() ||
21074 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21075 bool hasSigned = Subtarget->hasSSE41() ||
21076 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21078 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21081 // Check for x CC y ? x : y.
21082 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21083 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21088 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21091 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21094 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21097 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21099 // Check for x CC y ? y : x -- a min/max with reversed arms.
21100 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21101 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21106 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21109 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21112 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21115 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21119 return std::make_pair(Opc, NeedSplit);
21123 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21124 const X86Subtarget *Subtarget) {
21126 SDValue Cond = N->getOperand(0);
21127 SDValue LHS = N->getOperand(1);
21128 SDValue RHS = N->getOperand(2);
21130 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21131 SDValue CondSrc = Cond->getOperand(0);
21132 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21133 Cond = CondSrc->getOperand(0);
21136 MVT VT = N->getSimpleValueType(0);
21137 MVT EltVT = VT.getVectorElementType();
21138 unsigned NumElems = VT.getVectorNumElements();
21139 // There is no blend with immediate in AVX-512.
21140 if (VT.is512BitVector())
21143 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21145 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21148 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21151 // A vselect where all conditions and data are constants can be optimized into
21152 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21153 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21154 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21157 unsigned MaskValue = 0;
21158 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21161 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21162 for (unsigned i = 0; i < NumElems; ++i) {
21163 // Be sure we emit undef where we can.
21164 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21165 ShuffleMask[i] = -1;
21167 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21170 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21173 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21175 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21176 TargetLowering::DAGCombinerInfo &DCI,
21177 const X86Subtarget *Subtarget) {
21179 SDValue Cond = N->getOperand(0);
21180 // Get the LHS/RHS of the select.
21181 SDValue LHS = N->getOperand(1);
21182 SDValue RHS = N->getOperand(2);
21183 EVT VT = LHS.getValueType();
21184 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21186 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21187 // instructions match the semantics of the common C idiom x<y?x:y but not
21188 // x<=y?x:y, because of how they handle negative zero (which can be
21189 // ignored in unsafe-math mode).
21190 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21191 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21192 (Subtarget->hasSSE2() ||
21193 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21194 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21196 unsigned Opcode = 0;
21197 // Check for x CC y ? x : y.
21198 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21199 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21203 // Converting this to a min would handle NaNs incorrectly, and swapping
21204 // the operands would cause it to handle comparisons between positive
21205 // and negative zero incorrectly.
21206 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21207 if (!DAG.getTarget().Options.UnsafeFPMath &&
21208 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21210 std::swap(LHS, RHS);
21212 Opcode = X86ISD::FMIN;
21215 // Converting this to a min would handle comparisons between positive
21216 // and negative zero incorrectly.
21217 if (!DAG.getTarget().Options.UnsafeFPMath &&
21218 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21220 Opcode = X86ISD::FMIN;
21223 // Converting this to a min would handle both negative zeros and NaNs
21224 // incorrectly, but we can swap the operands to fix both.
21225 std::swap(LHS, RHS);
21229 Opcode = X86ISD::FMIN;
21233 // Converting this to a max would handle comparisons between positive
21234 // and negative zero incorrectly.
21235 if (!DAG.getTarget().Options.UnsafeFPMath &&
21236 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21238 Opcode = X86ISD::FMAX;
21241 // Converting this to a max would handle NaNs incorrectly, and swapping
21242 // the operands would cause it to handle comparisons between positive
21243 // and negative zero incorrectly.
21244 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21245 if (!DAG.getTarget().Options.UnsafeFPMath &&
21246 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21248 std::swap(LHS, RHS);
21250 Opcode = X86ISD::FMAX;
21253 // Converting this to a max would handle both negative zeros and NaNs
21254 // incorrectly, but we can swap the operands to fix both.
21255 std::swap(LHS, RHS);
21259 Opcode = X86ISD::FMAX;
21262 // Check for x CC y ? y : x -- a min/max with reversed arms.
21263 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21264 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21268 // Converting this to a min would handle comparisons between positive
21269 // and negative zero incorrectly, and swapping the operands would
21270 // cause it to handle NaNs incorrectly.
21271 if (!DAG.getTarget().Options.UnsafeFPMath &&
21272 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21273 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21275 std::swap(LHS, RHS);
21277 Opcode = X86ISD::FMIN;
21280 // Converting this to a min would handle NaNs incorrectly.
21281 if (!DAG.getTarget().Options.UnsafeFPMath &&
21282 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21284 Opcode = X86ISD::FMIN;
21287 // Converting this to a min would handle both negative zeros and NaNs
21288 // incorrectly, but we can swap the operands to fix both.
21289 std::swap(LHS, RHS);
21293 Opcode = X86ISD::FMIN;
21297 // Converting this to a max would handle NaNs incorrectly.
21298 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21300 Opcode = X86ISD::FMAX;
21303 // Converting this to a max would handle comparisons between positive
21304 // and negative zero incorrectly, and swapping the operands would
21305 // cause it to handle NaNs incorrectly.
21306 if (!DAG.getTarget().Options.UnsafeFPMath &&
21307 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21308 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21310 std::swap(LHS, RHS);
21312 Opcode = X86ISD::FMAX;
21315 // Converting this to a max would handle both negative zeros and NaNs
21316 // incorrectly, but we can swap the operands to fix both.
21317 std::swap(LHS, RHS);
21321 Opcode = X86ISD::FMAX;
21327 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21330 EVT CondVT = Cond.getValueType();
21331 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21332 CondVT.getVectorElementType() == MVT::i1) {
21333 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21334 // lowering on KNL. In this case we convert it to
21335 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21336 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21337 // Since SKX these selects have a proper lowering.
21338 EVT OpVT = LHS.getValueType();
21339 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21340 (OpVT.getVectorElementType() == MVT::i8 ||
21341 OpVT.getVectorElementType() == MVT::i16) &&
21342 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21343 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21344 DCI.AddToWorklist(Cond.getNode());
21345 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21348 // If this is a select between two integer constants, try to do some
21350 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21351 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21352 // Don't do this for crazy integer types.
21353 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21354 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21355 // so that TrueC (the true value) is larger than FalseC.
21356 bool NeedsCondInvert = false;
21358 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21359 // Efficiently invertible.
21360 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21361 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21362 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21363 NeedsCondInvert = true;
21364 std::swap(TrueC, FalseC);
21367 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21368 if (FalseC->getAPIntValue() == 0 &&
21369 TrueC->getAPIntValue().isPowerOf2()) {
21370 if (NeedsCondInvert) // Invert the condition if needed.
21371 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21372 DAG.getConstant(1, Cond.getValueType()));
21374 // Zero extend the condition if needed.
21375 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21377 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21378 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21379 DAG.getConstant(ShAmt, MVT::i8));
21382 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21383 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21384 if (NeedsCondInvert) // Invert the condition if needed.
21385 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21386 DAG.getConstant(1, Cond.getValueType()));
21388 // Zero extend the condition if needed.
21389 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21390 FalseC->getValueType(0), Cond);
21391 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21392 SDValue(FalseC, 0));
21395 // Optimize cases that will turn into an LEA instruction. This requires
21396 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21397 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21398 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21399 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21401 bool isFastMultiplier = false;
21403 switch ((unsigned char)Diff) {
21405 case 1: // result = add base, cond
21406 case 2: // result = lea base( , cond*2)
21407 case 3: // result = lea base(cond, cond*2)
21408 case 4: // result = lea base( , cond*4)
21409 case 5: // result = lea base(cond, cond*4)
21410 case 8: // result = lea base( , cond*8)
21411 case 9: // result = lea base(cond, cond*8)
21412 isFastMultiplier = true;
21417 if (isFastMultiplier) {
21418 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21419 if (NeedsCondInvert) // Invert the condition if needed.
21420 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21421 DAG.getConstant(1, Cond.getValueType()));
21423 // Zero extend the condition if needed.
21424 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21426 // Scale the condition by the difference.
21428 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21429 DAG.getConstant(Diff, Cond.getValueType()));
21431 // Add the base if non-zero.
21432 if (FalseC->getAPIntValue() != 0)
21433 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21434 SDValue(FalseC, 0));
21441 // Canonicalize max and min:
21442 // (x > y) ? x : y -> (x >= y) ? x : y
21443 // (x < y) ? x : y -> (x <= y) ? x : y
21444 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21445 // the need for an extra compare
21446 // against zero. e.g.
21447 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21449 // testl %edi, %edi
21451 // cmovgl %edi, %eax
21455 // cmovsl %eax, %edi
21456 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21457 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21458 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21459 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21464 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21465 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21466 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21467 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21472 // Early exit check
21473 if (!TLI.isTypeLegal(VT))
21476 // Match VSELECTs into subs with unsigned saturation.
21477 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21478 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21479 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21480 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21481 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21483 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21484 // left side invert the predicate to simplify logic below.
21486 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21488 CC = ISD::getSetCCInverse(CC, true);
21489 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21493 if (Other.getNode() && Other->getNumOperands() == 2 &&
21494 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21495 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21496 SDValue CondRHS = Cond->getOperand(1);
21498 // Look for a general sub with unsigned saturation first.
21499 // x >= y ? x-y : 0 --> subus x, y
21500 // x > y ? x-y : 0 --> subus x, y
21501 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21502 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21503 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21505 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21506 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21507 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21508 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21509 // If the RHS is a constant we have to reverse the const
21510 // canonicalization.
21511 // x > C-1 ? x+-C : 0 --> subus x, C
21512 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21513 CondRHSConst->getAPIntValue() ==
21514 (-OpRHSConst->getAPIntValue() - 1))
21515 return DAG.getNode(
21516 X86ISD::SUBUS, DL, VT, OpLHS,
21517 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21519 // Another special case: If C was a sign bit, the sub has been
21520 // canonicalized into a xor.
21521 // FIXME: Would it be better to use computeKnownBits to determine
21522 // whether it's safe to decanonicalize the xor?
21523 // x s< 0 ? x^C : 0 --> subus x, C
21524 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21525 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21526 OpRHSConst->getAPIntValue().isSignBit())
21527 // Note that we have to rebuild the RHS constant here to ensure we
21528 // don't rely on particular values of undef lanes.
21529 return DAG.getNode(
21530 X86ISD::SUBUS, DL, VT, OpLHS,
21531 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21536 // Try to match a min/max vector operation.
21537 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21538 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21539 unsigned Opc = ret.first;
21540 bool NeedSplit = ret.second;
21542 if (Opc && NeedSplit) {
21543 unsigned NumElems = VT.getVectorNumElements();
21544 // Extract the LHS vectors
21545 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21546 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21548 // Extract the RHS vectors
21549 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21550 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21552 // Create min/max for each subvector
21553 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21554 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21556 // Merge the result
21557 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21559 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21562 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21563 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21564 // Check if SETCC has already been promoted
21565 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21566 // Check that condition value type matches vselect operand type
21569 assert(Cond.getValueType().isVector() &&
21570 "vector select expects a vector selector!");
21572 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21573 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21575 if (!TValIsAllOnes && !FValIsAllZeros) {
21576 // Try invert the condition if true value is not all 1s and false value
21578 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21579 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21581 if (TValIsAllZeros || FValIsAllOnes) {
21582 SDValue CC = Cond.getOperand(2);
21583 ISD::CondCode NewCC =
21584 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21585 Cond.getOperand(0).getValueType().isInteger());
21586 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21587 std::swap(LHS, RHS);
21588 TValIsAllOnes = FValIsAllOnes;
21589 FValIsAllZeros = TValIsAllZeros;
21593 if (TValIsAllOnes || FValIsAllZeros) {
21596 if (TValIsAllOnes && FValIsAllZeros)
21598 else if (TValIsAllOnes)
21599 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21600 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21601 else if (FValIsAllZeros)
21602 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21603 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21605 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21609 // Try to fold this VSELECT into a MOVSS/MOVSD
21610 if (N->getOpcode() == ISD::VSELECT &&
21611 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21612 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21613 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21614 bool CanFold = false;
21615 unsigned NumElems = Cond.getNumOperands();
21619 if (isZero(Cond.getOperand(0))) {
21622 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21623 // fold (vselect <0,-1> -> (movsd A, B)
21624 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21625 CanFold = isAllOnes(Cond.getOperand(i));
21626 } else if (isAllOnes(Cond.getOperand(0))) {
21630 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21631 // fold (vselect <-1,0> -> (movsd B, A)
21632 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21633 CanFold = isZero(Cond.getOperand(i));
21637 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21638 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21639 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21642 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21643 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21644 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
21645 // (v2i64 (bitcast B)))))
21647 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
21648 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
21649 // (v2f64 (bitcast B)))))
21651 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
21652 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
21653 // (v2i64 (bitcast A)))))
21655 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
21656 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
21657 // (v2f64 (bitcast A)))))
21659 CanFold = (isZero(Cond.getOperand(0)) &&
21660 isZero(Cond.getOperand(1)) &&
21661 isAllOnes(Cond.getOperand(2)) &&
21662 isAllOnes(Cond.getOperand(3)));
21664 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
21665 isAllOnes(Cond.getOperand(1)) &&
21666 isZero(Cond.getOperand(2)) &&
21667 isZero(Cond.getOperand(3))) {
21669 std::swap(LHS, RHS);
21673 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
21674 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
21675 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
21676 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
21678 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
21684 // If we know that this node is legal then we know that it is going to be
21685 // matched by one of the SSE/AVX BLEND instructions. These instructions only
21686 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
21687 // to simplify previous instructions.
21688 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21689 !DCI.isBeforeLegalize() &&
21690 // We explicitly check against v8i16 and v16i16 because, although
21691 // they're marked as Custom, they might only be legal when Cond is a
21692 // build_vector of constants. This will be taken care in a later
21694 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
21695 VT != MVT::v8i16)) {
21696 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21698 // Don't optimize vector selects that map to mask-registers.
21702 // Check all uses of that condition operand to check whether it will be
21703 // consumed by non-BLEND instructions, which may depend on all bits are set
21705 for (SDNode::use_iterator I = Cond->use_begin(),
21706 E = Cond->use_end(); I != E; ++I)
21707 if (I->getOpcode() != ISD::VSELECT)
21708 // TODO: Add other opcodes eventually lowered into BLEND.
21711 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21712 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21714 APInt KnownZero, KnownOne;
21715 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21716 DCI.isBeforeLegalizeOps());
21717 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21718 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
21719 DCI.CommitTargetLoweringOpt(TLO);
21722 // We should generate an X86ISD::BLENDI from a vselect if its argument
21723 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21724 // constants. This specific pattern gets generated when we split a
21725 // selector for a 512 bit vector in a machine without AVX512 (but with
21726 // 256-bit vectors), during legalization:
21728 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21730 // Iff we find this pattern and the build_vectors are built from
21731 // constants, we translate the vselect into a shuffle_vector that we
21732 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21733 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
21734 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21735 if (Shuffle.getNode())
21742 // Check whether a boolean test is testing a boolean value generated by
21743 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21746 // Simplify the following patterns:
21747 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21748 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21749 // to (Op EFLAGS Cond)
21751 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21752 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21753 // to (Op EFLAGS !Cond)
21755 // where Op could be BRCOND or CMOV.
21757 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21758 // Quit if not CMP and SUB with its value result used.
21759 if (Cmp.getOpcode() != X86ISD::CMP &&
21760 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21763 // Quit if not used as a boolean value.
21764 if (CC != X86::COND_E && CC != X86::COND_NE)
21767 // Check CMP operands. One of them should be 0 or 1 and the other should be
21768 // an SetCC or extended from it.
21769 SDValue Op1 = Cmp.getOperand(0);
21770 SDValue Op2 = Cmp.getOperand(1);
21773 const ConstantSDNode* C = nullptr;
21774 bool needOppositeCond = (CC == X86::COND_E);
21775 bool checkAgainstTrue = false; // Is it a comparison against 1?
21777 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21779 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21781 else // Quit if all operands are not constants.
21784 if (C->getZExtValue() == 1) {
21785 needOppositeCond = !needOppositeCond;
21786 checkAgainstTrue = true;
21787 } else if (C->getZExtValue() != 0)
21788 // Quit if the constant is neither 0 or 1.
21791 bool truncatedToBoolWithAnd = false;
21792 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21793 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21794 SetCC.getOpcode() == ISD::TRUNCATE ||
21795 SetCC.getOpcode() == ISD::AND) {
21796 if (SetCC.getOpcode() == ISD::AND) {
21798 ConstantSDNode *CS;
21799 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21800 CS->getZExtValue() == 1)
21802 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21803 CS->getZExtValue() == 1)
21807 SetCC = SetCC.getOperand(OpIdx);
21808 truncatedToBoolWithAnd = true;
21810 SetCC = SetCC.getOperand(0);
21813 switch (SetCC.getOpcode()) {
21814 case X86ISD::SETCC_CARRY:
21815 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21816 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21817 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21818 // truncated to i1 using 'and'.
21819 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21821 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21822 "Invalid use of SETCC_CARRY!");
21824 case X86ISD::SETCC:
21825 // Set the condition code or opposite one if necessary.
21826 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21827 if (needOppositeCond)
21828 CC = X86::GetOppositeBranchCondition(CC);
21829 return SetCC.getOperand(1);
21830 case X86ISD::CMOV: {
21831 // Check whether false/true value has canonical one, i.e. 0 or 1.
21832 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21833 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21834 // Quit if true value is not a constant.
21837 // Quit if false value is not a constant.
21839 SDValue Op = SetCC.getOperand(0);
21840 // Skip 'zext' or 'trunc' node.
21841 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21842 Op.getOpcode() == ISD::TRUNCATE)
21843 Op = Op.getOperand(0);
21844 // A special case for rdrand/rdseed, where 0 is set if false cond is
21846 if ((Op.getOpcode() != X86ISD::RDRAND &&
21847 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21850 // Quit if false value is not the constant 0 or 1.
21851 bool FValIsFalse = true;
21852 if (FVal && FVal->getZExtValue() != 0) {
21853 if (FVal->getZExtValue() != 1)
21855 // If FVal is 1, opposite cond is needed.
21856 needOppositeCond = !needOppositeCond;
21857 FValIsFalse = false;
21859 // Quit if TVal is not the constant opposite of FVal.
21860 if (FValIsFalse && TVal->getZExtValue() != 1)
21862 if (!FValIsFalse && TVal->getZExtValue() != 0)
21864 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21865 if (needOppositeCond)
21866 CC = X86::GetOppositeBranchCondition(CC);
21867 return SetCC.getOperand(3);
21874 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21875 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21876 TargetLowering::DAGCombinerInfo &DCI,
21877 const X86Subtarget *Subtarget) {
21880 // If the flag operand isn't dead, don't touch this CMOV.
21881 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21884 SDValue FalseOp = N->getOperand(0);
21885 SDValue TrueOp = N->getOperand(1);
21886 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21887 SDValue Cond = N->getOperand(3);
21889 if (CC == X86::COND_E || CC == X86::COND_NE) {
21890 switch (Cond.getOpcode()) {
21894 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21895 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21896 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21902 Flags = checkBoolTestSetCCCombine(Cond, CC);
21903 if (Flags.getNode() &&
21904 // Extra check as FCMOV only supports a subset of X86 cond.
21905 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21906 SDValue Ops[] = { FalseOp, TrueOp,
21907 DAG.getConstant(CC, MVT::i8), Flags };
21908 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21911 // If this is a select between two integer constants, try to do some
21912 // optimizations. Note that the operands are ordered the opposite of SELECT
21914 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21915 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21916 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21917 // larger than FalseC (the false value).
21918 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21919 CC = X86::GetOppositeBranchCondition(CC);
21920 std::swap(TrueC, FalseC);
21921 std::swap(TrueOp, FalseOp);
21924 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21925 // This is efficient for any integer data type (including i8/i16) and
21927 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21928 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21929 DAG.getConstant(CC, MVT::i8), Cond);
21931 // Zero extend the condition if needed.
21932 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21934 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21935 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21936 DAG.getConstant(ShAmt, MVT::i8));
21937 if (N->getNumValues() == 2) // Dead flag value?
21938 return DCI.CombineTo(N, Cond, SDValue());
21942 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21943 // for any integer data type, including i8/i16.
21944 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21945 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21946 DAG.getConstant(CC, MVT::i8), Cond);
21948 // Zero extend the condition if needed.
21949 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21950 FalseC->getValueType(0), Cond);
21951 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21952 SDValue(FalseC, 0));
21954 if (N->getNumValues() == 2) // Dead flag value?
21955 return DCI.CombineTo(N, Cond, SDValue());
21959 // Optimize cases that will turn into an LEA instruction. This requires
21960 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21961 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21962 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21963 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21965 bool isFastMultiplier = false;
21967 switch ((unsigned char)Diff) {
21969 case 1: // result = add base, cond
21970 case 2: // result = lea base( , cond*2)
21971 case 3: // result = lea base(cond, cond*2)
21972 case 4: // result = lea base( , cond*4)
21973 case 5: // result = lea base(cond, cond*4)
21974 case 8: // result = lea base( , cond*8)
21975 case 9: // result = lea base(cond, cond*8)
21976 isFastMultiplier = true;
21981 if (isFastMultiplier) {
21982 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21983 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21984 DAG.getConstant(CC, MVT::i8), Cond);
21985 // Zero extend the condition if needed.
21986 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21988 // Scale the condition by the difference.
21990 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21991 DAG.getConstant(Diff, Cond.getValueType()));
21993 // Add the base if non-zero.
21994 if (FalseC->getAPIntValue() != 0)
21995 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21996 SDValue(FalseC, 0));
21997 if (N->getNumValues() == 2) // Dead flag value?
21998 return DCI.CombineTo(N, Cond, SDValue());
22005 // Handle these cases:
22006 // (select (x != c), e, c) -> select (x != c), e, x),
22007 // (select (x == c), c, e) -> select (x == c), x, e)
22008 // where the c is an integer constant, and the "select" is the combination
22009 // of CMOV and CMP.
22011 // The rationale for this change is that the conditional-move from a constant
22012 // needs two instructions, however, conditional-move from a register needs
22013 // only one instruction.
22015 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22016 // some instruction-combining opportunities. This opt needs to be
22017 // postponed as late as possible.
22019 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22020 // the DCI.xxxx conditions are provided to postpone the optimization as
22021 // late as possible.
22023 ConstantSDNode *CmpAgainst = nullptr;
22024 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22025 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22026 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22028 if (CC == X86::COND_NE &&
22029 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22030 CC = X86::GetOppositeBranchCondition(CC);
22031 std::swap(TrueOp, FalseOp);
22034 if (CC == X86::COND_E &&
22035 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22036 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22037 DAG.getConstant(CC, MVT::i8), Cond };
22038 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22046 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22047 const X86Subtarget *Subtarget) {
22048 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22050 default: return SDValue();
22051 // SSE/AVX/AVX2 blend intrinsics.
22052 case Intrinsic::x86_avx2_pblendvb:
22053 case Intrinsic::x86_avx2_pblendw:
22054 case Intrinsic::x86_avx2_pblendd_128:
22055 case Intrinsic::x86_avx2_pblendd_256:
22056 // Don't try to simplify this intrinsic if we don't have AVX2.
22057 if (!Subtarget->hasAVX2())
22060 case Intrinsic::x86_avx_blend_pd_256:
22061 case Intrinsic::x86_avx_blend_ps_256:
22062 case Intrinsic::x86_avx_blendv_pd_256:
22063 case Intrinsic::x86_avx_blendv_ps_256:
22064 // Don't try to simplify this intrinsic if we don't have AVX.
22065 if (!Subtarget->hasAVX())
22068 case Intrinsic::x86_sse41_pblendw:
22069 case Intrinsic::x86_sse41_blendpd:
22070 case Intrinsic::x86_sse41_blendps:
22071 case Intrinsic::x86_sse41_blendvps:
22072 case Intrinsic::x86_sse41_blendvpd:
22073 case Intrinsic::x86_sse41_pblendvb: {
22074 SDValue Op0 = N->getOperand(1);
22075 SDValue Op1 = N->getOperand(2);
22076 SDValue Mask = N->getOperand(3);
22078 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22079 if (!Subtarget->hasSSE41())
22082 // fold (blend A, A, Mask) -> A
22085 // fold (blend A, B, allZeros) -> A
22086 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22088 // fold (blend A, B, allOnes) -> B
22089 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22092 // Simplify the case where the mask is a constant i32 value.
22093 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22094 if (C->isNullValue())
22096 if (C->isAllOnesValue())
22103 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22104 case Intrinsic::x86_sse2_psrai_w:
22105 case Intrinsic::x86_sse2_psrai_d:
22106 case Intrinsic::x86_avx2_psrai_w:
22107 case Intrinsic::x86_avx2_psrai_d:
22108 case Intrinsic::x86_sse2_psra_w:
22109 case Intrinsic::x86_sse2_psra_d:
22110 case Intrinsic::x86_avx2_psra_w:
22111 case Intrinsic::x86_avx2_psra_d: {
22112 SDValue Op0 = N->getOperand(1);
22113 SDValue Op1 = N->getOperand(2);
22114 EVT VT = Op0.getValueType();
22115 assert(VT.isVector() && "Expected a vector type!");
22117 if (isa<BuildVectorSDNode>(Op1))
22118 Op1 = Op1.getOperand(0);
22120 if (!isa<ConstantSDNode>(Op1))
22123 EVT SVT = VT.getVectorElementType();
22124 unsigned SVTBits = SVT.getSizeInBits();
22126 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22127 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22128 uint64_t ShAmt = C.getZExtValue();
22130 // Don't try to convert this shift into a ISD::SRA if the shift
22131 // count is bigger than or equal to the element size.
22132 if (ShAmt >= SVTBits)
22135 // Trivial case: if the shift count is zero, then fold this
22136 // into the first operand.
22140 // Replace this packed shift intrinsic with a target independent
22142 SDValue Splat = DAG.getConstant(C, VT);
22143 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22148 /// PerformMulCombine - Optimize a single multiply with constant into two
22149 /// in order to implement it with two cheaper instructions, e.g.
22150 /// LEA + SHL, LEA + LEA.
22151 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22152 TargetLowering::DAGCombinerInfo &DCI) {
22153 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22156 EVT VT = N->getValueType(0);
22157 if (VT != MVT::i64)
22160 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22163 uint64_t MulAmt = C->getZExtValue();
22164 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22167 uint64_t MulAmt1 = 0;
22168 uint64_t MulAmt2 = 0;
22169 if ((MulAmt % 9) == 0) {
22171 MulAmt2 = MulAmt / 9;
22172 } else if ((MulAmt % 5) == 0) {
22174 MulAmt2 = MulAmt / 5;
22175 } else if ((MulAmt % 3) == 0) {
22177 MulAmt2 = MulAmt / 3;
22180 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22183 if (isPowerOf2_64(MulAmt2) &&
22184 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22185 // If second multiplifer is pow2, issue it first. We want the multiply by
22186 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22188 std::swap(MulAmt1, MulAmt2);
22191 if (isPowerOf2_64(MulAmt1))
22192 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22193 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22195 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22196 DAG.getConstant(MulAmt1, VT));
22198 if (isPowerOf2_64(MulAmt2))
22199 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22200 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22202 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22203 DAG.getConstant(MulAmt2, VT));
22205 // Do not add new nodes to DAG combiner worklist.
22206 DCI.CombineTo(N, NewMul, false);
22211 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22212 SDValue N0 = N->getOperand(0);
22213 SDValue N1 = N->getOperand(1);
22214 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22215 EVT VT = N0.getValueType();
22217 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22218 // since the result of setcc_c is all zero's or all ones.
22219 if (VT.isInteger() && !VT.isVector() &&
22220 N1C && N0.getOpcode() == ISD::AND &&
22221 N0.getOperand(1).getOpcode() == ISD::Constant) {
22222 SDValue N00 = N0.getOperand(0);
22223 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22224 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22225 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22226 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22227 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22228 APInt ShAmt = N1C->getAPIntValue();
22229 Mask = Mask.shl(ShAmt);
22231 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22232 N00, DAG.getConstant(Mask, VT));
22236 // Hardware support for vector shifts is sparse which makes us scalarize the
22237 // vector operations in many cases. Also, on sandybridge ADD is faster than
22239 // (shl V, 1) -> add V,V
22240 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22241 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22242 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22243 // We shift all of the values by one. In many cases we do not have
22244 // hardware support for this operation. This is better expressed as an ADD
22246 if (N1SplatC->getZExtValue() == 1)
22247 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22253 /// \brief Returns a vector of 0s if the node in input is a vector logical
22254 /// shift by a constant amount which is known to be bigger than or equal
22255 /// to the vector element size in bits.
22256 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22257 const X86Subtarget *Subtarget) {
22258 EVT VT = N->getValueType(0);
22260 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22261 (!Subtarget->hasInt256() ||
22262 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22265 SDValue Amt = N->getOperand(1);
22267 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22268 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22269 APInt ShiftAmt = AmtSplat->getAPIntValue();
22270 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22272 // SSE2/AVX2 logical shifts always return a vector of 0s
22273 // if the shift amount is bigger than or equal to
22274 // the element size. The constant shift amount will be
22275 // encoded as a 8-bit immediate.
22276 if (ShiftAmt.trunc(8).uge(MaxAmount))
22277 return getZeroVector(VT, Subtarget, DAG, DL);
22283 /// PerformShiftCombine - Combine shifts.
22284 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22285 TargetLowering::DAGCombinerInfo &DCI,
22286 const X86Subtarget *Subtarget) {
22287 if (N->getOpcode() == ISD::SHL) {
22288 SDValue V = PerformSHLCombine(N, DAG);
22289 if (V.getNode()) return V;
22292 if (N->getOpcode() != ISD::SRA) {
22293 // Try to fold this logical shift into a zero vector.
22294 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22295 if (V.getNode()) return V;
22301 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22302 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22303 // and friends. Likewise for OR -> CMPNEQSS.
22304 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22305 TargetLowering::DAGCombinerInfo &DCI,
22306 const X86Subtarget *Subtarget) {
22309 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22310 // we're requiring SSE2 for both.
22311 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22312 SDValue N0 = N->getOperand(0);
22313 SDValue N1 = N->getOperand(1);
22314 SDValue CMP0 = N0->getOperand(1);
22315 SDValue CMP1 = N1->getOperand(1);
22318 // The SETCCs should both refer to the same CMP.
22319 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22322 SDValue CMP00 = CMP0->getOperand(0);
22323 SDValue CMP01 = CMP0->getOperand(1);
22324 EVT VT = CMP00.getValueType();
22326 if (VT == MVT::f32 || VT == MVT::f64) {
22327 bool ExpectingFlags = false;
22328 // Check for any users that want flags:
22329 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22330 !ExpectingFlags && UI != UE; ++UI)
22331 switch (UI->getOpcode()) {
22336 ExpectingFlags = true;
22338 case ISD::CopyToReg:
22339 case ISD::SIGN_EXTEND:
22340 case ISD::ZERO_EXTEND:
22341 case ISD::ANY_EXTEND:
22345 if (!ExpectingFlags) {
22346 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22347 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22349 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22350 X86::CondCode tmp = cc0;
22355 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22356 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22357 // FIXME: need symbolic constants for these magic numbers.
22358 // See X86ATTInstPrinter.cpp:printSSECC().
22359 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22360 if (Subtarget->hasAVX512()) {
22361 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22362 CMP01, DAG.getConstant(x86cc, MVT::i8));
22363 if (N->getValueType(0) != MVT::i1)
22364 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22368 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22369 CMP00.getValueType(), CMP00, CMP01,
22370 DAG.getConstant(x86cc, MVT::i8));
22372 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22373 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22375 if (is64BitFP && !Subtarget->is64Bit()) {
22376 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22377 // 64-bit integer, since that's not a legal type. Since
22378 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22379 // bits, but can do this little dance to extract the lowest 32 bits
22380 // and work with those going forward.
22381 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22383 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22385 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22386 Vector32, DAG.getIntPtrConstant(0));
22390 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22391 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22392 DAG.getConstant(1, IntVT));
22393 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22394 return OneBitOfTruth;
22402 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22403 /// so it can be folded inside ANDNP.
22404 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22405 EVT VT = N->getValueType(0);
22407 // Match direct AllOnes for 128 and 256-bit vectors
22408 if (ISD::isBuildVectorAllOnes(N))
22411 // Look through a bit convert.
22412 if (N->getOpcode() == ISD::BITCAST)
22413 N = N->getOperand(0).getNode();
22415 // Sometimes the operand may come from a insert_subvector building a 256-bit
22417 if (VT.is256BitVector() &&
22418 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22419 SDValue V1 = N->getOperand(0);
22420 SDValue V2 = N->getOperand(1);
22422 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22423 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22424 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22425 ISD::isBuildVectorAllOnes(V2.getNode()))
22432 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22433 // register. In most cases we actually compare or select YMM-sized registers
22434 // and mixing the two types creates horrible code. This method optimizes
22435 // some of the transition sequences.
22436 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22437 TargetLowering::DAGCombinerInfo &DCI,
22438 const X86Subtarget *Subtarget) {
22439 EVT VT = N->getValueType(0);
22440 if (!VT.is256BitVector())
22443 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22444 N->getOpcode() == ISD::ZERO_EXTEND ||
22445 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22447 SDValue Narrow = N->getOperand(0);
22448 EVT NarrowVT = Narrow->getValueType(0);
22449 if (!NarrowVT.is128BitVector())
22452 if (Narrow->getOpcode() != ISD::XOR &&
22453 Narrow->getOpcode() != ISD::AND &&
22454 Narrow->getOpcode() != ISD::OR)
22457 SDValue N0 = Narrow->getOperand(0);
22458 SDValue N1 = Narrow->getOperand(1);
22461 // The Left side has to be a trunc.
22462 if (N0.getOpcode() != ISD::TRUNCATE)
22465 // The type of the truncated inputs.
22466 EVT WideVT = N0->getOperand(0)->getValueType(0);
22470 // The right side has to be a 'trunc' or a constant vector.
22471 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22472 ConstantSDNode *RHSConstSplat = nullptr;
22473 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22474 RHSConstSplat = RHSBV->getConstantSplatNode();
22475 if (!RHSTrunc && !RHSConstSplat)
22478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22480 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22483 // Set N0 and N1 to hold the inputs to the new wide operation.
22484 N0 = N0->getOperand(0);
22485 if (RHSConstSplat) {
22486 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22487 SDValue(RHSConstSplat, 0));
22488 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22489 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22490 } else if (RHSTrunc) {
22491 N1 = N1->getOperand(0);
22494 // Generate the wide operation.
22495 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22496 unsigned Opcode = N->getOpcode();
22498 case ISD::ANY_EXTEND:
22500 case ISD::ZERO_EXTEND: {
22501 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22502 APInt Mask = APInt::getAllOnesValue(InBits);
22503 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22504 return DAG.getNode(ISD::AND, DL, VT,
22505 Op, DAG.getConstant(Mask, VT));
22507 case ISD::SIGN_EXTEND:
22508 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22509 Op, DAG.getValueType(NarrowVT));
22511 llvm_unreachable("Unexpected opcode");
22515 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22516 TargetLowering::DAGCombinerInfo &DCI,
22517 const X86Subtarget *Subtarget) {
22518 EVT VT = N->getValueType(0);
22519 if (DCI.isBeforeLegalizeOps())
22522 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22526 // Create BEXTR instructions
22527 // BEXTR is ((X >> imm) & (2**size-1))
22528 if (VT == MVT::i32 || VT == MVT::i64) {
22529 SDValue N0 = N->getOperand(0);
22530 SDValue N1 = N->getOperand(1);
22533 // Check for BEXTR.
22534 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22535 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22536 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22537 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22538 if (MaskNode && ShiftNode) {
22539 uint64_t Mask = MaskNode->getZExtValue();
22540 uint64_t Shift = ShiftNode->getZExtValue();
22541 if (isMask_64(Mask)) {
22542 uint64_t MaskSize = CountPopulation_64(Mask);
22543 if (Shift + MaskSize <= VT.getSizeInBits())
22544 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22545 DAG.getConstant(Shift | (MaskSize << 8), VT));
22553 // Want to form ANDNP nodes:
22554 // 1) In the hopes of then easily combining them with OR and AND nodes
22555 // to form PBLEND/PSIGN.
22556 // 2) To match ANDN packed intrinsics
22557 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22560 SDValue N0 = N->getOperand(0);
22561 SDValue N1 = N->getOperand(1);
22564 // Check LHS for vnot
22565 if (N0.getOpcode() == ISD::XOR &&
22566 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22567 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22568 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22570 // Check RHS for vnot
22571 if (N1.getOpcode() == ISD::XOR &&
22572 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22573 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22574 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22579 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22580 TargetLowering::DAGCombinerInfo &DCI,
22581 const X86Subtarget *Subtarget) {
22582 if (DCI.isBeforeLegalizeOps())
22585 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22589 SDValue N0 = N->getOperand(0);
22590 SDValue N1 = N->getOperand(1);
22591 EVT VT = N->getValueType(0);
22593 // look for psign/blend
22594 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22595 if (!Subtarget->hasSSSE3() ||
22596 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22599 // Canonicalize pandn to RHS
22600 if (N0.getOpcode() == X86ISD::ANDNP)
22602 // or (and (m, y), (pandn m, x))
22603 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22604 SDValue Mask = N1.getOperand(0);
22605 SDValue X = N1.getOperand(1);
22607 if (N0.getOperand(0) == Mask)
22608 Y = N0.getOperand(1);
22609 if (N0.getOperand(1) == Mask)
22610 Y = N0.getOperand(0);
22612 // Check to see if the mask appeared in both the AND and ANDNP and
22616 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22617 // Look through mask bitcast.
22618 if (Mask.getOpcode() == ISD::BITCAST)
22619 Mask = Mask.getOperand(0);
22620 if (X.getOpcode() == ISD::BITCAST)
22621 X = X.getOperand(0);
22622 if (Y.getOpcode() == ISD::BITCAST)
22623 Y = Y.getOperand(0);
22625 EVT MaskVT = Mask.getValueType();
22627 // Validate that the Mask operand is a vector sra node.
22628 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22629 // there is no psrai.b
22630 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22631 unsigned SraAmt = ~0;
22632 if (Mask.getOpcode() == ISD::SRA) {
22633 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22634 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22635 SraAmt = AmtConst->getZExtValue();
22636 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22637 SDValue SraC = Mask.getOperand(1);
22638 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22640 if ((SraAmt + 1) != EltBits)
22645 // Now we know we at least have a plendvb with the mask val. See if
22646 // we can form a psignb/w/d.
22647 // psign = x.type == y.type == mask.type && y = sub(0, x);
22648 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22649 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22650 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22651 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22652 "Unsupported VT for PSIGN");
22653 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22654 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22656 // PBLENDVB only available on SSE 4.1
22657 if (!Subtarget->hasSSE41())
22660 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22662 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22663 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22664 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22665 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22666 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22670 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22673 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22674 MachineFunction &MF = DAG.getMachineFunction();
22675 bool OptForSize = MF.getFunction()->getAttributes().
22676 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
22678 // SHLD/SHRD instructions have lower register pressure, but on some
22679 // platforms they have higher latency than the equivalent
22680 // series of shifts/or that would otherwise be generated.
22681 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22682 // have higher latencies and we are not optimizing for size.
22683 if (!OptForSize && Subtarget->isSHLDSlow())
22686 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22688 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22690 if (!N0.hasOneUse() || !N1.hasOneUse())
22693 SDValue ShAmt0 = N0.getOperand(1);
22694 if (ShAmt0.getValueType() != MVT::i8)
22696 SDValue ShAmt1 = N1.getOperand(1);
22697 if (ShAmt1.getValueType() != MVT::i8)
22699 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22700 ShAmt0 = ShAmt0.getOperand(0);
22701 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22702 ShAmt1 = ShAmt1.getOperand(0);
22705 unsigned Opc = X86ISD::SHLD;
22706 SDValue Op0 = N0.getOperand(0);
22707 SDValue Op1 = N1.getOperand(0);
22708 if (ShAmt0.getOpcode() == ISD::SUB) {
22709 Opc = X86ISD::SHRD;
22710 std::swap(Op0, Op1);
22711 std::swap(ShAmt0, ShAmt1);
22714 unsigned Bits = VT.getSizeInBits();
22715 if (ShAmt1.getOpcode() == ISD::SUB) {
22716 SDValue Sum = ShAmt1.getOperand(0);
22717 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22718 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22719 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22720 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22721 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22722 return DAG.getNode(Opc, DL, VT,
22724 DAG.getNode(ISD::TRUNCATE, DL,
22727 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22728 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22730 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22731 return DAG.getNode(Opc, DL, VT,
22732 N0.getOperand(0), N1.getOperand(0),
22733 DAG.getNode(ISD::TRUNCATE, DL,
22740 // Generate NEG and CMOV for integer abs.
22741 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22742 EVT VT = N->getValueType(0);
22744 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22745 // 8-bit integer abs to NEG and CMOV.
22746 if (VT.isInteger() && VT.getSizeInBits() == 8)
22749 SDValue N0 = N->getOperand(0);
22750 SDValue N1 = N->getOperand(1);
22753 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22754 // and change it to SUB and CMOV.
22755 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22756 N0.getOpcode() == ISD::ADD &&
22757 N0.getOperand(1) == N1 &&
22758 N1.getOpcode() == ISD::SRA &&
22759 N1.getOperand(0) == N0.getOperand(0))
22760 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22761 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22762 // Generate SUB & CMOV.
22763 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22764 DAG.getConstant(0, VT), N0.getOperand(0));
22766 SDValue Ops[] = { N0.getOperand(0), Neg,
22767 DAG.getConstant(X86::COND_GE, MVT::i8),
22768 SDValue(Neg.getNode(), 1) };
22769 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22774 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22775 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22776 TargetLowering::DAGCombinerInfo &DCI,
22777 const X86Subtarget *Subtarget) {
22778 if (DCI.isBeforeLegalizeOps())
22781 if (Subtarget->hasCMov()) {
22782 SDValue RV = performIntegerAbsCombine(N, DAG);
22790 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22791 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22792 TargetLowering::DAGCombinerInfo &DCI,
22793 const X86Subtarget *Subtarget) {
22794 LoadSDNode *Ld = cast<LoadSDNode>(N);
22795 EVT RegVT = Ld->getValueType(0);
22796 EVT MemVT = Ld->getMemoryVT();
22798 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22800 // On Sandybridge unaligned 256bit loads are inefficient.
22801 ISD::LoadExtType Ext = Ld->getExtensionType();
22802 unsigned Alignment = Ld->getAlignment();
22803 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22804 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
22805 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22806 unsigned NumElems = RegVT.getVectorNumElements();
22810 SDValue Ptr = Ld->getBasePtr();
22811 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22813 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22815 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22816 Ld->getPointerInfo(), Ld->isVolatile(),
22817 Ld->isNonTemporal(), Ld->isInvariant(),
22819 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22820 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22821 Ld->getPointerInfo(), Ld->isVolatile(),
22822 Ld->isNonTemporal(), Ld->isInvariant(),
22823 std::min(16U, Alignment));
22824 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22826 Load2.getValue(1));
22828 SDValue NewVec = DAG.getUNDEF(RegVT);
22829 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22830 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22831 return DCI.CombineTo(N, NewVec, TF, true);
22837 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22838 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22839 const X86Subtarget *Subtarget) {
22840 StoreSDNode *St = cast<StoreSDNode>(N);
22841 EVT VT = St->getValue().getValueType();
22842 EVT StVT = St->getMemoryVT();
22844 SDValue StoredVal = St->getOperand(1);
22845 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22847 // If we are saving a concatenation of two XMM registers, perform two stores.
22848 // On Sandy Bridge, 256-bit memory operations are executed by two
22849 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22850 // memory operation.
22851 unsigned Alignment = St->getAlignment();
22852 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22853 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22854 StVT == VT && !IsAligned) {
22855 unsigned NumElems = VT.getVectorNumElements();
22859 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22860 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22862 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22863 SDValue Ptr0 = St->getBasePtr();
22864 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22866 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22867 St->getPointerInfo(), St->isVolatile(),
22868 St->isNonTemporal(), Alignment);
22869 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22870 St->getPointerInfo(), St->isVolatile(),
22871 St->isNonTemporal(),
22872 std::min(16U, Alignment));
22873 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22876 // Optimize trunc store (of multiple scalars) to shuffle and store.
22877 // First, pack all of the elements in one place. Next, store to memory
22878 // in fewer chunks.
22879 if (St->isTruncatingStore() && VT.isVector()) {
22880 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22881 unsigned NumElems = VT.getVectorNumElements();
22882 assert(StVT != VT && "Cannot truncate to the same type");
22883 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22884 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22886 // From, To sizes and ElemCount must be pow of two
22887 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22888 // We are going to use the original vector elt for storing.
22889 // Accumulated smaller vector elements must be a multiple of the store size.
22890 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22892 unsigned SizeRatio = FromSz / ToSz;
22894 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22896 // Create a type on which we perform the shuffle
22897 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22898 StVT.getScalarType(), NumElems*SizeRatio);
22900 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22902 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22903 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22904 for (unsigned i = 0; i != NumElems; ++i)
22905 ShuffleVec[i] = i * SizeRatio;
22907 // Can't shuffle using an illegal type.
22908 if (!TLI.isTypeLegal(WideVecVT))
22911 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22912 DAG.getUNDEF(WideVecVT),
22914 // At this point all of the data is stored at the bottom of the
22915 // register. We now need to save it to mem.
22917 // Find the largest store unit
22918 MVT StoreType = MVT::i8;
22919 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
22920 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
22921 MVT Tp = (MVT::SimpleValueType)tp;
22922 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22926 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22927 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22928 (64 <= NumElems * ToSz))
22929 StoreType = MVT::f64;
22931 // Bitcast the original vector into a vector of store-size units
22932 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22933 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22934 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22935 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22936 SmallVector<SDValue, 8> Chains;
22937 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22938 TLI.getPointerTy());
22939 SDValue Ptr = St->getBasePtr();
22941 // Perform one or more big stores into memory.
22942 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22943 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22944 StoreType, ShuffWide,
22945 DAG.getIntPtrConstant(i));
22946 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22947 St->getPointerInfo(), St->isVolatile(),
22948 St->isNonTemporal(), St->getAlignment());
22949 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22950 Chains.push_back(Ch);
22953 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22956 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22957 // the FP state in cases where an emms may be missing.
22958 // A preferable solution to the general problem is to figure out the right
22959 // places to insert EMMS. This qualifies as a quick hack.
22961 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22962 if (VT.getSizeInBits() != 64)
22965 const Function *F = DAG.getMachineFunction().getFunction();
22966 bool NoImplicitFloatOps = F->getAttributes().
22967 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22968 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22969 && Subtarget->hasSSE2();
22970 if ((VT.isVector() ||
22971 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22972 isa<LoadSDNode>(St->getValue()) &&
22973 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22974 St->getChain().hasOneUse() && !St->isVolatile()) {
22975 SDNode* LdVal = St->getValue().getNode();
22976 LoadSDNode *Ld = nullptr;
22977 int TokenFactorIndex = -1;
22978 SmallVector<SDValue, 8> Ops;
22979 SDNode* ChainVal = St->getChain().getNode();
22980 // Must be a store of a load. We currently handle two cases: the load
22981 // is a direct child, and it's under an intervening TokenFactor. It is
22982 // possible to dig deeper under nested TokenFactors.
22983 if (ChainVal == LdVal)
22984 Ld = cast<LoadSDNode>(St->getChain());
22985 else if (St->getValue().hasOneUse() &&
22986 ChainVal->getOpcode() == ISD::TokenFactor) {
22987 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22988 if (ChainVal->getOperand(i).getNode() == LdVal) {
22989 TokenFactorIndex = i;
22990 Ld = cast<LoadSDNode>(St->getValue());
22992 Ops.push_back(ChainVal->getOperand(i));
22996 if (!Ld || !ISD::isNormalLoad(Ld))
22999 // If this is not the MMX case, i.e. we are just turning i64 load/store
23000 // into f64 load/store, avoid the transformation if there are multiple
23001 // uses of the loaded value.
23002 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23007 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23008 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23010 if (Subtarget->is64Bit() || F64IsLegal) {
23011 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23012 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23013 Ld->getPointerInfo(), Ld->isVolatile(),
23014 Ld->isNonTemporal(), Ld->isInvariant(),
23015 Ld->getAlignment());
23016 SDValue NewChain = NewLd.getValue(1);
23017 if (TokenFactorIndex != -1) {
23018 Ops.push_back(NewChain);
23019 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23021 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23022 St->getPointerInfo(),
23023 St->isVolatile(), St->isNonTemporal(),
23024 St->getAlignment());
23027 // Otherwise, lower to two pairs of 32-bit loads / stores.
23028 SDValue LoAddr = Ld->getBasePtr();
23029 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23030 DAG.getConstant(4, MVT::i32));
23032 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23033 Ld->getPointerInfo(),
23034 Ld->isVolatile(), Ld->isNonTemporal(),
23035 Ld->isInvariant(), Ld->getAlignment());
23036 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23037 Ld->getPointerInfo().getWithOffset(4),
23038 Ld->isVolatile(), Ld->isNonTemporal(),
23040 MinAlign(Ld->getAlignment(), 4));
23042 SDValue NewChain = LoLd.getValue(1);
23043 if (TokenFactorIndex != -1) {
23044 Ops.push_back(LoLd);
23045 Ops.push_back(HiLd);
23046 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23049 LoAddr = St->getBasePtr();
23050 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23051 DAG.getConstant(4, MVT::i32));
23053 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23054 St->getPointerInfo(),
23055 St->isVolatile(), St->isNonTemporal(),
23056 St->getAlignment());
23057 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23058 St->getPointerInfo().getWithOffset(4),
23060 St->isNonTemporal(),
23061 MinAlign(St->getAlignment(), 4));
23062 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23067 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23068 /// and return the operands for the horizontal operation in LHS and RHS. A
23069 /// horizontal operation performs the binary operation on successive elements
23070 /// of its first operand, then on successive elements of its second operand,
23071 /// returning the resulting values in a vector. For example, if
23072 /// A = < float a0, float a1, float a2, float a3 >
23074 /// B = < float b0, float b1, float b2, float b3 >
23075 /// then the result of doing a horizontal operation on A and B is
23076 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23077 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23078 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23079 /// set to A, RHS to B, and the routine returns 'true'.
23080 /// Note that the binary operation should have the property that if one of the
23081 /// operands is UNDEF then the result is UNDEF.
23082 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23083 // Look for the following pattern: if
23084 // A = < float a0, float a1, float a2, float a3 >
23085 // B = < float b0, float b1, float b2, float b3 >
23087 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23088 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23089 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23090 // which is A horizontal-op B.
23092 // At least one of the operands should be a vector shuffle.
23093 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23094 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23097 MVT VT = LHS.getSimpleValueType();
23099 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23100 "Unsupported vector type for horizontal add/sub");
23102 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23103 // operate independently on 128-bit lanes.
23104 unsigned NumElts = VT.getVectorNumElements();
23105 unsigned NumLanes = VT.getSizeInBits()/128;
23106 unsigned NumLaneElts = NumElts / NumLanes;
23107 assert((NumLaneElts % 2 == 0) &&
23108 "Vector type should have an even number of elements in each lane");
23109 unsigned HalfLaneElts = NumLaneElts/2;
23111 // View LHS in the form
23112 // LHS = VECTOR_SHUFFLE A, B, LMask
23113 // If LHS is not a shuffle then pretend it is the shuffle
23114 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23115 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23118 SmallVector<int, 16> LMask(NumElts);
23119 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23120 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23121 A = LHS.getOperand(0);
23122 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23123 B = LHS.getOperand(1);
23124 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23125 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23127 if (LHS.getOpcode() != ISD::UNDEF)
23129 for (unsigned i = 0; i != NumElts; ++i)
23133 // Likewise, view RHS in the form
23134 // RHS = VECTOR_SHUFFLE C, D, RMask
23136 SmallVector<int, 16> RMask(NumElts);
23137 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23138 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23139 C = RHS.getOperand(0);
23140 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23141 D = RHS.getOperand(1);
23142 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23143 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23145 if (RHS.getOpcode() != ISD::UNDEF)
23147 for (unsigned i = 0; i != NumElts; ++i)
23151 // Check that the shuffles are both shuffling the same vectors.
23152 if (!(A == C && B == D) && !(A == D && B == C))
23155 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23156 if (!A.getNode() && !B.getNode())
23159 // If A and B occur in reverse order in RHS, then "swap" them (which means
23160 // rewriting the mask).
23162 CommuteVectorShuffleMask(RMask, NumElts);
23164 // At this point LHS and RHS are equivalent to
23165 // LHS = VECTOR_SHUFFLE A, B, LMask
23166 // RHS = VECTOR_SHUFFLE A, B, RMask
23167 // Check that the masks correspond to performing a horizontal operation.
23168 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23169 for (unsigned i = 0; i != NumLaneElts; ++i) {
23170 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23172 // Ignore any UNDEF components.
23173 if (LIdx < 0 || RIdx < 0 ||
23174 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23175 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23178 // Check that successive elements are being operated on. If not, this is
23179 // not a horizontal operation.
23180 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23181 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23182 if (!(LIdx == Index && RIdx == Index + 1) &&
23183 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23188 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23189 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23193 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23194 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23195 const X86Subtarget *Subtarget) {
23196 EVT VT = N->getValueType(0);
23197 SDValue LHS = N->getOperand(0);
23198 SDValue RHS = N->getOperand(1);
23200 // Try to synthesize horizontal adds from adds of shuffles.
23201 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23202 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23203 isHorizontalBinOp(LHS, RHS, true))
23204 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23208 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23209 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23210 const X86Subtarget *Subtarget) {
23211 EVT VT = N->getValueType(0);
23212 SDValue LHS = N->getOperand(0);
23213 SDValue RHS = N->getOperand(1);
23215 // Try to synthesize horizontal subs from subs of shuffles.
23216 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23217 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23218 isHorizontalBinOp(LHS, RHS, false))
23219 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23223 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23224 /// X86ISD::FXOR nodes.
23225 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23226 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23227 // F[X]OR(0.0, x) -> x
23228 // F[X]OR(x, 0.0) -> x
23229 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23230 if (C->getValueAPF().isPosZero())
23231 return N->getOperand(1);
23232 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23233 if (C->getValueAPF().isPosZero())
23234 return N->getOperand(0);
23238 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23239 /// X86ISD::FMAX nodes.
23240 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23241 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23243 // Only perform optimizations if UnsafeMath is used.
23244 if (!DAG.getTarget().Options.UnsafeFPMath)
23247 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23248 // into FMINC and FMAXC, which are Commutative operations.
23249 unsigned NewOp = 0;
23250 switch (N->getOpcode()) {
23251 default: llvm_unreachable("unknown opcode");
23252 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23253 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23256 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23257 N->getOperand(0), N->getOperand(1));
23260 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23261 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23262 // FAND(0.0, x) -> 0.0
23263 // FAND(x, 0.0) -> 0.0
23264 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23265 if (C->getValueAPF().isPosZero())
23266 return N->getOperand(0);
23267 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23268 if (C->getValueAPF().isPosZero())
23269 return N->getOperand(1);
23273 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23274 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23275 // FANDN(x, 0.0) -> 0.0
23276 // FANDN(0.0, x) -> x
23277 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23278 if (C->getValueAPF().isPosZero())
23279 return N->getOperand(1);
23280 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23281 if (C->getValueAPF().isPosZero())
23282 return N->getOperand(1);
23286 static SDValue PerformBTCombine(SDNode *N,
23288 TargetLowering::DAGCombinerInfo &DCI) {
23289 // BT ignores high bits in the bit index operand.
23290 SDValue Op1 = N->getOperand(1);
23291 if (Op1.hasOneUse()) {
23292 unsigned BitWidth = Op1.getValueSizeInBits();
23293 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23294 APInt KnownZero, KnownOne;
23295 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23296 !DCI.isBeforeLegalizeOps());
23297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23298 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23299 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23300 DCI.CommitTargetLoweringOpt(TLO);
23305 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23306 SDValue Op = N->getOperand(0);
23307 if (Op.getOpcode() == ISD::BITCAST)
23308 Op = Op.getOperand(0);
23309 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23310 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23311 VT.getVectorElementType().getSizeInBits() ==
23312 OpVT.getVectorElementType().getSizeInBits()) {
23313 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23318 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23319 const X86Subtarget *Subtarget) {
23320 EVT VT = N->getValueType(0);
23321 if (!VT.isVector())
23324 SDValue N0 = N->getOperand(0);
23325 SDValue N1 = N->getOperand(1);
23326 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23329 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23330 // both SSE and AVX2 since there is no sign-extended shift right
23331 // operation on a vector with 64-bit elements.
23332 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23333 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23334 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23335 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23336 SDValue N00 = N0.getOperand(0);
23338 // EXTLOAD has a better solution on AVX2,
23339 // it may be replaced with X86ISD::VSEXT node.
23340 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23341 if (!ISD::isNormalLoad(N00.getNode()))
23344 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23345 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23347 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23353 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23354 TargetLowering::DAGCombinerInfo &DCI,
23355 const X86Subtarget *Subtarget) {
23356 if (!DCI.isBeforeLegalizeOps())
23359 if (!Subtarget->hasFp256())
23362 EVT VT = N->getValueType(0);
23363 if (VT.isVector() && VT.getSizeInBits() == 256) {
23364 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23372 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23373 const X86Subtarget* Subtarget) {
23375 EVT VT = N->getValueType(0);
23377 // Let legalize expand this if it isn't a legal type yet.
23378 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23381 EVT ScalarVT = VT.getScalarType();
23382 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23383 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23386 SDValue A = N->getOperand(0);
23387 SDValue B = N->getOperand(1);
23388 SDValue C = N->getOperand(2);
23390 bool NegA = (A.getOpcode() == ISD::FNEG);
23391 bool NegB = (B.getOpcode() == ISD::FNEG);
23392 bool NegC = (C.getOpcode() == ISD::FNEG);
23394 // Negative multiplication when NegA xor NegB
23395 bool NegMul = (NegA != NegB);
23397 A = A.getOperand(0);
23399 B = B.getOperand(0);
23401 C = C.getOperand(0);
23405 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23407 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23409 return DAG.getNode(Opcode, dl, VT, A, B, C);
23412 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23413 TargetLowering::DAGCombinerInfo &DCI,
23414 const X86Subtarget *Subtarget) {
23415 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23416 // (and (i32 x86isd::setcc_carry), 1)
23417 // This eliminates the zext. This transformation is necessary because
23418 // ISD::SETCC is always legalized to i8.
23420 SDValue N0 = N->getOperand(0);
23421 EVT VT = N->getValueType(0);
23423 if (N0.getOpcode() == ISD::AND &&
23425 N0.getOperand(0).hasOneUse()) {
23426 SDValue N00 = N0.getOperand(0);
23427 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23428 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23429 if (!C || C->getZExtValue() != 1)
23431 return DAG.getNode(ISD::AND, dl, VT,
23432 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23433 N00.getOperand(0), N00.getOperand(1)),
23434 DAG.getConstant(1, VT));
23438 if (N0.getOpcode() == ISD::TRUNCATE &&
23440 N0.getOperand(0).hasOneUse()) {
23441 SDValue N00 = N0.getOperand(0);
23442 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23443 return DAG.getNode(ISD::AND, dl, VT,
23444 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23445 N00.getOperand(0), N00.getOperand(1)),
23446 DAG.getConstant(1, VT));
23449 if (VT.is256BitVector()) {
23450 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23458 // Optimize x == -y --> x+y == 0
23459 // x != -y --> x+y != 0
23460 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23461 const X86Subtarget* Subtarget) {
23462 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23463 SDValue LHS = N->getOperand(0);
23464 SDValue RHS = N->getOperand(1);
23465 EVT VT = N->getValueType(0);
23468 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23469 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23470 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23471 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23472 LHS.getValueType(), RHS, LHS.getOperand(1));
23473 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23474 addV, DAG.getConstant(0, addV.getValueType()), CC);
23476 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23477 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23478 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23479 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23480 RHS.getValueType(), LHS, RHS.getOperand(1));
23481 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23482 addV, DAG.getConstant(0, addV.getValueType()), CC);
23485 if (VT.getScalarType() == MVT::i1) {
23486 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23487 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23488 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23489 if (!IsSEXT0 && !IsVZero0)
23491 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23492 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23493 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23495 if (!IsSEXT1 && !IsVZero1)
23498 if (IsSEXT0 && IsVZero1) {
23499 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23500 if (CC == ISD::SETEQ)
23501 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23502 return LHS.getOperand(0);
23504 if (IsSEXT1 && IsVZero0) {
23505 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23506 if (CC == ISD::SETEQ)
23507 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23508 return RHS.getOperand(0);
23515 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23516 const X86Subtarget *Subtarget) {
23518 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23519 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23520 "X86insertps is only defined for v4x32");
23522 SDValue Ld = N->getOperand(1);
23523 if (MayFoldLoad(Ld)) {
23524 // Extract the countS bits from the immediate so we can get the proper
23525 // address when narrowing the vector load to a specific element.
23526 // When the second source op is a memory address, interps doesn't use
23527 // countS and just gets an f32 from that address.
23528 unsigned DestIndex =
23529 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23530 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23534 // Create this as a scalar to vector to match the instruction pattern.
23535 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23536 // countS bits are ignored when loading from memory on insertps, which
23537 // means we don't need to explicitly set them to 0.
23538 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23539 LoadScalarToVector, N->getOperand(2));
23542 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23543 // as "sbb reg,reg", since it can be extended without zext and produces
23544 // an all-ones bit which is more useful than 0/1 in some cases.
23545 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23548 return DAG.getNode(ISD::AND, DL, VT,
23549 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23550 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23551 DAG.getConstant(1, VT));
23552 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23553 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23554 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23555 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23558 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23559 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23560 TargetLowering::DAGCombinerInfo &DCI,
23561 const X86Subtarget *Subtarget) {
23563 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23564 SDValue EFLAGS = N->getOperand(1);
23566 if (CC == X86::COND_A) {
23567 // Try to convert COND_A into COND_B in an attempt to facilitate
23568 // materializing "setb reg".
23570 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23571 // cannot take an immediate as its first operand.
23573 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23574 EFLAGS.getValueType().isInteger() &&
23575 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23576 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23577 EFLAGS.getNode()->getVTList(),
23578 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23579 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23580 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23584 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23585 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23587 if (CC == X86::COND_B)
23588 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23592 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23593 if (Flags.getNode()) {
23594 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23595 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23601 // Optimize branch condition evaluation.
23603 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23604 TargetLowering::DAGCombinerInfo &DCI,
23605 const X86Subtarget *Subtarget) {
23607 SDValue Chain = N->getOperand(0);
23608 SDValue Dest = N->getOperand(1);
23609 SDValue EFLAGS = N->getOperand(3);
23610 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23614 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23615 if (Flags.getNode()) {
23616 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23617 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23624 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23625 SelectionDAG &DAG) {
23626 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23627 // optimize away operation when it's from a constant.
23629 // The general transformation is:
23630 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23631 // AND(VECTOR_CMP(x,y), constant2)
23632 // constant2 = UNARYOP(constant)
23634 // Early exit if this isn't a vector operation, the operand of the
23635 // unary operation isn't a bitwise AND, or if the sizes of the operations
23636 // aren't the same.
23637 EVT VT = N->getValueType(0);
23638 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23639 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23640 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23643 // Now check that the other operand of the AND is a constant. We could
23644 // make the transformation for non-constant splats as well, but it's unclear
23645 // that would be a benefit as it would not eliminate any operations, just
23646 // perform one more step in scalar code before moving to the vector unit.
23647 if (BuildVectorSDNode *BV =
23648 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23649 // Bail out if the vector isn't a constant.
23650 if (!BV->isConstant())
23653 // Everything checks out. Build up the new and improved node.
23655 EVT IntVT = BV->getValueType(0);
23656 // Create a new constant of the appropriate type for the transformed
23658 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23659 // The AND node needs bitcasts to/from an integer vector type around it.
23660 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23661 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23662 N->getOperand(0)->getOperand(0), MaskConst);
23663 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23670 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23671 const X86TargetLowering *XTLI) {
23672 // First try to optimize away the conversion entirely when it's
23673 // conditionally from a constant. Vectors only.
23674 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23675 if (Res != SDValue())
23678 // Now move on to more general possibilities.
23679 SDValue Op0 = N->getOperand(0);
23680 EVT InVT = Op0->getValueType(0);
23682 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23683 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23685 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23686 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23687 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23690 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23691 // a 32-bit target where SSE doesn't support i64->FP operations.
23692 if (Op0.getOpcode() == ISD::LOAD) {
23693 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23694 EVT VT = Ld->getValueType(0);
23695 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23696 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23697 !XTLI->getSubtarget()->is64Bit() &&
23699 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
23700 Ld->getChain(), Op0, DAG);
23701 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23708 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23709 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23710 X86TargetLowering::DAGCombinerInfo &DCI) {
23711 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23712 // the result is either zero or one (depending on the input carry bit).
23713 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23714 if (X86::isZeroNode(N->getOperand(0)) &&
23715 X86::isZeroNode(N->getOperand(1)) &&
23716 // We don't have a good way to replace an EFLAGS use, so only do this when
23718 SDValue(N, 1).use_empty()) {
23720 EVT VT = N->getValueType(0);
23721 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23722 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23723 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23724 DAG.getConstant(X86::COND_B,MVT::i8),
23726 DAG.getConstant(1, VT));
23727 return DCI.CombineTo(N, Res1, CarryOut);
23733 // fold (add Y, (sete X, 0)) -> adc 0, Y
23734 // (add Y, (setne X, 0)) -> sbb -1, Y
23735 // (sub (sete X, 0), Y) -> sbb 0, Y
23736 // (sub (setne X, 0), Y) -> adc -1, Y
23737 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23740 // Look through ZExts.
23741 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23742 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23745 SDValue SetCC = Ext.getOperand(0);
23746 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23749 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23750 if (CC != X86::COND_E && CC != X86::COND_NE)
23753 SDValue Cmp = SetCC.getOperand(1);
23754 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23755 !X86::isZeroNode(Cmp.getOperand(1)) ||
23756 !Cmp.getOperand(0).getValueType().isInteger())
23759 SDValue CmpOp0 = Cmp.getOperand(0);
23760 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23761 DAG.getConstant(1, CmpOp0.getValueType()));
23763 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23764 if (CC == X86::COND_NE)
23765 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23766 DL, OtherVal.getValueType(), OtherVal,
23767 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23768 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23769 DL, OtherVal.getValueType(), OtherVal,
23770 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23773 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23774 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23775 const X86Subtarget *Subtarget) {
23776 EVT VT = N->getValueType(0);
23777 SDValue Op0 = N->getOperand(0);
23778 SDValue Op1 = N->getOperand(1);
23780 // Try to synthesize horizontal adds from adds of shuffles.
23781 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23782 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23783 isHorizontalBinOp(Op0, Op1, true))
23784 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23786 return OptimizeConditionalInDecrement(N, DAG);
23789 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23790 const X86Subtarget *Subtarget) {
23791 SDValue Op0 = N->getOperand(0);
23792 SDValue Op1 = N->getOperand(1);
23794 // X86 can't encode an immediate LHS of a sub. See if we can push the
23795 // negation into a preceding instruction.
23796 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23797 // If the RHS of the sub is a XOR with one use and a constant, invert the
23798 // immediate. Then add one to the LHS of the sub so we can turn
23799 // X-Y -> X+~Y+1, saving one register.
23800 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23801 isa<ConstantSDNode>(Op1.getOperand(1))) {
23802 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23803 EVT VT = Op0.getValueType();
23804 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23806 DAG.getConstant(~XorC, VT));
23807 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23808 DAG.getConstant(C->getAPIntValue()+1, VT));
23812 // Try to synthesize horizontal adds from adds of shuffles.
23813 EVT VT = N->getValueType(0);
23814 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23815 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23816 isHorizontalBinOp(Op0, Op1, true))
23817 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23819 return OptimizeConditionalInDecrement(N, DAG);
23822 /// performVZEXTCombine - Performs build vector combines
23823 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23824 TargetLowering::DAGCombinerInfo &DCI,
23825 const X86Subtarget *Subtarget) {
23826 // (vzext (bitcast (vzext (x)) -> (vzext x)
23827 SDValue In = N->getOperand(0);
23828 while (In.getOpcode() == ISD::BITCAST)
23829 In = In.getOperand(0);
23831 if (In.getOpcode() != X86ISD::VZEXT)
23834 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
23838 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23839 DAGCombinerInfo &DCI) const {
23840 SelectionDAG &DAG = DCI.DAG;
23841 switch (N->getOpcode()) {
23843 case ISD::EXTRACT_VECTOR_ELT:
23844 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23846 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23847 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23848 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23849 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23850 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23851 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23854 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23855 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23856 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23857 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23858 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23859 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23860 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23861 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23862 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23864 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23866 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23867 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23868 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23869 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23870 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23871 case ISD::ANY_EXTEND:
23872 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23873 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23874 case ISD::SIGN_EXTEND_INREG:
23875 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23876 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23877 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23878 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23879 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23880 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23881 case X86ISD::SHUFP: // Handle all target specific shuffles
23882 case X86ISD::PALIGNR:
23883 case X86ISD::UNPCKH:
23884 case X86ISD::UNPCKL:
23885 case X86ISD::MOVHLPS:
23886 case X86ISD::MOVLHPS:
23887 case X86ISD::PSHUFB:
23888 case X86ISD::PSHUFD:
23889 case X86ISD::PSHUFHW:
23890 case X86ISD::PSHUFLW:
23891 case X86ISD::MOVSS:
23892 case X86ISD::MOVSD:
23893 case X86ISD::VPERMILPI:
23894 case X86ISD::VPERM2X128:
23895 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23896 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23897 case ISD::INTRINSIC_WO_CHAIN:
23898 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23899 case X86ISD::INSERTPS:
23900 return PerformINSERTPSCombine(N, DAG, Subtarget);
23901 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23907 /// isTypeDesirableForOp - Return true if the target has native support for
23908 /// the specified value type and it is 'desirable' to use the type for the
23909 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23910 /// instruction encodings are longer and some i16 instructions are slow.
23911 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23912 if (!isTypeLegal(VT))
23914 if (VT != MVT::i16)
23921 case ISD::SIGN_EXTEND:
23922 case ISD::ZERO_EXTEND:
23923 case ISD::ANY_EXTEND:
23936 /// IsDesirableToPromoteOp - This method query the target whether it is
23937 /// beneficial for dag combiner to promote the specified node. If true, it
23938 /// should return the desired promotion type by reference.
23939 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23940 EVT VT = Op.getValueType();
23941 if (VT != MVT::i16)
23944 bool Promote = false;
23945 bool Commute = false;
23946 switch (Op.getOpcode()) {
23949 LoadSDNode *LD = cast<LoadSDNode>(Op);
23950 // If the non-extending load has a single use and it's not live out, then it
23951 // might be folded.
23952 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23953 Op.hasOneUse()*/) {
23954 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23955 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23956 // The only case where we'd want to promote LOAD (rather then it being
23957 // promoted as an operand is when it's only use is liveout.
23958 if (UI->getOpcode() != ISD::CopyToReg)
23965 case ISD::SIGN_EXTEND:
23966 case ISD::ZERO_EXTEND:
23967 case ISD::ANY_EXTEND:
23972 SDValue N0 = Op.getOperand(0);
23973 // Look out for (store (shl (load), x)).
23974 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23987 SDValue N0 = Op.getOperand(0);
23988 SDValue N1 = Op.getOperand(1);
23989 if (!Commute && MayFoldLoad(N1))
23991 // Avoid disabling potential load folding opportunities.
23992 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23994 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24004 //===----------------------------------------------------------------------===//
24005 // X86 Inline Assembly Support
24006 //===----------------------------------------------------------------------===//
24009 // Helper to match a string separated by whitespace.
24010 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24011 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24013 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24014 StringRef piece(*args[i]);
24015 if (!s.startswith(piece)) // Check if the piece matches.
24018 s = s.substr(piece.size());
24019 StringRef::size_type pos = s.find_first_not_of(" \t");
24020 if (pos == 0) // We matched a prefix.
24028 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24031 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24033 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24034 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24035 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24036 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24038 if (AsmPieces.size() == 3)
24040 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24047 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24048 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24050 std::string AsmStr = IA->getAsmString();
24052 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24053 if (!Ty || Ty->getBitWidth() % 16 != 0)
24056 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24057 SmallVector<StringRef, 4> AsmPieces;
24058 SplitString(AsmStr, AsmPieces, ";\n");
24060 switch (AsmPieces.size()) {
24061 default: return false;
24063 // FIXME: this should verify that we are targeting a 486 or better. If not,
24064 // we will turn this bswap into something that will be lowered to logical
24065 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24066 // lower so don't worry about this.
24068 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24069 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24070 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24071 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24072 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24073 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24074 // No need to check constraints, nothing other than the equivalent of
24075 // "=r,0" would be valid here.
24076 return IntrinsicLowering::LowerToByteSwap(CI);
24079 // rorw $$8, ${0:w} --> llvm.bswap.i16
24080 if (CI->getType()->isIntegerTy(16) &&
24081 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24082 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24083 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24085 const std::string &ConstraintsStr = IA->getConstraintString();
24086 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24087 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24088 if (clobbersFlagRegisters(AsmPieces))
24089 return IntrinsicLowering::LowerToByteSwap(CI);
24093 if (CI->getType()->isIntegerTy(32) &&
24094 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24095 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24096 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24097 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24099 const std::string &ConstraintsStr = IA->getConstraintString();
24100 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24101 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24102 if (clobbersFlagRegisters(AsmPieces))
24103 return IntrinsicLowering::LowerToByteSwap(CI);
24106 if (CI->getType()->isIntegerTy(64)) {
24107 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24108 if (Constraints.size() >= 2 &&
24109 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24110 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24111 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24112 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24113 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24114 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24115 return IntrinsicLowering::LowerToByteSwap(CI);
24123 /// getConstraintType - Given a constraint letter, return the type of
24124 /// constraint it is for this target.
24125 X86TargetLowering::ConstraintType
24126 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24127 if (Constraint.size() == 1) {
24128 switch (Constraint[0]) {
24139 return C_RegisterClass;
24163 return TargetLowering::getConstraintType(Constraint);
24166 /// Examine constraint type and operand type and determine a weight value.
24167 /// This object must already have been set up with the operand type
24168 /// and the current alternative constraint selected.
24169 TargetLowering::ConstraintWeight
24170 X86TargetLowering::getSingleConstraintMatchWeight(
24171 AsmOperandInfo &info, const char *constraint) const {
24172 ConstraintWeight weight = CW_Invalid;
24173 Value *CallOperandVal = info.CallOperandVal;
24174 // If we don't have a value, we can't do a match,
24175 // but allow it at the lowest weight.
24176 if (!CallOperandVal)
24178 Type *type = CallOperandVal->getType();
24179 // Look at the constraint type.
24180 switch (*constraint) {
24182 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24193 if (CallOperandVal->getType()->isIntegerTy())
24194 weight = CW_SpecificReg;
24199 if (type->isFloatingPointTy())
24200 weight = CW_SpecificReg;
24203 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24204 weight = CW_SpecificReg;
24208 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24209 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24210 weight = CW_Register;
24213 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24214 if (C->getZExtValue() <= 31)
24215 weight = CW_Constant;
24219 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24220 if (C->getZExtValue() <= 63)
24221 weight = CW_Constant;
24225 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24226 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24227 weight = CW_Constant;
24231 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24232 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24233 weight = CW_Constant;
24237 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24238 if (C->getZExtValue() <= 3)
24239 weight = CW_Constant;
24243 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24244 if (C->getZExtValue() <= 0xff)
24245 weight = CW_Constant;
24250 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24251 weight = CW_Constant;
24255 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24256 if ((C->getSExtValue() >= -0x80000000LL) &&
24257 (C->getSExtValue() <= 0x7fffffffLL))
24258 weight = CW_Constant;
24262 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24263 if (C->getZExtValue() <= 0xffffffff)
24264 weight = CW_Constant;
24271 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24272 /// with another that has more specific requirements based on the type of the
24273 /// corresponding operand.
24274 const char *X86TargetLowering::
24275 LowerXConstraint(EVT ConstraintVT) const {
24276 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24277 // 'f' like normal targets.
24278 if (ConstraintVT.isFloatingPoint()) {
24279 if (Subtarget->hasSSE2())
24281 if (Subtarget->hasSSE1())
24285 return TargetLowering::LowerXConstraint(ConstraintVT);
24288 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24289 /// vector. If it is invalid, don't add anything to Ops.
24290 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24291 std::string &Constraint,
24292 std::vector<SDValue>&Ops,
24293 SelectionDAG &DAG) const {
24296 // Only support length 1 constraints for now.
24297 if (Constraint.length() > 1) return;
24299 char ConstraintLetter = Constraint[0];
24300 switch (ConstraintLetter) {
24303 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24304 if (C->getZExtValue() <= 31) {
24305 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24311 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24312 if (C->getZExtValue() <= 63) {
24313 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24319 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24320 if (isInt<8>(C->getSExtValue())) {
24321 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24327 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24328 if (C->getZExtValue() <= 255) {
24329 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24335 // 32-bit signed value
24336 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24337 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24338 C->getSExtValue())) {
24339 // Widen to 64 bits here to get it sign extended.
24340 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24343 // FIXME gcc accepts some relocatable values here too, but only in certain
24344 // memory models; it's complicated.
24349 // 32-bit unsigned value
24350 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24351 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24352 C->getZExtValue())) {
24353 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24357 // FIXME gcc accepts some relocatable values here too, but only in certain
24358 // memory models; it's complicated.
24362 // Literal immediates are always ok.
24363 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24364 // Widen to 64 bits here to get it sign extended.
24365 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24369 // In any sort of PIC mode addresses need to be computed at runtime by
24370 // adding in a register or some sort of table lookup. These can't
24371 // be used as immediates.
24372 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24375 // If we are in non-pic codegen mode, we allow the address of a global (with
24376 // an optional displacement) to be used with 'i'.
24377 GlobalAddressSDNode *GA = nullptr;
24378 int64_t Offset = 0;
24380 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24382 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24383 Offset += GA->getOffset();
24385 } else if (Op.getOpcode() == ISD::ADD) {
24386 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24387 Offset += C->getZExtValue();
24388 Op = Op.getOperand(0);
24391 } else if (Op.getOpcode() == ISD::SUB) {
24392 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24393 Offset += -C->getZExtValue();
24394 Op = Op.getOperand(0);
24399 // Otherwise, this isn't something we can handle, reject it.
24403 const GlobalValue *GV = GA->getGlobal();
24404 // If we require an extra load to get this address, as in PIC mode, we
24405 // can't accept it.
24406 if (isGlobalStubReference(
24407 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24410 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24411 GA->getValueType(0), Offset);
24416 if (Result.getNode()) {
24417 Ops.push_back(Result);
24420 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24423 std::pair<unsigned, const TargetRegisterClass*>
24424 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24426 // First, see if this is a constraint that directly corresponds to an LLVM
24428 if (Constraint.size() == 1) {
24429 // GCC Constraint Letters
24430 switch (Constraint[0]) {
24432 // TODO: Slight differences here in allocation order and leaving
24433 // RIP in the class. Do they matter any more here than they do
24434 // in the normal allocation?
24435 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24436 if (Subtarget->is64Bit()) {
24437 if (VT == MVT::i32 || VT == MVT::f32)
24438 return std::make_pair(0U, &X86::GR32RegClass);
24439 if (VT == MVT::i16)
24440 return std::make_pair(0U, &X86::GR16RegClass);
24441 if (VT == MVT::i8 || VT == MVT::i1)
24442 return std::make_pair(0U, &X86::GR8RegClass);
24443 if (VT == MVT::i64 || VT == MVT::f64)
24444 return std::make_pair(0U, &X86::GR64RegClass);
24447 // 32-bit fallthrough
24448 case 'Q': // Q_REGS
24449 if (VT == MVT::i32 || VT == MVT::f32)
24450 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24451 if (VT == MVT::i16)
24452 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24453 if (VT == MVT::i8 || VT == MVT::i1)
24454 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24455 if (VT == MVT::i64)
24456 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24458 case 'r': // GENERAL_REGS
24459 case 'l': // INDEX_REGS
24460 if (VT == MVT::i8 || VT == MVT::i1)
24461 return std::make_pair(0U, &X86::GR8RegClass);
24462 if (VT == MVT::i16)
24463 return std::make_pair(0U, &X86::GR16RegClass);
24464 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24465 return std::make_pair(0U, &X86::GR32RegClass);
24466 return std::make_pair(0U, &X86::GR64RegClass);
24467 case 'R': // LEGACY_REGS
24468 if (VT == MVT::i8 || VT == MVT::i1)
24469 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24470 if (VT == MVT::i16)
24471 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24472 if (VT == MVT::i32 || !Subtarget->is64Bit())
24473 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24474 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24475 case 'f': // FP Stack registers.
24476 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24477 // value to the correct fpstack register class.
24478 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24479 return std::make_pair(0U, &X86::RFP32RegClass);
24480 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24481 return std::make_pair(0U, &X86::RFP64RegClass);
24482 return std::make_pair(0U, &X86::RFP80RegClass);
24483 case 'y': // MMX_REGS if MMX allowed.
24484 if (!Subtarget->hasMMX()) break;
24485 return std::make_pair(0U, &X86::VR64RegClass);
24486 case 'Y': // SSE_REGS if SSE2 allowed
24487 if (!Subtarget->hasSSE2()) break;
24489 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24490 if (!Subtarget->hasSSE1()) break;
24492 switch (VT.SimpleTy) {
24494 // Scalar SSE types.
24497 return std::make_pair(0U, &X86::FR32RegClass);
24500 return std::make_pair(0U, &X86::FR64RegClass);
24508 return std::make_pair(0U, &X86::VR128RegClass);
24516 return std::make_pair(0U, &X86::VR256RegClass);
24521 return std::make_pair(0U, &X86::VR512RegClass);
24527 // Use the default implementation in TargetLowering to convert the register
24528 // constraint into a member of a register class.
24529 std::pair<unsigned, const TargetRegisterClass*> Res;
24530 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24532 // Not found as a standard register?
24534 // Map st(0) -> st(7) -> ST0
24535 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24536 tolower(Constraint[1]) == 's' &&
24537 tolower(Constraint[2]) == 't' &&
24538 Constraint[3] == '(' &&
24539 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24540 Constraint[5] == ')' &&
24541 Constraint[6] == '}') {
24543 Res.first = X86::FP0+Constraint[4]-'0';
24544 Res.second = &X86::RFP80RegClass;
24548 // GCC allows "st(0)" to be called just plain "st".
24549 if (StringRef("{st}").equals_lower(Constraint)) {
24550 Res.first = X86::FP0;
24551 Res.second = &X86::RFP80RegClass;
24556 if (StringRef("{flags}").equals_lower(Constraint)) {
24557 Res.first = X86::EFLAGS;
24558 Res.second = &X86::CCRRegClass;
24562 // 'A' means EAX + EDX.
24563 if (Constraint == "A") {
24564 Res.first = X86::EAX;
24565 Res.second = &X86::GR32_ADRegClass;
24571 // Otherwise, check to see if this is a register class of the wrong value
24572 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24573 // turn into {ax},{dx}.
24574 if (Res.second->hasType(VT))
24575 return Res; // Correct type already, nothing to do.
24577 // All of the single-register GCC register classes map their values onto
24578 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24579 // really want an 8-bit or 32-bit register, map to the appropriate register
24580 // class and return the appropriate register.
24581 if (Res.second == &X86::GR16RegClass) {
24582 if (VT == MVT::i8 || VT == MVT::i1) {
24583 unsigned DestReg = 0;
24584 switch (Res.first) {
24586 case X86::AX: DestReg = X86::AL; break;
24587 case X86::DX: DestReg = X86::DL; break;
24588 case X86::CX: DestReg = X86::CL; break;
24589 case X86::BX: DestReg = X86::BL; break;
24592 Res.first = DestReg;
24593 Res.second = &X86::GR8RegClass;
24595 } else if (VT == MVT::i32 || VT == MVT::f32) {
24596 unsigned DestReg = 0;
24597 switch (Res.first) {
24599 case X86::AX: DestReg = X86::EAX; break;
24600 case X86::DX: DestReg = X86::EDX; break;
24601 case X86::CX: DestReg = X86::ECX; break;
24602 case X86::BX: DestReg = X86::EBX; break;
24603 case X86::SI: DestReg = X86::ESI; break;
24604 case X86::DI: DestReg = X86::EDI; break;
24605 case X86::BP: DestReg = X86::EBP; break;
24606 case X86::SP: DestReg = X86::ESP; break;
24609 Res.first = DestReg;
24610 Res.second = &X86::GR32RegClass;
24612 } else if (VT == MVT::i64 || VT == MVT::f64) {
24613 unsigned DestReg = 0;
24614 switch (Res.first) {
24616 case X86::AX: DestReg = X86::RAX; break;
24617 case X86::DX: DestReg = X86::RDX; break;
24618 case X86::CX: DestReg = X86::RCX; break;
24619 case X86::BX: DestReg = X86::RBX; break;
24620 case X86::SI: DestReg = X86::RSI; break;
24621 case X86::DI: DestReg = X86::RDI; break;
24622 case X86::BP: DestReg = X86::RBP; break;
24623 case X86::SP: DestReg = X86::RSP; break;
24626 Res.first = DestReg;
24627 Res.second = &X86::GR64RegClass;
24630 } else if (Res.second == &X86::FR32RegClass ||
24631 Res.second == &X86::FR64RegClass ||
24632 Res.second == &X86::VR128RegClass ||
24633 Res.second == &X86::VR256RegClass ||
24634 Res.second == &X86::FR32XRegClass ||
24635 Res.second == &X86::FR64XRegClass ||
24636 Res.second == &X86::VR128XRegClass ||
24637 Res.second == &X86::VR256XRegClass ||
24638 Res.second == &X86::VR512RegClass) {
24639 // Handle references to XMM physical registers that got mapped into the
24640 // wrong class. This can happen with constraints like {xmm0} where the
24641 // target independent register mapper will just pick the first match it can
24642 // find, ignoring the required type.
24644 if (VT == MVT::f32 || VT == MVT::i32)
24645 Res.second = &X86::FR32RegClass;
24646 else if (VT == MVT::f64 || VT == MVT::i64)
24647 Res.second = &X86::FR64RegClass;
24648 else if (X86::VR128RegClass.hasType(VT))
24649 Res.second = &X86::VR128RegClass;
24650 else if (X86::VR256RegClass.hasType(VT))
24651 Res.second = &X86::VR256RegClass;
24652 else if (X86::VR512RegClass.hasType(VT))
24653 Res.second = &X86::VR512RegClass;
24659 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24661 // Scaling factors are not free at all.
24662 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24663 // will take 2 allocations in the out of order engine instead of 1
24664 // for plain addressing mode, i.e. inst (reg1).
24666 // vaddps (%rsi,%drx), %ymm0, %ymm1
24667 // Requires two allocations (one for the load, one for the computation)
24669 // vaddps (%rsi), %ymm0, %ymm1
24670 // Requires just 1 allocation, i.e., freeing allocations for other operations
24671 // and having less micro operations to execute.
24673 // For some X86 architectures, this is even worse because for instance for
24674 // stores, the complex addressing mode forces the instruction to use the
24675 // "load" ports instead of the dedicated "store" port.
24676 // E.g., on Haswell:
24677 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24678 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24679 if (isLegalAddressingMode(AM, Ty))
24680 // Scale represents reg2 * scale, thus account for 1
24681 // as soon as we use a second register.
24682 return AM.Scale != 0;
24686 bool X86TargetLowering::isTargetFTOL() const {
24687 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();