1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
203 // are Legal, f80 is custom lowered.
204 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
207 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
209 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
212 if (X86ScalarSSEf32) {
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
214 // f32 and f64 cases are Legal, f80 case is not
215 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
221 // Handle FP_TO_UINT by promoting the destination to a larger signed
223 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
225 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
227 if (Subtarget->is64Bit()) {
228 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
229 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
230 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
234 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 } else if (!Subtarget->useSoftFloat()) {
237 // Since AVX is a superset of SSE3, only check for SSE here.
238 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
239 // Expand FP_TO_UINT into a select.
240 // FIXME: We would like to use a Custom expander here eventually to do
241 // the optimal thing for SSE vs. the default expansion in the legalizer.
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
244 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
249 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
252 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
253 if (!X86ScalarSSEf64) {
254 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
255 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
258 // Without SSE, i64->f64 goes through memory.
259 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
263 // Scalar integer divide and remainder are lowered to use operations that
264 // produce two results, to match the available instructions. This exposes
265 // the two-result form to trivial CSE, which is able to combine x/y and x%y
266 // into a single instruction.
268 // Scalar integer multiply-high is also lowered to use two-result
269 // operations, to match the available instructions. However, plain multiply
270 // (low) operations are left as Legal, as there are single-result
271 // instructions for this in x86. Using the two-result multiply instructions
272 // when both high and low results are needed must be arranged by dagcombine.
273 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
275 setOperationAction(ISD::MULHS, VT, Expand);
276 setOperationAction(ISD::MULHU, VT, Expand);
277 setOperationAction(ISD::SDIV, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
282 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
283 setOperationAction(ISD::ADDC, VT, Custom);
284 setOperationAction(ISD::ADDE, VT, Custom);
285 setOperationAction(ISD::SUBC, VT, Custom);
286 setOperationAction(ISD::SUBE, VT, Custom);
289 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
290 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
291 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
296 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
305 if (Subtarget->is64Bit())
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
309 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
310 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
312 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
313 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
314 // is. We should promote the value to 64-bits to solve this.
315 // This is what the CRT headers do - `fmodf` is an inline header
316 // function casting to f64 and calling `fmod`.
317 setOperationAction(ISD::FREM , MVT::f32 , Promote);
319 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->isTarget64BitLP64()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::VAARG , MVT::Other, Custom);
503 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
505 // TargetInfo::CharPtrBuiltinVaList
506 setOperationAction(ISD::VAARG , MVT::Other, Expand);
507 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
510 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
511 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
513 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
515 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
516 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
517 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
519 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
520 // f32 and f64 use SSE.
521 // Set up the FP register classes.
522 addRegisterClass(MVT::f32, &X86::FR32RegClass);
523 addRegisterClass(MVT::f64, &X86::FR64RegClass);
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS , MVT::f64, Custom);
527 setOperationAction(ISD::FABS , MVT::f32, Custom);
529 // Use XORP to simulate FNEG.
530 setOperationAction(ISD::FNEG , MVT::f64, Custom);
531 setOperationAction(ISD::FNEG , MVT::f32, Custom);
533 // Use ANDPD and ORPD to simulate FCOPYSIGN.
534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
537 // Lower this to FGETSIGNx86 plus an AND.
538 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
539 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
541 // We don't support sin/cos/fmod
542 setOperationAction(ISD::FSIN , MVT::f64, Expand);
543 setOperationAction(ISD::FCOS , MVT::f64, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
545 setOperationAction(ISD::FSIN , MVT::f32, Expand);
546 setOperationAction(ISD::FCOS , MVT::f32, Expand);
547 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
549 // Expand FP immediates into loads from the stack, except for the special
551 addLegalFPImmediate(APFloat(+0.0)); // xorpd
552 addLegalFPImmediate(APFloat(+0.0f)); // xorps
553 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
554 // Use SSE for f32, x87 for f64.
555 // Set up the FP register classes.
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
557 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
559 // Use ANDPS to simulate FABS.
560 setOperationAction(ISD::FABS , MVT::f32, Custom);
562 // Use XORP to simulate FNEG.
563 setOperationAction(ISD::FNEG , MVT::f32, Custom);
565 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
567 // Use ANDPS and ORPS to simulate FCOPYSIGN.
568 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
569 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
571 // We don't support sin/cos/fmod
572 setOperationAction(ISD::FSIN , MVT::f32, Expand);
573 setOperationAction(ISD::FCOS , MVT::f32, Expand);
574 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
576 // Special cases we handle for FP constants.
577 addLegalFPImmediate(APFloat(+0.0f)); // xorps
578 addLegalFPImmediate(APFloat(+0.0)); // FLD0
579 addLegalFPImmediate(APFloat(+1.0)); // FLD1
580 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
581 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
583 if (!TM.Options.UnsafeFPMath) {
584 setOperationAction(ISD::FSIN , MVT::f64, Expand);
585 setOperationAction(ISD::FCOS , MVT::f64, Expand);
586 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
588 } else if (!Subtarget->useSoftFloat()) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
592 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
599 if (!TM.Options.UnsafeFPMath) {
600 setOperationAction(ISD::FSIN , MVT::f64, Expand);
601 setOperationAction(ISD::FSIN , MVT::f32, Expand);
602 setOperationAction(ISD::FCOS , MVT::f64, Expand);
603 setOperationAction(ISD::FCOS , MVT::f32, Expand);
604 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
607 addLegalFPImmediate(APFloat(+0.0)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
617 // We don't support FMA.
618 setOperationAction(ISD::FMA, MVT::f64, Expand);
619 setOperationAction(ISD::FMA, MVT::f32, Expand);
621 // Long double always uses X87.
622 if (!Subtarget->useSoftFloat()) {
623 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
624 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
627 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
628 addLegalFPImmediate(TmpFlt); // FLD0
630 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
633 APFloat TmpFlt2(+1.0);
634 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
636 addLegalFPImmediate(TmpFlt2); // FLD1
637 TmpFlt2.changeSign();
638 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
641 if (!TM.Options.UnsafeFPMath) {
642 setOperationAction(ISD::FSIN , MVT::f80, Expand);
643 setOperationAction(ISD::FCOS , MVT::f80, Expand);
644 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
648 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
649 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
650 setOperationAction(ISD::FRINT, MVT::f80, Expand);
651 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
652 setOperationAction(ISD::FMA, MVT::f80, Expand);
655 // Always use a library call for pow.
656 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
657 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
660 setOperationAction(ISD::FLOG, MVT::f80, Expand);
661 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
663 setOperationAction(ISD::FEXP, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
665 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
666 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
668 // First set operation action for all vector types to either promote
669 // (for widening) or expand (for scalarization). Then we will selectively
670 // turn on ones that can be effectively codegen'd.
671 for (MVT VT : MVT::vector_valuetypes()) {
672 setOperationAction(ISD::ADD , VT, Expand);
673 setOperationAction(ISD::SUB , VT, Expand);
674 setOperationAction(ISD::FADD, VT, Expand);
675 setOperationAction(ISD::FNEG, VT, Expand);
676 setOperationAction(ISD::FSUB, VT, Expand);
677 setOperationAction(ISD::MUL , VT, Expand);
678 setOperationAction(ISD::FMUL, VT, Expand);
679 setOperationAction(ISD::SDIV, VT, Expand);
680 setOperationAction(ISD::UDIV, VT, Expand);
681 setOperationAction(ISD::FDIV, VT, Expand);
682 setOperationAction(ISD::SREM, VT, Expand);
683 setOperationAction(ISD::UREM, VT, Expand);
684 setOperationAction(ISD::LOAD, VT, Expand);
685 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
687 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
688 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
689 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::FABS, VT, Expand);
691 setOperationAction(ISD::FSIN, VT, Expand);
692 setOperationAction(ISD::FSINCOS, VT, Expand);
693 setOperationAction(ISD::FCOS, VT, Expand);
694 setOperationAction(ISD::FSINCOS, VT, Expand);
695 setOperationAction(ISD::FREM, VT, Expand);
696 setOperationAction(ISD::FMA, VT, Expand);
697 setOperationAction(ISD::FPOWI, VT, Expand);
698 setOperationAction(ISD::FSQRT, VT, Expand);
699 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
700 setOperationAction(ISD::FFLOOR, VT, Expand);
701 setOperationAction(ISD::FCEIL, VT, Expand);
702 setOperationAction(ISD::FTRUNC, VT, Expand);
703 setOperationAction(ISD::FRINT, VT, Expand);
704 setOperationAction(ISD::FNEARBYINT, VT, Expand);
705 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
706 setOperationAction(ISD::MULHS, VT, Expand);
707 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
708 setOperationAction(ISD::MULHU, VT, Expand);
709 setOperationAction(ISD::SDIVREM, VT, Expand);
710 setOperationAction(ISD::UDIVREM, VT, Expand);
711 setOperationAction(ISD::FPOW, VT, Expand);
712 setOperationAction(ISD::CTPOP, VT, Expand);
713 setOperationAction(ISD::CTTZ, VT, Expand);
714 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
715 setOperationAction(ISD::CTLZ, VT, Expand);
716 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
717 setOperationAction(ISD::SHL, VT, Expand);
718 setOperationAction(ISD::SRA, VT, Expand);
719 setOperationAction(ISD::SRL, VT, Expand);
720 setOperationAction(ISD::ROTL, VT, Expand);
721 setOperationAction(ISD::ROTR, VT, Expand);
722 setOperationAction(ISD::BSWAP, VT, Expand);
723 setOperationAction(ISD::SETCC, VT, Expand);
724 setOperationAction(ISD::FLOG, VT, Expand);
725 setOperationAction(ISD::FLOG2, VT, Expand);
726 setOperationAction(ISD::FLOG10, VT, Expand);
727 setOperationAction(ISD::FEXP, VT, Expand);
728 setOperationAction(ISD::FEXP2, VT, Expand);
729 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
730 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
731 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
732 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
734 setOperationAction(ISD::TRUNCATE, VT, Expand);
735 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
736 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
737 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
738 setOperationAction(ISD::VSELECT, VT, Expand);
739 setOperationAction(ISD::SELECT_CC, VT, Expand);
740 for (MVT InnerVT : MVT::vector_valuetypes()) {
741 setTruncStoreAction(InnerVT, VT, Expand);
743 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
744 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
746 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
747 // types, we have to deal with them whether we ask for Expansion or not.
748 // Setting Expand causes its own optimisation problems though, so leave
750 if (VT.getVectorElementType() == MVT::i1)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
753 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
754 // split/scalarized right now.
755 if (VT.getVectorElementType() == MVT::f16)
756 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
760 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
761 // with -msoft-float, disable use of MMX as well.
762 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
763 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
764 // No operations on x86mmx supported, everything uses intrinsics.
767 // MMX-sized vectors (other than x86mmx) are expected to be expanded
768 // into smaller operations.
769 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
770 setOperationAction(ISD::MULHS, MMXTy, Expand);
771 setOperationAction(ISD::AND, MMXTy, Expand);
772 setOperationAction(ISD::OR, MMXTy, Expand);
773 setOperationAction(ISD::XOR, MMXTy, Expand);
774 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
775 setOperationAction(ISD::SELECT, MMXTy, Expand);
776 setOperationAction(ISD::BITCAST, MMXTy, Expand);
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
781 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
783 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
789 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
790 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
791 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
792 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
793 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
795 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
796 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
799 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
800 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
802 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
803 // registers cannot be used even for integer operations.
804 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
805 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
806 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
807 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
809 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
810 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
811 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
812 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
813 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
814 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
815 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
816 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
817 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
819 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
820 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
821 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
822 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
823 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
824 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
825 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
831 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
833 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
834 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
835 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
836 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
838 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
839 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
840 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
841 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
843 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
854 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
857 // ISD::CTTZ v2i64 - scalarization is faster.
858 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
861 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
863 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
864 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
865 MVT VT = (MVT::SimpleValueType)i;
866 // Do not attempt to custom lower non-power-of-2 vectors
867 if (!isPowerOf2_32(VT.getVectorNumElements()))
869 // Do not attempt to custom lower non-128-bit vectors
870 if (!VT.is128BitVector())
872 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
874 setOperationAction(ISD::VSELECT, VT, Custom);
875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
878 // We support custom legalizing of sext and anyext loads for specific
879 // memory vector types which we can load as a scalar (or sequence of
880 // scalars) and extend in-register to a legal 128-bit vector type. For sext
881 // loads these must work with a single scalar load.
882 for (MVT VT : MVT::integer_vector_valuetypes()) {
883 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
886 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
887 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
888 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
889 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
899 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
908 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
912 // Do not attempt to promote non-128-bit vectors
913 if (!VT.is128BitVector())
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1054 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1059 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1061 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1065 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1075 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1076 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1078 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1088 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1089 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1091 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1092 // even though v8i16 is a legal type.
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1098 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1099 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1102 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1104 for (MVT VT : MVT::fp_vector_valuetypes())
1105 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1111 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1123 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1127 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1130 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1133 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1136 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1146 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1150 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1152 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1153 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1155 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1156 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1157 setOperationAction(ISD::FMA, MVT::f32, Legal);
1158 setOperationAction(ISD::FMA, MVT::f64, Legal);
1161 if (Subtarget->hasInt256()) {
1162 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1163 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1164 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1165 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1167 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1168 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1169 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1170 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1172 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1173 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1174 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1177 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1179 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1180 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1184 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1187 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1190 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1193 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1195 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1196 // when we have a 256bit-wide blend with immediate.
1197 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1199 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1205 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1212 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1214 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1234 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1240 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1243 // In the customized shift lowering, the legal cases in AVX2 will be
1245 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1254 // Custom lower several nodes for 256-bit types.
1255 for (MVT VT : MVT::vector_valuetypes()) {
1256 if (VT.getScalarSizeInBits() >= 32) {
1257 setOperationAction(ISD::MLOAD, VT, Legal);
1258 setOperationAction(ISD::MSTORE, VT, Legal);
1260 // Extract subvector is special because the value type
1261 // (result) is 128-bit but the source is 256-bit wide.
1262 if (VT.is128BitVector()) {
1263 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1265 // Do not attempt to custom lower other non-256-bit vectors
1266 if (!VT.is256BitVector())
1269 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1270 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1271 setOperationAction(ISD::VSELECT, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 if (Subtarget->hasInt256())
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 for (MVT VT : MVT::fp_vector_valuetypes())
1314 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1316 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1317 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1318 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1319 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1320 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1321 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1322 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1324 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1325 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1326 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1327 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1329 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1330 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1331 setOperationAction(ISD::XOR, MVT::i1, Legal);
1332 setOperationAction(ISD::OR, MVT::i1, Legal);
1333 setOperationAction(ISD::AND, MVT::i1, Legal);
1334 setOperationAction(ISD::SUB, MVT::i1, Custom);
1335 setOperationAction(ISD::ADD, MVT::i1, Custom);
1336 setOperationAction(ISD::MUL, MVT::i1, Custom);
1337 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1339 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1340 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1341 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1343 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1345 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1347 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1350 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1356 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1357 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1359 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1360 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1361 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1362 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1363 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1364 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1365 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1366 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1367 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1368 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1371 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1372 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1373 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1374 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1376 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1377 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1379 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1380 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1381 if (Subtarget->hasVLX()){
1382 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1383 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1384 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1385 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1386 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1388 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1389 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1390 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1391 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1392 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1394 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1396 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1397 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1398 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1399 if (Subtarget->hasDQI()) {
1400 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1401 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1407 if (Subtarget->hasVLX()) {
1408 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1418 if (Subtarget->hasVLX()) {
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1422 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1425 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1426 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1440 if (Subtarget->hasDQI()) {
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1444 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1448 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1449 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1450 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1451 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1452 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1453 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1461 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1464 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1466 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1468 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1470 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1478 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1479 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1480 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1481 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1482 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1483 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1484 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1485 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1487 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1488 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1490 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1491 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1493 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1495 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1498 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1499 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1501 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1502 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1507 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1511 if (Subtarget->hasCDI()) {
1512 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1513 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1517 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1518 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1520 if (Subtarget->hasVLX() && Subtarget->hasCDI()) {
1521 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1522 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1523 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1524 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1531 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1532 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1535 if (Subtarget->hasDQI()) {
1536 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1537 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1538 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1540 // Custom lower several nodes.
1541 for (MVT VT : MVT::vector_valuetypes()) {
1542 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1544 setOperationAction(ISD::AND, VT, Legal);
1545 setOperationAction(ISD::OR, VT, Legal);
1546 setOperationAction(ISD::XOR, VT, Legal);
1548 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1549 setOperationAction(ISD::MGATHER, VT, Custom);
1550 setOperationAction(ISD::MSCATTER, VT, Custom);
1552 // Extract subvector is special because the value type
1553 // (result) is 256/128-bit but the source is 512-bit wide.
1554 if (VT.is128BitVector() || VT.is256BitVector()) {
1555 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1557 if (VT.getVectorElementType() == MVT::i1)
1558 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1560 // Do not attempt to custom lower other non-512-bit vectors
1561 if (!VT.is512BitVector())
1564 if (EltSize >= 32) {
1565 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1566 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1567 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1568 setOperationAction(ISD::VSELECT, VT, Legal);
1569 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1570 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1571 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1572 setOperationAction(ISD::MLOAD, VT, Legal);
1573 setOperationAction(ISD::MSTORE, VT, Legal);
1576 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1577 MVT VT = (MVT::SimpleValueType)i;
1579 // Do not attempt to promote non-512-bit vectors.
1580 if (!VT.is512BitVector())
1583 setOperationAction(ISD::SELECT, VT, Promote);
1584 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1588 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1589 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1590 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1592 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1593 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1595 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1596 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1597 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1598 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1599 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1600 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1601 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1602 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1603 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1604 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1605 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1606 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1607 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1608 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1609 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1610 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1611 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1612 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1613 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1614 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1615 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1616 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1617 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1618 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1619 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1620 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1621 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1622 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1623 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1624 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1625 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1626 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1627 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1628 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1629 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1630 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1631 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1632 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1633 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1635 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1636 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1637 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1638 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1639 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1640 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1641 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1642 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1644 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1645 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1646 if (Subtarget->hasVLX())
1647 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1649 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1650 const MVT VT = (MVT::SimpleValueType)i;
1652 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1654 // Do not attempt to promote non-512-bit vectors.
1655 if (!VT.is512BitVector())
1659 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1660 setOperationAction(ISD::VSELECT, VT, Legal);
1665 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1666 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1667 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1669 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1670 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1671 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1672 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1673 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1674 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1675 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1676 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1677 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1678 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1679 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1680 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1682 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1683 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1684 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1685 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1686 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1687 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1688 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1689 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1691 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1692 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1693 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1694 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1695 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1696 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1697 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1698 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1701 // We want to custom lower some of our intrinsics.
1702 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1703 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1704 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1705 if (!Subtarget->is64Bit())
1706 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1708 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1709 // handle type legalization for these operations here.
1711 // FIXME: We really should do custom legalization for addition and
1712 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1713 // than generic legalization for 64-bit multiplication-with-overflow, though.
1714 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1715 // Add/Sub/Mul with overflow operations are custom lowered.
1717 setOperationAction(ISD::SADDO, VT, Custom);
1718 setOperationAction(ISD::UADDO, VT, Custom);
1719 setOperationAction(ISD::SSUBO, VT, Custom);
1720 setOperationAction(ISD::USUBO, VT, Custom);
1721 setOperationAction(ISD::SMULO, VT, Custom);
1722 setOperationAction(ISD::UMULO, VT, Custom);
1725 if (!Subtarget->is64Bit()) {
1726 // These libcalls are not available in 32-bit.
1727 setLibcallName(RTLIB::SHL_I128, nullptr);
1728 setLibcallName(RTLIB::SRL_I128, nullptr);
1729 setLibcallName(RTLIB::SRA_I128, nullptr);
1732 // Combine sin / cos into one node or libcall if possible.
1733 if (Subtarget->hasSinCos()) {
1734 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1735 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1736 if (Subtarget->isTargetDarwin()) {
1737 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1738 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1739 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1740 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1744 if (Subtarget->isTargetWin64()) {
1745 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1746 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1747 setOperationAction(ISD::SREM, MVT::i128, Custom);
1748 setOperationAction(ISD::UREM, MVT::i128, Custom);
1749 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1750 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1753 // We have target-specific dag combine patterns for the following nodes:
1754 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1755 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1756 setTargetDAGCombine(ISD::BITCAST);
1757 setTargetDAGCombine(ISD::VSELECT);
1758 setTargetDAGCombine(ISD::SELECT);
1759 setTargetDAGCombine(ISD::SHL);
1760 setTargetDAGCombine(ISD::SRA);
1761 setTargetDAGCombine(ISD::SRL);
1762 setTargetDAGCombine(ISD::OR);
1763 setTargetDAGCombine(ISD::AND);
1764 setTargetDAGCombine(ISD::ADD);
1765 setTargetDAGCombine(ISD::FADD);
1766 setTargetDAGCombine(ISD::FSUB);
1767 setTargetDAGCombine(ISD::FMA);
1768 setTargetDAGCombine(ISD::SUB);
1769 setTargetDAGCombine(ISD::LOAD);
1770 setTargetDAGCombine(ISD::MLOAD);
1771 setTargetDAGCombine(ISD::STORE);
1772 setTargetDAGCombine(ISD::MSTORE);
1773 setTargetDAGCombine(ISD::ZERO_EXTEND);
1774 setTargetDAGCombine(ISD::ANY_EXTEND);
1775 setTargetDAGCombine(ISD::SIGN_EXTEND);
1776 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1777 setTargetDAGCombine(ISD::SINT_TO_FP);
1778 setTargetDAGCombine(ISD::UINT_TO_FP);
1779 setTargetDAGCombine(ISD::SETCC);
1780 setTargetDAGCombine(ISD::BUILD_VECTOR);
1781 setTargetDAGCombine(ISD::MUL);
1782 setTargetDAGCombine(ISD::XOR);
1784 computeRegisterProperties(Subtarget->getRegisterInfo());
1786 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1787 MaxStoresPerMemsetOptSize = 8;
1788 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1789 MaxStoresPerMemcpyOptSize = 4;
1790 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1791 MaxStoresPerMemmoveOptSize = 4;
1792 setPrefLoopAlignment(4); // 2^4 bytes.
1794 // A predictable cmov does not hurt on an in-order CPU.
1795 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1796 PredictableSelectIsExpensive = !Subtarget->isAtom();
1797 EnableExtLdPromotion = true;
1798 setPrefFunctionAlignment(4); // 2^4 bytes.
1800 verifyIntrinsicTables();
1803 // This has so far only been implemented for 64-bit MachO.
1804 bool X86TargetLowering::useLoadStackGuardNode() const {
1805 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1808 TargetLoweringBase::LegalizeTypeAction
1809 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1810 if (ExperimentalVectorWideningLegalization &&
1811 VT.getVectorNumElements() != 1 &&
1812 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1813 return TypeWidenVector;
1815 return TargetLoweringBase::getPreferredVectorAction(VT);
1818 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1821 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1823 const unsigned NumElts = VT.getVectorNumElements();
1824 const EVT EltVT = VT.getVectorElementType();
1825 if (VT.is512BitVector()) {
1826 if (Subtarget->hasAVX512())
1827 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1828 EltVT == MVT::f32 || EltVT == MVT::f64)
1830 case 8: return MVT::v8i1;
1831 case 16: return MVT::v16i1;
1833 if (Subtarget->hasBWI())
1834 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1836 case 32: return MVT::v32i1;
1837 case 64: return MVT::v64i1;
1841 if (VT.is256BitVector() || VT.is128BitVector()) {
1842 if (Subtarget->hasVLX())
1843 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1844 EltVT == MVT::f32 || EltVT == MVT::f64)
1846 case 2: return MVT::v2i1;
1847 case 4: return MVT::v4i1;
1848 case 8: return MVT::v8i1;
1850 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1851 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1853 case 8: return MVT::v8i1;
1854 case 16: return MVT::v16i1;
1855 case 32: return MVT::v32i1;
1859 return VT.changeVectorElementTypeToInteger();
1862 /// Helper for getByValTypeAlignment to determine
1863 /// the desired ByVal argument alignment.
1864 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1867 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1868 if (VTy->getBitWidth() == 128)
1870 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1871 unsigned EltAlign = 0;
1872 getMaxByValAlign(ATy->getElementType(), EltAlign);
1873 if (EltAlign > MaxAlign)
1874 MaxAlign = EltAlign;
1875 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1876 for (auto *EltTy : STy->elements()) {
1877 unsigned EltAlign = 0;
1878 getMaxByValAlign(EltTy, EltAlign);
1879 if (EltAlign > MaxAlign)
1880 MaxAlign = EltAlign;
1887 /// Return the desired alignment for ByVal aggregate
1888 /// function arguments in the caller parameter area. For X86, aggregates
1889 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1890 /// are at 4-byte boundaries.
1891 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1892 const DataLayout &DL) const {
1893 if (Subtarget->is64Bit()) {
1894 // Max of 8 and alignment of type.
1895 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1902 if (Subtarget->hasSSE1())
1903 getMaxByValAlign(Ty, Align);
1907 /// Returns the target specific optimal type for load
1908 /// and store operations as a result of memset, memcpy, and memmove
1909 /// lowering. If DstAlign is zero that means it's safe to destination
1910 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1911 /// means there isn't a need to check it against alignment requirement,
1912 /// probably because the source does not need to be loaded. If 'IsMemset' is
1913 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1914 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1915 /// source is constant so it does not need to be loaded.
1916 /// It returns EVT::Other if the type should be determined using generic
1917 /// target-independent logic.
1919 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1920 unsigned DstAlign, unsigned SrcAlign,
1921 bool IsMemset, bool ZeroMemset,
1923 MachineFunction &MF) const {
1924 const Function *F = MF.getFunction();
1925 if ((!IsMemset || ZeroMemset) &&
1926 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1928 (!Subtarget->isUnalignedMem16Slow() ||
1929 ((DstAlign == 0 || DstAlign >= 16) &&
1930 (SrcAlign == 0 || SrcAlign >= 16)))) {
1932 // FIXME: Check if unaligned 32-byte accesses are slow.
1933 if (Subtarget->hasInt256())
1935 if (Subtarget->hasFp256())
1938 if (Subtarget->hasSSE2())
1940 if (Subtarget->hasSSE1())
1942 } else if (!MemcpyStrSrc && Size >= 8 &&
1943 !Subtarget->is64Bit() &&
1944 Subtarget->hasSSE2()) {
1945 // Do not use f64 to lower memcpy if source is string constant. It's
1946 // better to use i32 to avoid the loads.
1950 // This is a compromise. If we reach here, unaligned accesses may be slow on
1951 // this target. However, creating smaller, aligned accesses could be even
1952 // slower and would certainly be a lot more code.
1953 if (Subtarget->is64Bit() && Size >= 8)
1958 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1960 return X86ScalarSSEf32;
1961 else if (VT == MVT::f64)
1962 return X86ScalarSSEf64;
1967 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1972 switch (VT.getSizeInBits()) {
1974 // 8-byte and under are always assumed to be fast.
1978 *Fast = !Subtarget->isUnalignedMem16Slow();
1981 *Fast = !Subtarget->isUnalignedMem32Slow();
1983 // TODO: What about AVX-512 (512-bit) accesses?
1986 // Misaligned accesses of any size are always allowed.
1990 /// Return the entry encoding for a jump table in the
1991 /// current function. The returned value is a member of the
1992 /// MachineJumpTableInfo::JTEntryKind enum.
1993 unsigned X86TargetLowering::getJumpTableEncoding() const {
1994 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1996 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1997 Subtarget->isPICStyleGOT())
1998 return MachineJumpTableInfo::EK_Custom32;
2000 // Otherwise, use the normal jump table encoding heuristics.
2001 return TargetLowering::getJumpTableEncoding();
2004 bool X86TargetLowering::useSoftFloat() const {
2005 return Subtarget->useSoftFloat();
2009 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2010 const MachineBasicBlock *MBB,
2011 unsigned uid,MCContext &Ctx) const{
2012 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2013 Subtarget->isPICStyleGOT());
2014 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2016 return MCSymbolRefExpr::create(MBB->getSymbol(),
2017 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2020 /// Returns relocation base for the given PIC jumptable.
2021 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2022 SelectionDAG &DAG) const {
2023 if (!Subtarget->is64Bit())
2024 // This doesn't have SDLoc associated with it, but is not really the
2025 // same as a Register.
2026 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2027 getPointerTy(DAG.getDataLayout()));
2031 /// This returns the relocation base for the given PIC jumptable,
2032 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2033 const MCExpr *X86TargetLowering::
2034 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2035 MCContext &Ctx) const {
2036 // X86-64 uses RIP relative addressing based on the jump table label.
2037 if (Subtarget->isPICStyleRIPRel())
2038 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2040 // Otherwise, the reference is relative to the PIC base.
2041 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2044 std::pair<const TargetRegisterClass *, uint8_t>
2045 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2047 const TargetRegisterClass *RRC = nullptr;
2049 switch (VT.SimpleTy) {
2051 return TargetLowering::findRepresentativeClass(TRI, VT);
2052 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2053 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2056 RRC = &X86::VR64RegClass;
2058 case MVT::f32: case MVT::f64:
2059 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2060 case MVT::v4f32: case MVT::v2f64:
2061 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2063 RRC = &X86::VR128RegClass;
2066 return std::make_pair(RRC, Cost);
2069 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2070 unsigned &Offset) const {
2071 if (!Subtarget->isTargetLinux())
2074 if (Subtarget->is64Bit()) {
2075 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2077 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2089 /// Android provides a fixed TLS slot for the SafeStack pointer.
2090 /// See the definition of TLS_SLOT_SAFESTACK in
2091 /// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2092 bool X86TargetLowering::getSafeStackPointerLocation(unsigned &AddressSpace,
2093 unsigned &Offset) const {
2094 if (!Subtarget->isTargetAndroid())
2097 if (Subtarget->is64Bit()) {
2098 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2100 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2112 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2113 unsigned DestAS) const {
2114 assert(SrcAS != DestAS && "Expected different address spaces!");
2116 return SrcAS < 256 && DestAS < 256;
2119 //===----------------------------------------------------------------------===//
2120 // Return Value Calling Convention Implementation
2121 //===----------------------------------------------------------------------===//
2123 #include "X86GenCallingConv.inc"
2125 bool X86TargetLowering::CanLowerReturn(
2126 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2127 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2128 SmallVector<CCValAssign, 16> RVLocs;
2129 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2130 return CCInfo.CheckReturn(Outs, RetCC_X86);
2133 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2134 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2139 X86TargetLowering::LowerReturn(SDValue Chain,
2140 CallingConv::ID CallConv, bool isVarArg,
2141 const SmallVectorImpl<ISD::OutputArg> &Outs,
2142 const SmallVectorImpl<SDValue> &OutVals,
2143 SDLoc dl, SelectionDAG &DAG) const {
2144 MachineFunction &MF = DAG.getMachineFunction();
2145 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2147 SmallVector<CCValAssign, 16> RVLocs;
2148 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2149 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2152 SmallVector<SDValue, 6> RetOps;
2153 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2154 // Operand #1 = Bytes To Pop
2155 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2158 // Copy the result values into the output registers.
2159 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2160 CCValAssign &VA = RVLocs[i];
2161 assert(VA.isRegLoc() && "Can only return in registers!");
2162 SDValue ValToCopy = OutVals[i];
2163 EVT ValVT = ValToCopy.getValueType();
2165 // Promote values to the appropriate types.
2166 if (VA.getLocInfo() == CCValAssign::SExt)
2167 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2168 else if (VA.getLocInfo() == CCValAssign::ZExt)
2169 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2170 else if (VA.getLocInfo() == CCValAssign::AExt) {
2171 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2172 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2174 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2176 else if (VA.getLocInfo() == CCValAssign::BCvt)
2177 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2179 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2180 "Unexpected FP-extend for return value.");
2182 // If this is x86-64, and we disabled SSE, we can't return FP values,
2183 // or SSE or MMX vectors.
2184 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2185 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2186 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2187 report_fatal_error("SSE register return with SSE disabled");
2189 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2190 // llvm-gcc has never done it right and no one has noticed, so this
2191 // should be OK for now.
2192 if (ValVT == MVT::f64 &&
2193 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2194 report_fatal_error("SSE2 register return with SSE2 disabled");
2196 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2197 // the RET instruction and handled by the FP Stackifier.
2198 if (VA.getLocReg() == X86::FP0 ||
2199 VA.getLocReg() == X86::FP1) {
2200 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2201 // change the value to the FP stack register class.
2202 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2203 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2204 RetOps.push_back(ValToCopy);
2205 // Don't emit a copytoreg.
2209 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2210 // which is returned in RAX / RDX.
2211 if (Subtarget->is64Bit()) {
2212 if (ValVT == MVT::x86mmx) {
2213 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2214 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2215 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2217 // If we don't have SSE2 available, convert to v4f32 so the generated
2218 // register is legal.
2219 if (!Subtarget->hasSSE2())
2220 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2225 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2226 Flag = Chain.getValue(1);
2227 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2230 // All x86 ABIs require that for returning structs by value we copy
2231 // the sret argument into %rax/%eax (depending on ABI) for the return.
2232 // We saved the argument into a virtual register in the entry block,
2233 // so now we copy the value out and into %rax/%eax.
2235 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2236 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2237 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2238 // either case FuncInfo->setSRetReturnReg() will have been called.
2239 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2240 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2241 getPointerTy(MF.getDataLayout()));
2244 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2245 X86::RAX : X86::EAX;
2246 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2247 Flag = Chain.getValue(1);
2249 // RAX/EAX now acts like a return value.
2251 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2254 RetOps[0] = Chain; // Update chain.
2256 // Add the flag if we have it.
2258 RetOps.push_back(Flag);
2260 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2263 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2264 if (N->getNumValues() != 1)
2266 if (!N->hasNUsesOfValue(1, 0))
2269 SDValue TCChain = Chain;
2270 SDNode *Copy = *N->use_begin();
2271 if (Copy->getOpcode() == ISD::CopyToReg) {
2272 // If the copy has a glue operand, we conservatively assume it isn't safe to
2273 // perform a tail call.
2274 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2276 TCChain = Copy->getOperand(0);
2277 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2280 bool HasRet = false;
2281 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2283 if (UI->getOpcode() != X86ISD::RET_FLAG)
2285 // If we are returning more than one value, we can definitely
2286 // not make a tail call see PR19530
2287 if (UI->getNumOperands() > 4)
2289 if (UI->getNumOperands() == 4 &&
2290 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2303 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2304 ISD::NodeType ExtendKind) const {
2306 // TODO: Is this also valid on 32-bit?
2307 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2308 ReturnMVT = MVT::i8;
2310 ReturnMVT = MVT::i32;
2312 EVT MinVT = getRegisterType(Context, ReturnMVT);
2313 return VT.bitsLT(MinVT) ? MinVT : VT;
2316 /// Lower the result values of a call into the
2317 /// appropriate copies out of appropriate physical registers.
2320 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2321 CallingConv::ID CallConv, bool isVarArg,
2322 const SmallVectorImpl<ISD::InputArg> &Ins,
2323 SDLoc dl, SelectionDAG &DAG,
2324 SmallVectorImpl<SDValue> &InVals) const {
2326 // Assign locations to each value returned by this call.
2327 SmallVector<CCValAssign, 16> RVLocs;
2328 bool Is64Bit = Subtarget->is64Bit();
2329 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2331 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2333 // Copy all of the result registers out of their specified physreg.
2334 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2335 CCValAssign &VA = RVLocs[i];
2336 EVT CopyVT = VA.getLocVT();
2338 // If this is x86-64, and we disabled SSE, we can't return FP values
2339 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2340 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2341 report_fatal_error("SSE register return with SSE disabled");
2344 // If we prefer to use the value in xmm registers, copy it out as f80 and
2345 // use a truncate to move it from fp stack reg to xmm reg.
2346 bool RoundAfterCopy = false;
2347 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2348 isScalarFPTypeInSSEReg(VA.getValVT())) {
2350 RoundAfterCopy = (CopyVT != VA.getLocVT());
2353 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2354 CopyVT, InFlag).getValue(1);
2355 SDValue Val = Chain.getValue(0);
2358 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2359 // This truncation won't change the value.
2360 DAG.getIntPtrConstant(1, dl));
2362 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2363 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2365 InFlag = Chain.getValue(2);
2366 InVals.push_back(Val);
2372 //===----------------------------------------------------------------------===//
2373 // C & StdCall & Fast Calling Convention implementation
2374 //===----------------------------------------------------------------------===//
2375 // StdCall calling convention seems to be standard for many Windows' API
2376 // routines and around. It differs from C calling convention just a little:
2377 // callee should clean up the stack, not caller. Symbols should be also
2378 // decorated in some fancy way :) It doesn't support any vector arguments.
2379 // For info on fast calling convention see Fast Calling Convention (tail call)
2380 // implementation LowerX86_32FastCCCallTo.
2382 /// CallIsStructReturn - Determines whether a call uses struct return
2384 enum StructReturnType {
2389 static StructReturnType
2390 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2392 return NotStructReturn;
2394 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2395 if (!Flags.isSRet())
2396 return NotStructReturn;
2397 if (Flags.isInReg())
2398 return RegStructReturn;
2399 return StackStructReturn;
2402 /// Determines whether a function uses struct return semantics.
2403 static StructReturnType
2404 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2406 return NotStructReturn;
2408 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2409 if (!Flags.isSRet())
2410 return NotStructReturn;
2411 if (Flags.isInReg())
2412 return RegStructReturn;
2413 return StackStructReturn;
2416 /// Make a copy of an aggregate at address specified by "Src" to address
2417 /// "Dst" with size and alignment information specified by the specific
2418 /// parameter attribute. The copy will be passed as a byval function parameter.
2420 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2421 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2423 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2425 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2426 /*isVolatile*/false, /*AlwaysInline=*/true,
2427 /*isTailCall*/false,
2428 MachinePointerInfo(), MachinePointerInfo());
2431 /// Return true if the calling convention is one that
2432 /// supports tail call optimization.
2433 static bool IsTailCallConvention(CallingConv::ID CC) {
2434 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2435 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2438 /// \brief Return true if the calling convention is a C calling convention.
2439 static bool IsCCallConvention(CallingConv::ID CC) {
2440 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2441 CC == CallingConv::X86_64_SysV);
2444 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2446 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2447 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2451 CallingConv::ID CalleeCC = CS.getCallingConv();
2452 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2458 /// Return true if the function is being made into
2459 /// a tailcall target by changing its ABI.
2460 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2461 bool GuaranteedTailCallOpt) {
2462 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2466 X86TargetLowering::LowerMemArgument(SDValue Chain,
2467 CallingConv::ID CallConv,
2468 const SmallVectorImpl<ISD::InputArg> &Ins,
2469 SDLoc dl, SelectionDAG &DAG,
2470 const CCValAssign &VA,
2471 MachineFrameInfo *MFI,
2473 // Create the nodes corresponding to a load from this parameter slot.
2474 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2475 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2476 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2477 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2480 // If value is passed by pointer we have address passed instead of the value
2482 bool ExtendedInMem = VA.isExtInLoc() &&
2483 VA.getValVT().getScalarType() == MVT::i1;
2485 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2486 ValVT = VA.getLocVT();
2488 ValVT = VA.getValVT();
2490 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2491 // changed with more analysis.
2492 // In case of tail call optimization mark all arguments mutable. Since they
2493 // could be overwritten by lowering of arguments in case of a tail call.
2494 if (Flags.isByVal()) {
2495 unsigned Bytes = Flags.getByValSize();
2496 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2497 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2498 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2500 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2501 VA.getLocMemOffset(), isImmutable);
2502 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2503 SDValue Val = DAG.getLoad(
2504 ValVT, dl, Chain, FIN,
2505 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2507 return ExtendedInMem ?
2508 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2512 // FIXME: Get this from tablegen.
2513 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2514 const X86Subtarget *Subtarget) {
2515 assert(Subtarget->is64Bit());
2517 if (Subtarget->isCallingConvWin64(CallConv)) {
2518 static const MCPhysReg GPR64ArgRegsWin64[] = {
2519 X86::RCX, X86::RDX, X86::R8, X86::R9
2521 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2524 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2525 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2527 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2530 // FIXME: Get this from tablegen.
2531 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2532 CallingConv::ID CallConv,
2533 const X86Subtarget *Subtarget) {
2534 assert(Subtarget->is64Bit());
2535 if (Subtarget->isCallingConvWin64(CallConv)) {
2536 // The XMM registers which might contain var arg parameters are shadowed
2537 // in their paired GPR. So we only need to save the GPR to their home
2539 // TODO: __vectorcall will change this.
2543 const Function *Fn = MF.getFunction();
2544 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2545 bool isSoftFloat = Subtarget->useSoftFloat();
2546 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2547 "SSE register cannot be used when SSE is disabled!");
2548 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2549 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2553 static const MCPhysReg XMMArgRegs64Bit[] = {
2554 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2555 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2557 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2560 SDValue X86TargetLowering::LowerFormalArguments(
2561 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2562 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2563 SmallVectorImpl<SDValue> &InVals) const {
2564 MachineFunction &MF = DAG.getMachineFunction();
2565 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2566 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2568 const Function* Fn = MF.getFunction();
2569 if (Fn->hasExternalLinkage() &&
2570 Subtarget->isTargetCygMing() &&
2571 Fn->getName() == "main")
2572 FuncInfo->setForceFramePointer(true);
2574 MachineFrameInfo *MFI = MF.getFrameInfo();
2575 bool Is64Bit = Subtarget->is64Bit();
2576 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2578 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2579 "Var args not supported with calling convention fastcc, ghc or hipe");
2581 // Assign locations to all of the incoming arguments.
2582 SmallVector<CCValAssign, 16> ArgLocs;
2583 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2585 // Allocate shadow area for Win64
2587 CCInfo.AllocateStack(32, 8);
2589 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2591 unsigned LastVal = ~0U;
2593 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2594 CCValAssign &VA = ArgLocs[i];
2595 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2597 assert(VA.getValNo() != LastVal &&
2598 "Don't support value assigned to multiple locs yet");
2600 LastVal = VA.getValNo();
2602 if (VA.isRegLoc()) {
2603 EVT RegVT = VA.getLocVT();
2604 const TargetRegisterClass *RC;
2605 if (RegVT == MVT::i32)
2606 RC = &X86::GR32RegClass;
2607 else if (Is64Bit && RegVT == MVT::i64)
2608 RC = &X86::GR64RegClass;
2609 else if (RegVT == MVT::f32)
2610 RC = &X86::FR32RegClass;
2611 else if (RegVT == MVT::f64)
2612 RC = &X86::FR64RegClass;
2613 else if (RegVT.is512BitVector())
2614 RC = &X86::VR512RegClass;
2615 else if (RegVT.is256BitVector())
2616 RC = &X86::VR256RegClass;
2617 else if (RegVT.is128BitVector())
2618 RC = &X86::VR128RegClass;
2619 else if (RegVT == MVT::x86mmx)
2620 RC = &X86::VR64RegClass;
2621 else if (RegVT == MVT::i1)
2622 RC = &X86::VK1RegClass;
2623 else if (RegVT == MVT::v8i1)
2624 RC = &X86::VK8RegClass;
2625 else if (RegVT == MVT::v16i1)
2626 RC = &X86::VK16RegClass;
2627 else if (RegVT == MVT::v32i1)
2628 RC = &X86::VK32RegClass;
2629 else if (RegVT == MVT::v64i1)
2630 RC = &X86::VK64RegClass;
2632 llvm_unreachable("Unknown argument type!");
2634 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2635 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2637 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2638 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2640 if (VA.getLocInfo() == CCValAssign::SExt)
2641 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2642 DAG.getValueType(VA.getValVT()));
2643 else if (VA.getLocInfo() == CCValAssign::ZExt)
2644 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2645 DAG.getValueType(VA.getValVT()));
2646 else if (VA.getLocInfo() == CCValAssign::BCvt)
2647 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2649 if (VA.isExtInLoc()) {
2650 // Handle MMX values passed in XMM regs.
2651 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2652 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2654 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2657 assert(VA.isMemLoc());
2658 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2661 // If value is passed via pointer - do a load.
2662 if (VA.getLocInfo() == CCValAssign::Indirect)
2663 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2664 MachinePointerInfo(), false, false, false, 0);
2666 InVals.push_back(ArgValue);
2669 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2670 // All x86 ABIs require that for returning structs by value we copy the
2671 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2672 // the argument into a virtual register so that we can access it from the
2674 if (Ins[i].Flags.isSRet()) {
2675 unsigned Reg = FuncInfo->getSRetReturnReg();
2677 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2678 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2679 FuncInfo->setSRetReturnReg(Reg);
2681 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2682 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2687 unsigned StackSize = CCInfo.getNextStackOffset();
2688 // Align stack specially for tail calls.
2689 if (FuncIsMadeTailCallSafe(CallConv,
2690 MF.getTarget().Options.GuaranteedTailCallOpt))
2691 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2693 // If the function takes variable number of arguments, make a frame index for
2694 // the start of the first vararg value... for expansion of llvm.va_start. We
2695 // can skip this if there are no va_start calls.
2696 if (MFI->hasVAStart() &&
2697 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2698 CallConv != CallingConv::X86_ThisCall))) {
2699 FuncInfo->setVarArgsFrameIndex(
2700 MFI->CreateFixedObject(1, StackSize, true));
2703 MachineModuleInfo &MMI = MF.getMMI();
2705 // Figure out if XMM registers are in use.
2706 assert(!(Subtarget->useSoftFloat() &&
2707 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2708 "SSE register cannot be used when SSE is disabled!");
2710 // 64-bit calling conventions support varargs and register parameters, so we
2711 // have to do extra work to spill them in the prologue.
2712 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2713 // Find the first unallocated argument registers.
2714 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2715 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2716 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2717 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2718 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2719 "SSE register cannot be used when SSE is disabled!");
2721 // Gather all the live in physical registers.
2722 SmallVector<SDValue, 6> LiveGPRs;
2723 SmallVector<SDValue, 8> LiveXMMRegs;
2725 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2726 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2728 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2730 if (!ArgXMMs.empty()) {
2731 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2732 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2733 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2734 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2735 LiveXMMRegs.push_back(
2736 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2741 // Get to the caller-allocated home save location. Add 8 to account
2742 // for the return address.
2743 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2744 FuncInfo->setRegSaveFrameIndex(
2745 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2746 // Fixup to set vararg frame on shadow area (4 x i64).
2748 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2750 // For X86-64, if there are vararg parameters that are passed via
2751 // registers, then we must store them to their spots on the stack so
2752 // they may be loaded by deferencing the result of va_next.
2753 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2754 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2755 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2756 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2759 // Store the integer parameter registers.
2760 SmallVector<SDValue, 8> MemOps;
2761 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2762 getPointerTy(DAG.getDataLayout()));
2763 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2764 for (SDValue Val : LiveGPRs) {
2765 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2766 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2768 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2769 MachinePointerInfo::getFixedStack(
2770 DAG.getMachineFunction(),
2771 FuncInfo->getRegSaveFrameIndex(), Offset),
2773 MemOps.push_back(Store);
2777 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2778 // Now store the XMM (fp + vector) parameter registers.
2779 SmallVector<SDValue, 12> SaveXMMOps;
2780 SaveXMMOps.push_back(Chain);
2781 SaveXMMOps.push_back(ALVal);
2782 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2783 FuncInfo->getRegSaveFrameIndex(), dl));
2784 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2785 FuncInfo->getVarArgsFPOffset(), dl));
2786 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2788 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2789 MVT::Other, SaveXMMOps));
2792 if (!MemOps.empty())
2793 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2796 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2797 // Find the largest legal vector type.
2798 MVT VecVT = MVT::Other;
2799 // FIXME: Only some x86_32 calling conventions support AVX512.
2800 if (Subtarget->hasAVX512() &&
2801 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2802 CallConv == CallingConv::Intel_OCL_BI)))
2803 VecVT = MVT::v16f32;
2804 else if (Subtarget->hasAVX())
2806 else if (Subtarget->hasSSE2())
2809 // We forward some GPRs and some vector types.
2810 SmallVector<MVT, 2> RegParmTypes;
2811 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2812 RegParmTypes.push_back(IntVT);
2813 if (VecVT != MVT::Other)
2814 RegParmTypes.push_back(VecVT);
2816 // Compute the set of forwarded registers. The rest are scratch.
2817 SmallVectorImpl<ForwardedRegister> &Forwards =
2818 FuncInfo->getForwardedMustTailRegParms();
2819 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2821 // Conservatively forward AL on x86_64, since it might be used for varargs.
2822 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2823 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2824 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2827 // Copy all forwards from physical to virtual registers.
2828 for (ForwardedRegister &F : Forwards) {
2829 // FIXME: Can we use a less constrained schedule?
2830 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2831 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2832 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2836 // Some CCs need callee pop.
2837 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2838 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2839 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2841 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2842 // If this is an sret function, the return should pop the hidden pointer.
2843 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2844 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2845 argsAreStructReturn(Ins) == StackStructReturn)
2846 FuncInfo->setBytesToPopOnReturn(4);
2850 // RegSaveFrameIndex is X86-64 only.
2851 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2852 if (CallConv == CallingConv::X86_FastCall ||
2853 CallConv == CallingConv::X86_ThisCall)
2854 // fastcc functions can't have varargs.
2855 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2858 FuncInfo->setArgumentStackSize(StackSize);
2860 if (MMI.hasWinEHFuncInfo(Fn)) {
2862 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2863 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2864 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2865 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2866 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2867 MachinePointerInfo::getFixedStack(
2868 DAG.getMachineFunction(), UnwindHelpFI),
2869 /*isVolatile=*/true,
2870 /*isNonTemporal=*/false, /*Alignment=*/0);
2872 // Functions using Win32 EH are considered to have opaque SP adjustments
2873 // to force local variables to be addressed from the frame or base
2875 MFI->setHasOpaqueSPAdjustment(true);
2883 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2884 SDValue StackPtr, SDValue Arg,
2885 SDLoc dl, SelectionDAG &DAG,
2886 const CCValAssign &VA,
2887 ISD::ArgFlagsTy Flags) const {
2888 unsigned LocMemOffset = VA.getLocMemOffset();
2889 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2890 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2892 if (Flags.isByVal())
2893 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2895 return DAG.getStore(
2896 Chain, dl, Arg, PtrOff,
2897 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2901 /// Emit a load of return address if tail call
2902 /// optimization is performed and it is required.
2904 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2905 SDValue &OutRetAddr, SDValue Chain,
2906 bool IsTailCall, bool Is64Bit,
2907 int FPDiff, SDLoc dl) const {
2908 // Adjust the Return address stack slot.
2909 EVT VT = getPointerTy(DAG.getDataLayout());
2910 OutRetAddr = getReturnAddressFrameIndex(DAG);
2912 // Load the "old" Return address.
2913 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2914 false, false, false, 0);
2915 return SDValue(OutRetAddr.getNode(), 1);
2918 /// Emit a store of the return address if tail call
2919 /// optimization is performed and it is required (FPDiff!=0).
2920 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2921 SDValue Chain, SDValue RetAddrFrIdx,
2922 EVT PtrVT, unsigned SlotSize,
2923 int FPDiff, SDLoc dl) {
2924 // Store the return address to the appropriate stack slot.
2925 if (!FPDiff) return Chain;
2926 // Calculate the new stack slot for the return address.
2927 int NewReturnAddrFI =
2928 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2930 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2931 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2932 MachinePointerInfo::getFixedStack(
2933 DAG.getMachineFunction(), NewReturnAddrFI),
2938 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2939 /// operation of specified width.
2940 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2942 unsigned NumElems = VT.getVectorNumElements();
2943 SmallVector<int, 8> Mask;
2944 Mask.push_back(NumElems);
2945 for (unsigned i = 1; i != NumElems; ++i)
2947 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2951 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2952 SmallVectorImpl<SDValue> &InVals) const {
2953 SelectionDAG &DAG = CLI.DAG;
2955 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2956 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2957 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2958 SDValue Chain = CLI.Chain;
2959 SDValue Callee = CLI.Callee;
2960 CallingConv::ID CallConv = CLI.CallConv;
2961 bool &isTailCall = CLI.IsTailCall;
2962 bool isVarArg = CLI.IsVarArg;
2964 MachineFunction &MF = DAG.getMachineFunction();
2965 bool Is64Bit = Subtarget->is64Bit();
2966 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2967 StructReturnType SR = callIsStructReturn(Outs);
2968 bool IsSibcall = false;
2969 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2970 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2972 if (Attr.getValueAsString() == "true")
2975 if (Subtarget->isPICStyleGOT() &&
2976 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2977 // If we are using a GOT, disable tail calls to external symbols with
2978 // default visibility. Tail calling such a symbol requires using a GOT
2979 // relocation, which forces early binding of the symbol. This breaks code
2980 // that require lazy function symbol resolution. Using musttail or
2981 // GuaranteedTailCallOpt will override this.
2982 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2983 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2984 G->getGlobal()->hasDefaultVisibility()))
2988 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2990 // Force this to be a tail call. The verifier rules are enough to ensure
2991 // that we can lower this successfully without moving the return address
2994 } else if (isTailCall) {
2995 // Check if it's really possible to do a tail call.
2996 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2997 isVarArg, SR != NotStructReturn,
2998 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2999 Outs, OutVals, Ins, DAG);
3001 // Sibcalls are automatically detected tailcalls which do not require
3003 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3010 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
3011 "Var args not supported with calling convention fastcc, ghc or hipe");
3013 // Analyze operands of the call, assigning locations to each operand.
3014 SmallVector<CCValAssign, 16> ArgLocs;
3015 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3017 // Allocate shadow area for Win64
3019 CCInfo.AllocateStack(32, 8);
3021 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3023 // Get a count of how many bytes are to be pushed on the stack.
3024 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3026 // This is a sibcall. The memory operands are available in caller's
3027 // own caller's stack.
3029 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3030 IsTailCallConvention(CallConv))
3031 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3034 if (isTailCall && !IsSibcall && !IsMustTail) {
3035 // Lower arguments at fp - stackoffset + fpdiff.
3036 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3038 FPDiff = NumBytesCallerPushed - NumBytes;
3040 // Set the delta of movement of the returnaddr stackslot.
3041 // But only set if delta is greater than previous delta.
3042 if (FPDiff < X86Info->getTCReturnAddrDelta())
3043 X86Info->setTCReturnAddrDelta(FPDiff);
3046 unsigned NumBytesToPush = NumBytes;
3047 unsigned NumBytesToPop = NumBytes;
3049 // If we have an inalloca argument, all stack space has already been allocated
3050 // for us and be right at the top of the stack. We don't support multiple
3051 // arguments passed in memory when using inalloca.
3052 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3054 if (!ArgLocs.back().isMemLoc())
3055 report_fatal_error("cannot use inalloca attribute on a register "
3057 if (ArgLocs.back().getLocMemOffset() != 0)
3058 report_fatal_error("any parameter with the inalloca attribute must be "
3059 "the only memory argument");
3063 Chain = DAG.getCALLSEQ_START(
3064 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3066 SDValue RetAddrFrIdx;
3067 // Load return address for tail calls.
3068 if (isTailCall && FPDiff)
3069 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3070 Is64Bit, FPDiff, dl);
3072 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3073 SmallVector<SDValue, 8> MemOpChains;
3076 // Walk the register/memloc assignments, inserting copies/loads. In the case
3077 // of tail call optimization arguments are handle later.
3078 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3079 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3080 // Skip inalloca arguments, they have already been written.
3081 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3082 if (Flags.isInAlloca())
3085 CCValAssign &VA = ArgLocs[i];
3086 EVT RegVT = VA.getLocVT();
3087 SDValue Arg = OutVals[i];
3088 bool isByVal = Flags.isByVal();
3090 // Promote the value if needed.
3091 switch (VA.getLocInfo()) {
3092 default: llvm_unreachable("Unknown loc info!");
3093 case CCValAssign::Full: break;
3094 case CCValAssign::SExt:
3095 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3097 case CCValAssign::ZExt:
3098 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3100 case CCValAssign::AExt:
3101 if (Arg.getValueType().isVector() &&
3102 Arg.getValueType().getScalarType() == MVT::i1)
3103 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3104 else if (RegVT.is128BitVector()) {
3105 // Special case: passing MMX values in XMM registers.
3106 Arg = DAG.getBitcast(MVT::i64, Arg);
3107 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3108 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3110 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3112 case CCValAssign::BCvt:
3113 Arg = DAG.getBitcast(RegVT, Arg);
3115 case CCValAssign::Indirect: {
3116 // Store the argument.
3117 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3118 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3119 Chain = DAG.getStore(
3120 Chain, dl, Arg, SpillSlot,
3121 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3128 if (VA.isRegLoc()) {
3129 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3130 if (isVarArg && IsWin64) {
3131 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3132 // shadow reg if callee is a varargs function.
3133 unsigned ShadowReg = 0;
3134 switch (VA.getLocReg()) {
3135 case X86::XMM0: ShadowReg = X86::RCX; break;
3136 case X86::XMM1: ShadowReg = X86::RDX; break;
3137 case X86::XMM2: ShadowReg = X86::R8; break;
3138 case X86::XMM3: ShadowReg = X86::R9; break;
3141 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3143 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3144 assert(VA.isMemLoc());
3145 if (!StackPtr.getNode())
3146 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3147 getPointerTy(DAG.getDataLayout()));
3148 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3149 dl, DAG, VA, Flags));
3153 if (!MemOpChains.empty())
3154 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3156 if (Subtarget->isPICStyleGOT()) {
3157 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3160 RegsToPass.push_back(std::make_pair(
3161 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3162 getPointerTy(DAG.getDataLayout()))));
3164 // If we are tail calling and generating PIC/GOT style code load the
3165 // address of the callee into ECX. The value in ecx is used as target of
3166 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3167 // for tail calls on PIC/GOT architectures. Normally we would just put the
3168 // address of GOT into ebx and then call target@PLT. But for tail calls
3169 // ebx would be restored (since ebx is callee saved) before jumping to the
3172 // Note: The actual moving to ECX is done further down.
3173 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3174 if (G && !G->getGlobal()->hasLocalLinkage() &&
3175 G->getGlobal()->hasDefaultVisibility())
3176 Callee = LowerGlobalAddress(Callee, DAG);
3177 else if (isa<ExternalSymbolSDNode>(Callee))
3178 Callee = LowerExternalSymbol(Callee, DAG);
3182 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3183 // From AMD64 ABI document:
3184 // For calls that may call functions that use varargs or stdargs
3185 // (prototype-less calls or calls to functions containing ellipsis (...) in
3186 // the declaration) %al is used as hidden argument to specify the number
3187 // of SSE registers used. The contents of %al do not need to match exactly
3188 // the number of registers, but must be an ubound on the number of SSE
3189 // registers used and is in the range 0 - 8 inclusive.
3191 // Count the number of XMM registers allocated.
3192 static const MCPhysReg XMMArgRegs[] = {
3193 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3194 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3196 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3197 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3198 && "SSE registers cannot be used when SSE is disabled");
3200 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3201 DAG.getConstant(NumXMMRegs, dl,
3205 if (isVarArg && IsMustTail) {
3206 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3207 for (const auto &F : Forwards) {
3208 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3209 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3213 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3214 // don't need this because the eligibility check rejects calls that require
3215 // shuffling arguments passed in memory.
3216 if (!IsSibcall && isTailCall) {
3217 // Force all the incoming stack arguments to be loaded from the stack
3218 // before any new outgoing arguments are stored to the stack, because the
3219 // outgoing stack slots may alias the incoming argument stack slots, and
3220 // the alias isn't otherwise explicit. This is slightly more conservative
3221 // than necessary, because it means that each store effectively depends
3222 // on every argument instead of just those arguments it would clobber.
3223 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3225 SmallVector<SDValue, 8> MemOpChains2;
3228 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3229 CCValAssign &VA = ArgLocs[i];
3232 assert(VA.isMemLoc());
3233 SDValue Arg = OutVals[i];
3234 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3235 // Skip inalloca arguments. They don't require any work.
3236 if (Flags.isInAlloca())
3238 // Create frame index.
3239 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3240 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3241 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3242 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3244 if (Flags.isByVal()) {
3245 // Copy relative to framepointer.
3246 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3247 if (!StackPtr.getNode())
3248 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3249 getPointerTy(DAG.getDataLayout()));
3250 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3253 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3257 // Store relative to framepointer.
3258 MemOpChains2.push_back(DAG.getStore(
3259 ArgChain, dl, Arg, FIN,
3260 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3265 if (!MemOpChains2.empty())
3266 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3268 // Store the return address to the appropriate stack slot.
3269 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3270 getPointerTy(DAG.getDataLayout()),
3271 RegInfo->getSlotSize(), FPDiff, dl);
3274 // Build a sequence of copy-to-reg nodes chained together with token chain
3275 // and flag operands which copy the outgoing args into registers.
3277 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3278 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3279 RegsToPass[i].second, InFlag);
3280 InFlag = Chain.getValue(1);
3283 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3284 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3285 // In the 64-bit large code model, we have to make all calls
3286 // through a register, since the call instruction's 32-bit
3287 // pc-relative offset may not be large enough to hold the whole
3289 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3290 // If the callee is a GlobalAddress node (quite common, every direct call
3291 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3293 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3295 // We should use extra load for direct calls to dllimported functions in
3297 const GlobalValue *GV = G->getGlobal();
3298 if (!GV->hasDLLImportStorageClass()) {
3299 unsigned char OpFlags = 0;
3300 bool ExtraLoad = false;
3301 unsigned WrapperKind = ISD::DELETED_NODE;
3303 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3304 // external symbols most go through the PLT in PIC mode. If the symbol
3305 // has hidden or protected visibility, or if it is static or local, then
3306 // we don't need to use the PLT - we can directly call it.
3307 if (Subtarget->isTargetELF() &&
3308 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3309 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3310 OpFlags = X86II::MO_PLT;
3311 } else if (Subtarget->isPICStyleStubAny() &&
3312 !GV->isStrongDefinitionForLinker() &&
3313 (!Subtarget->getTargetTriple().isMacOSX() ||
3314 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3315 // PC-relative references to external symbols should go through $stub,
3316 // unless we're building with the leopard linker or later, which
3317 // automatically synthesizes these stubs.
3318 OpFlags = X86II::MO_DARWIN_STUB;
3319 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3320 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3321 // If the function is marked as non-lazy, generate an indirect call
3322 // which loads from the GOT directly. This avoids runtime overhead
3323 // at the cost of eager binding (and one extra byte of encoding).
3324 OpFlags = X86II::MO_GOTPCREL;
3325 WrapperKind = X86ISD::WrapperRIP;
3329 Callee = DAG.getTargetGlobalAddress(
3330 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3332 // Add a wrapper if needed.
3333 if (WrapperKind != ISD::DELETED_NODE)
3334 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3335 getPointerTy(DAG.getDataLayout()), Callee);
3336 // Add extra indirection if needed.
3338 Callee = DAG.getLoad(
3339 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3340 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3343 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3344 unsigned char OpFlags = 0;
3346 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3347 // external symbols should go through the PLT.
3348 if (Subtarget->isTargetELF() &&
3349 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3350 OpFlags = X86II::MO_PLT;
3351 } else if (Subtarget->isPICStyleStubAny() &&
3352 (!Subtarget->getTargetTriple().isMacOSX() ||
3353 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3354 // PC-relative references to external symbols should go through $stub,
3355 // unless we're building with the leopard linker or later, which
3356 // automatically synthesizes these stubs.
3357 OpFlags = X86II::MO_DARWIN_STUB;
3360 Callee = DAG.getTargetExternalSymbol(
3361 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3362 } else if (Subtarget->isTarget64BitILP32() &&
3363 Callee->getValueType(0) == MVT::i32) {
3364 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3365 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3368 // Returns a chain & a flag for retval copy to use.
3369 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3370 SmallVector<SDValue, 8> Ops;
3372 if (!IsSibcall && isTailCall) {
3373 Chain = DAG.getCALLSEQ_END(Chain,
3374 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3375 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3376 InFlag = Chain.getValue(1);
3379 Ops.push_back(Chain);
3380 Ops.push_back(Callee);
3383 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3385 // Add argument registers to the end of the list so that they are known live
3387 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3388 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3389 RegsToPass[i].second.getValueType()));
3391 // Add a register mask operand representing the call-preserved registers.
3392 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3393 assert(Mask && "Missing call preserved mask for calling convention");
3395 // If this is an invoke in a 32-bit function using a funclet-based
3396 // personality, assume the function clobbers all registers. If an exception
3397 // is thrown, the runtime will not restore CSRs.
3398 // FIXME: Model this more precisely so that we can register allocate across
3399 // the normal edge and spill and fill across the exceptional edge.
3400 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3401 const Function *CallerFn = MF.getFunction();
3402 EHPersonality Pers =
3403 CallerFn->hasPersonalityFn()
3404 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3405 : EHPersonality::Unknown;
3406 if (isFuncletEHPersonality(Pers))
3407 Mask = RegInfo->getNoPreservedMask();
3410 Ops.push_back(DAG.getRegisterMask(Mask));
3412 if (InFlag.getNode())
3413 Ops.push_back(InFlag);
3417 //// If this is the first return lowered for this function, add the regs
3418 //// to the liveout set for the function.
3419 // This isn't right, although it's probably harmless on x86; liveouts
3420 // should be computed from returns not tail calls. Consider a void
3421 // function making a tail call to a function returning int.
3422 MF.getFrameInfo()->setHasTailCall();
3423 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3426 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3427 InFlag = Chain.getValue(1);
3429 // Create the CALLSEQ_END node.
3430 unsigned NumBytesForCalleeToPop;
3431 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3432 DAG.getTarget().Options.GuaranteedTailCallOpt))
3433 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3434 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3435 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3436 SR == StackStructReturn)
3437 // If this is a call to a struct-return function, the callee
3438 // pops the hidden struct pointer, so we have to push it back.
3439 // This is common for Darwin/X86, Linux & Mingw32 targets.
3440 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3441 NumBytesForCalleeToPop = 4;
3443 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3445 // Returns a flag for retval copy to use.
3447 Chain = DAG.getCALLSEQ_END(Chain,
3448 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3449 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3452 InFlag = Chain.getValue(1);
3455 // Handle result values, copying them out of physregs into vregs that we
3457 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3458 Ins, dl, DAG, InVals);
3461 //===----------------------------------------------------------------------===//
3462 // Fast Calling Convention (tail call) implementation
3463 //===----------------------------------------------------------------------===//
3465 // Like std call, callee cleans arguments, convention except that ECX is
3466 // reserved for storing the tail called function address. Only 2 registers are
3467 // free for argument passing (inreg). Tail call optimization is performed
3469 // * tailcallopt is enabled
3470 // * caller/callee are fastcc
3471 // On X86_64 architecture with GOT-style position independent code only local
3472 // (within module) calls are supported at the moment.
3473 // To keep the stack aligned according to platform abi the function
3474 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3475 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3476 // If a tail called function callee has more arguments than the caller the
3477 // caller needs to make sure that there is room to move the RETADDR to. This is
3478 // achieved by reserving an area the size of the argument delta right after the
3479 // original RETADDR, but before the saved framepointer or the spilled registers
3480 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3492 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3495 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3496 SelectionDAG& DAG) const {
3497 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3498 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3499 unsigned StackAlignment = TFI.getStackAlignment();
3500 uint64_t AlignMask = StackAlignment - 1;
3501 int64_t Offset = StackSize;
3502 unsigned SlotSize = RegInfo->getSlotSize();
3503 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3504 // Number smaller than 12 so just add the difference.
3505 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3507 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3508 Offset = ((~AlignMask) & Offset) + StackAlignment +
3509 (StackAlignment-SlotSize);
3514 /// Return true if the given stack call argument is already available in the
3515 /// same position (relatively) of the caller's incoming argument stack.
3517 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3518 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3519 const X86InstrInfo *TII) {
3520 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3522 if (Arg.getOpcode() == ISD::CopyFromReg) {
3523 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3524 if (!TargetRegisterInfo::isVirtualRegister(VR))
3526 MachineInstr *Def = MRI->getVRegDef(VR);
3529 if (!Flags.isByVal()) {
3530 if (!TII->isLoadFromStackSlot(Def, FI))
3533 unsigned Opcode = Def->getOpcode();
3534 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3535 Opcode == X86::LEA64_32r) &&
3536 Def->getOperand(1).isFI()) {
3537 FI = Def->getOperand(1).getIndex();
3538 Bytes = Flags.getByValSize();
3542 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3543 if (Flags.isByVal())
3544 // ByVal argument is passed in as a pointer but it's now being
3545 // dereferenced. e.g.
3546 // define @foo(%struct.X* %A) {
3547 // tail call @bar(%struct.X* byval %A)
3550 SDValue Ptr = Ld->getBasePtr();
3551 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3554 FI = FINode->getIndex();
3555 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3556 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3557 FI = FINode->getIndex();
3558 Bytes = Flags.getByValSize();
3562 assert(FI != INT_MAX);
3563 if (!MFI->isFixedObjectIndex(FI))
3565 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3568 /// Check whether the call is eligible for tail call optimization. Targets
3569 /// that want to do tail call optimization should implement this function.
3570 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3571 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3572 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3573 const SmallVectorImpl<ISD::OutputArg> &Outs,
3574 const SmallVectorImpl<SDValue> &OutVals,
3575 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3576 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3579 // If -tailcallopt is specified, make fastcc functions tail-callable.
3580 const MachineFunction &MF = DAG.getMachineFunction();
3581 const Function *CallerF = MF.getFunction();
3583 // If the function return type is x86_fp80 and the callee return type is not,
3584 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3585 // perform a tailcall optimization here.
3586 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3589 CallingConv::ID CallerCC = CallerF->getCallingConv();
3590 bool CCMatch = CallerCC == CalleeCC;
3591 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3592 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3594 // Win64 functions have extra shadow space for argument homing. Don't do the
3595 // sibcall if the caller and callee have mismatched expectations for this
3597 if (IsCalleeWin64 != IsCallerWin64)
3600 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3601 if (IsTailCallConvention(CalleeCC) && CCMatch)
3606 // Look for obvious safe cases to perform tail call optimization that do not
3607 // require ABI changes. This is what gcc calls sibcall.
3609 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3610 // emit a special epilogue.
3611 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3612 if (RegInfo->needsStackRealignment(MF))
3615 // Also avoid sibcall optimization if either caller or callee uses struct
3616 // return semantics.
3617 if (isCalleeStructRet || isCallerStructRet)
3620 // An stdcall/thiscall caller is expected to clean up its arguments; the
3621 // callee isn't going to do that.
3622 // FIXME: this is more restrictive than needed. We could produce a tailcall
3623 // when the stack adjustment matches. For example, with a thiscall that takes
3624 // only one argument.
3625 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3626 CallerCC == CallingConv::X86_ThisCall))
3629 // Do not sibcall optimize vararg calls unless all arguments are passed via
3631 if (isVarArg && !Outs.empty()) {
3633 // Optimizing for varargs on Win64 is unlikely to be safe without
3634 // additional testing.
3635 if (IsCalleeWin64 || IsCallerWin64)
3638 SmallVector<CCValAssign, 16> ArgLocs;
3639 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3642 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3643 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3644 if (!ArgLocs[i].isRegLoc())
3648 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3649 // stack. Therefore, if it's not used by the call it is not safe to optimize
3650 // this into a sibcall.
3651 bool Unused = false;
3652 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3659 SmallVector<CCValAssign, 16> RVLocs;
3660 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3662 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3663 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3664 CCValAssign &VA = RVLocs[i];
3665 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3670 // If the calling conventions do not match, then we'd better make sure the
3671 // results are returned in the same way as what the caller expects.
3673 SmallVector<CCValAssign, 16> RVLocs1;
3674 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3676 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3678 SmallVector<CCValAssign, 16> RVLocs2;
3679 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3681 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3683 if (RVLocs1.size() != RVLocs2.size())
3685 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3686 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3688 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3690 if (RVLocs1[i].isRegLoc()) {
3691 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3694 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3700 // If the callee takes no arguments then go on to check the results of the
3702 if (!Outs.empty()) {
3703 // Check if stack adjustment is needed. For now, do not do this if any
3704 // argument is passed on the stack.
3705 SmallVector<CCValAssign, 16> ArgLocs;
3706 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3709 // Allocate shadow area for Win64
3711 CCInfo.AllocateStack(32, 8);
3713 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3714 if (CCInfo.getNextStackOffset()) {
3715 MachineFunction &MF = DAG.getMachineFunction();
3716 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3719 // Check if the arguments are already laid out in the right way as
3720 // the caller's fixed stack objects.
3721 MachineFrameInfo *MFI = MF.getFrameInfo();
3722 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3723 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3724 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3725 CCValAssign &VA = ArgLocs[i];
3726 SDValue Arg = OutVals[i];
3727 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3728 if (VA.getLocInfo() == CCValAssign::Indirect)
3730 if (!VA.isRegLoc()) {
3731 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3738 // If the tailcall address may be in a register, then make sure it's
3739 // possible to register allocate for it. In 32-bit, the call address can
3740 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3741 // callee-saved registers are restored. These happen to be the same
3742 // registers used to pass 'inreg' arguments so watch out for those.
3743 if (!Subtarget->is64Bit() &&
3744 ((!isa<GlobalAddressSDNode>(Callee) &&
3745 !isa<ExternalSymbolSDNode>(Callee)) ||
3746 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3747 unsigned NumInRegs = 0;
3748 // In PIC we need an extra register to formulate the address computation
3750 unsigned MaxInRegs =
3751 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3753 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3754 CCValAssign &VA = ArgLocs[i];
3757 unsigned Reg = VA.getLocReg();
3760 case X86::EAX: case X86::EDX: case X86::ECX:
3761 if (++NumInRegs == MaxInRegs)
3773 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3774 const TargetLibraryInfo *libInfo) const {
3775 return X86::createFastISel(funcInfo, libInfo);
3778 //===----------------------------------------------------------------------===//
3779 // Other Lowering Hooks
3780 //===----------------------------------------------------------------------===//
3782 static bool MayFoldLoad(SDValue Op) {
3783 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3786 static bool MayFoldIntoStore(SDValue Op) {
3787 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3790 static bool isTargetShuffle(unsigned Opcode) {
3792 default: return false;
3793 case X86ISD::BLENDI:
3794 case X86ISD::PSHUFB:
3795 case X86ISD::PSHUFD:
3796 case X86ISD::PSHUFHW:
3797 case X86ISD::PSHUFLW:
3799 case X86ISD::PALIGNR:
3800 case X86ISD::MOVLHPS:
3801 case X86ISD::MOVLHPD:
3802 case X86ISD::MOVHLPS:
3803 case X86ISD::MOVLPS:
3804 case X86ISD::MOVLPD:
3805 case X86ISD::MOVSHDUP:
3806 case X86ISD::MOVSLDUP:
3807 case X86ISD::MOVDDUP:
3810 case X86ISD::UNPCKL:
3811 case X86ISD::UNPCKH:
3812 case X86ISD::VPERMILPI:
3813 case X86ISD::VPERM2X128:
3814 case X86ISD::VPERMI:
3815 case X86ISD::VPERMV:
3816 case X86ISD::VPERMV3:
3821 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3822 SDValue V1, unsigned TargetMask,
3823 SelectionDAG &DAG) {
3825 default: llvm_unreachable("Unknown x86 shuffle node");
3826 case X86ISD::PSHUFD:
3827 case X86ISD::PSHUFHW:
3828 case X86ISD::PSHUFLW:
3829 case X86ISD::VPERMILPI:
3830 case X86ISD::VPERMI:
3831 return DAG.getNode(Opc, dl, VT, V1,
3832 DAG.getConstant(TargetMask, dl, MVT::i8));
3836 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3837 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3839 default: llvm_unreachable("Unknown x86 shuffle node");
3840 case X86ISD::MOVLHPS:
3841 case X86ISD::MOVLHPD:
3842 case X86ISD::MOVHLPS:
3843 case X86ISD::MOVLPS:
3844 case X86ISD::MOVLPD:
3847 case X86ISD::UNPCKL:
3848 case X86ISD::UNPCKH:
3849 return DAG.getNode(Opc, dl, VT, V1, V2);
3853 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3854 MachineFunction &MF = DAG.getMachineFunction();
3855 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3856 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3857 int ReturnAddrIndex = FuncInfo->getRAIndex();
3859 if (ReturnAddrIndex == 0) {
3860 // Set up a frame object for the return address.
3861 unsigned SlotSize = RegInfo->getSlotSize();
3862 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3865 FuncInfo->setRAIndex(ReturnAddrIndex);
3868 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3871 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3872 bool hasSymbolicDisplacement) {
3873 // Offset should fit into 32 bit immediate field.
3874 if (!isInt<32>(Offset))
3877 // If we don't have a symbolic displacement - we don't have any extra
3879 if (!hasSymbolicDisplacement)
3882 // FIXME: Some tweaks might be needed for medium code model.
3883 if (M != CodeModel::Small && M != CodeModel::Kernel)
3886 // For small code model we assume that latest object is 16MB before end of 31
3887 // bits boundary. We may also accept pretty large negative constants knowing
3888 // that all objects are in the positive half of address space.
3889 if (M == CodeModel::Small && Offset < 16*1024*1024)
3892 // For kernel code model we know that all object resist in the negative half
3893 // of 32bits address space. We may not accept negative offsets, since they may
3894 // be just off and we may accept pretty large positive ones.
3895 if (M == CodeModel::Kernel && Offset >= 0)
3901 /// Determines whether the callee is required to pop its own arguments.
3902 /// Callee pop is necessary to support tail calls.
3903 bool X86::isCalleePop(CallingConv::ID CallingConv,
3904 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3906 if (IsTailCallConvention(CallingConv))
3907 return IsVarArg ? false : TailCallOpt;
3909 switch (CallingConv) {
3912 case CallingConv::X86_StdCall:
3913 case CallingConv::X86_FastCall:
3914 case CallingConv::X86_ThisCall:
3919 /// \brief Return true if the condition is an unsigned comparison operation.
3920 static bool isX86CCUnsigned(unsigned X86CC) {
3922 default: llvm_unreachable("Invalid integer condition!");
3923 case X86::COND_E: return true;
3924 case X86::COND_G: return false;
3925 case X86::COND_GE: return false;
3926 case X86::COND_L: return false;
3927 case X86::COND_LE: return false;
3928 case X86::COND_NE: return true;
3929 case X86::COND_B: return true;
3930 case X86::COND_A: return true;
3931 case X86::COND_BE: return true;
3932 case X86::COND_AE: return true;
3934 llvm_unreachable("covered switch fell through?!");
3937 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3938 /// condition code, returning the condition code and the LHS/RHS of the
3939 /// comparison to make.
3940 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3941 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3943 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3944 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3945 // X > -1 -> X == 0, jump !sign.
3946 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3947 return X86::COND_NS;
3949 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3950 // X < 0 -> X == 0, jump on sign.
3953 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3955 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3956 return X86::COND_LE;
3960 switch (SetCCOpcode) {
3961 default: llvm_unreachable("Invalid integer condition!");
3962 case ISD::SETEQ: return X86::COND_E;
3963 case ISD::SETGT: return X86::COND_G;
3964 case ISD::SETGE: return X86::COND_GE;
3965 case ISD::SETLT: return X86::COND_L;
3966 case ISD::SETLE: return X86::COND_LE;
3967 case ISD::SETNE: return X86::COND_NE;
3968 case ISD::SETULT: return X86::COND_B;
3969 case ISD::SETUGT: return X86::COND_A;
3970 case ISD::SETULE: return X86::COND_BE;
3971 case ISD::SETUGE: return X86::COND_AE;
3975 // First determine if it is required or is profitable to flip the operands.
3977 // If LHS is a foldable load, but RHS is not, flip the condition.
3978 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3979 !ISD::isNON_EXTLoad(RHS.getNode())) {
3980 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3981 std::swap(LHS, RHS);
3984 switch (SetCCOpcode) {
3990 std::swap(LHS, RHS);
3994 // On a floating point condition, the flags are set as follows:
3996 // 0 | 0 | 0 | X > Y
3997 // 0 | 0 | 1 | X < Y
3998 // 1 | 0 | 0 | X == Y
3999 // 1 | 1 | 1 | unordered
4000 switch (SetCCOpcode) {
4001 default: llvm_unreachable("Condcode should be pre-legalized away");
4003 case ISD::SETEQ: return X86::COND_E;
4004 case ISD::SETOLT: // flipped
4006 case ISD::SETGT: return X86::COND_A;
4007 case ISD::SETOLE: // flipped
4009 case ISD::SETGE: return X86::COND_AE;
4010 case ISD::SETUGT: // flipped
4012 case ISD::SETLT: return X86::COND_B;
4013 case ISD::SETUGE: // flipped
4015 case ISD::SETLE: return X86::COND_BE;
4017 case ISD::SETNE: return X86::COND_NE;
4018 case ISD::SETUO: return X86::COND_P;
4019 case ISD::SETO: return X86::COND_NP;
4021 case ISD::SETUNE: return X86::COND_INVALID;
4025 /// Is there a floating point cmov for the specific X86 condition code?
4026 /// Current x86 isa includes the following FP cmov instructions:
4027 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4028 static bool hasFPCMov(unsigned X86CC) {
4044 /// Returns true if the target can instruction select the
4045 /// specified FP immediate natively. If false, the legalizer will
4046 /// materialize the FP immediate as a load from a constant pool.
4047 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4048 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4049 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4055 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4056 ISD::LoadExtType ExtTy,
4058 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4059 // relocation target a movq or addq instruction: don't let the load shrink.
4060 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4061 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4062 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4063 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4067 /// \brief Returns true if it is beneficial to convert a load of a constant
4068 /// to just the constant itself.
4069 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4071 assert(Ty->isIntegerTy());
4073 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4074 if (BitSize == 0 || BitSize > 64)
4079 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4080 unsigned Index) const {
4081 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4084 return (Index == 0 || Index == ResVT.getVectorNumElements());
4087 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4088 // Speculate cttz only if we can directly use TZCNT.
4089 return Subtarget->hasBMI();
4092 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4093 // Speculate ctlz only if we can directly use LZCNT.
4094 return Subtarget->hasLZCNT();
4097 /// Return true if every element in Mask, beginning
4098 /// from position Pos and ending in Pos+Size is undef.
4099 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4100 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4106 /// Return true if Val is undef or if its value falls within the
4107 /// specified range (L, H].
4108 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4109 return (Val < 0) || (Val >= Low && Val < Hi);
4112 /// Val is either less than zero (undef) or equal to the specified value.
4113 static bool isUndefOrEqual(int Val, int CmpVal) {
4114 return (Val < 0 || Val == CmpVal);
4117 /// Return true if every element in Mask, beginning
4118 /// from position Pos and ending in Pos+Size, falls within the specified
4119 /// sequential range (Low, Low+Size]. or is undef.
4120 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4121 unsigned Pos, unsigned Size, int Low) {
4122 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4123 if (!isUndefOrEqual(Mask[i], Low))
4128 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4129 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4130 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4131 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4132 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4135 // The index should be aligned on a vecWidth-bit boundary.
4137 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4139 MVT VT = N->getSimpleValueType(0);
4140 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4141 bool Result = (Index * ElSize) % vecWidth == 0;
4146 /// Return true if the specified INSERT_SUBVECTOR
4147 /// operand specifies a subvector insert that is suitable for input to
4148 /// insertion of 128 or 256-bit subvectors
4149 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4150 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4151 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4153 // The index should be aligned on a vecWidth-bit boundary.
4155 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4157 MVT VT = N->getSimpleValueType(0);
4158 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4159 bool Result = (Index * ElSize) % vecWidth == 0;
4164 bool X86::isVINSERT128Index(SDNode *N) {
4165 return isVINSERTIndex(N, 128);
4168 bool X86::isVINSERT256Index(SDNode *N) {
4169 return isVINSERTIndex(N, 256);
4172 bool X86::isVEXTRACT128Index(SDNode *N) {
4173 return isVEXTRACTIndex(N, 128);
4176 bool X86::isVEXTRACT256Index(SDNode *N) {
4177 return isVEXTRACTIndex(N, 256);
4180 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4181 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4182 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4183 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4186 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4188 MVT VecVT = N->getOperand(0).getSimpleValueType();
4189 MVT ElVT = VecVT.getVectorElementType();
4191 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4192 return Index / NumElemsPerChunk;
4195 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4196 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4197 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4198 llvm_unreachable("Illegal insert subvector for VINSERT");
4201 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4203 MVT VecVT = N->getSimpleValueType(0);
4204 MVT ElVT = VecVT.getVectorElementType();
4206 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4207 return Index / NumElemsPerChunk;
4210 /// Return the appropriate immediate to extract the specified
4211 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4212 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4213 return getExtractVEXTRACTImmediate(N, 128);
4216 /// Return the appropriate immediate to extract the specified
4217 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4218 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4219 return getExtractVEXTRACTImmediate(N, 256);
4222 /// Return the appropriate immediate to insert at the specified
4223 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4224 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4225 return getInsertVINSERTImmediate(N, 128);
4228 /// Return the appropriate immediate to insert at the specified
4229 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4230 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4231 return getInsertVINSERTImmediate(N, 256);
4234 /// Returns true if V is a constant integer zero.
4235 static bool isZero(SDValue V) {
4236 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4237 return C && C->isNullValue();
4240 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4241 bool X86::isZeroNode(SDValue Elt) {
4244 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4245 return CFP->getValueAPF().isPosZero();
4249 // Build a vector of constants
4250 // Use an UNDEF node if MaskElt == -1.
4251 // Spilt 64-bit constants in the 32-bit mode.
4252 static SDValue getConstVector(ArrayRef<int> Values, EVT VT,
4254 SDLoc dl, bool IsMask = false) {
4256 SmallVector<SDValue, 32> Ops;
4259 EVT ConstVecVT = VT;
4260 unsigned NumElts = VT.getVectorNumElements();
4261 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4262 if (!In64BitMode && VT.getScalarType() == MVT::i64) {
4263 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4267 EVT EltVT = ConstVecVT.getScalarType();
4268 for (unsigned i = 0; i < NumElts; ++i) {
4269 bool IsUndef = Values[i] < 0 && IsMask;
4270 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4271 DAG.getConstant(Values[i], dl, EltVT);
4272 Ops.push_back(OpNode);
4274 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4275 DAG.getConstant(0, dl, EltVT));
4277 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4279 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4283 /// Returns a vector of specified type with all zero elements.
4284 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4285 SelectionDAG &DAG, SDLoc dl) {
4286 assert(VT.isVector() && "Expected a vector type");
4288 // Always build SSE zero vectors as <4 x i32> bitcasted
4289 // to their dest type. This ensures they get CSE'd.
4291 if (VT.is128BitVector()) { // SSE
4292 if (Subtarget->hasSSE2()) { // SSE2
4293 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4294 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4296 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4297 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4299 } else if (VT.is256BitVector()) { // AVX
4300 if (Subtarget->hasInt256()) { // AVX2
4301 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4302 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4303 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4305 // 256-bit logic and arithmetic instructions in AVX are all
4306 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4307 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4308 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4309 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4311 } else if (VT.is512BitVector()) { // AVX-512
4312 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4313 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4314 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4315 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4316 } else if (VT.getScalarType() == MVT::i1) {
4318 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4319 && "Unexpected vector type");
4320 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4321 && "Unexpected vector type");
4322 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4323 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4324 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4326 llvm_unreachable("Unexpected vector type");
4328 return DAG.getBitcast(VT, Vec);
4331 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4332 SelectionDAG &DAG, SDLoc dl,
4333 unsigned vectorWidth) {
4334 assert((vectorWidth == 128 || vectorWidth == 256) &&
4335 "Unsupported vector width");
4336 EVT VT = Vec.getValueType();
4337 EVT ElVT = VT.getVectorElementType();
4338 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4339 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4340 VT.getVectorNumElements()/Factor);
4342 // Extract from UNDEF is UNDEF.
4343 if (Vec.getOpcode() == ISD::UNDEF)
4344 return DAG.getUNDEF(ResultVT);
4346 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4347 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4349 // This is the index of the first element of the vectorWidth-bit chunk
4351 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4354 // If the input is a buildvector just emit a smaller one.
4355 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4356 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4357 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4360 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4361 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4364 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4365 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4366 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4367 /// instructions or a simple subregister reference. Idx is an index in the
4368 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4369 /// lowering EXTRACT_VECTOR_ELT operations easier.
4370 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4371 SelectionDAG &DAG, SDLoc dl) {
4372 assert((Vec.getValueType().is256BitVector() ||
4373 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4374 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4377 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4378 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4379 SelectionDAG &DAG, SDLoc dl) {
4380 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4381 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4384 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4385 unsigned IdxVal, SelectionDAG &DAG,
4386 SDLoc dl, unsigned vectorWidth) {
4387 assert((vectorWidth == 128 || vectorWidth == 256) &&
4388 "Unsupported vector width");
4389 // Inserting UNDEF is Result
4390 if (Vec.getOpcode() == ISD::UNDEF)
4392 EVT VT = Vec.getValueType();
4393 EVT ElVT = VT.getVectorElementType();
4394 EVT ResultVT = Result.getValueType();
4396 // Insert the relevant vectorWidth bits.
4397 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4399 // This is the index of the first element of the vectorWidth-bit chunk
4401 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4404 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4405 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4408 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4409 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4410 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4411 /// simple superregister reference. Idx is an index in the 128 bits
4412 /// we want. It need not be aligned to a 128-bit boundary. That makes
4413 /// lowering INSERT_VECTOR_ELT operations easier.
4414 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4415 SelectionDAG &DAG, SDLoc dl) {
4416 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4418 // For insertion into the zero index (low half) of a 256-bit vector, it is
4419 // more efficient to generate a blend with immediate instead of an insert*128.
4420 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4421 // extend the subvector to the size of the result vector. Make sure that
4422 // we are not recursing on that node by checking for undef here.
4423 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4424 Result.getOpcode() != ISD::UNDEF) {
4425 EVT ResultVT = Result.getValueType();
4426 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4427 SDValue Undef = DAG.getUNDEF(ResultVT);
4428 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4431 // The blend instruction, and therefore its mask, depend on the data type.
4432 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4433 if (ScalarType.isFloatingPoint()) {
4434 // Choose either vblendps (float) or vblendpd (double).
4435 unsigned ScalarSize = ScalarType.getSizeInBits();
4436 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4437 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4438 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4439 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4442 const X86Subtarget &Subtarget =
4443 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4445 // AVX2 is needed for 256-bit integer blend support.
4446 // Integers must be cast to 32-bit because there is only vpblendd;
4447 // vpblendw can't be used for this because it has a handicapped mask.
4449 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4450 // is still more efficient than using the wrong domain vinsertf128 that
4451 // will be created by InsertSubVector().
4452 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4454 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4455 Vec256 = DAG.getBitcast(CastVT, Vec256);
4456 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4457 return DAG.getBitcast(ResultVT, Vec256);
4460 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4463 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4464 SelectionDAG &DAG, SDLoc dl) {
4465 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4466 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4469 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4470 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4471 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4472 /// large BUILD_VECTORS.
4473 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4474 unsigned NumElems, SelectionDAG &DAG,
4476 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4477 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4480 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4481 unsigned NumElems, SelectionDAG &DAG,
4483 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4484 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4487 /// Returns a vector of specified type with all bits set.
4488 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4489 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4490 /// Then bitcast to their original type, ensuring they get CSE'd.
4491 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4492 SelectionDAG &DAG, SDLoc dl) {
4493 assert(VT.isVector() && "Expected a vector type");
4495 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4497 if (VT.is512BitVector()) {
4498 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4499 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4500 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4501 } else if (VT.is256BitVector()) {
4502 if (Subtarget->hasInt256()) { // AVX2
4503 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4504 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4506 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4507 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4509 } else if (VT.is128BitVector()) {
4510 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4512 llvm_unreachable("Unexpected vector type");
4514 return DAG.getBitcast(VT, Vec);
4517 /// Returns a vector_shuffle node for an unpackl operation.
4518 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4520 unsigned NumElems = VT.getVectorNumElements();
4521 SmallVector<int, 8> Mask;
4522 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4524 Mask.push_back(i + NumElems);
4526 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4529 /// Returns a vector_shuffle node for an unpackh operation.
4530 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4532 unsigned NumElems = VT.getVectorNumElements();
4533 SmallVector<int, 8> Mask;
4534 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4535 Mask.push_back(i + Half);
4536 Mask.push_back(i + NumElems + Half);
4538 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4541 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4542 /// This produces a shuffle where the low element of V2 is swizzled into the
4543 /// zero/undef vector, landing at element Idx.
4544 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4545 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4547 const X86Subtarget *Subtarget,
4548 SelectionDAG &DAG) {
4549 MVT VT = V2.getSimpleValueType();
4551 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4552 unsigned NumElems = VT.getVectorNumElements();
4553 SmallVector<int, 16> MaskVec;
4554 for (unsigned i = 0; i != NumElems; ++i)
4555 // If this is the insertion idx, put the low elt of V2 here.
4556 MaskVec.push_back(i == Idx ? NumElems : i);
4557 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4560 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4561 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4562 /// uses one source. Note that this will set IsUnary for shuffles which use a
4563 /// single input multiple times, and in those cases it will
4564 /// adjust the mask to only have indices within that single input.
4565 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4566 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4567 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4568 unsigned NumElems = VT.getVectorNumElements();
4572 bool IsFakeUnary = false;
4573 switch(N->getOpcode()) {
4574 case X86ISD::BLENDI:
4575 ImmN = N->getOperand(N->getNumOperands()-1);
4576 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4579 ImmN = N->getOperand(N->getNumOperands()-1);
4580 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4581 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4583 case X86ISD::UNPCKH:
4584 DecodeUNPCKHMask(VT, Mask);
4585 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4587 case X86ISD::UNPCKL:
4588 DecodeUNPCKLMask(VT, Mask);
4589 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4591 case X86ISD::MOVHLPS:
4592 DecodeMOVHLPSMask(NumElems, Mask);
4593 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4595 case X86ISD::MOVLHPS:
4596 DecodeMOVLHPSMask(NumElems, Mask);
4597 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4599 case X86ISD::PALIGNR:
4600 ImmN = N->getOperand(N->getNumOperands()-1);
4601 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4603 case X86ISD::PSHUFD:
4604 case X86ISD::VPERMILPI:
4605 ImmN = N->getOperand(N->getNumOperands()-1);
4606 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4609 case X86ISD::PSHUFHW:
4610 ImmN = N->getOperand(N->getNumOperands()-1);
4611 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4614 case X86ISD::PSHUFLW:
4615 ImmN = N->getOperand(N->getNumOperands()-1);
4616 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4619 case X86ISD::PSHUFB: {
4621 SDValue MaskNode = N->getOperand(1);
4622 while (MaskNode->getOpcode() == ISD::BITCAST)
4623 MaskNode = MaskNode->getOperand(0);
4625 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4626 // If we have a build-vector, then things are easy.
4627 EVT VT = MaskNode.getValueType();
4628 assert(VT.isVector() &&
4629 "Can't produce a non-vector with a build_vector!");
4630 if (!VT.isInteger())
4633 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4635 SmallVector<uint64_t, 32> RawMask;
4636 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4637 SDValue Op = MaskNode->getOperand(i);
4638 if (Op->getOpcode() == ISD::UNDEF) {
4639 RawMask.push_back((uint64_t)SM_SentinelUndef);
4642 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4645 APInt MaskElement = CN->getAPIntValue();
4647 // We now have to decode the element which could be any integer size and
4648 // extract each byte of it.
4649 for (int j = 0; j < NumBytesPerElement; ++j) {
4650 // Note that this is x86 and so always little endian: the low byte is
4651 // the first byte of the mask.
4652 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4653 MaskElement = MaskElement.lshr(8);
4656 DecodePSHUFBMask(RawMask, Mask);
4660 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4664 SDValue Ptr = MaskLoad->getBasePtr();
4665 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4666 Ptr->getOpcode() == X86ISD::WrapperRIP)
4667 Ptr = Ptr->getOperand(0);
4669 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4670 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4673 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4674 DecodePSHUFBMask(C, Mask);
4682 case X86ISD::VPERMI:
4683 ImmN = N->getOperand(N->getNumOperands()-1);
4684 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4689 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4691 case X86ISD::VPERM2X128:
4692 ImmN = N->getOperand(N->getNumOperands()-1);
4693 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4694 if (Mask.empty()) return false;
4695 // Mask only contains negative index if an element is zero.
4696 if (std::any_of(Mask.begin(), Mask.end(),
4697 [](int M){ return M == SM_SentinelZero; }))
4700 case X86ISD::MOVSLDUP:
4701 DecodeMOVSLDUPMask(VT, Mask);
4704 case X86ISD::MOVSHDUP:
4705 DecodeMOVSHDUPMask(VT, Mask);
4708 case X86ISD::MOVDDUP:
4709 DecodeMOVDDUPMask(VT, Mask);
4712 case X86ISD::MOVLHPD:
4713 case X86ISD::MOVLPD:
4714 case X86ISD::MOVLPS:
4715 // Not yet implemented
4717 case X86ISD::VPERMV: {
4719 SDValue MaskNode = N->getOperand(0);
4720 while (MaskNode->getOpcode() == ISD::BITCAST)
4721 MaskNode = MaskNode->getOperand(0);
4723 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4724 SmallVector<uint64_t, 32> RawMask;
4725 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4726 // If we have a build-vector, then things are easy.
4727 assert(MaskNode.getValueType().isInteger() &&
4728 MaskNode.getValueType().getVectorNumElements() ==
4729 VT.getVectorNumElements());
4731 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4732 SDValue Op = MaskNode->getOperand(i);
4733 if (Op->getOpcode() == ISD::UNDEF)
4734 RawMask.push_back((uint64_t)SM_SentinelUndef);
4735 else if (isa<ConstantSDNode>(Op)) {
4736 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4737 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4741 DecodeVPERMVMask(RawMask, Mask);
4744 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4745 unsigned NumEltsInMask = MaskNode->getNumOperands();
4746 MaskNode = MaskNode->getOperand(0);
4747 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4749 APInt MaskEltValue = CN->getAPIntValue();
4750 for (unsigned i = 0; i < NumEltsInMask; ++i)
4751 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4752 DecodeVPERMVMask(RawMask, Mask);
4755 // It may be a scalar load
4758 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4762 SDValue Ptr = MaskLoad->getBasePtr();
4763 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4764 Ptr->getOpcode() == X86ISD::WrapperRIP)
4765 Ptr = Ptr->getOperand(0);
4767 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4768 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4771 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4773 DecodeVPERMVMask(C, VT, Mask);
4780 case X86ISD::VPERMV3: {
4782 SDValue MaskNode = N->getOperand(1);
4783 while (MaskNode->getOpcode() == ISD::BITCAST)
4784 MaskNode = MaskNode->getOperand(1);
4786 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4787 // If we have a build-vector, then things are easy.
4788 assert(MaskNode.getValueType().isInteger() &&
4789 MaskNode.getValueType().getVectorNumElements() ==
4790 VT.getVectorNumElements());
4792 SmallVector<uint64_t, 32> RawMask;
4793 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4795 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4796 SDValue Op = MaskNode->getOperand(i);
4797 if (Op->getOpcode() == ISD::UNDEF)
4798 RawMask.push_back((uint64_t)SM_SentinelUndef);
4800 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4803 APInt MaskElement = CN->getAPIntValue();
4804 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4807 DecodeVPERMV3Mask(RawMask, Mask);
4811 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4815 SDValue Ptr = MaskLoad->getBasePtr();
4816 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4817 Ptr->getOpcode() == X86ISD::WrapperRIP)
4818 Ptr = Ptr->getOperand(0);
4820 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4821 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4824 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4826 DecodeVPERMV3Mask(C, VT, Mask);
4833 default: llvm_unreachable("unknown target shuffle node");
4836 // If we have a fake unary shuffle, the shuffle mask is spread across two
4837 // inputs that are actually the same node. Re-map the mask to always point
4838 // into the first input.
4841 if (M >= (int)Mask.size())
4847 /// Returns the scalar element that will make up the ith
4848 /// element of the result of the vector shuffle.
4849 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4852 return SDValue(); // Limit search depth.
4854 SDValue V = SDValue(N, 0);
4855 EVT VT = V.getValueType();
4856 unsigned Opcode = V.getOpcode();
4858 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4859 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4860 int Elt = SV->getMaskElt(Index);
4863 return DAG.getUNDEF(VT.getVectorElementType());
4865 unsigned NumElems = VT.getVectorNumElements();
4866 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4867 : SV->getOperand(1);
4868 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4871 // Recurse into target specific vector shuffles to find scalars.
4872 if (isTargetShuffle(Opcode)) {
4873 MVT ShufVT = V.getSimpleValueType();
4874 unsigned NumElems = ShufVT.getVectorNumElements();
4875 SmallVector<int, 16> ShuffleMask;
4878 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4881 int Elt = ShuffleMask[Index];
4883 return DAG.getUNDEF(ShufVT.getVectorElementType());
4885 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4887 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4891 // Actual nodes that may contain scalar elements
4892 if (Opcode == ISD::BITCAST) {
4893 V = V.getOperand(0);
4894 EVT SrcVT = V.getValueType();
4895 unsigned NumElems = VT.getVectorNumElements();
4897 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4901 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4902 return (Index == 0) ? V.getOperand(0)
4903 : DAG.getUNDEF(VT.getVectorElementType());
4905 if (V.getOpcode() == ISD::BUILD_VECTOR)
4906 return V.getOperand(Index);
4911 /// Custom lower build_vector of v16i8.
4912 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4913 unsigned NumNonZero, unsigned NumZero,
4915 const X86Subtarget* Subtarget,
4916 const TargetLowering &TLI) {
4924 // SSE4.1 - use PINSRB to insert each byte directly.
4925 if (Subtarget->hasSSE41()) {
4926 for (unsigned i = 0; i < 16; ++i) {
4927 bool isNonZero = (NonZeros & (1 << i)) != 0;
4931 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4933 V = DAG.getUNDEF(MVT::v16i8);
4936 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4937 MVT::v16i8, V, Op.getOperand(i),
4938 DAG.getIntPtrConstant(i, dl));
4945 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4946 for (unsigned i = 0; i < 16; ++i) {
4947 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4948 if (ThisIsNonZero && First) {
4950 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4952 V = DAG.getUNDEF(MVT::v8i16);
4957 SDValue ThisElt, LastElt;
4958 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4959 if (LastIsNonZero) {
4960 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4961 MVT::i16, Op.getOperand(i-1));
4963 if (ThisIsNonZero) {
4964 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4965 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4966 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4968 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4972 if (ThisElt.getNode())
4973 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4974 DAG.getIntPtrConstant(i/2, dl));
4978 return DAG.getBitcast(MVT::v16i8, V);
4981 /// Custom lower build_vector of v8i16.
4982 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4983 unsigned NumNonZero, unsigned NumZero,
4985 const X86Subtarget* Subtarget,
4986 const TargetLowering &TLI) {
4993 for (unsigned i = 0; i < 8; ++i) {
4994 bool isNonZero = (NonZeros & (1 << i)) != 0;
4998 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5000 V = DAG.getUNDEF(MVT::v8i16);
5003 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5004 MVT::v8i16, V, Op.getOperand(i),
5005 DAG.getIntPtrConstant(i, dl));
5012 /// Custom lower build_vector of v4i32 or v4f32.
5013 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5014 const X86Subtarget *Subtarget,
5015 const TargetLowering &TLI) {
5016 // Find all zeroable elements.
5017 std::bitset<4> Zeroable;
5018 for (int i=0; i < 4; ++i) {
5019 SDValue Elt = Op->getOperand(i);
5020 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5022 assert(Zeroable.size() - Zeroable.count() > 1 &&
5023 "We expect at least two non-zero elements!");
5025 // We only know how to deal with build_vector nodes where elements are either
5026 // zeroable or extract_vector_elt with constant index.
5027 SDValue FirstNonZero;
5028 unsigned FirstNonZeroIdx;
5029 for (unsigned i=0; i < 4; ++i) {
5032 SDValue Elt = Op->getOperand(i);
5033 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5034 !isa<ConstantSDNode>(Elt.getOperand(1)))
5036 // Make sure that this node is extracting from a 128-bit vector.
5037 MVT VT = Elt.getOperand(0).getSimpleValueType();
5038 if (!VT.is128BitVector())
5040 if (!FirstNonZero.getNode()) {
5042 FirstNonZeroIdx = i;
5046 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5047 SDValue V1 = FirstNonZero.getOperand(0);
5048 MVT VT = V1.getSimpleValueType();
5050 // See if this build_vector can be lowered as a blend with zero.
5052 unsigned EltMaskIdx, EltIdx;
5054 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5055 if (Zeroable[EltIdx]) {
5056 // The zero vector will be on the right hand side.
5057 Mask[EltIdx] = EltIdx+4;
5061 Elt = Op->getOperand(EltIdx);
5062 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5063 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5064 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5066 Mask[EltIdx] = EltIdx;
5070 // Let the shuffle legalizer deal with blend operations.
5071 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5072 if (V1.getSimpleValueType() != VT)
5073 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5074 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5077 // See if we can lower this build_vector to a INSERTPS.
5078 if (!Subtarget->hasSSE41())
5081 SDValue V2 = Elt.getOperand(0);
5082 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5085 bool CanFold = true;
5086 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5090 SDValue Current = Op->getOperand(i);
5091 SDValue SrcVector = Current->getOperand(0);
5094 CanFold = SrcVector == V1 &&
5095 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5101 assert(V1.getNode() && "Expected at least two non-zero elements!");
5102 if (V1.getSimpleValueType() != MVT::v4f32)
5103 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5104 if (V2.getSimpleValueType() != MVT::v4f32)
5105 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5107 // Ok, we can emit an INSERTPS instruction.
5108 unsigned ZMask = Zeroable.to_ulong();
5110 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5111 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5113 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5114 DAG.getIntPtrConstant(InsertPSMask, DL));
5115 return DAG.getBitcast(VT, Result);
5118 /// Return a vector logical shift node.
5119 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5120 unsigned NumBits, SelectionDAG &DAG,
5121 const TargetLowering &TLI, SDLoc dl) {
5122 assert(VT.is128BitVector() && "Unknown type for VShift");
5123 MVT ShVT = MVT::v2i64;
5124 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5125 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5126 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5127 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5128 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5129 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5133 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5135 // Check if the scalar load can be widened into a vector load. And if
5136 // the address is "base + cst" see if the cst can be "absorbed" into
5137 // the shuffle mask.
5138 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5139 SDValue Ptr = LD->getBasePtr();
5140 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5142 EVT PVT = LD->getValueType(0);
5143 if (PVT != MVT::i32 && PVT != MVT::f32)
5148 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5149 FI = FINode->getIndex();
5151 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5152 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5153 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5154 Offset = Ptr.getConstantOperandVal(1);
5155 Ptr = Ptr.getOperand(0);
5160 // FIXME: 256-bit vector instructions don't require a strict alignment,
5161 // improve this code to support it better.
5162 unsigned RequiredAlign = VT.getSizeInBits()/8;
5163 SDValue Chain = LD->getChain();
5164 // Make sure the stack object alignment is at least 16 or 32.
5165 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5166 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5167 if (MFI->isFixedObjectIndex(FI)) {
5168 // Can't change the alignment. FIXME: It's possible to compute
5169 // the exact stack offset and reference FI + adjust offset instead.
5170 // If someone *really* cares about this. That's the way to implement it.
5173 MFI->setObjectAlignment(FI, RequiredAlign);
5177 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5178 // Ptr + (Offset & ~15).
5181 if ((Offset % RequiredAlign) & 3)
5183 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5186 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5187 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5190 int EltNo = (Offset - StartOffset) >> 2;
5191 unsigned NumElems = VT.getVectorNumElements();
5193 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5194 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5195 LD->getPointerInfo().getWithOffset(StartOffset),
5196 false, false, false, 0);
5198 SmallVector<int, 8> Mask(NumElems, EltNo);
5200 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5206 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5207 /// elements can be replaced by a single large load which has the same value as
5208 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5210 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5212 /// FIXME: we'd also like to handle the case where the last elements are zero
5213 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5214 /// There's even a handy isZeroNode for that purpose.
5215 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5216 SDLoc &DL, SelectionDAG &DAG,
5217 bool isAfterLegalize) {
5218 unsigned NumElems = Elts.size();
5220 LoadSDNode *LDBase = nullptr;
5221 unsigned LastLoadedElt = -1U;
5223 // For each element in the initializer, see if we've found a load or an undef.
5224 // If we don't find an initial load element, or later load elements are
5225 // non-consecutive, bail out.
5226 for (unsigned i = 0; i < NumElems; ++i) {
5227 SDValue Elt = Elts[i];
5228 // Look through a bitcast.
5229 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5230 Elt = Elt.getOperand(0);
5231 if (!Elt.getNode() ||
5232 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5235 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5237 LDBase = cast<LoadSDNode>(Elt.getNode());
5241 if (Elt.getOpcode() == ISD::UNDEF)
5244 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5245 EVT LdVT = Elt.getValueType();
5246 // Each loaded element must be the correct fractional portion of the
5247 // requested vector load.
5248 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5250 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5255 // If we have found an entire vector of loads and undefs, then return a large
5256 // load of the entire vector width starting at the base pointer. If we found
5257 // consecutive loads for the low half, generate a vzext_load node.
5258 if (LastLoadedElt == NumElems - 1) {
5259 assert(LDBase && "Did not find base load for merging consecutive loads");
5260 EVT EltVT = LDBase->getValueType(0);
5261 // Ensure that the input vector size for the merged loads matches the
5262 // cumulative size of the input elements.
5263 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5266 if (isAfterLegalize &&
5267 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5270 SDValue NewLd = SDValue();
5272 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5273 LDBase->getPointerInfo(), LDBase->isVolatile(),
5274 LDBase->isNonTemporal(), LDBase->isInvariant(),
5275 LDBase->getAlignment());
5277 if (LDBase->hasAnyUseOfValue(1)) {
5278 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5280 SDValue(NewLd.getNode(), 1));
5281 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5282 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5283 SDValue(NewLd.getNode(), 1));
5289 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5290 //of a v4i32 / v4f32. It's probably worth generalizing.
5291 EVT EltVT = VT.getVectorElementType();
5292 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5293 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5294 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5295 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5297 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5298 LDBase->getPointerInfo(),
5299 LDBase->getAlignment(),
5300 false/*isVolatile*/, true/*ReadMem*/,
5303 // Make sure the newly-created LOAD is in the same position as LDBase in
5304 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5305 // update uses of LDBase's output chain to use the TokenFactor.
5306 if (LDBase->hasAnyUseOfValue(1)) {
5307 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5308 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5309 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5310 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5311 SDValue(ResNode.getNode(), 1));
5314 return DAG.getBitcast(VT, ResNode);
5319 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5320 /// to generate a splat value for the following cases:
5321 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5322 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5323 /// a scalar load, or a constant.
5324 /// The VBROADCAST node is returned when a pattern is found,
5325 /// or SDValue() otherwise.
5326 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5327 SelectionDAG &DAG) {
5328 // VBROADCAST requires AVX.
5329 // TODO: Splats could be generated for non-AVX CPUs using SSE
5330 // instructions, but there's less potential gain for only 128-bit vectors.
5331 if (!Subtarget->hasAVX())
5334 MVT VT = Op.getSimpleValueType();
5337 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5338 "Unsupported vector type for broadcast.");
5343 switch (Op.getOpcode()) {
5345 // Unknown pattern found.
5348 case ISD::BUILD_VECTOR: {
5349 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5350 BitVector UndefElements;
5351 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5353 // We need a splat of a single value to use broadcast, and it doesn't
5354 // make any sense if the value is only in one element of the vector.
5355 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5359 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5360 Ld.getOpcode() == ISD::ConstantFP);
5362 // Make sure that all of the users of a non-constant load are from the
5363 // BUILD_VECTOR node.
5364 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5369 case ISD::VECTOR_SHUFFLE: {
5370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5372 // Shuffles must have a splat mask where the first element is
5374 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5377 SDValue Sc = Op.getOperand(0);
5378 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5379 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5381 if (!Subtarget->hasInt256())
5384 // Use the register form of the broadcast instruction available on AVX2.
5385 if (VT.getSizeInBits() >= 256)
5386 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5387 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5390 Ld = Sc.getOperand(0);
5391 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5392 Ld.getOpcode() == ISD::ConstantFP);
5394 // The scalar_to_vector node and the suspected
5395 // load node must have exactly one user.
5396 // Constants may have multiple users.
5398 // AVX-512 has register version of the broadcast
5399 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5400 Ld.getValueType().getSizeInBits() >= 32;
5401 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5408 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5409 bool IsGE256 = (VT.getSizeInBits() >= 256);
5411 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5412 // instruction to save 8 or more bytes of constant pool data.
5413 // TODO: If multiple splats are generated to load the same constant,
5414 // it may be detrimental to overall size. There needs to be a way to detect
5415 // that condition to know if this is truly a size win.
5416 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5418 // Handle broadcasting a single constant scalar from the constant pool
5420 // On Sandybridge (no AVX2), it is still better to load a constant vector
5421 // from the constant pool and not to broadcast it from a scalar.
5422 // But override that restriction when optimizing for size.
5423 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5424 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5425 EVT CVT = Ld.getValueType();
5426 assert(!CVT.isVector() && "Must not broadcast a vector type");
5428 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5429 // For size optimization, also splat v2f64 and v2i64, and for size opt
5430 // with AVX2, also splat i8 and i16.
5431 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5432 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5433 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5434 const Constant *C = nullptr;
5435 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5436 C = CI->getConstantIntValue();
5437 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5438 C = CF->getConstantFPValue();
5440 assert(C && "Invalid constant type");
5442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5444 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5445 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5447 CVT, dl, DAG.getEntryNode(), CP,
5448 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5449 false, false, Alignment);
5451 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5455 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5457 // Handle AVX2 in-register broadcasts.
5458 if (!IsLoad && Subtarget->hasInt256() &&
5459 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5460 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5462 // The scalar source must be a normal load.
5466 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5467 (Subtarget->hasVLX() && ScalarSize == 64))
5468 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5470 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5471 // double since there is no vbroadcastsd xmm
5472 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5473 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5474 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5477 // Unsupported broadcast.
5481 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5482 /// underlying vector and index.
5484 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5486 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5488 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5489 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5492 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5494 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5496 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5497 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5500 // In this case the vector is the extract_subvector expression and the index
5501 // is 2, as specified by the shuffle.
5502 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5503 SDValue ShuffleVec = SVOp->getOperand(0);
5504 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5505 assert(ShuffleVecVT.getVectorElementType() ==
5506 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5508 int ShuffleIdx = SVOp->getMaskElt(Idx);
5509 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5510 ExtractedFromVec = ShuffleVec;
5516 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5517 MVT VT = Op.getSimpleValueType();
5519 // Skip if insert_vec_elt is not supported.
5520 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5521 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5525 unsigned NumElems = Op.getNumOperands();
5529 SmallVector<unsigned, 4> InsertIndices;
5530 SmallVector<int, 8> Mask(NumElems, -1);
5532 for (unsigned i = 0; i != NumElems; ++i) {
5533 unsigned Opc = Op.getOperand(i).getOpcode();
5535 if (Opc == ISD::UNDEF)
5538 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5539 // Quit if more than 1 elements need inserting.
5540 if (InsertIndices.size() > 1)
5543 InsertIndices.push_back(i);
5547 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5548 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5549 // Quit if non-constant index.
5550 if (!isa<ConstantSDNode>(ExtIdx))
5552 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5554 // Quit if extracted from vector of different type.
5555 if (ExtractedFromVec.getValueType() != VT)
5558 if (!VecIn1.getNode())
5559 VecIn1 = ExtractedFromVec;
5560 else if (VecIn1 != ExtractedFromVec) {
5561 if (!VecIn2.getNode())
5562 VecIn2 = ExtractedFromVec;
5563 else if (VecIn2 != ExtractedFromVec)
5564 // Quit if more than 2 vectors to shuffle
5568 if (ExtractedFromVec == VecIn1)
5570 else if (ExtractedFromVec == VecIn2)
5571 Mask[i] = Idx + NumElems;
5574 if (!VecIn1.getNode())
5577 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5578 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5579 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5580 unsigned Idx = InsertIndices[i];
5581 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5582 DAG.getIntPtrConstant(Idx, DL));
5588 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5589 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5590 Op.getScalarValueSizeInBits() == 1 &&
5591 "Can not convert non-constant vector");
5592 uint64_t Immediate = 0;
5593 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5594 SDValue In = Op.getOperand(idx);
5595 if (In.getOpcode() != ISD::UNDEF)
5596 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5600 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5601 return DAG.getConstant(Immediate, dl, VT);
5603 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5605 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5607 MVT VT = Op.getSimpleValueType();
5608 assert((VT.getVectorElementType() == MVT::i1) &&
5609 "Unexpected type in LowerBUILD_VECTORvXi1!");
5612 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5613 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5614 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5615 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5618 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5619 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5620 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5621 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5624 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5625 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5626 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5627 return DAG.getBitcast(VT, Imm);
5628 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5629 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5630 DAG.getIntPtrConstant(0, dl));
5633 // Vector has one or more non-const elements
5634 uint64_t Immediate = 0;
5635 SmallVector<unsigned, 16> NonConstIdx;
5636 bool IsSplat = true;
5637 bool HasConstElts = false;
5639 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5640 SDValue In = Op.getOperand(idx);
5641 if (In.getOpcode() == ISD::UNDEF)
5643 if (!isa<ConstantSDNode>(In))
5644 NonConstIdx.push_back(idx);
5646 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5647 HasConstElts = true;
5651 else if (In != Op.getOperand(SplatIdx))
5655 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5657 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5658 DAG.getConstant(1, dl, VT),
5659 DAG.getConstant(0, dl, VT));
5661 // insert elements one by one
5665 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5666 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5668 else if (HasConstElts)
5669 Imm = DAG.getConstant(0, dl, VT);
5671 Imm = DAG.getUNDEF(VT);
5672 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5673 DstVec = DAG.getBitcast(VT, Imm);
5675 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5676 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5677 DAG.getIntPtrConstant(0, dl));
5680 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5681 unsigned InsertIdx = NonConstIdx[i];
5682 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5683 Op.getOperand(InsertIdx),
5684 DAG.getIntPtrConstant(InsertIdx, dl));
5689 /// \brief Return true if \p N implements a horizontal binop and return the
5690 /// operands for the horizontal binop into V0 and V1.
5692 /// This is a helper function of LowerToHorizontalOp().
5693 /// This function checks that the build_vector \p N in input implements a
5694 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5695 /// operation to match.
5696 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5697 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5698 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5701 /// This function only analyzes elements of \p N whose indices are
5702 /// in range [BaseIdx, LastIdx).
5703 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5705 unsigned BaseIdx, unsigned LastIdx,
5706 SDValue &V0, SDValue &V1) {
5707 EVT VT = N->getValueType(0);
5709 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5710 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5711 "Invalid Vector in input!");
5713 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5714 bool CanFold = true;
5715 unsigned ExpectedVExtractIdx = BaseIdx;
5716 unsigned NumElts = LastIdx - BaseIdx;
5717 V0 = DAG.getUNDEF(VT);
5718 V1 = DAG.getUNDEF(VT);
5720 // Check if N implements a horizontal binop.
5721 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5722 SDValue Op = N->getOperand(i + BaseIdx);
5725 if (Op->getOpcode() == ISD::UNDEF) {
5726 // Update the expected vector extract index.
5727 if (i * 2 == NumElts)
5728 ExpectedVExtractIdx = BaseIdx;
5729 ExpectedVExtractIdx += 2;
5733 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5738 SDValue Op0 = Op.getOperand(0);
5739 SDValue Op1 = Op.getOperand(1);
5741 // Try to match the following pattern:
5742 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5743 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5744 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5745 Op0.getOperand(0) == Op1.getOperand(0) &&
5746 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5747 isa<ConstantSDNode>(Op1.getOperand(1)));
5751 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5752 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5754 if (i * 2 < NumElts) {
5755 if (V0.getOpcode() == ISD::UNDEF) {
5756 V0 = Op0.getOperand(0);
5757 if (V0.getValueType() != VT)
5761 if (V1.getOpcode() == ISD::UNDEF) {
5762 V1 = Op0.getOperand(0);
5763 if (V1.getValueType() != VT)
5766 if (i * 2 == NumElts)
5767 ExpectedVExtractIdx = BaseIdx;
5770 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5771 if (I0 == ExpectedVExtractIdx)
5772 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5773 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5774 // Try to match the following dag sequence:
5775 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5776 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5780 ExpectedVExtractIdx += 2;
5786 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5787 /// a concat_vector.
5789 /// This is a helper function of LowerToHorizontalOp().
5790 /// This function expects two 256-bit vectors called V0 and V1.
5791 /// At first, each vector is split into two separate 128-bit vectors.
5792 /// Then, the resulting 128-bit vectors are used to implement two
5793 /// horizontal binary operations.
5795 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5797 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5798 /// the two new horizontal binop.
5799 /// When Mode is set, the first horizontal binop dag node would take as input
5800 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5801 /// horizontal binop dag node would take as input the lower 128-bit of V1
5802 /// and the upper 128-bit of V1.
5804 /// HADD V0_LO, V0_HI
5805 /// HADD V1_LO, V1_HI
5807 /// Otherwise, the first horizontal binop dag node takes as input the lower
5808 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5809 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5811 /// HADD V0_LO, V1_LO
5812 /// HADD V0_HI, V1_HI
5814 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5815 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5816 /// the upper 128-bits of the result.
5817 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5818 SDLoc DL, SelectionDAG &DAG,
5819 unsigned X86Opcode, bool Mode,
5820 bool isUndefLO, bool isUndefHI) {
5821 EVT VT = V0.getValueType();
5822 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5823 "Invalid nodes in input!");
5825 unsigned NumElts = VT.getVectorNumElements();
5826 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5827 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5828 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5829 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5830 EVT NewVT = V0_LO.getValueType();
5832 SDValue LO = DAG.getUNDEF(NewVT);
5833 SDValue HI = DAG.getUNDEF(NewVT);
5836 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5837 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5838 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5839 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5840 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5842 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5843 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5844 V1_LO->getOpcode() != ISD::UNDEF))
5845 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5847 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5848 V1_HI->getOpcode() != ISD::UNDEF))
5849 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5852 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5855 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5857 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5858 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5859 EVT VT = BV->getValueType(0);
5860 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5861 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5865 unsigned NumElts = VT.getVectorNumElements();
5866 SDValue InVec0 = DAG.getUNDEF(VT);
5867 SDValue InVec1 = DAG.getUNDEF(VT);
5869 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5870 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5872 // Odd-numbered elements in the input build vector are obtained from
5873 // adding two integer/float elements.
5874 // Even-numbered elements in the input build vector are obtained from
5875 // subtracting two integer/float elements.
5876 unsigned ExpectedOpcode = ISD::FSUB;
5877 unsigned NextExpectedOpcode = ISD::FADD;
5878 bool AddFound = false;
5879 bool SubFound = false;
5881 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5882 SDValue Op = BV->getOperand(i);
5884 // Skip 'undef' values.
5885 unsigned Opcode = Op.getOpcode();
5886 if (Opcode == ISD::UNDEF) {
5887 std::swap(ExpectedOpcode, NextExpectedOpcode);
5891 // Early exit if we found an unexpected opcode.
5892 if (Opcode != ExpectedOpcode)
5895 SDValue Op0 = Op.getOperand(0);
5896 SDValue Op1 = Op.getOperand(1);
5898 // Try to match the following pattern:
5899 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5900 // Early exit if we cannot match that sequence.
5901 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5902 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5903 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5904 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5905 Op0.getOperand(1) != Op1.getOperand(1))
5908 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5912 // We found a valid add/sub node. Update the information accordingly.
5918 // Update InVec0 and InVec1.
5919 if (InVec0.getOpcode() == ISD::UNDEF) {
5920 InVec0 = Op0.getOperand(0);
5921 if (InVec0.getValueType() != VT)
5924 if (InVec1.getOpcode() == ISD::UNDEF) {
5925 InVec1 = Op1.getOperand(0);
5926 if (InVec1.getValueType() != VT)
5930 // Make sure that operands in input to each add/sub node always
5931 // come from a same pair of vectors.
5932 if (InVec0 != Op0.getOperand(0)) {
5933 if (ExpectedOpcode == ISD::FSUB)
5936 // FADD is commutable. Try to commute the operands
5937 // and then test again.
5938 std::swap(Op0, Op1);
5939 if (InVec0 != Op0.getOperand(0))
5943 if (InVec1 != Op1.getOperand(0))
5946 // Update the pair of expected opcodes.
5947 std::swap(ExpectedOpcode, NextExpectedOpcode);
5950 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5951 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5952 InVec1.getOpcode() != ISD::UNDEF)
5953 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5958 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5959 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5960 const X86Subtarget *Subtarget,
5961 SelectionDAG &DAG) {
5962 EVT VT = BV->getValueType(0);
5963 unsigned NumElts = VT.getVectorNumElements();
5964 unsigned NumUndefsLO = 0;
5965 unsigned NumUndefsHI = 0;
5966 unsigned Half = NumElts/2;
5968 // Count the number of UNDEF operands in the build_vector in input.
5969 for (unsigned i = 0, e = Half; i != e; ++i)
5970 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5973 for (unsigned i = Half, e = NumElts; i != e; ++i)
5974 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5977 // Early exit if this is either a build_vector of all UNDEFs or all the
5978 // operands but one are UNDEF.
5979 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5983 SDValue InVec0, InVec1;
5984 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5985 // Try to match an SSE3 float HADD/HSUB.
5986 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5987 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5989 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5990 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5991 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5992 // Try to match an SSSE3 integer HADD/HSUB.
5993 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5994 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5996 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5997 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6000 if (!Subtarget->hasAVX())
6003 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6004 // Try to match an AVX horizontal add/sub of packed single/double
6005 // precision floating point values from 256-bit vectors.
6006 SDValue InVec2, InVec3;
6007 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6008 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6009 ((InVec0.getOpcode() == ISD::UNDEF ||
6010 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6011 ((InVec1.getOpcode() == ISD::UNDEF ||
6012 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6013 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6015 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6016 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6017 ((InVec0.getOpcode() == ISD::UNDEF ||
6018 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6019 ((InVec1.getOpcode() == ISD::UNDEF ||
6020 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6021 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6022 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6023 // Try to match an AVX2 horizontal add/sub of signed integers.
6024 SDValue InVec2, InVec3;
6026 bool CanFold = true;
6028 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6029 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6030 ((InVec0.getOpcode() == ISD::UNDEF ||
6031 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6032 ((InVec1.getOpcode() == ISD::UNDEF ||
6033 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6034 X86Opcode = X86ISD::HADD;
6035 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6036 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6037 ((InVec0.getOpcode() == ISD::UNDEF ||
6038 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6039 ((InVec1.getOpcode() == ISD::UNDEF ||
6040 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6041 X86Opcode = X86ISD::HSUB;
6046 // Fold this build_vector into a single horizontal add/sub.
6047 // Do this only if the target has AVX2.
6048 if (Subtarget->hasAVX2())
6049 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6051 // Do not try to expand this build_vector into a pair of horizontal
6052 // add/sub if we can emit a pair of scalar add/sub.
6053 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6056 // Convert this build_vector into a pair of horizontal binop followed by
6058 bool isUndefLO = NumUndefsLO == Half;
6059 bool isUndefHI = NumUndefsHI == Half;
6060 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6061 isUndefLO, isUndefHI);
6065 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6066 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6068 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6069 X86Opcode = X86ISD::HADD;
6070 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6071 X86Opcode = X86ISD::HSUB;
6072 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6073 X86Opcode = X86ISD::FHADD;
6074 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6075 X86Opcode = X86ISD::FHSUB;
6079 // Don't try to expand this build_vector into a pair of horizontal add/sub
6080 // if we can simply emit a pair of scalar add/sub.
6081 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6084 // Convert this build_vector into two horizontal add/sub followed by
6086 bool isUndefLO = NumUndefsLO == Half;
6087 bool isUndefHI = NumUndefsHI == Half;
6088 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6089 isUndefLO, isUndefHI);
6096 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6099 MVT VT = Op.getSimpleValueType();
6100 MVT ExtVT = VT.getVectorElementType();
6101 unsigned NumElems = Op.getNumOperands();
6103 // Generate vectors for predicate vectors.
6104 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6105 return LowerBUILD_VECTORvXi1(Op, DAG);
6107 // Vectors containing all zeros can be matched by pxor and xorps later
6108 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6109 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6110 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6111 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6114 return getZeroVector(VT, Subtarget, DAG, dl);
6117 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6118 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6119 // vpcmpeqd on 256-bit vectors.
6120 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6121 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6124 if (!VT.is512BitVector())
6125 return getOnesVector(VT, Subtarget, DAG, dl);
6128 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6129 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6131 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6132 return HorizontalOp;
6133 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6136 unsigned EVTBits = ExtVT.getSizeInBits();
6138 unsigned NumZero = 0;
6139 unsigned NumNonZero = 0;
6140 unsigned NonZeros = 0;
6141 bool IsAllConstants = true;
6142 SmallSet<SDValue, 8> Values;
6143 for (unsigned i = 0; i < NumElems; ++i) {
6144 SDValue Elt = Op.getOperand(i);
6145 if (Elt.getOpcode() == ISD::UNDEF)
6148 if (Elt.getOpcode() != ISD::Constant &&
6149 Elt.getOpcode() != ISD::ConstantFP)
6150 IsAllConstants = false;
6151 if (X86::isZeroNode(Elt))
6154 NonZeros |= (1 << i);
6159 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6160 if (NumNonZero == 0)
6161 return DAG.getUNDEF(VT);
6163 // Special case for single non-zero, non-undef, element.
6164 if (NumNonZero == 1) {
6165 unsigned Idx = countTrailingZeros(NonZeros);
6166 SDValue Item = Op.getOperand(Idx);
6168 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6169 // the value are obviously zero, truncate the value to i32 and do the
6170 // insertion that way. Only do this if the value is non-constant or if the
6171 // value is a constant being inserted into element 0. It is cheaper to do
6172 // a constant pool load than it is to do a movd + shuffle.
6173 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6174 (!IsAllConstants || Idx == 0)) {
6175 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6177 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6178 EVT VecVT = MVT::v4i32;
6180 // Truncate the value (which may itself be a constant) to i32, and
6181 // convert it to a vector with movd (S2V+shuffle to zero extend).
6182 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6183 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6184 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6185 Item, Idx * 2, true, Subtarget, DAG));
6189 // If we have a constant or non-constant insertion into the low element of
6190 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6191 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6192 // depending on what the source datatype is.
6195 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6197 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6198 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6199 if (VT.is512BitVector()) {
6200 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6201 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6202 Item, DAG.getIntPtrConstant(0, dl));
6204 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6205 "Expected an SSE value type!");
6206 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6207 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6208 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6211 // We can't directly insert an i8 or i16 into a vector, so zero extend
6213 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6214 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6215 if (VT.is256BitVector()) {
6216 if (Subtarget->hasAVX()) {
6217 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6218 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6220 // Without AVX, we need to extend to a 128-bit vector and then
6221 // insert into the 256-bit vector.
6222 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6223 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6224 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6227 assert(VT.is128BitVector() && "Expected an SSE value type!");
6228 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6229 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6231 return DAG.getBitcast(VT, Item);
6235 // Is it a vector logical left shift?
6236 if (NumElems == 2 && Idx == 1 &&
6237 X86::isZeroNode(Op.getOperand(0)) &&
6238 !X86::isZeroNode(Op.getOperand(1))) {
6239 unsigned NumBits = VT.getSizeInBits();
6240 return getVShift(true, VT,
6241 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6242 VT, Op.getOperand(1)),
6243 NumBits/2, DAG, *this, dl);
6246 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6249 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6250 // is a non-constant being inserted into an element other than the low one,
6251 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6252 // movd/movss) to move this into the low element, then shuffle it into
6254 if (EVTBits == 32) {
6255 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6256 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6260 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6261 if (Values.size() == 1) {
6262 if (EVTBits == 32) {
6263 // Instead of a shuffle like this:
6264 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6265 // Check if it's possible to issue this instead.
6266 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6267 unsigned Idx = countTrailingZeros(NonZeros);
6268 SDValue Item = Op.getOperand(Idx);
6269 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6270 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6275 // A vector full of immediates; various special cases are already
6276 // handled, so this is best done with a single constant-pool load.
6280 // For AVX-length vectors, see if we can use a vector load to get all of the
6281 // elements, otherwise build the individual 128-bit pieces and use
6282 // shuffles to put them in place.
6283 if (VT.is256BitVector() || VT.is512BitVector()) {
6284 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6286 // Check for a build vector of consecutive loads.
6287 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6290 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6292 // Build both the lower and upper subvector.
6293 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6294 makeArrayRef(&V[0], NumElems/2));
6295 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6296 makeArrayRef(&V[NumElems / 2], NumElems/2));
6298 // Recreate the wider vector with the lower and upper part.
6299 if (VT.is256BitVector())
6300 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6301 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6304 // Let legalizer expand 2-wide build_vectors.
6305 if (EVTBits == 64) {
6306 if (NumNonZero == 1) {
6307 // One half is zero or undef.
6308 unsigned Idx = countTrailingZeros(NonZeros);
6309 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6310 Op.getOperand(Idx));
6311 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6316 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6317 if (EVTBits == 8 && NumElems == 16)
6318 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6322 if (EVTBits == 16 && NumElems == 8)
6323 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6327 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6328 if (EVTBits == 32 && NumElems == 4)
6329 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6332 // If element VT is == 32 bits, turn it into a number of shuffles.
6333 SmallVector<SDValue, 8> V(NumElems);
6334 if (NumElems == 4 && NumZero > 0) {
6335 for (unsigned i = 0; i < 4; ++i) {
6336 bool isZero = !(NonZeros & (1 << i));
6338 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6340 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6343 for (unsigned i = 0; i < 2; ++i) {
6344 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6347 V[i] = V[i*2]; // Must be a zero vector.
6350 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6353 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6356 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6361 bool Reverse1 = (NonZeros & 0x3) == 2;
6362 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6366 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6367 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6369 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6372 if (Values.size() > 1 && VT.is128BitVector()) {
6373 // Check for a build vector of consecutive loads.
6374 for (unsigned i = 0; i < NumElems; ++i)
6375 V[i] = Op.getOperand(i);
6377 // Check for elements which are consecutive loads.
6378 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6381 // Check for a build vector from mostly shuffle plus few inserting.
6382 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6385 // For SSE 4.1, use insertps to put the high elements into the low element.
6386 if (Subtarget->hasSSE41()) {
6388 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6389 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6391 Result = DAG.getUNDEF(VT);
6393 for (unsigned i = 1; i < NumElems; ++i) {
6394 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6395 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6396 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6401 // Otherwise, expand into a number of unpckl*, start by extending each of
6402 // our (non-undef) elements to the full vector width with the element in the
6403 // bottom slot of the vector (which generates no code for SSE).
6404 for (unsigned i = 0; i < NumElems; ++i) {
6405 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6406 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6408 V[i] = DAG.getUNDEF(VT);
6411 // Next, we iteratively mix elements, e.g. for v4f32:
6412 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6413 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6414 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6415 unsigned EltStride = NumElems >> 1;
6416 while (EltStride != 0) {
6417 for (unsigned i = 0; i < EltStride; ++i) {
6418 // If V[i+EltStride] is undef and this is the first round of mixing,
6419 // then it is safe to just drop this shuffle: V[i] is already in the
6420 // right place, the one element (since it's the first round) being
6421 // inserted as undef can be dropped. This isn't safe for successive
6422 // rounds because they will permute elements within both vectors.
6423 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6424 EltStride == NumElems/2)
6427 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6436 // 256-bit AVX can use the vinsertf128 instruction
6437 // to create 256-bit vectors from two other 128-bit ones.
6438 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6440 MVT ResVT = Op.getSimpleValueType();
6442 assert((ResVT.is256BitVector() ||
6443 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6445 SDValue V1 = Op.getOperand(0);
6446 SDValue V2 = Op.getOperand(1);
6447 unsigned NumElems = ResVT.getVectorNumElements();
6448 if (ResVT.is256BitVector())
6449 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6451 if (Op.getNumOperands() == 4) {
6452 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6453 ResVT.getVectorNumElements()/2);
6454 SDValue V3 = Op.getOperand(2);
6455 SDValue V4 = Op.getOperand(3);
6456 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6457 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6459 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6462 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6463 const X86Subtarget *Subtarget,
6464 SelectionDAG & DAG) {
6466 MVT ResVT = Op.getSimpleValueType();
6467 unsigned NumOfOperands = Op.getNumOperands();
6469 assert(isPowerOf2_32(NumOfOperands) &&
6470 "Unexpected number of operands in CONCAT_VECTORS");
6472 if (NumOfOperands > 2) {
6473 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6474 ResVT.getVectorNumElements()/2);
6475 SmallVector<SDValue, 2> Ops;
6476 for (unsigned i = 0; i < NumOfOperands/2; i++)
6477 Ops.push_back(Op.getOperand(i));
6478 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6480 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6481 Ops.push_back(Op.getOperand(i));
6482 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6483 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6486 SDValue V1 = Op.getOperand(0);
6487 SDValue V2 = Op.getOperand(1);
6488 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6489 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6491 if (IsZeroV1 && IsZeroV2)
6492 return getZeroVector(ResVT, Subtarget, DAG, dl);
6494 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6495 SDValue Undef = DAG.getUNDEF(ResVT);
6496 unsigned NumElems = ResVT.getVectorNumElements();
6497 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6499 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6500 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6504 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6505 // Zero the upper bits of V1
6506 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6507 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6510 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6513 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6514 const X86Subtarget *Subtarget,
6515 SelectionDAG &DAG) {
6516 MVT VT = Op.getSimpleValueType();
6517 if (VT.getVectorElementType() == MVT::i1)
6518 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6520 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6521 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6522 Op.getNumOperands() == 4)));
6524 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6525 // from two other 128-bit ones.
6527 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6528 return LowerAVXCONCAT_VECTORS(Op, DAG);
6531 //===----------------------------------------------------------------------===//
6532 // Vector shuffle lowering
6534 // This is an experimental code path for lowering vector shuffles on x86. It is
6535 // designed to handle arbitrary vector shuffles and blends, gracefully
6536 // degrading performance as necessary. It works hard to recognize idiomatic
6537 // shuffles and lower them to optimal instruction patterns without leaving
6538 // a framework that allows reasonably efficient handling of all vector shuffle
6540 //===----------------------------------------------------------------------===//
6542 /// \brief Tiny helper function to identify a no-op mask.
6544 /// This is a somewhat boring predicate function. It checks whether the mask
6545 /// array input, which is assumed to be a single-input shuffle mask of the kind
6546 /// used by the X86 shuffle instructions (not a fully general
6547 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6548 /// in-place shuffle are 'no-op's.
6549 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6550 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6551 if (Mask[i] != -1 && Mask[i] != i)
6556 /// \brief Helper function to classify a mask as a single-input mask.
6558 /// This isn't a generic single-input test because in the vector shuffle
6559 /// lowering we canonicalize single inputs to be the first input operand. This
6560 /// means we can more quickly test for a single input by only checking whether
6561 /// an input from the second operand exists. We also assume that the size of
6562 /// mask corresponds to the size of the input vectors which isn't true in the
6563 /// fully general case.
6564 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6566 if (M >= (int)Mask.size())
6571 /// \brief Test whether there are elements crossing 128-bit lanes in this
6574 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6575 /// and we routinely test for these.
6576 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6577 int LaneSize = 128 / VT.getScalarSizeInBits();
6578 int Size = Mask.size();
6579 for (int i = 0; i < Size; ++i)
6580 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6585 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6587 /// This checks a shuffle mask to see if it is performing the same
6588 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6589 /// that it is also not lane-crossing. It may however involve a blend from the
6590 /// same lane of a second vector.
6592 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6593 /// non-trivial to compute in the face of undef lanes. The representation is
6594 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6595 /// entries from both V1 and V2 inputs to the wider mask.
6597 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6598 SmallVectorImpl<int> &RepeatedMask) {
6599 int LaneSize = 128 / VT.getScalarSizeInBits();
6600 RepeatedMask.resize(LaneSize, -1);
6601 int Size = Mask.size();
6602 for (int i = 0; i < Size; ++i) {
6605 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6606 // This entry crosses lanes, so there is no way to model this shuffle.
6609 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6610 if (RepeatedMask[i % LaneSize] == -1)
6611 // This is the first non-undef entry in this slot of a 128-bit lane.
6612 RepeatedMask[i % LaneSize] =
6613 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6614 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6615 // Found a mismatch with the repeated mask.
6621 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6624 /// This is a fast way to test a shuffle mask against a fixed pattern:
6626 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6628 /// It returns true if the mask is exactly as wide as the argument list, and
6629 /// each element of the mask is either -1 (signifying undef) or the value given
6630 /// in the argument.
6631 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6632 ArrayRef<int> ExpectedMask) {
6633 if (Mask.size() != ExpectedMask.size())
6636 int Size = Mask.size();
6638 // If the values are build vectors, we can look through them to find
6639 // equivalent inputs that make the shuffles equivalent.
6640 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6641 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6643 for (int i = 0; i < Size; ++i)
6644 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6645 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6646 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6647 if (!MaskBV || !ExpectedBV ||
6648 MaskBV->getOperand(Mask[i] % Size) !=
6649 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6656 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6658 /// This helper function produces an 8-bit shuffle immediate corresponding to
6659 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6660 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6663 /// NB: We rely heavily on "undef" masks preserving the input lane.
6664 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6665 SelectionDAG &DAG) {
6666 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6667 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6668 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6669 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6670 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6673 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6674 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6675 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6676 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6677 return DAG.getConstant(Imm, DL, MVT::i8);
6680 /// \brief Compute whether each element of a shuffle is zeroable.
6682 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6683 /// Either it is an undef element in the shuffle mask, the element of the input
6684 /// referenced is undef, or the element of the input referenced is known to be
6685 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6686 /// as many lanes with this technique as possible to simplify the remaining
6688 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6689 SDValue V1, SDValue V2) {
6690 SmallBitVector Zeroable(Mask.size(), false);
6692 while (V1.getOpcode() == ISD::BITCAST)
6693 V1 = V1->getOperand(0);
6694 while (V2.getOpcode() == ISD::BITCAST)
6695 V2 = V2->getOperand(0);
6697 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6698 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6700 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6702 // Handle the easy cases.
6703 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6708 // If this is an index into a build_vector node (which has the same number
6709 // of elements), dig out the input value and use it.
6710 SDValue V = M < Size ? V1 : V2;
6711 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6714 SDValue Input = V.getOperand(M % Size);
6715 // The UNDEF opcode check really should be dead code here, but not quite
6716 // worth asserting on (it isn't invalid, just unexpected).
6717 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6724 // X86 has dedicated unpack instructions that can handle specific blend
6725 // operations: UNPCKH and UNPCKL.
6726 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6727 SDValue V1, SDValue V2,
6728 SelectionDAG &DAG) {
6729 int NumElts = VT.getVectorNumElements();
6732 bool UnpcklSwapped = true;
6733 bool UnpckhSwapped = true;
6734 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6736 for (int i = 0; i < NumElts; ++i) {
6737 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6739 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6740 int HiPos = LoPos + NumEltsInLane / 2;
6741 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6742 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6746 if (Mask[i] != LoPos)
6748 if (Mask[i] != HiPos)
6750 if (Mask[i] != LoPosSwapped)
6751 UnpcklSwapped = false;
6752 if (Mask[i] != HiPosSwapped)
6753 UnpckhSwapped = false;
6754 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6758 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6760 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6762 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6764 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6766 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6770 /// \brief Try to emit a bitmask instruction for a shuffle.
6772 /// This handles cases where we can model a blend exactly as a bitmask due to
6773 /// one of the inputs being zeroable.
6774 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6775 SDValue V2, ArrayRef<int> Mask,
6776 SelectionDAG &DAG) {
6777 MVT EltVT = VT.getScalarType();
6778 int NumEltBits = EltVT.getSizeInBits();
6779 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6780 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6781 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6783 if (EltVT.isFloatingPoint()) {
6784 Zero = DAG.getBitcast(EltVT, Zero);
6785 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6787 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6788 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6790 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6793 if (Mask[i] % Size != i)
6794 return SDValue(); // Not a blend.
6796 V = Mask[i] < Size ? V1 : V2;
6797 else if (V != (Mask[i] < Size ? V1 : V2))
6798 return SDValue(); // Can only let one input through the mask.
6800 VMaskOps[i] = AllOnes;
6803 return SDValue(); // No non-zeroable elements!
6805 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6806 V = DAG.getNode(VT.isFloatingPoint()
6807 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6812 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6814 /// This is used as a fallback approach when first class blend instructions are
6815 /// unavailable. Currently it is only suitable for integer vectors, but could
6816 /// be generalized for floating point vectors if desirable.
6817 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6818 SDValue V2, ArrayRef<int> Mask,
6819 SelectionDAG &DAG) {
6820 assert(VT.isInteger() && "Only supports integer vector types!");
6821 MVT EltVT = VT.getScalarType();
6822 int NumEltBits = EltVT.getSizeInBits();
6823 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6824 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6826 SmallVector<SDValue, 16> MaskOps;
6827 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6828 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6829 return SDValue(); // Shuffled input!
6830 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6833 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6834 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6835 // We have to cast V2 around.
6836 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6837 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6838 DAG.getBitcast(MaskVT, V1Mask),
6839 DAG.getBitcast(MaskVT, V2)));
6840 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6843 /// \brief Try to emit a blend instruction for a shuffle.
6845 /// This doesn't do any checks for the availability of instructions for blending
6846 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6847 /// be matched in the backend with the type given. What it does check for is
6848 /// that the shuffle mask is in fact a blend.
6849 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6850 SDValue V2, ArrayRef<int> Mask,
6851 const X86Subtarget *Subtarget,
6852 SelectionDAG &DAG) {
6853 unsigned BlendMask = 0;
6854 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6855 if (Mask[i] >= Size) {
6856 if (Mask[i] != i + Size)
6857 return SDValue(); // Shuffled V2 input!
6858 BlendMask |= 1u << i;
6861 if (Mask[i] >= 0 && Mask[i] != i)
6862 return SDValue(); // Shuffled V1 input!
6864 switch (VT.SimpleTy) {
6869 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6870 DAG.getConstant(BlendMask, DL, MVT::i8));
6874 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6878 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6879 // that instruction.
6880 if (Subtarget->hasAVX2()) {
6881 // Scale the blend by the number of 32-bit dwords per element.
6882 int Scale = VT.getScalarSizeInBits() / 32;
6884 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6885 if (Mask[i] >= Size)
6886 for (int j = 0; j < Scale; ++j)
6887 BlendMask |= 1u << (i * Scale + j);
6889 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6890 V1 = DAG.getBitcast(BlendVT, V1);
6891 V2 = DAG.getBitcast(BlendVT, V2);
6892 return DAG.getBitcast(
6893 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6894 DAG.getConstant(BlendMask, DL, MVT::i8)));
6898 // For integer shuffles we need to expand the mask and cast the inputs to
6899 // v8i16s prior to blending.
6900 int Scale = 8 / VT.getVectorNumElements();
6902 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6903 if (Mask[i] >= Size)
6904 for (int j = 0; j < Scale; ++j)
6905 BlendMask |= 1u << (i * Scale + j);
6907 V1 = DAG.getBitcast(MVT::v8i16, V1);
6908 V2 = DAG.getBitcast(MVT::v8i16, V2);
6909 return DAG.getBitcast(VT,
6910 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6911 DAG.getConstant(BlendMask, DL, MVT::i8)));
6915 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6916 SmallVector<int, 8> RepeatedMask;
6917 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6918 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6919 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6921 for (int i = 0; i < 8; ++i)
6922 if (RepeatedMask[i] >= 16)
6923 BlendMask |= 1u << i;
6924 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6925 DAG.getConstant(BlendMask, DL, MVT::i8));
6931 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6932 "256-bit byte-blends require AVX2 support!");
6934 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6935 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6938 // Scale the blend by the number of bytes per element.
6939 int Scale = VT.getScalarSizeInBits() / 8;
6941 // This form of blend is always done on bytes. Compute the byte vector
6943 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6945 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6946 // mix of LLVM's code generator and the x86 backend. We tell the code
6947 // generator that boolean values in the elements of an x86 vector register
6948 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6949 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6950 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6951 // of the element (the remaining are ignored) and 0 in that high bit would
6952 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6953 // the LLVM model for boolean values in vector elements gets the relevant
6954 // bit set, it is set backwards and over constrained relative to x86's
6956 SmallVector<SDValue, 32> VSELECTMask;
6957 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6958 for (int j = 0; j < Scale; ++j)
6959 VSELECTMask.push_back(
6960 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6961 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6964 V1 = DAG.getBitcast(BlendVT, V1);
6965 V2 = DAG.getBitcast(BlendVT, V2);
6966 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6967 DAG.getNode(ISD::BUILD_VECTOR, DL,
6968 BlendVT, VSELECTMask),
6973 llvm_unreachable("Not a supported integer vector type!");
6977 /// \brief Try to lower as a blend of elements from two inputs followed by
6978 /// a single-input permutation.
6980 /// This matches the pattern where we can blend elements from two inputs and
6981 /// then reduce the shuffle to a single-input permutation.
6982 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6985 SelectionDAG &DAG) {
6986 // We build up the blend mask while checking whether a blend is a viable way
6987 // to reduce the shuffle.
6988 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6989 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6991 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6995 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6997 if (BlendMask[Mask[i] % Size] == -1)
6998 BlendMask[Mask[i] % Size] = Mask[i];
6999 else if (BlendMask[Mask[i] % Size] != Mask[i])
7000 return SDValue(); // Can't blend in the needed input!
7002 PermuteMask[i] = Mask[i] % Size;
7005 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7006 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7009 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7010 /// blends and permutes.
7012 /// This matches the extremely common pattern for handling combined
7013 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7014 /// operations. It will try to pick the best arrangement of shuffles and
7016 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7020 SelectionDAG &DAG) {
7021 // Shuffle the input elements into the desired positions in V1 and V2 and
7022 // blend them together.
7023 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7024 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7025 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7026 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7027 if (Mask[i] >= 0 && Mask[i] < Size) {
7028 V1Mask[i] = Mask[i];
7030 } else if (Mask[i] >= Size) {
7031 V2Mask[i] = Mask[i] - Size;
7032 BlendMask[i] = i + Size;
7035 // Try to lower with the simpler initial blend strategy unless one of the
7036 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7037 // shuffle may be able to fold with a load or other benefit. However, when
7038 // we'll have to do 2x as many shuffles in order to achieve this, blending
7039 // first is a better strategy.
7040 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7041 if (SDValue BlendPerm =
7042 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7045 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7046 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7047 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7050 /// \brief Try to lower a vector shuffle as a byte rotation.
7052 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7053 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7054 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7055 /// try to generically lower a vector shuffle through such an pattern. It
7056 /// does not check for the profitability of lowering either as PALIGNR or
7057 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7058 /// This matches shuffle vectors that look like:
7060 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7062 /// Essentially it concatenates V1 and V2, shifts right by some number of
7063 /// elements, and takes the low elements as the result. Note that while this is
7064 /// specified as a *right shift* because x86 is little-endian, it is a *left
7065 /// rotate* of the vector lanes.
7066 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7069 const X86Subtarget *Subtarget,
7070 SelectionDAG &DAG) {
7071 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7073 int NumElts = Mask.size();
7074 int NumLanes = VT.getSizeInBits() / 128;
7075 int NumLaneElts = NumElts / NumLanes;
7077 // We need to detect various ways of spelling a rotation:
7078 // [11, 12, 13, 14, 15, 0, 1, 2]
7079 // [-1, 12, 13, 14, -1, -1, 1, -1]
7080 // [-1, -1, -1, -1, -1, -1, 1, 2]
7081 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7082 // [-1, 4, 5, 6, -1, -1, 9, -1]
7083 // [-1, 4, 5, 6, -1, -1, -1, -1]
7086 for (int l = 0; l < NumElts; l += NumLaneElts) {
7087 for (int i = 0; i < NumLaneElts; ++i) {
7088 if (Mask[l + i] == -1)
7090 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7092 // Get the mod-Size index and lane correct it.
7093 int LaneIdx = (Mask[l + i] % NumElts) - l;
7094 // Make sure it was in this lane.
7095 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7098 // Determine where a rotated vector would have started.
7099 int StartIdx = i - LaneIdx;
7101 // The identity rotation isn't interesting, stop.
7104 // If we found the tail of a vector the rotation must be the missing
7105 // front. If we found the head of a vector, it must be how much of the
7107 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7110 Rotation = CandidateRotation;
7111 else if (Rotation != CandidateRotation)
7112 // The rotations don't match, so we can't match this mask.
7115 // Compute which value this mask is pointing at.
7116 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7118 // Compute which of the two target values this index should be assigned
7119 // to. This reflects whether the high elements are remaining or the low
7120 // elements are remaining.
7121 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7123 // Either set up this value if we've not encountered it before, or check
7124 // that it remains consistent.
7127 else if (TargetV != MaskV)
7128 // This may be a rotation, but it pulls from the inputs in some
7129 // unsupported interleaving.
7134 // Check that we successfully analyzed the mask, and normalize the results.
7135 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7136 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7142 // The actual rotate instruction rotates bytes, so we need to scale the
7143 // rotation based on how many bytes are in the vector lane.
7144 int Scale = 16 / NumLaneElts;
7146 // SSSE3 targets can use the palignr instruction.
7147 if (Subtarget->hasSSSE3()) {
7148 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7149 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7150 Lo = DAG.getBitcast(AlignVT, Lo);
7151 Hi = DAG.getBitcast(AlignVT, Hi);
7153 return DAG.getBitcast(
7154 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7155 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7158 assert(VT.getSizeInBits() == 128 &&
7159 "Rotate-based lowering only supports 128-bit lowering!");
7160 assert(Mask.size() <= 16 &&
7161 "Can shuffle at most 16 bytes in a 128-bit vector!");
7163 // Default SSE2 implementation
7164 int LoByteShift = 16 - Rotation * Scale;
7165 int HiByteShift = Rotation * Scale;
7167 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7168 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7169 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7171 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7172 DAG.getConstant(LoByteShift, DL, MVT::i8));
7173 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7174 DAG.getConstant(HiByteShift, DL, MVT::i8));
7175 return DAG.getBitcast(VT,
7176 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7179 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7181 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7182 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7183 /// matches elements from one of the input vectors shuffled to the left or
7184 /// right with zeroable elements 'shifted in'. It handles both the strictly
7185 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7188 /// PSHL : (little-endian) left bit shift.
7189 /// [ zz, 0, zz, 2 ]
7190 /// [ -1, 4, zz, -1 ]
7191 /// PSRL : (little-endian) right bit shift.
7193 /// [ -1, -1, 7, zz]
7194 /// PSLLDQ : (little-endian) left byte shift
7195 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7196 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7197 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7198 /// PSRLDQ : (little-endian) right byte shift
7199 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7200 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7201 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7202 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7203 SDValue V2, ArrayRef<int> Mask,
7204 SelectionDAG &DAG) {
7205 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7207 int Size = Mask.size();
7208 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7210 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7211 for (int i = 0; i < Size; i += Scale)
7212 for (int j = 0; j < Shift; ++j)
7213 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7219 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7220 for (int i = 0; i != Size; i += Scale) {
7221 unsigned Pos = Left ? i + Shift : i;
7222 unsigned Low = Left ? i : i + Shift;
7223 unsigned Len = Scale - Shift;
7224 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7225 Low + (V == V1 ? 0 : Size)))
7229 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7230 bool ByteShift = ShiftEltBits > 64;
7231 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7232 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7233 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7235 // Normalize the scale for byte shifts to still produce an i64 element
7237 Scale = ByteShift ? Scale / 2 : Scale;
7239 // We need to round trip through the appropriate type for the shift.
7240 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7241 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7242 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7243 "Illegal integer vector type");
7244 V = DAG.getBitcast(ShiftVT, V);
7246 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7247 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7248 return DAG.getBitcast(VT, V);
7251 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7252 // keep doubling the size of the integer elements up to that. We can
7253 // then shift the elements of the integer vector by whole multiples of
7254 // their width within the elements of the larger integer vector. Test each
7255 // multiple to see if we can find a match with the moved element indices
7256 // and that the shifted in elements are all zeroable.
7257 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7258 for (int Shift = 1; Shift != Scale; ++Shift)
7259 for (bool Left : {true, false})
7260 if (CheckZeros(Shift, Scale, Left))
7261 for (SDValue V : {V1, V2})
7262 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7269 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7270 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7271 SDValue V2, ArrayRef<int> Mask,
7272 SelectionDAG &DAG) {
7273 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7274 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7276 int Size = Mask.size();
7277 int HalfSize = Size / 2;
7278 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7280 // Upper half must be undefined.
7281 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7284 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7285 // Remainder of lower half result is zero and upper half is all undef.
7286 auto LowerAsEXTRQ = [&]() {
7287 // Determine the extraction length from the part of the
7288 // lower half that isn't zeroable.
7290 for (; Len >= 0; --Len)
7291 if (!Zeroable[Len - 1])
7293 assert(Len > 0 && "Zeroable shuffle mask");
7295 // Attempt to match first Len sequential elements from the lower half.
7298 for (int i = 0; i != Len; ++i) {
7302 SDValue &V = (M < Size ? V1 : V2);
7305 // All mask elements must be in the lower half.
7309 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7320 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7321 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7322 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7323 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7324 DAG.getConstant(BitLen, DL, MVT::i8),
7325 DAG.getConstant(BitIdx, DL, MVT::i8));
7328 if (SDValue ExtrQ = LowerAsEXTRQ())
7331 // INSERTQ: Extract lowest Len elements from lower half of second source and
7332 // insert over first source, starting at Idx.
7333 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7334 auto LowerAsInsertQ = [&]() {
7335 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7338 // Attempt to match first source from mask before insertion point.
7339 if (isUndefInRange(Mask, 0, Idx)) {
7341 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7343 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7349 // Extend the extraction length looking to match both the insertion of
7350 // the second source and the remaining elements of the first.
7351 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7356 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7358 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7364 // Match the remaining elements of the lower half.
7365 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7367 } else if ((!Base || (Base == V1)) &&
7368 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7370 } else if ((!Base || (Base == V2)) &&
7371 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7378 // We may not have a base (first source) - this can safely be undefined.
7380 Base = DAG.getUNDEF(VT);
7382 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7383 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7384 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7385 DAG.getConstant(BitLen, DL, MVT::i8),
7386 DAG.getConstant(BitIdx, DL, MVT::i8));
7393 if (SDValue InsertQ = LowerAsInsertQ())
7399 /// \brief Lower a vector shuffle as a zero or any extension.
7401 /// Given a specific number of elements, element bit width, and extension
7402 /// stride, produce either a zero or any extension based on the available
7403 /// features of the subtarget. The extended elements are consecutive and
7404 /// begin and can start from an offseted element index in the input; to
7405 /// avoid excess shuffling the offset must either being in the bottom lane
7406 /// or at the start of a higher lane. All extended elements must be from
7408 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7409 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7410 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7411 assert(Scale > 1 && "Need a scale to extend.");
7412 int EltBits = VT.getScalarSizeInBits();
7413 int NumElements = VT.getVectorNumElements();
7414 int NumEltsPerLane = 128 / EltBits;
7415 int OffsetLane = Offset / NumEltsPerLane;
7416 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7417 "Only 8, 16, and 32 bit elements can be extended.");
7418 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7419 assert(0 <= Offset && "Extension offset must be positive.");
7420 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7421 "Extension offset must be in the first lane or start an upper lane.");
7423 // Check that an index is in same lane as the base offset.
7424 auto SafeOffset = [&](int Idx) {
7425 return OffsetLane == (Idx / NumEltsPerLane);
7428 // Shift along an input so that the offset base moves to the first element.
7429 auto ShuffleOffset = [&](SDValue V) {
7433 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7434 for (int i = 0; i * Scale < NumElements; ++i) {
7435 int SrcIdx = i + Offset;
7436 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7438 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7441 // Found a valid zext mask! Try various lowering strategies based on the
7442 // input type and available ISA extensions.
7443 if (Subtarget->hasSSE41()) {
7444 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7445 // PUNPCK will catch this in a later shuffle match.
7446 if (Offset && Scale == 2 && VT.getSizeInBits() == 128)
7448 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7449 NumElements / Scale);
7450 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7451 return DAG.getBitcast(VT, InputV);
7454 assert(VT.getSizeInBits() == 128 && "Only 128-bit vectors can be extended.");
7456 // For any extends we can cheat for larger element sizes and use shuffle
7457 // instructions that can fold with a load and/or copy.
7458 if (AnyExt && EltBits == 32) {
7459 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7461 return DAG.getBitcast(
7462 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7463 DAG.getBitcast(MVT::v4i32, InputV),
7464 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7466 if (AnyExt && EltBits == 16 && Scale > 2) {
7467 int PSHUFDMask[4] = {Offset / 2, -1,
7468 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7469 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7470 DAG.getBitcast(MVT::v4i32, InputV),
7471 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7472 int PSHUFWMask[4] = {1, -1, -1, -1};
7473 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7474 return DAG.getBitcast(
7475 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7476 DAG.getBitcast(MVT::v8i16, InputV),
7477 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7480 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7482 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7483 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7484 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7486 int LoIdx = Offset * EltBits;
7487 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7488 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7489 DAG.getConstant(EltBits, DL, MVT::i8),
7490 DAG.getConstant(LoIdx, DL, MVT::i8)));
7492 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7493 !SafeOffset(Offset + 1))
7494 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7496 int HiIdx = (Offset + 1) * EltBits;
7497 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7498 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7499 DAG.getConstant(EltBits, DL, MVT::i8),
7500 DAG.getConstant(HiIdx, DL, MVT::i8)));
7501 return DAG.getNode(ISD::BITCAST, DL, VT,
7502 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7505 // If this would require more than 2 unpack instructions to expand, use
7506 // pshufb when available. We can only use more than 2 unpack instructions
7507 // when zero extending i8 elements which also makes it easier to use pshufb.
7508 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7509 assert(NumElements == 16 && "Unexpected byte vector width!");
7510 SDValue PSHUFBMask[16];
7511 for (int i = 0; i < 16; ++i) {
7512 int Idx = Offset + (i / Scale);
7513 PSHUFBMask[i] = DAG.getConstant(
7514 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7516 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7517 return DAG.getBitcast(VT,
7518 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7519 DAG.getNode(ISD::BUILD_VECTOR, DL,
7520 MVT::v16i8, PSHUFBMask)));
7523 // If we are extending from an offset, ensure we start on a boundary that
7524 // we can unpack from.
7525 int AlignToUnpack = Offset % (NumElements / Scale);
7526 if (AlignToUnpack) {
7527 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7528 for (int i = AlignToUnpack; i < NumElements; ++i)
7529 ShMask[i - AlignToUnpack] = i;
7530 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7531 Offset -= AlignToUnpack;
7534 // Otherwise emit a sequence of unpacks.
7536 unsigned UnpackLoHi = X86ISD::UNPCKL;
7537 if (Offset >= (NumElements / 2)) {
7538 UnpackLoHi = X86ISD::UNPCKH;
7539 Offset -= (NumElements / 2);
7542 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7543 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7544 : getZeroVector(InputVT, Subtarget, DAG, DL);
7545 InputV = DAG.getBitcast(InputVT, InputV);
7546 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7550 } while (Scale > 1);
7551 return DAG.getBitcast(VT, InputV);
7554 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7556 /// This routine will try to do everything in its power to cleverly lower
7557 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7558 /// check for the profitability of this lowering, it tries to aggressively
7559 /// match this pattern. It will use all of the micro-architectural details it
7560 /// can to emit an efficient lowering. It handles both blends with all-zero
7561 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7562 /// masking out later).
7564 /// The reason we have dedicated lowering for zext-style shuffles is that they
7565 /// are both incredibly common and often quite performance sensitive.
7566 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7567 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7568 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7569 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7571 int Bits = VT.getSizeInBits();
7572 int NumLanes = Bits / 128;
7573 int NumElements = VT.getVectorNumElements();
7574 int NumEltsPerLane = NumElements / NumLanes;
7575 assert(VT.getScalarSizeInBits() <= 32 &&
7576 "Exceeds 32-bit integer zero extension limit");
7577 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7579 // Define a helper function to check a particular ext-scale and lower to it if
7581 auto Lower = [&](int Scale) -> SDValue {
7586 for (int i = 0; i < NumElements; ++i) {
7589 continue; // Valid anywhere but doesn't tell us anything.
7590 if (i % Scale != 0) {
7591 // Each of the extended elements need to be zeroable.
7595 // We no longer are in the anyext case.
7600 // Each of the base elements needs to be consecutive indices into the
7601 // same input vector.
7602 SDValue V = M < NumElements ? V1 : V2;
7603 M = M % NumElements;
7606 Offset = M - (i / Scale);
7607 } else if (InputV != V)
7608 return SDValue(); // Flip-flopping inputs.
7610 // Offset must start in the lowest 128-bit lane or at the start of an
7612 // FIXME: Is it ever worth allowing a negative base offset?
7613 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7614 (Offset % NumEltsPerLane) == 0))
7617 // If we are offsetting, all referenced entries must come from the same
7619 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7622 if ((M % NumElements) != (Offset + (i / Scale)))
7623 return SDValue(); // Non-consecutive strided elements.
7627 // If we fail to find an input, we have a zero-shuffle which should always
7628 // have already been handled.
7629 // FIXME: Maybe handle this here in case during blending we end up with one?
7633 // If we are offsetting, don't extend if we only match a single input, we
7634 // can always do better by using a basic PSHUF or PUNPCK.
7635 if (Offset != 0 && Matches < 2)
7638 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7639 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7642 // The widest scale possible for extending is to a 64-bit integer.
7643 assert(Bits % 64 == 0 &&
7644 "The number of bits in a vector must be divisible by 64 on x86!");
7645 int NumExtElements = Bits / 64;
7647 // Each iteration, try extending the elements half as much, but into twice as
7649 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7650 assert(NumElements % NumExtElements == 0 &&
7651 "The input vector size must be divisible by the extended size.");
7652 if (SDValue V = Lower(NumElements / NumExtElements))
7656 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7660 // Returns one of the source operands if the shuffle can be reduced to a
7661 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7662 auto CanZExtLowHalf = [&]() {
7663 for (int i = NumElements / 2; i != NumElements; ++i)
7666 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7668 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7673 if (SDValue V = CanZExtLowHalf()) {
7674 V = DAG.getBitcast(MVT::v2i64, V);
7675 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7676 return DAG.getBitcast(VT, V);
7679 // No viable ext lowering found.
7683 /// \brief Try to get a scalar value for a specific element of a vector.
7685 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7686 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7687 SelectionDAG &DAG) {
7688 MVT VT = V.getSimpleValueType();
7689 MVT EltVT = VT.getVectorElementType();
7690 while (V.getOpcode() == ISD::BITCAST)
7691 V = V.getOperand(0);
7692 // If the bitcasts shift the element size, we can't extract an equivalent
7694 MVT NewVT = V.getSimpleValueType();
7695 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7698 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7699 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7700 // Ensure the scalar operand is the same size as the destination.
7701 // FIXME: Add support for scalar truncation where possible.
7702 SDValue S = V.getOperand(Idx);
7703 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7704 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7710 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7712 /// This is particularly important because the set of instructions varies
7713 /// significantly based on whether the operand is a load or not.
7714 static bool isShuffleFoldableLoad(SDValue V) {
7715 while (V.getOpcode() == ISD::BITCAST)
7716 V = V.getOperand(0);
7718 return ISD::isNON_EXTLoad(V.getNode());
7721 /// \brief Try to lower insertion of a single element into a zero vector.
7723 /// This is a common pattern that we have especially efficient patterns to lower
7724 /// across all subtarget feature sets.
7725 static SDValue lowerVectorShuffleAsElementInsertion(
7726 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7727 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7728 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7730 MVT EltVT = VT.getVectorElementType();
7732 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7733 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7735 bool IsV1Zeroable = true;
7736 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7737 if (i != V2Index && !Zeroable[i]) {
7738 IsV1Zeroable = false;
7742 // Check for a single input from a SCALAR_TO_VECTOR node.
7743 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7744 // all the smarts here sunk into that routine. However, the current
7745 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7746 // vector shuffle lowering is dead.
7747 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7749 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7750 // We need to zext the scalar if it is smaller than an i32.
7751 V2S = DAG.getBitcast(EltVT, V2S);
7752 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7753 // Using zext to expand a narrow element won't work for non-zero
7758 // Zero-extend directly to i32.
7760 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7762 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7763 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7764 EltVT == MVT::i16) {
7765 // Either not inserting from the low element of the input or the input
7766 // element size is too small to use VZEXT_MOVL to clear the high bits.
7770 if (!IsV1Zeroable) {
7771 // If V1 can't be treated as a zero vector we have fewer options to lower
7772 // this. We can't support integer vectors or non-zero targets cheaply, and
7773 // the V1 elements can't be permuted in any way.
7774 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7775 if (!VT.isFloatingPoint() || V2Index != 0)
7777 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7778 V1Mask[V2Index] = -1;
7779 if (!isNoopShuffleMask(V1Mask))
7781 // This is essentially a special case blend operation, but if we have
7782 // general purpose blend operations, they are always faster. Bail and let
7783 // the rest of the lowering handle these as blends.
7784 if (Subtarget->hasSSE41())
7787 // Otherwise, use MOVSD or MOVSS.
7788 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7789 "Only two types of floating point element types to handle!");
7790 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7794 // This lowering only works for the low element with floating point vectors.
7795 if (VT.isFloatingPoint() && V2Index != 0)
7798 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7800 V2 = DAG.getBitcast(VT, V2);
7803 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7804 // the desired position. Otherwise it is more efficient to do a vector
7805 // shift left. We know that we can do a vector shift left because all
7806 // the inputs are zero.
7807 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7808 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7809 V2Shuffle[V2Index] = 0;
7810 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7812 V2 = DAG.getBitcast(MVT::v2i64, V2);
7814 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7815 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7816 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7817 DAG.getDataLayout(), VT)));
7818 V2 = DAG.getBitcast(VT, V2);
7824 /// \brief Try to lower broadcast of a single element.
7826 /// For convenience, this code also bundles all of the subtarget feature set
7827 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7828 /// a convenient way to factor it out.
7829 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7831 const X86Subtarget *Subtarget,
7832 SelectionDAG &DAG) {
7833 if (!Subtarget->hasAVX())
7835 if (VT.isInteger() && !Subtarget->hasAVX2())
7838 // Check that the mask is a broadcast.
7839 int BroadcastIdx = -1;
7841 if (M >= 0 && BroadcastIdx == -1)
7843 else if (M >= 0 && M != BroadcastIdx)
7846 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7847 "a sorted mask where the broadcast "
7850 // Go up the chain of (vector) values to find a scalar load that we can
7851 // combine with the broadcast.
7853 switch (V.getOpcode()) {
7854 case ISD::CONCAT_VECTORS: {
7855 int OperandSize = Mask.size() / V.getNumOperands();
7856 V = V.getOperand(BroadcastIdx / OperandSize);
7857 BroadcastIdx %= OperandSize;
7861 case ISD::INSERT_SUBVECTOR: {
7862 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7863 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7867 int BeginIdx = (int)ConstantIdx->getZExtValue();
7869 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7870 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7871 BroadcastIdx -= BeginIdx;
7882 // Check if this is a broadcast of a scalar. We special case lowering
7883 // for scalars so that we can more effectively fold with loads.
7884 // First, look through bitcast: if the original value has a larger element
7885 // type than the shuffle, the broadcast element is in essence truncated.
7886 // Make that explicit to ease folding.
7887 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7888 EVT EltVT = VT.getVectorElementType();
7889 SDValue V0 = V.getOperand(0);
7890 EVT V0VT = V0.getValueType();
7892 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7893 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7894 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7895 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7900 // Also check the simpler case, where we can directly reuse the scalar.
7901 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7902 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7903 V = V.getOperand(BroadcastIdx);
7905 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7906 // Only AVX2 has register broadcasts.
7907 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7909 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7910 // We can't broadcast from a vector register without AVX2, and we can only
7911 // broadcast from the zero-element of a vector register.
7915 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7918 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7919 // INSERTPS when the V1 elements are already in the correct locations
7920 // because otherwise we can just always use two SHUFPS instructions which
7921 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7922 // perform INSERTPS if a single V1 element is out of place and all V2
7923 // elements are zeroable.
7924 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7926 SelectionDAG &DAG) {
7927 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7928 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7929 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7930 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7932 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7935 int V1DstIndex = -1;
7936 int V2DstIndex = -1;
7937 bool V1UsedInPlace = false;
7939 for (int i = 0; i < 4; ++i) {
7940 // Synthesize a zero mask from the zeroable elements (includes undefs).
7946 // Flag if we use any V1 inputs in place.
7948 V1UsedInPlace = true;
7952 // We can only insert a single non-zeroable element.
7953 if (V1DstIndex != -1 || V2DstIndex != -1)
7957 // V1 input out of place for insertion.
7960 // V2 input for insertion.
7965 // Don't bother if we have no (non-zeroable) element for insertion.
7966 if (V1DstIndex == -1 && V2DstIndex == -1)
7969 // Determine element insertion src/dst indices. The src index is from the
7970 // start of the inserted vector, not the start of the concatenated vector.
7971 unsigned V2SrcIndex = 0;
7972 if (V1DstIndex != -1) {
7973 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7974 // and don't use the original V2 at all.
7975 V2SrcIndex = Mask[V1DstIndex];
7976 V2DstIndex = V1DstIndex;
7979 V2SrcIndex = Mask[V2DstIndex] - 4;
7982 // If no V1 inputs are used in place, then the result is created only from
7983 // the zero mask and the V2 insertion - so remove V1 dependency.
7985 V1 = DAG.getUNDEF(MVT::v4f32);
7987 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7988 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7990 // Insert the V2 element into the desired position.
7992 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7993 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7996 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7997 /// UNPCK instruction.
7999 /// This specifically targets cases where we end up with alternating between
8000 /// the two inputs, and so can permute them into something that feeds a single
8001 /// UNPCK instruction. Note that this routine only targets integer vectors
8002 /// because for floating point vectors we have a generalized SHUFPS lowering
8003 /// strategy that handles everything that doesn't *exactly* match an unpack,
8004 /// making this clever lowering unnecessary.
8005 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8006 SDValue V1, SDValue V2,
8008 SelectionDAG &DAG) {
8009 assert(!VT.isFloatingPoint() &&
8010 "This routine only supports integer vectors.");
8011 assert(!isSingleInputShuffleMask(Mask) &&
8012 "This routine should only be used when blending two inputs.");
8013 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8015 int Size = Mask.size();
8017 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8018 return M >= 0 && M % Size < Size / 2;
8020 int NumHiInputs = std::count_if(
8021 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8023 bool UnpackLo = NumLoInputs >= NumHiInputs;
8025 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8026 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8027 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8029 for (int i = 0; i < Size; ++i) {
8033 // Each element of the unpack contains Scale elements from this mask.
8034 int UnpackIdx = i / Scale;
8036 // We only handle the case where V1 feeds the first slots of the unpack.
8037 // We rely on canonicalization to ensure this is the case.
8038 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8041 // Setup the mask for this input. The indexing is tricky as we have to
8042 // handle the unpack stride.
8043 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8044 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8048 // If we will have to shuffle both inputs to use the unpack, check whether
8049 // we can just unpack first and shuffle the result. If so, skip this unpack.
8050 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8051 !isNoopShuffleMask(V2Mask))
8054 // Shuffle the inputs into place.
8055 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8056 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8058 // Cast the inputs to the type we will use to unpack them.
8059 V1 = DAG.getBitcast(UnpackVT, V1);
8060 V2 = DAG.getBitcast(UnpackVT, V2);
8062 // Unpack the inputs and cast the result back to the desired type.
8063 return DAG.getBitcast(
8064 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8068 // We try each unpack from the largest to the smallest to try and find one
8069 // that fits this mask.
8070 int OrigNumElements = VT.getVectorNumElements();
8071 int OrigScalarSize = VT.getScalarSizeInBits();
8072 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8073 int Scale = ScalarSize / OrigScalarSize;
8074 int NumElements = OrigNumElements / Scale;
8075 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8076 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8080 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8082 if (NumLoInputs == 0 || NumHiInputs == 0) {
8083 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8084 "We have to have *some* inputs!");
8085 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8087 // FIXME: We could consider the total complexity of the permute of each
8088 // possible unpacking. Or at the least we should consider how many
8089 // half-crossings are created.
8090 // FIXME: We could consider commuting the unpacks.
8092 SmallVector<int, 32> PermMask;
8093 PermMask.assign(Size, -1);
8094 for (int i = 0; i < Size; ++i) {
8098 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8101 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8103 return DAG.getVectorShuffle(
8104 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8106 DAG.getUNDEF(VT), PermMask);
8112 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8114 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8115 /// support for floating point shuffles but not integer shuffles. These
8116 /// instructions will incur a domain crossing penalty on some chips though so
8117 /// it is better to avoid lowering through this for integer vectors where
8119 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8120 const X86Subtarget *Subtarget,
8121 SelectionDAG &DAG) {
8123 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8124 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8125 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8126 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8127 ArrayRef<int> Mask = SVOp->getMask();
8128 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8130 if (isSingleInputShuffleMask(Mask)) {
8131 // Use low duplicate instructions for masks that match their pattern.
8132 if (Subtarget->hasSSE3())
8133 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8134 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8136 // Straight shuffle of a single input vector. Simulate this by using the
8137 // single input as both of the "inputs" to this instruction..
8138 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8140 if (Subtarget->hasAVX()) {
8141 // If we have AVX, we can use VPERMILPS which will allow folding a load
8142 // into the shuffle.
8143 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8144 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8147 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8148 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8150 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8151 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8153 // If we have a single input, insert that into V1 if we can do so cheaply.
8154 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8155 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8156 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8158 // Try inverting the insertion since for v2 masks it is easy to do and we
8159 // can't reliably sort the mask one way or the other.
8160 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8161 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8162 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8163 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8167 // Try to use one of the special instruction patterns to handle two common
8168 // blend patterns if a zero-blend above didn't work.
8169 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8170 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8171 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8172 // We can either use a special instruction to load over the low double or
8173 // to move just the low double.
8175 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8177 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8179 if (Subtarget->hasSSE41())
8180 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8184 // Use dedicated unpack instructions for masks that match their pattern.
8185 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8186 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8187 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8188 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8190 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8191 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8192 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8195 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8197 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8198 /// the integer unit to minimize domain crossing penalties. However, for blends
8199 /// it falls back to the floating point shuffle operation with appropriate bit
8201 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8202 const X86Subtarget *Subtarget,
8203 SelectionDAG &DAG) {
8205 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8206 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8207 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8208 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8209 ArrayRef<int> Mask = SVOp->getMask();
8210 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8212 if (isSingleInputShuffleMask(Mask)) {
8213 // Check for being able to broadcast a single element.
8214 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8215 Mask, Subtarget, DAG))
8218 // Straight shuffle of a single input vector. For everything from SSE2
8219 // onward this has a single fast instruction with no scary immediates.
8220 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8221 V1 = DAG.getBitcast(MVT::v4i32, V1);
8222 int WidenedMask[4] = {
8223 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8224 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8225 return DAG.getBitcast(
8227 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8228 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8230 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8231 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8232 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8233 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8235 // If we have a blend of two PACKUS operations an the blend aligns with the
8236 // low and half halves, we can just merge the PACKUS operations. This is
8237 // particularly important as it lets us merge shuffles that this routine itself
8239 auto GetPackNode = [](SDValue V) {
8240 while (V.getOpcode() == ISD::BITCAST)
8241 V = V.getOperand(0);
8243 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8245 if (SDValue V1Pack = GetPackNode(V1))
8246 if (SDValue V2Pack = GetPackNode(V2))
8247 return DAG.getBitcast(MVT::v2i64,
8248 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8249 Mask[0] == 0 ? V1Pack.getOperand(0)
8250 : V1Pack.getOperand(1),
8251 Mask[1] == 2 ? V2Pack.getOperand(0)
8252 : V2Pack.getOperand(1)));
8254 // Try to use shift instructions.
8256 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8259 // When loading a scalar and then shuffling it into a vector we can often do
8260 // the insertion cheaply.
8261 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8262 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8264 // Try inverting the insertion since for v2 masks it is easy to do and we
8265 // can't reliably sort the mask one way or the other.
8266 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8267 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8268 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8271 // We have different paths for blend lowering, but they all must use the
8272 // *exact* same predicate.
8273 bool IsBlendSupported = Subtarget->hasSSE41();
8274 if (IsBlendSupported)
8275 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8279 // Use dedicated unpack instructions for masks that match their pattern.
8280 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8281 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8282 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8283 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8285 // Try to use byte rotation instructions.
8286 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8287 if (Subtarget->hasSSSE3())
8288 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8289 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8292 // If we have direct support for blends, we should lower by decomposing into
8293 // a permute. That will be faster than the domain cross.
8294 if (IsBlendSupported)
8295 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8298 // We implement this with SHUFPD which is pretty lame because it will likely
8299 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8300 // However, all the alternatives are still more cycles and newer chips don't
8301 // have this problem. It would be really nice if x86 had better shuffles here.
8302 V1 = DAG.getBitcast(MVT::v2f64, V1);
8303 V2 = DAG.getBitcast(MVT::v2f64, V2);
8304 return DAG.getBitcast(MVT::v2i64,
8305 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8308 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8310 /// This is used to disable more specialized lowerings when the shufps lowering
8311 /// will happen to be efficient.
8312 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8313 // This routine only handles 128-bit shufps.
8314 assert(Mask.size() == 4 && "Unsupported mask size!");
8316 // To lower with a single SHUFPS we need to have the low half and high half
8317 // each requiring a single input.
8318 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8320 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8326 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8328 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8329 /// It makes no assumptions about whether this is the *best* lowering, it simply
8331 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8332 ArrayRef<int> Mask, SDValue V1,
8333 SDValue V2, SelectionDAG &DAG) {
8334 SDValue LowV = V1, HighV = V2;
8335 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8338 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8340 if (NumV2Elements == 1) {
8342 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8345 // Compute the index adjacent to V2Index and in the same half by toggling
8347 int V2AdjIndex = V2Index ^ 1;
8349 if (Mask[V2AdjIndex] == -1) {
8350 // Handles all the cases where we have a single V2 element and an undef.
8351 // This will only ever happen in the high lanes because we commute the
8352 // vector otherwise.
8354 std::swap(LowV, HighV);
8355 NewMask[V2Index] -= 4;
8357 // Handle the case where the V2 element ends up adjacent to a V1 element.
8358 // To make this work, blend them together as the first step.
8359 int V1Index = V2AdjIndex;
8360 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8361 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8362 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8364 // Now proceed to reconstruct the final blend as we have the necessary
8365 // high or low half formed.
8372 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8373 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8375 } else if (NumV2Elements == 2) {
8376 if (Mask[0] < 4 && Mask[1] < 4) {
8377 // Handle the easy case where we have V1 in the low lanes and V2 in the
8381 } else if (Mask[2] < 4 && Mask[3] < 4) {
8382 // We also handle the reversed case because this utility may get called
8383 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8384 // arrange things in the right direction.
8390 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8391 // trying to place elements directly, just blend them and set up the final
8392 // shuffle to place them.
8394 // The first two blend mask elements are for V1, the second two are for
8396 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8397 Mask[2] < 4 ? Mask[2] : Mask[3],
8398 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8399 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8400 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8401 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8403 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8406 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8407 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8408 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8409 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8412 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8413 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8416 /// \brief Lower 4-lane 32-bit floating point shuffles.
8418 /// Uses instructions exclusively from the floating point unit to minimize
8419 /// domain crossing penalties, as these are sufficient to implement all v4f32
8421 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8422 const X86Subtarget *Subtarget,
8423 SelectionDAG &DAG) {
8425 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8426 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8427 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8428 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8429 ArrayRef<int> Mask = SVOp->getMask();
8430 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8433 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8435 if (NumV2Elements == 0) {
8436 // Check for being able to broadcast a single element.
8437 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8438 Mask, Subtarget, DAG))
8441 // Use even/odd duplicate instructions for masks that match their pattern.
8442 if (Subtarget->hasSSE3()) {
8443 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8444 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8445 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8446 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8449 if (Subtarget->hasAVX()) {
8450 // If we have AVX, we can use VPERMILPS which will allow folding a load
8451 // into the shuffle.
8452 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8453 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8456 // Otherwise, use a straight shuffle of a single input vector. We pass the
8457 // input vector to both operands to simulate this with a SHUFPS.
8458 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8459 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8462 // There are special ways we can lower some single-element blends. However, we
8463 // have custom ways we can lower more complex single-element blends below that
8464 // we defer to if both this and BLENDPS fail to match, so restrict this to
8465 // when the V2 input is targeting element 0 of the mask -- that is the fast
8467 if (NumV2Elements == 1 && Mask[0] >= 4)
8468 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8469 Mask, Subtarget, DAG))
8472 if (Subtarget->hasSSE41()) {
8473 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8477 // Use INSERTPS if we can complete the shuffle efficiently.
8478 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8481 if (!isSingleSHUFPSMask(Mask))
8482 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8483 DL, MVT::v4f32, V1, V2, Mask, DAG))
8487 // Use dedicated unpack instructions for masks that match their pattern.
8488 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8489 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8490 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8491 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8492 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8493 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8494 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8495 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8497 // Otherwise fall back to a SHUFPS lowering strategy.
8498 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8501 /// \brief Lower 4-lane i32 vector shuffles.
8503 /// We try to handle these with integer-domain shuffles where we can, but for
8504 /// blends we use the floating point domain blend instructions.
8505 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8506 const X86Subtarget *Subtarget,
8507 SelectionDAG &DAG) {
8509 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8510 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8511 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8512 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8513 ArrayRef<int> Mask = SVOp->getMask();
8514 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8516 // Whenever we can lower this as a zext, that instruction is strictly faster
8517 // than any alternative. It also allows us to fold memory operands into the
8518 // shuffle in many cases.
8519 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8520 Mask, Subtarget, DAG))
8524 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8526 if (NumV2Elements == 0) {
8527 // Check for being able to broadcast a single element.
8528 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8529 Mask, Subtarget, DAG))
8532 // Straight shuffle of a single input vector. For everything from SSE2
8533 // onward this has a single fast instruction with no scary immediates.
8534 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8535 // but we aren't actually going to use the UNPCK instruction because doing
8536 // so prevents folding a load into this instruction or making a copy.
8537 const int UnpackLoMask[] = {0, 0, 1, 1};
8538 const int UnpackHiMask[] = {2, 2, 3, 3};
8539 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8540 Mask = UnpackLoMask;
8541 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8542 Mask = UnpackHiMask;
8544 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8545 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8548 // Try to use shift instructions.
8550 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8553 // There are special ways we can lower some single-element blends.
8554 if (NumV2Elements == 1)
8555 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8556 Mask, Subtarget, DAG))
8559 // We have different paths for blend lowering, but they all must use the
8560 // *exact* same predicate.
8561 bool IsBlendSupported = Subtarget->hasSSE41();
8562 if (IsBlendSupported)
8563 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8567 if (SDValue Masked =
8568 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8571 // Use dedicated unpack instructions for masks that match their pattern.
8572 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8573 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8574 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8575 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8576 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8577 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8578 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8579 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8581 // Try to use byte rotation instructions.
8582 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8583 if (Subtarget->hasSSSE3())
8584 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8585 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8588 // If we have direct support for blends, we should lower by decomposing into
8589 // a permute. That will be faster than the domain cross.
8590 if (IsBlendSupported)
8591 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8594 // Try to lower by permuting the inputs into an unpack instruction.
8595 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8599 // We implement this with SHUFPS because it can blend from two vectors.
8600 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8601 // up the inputs, bypassing domain shift penalties that we would encur if we
8602 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8604 return DAG.getBitcast(
8606 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8607 DAG.getBitcast(MVT::v4f32, V2), Mask));
8610 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8611 /// shuffle lowering, and the most complex part.
8613 /// The lowering strategy is to try to form pairs of input lanes which are
8614 /// targeted at the same half of the final vector, and then use a dword shuffle
8615 /// to place them onto the right half, and finally unpack the paired lanes into
8616 /// their final position.
8618 /// The exact breakdown of how to form these dword pairs and align them on the
8619 /// correct sides is really tricky. See the comments within the function for
8620 /// more of the details.
8622 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8623 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8624 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8625 /// vector, form the analogous 128-bit 8-element Mask.
8626 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8627 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8628 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8629 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8630 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8632 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8633 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8634 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8636 SmallVector<int, 4> LoInputs;
8637 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8638 [](int M) { return M >= 0; });
8639 std::sort(LoInputs.begin(), LoInputs.end());
8640 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8641 SmallVector<int, 4> HiInputs;
8642 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8643 [](int M) { return M >= 0; });
8644 std::sort(HiInputs.begin(), HiInputs.end());
8645 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8647 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8648 int NumHToL = LoInputs.size() - NumLToL;
8650 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8651 int NumHToH = HiInputs.size() - NumLToH;
8652 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8653 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8654 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8655 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8657 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8658 // such inputs we can swap two of the dwords across the half mark and end up
8659 // with <=2 inputs to each half in each half. Once there, we can fall through
8660 // to the generic code below. For example:
8662 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8663 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8665 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8666 // and an existing 2-into-2 on the other half. In this case we may have to
8667 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8668 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8669 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8670 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8671 // half than the one we target for fixing) will be fixed when we re-enter this
8672 // path. We will also combine away any sequence of PSHUFD instructions that
8673 // result into a single instruction. Here is an example of the tricky case:
8675 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8676 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8678 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8680 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8681 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8683 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8684 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8686 // The result is fine to be handled by the generic logic.
8687 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8688 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8689 int AOffset, int BOffset) {
8690 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8691 "Must call this with A having 3 or 1 inputs from the A half.");
8692 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8693 "Must call this with B having 1 or 3 inputs from the B half.");
8694 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8695 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8697 bool ThreeAInputs = AToAInputs.size() == 3;
8699 // Compute the index of dword with only one word among the three inputs in
8700 // a half by taking the sum of the half with three inputs and subtracting
8701 // the sum of the actual three inputs. The difference is the remaining
8704 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8705 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8706 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8707 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8708 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8709 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8710 int TripleNonInputIdx =
8711 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8712 TripleDWord = TripleNonInputIdx / 2;
8714 // We use xor with one to compute the adjacent DWord to whichever one the
8716 OneInputDWord = (OneInput / 2) ^ 1;
8718 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8719 // and BToA inputs. If there is also such a problem with the BToB and AToB
8720 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8721 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8722 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8723 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8724 // Compute how many inputs will be flipped by swapping these DWords. We
8726 // to balance this to ensure we don't form a 3-1 shuffle in the other
8728 int NumFlippedAToBInputs =
8729 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8730 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8731 int NumFlippedBToBInputs =
8732 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8733 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8734 if ((NumFlippedAToBInputs == 1 &&
8735 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8736 (NumFlippedBToBInputs == 1 &&
8737 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8738 // We choose whether to fix the A half or B half based on whether that
8739 // half has zero flipped inputs. At zero, we may not be able to fix it
8740 // with that half. We also bias towards fixing the B half because that
8741 // will more commonly be the high half, and we have to bias one way.
8742 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8743 ArrayRef<int> Inputs) {
8744 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8745 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8746 PinnedIdx ^ 1) != Inputs.end();
8747 // Determine whether the free index is in the flipped dword or the
8748 // unflipped dword based on where the pinned index is. We use this bit
8749 // in an xor to conditionally select the adjacent dword.
8750 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8751 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8752 FixFreeIdx) != Inputs.end();
8753 if (IsFixIdxInput == IsFixFreeIdxInput)
8755 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8756 FixFreeIdx) != Inputs.end();
8757 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8758 "We need to be changing the number of flipped inputs!");
8759 int PSHUFHalfMask[] = {0, 1, 2, 3};
8760 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8761 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8763 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8766 if (M != -1 && M == FixIdx)
8768 else if (M != -1 && M == FixFreeIdx)
8771 if (NumFlippedBToBInputs != 0) {
8773 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8774 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8776 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8777 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8778 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8783 int PSHUFDMask[] = {0, 1, 2, 3};
8784 PSHUFDMask[ADWord] = BDWord;
8785 PSHUFDMask[BDWord] = ADWord;
8788 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8789 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8791 // Adjust the mask to match the new locations of A and B.
8793 if (M != -1 && M/2 == ADWord)
8794 M = 2 * BDWord + M % 2;
8795 else if (M != -1 && M/2 == BDWord)
8796 M = 2 * ADWord + M % 2;
8798 // Recurse back into this routine to re-compute state now that this isn't
8799 // a 3 and 1 problem.
8800 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8803 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8804 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8805 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8806 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8808 // At this point there are at most two inputs to the low and high halves from
8809 // each half. That means the inputs can always be grouped into dwords and
8810 // those dwords can then be moved to the correct half with a dword shuffle.
8811 // We use at most one low and one high word shuffle to collect these paired
8812 // inputs into dwords, and finally a dword shuffle to place them.
8813 int PSHUFLMask[4] = {-1, -1, -1, -1};
8814 int PSHUFHMask[4] = {-1, -1, -1, -1};
8815 int PSHUFDMask[4] = {-1, -1, -1, -1};
8817 // First fix the masks for all the inputs that are staying in their
8818 // original halves. This will then dictate the targets of the cross-half
8820 auto fixInPlaceInputs =
8821 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8822 MutableArrayRef<int> SourceHalfMask,
8823 MutableArrayRef<int> HalfMask, int HalfOffset) {
8824 if (InPlaceInputs.empty())
8826 if (InPlaceInputs.size() == 1) {
8827 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8828 InPlaceInputs[0] - HalfOffset;
8829 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8832 if (IncomingInputs.empty()) {
8833 // Just fix all of the in place inputs.
8834 for (int Input : InPlaceInputs) {
8835 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8836 PSHUFDMask[Input / 2] = Input / 2;
8841 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8842 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8843 InPlaceInputs[0] - HalfOffset;
8844 // Put the second input next to the first so that they are packed into
8845 // a dword. We find the adjacent index by toggling the low bit.
8846 int AdjIndex = InPlaceInputs[0] ^ 1;
8847 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8848 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8849 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8851 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8852 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8854 // Now gather the cross-half inputs and place them into a free dword of
8855 // their target half.
8856 // FIXME: This operation could almost certainly be simplified dramatically to
8857 // look more like the 3-1 fixing operation.
8858 auto moveInputsToRightHalf = [&PSHUFDMask](
8859 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8860 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8861 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8863 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8864 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8866 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8868 int LowWord = Word & ~1;
8869 int HighWord = Word | 1;
8870 return isWordClobbered(SourceHalfMask, LowWord) ||
8871 isWordClobbered(SourceHalfMask, HighWord);
8874 if (IncomingInputs.empty())
8877 if (ExistingInputs.empty()) {
8878 // Map any dwords with inputs from them into the right half.
8879 for (int Input : IncomingInputs) {
8880 // If the source half mask maps over the inputs, turn those into
8881 // swaps and use the swapped lane.
8882 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8883 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8884 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8885 Input - SourceOffset;
8886 // We have to swap the uses in our half mask in one sweep.
8887 for (int &M : HalfMask)
8888 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8890 else if (M == Input)
8891 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8893 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8894 Input - SourceOffset &&
8895 "Previous placement doesn't match!");
8897 // Note that this correctly re-maps both when we do a swap and when
8898 // we observe the other side of the swap above. We rely on that to
8899 // avoid swapping the members of the input list directly.
8900 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8903 // Map the input's dword into the correct half.
8904 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8905 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8907 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8909 "Previous placement doesn't match!");
8912 // And just directly shift any other-half mask elements to be same-half
8913 // as we will have mirrored the dword containing the element into the
8914 // same position within that half.
8915 for (int &M : HalfMask)
8916 if (M >= SourceOffset && M < SourceOffset + 4) {
8917 M = M - SourceOffset + DestOffset;
8918 assert(M >= 0 && "This should never wrap below zero!");
8923 // Ensure we have the input in a viable dword of its current half. This
8924 // is particularly tricky because the original position may be clobbered
8925 // by inputs being moved and *staying* in that half.
8926 if (IncomingInputs.size() == 1) {
8927 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8928 int InputFixed = std::find(std::begin(SourceHalfMask),
8929 std::end(SourceHalfMask), -1) -
8930 std::begin(SourceHalfMask) + SourceOffset;
8931 SourceHalfMask[InputFixed - SourceOffset] =
8932 IncomingInputs[0] - SourceOffset;
8933 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8935 IncomingInputs[0] = InputFixed;
8937 } else if (IncomingInputs.size() == 2) {
8938 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8939 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8940 // We have two non-adjacent or clobbered inputs we need to extract from
8941 // the source half. To do this, we need to map them into some adjacent
8942 // dword slot in the source mask.
8943 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8944 IncomingInputs[1] - SourceOffset};
8946 // If there is a free slot in the source half mask adjacent to one of
8947 // the inputs, place the other input in it. We use (Index XOR 1) to
8948 // compute an adjacent index.
8949 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8950 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8951 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8952 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8953 InputsFixed[1] = InputsFixed[0] ^ 1;
8954 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8955 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8956 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8957 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8958 InputsFixed[0] = InputsFixed[1] ^ 1;
8959 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8960 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8961 // The two inputs are in the same DWord but it is clobbered and the
8962 // adjacent DWord isn't used at all. Move both inputs to the free
8964 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8965 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8966 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8967 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8969 // The only way we hit this point is if there is no clobbering
8970 // (because there are no off-half inputs to this half) and there is no
8971 // free slot adjacent to one of the inputs. In this case, we have to
8972 // swap an input with a non-input.
8973 for (int i = 0; i < 4; ++i)
8974 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8975 "We can't handle any clobbers here!");
8976 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8977 "Cannot have adjacent inputs here!");
8979 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8980 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8982 // We also have to update the final source mask in this case because
8983 // it may need to undo the above swap.
8984 for (int &M : FinalSourceHalfMask)
8985 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8986 M = InputsFixed[1] + SourceOffset;
8987 else if (M == InputsFixed[1] + SourceOffset)
8988 M = (InputsFixed[0] ^ 1) + SourceOffset;
8990 InputsFixed[1] = InputsFixed[0] ^ 1;
8993 // Point everything at the fixed inputs.
8994 for (int &M : HalfMask)
8995 if (M == IncomingInputs[0])
8996 M = InputsFixed[0] + SourceOffset;
8997 else if (M == IncomingInputs[1])
8998 M = InputsFixed[1] + SourceOffset;
9000 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9001 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9004 llvm_unreachable("Unhandled input size!");
9007 // Now hoist the DWord down to the right half.
9008 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9009 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9010 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9011 for (int &M : HalfMask)
9012 for (int Input : IncomingInputs)
9014 M = FreeDWord * 2 + Input % 2;
9016 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9017 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9018 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9019 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9021 // Now enact all the shuffles we've computed to move the inputs into their
9023 if (!isNoopShuffleMask(PSHUFLMask))
9024 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9025 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9026 if (!isNoopShuffleMask(PSHUFHMask))
9027 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9028 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9029 if (!isNoopShuffleMask(PSHUFDMask))
9032 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9033 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9035 // At this point, each half should contain all its inputs, and we can then
9036 // just shuffle them into their final position.
9037 assert(std::count_if(LoMask.begin(), LoMask.end(),
9038 [](int M) { return M >= 4; }) == 0 &&
9039 "Failed to lift all the high half inputs to the low mask!");
9040 assert(std::count_if(HiMask.begin(), HiMask.end(),
9041 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9042 "Failed to lift all the low half inputs to the high mask!");
9044 // Do a half shuffle for the low mask.
9045 if (!isNoopShuffleMask(LoMask))
9046 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9047 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9049 // Do a half shuffle with the high mask after shifting its values down.
9050 for (int &M : HiMask)
9053 if (!isNoopShuffleMask(HiMask))
9054 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9055 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9060 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9061 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9062 SDValue V2, ArrayRef<int> Mask,
9063 SelectionDAG &DAG, bool &V1InUse,
9065 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9071 int Size = Mask.size();
9072 int Scale = 16 / Size;
9073 for (int i = 0; i < 16; ++i) {
9074 if (Mask[i / Scale] == -1) {
9075 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9077 const int ZeroMask = 0x80;
9078 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9080 int V2Idx = Mask[i / Scale] < Size
9082 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9083 if (Zeroable[i / Scale])
9084 V1Idx = V2Idx = ZeroMask;
9085 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9086 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9087 V1InUse |= (ZeroMask != V1Idx);
9088 V2InUse |= (ZeroMask != V2Idx);
9093 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9094 DAG.getBitcast(MVT::v16i8, V1),
9095 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9097 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9098 DAG.getBitcast(MVT::v16i8, V2),
9099 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9101 // If we need shuffled inputs from both, blend the two.
9103 if (V1InUse && V2InUse)
9104 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9106 V = V1InUse ? V1 : V2;
9108 // Cast the result back to the correct type.
9109 return DAG.getBitcast(VT, V);
9112 /// \brief Generic lowering of 8-lane i16 shuffles.
9114 /// This handles both single-input shuffles and combined shuffle/blends with
9115 /// two inputs. The single input shuffles are immediately delegated to
9116 /// a dedicated lowering routine.
9118 /// The blends are lowered in one of three fundamental ways. If there are few
9119 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9120 /// of the input is significantly cheaper when lowered as an interleaving of
9121 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9122 /// halves of the inputs separately (making them have relatively few inputs)
9123 /// and then concatenate them.
9124 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9125 const X86Subtarget *Subtarget,
9126 SelectionDAG &DAG) {
9128 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9129 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9130 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9131 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9132 ArrayRef<int> OrigMask = SVOp->getMask();
9133 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9134 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9135 MutableArrayRef<int> Mask(MaskStorage);
9137 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9139 // Whenever we can lower this as a zext, that instruction is strictly faster
9140 // than any alternative.
9141 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9142 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9145 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9147 auto isV2 = [](int M) { return M >= 8; };
9149 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9151 if (NumV2Inputs == 0) {
9152 // Check for being able to broadcast a single element.
9153 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9154 Mask, Subtarget, DAG))
9157 // Try to use shift instructions.
9159 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9162 // Use dedicated unpack instructions for masks that match their pattern.
9163 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9164 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9165 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9166 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9168 // Try to use byte rotation instructions.
9169 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9170 Mask, Subtarget, DAG))
9173 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9177 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9178 "All single-input shuffles should be canonicalized to be V1-input "
9181 // Try to use shift instructions.
9183 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9186 // See if we can use SSE4A Extraction / Insertion.
9187 if (Subtarget->hasSSE4A())
9188 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9191 // There are special ways we can lower some single-element blends.
9192 if (NumV2Inputs == 1)
9193 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9194 Mask, Subtarget, DAG))
9197 // We have different paths for blend lowering, but they all must use the
9198 // *exact* same predicate.
9199 bool IsBlendSupported = Subtarget->hasSSE41();
9200 if (IsBlendSupported)
9201 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9205 if (SDValue Masked =
9206 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9209 // Use dedicated unpack instructions for masks that match their pattern.
9210 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9211 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9212 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9213 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9215 // Try to use byte rotation instructions.
9216 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9217 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9220 if (SDValue BitBlend =
9221 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9224 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9228 // If we can't directly blend but can use PSHUFB, that will be better as it
9229 // can both shuffle and set up the inefficient blend.
9230 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9231 bool V1InUse, V2InUse;
9232 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9236 // We can always bit-blend if we have to so the fallback strategy is to
9237 // decompose into single-input permutes and blends.
9238 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9242 /// \brief Check whether a compaction lowering can be done by dropping even
9243 /// elements and compute how many times even elements must be dropped.
9245 /// This handles shuffles which take every Nth element where N is a power of
9246 /// two. Example shuffle masks:
9248 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9249 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9250 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9251 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9252 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9253 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9255 /// Any of these lanes can of course be undef.
9257 /// This routine only supports N <= 3.
9258 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9261 /// \returns N above, or the number of times even elements must be dropped if
9262 /// there is such a number. Otherwise returns zero.
9263 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9264 // Figure out whether we're looping over two inputs or just one.
9265 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9267 // The modulus for the shuffle vector entries is based on whether this is
9268 // a single input or not.
9269 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9270 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9271 "We should only be called with masks with a power-of-2 size!");
9273 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9275 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9276 // and 2^3 simultaneously. This is because we may have ambiguity with
9277 // partially undef inputs.
9278 bool ViableForN[3] = {true, true, true};
9280 for (int i = 0, e = Mask.size(); i < e; ++i) {
9281 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9286 bool IsAnyViable = false;
9287 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9288 if (ViableForN[j]) {
9291 // The shuffle mask must be equal to (i * 2^N) % M.
9292 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9295 ViableForN[j] = false;
9297 // Early exit if we exhaust the possible powers of two.
9302 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9306 // Return 0 as there is no viable power of two.
9310 /// \brief Generic lowering of v16i8 shuffles.
9312 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9313 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9314 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9315 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9317 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9318 const X86Subtarget *Subtarget,
9319 SelectionDAG &DAG) {
9321 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9322 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9323 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9324 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9325 ArrayRef<int> Mask = SVOp->getMask();
9326 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9328 // Try to use shift instructions.
9330 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9333 // Try to use byte rotation instructions.
9334 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9335 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9338 // Try to use a zext lowering.
9339 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9340 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9343 // See if we can use SSE4A Extraction / Insertion.
9344 if (Subtarget->hasSSE4A())
9345 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9349 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9351 // For single-input shuffles, there are some nicer lowering tricks we can use.
9352 if (NumV2Elements == 0) {
9353 // Check for being able to broadcast a single element.
9354 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9355 Mask, Subtarget, DAG))
9358 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9359 // Notably, this handles splat and partial-splat shuffles more efficiently.
9360 // However, it only makes sense if the pre-duplication shuffle simplifies
9361 // things significantly. Currently, this means we need to be able to
9362 // express the pre-duplication shuffle as an i16 shuffle.
9364 // FIXME: We should check for other patterns which can be widened into an
9365 // i16 shuffle as well.
9366 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9367 for (int i = 0; i < 16; i += 2)
9368 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9373 auto tryToWidenViaDuplication = [&]() -> SDValue {
9374 if (!canWidenViaDuplication(Mask))
9376 SmallVector<int, 4> LoInputs;
9377 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9378 [](int M) { return M >= 0 && M < 8; });
9379 std::sort(LoInputs.begin(), LoInputs.end());
9380 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9382 SmallVector<int, 4> HiInputs;
9383 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9384 [](int M) { return M >= 8; });
9385 std::sort(HiInputs.begin(), HiInputs.end());
9386 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9389 bool TargetLo = LoInputs.size() >= HiInputs.size();
9390 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9391 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9393 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9394 SmallDenseMap<int, int, 8> LaneMap;
9395 for (int I : InPlaceInputs) {
9396 PreDupI16Shuffle[I/2] = I/2;
9399 int j = TargetLo ? 0 : 4, je = j + 4;
9400 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9401 // Check if j is already a shuffle of this input. This happens when
9402 // there are two adjacent bytes after we move the low one.
9403 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9404 // If we haven't yet mapped the input, search for a slot into which
9406 while (j < je && PreDupI16Shuffle[j] != -1)
9410 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9413 // Map this input with the i16 shuffle.
9414 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9417 // Update the lane map based on the mapping we ended up with.
9418 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9420 V1 = DAG.getBitcast(
9422 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9423 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9425 // Unpack the bytes to form the i16s that will be shuffled into place.
9426 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9427 MVT::v16i8, V1, V1);
9429 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9430 for (int i = 0; i < 16; ++i)
9431 if (Mask[i] != -1) {
9432 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9433 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9434 if (PostDupI16Shuffle[i / 2] == -1)
9435 PostDupI16Shuffle[i / 2] = MappedMask;
9437 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9438 "Conflicting entrties in the original shuffle!");
9440 return DAG.getBitcast(
9442 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9443 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9445 if (SDValue V = tryToWidenViaDuplication())
9449 if (SDValue Masked =
9450 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9453 // Use dedicated unpack instructions for masks that match their pattern.
9454 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9455 0, 16, 1, 17, 2, 18, 3, 19,
9457 4, 20, 5, 21, 6, 22, 7, 23}))
9458 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9459 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9460 8, 24, 9, 25, 10, 26, 11, 27,
9462 12, 28, 13, 29, 14, 30, 15, 31}))
9463 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9465 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9466 // with PSHUFB. It is important to do this before we attempt to generate any
9467 // blends but after all of the single-input lowerings. If the single input
9468 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9469 // want to preserve that and we can DAG combine any longer sequences into
9470 // a PSHUFB in the end. But once we start blending from multiple inputs,
9471 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9472 // and there are *very* few patterns that would actually be faster than the
9473 // PSHUFB approach because of its ability to zero lanes.
9475 // FIXME: The only exceptions to the above are blends which are exact
9476 // interleavings with direct instructions supporting them. We currently don't
9477 // handle those well here.
9478 if (Subtarget->hasSSSE3()) {
9479 bool V1InUse = false;
9480 bool V2InUse = false;
9482 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9483 DAG, V1InUse, V2InUse);
9485 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9486 // do so. This avoids using them to handle blends-with-zero which is
9487 // important as a single pshufb is significantly faster for that.
9488 if (V1InUse && V2InUse) {
9489 if (Subtarget->hasSSE41())
9490 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9491 Mask, Subtarget, DAG))
9494 // We can use an unpack to do the blending rather than an or in some
9495 // cases. Even though the or may be (very minorly) more efficient, we
9496 // preference this lowering because there are common cases where part of
9497 // the complexity of the shuffles goes away when we do the final blend as
9499 // FIXME: It might be worth trying to detect if the unpack-feeding
9500 // shuffles will both be pshufb, in which case we shouldn't bother with
9502 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9503 DL, MVT::v16i8, V1, V2, Mask, DAG))
9510 // There are special ways we can lower some single-element blends.
9511 if (NumV2Elements == 1)
9512 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9513 Mask, Subtarget, DAG))
9516 if (SDValue BitBlend =
9517 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9520 // Check whether a compaction lowering can be done. This handles shuffles
9521 // which take every Nth element for some even N. See the helper function for
9524 // We special case these as they can be particularly efficiently handled with
9525 // the PACKUSB instruction on x86 and they show up in common patterns of
9526 // rearranging bytes to truncate wide elements.
9527 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9528 // NumEvenDrops is the power of two stride of the elements. Another way of
9529 // thinking about it is that we need to drop the even elements this many
9530 // times to get the original input.
9531 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9533 // First we need to zero all the dropped bytes.
9534 assert(NumEvenDrops <= 3 &&
9535 "No support for dropping even elements more than 3 times.");
9536 // We use the mask type to pick which bytes are preserved based on how many
9537 // elements are dropped.
9538 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9539 SDValue ByteClearMask = DAG.getBitcast(
9540 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9541 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9543 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9545 // Now pack things back together.
9546 V1 = DAG.getBitcast(MVT::v8i16, V1);
9547 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9548 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9549 for (int i = 1; i < NumEvenDrops; ++i) {
9550 Result = DAG.getBitcast(MVT::v8i16, Result);
9551 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9557 // Handle multi-input cases by blending single-input shuffles.
9558 if (NumV2Elements > 0)
9559 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9562 // The fallback path for single-input shuffles widens this into two v8i16
9563 // vectors with unpacks, shuffles those, and then pulls them back together
9567 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9568 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9569 for (int i = 0; i < 16; ++i)
9571 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9573 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9575 SDValue VLoHalf, VHiHalf;
9576 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9577 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9579 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9580 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9581 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9582 [](int M) { return M >= 0 && M % 2 == 1; })) {
9583 // Use a mask to drop the high bytes.
9584 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9585 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9586 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9588 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9589 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9591 // Squash the masks to point directly into VLoHalf.
9592 for (int &M : LoBlendMask)
9595 for (int &M : HiBlendMask)
9599 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9600 // VHiHalf so that we can blend them as i16s.
9601 VLoHalf = DAG.getBitcast(
9602 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9603 VHiHalf = DAG.getBitcast(
9604 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9607 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9608 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9610 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9613 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9615 /// This routine breaks down the specific type of 128-bit shuffle and
9616 /// dispatches to the lowering routines accordingly.
9617 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9618 MVT VT, const X86Subtarget *Subtarget,
9619 SelectionDAG &DAG) {
9620 switch (VT.SimpleTy) {
9622 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9624 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9626 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9628 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9630 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9632 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9635 llvm_unreachable("Unimplemented!");
9639 /// \brief Helper function to test whether a shuffle mask could be
9640 /// simplified by widening the elements being shuffled.
9642 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9643 /// leaves it in an unspecified state.
9645 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9646 /// shuffle masks. The latter have the special property of a '-2' representing
9647 /// a zero-ed lane of a vector.
9648 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9649 SmallVectorImpl<int> &WidenedMask) {
9650 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9651 // If both elements are undef, its trivial.
9652 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9653 WidenedMask.push_back(SM_SentinelUndef);
9657 // Check for an undef mask and a mask value properly aligned to fit with
9658 // a pair of values. If we find such a case, use the non-undef mask's value.
9659 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9660 WidenedMask.push_back(Mask[i + 1] / 2);
9663 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9664 WidenedMask.push_back(Mask[i] / 2);
9668 // When zeroing, we need to spread the zeroing across both lanes to widen.
9669 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9670 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9671 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9672 WidenedMask.push_back(SM_SentinelZero);
9678 // Finally check if the two mask values are adjacent and aligned with
9680 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9681 WidenedMask.push_back(Mask[i] / 2);
9685 // Otherwise we can't safely widen the elements used in this shuffle.
9688 assert(WidenedMask.size() == Mask.size() / 2 &&
9689 "Incorrect size of mask after widening the elements!");
9694 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9696 /// This routine just extracts two subvectors, shuffles them independently, and
9697 /// then concatenates them back together. This should work effectively with all
9698 /// AVX vector shuffle types.
9699 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9700 SDValue V2, ArrayRef<int> Mask,
9701 SelectionDAG &DAG) {
9702 assert(VT.getSizeInBits() >= 256 &&
9703 "Only for 256-bit or wider vector shuffles!");
9704 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9705 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9707 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9708 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9710 int NumElements = VT.getVectorNumElements();
9711 int SplitNumElements = NumElements / 2;
9712 MVT ScalarVT = VT.getScalarType();
9713 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9715 // Rather than splitting build-vectors, just build two narrower build
9716 // vectors. This helps shuffling with splats and zeros.
9717 auto SplitVector = [&](SDValue V) {
9718 while (V.getOpcode() == ISD::BITCAST)
9719 V = V->getOperand(0);
9721 MVT OrigVT = V.getSimpleValueType();
9722 int OrigNumElements = OrigVT.getVectorNumElements();
9723 int OrigSplitNumElements = OrigNumElements / 2;
9724 MVT OrigScalarVT = OrigVT.getScalarType();
9725 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9729 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9731 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9732 DAG.getIntPtrConstant(0, DL));
9733 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9734 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9737 SmallVector<SDValue, 16> LoOps, HiOps;
9738 for (int i = 0; i < OrigSplitNumElements; ++i) {
9739 LoOps.push_back(BV->getOperand(i));
9740 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9742 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9743 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9745 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9746 DAG.getBitcast(SplitVT, HiV));
9749 SDValue LoV1, HiV1, LoV2, HiV2;
9750 std::tie(LoV1, HiV1) = SplitVector(V1);
9751 std::tie(LoV2, HiV2) = SplitVector(V2);
9753 // Now create two 4-way blends of these half-width vectors.
9754 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9755 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9756 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9757 for (int i = 0; i < SplitNumElements; ++i) {
9758 int M = HalfMask[i];
9759 if (M >= NumElements) {
9760 if (M >= NumElements + SplitNumElements)
9764 V2BlendMask.push_back(M - NumElements);
9765 V1BlendMask.push_back(-1);
9766 BlendMask.push_back(SplitNumElements + i);
9767 } else if (M >= 0) {
9768 if (M >= SplitNumElements)
9772 V2BlendMask.push_back(-1);
9773 V1BlendMask.push_back(M);
9774 BlendMask.push_back(i);
9776 V2BlendMask.push_back(-1);
9777 V1BlendMask.push_back(-1);
9778 BlendMask.push_back(-1);
9782 // Because the lowering happens after all combining takes place, we need to
9783 // manually combine these blend masks as much as possible so that we create
9784 // a minimal number of high-level vector shuffle nodes.
9786 // First try just blending the halves of V1 or V2.
9787 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9788 return DAG.getUNDEF(SplitVT);
9789 if (!UseLoV2 && !UseHiV2)
9790 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9791 if (!UseLoV1 && !UseHiV1)
9792 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9794 SDValue V1Blend, V2Blend;
9795 if (UseLoV1 && UseHiV1) {
9797 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9799 // We only use half of V1 so map the usage down into the final blend mask.
9800 V1Blend = UseLoV1 ? LoV1 : HiV1;
9801 for (int i = 0; i < SplitNumElements; ++i)
9802 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9803 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9805 if (UseLoV2 && UseHiV2) {
9807 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9809 // We only use half of V2 so map the usage down into the final blend mask.
9810 V2Blend = UseLoV2 ? LoV2 : HiV2;
9811 for (int i = 0; i < SplitNumElements; ++i)
9812 if (BlendMask[i] >= SplitNumElements)
9813 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9815 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9817 SDValue Lo = HalfBlend(LoMask);
9818 SDValue Hi = HalfBlend(HiMask);
9819 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9822 /// \brief Either split a vector in halves or decompose the shuffles and the
9825 /// This is provided as a good fallback for many lowerings of non-single-input
9826 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9827 /// between splitting the shuffle into 128-bit components and stitching those
9828 /// back together vs. extracting the single-input shuffles and blending those
9830 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9831 SDValue V2, ArrayRef<int> Mask,
9832 SelectionDAG &DAG) {
9833 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9834 "lower single-input shuffles as it "
9835 "could then recurse on itself.");
9836 int Size = Mask.size();
9838 // If this can be modeled as a broadcast of two elements followed by a blend,
9839 // prefer that lowering. This is especially important because broadcasts can
9840 // often fold with memory operands.
9841 auto DoBothBroadcast = [&] {
9842 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9845 if (V2BroadcastIdx == -1)
9846 V2BroadcastIdx = M - Size;
9847 else if (M - Size != V2BroadcastIdx)
9849 } else if (M >= 0) {
9850 if (V1BroadcastIdx == -1)
9852 else if (M != V1BroadcastIdx)
9857 if (DoBothBroadcast())
9858 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9861 // If the inputs all stem from a single 128-bit lane of each input, then we
9862 // split them rather than blending because the split will decompose to
9863 // unusually few instructions.
9864 int LaneCount = VT.getSizeInBits() / 128;
9865 int LaneSize = Size / LaneCount;
9866 SmallBitVector LaneInputs[2];
9867 LaneInputs[0].resize(LaneCount, false);
9868 LaneInputs[1].resize(LaneCount, false);
9869 for (int i = 0; i < Size; ++i)
9871 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9872 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9873 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9875 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9876 // that the decomposed single-input shuffles don't end up here.
9877 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9880 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9881 /// a permutation and blend of those lanes.
9883 /// This essentially blends the out-of-lane inputs to each lane into the lane
9884 /// from a permuted copy of the vector. This lowering strategy results in four
9885 /// instructions in the worst case for a single-input cross lane shuffle which
9886 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9887 /// of. Special cases for each particular shuffle pattern should be handled
9888 /// prior to trying this lowering.
9889 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9890 SDValue V1, SDValue V2,
9892 SelectionDAG &DAG) {
9893 // FIXME: This should probably be generalized for 512-bit vectors as well.
9894 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9895 int LaneSize = Mask.size() / 2;
9897 // If there are only inputs from one 128-bit lane, splitting will in fact be
9898 // less expensive. The flags track whether the given lane contains an element
9899 // that crosses to another lane.
9900 bool LaneCrossing[2] = {false, false};
9901 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9902 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9903 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9904 if (!LaneCrossing[0] || !LaneCrossing[1])
9905 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9907 if (isSingleInputShuffleMask(Mask)) {
9908 SmallVector<int, 32> FlippedBlendMask;
9909 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9910 FlippedBlendMask.push_back(
9911 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9913 : Mask[i] % LaneSize +
9914 (i / LaneSize) * LaneSize + Size));
9916 // Flip the vector, and blend the results which should now be in-lane. The
9917 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9918 // 5 for the high source. The value 3 selects the high half of source 2 and
9919 // the value 2 selects the low half of source 2. We only use source 2 to
9920 // allow folding it into a memory operand.
9921 unsigned PERMMask = 3 | 2 << 4;
9922 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9923 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9924 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9927 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9928 // will be handled by the above logic and a blend of the results, much like
9929 // other patterns in AVX.
9930 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9933 /// \brief Handle lowering 2-lane 128-bit shuffles.
9934 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9935 SDValue V2, ArrayRef<int> Mask,
9936 const X86Subtarget *Subtarget,
9937 SelectionDAG &DAG) {
9938 // TODO: If minimizing size and one of the inputs is a zero vector and the
9939 // the zero vector has only one use, we could use a VPERM2X128 to save the
9940 // instruction bytes needed to explicitly generate the zero vector.
9942 // Blends are faster and handle all the non-lane-crossing cases.
9943 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9947 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9948 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9950 // If either input operand is a zero vector, use VPERM2X128 because its mask
9951 // allows us to replace the zero input with an implicit zero.
9952 if (!IsV1Zero && !IsV2Zero) {
9953 // Check for patterns which can be matched with a single insert of a 128-bit
9955 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9956 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9957 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9958 VT.getVectorNumElements() / 2);
9959 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9960 DAG.getIntPtrConstant(0, DL));
9961 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9962 OnlyUsesV1 ? V1 : V2,
9963 DAG.getIntPtrConstant(0, DL));
9964 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9968 // Otherwise form a 128-bit permutation. After accounting for undefs,
9969 // convert the 64-bit shuffle mask selection values into 128-bit
9970 // selection bits by dividing the indexes by 2 and shifting into positions
9971 // defined by a vperm2*128 instruction's immediate control byte.
9973 // The immediate permute control byte looks like this:
9974 // [1:0] - select 128 bits from sources for low half of destination
9976 // [3] - zero low half of destination
9977 // [5:4] - select 128 bits from sources for high half of destination
9979 // [7] - zero high half of destination
9981 int MaskLO = Mask[0];
9982 if (MaskLO == SM_SentinelUndef)
9983 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9985 int MaskHI = Mask[2];
9986 if (MaskHI == SM_SentinelUndef)
9987 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9989 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9991 // If either input is a zero vector, replace it with an undef input.
9992 // Shuffle mask values < 4 are selecting elements of V1.
9993 // Shuffle mask values >= 4 are selecting elements of V2.
9994 // Adjust each half of the permute mask by clearing the half that was
9995 // selecting the zero vector and setting the zero mask bit.
9997 V1 = DAG.getUNDEF(VT);
9999 PermMask = (PermMask & 0xf0) | 0x08;
10001 PermMask = (PermMask & 0x0f) | 0x80;
10004 V2 = DAG.getUNDEF(VT);
10006 PermMask = (PermMask & 0xf0) | 0x08;
10008 PermMask = (PermMask & 0x0f) | 0x80;
10011 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10012 DAG.getConstant(PermMask, DL, MVT::i8));
10015 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10016 /// shuffling each lane.
10018 /// This will only succeed when the result of fixing the 128-bit lanes results
10019 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10020 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10021 /// the lane crosses early and then use simpler shuffles within each lane.
10023 /// FIXME: It might be worthwhile at some point to support this without
10024 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10025 /// in x86 only floating point has interesting non-repeating shuffles, and even
10026 /// those are still *marginally* more expensive.
10027 static SDValue lowerVectorShuffleByMerging128BitLanes(
10028 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10029 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10030 assert(!isSingleInputShuffleMask(Mask) &&
10031 "This is only useful with multiple inputs.");
10033 int Size = Mask.size();
10034 int LaneSize = 128 / VT.getScalarSizeInBits();
10035 int NumLanes = Size / LaneSize;
10036 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10038 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10039 // check whether the in-128-bit lane shuffles share a repeating pattern.
10040 SmallVector<int, 4> Lanes;
10041 Lanes.resize(NumLanes, -1);
10042 SmallVector<int, 4> InLaneMask;
10043 InLaneMask.resize(LaneSize, -1);
10044 for (int i = 0; i < Size; ++i) {
10048 int j = i / LaneSize;
10050 if (Lanes[j] < 0) {
10051 // First entry we've seen for this lane.
10052 Lanes[j] = Mask[i] / LaneSize;
10053 } else if (Lanes[j] != Mask[i] / LaneSize) {
10054 // This doesn't match the lane selected previously!
10058 // Check that within each lane we have a consistent shuffle mask.
10059 int k = i % LaneSize;
10060 if (InLaneMask[k] < 0) {
10061 InLaneMask[k] = Mask[i] % LaneSize;
10062 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10063 // This doesn't fit a repeating in-lane mask.
10068 // First shuffle the lanes into place.
10069 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10070 VT.getSizeInBits() / 64);
10071 SmallVector<int, 8> LaneMask;
10072 LaneMask.resize(NumLanes * 2, -1);
10073 for (int i = 0; i < NumLanes; ++i)
10074 if (Lanes[i] >= 0) {
10075 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10076 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10079 V1 = DAG.getBitcast(LaneVT, V1);
10080 V2 = DAG.getBitcast(LaneVT, V2);
10081 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10083 // Cast it back to the type we actually want.
10084 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10086 // Now do a simple shuffle that isn't lane crossing.
10087 SmallVector<int, 8> NewMask;
10088 NewMask.resize(Size, -1);
10089 for (int i = 0; i < Size; ++i)
10091 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10092 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10093 "Must not introduce lane crosses at this point!");
10095 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10098 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10101 /// This returns true if the elements from a particular input are already in the
10102 /// slot required by the given mask and require no permutation.
10103 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10104 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10105 int Size = Mask.size();
10106 for (int i = 0; i < Size; ++i)
10107 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10113 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10114 ArrayRef<int> Mask, SDValue V1,
10115 SDValue V2, SelectionDAG &DAG) {
10117 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10118 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10119 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10120 int NumElts = VT.getVectorNumElements();
10121 bool ShufpdMask = true;
10122 bool CommutableMask = true;
10123 unsigned Immediate = 0;
10124 for (int i = 0; i < NumElts; ++i) {
10127 int Val = (i & 6) + NumElts * (i & 1);
10128 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10129 if (Mask[i] < Val || Mask[i] > Val + 1)
10130 ShufpdMask = false;
10131 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10132 CommutableMask = false;
10133 Immediate |= (Mask[i] % 2) << i;
10136 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10137 DAG.getConstant(Immediate, DL, MVT::i8));
10138 if (CommutableMask)
10139 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10140 DAG.getConstant(Immediate, DL, MVT::i8));
10144 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10146 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10147 /// isn't available.
10148 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10149 const X86Subtarget *Subtarget,
10150 SelectionDAG &DAG) {
10152 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10153 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10154 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10155 ArrayRef<int> Mask = SVOp->getMask();
10156 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10158 SmallVector<int, 4> WidenedMask;
10159 if (canWidenShuffleElements(Mask, WidenedMask))
10160 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10163 if (isSingleInputShuffleMask(Mask)) {
10164 // Check for being able to broadcast a single element.
10165 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10166 Mask, Subtarget, DAG))
10169 // Use low duplicate instructions for masks that match their pattern.
10170 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10171 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10173 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10174 // Non-half-crossing single input shuffles can be lowerid with an
10175 // interleaved permutation.
10176 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10177 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10178 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10179 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10182 // With AVX2 we have direct support for this permutation.
10183 if (Subtarget->hasAVX2())
10184 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10185 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10187 // Otherwise, fall back.
10188 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10192 // X86 has dedicated unpack instructions that can handle specific blend
10193 // operations: UNPCKH and UNPCKL.
10194 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10195 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10196 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10197 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10198 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10199 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10200 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10201 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10203 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10207 // Check if the blend happens to exactly fit that of SHUFPD.
10209 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10212 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10213 // shuffle. However, if we have AVX2 and either inputs are already in place,
10214 // we will be able to shuffle even across lanes the other input in a single
10215 // instruction so skip this pattern.
10216 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10217 isShuffleMaskInputInPlace(1, Mask))))
10218 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10219 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10222 // If we have AVX2 then we always want to lower with a blend because an v4 we
10223 // can fully permute the elements.
10224 if (Subtarget->hasAVX2())
10225 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10228 // Otherwise fall back on generic lowering.
10229 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10232 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10234 /// This routine is only called when we have AVX2 and thus a reasonable
10235 /// instruction set for v4i64 shuffling..
10236 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10237 const X86Subtarget *Subtarget,
10238 SelectionDAG &DAG) {
10240 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10241 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10242 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10243 ArrayRef<int> Mask = SVOp->getMask();
10244 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10245 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10247 SmallVector<int, 4> WidenedMask;
10248 if (canWidenShuffleElements(Mask, WidenedMask))
10249 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10252 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10256 // Check for being able to broadcast a single element.
10257 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10258 Mask, Subtarget, DAG))
10261 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10262 // use lower latency instructions that will operate on both 128-bit lanes.
10263 SmallVector<int, 2> RepeatedMask;
10264 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10265 if (isSingleInputShuffleMask(Mask)) {
10266 int PSHUFDMask[] = {-1, -1, -1, -1};
10267 for (int i = 0; i < 2; ++i)
10268 if (RepeatedMask[i] >= 0) {
10269 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10270 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10272 return DAG.getBitcast(
10274 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10275 DAG.getBitcast(MVT::v8i32, V1),
10276 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10280 // AVX2 provides a direct instruction for permuting a single input across
10282 if (isSingleInputShuffleMask(Mask))
10283 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10284 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10286 // Try to use shift instructions.
10287 if (SDValue Shift =
10288 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10291 // Use dedicated unpack instructions for masks that match their pattern.
10292 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10293 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10294 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10295 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10296 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10297 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10298 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10299 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10301 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10302 // shuffle. However, if we have AVX2 and either inputs are already in place,
10303 // we will be able to shuffle even across lanes the other input in a single
10304 // instruction so skip this pattern.
10305 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10306 isShuffleMaskInputInPlace(1, Mask))))
10307 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10308 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10311 // Otherwise fall back on generic blend lowering.
10312 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10316 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10318 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10319 /// isn't available.
10320 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10321 const X86Subtarget *Subtarget,
10322 SelectionDAG &DAG) {
10324 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10325 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10326 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10327 ArrayRef<int> Mask = SVOp->getMask();
10328 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10330 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10334 // Check for being able to broadcast a single element.
10335 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10336 Mask, Subtarget, DAG))
10339 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10340 // options to efficiently lower the shuffle.
10341 SmallVector<int, 4> RepeatedMask;
10342 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10343 assert(RepeatedMask.size() == 4 &&
10344 "Repeated masks must be half the mask width!");
10346 // Use even/odd duplicate instructions for masks that match their pattern.
10347 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10348 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10349 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10350 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10352 if (isSingleInputShuffleMask(Mask))
10353 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10354 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10356 // Use dedicated unpack instructions for masks that match their pattern.
10357 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10358 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10359 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10360 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10361 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10362 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10363 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10364 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10366 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10367 // have already handled any direct blends. We also need to squash the
10368 // repeated mask into a simulated v4f32 mask.
10369 for (int i = 0; i < 4; ++i)
10370 if (RepeatedMask[i] >= 8)
10371 RepeatedMask[i] -= 4;
10372 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10375 // If we have a single input shuffle with different shuffle patterns in the
10376 // two 128-bit lanes use the variable mask to VPERMILPS.
10377 if (isSingleInputShuffleMask(Mask)) {
10378 SDValue VPermMask[8];
10379 for (int i = 0; i < 8; ++i)
10380 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10381 : DAG.getConstant(Mask[i], DL, MVT::i32);
10382 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10383 return DAG.getNode(
10384 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10385 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10387 if (Subtarget->hasAVX2())
10388 return DAG.getNode(
10389 X86ISD::VPERMV, DL, MVT::v8f32,
10390 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10391 MVT::v8i32, VPermMask)),
10394 // Otherwise, fall back.
10395 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10399 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10401 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10402 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10405 // If we have AVX2 then we always want to lower with a blend because at v8 we
10406 // can fully permute the elements.
10407 if (Subtarget->hasAVX2())
10408 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10411 // Otherwise fall back on generic lowering.
10412 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10415 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10417 /// This routine is only called when we have AVX2 and thus a reasonable
10418 /// instruction set for v8i32 shuffling..
10419 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10420 const X86Subtarget *Subtarget,
10421 SelectionDAG &DAG) {
10423 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10424 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10425 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10426 ArrayRef<int> Mask = SVOp->getMask();
10427 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10428 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10430 // Whenever we can lower this as a zext, that instruction is strictly faster
10431 // than any alternative. It also allows us to fold memory operands into the
10432 // shuffle in many cases.
10433 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10434 Mask, Subtarget, DAG))
10437 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10441 // Check for being able to broadcast a single element.
10442 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10443 Mask, Subtarget, DAG))
10446 // If the shuffle mask is repeated in each 128-bit lane we can use more
10447 // efficient instructions that mirror the shuffles across the two 128-bit
10449 SmallVector<int, 4> RepeatedMask;
10450 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10451 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10452 if (isSingleInputShuffleMask(Mask))
10453 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10454 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10456 // Use dedicated unpack instructions for masks that match their pattern.
10457 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10458 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10459 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10460 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10461 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10462 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10463 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10464 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10467 // Try to use shift instructions.
10468 if (SDValue Shift =
10469 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10472 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10473 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10476 // If the shuffle patterns aren't repeated but it is a single input, directly
10477 // generate a cross-lane VPERMD instruction.
10478 if (isSingleInputShuffleMask(Mask)) {
10479 SDValue VPermMask[8];
10480 for (int i = 0; i < 8; ++i)
10481 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10482 : DAG.getConstant(Mask[i], DL, MVT::i32);
10483 return DAG.getNode(
10484 X86ISD::VPERMV, DL, MVT::v8i32,
10485 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10488 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10490 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10491 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10494 // Otherwise fall back on generic blend lowering.
10495 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10499 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10501 /// This routine is only called when we have AVX2 and thus a reasonable
10502 /// instruction set for v16i16 shuffling..
10503 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10504 const X86Subtarget *Subtarget,
10505 SelectionDAG &DAG) {
10507 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10508 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10509 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10510 ArrayRef<int> Mask = SVOp->getMask();
10511 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10512 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10514 // Whenever we can lower this as a zext, that instruction is strictly faster
10515 // than any alternative. It also allows us to fold memory operands into the
10516 // shuffle in many cases.
10517 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10518 Mask, Subtarget, DAG))
10521 // Check for being able to broadcast a single element.
10522 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10523 Mask, Subtarget, DAG))
10526 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10530 // Use dedicated unpack instructions for masks that match their pattern.
10531 if (isShuffleEquivalent(V1, V2, Mask,
10532 {// First 128-bit lane:
10533 0, 16, 1, 17, 2, 18, 3, 19,
10534 // Second 128-bit lane:
10535 8, 24, 9, 25, 10, 26, 11, 27}))
10536 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10537 if (isShuffleEquivalent(V1, V2, Mask,
10538 {// First 128-bit lane:
10539 4, 20, 5, 21, 6, 22, 7, 23,
10540 // Second 128-bit lane:
10541 12, 28, 13, 29, 14, 30, 15, 31}))
10542 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10544 // Try to use shift instructions.
10545 if (SDValue Shift =
10546 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10549 // Try to use byte rotation instructions.
10550 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10551 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10554 if (isSingleInputShuffleMask(Mask)) {
10555 // There are no generalized cross-lane shuffle operations available on i16
10557 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10558 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10561 SmallVector<int, 8> RepeatedMask;
10562 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10563 // As this is a single-input shuffle, the repeated mask should be
10564 // a strictly valid v8i16 mask that we can pass through to the v8i16
10565 // lowering to handle even the v16 case.
10566 return lowerV8I16GeneralSingleInputVectorShuffle(
10567 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10570 SDValue PSHUFBMask[32];
10571 for (int i = 0; i < 16; ++i) {
10572 if (Mask[i] == -1) {
10573 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10577 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10578 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10579 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10580 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10582 return DAG.getBitcast(MVT::v16i16,
10583 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10584 DAG.getBitcast(MVT::v32i8, V1),
10585 DAG.getNode(ISD::BUILD_VECTOR, DL,
10586 MVT::v32i8, PSHUFBMask)));
10589 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10591 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10592 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10595 // Otherwise fall back on generic lowering.
10596 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10599 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10601 /// This routine is only called when we have AVX2 and thus a reasonable
10602 /// instruction set for v32i8 shuffling..
10603 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10604 const X86Subtarget *Subtarget,
10605 SelectionDAG &DAG) {
10607 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10608 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10609 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10610 ArrayRef<int> Mask = SVOp->getMask();
10611 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10612 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10614 // Whenever we can lower this as a zext, that instruction is strictly faster
10615 // than any alternative. It also allows us to fold memory operands into the
10616 // shuffle in many cases.
10617 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10618 Mask, Subtarget, DAG))
10621 // Check for being able to broadcast a single element.
10622 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10623 Mask, Subtarget, DAG))
10626 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10630 // Use dedicated unpack instructions for masks that match their pattern.
10631 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10633 if (isShuffleEquivalent(
10635 {// First 128-bit lane:
10636 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10637 // Second 128-bit lane:
10638 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10639 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10640 if (isShuffleEquivalent(
10642 {// First 128-bit lane:
10643 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10644 // Second 128-bit lane:
10645 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10646 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10648 // Try to use shift instructions.
10649 if (SDValue Shift =
10650 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10653 // Try to use byte rotation instructions.
10654 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10655 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10658 if (isSingleInputShuffleMask(Mask)) {
10659 // There are no generalized cross-lane shuffle operations available on i8
10661 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10662 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10665 SDValue PSHUFBMask[32];
10666 for (int i = 0; i < 32; ++i)
10669 ? DAG.getUNDEF(MVT::i8)
10670 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10673 return DAG.getNode(
10674 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10675 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10678 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10680 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10681 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10684 // Otherwise fall back on generic lowering.
10685 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10688 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10690 /// This routine either breaks down the specific type of a 256-bit x86 vector
10691 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10692 /// together based on the available instructions.
10693 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10694 MVT VT, const X86Subtarget *Subtarget,
10695 SelectionDAG &DAG) {
10697 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10698 ArrayRef<int> Mask = SVOp->getMask();
10700 // If we have a single input to the zero element, insert that into V1 if we
10701 // can do so cheaply.
10702 int NumElts = VT.getVectorNumElements();
10703 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10704 return M >= NumElts;
10707 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10708 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10709 DL, VT, V1, V2, Mask, Subtarget, DAG))
10712 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10713 // can check for those subtargets here and avoid much of the subtarget
10714 // querying in the per-vector-type lowering routines. With AVX1 we have
10715 // essentially *zero* ability to manipulate a 256-bit vector with integer
10716 // types. Since we'll use floating point types there eventually, just
10717 // immediately cast everything to a float and operate entirely in that domain.
10718 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10719 int ElementBits = VT.getScalarSizeInBits();
10720 if (ElementBits < 32)
10721 // No floating point type available, decompose into 128-bit vectors.
10722 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10724 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10725 VT.getVectorNumElements());
10726 V1 = DAG.getBitcast(FpVT, V1);
10727 V2 = DAG.getBitcast(FpVT, V2);
10728 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10731 switch (VT.SimpleTy) {
10733 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10735 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10737 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10739 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10741 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10743 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10746 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10750 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10751 ArrayRef<int> Mask, SDValue V1,
10752 SDValue V2, SelectionDAG &DAG) {
10754 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10756 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10757 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10759 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10760 if (isSingleInputShuffleMask(Mask))
10761 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10763 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10766 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10767 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10768 const X86Subtarget *Subtarget,
10769 SelectionDAG &DAG) {
10771 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10772 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10773 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10774 ArrayRef<int> Mask = SVOp->getMask();
10775 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10777 if (SDValue Unpck =
10778 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10781 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10784 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10785 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10786 const X86Subtarget *Subtarget,
10787 SelectionDAG &DAG) {
10789 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10790 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10791 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10792 ArrayRef<int> Mask = SVOp->getMask();
10793 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10795 if (SDValue Unpck =
10796 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10799 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10802 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10803 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10804 const X86Subtarget *Subtarget,
10805 SelectionDAG &DAG) {
10807 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10808 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10809 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10810 ArrayRef<int> Mask = SVOp->getMask();
10811 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10813 if (SDValue Unpck =
10814 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10817 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10820 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10821 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10822 const X86Subtarget *Subtarget,
10823 SelectionDAG &DAG) {
10825 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10826 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10827 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10828 ArrayRef<int> Mask = SVOp->getMask();
10829 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10831 if (SDValue Unpck =
10832 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10835 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10838 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10839 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10840 const X86Subtarget *Subtarget,
10841 SelectionDAG &DAG) {
10843 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10844 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10845 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10846 ArrayRef<int> Mask = SVOp->getMask();
10847 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10848 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10850 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10853 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10854 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10855 const X86Subtarget *Subtarget,
10856 SelectionDAG &DAG) {
10858 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10859 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10860 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10861 ArrayRef<int> Mask = SVOp->getMask();
10862 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10863 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10865 // FIXME: Implement direct support for this type!
10866 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10869 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10871 /// This routine either breaks down the specific type of a 512-bit x86 vector
10872 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10873 /// together based on the available instructions.
10874 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10875 MVT VT, const X86Subtarget *Subtarget,
10876 SelectionDAG &DAG) {
10878 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10879 ArrayRef<int> Mask = SVOp->getMask();
10880 assert(Subtarget->hasAVX512() &&
10881 "Cannot lower 512-bit vectors w/ basic ISA!");
10883 // Check for being able to broadcast a single element.
10884 if (SDValue Broadcast =
10885 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10888 // Dispatch to each element type for lowering. If we don't have supprot for
10889 // specific element type shuffles at 512 bits, immediately split them and
10890 // lower them. Each lowering routine of a given type is allowed to assume that
10891 // the requisite ISA extensions for that element type are available.
10892 switch (VT.SimpleTy) {
10894 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10896 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10898 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10900 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10902 if (Subtarget->hasBWI())
10903 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10906 if (Subtarget->hasBWI())
10907 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10911 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10914 // Otherwise fall back on splitting.
10915 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10918 // Lower vXi1 vector shuffles.
10919 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10920 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10921 // vector, shuffle and then truncate it back.
10922 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10923 MVT VT, const X86Subtarget *Subtarget,
10924 SelectionDAG &DAG) {
10926 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10927 ArrayRef<int> Mask = SVOp->getMask();
10928 assert(Subtarget->hasAVX512() &&
10929 "Cannot lower 512-bit vectors w/o basic ISA!");
10931 switch (VT.SimpleTy) {
10933 assert(false && "Expected a vector of i1 elements");
10936 ExtVT = MVT::v2i64;
10939 ExtVT = MVT::v4i32;
10942 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
10945 ExtVT = MVT::v16i32;
10948 ExtVT = MVT::v32i16;
10951 ExtVT = MVT::v64i8;
10955 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10956 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10957 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
10958 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10960 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
10963 V2 = DAG.getUNDEF(ExtVT);
10964 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
10965 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10966 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
10967 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10969 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
10970 return DAG.getNode(ISD::TRUNCATE, DL, VT,
10971 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
10973 /// \brief Top-level lowering for x86 vector shuffles.
10975 /// This handles decomposition, canonicalization, and lowering of all x86
10976 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10977 /// above in helper routines. The canonicalization attempts to widen shuffles
10978 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10979 /// s.t. only one of the two inputs needs to be tested, etc.
10980 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10981 SelectionDAG &DAG) {
10982 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10983 ArrayRef<int> Mask = SVOp->getMask();
10984 SDValue V1 = Op.getOperand(0);
10985 SDValue V2 = Op.getOperand(1);
10986 MVT VT = Op.getSimpleValueType();
10987 int NumElements = VT.getVectorNumElements();
10989 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
10991 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
10992 "Can't lower MMX shuffles");
10994 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10995 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10996 if (V1IsUndef && V2IsUndef)
10997 return DAG.getUNDEF(VT);
10999 // When we create a shuffle node we put the UNDEF node to second operand,
11000 // but in some cases the first operand may be transformed to UNDEF.
11001 // In this case we should just commute the node.
11003 return DAG.getCommutedVectorShuffle(*SVOp);
11005 // Check for non-undef masks pointing at an undef vector and make the masks
11006 // undef as well. This makes it easier to match the shuffle based solely on
11010 if (M >= NumElements) {
11011 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11012 for (int &M : NewMask)
11013 if (M >= NumElements)
11015 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11018 // We actually see shuffles that are entirely re-arrangements of a set of
11019 // zero inputs. This mostly happens while decomposing complex shuffles into
11020 // simple ones. Directly lower these as a buildvector of zeros.
11021 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11022 if (Zeroable.all())
11023 return getZeroVector(VT, Subtarget, DAG, dl);
11025 // Try to collapse shuffles into using a vector type with fewer elements but
11026 // wider element types. We cap this to not form integers or floating point
11027 // elements wider than 64 bits, but it might be interesting to form i128
11028 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11029 SmallVector<int, 16> WidenedMask;
11030 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11031 canWidenShuffleElements(Mask, WidenedMask)) {
11032 MVT NewEltVT = VT.isFloatingPoint()
11033 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11034 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11035 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11036 // Make sure that the new vector type is legal. For example, v2f64 isn't
11038 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11039 V1 = DAG.getBitcast(NewVT, V1);
11040 V2 = DAG.getBitcast(NewVT, V2);
11041 return DAG.getBitcast(
11042 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11046 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11047 for (int M : SVOp->getMask())
11049 ++NumUndefElements;
11050 else if (M < NumElements)
11055 // Commute the shuffle as needed such that more elements come from V1 than
11056 // V2. This allows us to match the shuffle pattern strictly on how many
11057 // elements come from V1 without handling the symmetric cases.
11058 if (NumV2Elements > NumV1Elements)
11059 return DAG.getCommutedVectorShuffle(*SVOp);
11061 // When the number of V1 and V2 elements are the same, try to minimize the
11062 // number of uses of V2 in the low half of the vector. When that is tied,
11063 // ensure that the sum of indices for V1 is equal to or lower than the sum
11064 // indices for V2. When those are equal, try to ensure that the number of odd
11065 // indices for V1 is lower than the number of odd indices for V2.
11066 if (NumV1Elements == NumV2Elements) {
11067 int LowV1Elements = 0, LowV2Elements = 0;
11068 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11069 if (M >= NumElements)
11073 if (LowV2Elements > LowV1Elements) {
11074 return DAG.getCommutedVectorShuffle(*SVOp);
11075 } else if (LowV2Elements == LowV1Elements) {
11076 int SumV1Indices = 0, SumV2Indices = 0;
11077 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11078 if (SVOp->getMask()[i] >= NumElements)
11080 else if (SVOp->getMask()[i] >= 0)
11082 if (SumV2Indices < SumV1Indices) {
11083 return DAG.getCommutedVectorShuffle(*SVOp);
11084 } else if (SumV2Indices == SumV1Indices) {
11085 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11086 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11087 if (SVOp->getMask()[i] >= NumElements)
11088 NumV2OddIndices += i % 2;
11089 else if (SVOp->getMask()[i] >= 0)
11090 NumV1OddIndices += i % 2;
11091 if (NumV2OddIndices < NumV1OddIndices)
11092 return DAG.getCommutedVectorShuffle(*SVOp);
11097 // For each vector width, delegate to a specialized lowering routine.
11098 if (VT.getSizeInBits() == 128)
11099 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11101 if (VT.getSizeInBits() == 256)
11102 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11104 if (VT.getSizeInBits() == 512)
11105 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11108 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11109 llvm_unreachable("Unimplemented!");
11112 // This function assumes its argument is a BUILD_VECTOR of constants or
11113 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11115 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11116 unsigned &MaskValue) {
11118 unsigned NumElems = BuildVector->getNumOperands();
11120 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11121 // We don't handle the >2 lanes case right now.
11122 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11126 unsigned NumElemsInLane = NumElems / NumLanes;
11128 // Blend for v16i16 should be symmetric for the both lanes.
11129 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11130 SDValue EltCond = BuildVector->getOperand(i);
11131 SDValue SndLaneEltCond =
11132 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11134 int Lane1Cond = -1, Lane2Cond = -1;
11135 if (isa<ConstantSDNode>(EltCond))
11136 Lane1Cond = !isZero(EltCond);
11137 if (isa<ConstantSDNode>(SndLaneEltCond))
11138 Lane2Cond = !isZero(SndLaneEltCond);
11140 unsigned LaneMask = 0;
11141 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11142 // Lane1Cond != 0, means we want the first argument.
11143 // Lane1Cond == 0, means we want the second argument.
11144 // The encoding of this argument is 0 for the first argument, 1
11145 // for the second. Therefore, invert the condition.
11146 LaneMask = !Lane1Cond << i;
11147 else if (Lane1Cond < 0)
11148 LaneMask = !Lane2Cond << i;
11152 MaskValue |= LaneMask;
11154 MaskValue |= LaneMask << NumElemsInLane;
11159 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11160 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11161 const X86Subtarget *Subtarget,
11162 SelectionDAG &DAG) {
11163 SDValue Cond = Op.getOperand(0);
11164 SDValue LHS = Op.getOperand(1);
11165 SDValue RHS = Op.getOperand(2);
11167 MVT VT = Op.getSimpleValueType();
11169 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11171 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11173 // Only non-legal VSELECTs reach this lowering, convert those into generic
11174 // shuffles and re-use the shuffle lowering path for blends.
11175 SmallVector<int, 32> Mask;
11176 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11177 SDValue CondElt = CondBV->getOperand(i);
11179 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11181 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11184 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11185 // A vselect where all conditions and data are constants can be optimized into
11186 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11187 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11188 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11189 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11192 // Try to lower this to a blend-style vector shuffle. This can handle all
11193 // constant condition cases.
11194 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11197 // Variable blends are only legal from SSE4.1 onward.
11198 if (!Subtarget->hasSSE41())
11201 // Only some types will be legal on some subtargets. If we can emit a legal
11202 // VSELECT-matching blend, return Op, and but if we need to expand, return
11204 switch (Op.getSimpleValueType().SimpleTy) {
11206 // Most of the vector types have blends past SSE4.1.
11210 // The byte blends for AVX vectors were introduced only in AVX2.
11211 if (Subtarget->hasAVX2())
11218 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11219 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11222 // FIXME: We should custom lower this by fixing the condition and using i8
11228 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11229 MVT VT = Op.getSimpleValueType();
11232 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11235 if (VT.getSizeInBits() == 8) {
11236 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11237 Op.getOperand(0), Op.getOperand(1));
11238 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11239 DAG.getValueType(VT));
11240 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11243 if (VT.getSizeInBits() == 16) {
11244 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11245 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11247 return DAG.getNode(
11248 ISD::TRUNCATE, dl, MVT::i16,
11249 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11250 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11251 Op.getOperand(1)));
11252 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11253 Op.getOperand(0), Op.getOperand(1));
11254 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11255 DAG.getValueType(VT));
11256 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11259 if (VT == MVT::f32) {
11260 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11261 // the result back to FR32 register. It's only worth matching if the
11262 // result has a single use which is a store or a bitcast to i32. And in
11263 // the case of a store, it's not worth it if the index is a constant 0,
11264 // because a MOVSSmr can be used instead, which is smaller and faster.
11265 if (!Op.hasOneUse())
11267 SDNode *User = *Op.getNode()->use_begin();
11268 if ((User->getOpcode() != ISD::STORE ||
11269 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11270 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11271 (User->getOpcode() != ISD::BITCAST ||
11272 User->getValueType(0) != MVT::i32))
11274 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11275 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11277 return DAG.getBitcast(MVT::f32, Extract);
11280 if (VT == MVT::i32 || VT == MVT::i64) {
11281 // ExtractPS/pextrq works with constant index.
11282 if (isa<ConstantSDNode>(Op.getOperand(1)))
11288 /// Extract one bit from mask vector, like v16i1 or v8i1.
11289 /// AVX-512 feature.
11291 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11292 SDValue Vec = Op.getOperand(0);
11294 MVT VecVT = Vec.getSimpleValueType();
11295 SDValue Idx = Op.getOperand(1);
11296 MVT EltVT = Op.getSimpleValueType();
11298 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11299 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11300 "Unexpected vector type in ExtractBitFromMaskVector");
11302 // variable index can't be handled in mask registers,
11303 // extend vector to VR512
11304 if (!isa<ConstantSDNode>(Idx)) {
11305 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11306 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11307 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11308 ExtVT.getVectorElementType(), Ext, Idx);
11309 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11312 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11313 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11314 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11315 rc = getRegClassFor(MVT::v16i1);
11316 unsigned MaxSift = rc->getSize()*8 - 1;
11317 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11318 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11319 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11320 DAG.getConstant(MaxSift, dl, MVT::i8));
11321 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11322 DAG.getIntPtrConstant(0, dl));
11326 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11327 SelectionDAG &DAG) const {
11329 SDValue Vec = Op.getOperand(0);
11330 MVT VecVT = Vec.getSimpleValueType();
11331 SDValue Idx = Op.getOperand(1);
11333 if (Op.getSimpleValueType() == MVT::i1)
11334 return ExtractBitFromMaskVector(Op, DAG);
11336 if (!isa<ConstantSDNode>(Idx)) {
11337 if (VecVT.is512BitVector() ||
11338 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11339 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11342 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11343 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11344 MaskEltVT.getSizeInBits());
11346 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11347 auto PtrVT = getPointerTy(DAG.getDataLayout());
11348 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11349 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11350 DAG.getConstant(0, dl, PtrVT));
11351 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11352 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11353 DAG.getConstant(0, dl, PtrVT));
11358 // If this is a 256-bit vector result, first extract the 128-bit vector and
11359 // then extract the element from the 128-bit vector.
11360 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11362 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11363 // Get the 128-bit vector.
11364 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11365 MVT EltVT = VecVT.getVectorElementType();
11367 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11369 //if (IdxVal >= NumElems/2)
11370 // IdxVal -= NumElems/2;
11371 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11372 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11373 DAG.getConstant(IdxVal, dl, MVT::i32));
11376 assert(VecVT.is128BitVector() && "Unexpected vector length");
11378 if (Subtarget->hasSSE41())
11379 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11382 MVT VT = Op.getSimpleValueType();
11383 // TODO: handle v16i8.
11384 if (VT.getSizeInBits() == 16) {
11385 SDValue Vec = Op.getOperand(0);
11386 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11388 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11389 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11390 DAG.getBitcast(MVT::v4i32, Vec),
11391 Op.getOperand(1)));
11392 // Transform it so it match pextrw which produces a 32-bit result.
11393 MVT EltVT = MVT::i32;
11394 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11395 Op.getOperand(0), Op.getOperand(1));
11396 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11397 DAG.getValueType(VT));
11398 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11401 if (VT.getSizeInBits() == 32) {
11402 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11406 // SHUFPS the element to the lowest double word, then movss.
11407 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11408 MVT VVT = Op.getOperand(0).getSimpleValueType();
11409 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11410 DAG.getUNDEF(VVT), Mask);
11411 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11412 DAG.getIntPtrConstant(0, dl));
11415 if (VT.getSizeInBits() == 64) {
11416 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11417 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11418 // to match extract_elt for f64.
11419 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11423 // UNPCKHPD the element to the lowest double word, then movsd.
11424 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11425 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11426 int Mask[2] = { 1, -1 };
11427 MVT VVT = Op.getOperand(0).getSimpleValueType();
11428 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11429 DAG.getUNDEF(VVT), Mask);
11430 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11431 DAG.getIntPtrConstant(0, dl));
11437 /// Insert one bit to mask vector, like v16i1 or v8i1.
11438 /// AVX-512 feature.
11440 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11442 SDValue Vec = Op.getOperand(0);
11443 SDValue Elt = Op.getOperand(1);
11444 SDValue Idx = Op.getOperand(2);
11445 MVT VecVT = Vec.getSimpleValueType();
11447 if (!isa<ConstantSDNode>(Idx)) {
11448 // Non constant index. Extend source and destination,
11449 // insert element and then truncate the result.
11450 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11451 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11452 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11453 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11454 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11455 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11458 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11459 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11461 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11462 DAG.getConstant(IdxVal, dl, MVT::i8));
11463 if (Vec.getOpcode() == ISD::UNDEF)
11465 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11468 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11469 SelectionDAG &DAG) const {
11470 MVT VT = Op.getSimpleValueType();
11471 MVT EltVT = VT.getVectorElementType();
11473 if (EltVT == MVT::i1)
11474 return InsertBitToMaskVector(Op, DAG);
11477 SDValue N0 = Op.getOperand(0);
11478 SDValue N1 = Op.getOperand(1);
11479 SDValue N2 = Op.getOperand(2);
11480 if (!isa<ConstantSDNode>(N2))
11482 auto *N2C = cast<ConstantSDNode>(N2);
11483 unsigned IdxVal = N2C->getZExtValue();
11485 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11486 // into that, and then insert the subvector back into the result.
11487 if (VT.is256BitVector() || VT.is512BitVector()) {
11488 // With a 256-bit vector, we can insert into the zero element efficiently
11489 // using a blend if we have AVX or AVX2 and the right data type.
11490 if (VT.is256BitVector() && IdxVal == 0) {
11491 // TODO: It is worthwhile to cast integer to floating point and back
11492 // and incur a domain crossing penalty if that's what we'll end up
11493 // doing anyway after extracting to a 128-bit vector.
11494 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11495 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11496 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11497 N2 = DAG.getIntPtrConstant(1, dl);
11498 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11502 // Get the desired 128-bit vector chunk.
11503 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11505 // Insert the element into the desired chunk.
11506 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11507 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11509 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11510 DAG.getConstant(IdxIn128, dl, MVT::i32));
11512 // Insert the changed part back into the bigger vector
11513 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11515 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11517 if (Subtarget->hasSSE41()) {
11518 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11520 if (VT == MVT::v8i16) {
11521 Opc = X86ISD::PINSRW;
11523 assert(VT == MVT::v16i8);
11524 Opc = X86ISD::PINSRB;
11527 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11529 if (N1.getValueType() != MVT::i32)
11530 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11531 if (N2.getValueType() != MVT::i32)
11532 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11533 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11536 if (EltVT == MVT::f32) {
11537 // Bits [7:6] of the constant are the source select. This will always be
11538 // zero here. The DAG Combiner may combine an extract_elt index into
11539 // these bits. For example (insert (extract, 3), 2) could be matched by
11540 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11541 // Bits [5:4] of the constant are the destination select. This is the
11542 // value of the incoming immediate.
11543 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11544 // combine either bitwise AND or insert of float 0.0 to set these bits.
11546 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11547 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11548 // If this is an insertion of 32-bits into the low 32-bits of
11549 // a vector, we prefer to generate a blend with immediate rather
11550 // than an insertps. Blends are simpler operations in hardware and so
11551 // will always have equal or better performance than insertps.
11552 // But if optimizing for size and there's a load folding opportunity,
11553 // generate insertps because blendps does not have a 32-bit memory
11555 N2 = DAG.getIntPtrConstant(1, dl);
11556 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11557 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11559 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11560 // Create this as a scalar to vector..
11561 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11562 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11565 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11566 // PINSR* works with constant index.
11571 if (EltVT == MVT::i8)
11574 if (EltVT.getSizeInBits() == 16) {
11575 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11576 // as its second argument.
11577 if (N1.getValueType() != MVT::i32)
11578 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11579 if (N2.getValueType() != MVT::i32)
11580 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11581 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11586 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11588 MVT OpVT = Op.getSimpleValueType();
11590 // If this is a 256-bit vector result, first insert into a 128-bit
11591 // vector and then insert into the 256-bit vector.
11592 if (!OpVT.is128BitVector()) {
11593 // Insert into a 128-bit vector.
11594 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11595 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11596 OpVT.getVectorNumElements() / SizeFactor);
11598 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11600 // Insert the 128-bit vector.
11601 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11604 if (OpVT == MVT::v1i64 &&
11605 Op.getOperand(0).getValueType() == MVT::i64)
11606 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11608 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11609 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11610 return DAG.getBitcast(
11611 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11614 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11615 // a simple subregister reference or explicit instructions to grab
11616 // upper bits of a vector.
11617 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11618 SelectionDAG &DAG) {
11620 SDValue In = Op.getOperand(0);
11621 SDValue Idx = Op.getOperand(1);
11622 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11623 MVT ResVT = Op.getSimpleValueType();
11624 MVT InVT = In.getSimpleValueType();
11626 if (Subtarget->hasFp256()) {
11627 if (ResVT.is128BitVector() &&
11628 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11629 isa<ConstantSDNode>(Idx)) {
11630 return Extract128BitVector(In, IdxVal, DAG, dl);
11632 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11633 isa<ConstantSDNode>(Idx)) {
11634 return Extract256BitVector(In, IdxVal, DAG, dl);
11640 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11641 // simple superregister reference or explicit instructions to insert
11642 // the upper bits of a vector.
11643 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11644 SelectionDAG &DAG) {
11645 if (!Subtarget->hasAVX())
11649 SDValue Vec = Op.getOperand(0);
11650 SDValue SubVec = Op.getOperand(1);
11651 SDValue Idx = Op.getOperand(2);
11653 if (!isa<ConstantSDNode>(Idx))
11656 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11657 MVT OpVT = Op.getSimpleValueType();
11658 MVT SubVecVT = SubVec.getSimpleValueType();
11660 // Fold two 16-byte subvector loads into one 32-byte load:
11661 // (insert_subvector (insert_subvector undef, (load addr), 0),
11662 // (load addr + 16), Elts/2)
11664 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11665 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11666 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11667 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11668 if (Idx2 && Idx2->getZExtValue() == 0) {
11669 SDValue SubVec2 = Vec.getOperand(1);
11670 // If needed, look through a bitcast to get to the load.
11671 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11672 SubVec2 = SubVec2.getOperand(0);
11674 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11676 unsigned Alignment = FirstLd->getAlignment();
11677 unsigned AS = FirstLd->getAddressSpace();
11678 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11679 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11680 OpVT, AS, Alignment, &Fast) && Fast) {
11681 SDValue Ops[] = { SubVec2, SubVec };
11682 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11689 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11690 SubVecVT.is128BitVector())
11691 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11693 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11694 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11696 if (OpVT.getVectorElementType() == MVT::i1) {
11697 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11699 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11700 SDValue Undef = DAG.getUNDEF(OpVT);
11701 unsigned NumElems = OpVT.getVectorNumElements();
11702 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11704 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11705 // Zero upper bits of the Vec
11706 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11707 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11709 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11711 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11712 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11715 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11717 // Zero upper bits of the Vec2
11718 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11719 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11720 // Zero lower bits of the Vec
11721 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11722 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11723 // Merge them together
11724 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11730 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11731 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11732 // one of the above mentioned nodes. It has to be wrapped because otherwise
11733 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11734 // be used to form addressing mode. These wrapped nodes will be selected
11737 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11738 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11740 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11741 // global base reg.
11742 unsigned char OpFlag = 0;
11743 unsigned WrapperKind = X86ISD::Wrapper;
11744 CodeModel::Model M = DAG.getTarget().getCodeModel();
11746 if (Subtarget->isPICStyleRIPRel() &&
11747 (M == CodeModel::Small || M == CodeModel::Kernel))
11748 WrapperKind = X86ISD::WrapperRIP;
11749 else if (Subtarget->isPICStyleGOT())
11750 OpFlag = X86II::MO_GOTOFF;
11751 else if (Subtarget->isPICStyleStubPIC())
11752 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11754 auto PtrVT = getPointerTy(DAG.getDataLayout());
11755 SDValue Result = DAG.getTargetConstantPool(
11756 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11758 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11759 // With PIC, the address is actually $g + Offset.
11762 DAG.getNode(ISD::ADD, DL, PtrVT,
11763 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11769 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11770 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11772 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11773 // global base reg.
11774 unsigned char OpFlag = 0;
11775 unsigned WrapperKind = X86ISD::Wrapper;
11776 CodeModel::Model M = DAG.getTarget().getCodeModel();
11778 if (Subtarget->isPICStyleRIPRel() &&
11779 (M == CodeModel::Small || M == CodeModel::Kernel))
11780 WrapperKind = X86ISD::WrapperRIP;
11781 else if (Subtarget->isPICStyleGOT())
11782 OpFlag = X86II::MO_GOTOFF;
11783 else if (Subtarget->isPICStyleStubPIC())
11784 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11786 auto PtrVT = getPointerTy(DAG.getDataLayout());
11787 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11789 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11791 // With PIC, the address is actually $g + Offset.
11794 DAG.getNode(ISD::ADD, DL, PtrVT,
11795 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11801 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11802 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11804 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11805 // global base reg.
11806 unsigned char OpFlag = 0;
11807 unsigned WrapperKind = X86ISD::Wrapper;
11808 CodeModel::Model M = DAG.getTarget().getCodeModel();
11810 if (Subtarget->isPICStyleRIPRel() &&
11811 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11812 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11813 OpFlag = X86II::MO_GOTPCREL;
11814 WrapperKind = X86ISD::WrapperRIP;
11815 } else if (Subtarget->isPICStyleGOT()) {
11816 OpFlag = X86II::MO_GOT;
11817 } else if (Subtarget->isPICStyleStubPIC()) {
11818 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11819 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11820 OpFlag = X86II::MO_DARWIN_NONLAZY;
11823 auto PtrVT = getPointerTy(DAG.getDataLayout());
11824 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11827 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11829 // With PIC, the address is actually $g + Offset.
11830 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11831 !Subtarget->is64Bit()) {
11833 DAG.getNode(ISD::ADD, DL, PtrVT,
11834 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11837 // For symbols that require a load from a stub to get the address, emit the
11839 if (isGlobalStubReference(OpFlag))
11840 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11841 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11842 false, false, false, 0);
11848 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11849 // Create the TargetBlockAddressAddress node.
11850 unsigned char OpFlags =
11851 Subtarget->ClassifyBlockAddressReference();
11852 CodeModel::Model M = DAG.getTarget().getCodeModel();
11853 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11854 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11856 auto PtrVT = getPointerTy(DAG.getDataLayout());
11857 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11859 if (Subtarget->isPICStyleRIPRel() &&
11860 (M == CodeModel::Small || M == CodeModel::Kernel))
11861 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11863 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11865 // With PIC, the address is actually $g + Offset.
11866 if (isGlobalRelativeToPICBase(OpFlags)) {
11867 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11868 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11875 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11876 int64_t Offset, SelectionDAG &DAG) const {
11877 // Create the TargetGlobalAddress node, folding in the constant
11878 // offset if it is legal.
11879 unsigned char OpFlags =
11880 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11881 CodeModel::Model M = DAG.getTarget().getCodeModel();
11882 auto PtrVT = getPointerTy(DAG.getDataLayout());
11884 if (OpFlags == X86II::MO_NO_FLAG &&
11885 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11886 // A direct static reference to a global.
11887 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11890 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11893 if (Subtarget->isPICStyleRIPRel() &&
11894 (M == CodeModel::Small || M == CodeModel::Kernel))
11895 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11897 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11899 // With PIC, the address is actually $g + Offset.
11900 if (isGlobalRelativeToPICBase(OpFlags)) {
11901 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11902 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11905 // For globals that require a load from a stub to get the address, emit the
11907 if (isGlobalStubReference(OpFlags))
11908 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11909 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11910 false, false, false, 0);
11912 // If there was a non-zero offset that we didn't fold, create an explicit
11913 // addition for it.
11915 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11916 DAG.getConstant(Offset, dl, PtrVT));
11922 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11923 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11924 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11925 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11929 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11930 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11931 unsigned char OperandFlags, bool LocalDynamic = false) {
11932 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11933 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11935 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11936 GA->getValueType(0),
11940 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11944 SDValue Ops[] = { Chain, TGA, *InFlag };
11945 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11947 SDValue Ops[] = { Chain, TGA };
11948 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11951 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11952 MFI->setAdjustsStack(true);
11953 MFI->setHasCalls(true);
11955 SDValue Flag = Chain.getValue(1);
11956 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11959 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11961 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11964 SDLoc dl(GA); // ? function entry point might be better
11965 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11966 DAG.getNode(X86ISD::GlobalBaseReg,
11967 SDLoc(), PtrVT), InFlag);
11968 InFlag = Chain.getValue(1);
11970 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11973 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11975 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11977 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11978 X86::RAX, X86II::MO_TLSGD);
11981 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11987 // Get the start address of the TLS block for this module.
11988 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11989 .getInfo<X86MachineFunctionInfo>();
11990 MFI->incNumLocalDynamicTLSAccesses();
11994 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11995 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11998 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11999 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12000 InFlag = Chain.getValue(1);
12001 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12002 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12005 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12009 unsigned char OperandFlags = X86II::MO_DTPOFF;
12010 unsigned WrapperKind = X86ISD::Wrapper;
12011 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12012 GA->getValueType(0),
12013 GA->getOffset(), OperandFlags);
12014 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12016 // Add x@dtpoff with the base.
12017 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12020 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12021 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12022 const EVT PtrVT, TLSModel::Model model,
12023 bool is64Bit, bool isPIC) {
12026 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12027 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12028 is64Bit ? 257 : 256));
12030 SDValue ThreadPointer =
12031 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12032 MachinePointerInfo(Ptr), false, false, false, 0);
12034 unsigned char OperandFlags = 0;
12035 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12037 unsigned WrapperKind = X86ISD::Wrapper;
12038 if (model == TLSModel::LocalExec) {
12039 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12040 } else if (model == TLSModel::InitialExec) {
12042 OperandFlags = X86II::MO_GOTTPOFF;
12043 WrapperKind = X86ISD::WrapperRIP;
12045 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12048 llvm_unreachable("Unexpected model");
12051 // emit "addl x@ntpoff,%eax" (local exec)
12052 // or "addl x@indntpoff,%eax" (initial exec)
12053 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12055 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12056 GA->getOffset(), OperandFlags);
12057 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12059 if (model == TLSModel::InitialExec) {
12060 if (isPIC && !is64Bit) {
12061 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12062 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12066 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12067 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12068 false, false, false, 0);
12071 // The address of the thread local variable is the add of the thread
12072 // pointer with the offset of the variable.
12073 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12077 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12079 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12080 const GlobalValue *GV = GA->getGlobal();
12081 auto PtrVT = getPointerTy(DAG.getDataLayout());
12083 if (Subtarget->isTargetELF()) {
12084 if (DAG.getTarget().Options.EmulatedTLS)
12085 return LowerToTLSEmulatedModel(GA, DAG);
12086 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12088 case TLSModel::GeneralDynamic:
12089 if (Subtarget->is64Bit())
12090 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12091 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12092 case TLSModel::LocalDynamic:
12093 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12094 Subtarget->is64Bit());
12095 case TLSModel::InitialExec:
12096 case TLSModel::LocalExec:
12097 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12098 DAG.getTarget().getRelocationModel() ==
12101 llvm_unreachable("Unknown TLS model.");
12104 if (Subtarget->isTargetDarwin()) {
12105 // Darwin only has one model of TLS. Lower to that.
12106 unsigned char OpFlag = 0;
12107 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12108 X86ISD::WrapperRIP : X86ISD::Wrapper;
12110 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12111 // global base reg.
12112 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12113 !Subtarget->is64Bit();
12115 OpFlag = X86II::MO_TLVP_PIC_BASE;
12117 OpFlag = X86II::MO_TLVP;
12119 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12120 GA->getValueType(0),
12121 GA->getOffset(), OpFlag);
12122 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12124 // With PIC32, the address is actually $g + Offset.
12126 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12127 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12130 // Lowering the machine isd will make sure everything is in the right
12132 SDValue Chain = DAG.getEntryNode();
12133 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12134 SDValue Args[] = { Chain, Offset };
12135 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12137 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12138 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12139 MFI->setAdjustsStack(true);
12141 // And our return value (tls address) is in the standard call return value
12143 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12144 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12147 if (Subtarget->isTargetKnownWindowsMSVC() ||
12148 Subtarget->isTargetWindowsGNU()) {
12149 // Just use the implicit TLS architecture
12150 // Need to generate someting similar to:
12151 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12153 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12154 // mov rcx, qword [rdx+rcx*8]
12155 // mov eax, .tls$:tlsvar
12156 // [rax+rcx] contains the address
12157 // Windows 64bit: gs:0x58
12158 // Windows 32bit: fs:__tls_array
12161 SDValue Chain = DAG.getEntryNode();
12163 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12164 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12165 // use its literal value of 0x2C.
12166 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12167 ? Type::getInt8PtrTy(*DAG.getContext(),
12169 : Type::getInt32PtrTy(*DAG.getContext(),
12172 SDValue TlsArray = Subtarget->is64Bit()
12173 ? DAG.getIntPtrConstant(0x58, dl)
12174 : (Subtarget->isTargetWindowsGNU()
12175 ? DAG.getIntPtrConstant(0x2C, dl)
12176 : DAG.getExternalSymbol("_tls_array", PtrVT));
12178 SDValue ThreadPointer =
12179 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12183 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12184 res = ThreadPointer;
12186 // Load the _tls_index variable
12187 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12188 if (Subtarget->is64Bit())
12189 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12190 MachinePointerInfo(), MVT::i32, false, false,
12193 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12196 auto &DL = DAG.getDataLayout();
12198 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12199 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12201 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12204 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12207 // Get the offset of start of .tls section
12208 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12209 GA->getValueType(0),
12210 GA->getOffset(), X86II::MO_SECREL);
12211 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12213 // The address of the thread local variable is the add of the thread
12214 // pointer with the offset of the variable.
12215 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12218 llvm_unreachable("TLS not implemented for this target.");
12221 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12222 /// and take a 2 x i32 value to shift plus a shift amount.
12223 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12224 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12225 MVT VT = Op.getSimpleValueType();
12226 unsigned VTBits = VT.getSizeInBits();
12228 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12229 SDValue ShOpLo = Op.getOperand(0);
12230 SDValue ShOpHi = Op.getOperand(1);
12231 SDValue ShAmt = Op.getOperand(2);
12232 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12233 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12235 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12236 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12237 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12238 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12239 : DAG.getConstant(0, dl, VT);
12241 SDValue Tmp2, Tmp3;
12242 if (Op.getOpcode() == ISD::SHL_PARTS) {
12243 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12244 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12246 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12247 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12250 // If the shift amount is larger or equal than the width of a part we can't
12251 // rely on the results of shld/shrd. Insert a test and select the appropriate
12252 // values for large shift amounts.
12253 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12254 DAG.getConstant(VTBits, dl, MVT::i8));
12255 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12256 AndNode, DAG.getConstant(0, dl, MVT::i8));
12259 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12260 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12261 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12263 if (Op.getOpcode() == ISD::SHL_PARTS) {
12264 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12265 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12267 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12268 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12271 SDValue Ops[2] = { Lo, Hi };
12272 return DAG.getMergeValues(Ops, dl);
12275 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12276 SelectionDAG &DAG) const {
12277 SDValue Src = Op.getOperand(0);
12278 MVT SrcVT = Src.getSimpleValueType();
12279 MVT VT = Op.getSimpleValueType();
12282 if (SrcVT.isVector()) {
12283 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12284 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12285 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12286 DAG.getUNDEF(SrcVT)));
12288 if (SrcVT.getVectorElementType() == MVT::i1) {
12289 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12290 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12291 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12296 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12297 "Unknown SINT_TO_FP to lower!");
12299 // These are really Legal; return the operand so the caller accepts it as
12301 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12303 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12304 Subtarget->is64Bit()) {
12308 unsigned Size = SrcVT.getSizeInBits()/8;
12309 MachineFunction &MF = DAG.getMachineFunction();
12310 auto PtrVT = getPointerTy(MF.getDataLayout());
12311 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12312 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12313 SDValue Chain = DAG.getStore(
12314 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12315 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12317 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12320 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12322 SelectionDAG &DAG) const {
12326 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12328 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12330 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12332 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12334 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12335 MachineMemOperand *MMO;
12337 int SSFI = FI->getIndex();
12338 MMO = DAG.getMachineFunction().getMachineMemOperand(
12339 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12340 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12342 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12343 StackSlot = StackSlot.getOperand(1);
12345 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12346 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12348 Tys, Ops, SrcVT, MMO);
12351 Chain = Result.getValue(1);
12352 SDValue InFlag = Result.getValue(2);
12354 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12355 // shouldn't be necessary except that RFP cannot be live across
12356 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12357 MachineFunction &MF = DAG.getMachineFunction();
12358 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12359 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12360 auto PtrVT = getPointerTy(MF.getDataLayout());
12361 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12362 Tys = DAG.getVTList(MVT::Other);
12364 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12366 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12367 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12368 MachineMemOperand::MOStore, SSFISize, SSFISize);
12370 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12371 Ops, Op.getValueType(), MMO);
12372 Result = DAG.getLoad(
12373 Op.getValueType(), DL, Chain, StackSlot,
12374 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12375 false, false, false, 0);
12381 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12382 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12383 SelectionDAG &DAG) const {
12384 // This algorithm is not obvious. Here it is what we're trying to output:
12387 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12388 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12390 haddpd %xmm0, %xmm0
12392 pshufd $0x4e, %xmm0, %xmm1
12398 LLVMContext *Context = DAG.getContext();
12400 // Build some magic constants.
12401 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12402 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12403 auto PtrVT = getPointerTy(DAG.getDataLayout());
12404 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12406 SmallVector<Constant*,2> CV1;
12408 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12409 APInt(64, 0x4330000000000000ULL))));
12411 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12412 APInt(64, 0x4530000000000000ULL))));
12413 Constant *C1 = ConstantVector::get(CV1);
12414 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12416 // Load the 64-bit value into an XMM register.
12417 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12420 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12421 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12422 false, false, false, 16);
12424 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12427 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12428 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12429 false, false, false, 16);
12430 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12431 // TODO: Are there any fast-math-flags to propagate here?
12432 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12435 if (Subtarget->hasSSE3()) {
12436 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12437 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12439 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12440 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12442 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12443 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12446 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12447 DAG.getIntPtrConstant(0, dl));
12450 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12451 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12452 SelectionDAG &DAG) const {
12454 // FP constant to bias correct the final result.
12455 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12458 // Load the 32-bit value into an XMM register.
12459 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12462 // Zero out the upper parts of the register.
12463 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12465 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12466 DAG.getBitcast(MVT::v2f64, Load),
12467 DAG.getIntPtrConstant(0, dl));
12469 // Or the load with the bias.
12470 SDValue Or = DAG.getNode(
12471 ISD::OR, dl, MVT::v2i64,
12472 DAG.getBitcast(MVT::v2i64,
12473 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12474 DAG.getBitcast(MVT::v2i64,
12475 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12477 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12478 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12480 // Subtract the bias.
12481 // TODO: Are there any fast-math-flags to propagate here?
12482 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12484 // Handle final rounding.
12485 EVT DestVT = Op.getValueType();
12487 if (DestVT.bitsLT(MVT::f64))
12488 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12489 DAG.getIntPtrConstant(0, dl));
12490 if (DestVT.bitsGT(MVT::f64))
12491 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12493 // Handle final rounding.
12497 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12498 const X86Subtarget &Subtarget) {
12499 // The algorithm is the following:
12500 // #ifdef __SSE4_1__
12501 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12502 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12503 // (uint4) 0x53000000, 0xaa);
12505 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12506 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12508 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12509 // return (float4) lo + fhi;
12511 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12512 // reassociate the two FADDs, and if we do that, the algorithm fails
12513 // spectacularly (PR24512).
12514 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12515 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12516 // there's also the MachineCombiner reassociations happening on Machine IR.
12517 if (DAG.getTarget().Options.UnsafeFPMath)
12521 SDValue V = Op->getOperand(0);
12522 EVT VecIntVT = V.getValueType();
12523 bool Is128 = VecIntVT == MVT::v4i32;
12524 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12525 // If we convert to something else than the supported type, e.g., to v4f64,
12527 if (VecFloatVT != Op->getValueType(0))
12530 unsigned NumElts = VecIntVT.getVectorNumElements();
12531 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12532 "Unsupported custom type");
12533 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12535 // In the #idef/#else code, we have in common:
12536 // - The vector of constants:
12542 // Create the splat vector for 0x4b000000.
12543 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12544 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12545 CstLow, CstLow, CstLow, CstLow};
12546 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12547 makeArrayRef(&CstLowArray[0], NumElts));
12548 // Create the splat vector for 0x53000000.
12549 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12550 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12551 CstHigh, CstHigh, CstHigh, CstHigh};
12552 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12553 makeArrayRef(&CstHighArray[0], NumElts));
12555 // Create the right shift.
12556 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12557 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12558 CstShift, CstShift, CstShift, CstShift};
12559 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12560 makeArrayRef(&CstShiftArray[0], NumElts));
12561 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12564 if (Subtarget.hasSSE41()) {
12565 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12566 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12567 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12568 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12569 // Low will be bitcasted right away, so do not bother bitcasting back to its
12571 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12572 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12573 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12574 // (uint4) 0x53000000, 0xaa);
12575 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12576 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12577 // High will be bitcasted right away, so do not bother bitcasting back to
12578 // its original type.
12579 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12580 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12582 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12583 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12584 CstMask, CstMask, CstMask);
12585 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12586 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12587 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12589 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12590 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12593 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12594 SDValue CstFAdd = DAG.getConstantFP(
12595 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12596 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12597 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12598 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12599 makeArrayRef(&CstFAddArray[0], NumElts));
12601 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12602 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12603 // TODO: Are there any fast-math-flags to propagate here?
12605 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12606 // return (float4) lo + fhi;
12607 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12608 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12611 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12612 SelectionDAG &DAG) const {
12613 SDValue N0 = Op.getOperand(0);
12614 MVT SVT = N0.getSimpleValueType();
12617 switch (SVT.SimpleTy) {
12619 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12624 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12625 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12626 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12630 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12633 if (Subtarget->hasAVX512())
12634 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12635 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12637 llvm_unreachable(nullptr);
12640 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12641 SelectionDAG &DAG) const {
12642 SDValue N0 = Op.getOperand(0);
12644 auto PtrVT = getPointerTy(DAG.getDataLayout());
12646 if (Op.getValueType().isVector())
12647 return lowerUINT_TO_FP_vec(Op, DAG);
12649 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12650 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12651 // the optimization here.
12652 if (DAG.SignBitIsZero(N0))
12653 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12655 MVT SrcVT = N0.getSimpleValueType();
12656 MVT DstVT = Op.getSimpleValueType();
12658 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12659 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12660 // Conversions from unsigned i32 to f32/f64 are legal,
12661 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12665 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12666 return LowerUINT_TO_FP_i64(Op, DAG);
12667 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12668 return LowerUINT_TO_FP_i32(Op, DAG);
12669 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12672 // Make a 64-bit buffer, and use it to build an FILD.
12673 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12674 if (SrcVT == MVT::i32) {
12675 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12676 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12677 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12678 StackSlot, MachinePointerInfo(),
12680 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12681 OffsetSlot, MachinePointerInfo(),
12683 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12687 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12688 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12689 StackSlot, MachinePointerInfo(),
12691 // For i64 source, we need to add the appropriate power of 2 if the input
12692 // was negative. This is the same as the optimization in
12693 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12694 // we must be careful to do the computation in x87 extended precision, not
12695 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12696 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12697 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12698 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12699 MachineMemOperand::MOLoad, 8, 8);
12701 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12702 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12703 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12706 APInt FF(32, 0x5F800000ULL);
12708 // Check whether the sign bit is set.
12709 SDValue SignSet = DAG.getSetCC(
12710 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12711 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12713 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12714 SDValue FudgePtr = DAG.getConstantPool(
12715 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12717 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12718 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12719 SDValue Four = DAG.getIntPtrConstant(4, dl);
12720 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12722 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12724 // Load the value out, extending it from f32 to f80.
12725 // FIXME: Avoid the extend by constructing the right constant pool?
12726 SDValue Fudge = DAG.getExtLoad(
12727 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12728 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12729 false, false, false, 4);
12730 // Extend everything to 80 bits to force it to be done on x87.
12731 // TODO: Are there any fast-math-flags to propagate here?
12732 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12733 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12734 DAG.getIntPtrConstant(0, dl));
12737 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12738 // is legal, or has an f16 source (which needs to be promoted to f32),
12739 // just return an <SDValue(), SDValue()> pair.
12740 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12741 // to i16, i32 or i64, and we lower it to a legal sequence.
12742 // If lowered to the final integer result we return a <result, SDValue()> pair.
12743 // Otherwise we lower it to a sequence ending with a FIST, return a
12744 // <FIST, StackSlot> pair, and the caller is responsible for loading
12745 // the final integer result from StackSlot.
12746 std::pair<SDValue,SDValue>
12747 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12748 bool IsSigned, bool IsReplace) const {
12751 EVT DstTy = Op.getValueType();
12752 EVT TheVT = Op.getOperand(0).getValueType();
12753 auto PtrVT = getPointerTy(DAG.getDataLayout());
12755 if (TheVT == MVT::f16)
12756 // We need to promote the f16 to f32 before using the lowering
12757 // in this routine.
12758 return std::make_pair(SDValue(), SDValue());
12760 assert((TheVT == MVT::f32 ||
12761 TheVT == MVT::f64 ||
12762 TheVT == MVT::f80) &&
12763 "Unexpected FP operand type in FP_TO_INTHelper");
12765 // If using FIST to compute an unsigned i64, we'll need some fixup
12766 // to handle values above the maximum signed i64. A FIST is always
12767 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12768 bool UnsignedFixup = !IsSigned &&
12769 DstTy == MVT::i64 &&
12770 (!Subtarget->is64Bit() ||
12771 !isScalarFPTypeInSSEReg(TheVT));
12773 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12774 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12775 // The low 32 bits of the fist result will have the correct uint32 result.
12776 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12780 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12781 DstTy.getSimpleVT() >= MVT::i16 &&
12782 "Unknown FP_TO_INT to lower!");
12784 // These are really Legal.
12785 if (DstTy == MVT::i32 &&
12786 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12787 return std::make_pair(SDValue(), SDValue());
12788 if (Subtarget->is64Bit() &&
12789 DstTy == MVT::i64 &&
12790 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12791 return std::make_pair(SDValue(), SDValue());
12793 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12795 MachineFunction &MF = DAG.getMachineFunction();
12796 unsigned MemSize = DstTy.getSizeInBits()/8;
12797 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12798 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12801 switch (DstTy.getSimpleVT().SimpleTy) {
12802 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12803 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12804 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12805 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12808 SDValue Chain = DAG.getEntryNode();
12809 SDValue Value = Op.getOperand(0);
12810 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12812 if (UnsignedFixup) {
12814 // Conversion to unsigned i64 is implemented with a select,
12815 // depending on whether the source value fits in the range
12816 // of a signed i64. Let Thresh be the FP equivalent of
12817 // 0x8000000000000000ULL.
12819 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12820 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12821 // Fist-to-mem64 FistSrc
12822 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12823 // to XOR'ing the high 32 bits with Adjust.
12825 // Being a power of 2, Thresh is exactly representable in all FP formats.
12826 // For X87 we'd like to use the smallest FP type for this constant, but
12827 // for DAG type consistency we have to match the FP operand type.
12829 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12830 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12831 bool LosesInfo = false;
12832 if (TheVT == MVT::f64)
12833 // The rounding mode is irrelevant as the conversion should be exact.
12834 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12836 else if (TheVT == MVT::f80)
12837 Status = Thresh.convert(APFloat::x87DoubleExtended,
12838 APFloat::rmNearestTiesToEven, &LosesInfo);
12840 assert(Status == APFloat::opOK && !LosesInfo &&
12841 "FP conversion should have been exact");
12843 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12845 SDValue Cmp = DAG.getSetCC(DL,
12846 getSetCCResultType(DAG.getDataLayout(),
12847 *DAG.getContext(), TheVT),
12848 Value, ThreshVal, ISD::SETLT);
12849 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12850 DAG.getConstant(0, DL, MVT::i32),
12851 DAG.getConstant(0x80000000, DL, MVT::i32));
12852 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12853 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12854 *DAG.getContext(), TheVT),
12855 Value, ThreshVal, ISD::SETLT);
12856 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12859 // FIXME This causes a redundant load/store if the SSE-class value is already
12860 // in memory, such as if it is on the callstack.
12861 if (isScalarFPTypeInSSEReg(TheVT)) {
12862 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12863 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12864 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12866 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12868 Chain, StackSlot, DAG.getValueType(TheVT)
12871 MachineMemOperand *MMO =
12872 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12873 MachineMemOperand::MOLoad, MemSize, MemSize);
12874 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12875 Chain = Value.getValue(1);
12876 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12877 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12880 MachineMemOperand *MMO =
12881 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12882 MachineMemOperand::MOStore, MemSize, MemSize);
12884 if (UnsignedFixup) {
12886 // Insert the FIST, load its result as two i32's,
12887 // and XOR the high i32 with Adjust.
12889 SDValue FistOps[] = { Chain, Value, StackSlot };
12890 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12891 FistOps, DstTy, MMO);
12893 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12894 MachinePointerInfo(),
12895 false, false, false, 0);
12896 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12897 DAG.getConstant(4, DL, PtrVT));
12899 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12900 MachinePointerInfo(),
12901 false, false, false, 0);
12902 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12904 if (Subtarget->is64Bit()) {
12905 // Join High32 and Low32 into a 64-bit result.
12906 // (High32 << 32) | Low32
12907 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12908 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12909 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12910 DAG.getConstant(32, DL, MVT::i8));
12911 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12912 return std::make_pair(Result, SDValue());
12915 SDValue ResultOps[] = { Low32, High32 };
12917 SDValue pair = IsReplace
12918 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12919 : DAG.getMergeValues(ResultOps, DL);
12920 return std::make_pair(pair, SDValue());
12922 // Build the FP_TO_INT*_IN_MEM
12923 SDValue Ops[] = { Chain, Value, StackSlot };
12924 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12926 return std::make_pair(FIST, StackSlot);
12930 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12931 const X86Subtarget *Subtarget) {
12932 MVT VT = Op->getSimpleValueType(0);
12933 SDValue In = Op->getOperand(0);
12934 MVT InVT = In.getSimpleValueType();
12937 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12938 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12940 // Optimize vectors in AVX mode:
12943 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12944 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12945 // Concat upper and lower parts.
12948 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12949 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12950 // Concat upper and lower parts.
12953 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12954 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12955 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12958 if (Subtarget->hasInt256())
12959 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12961 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12962 SDValue Undef = DAG.getUNDEF(InVT);
12963 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12964 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12965 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12967 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12968 VT.getVectorNumElements()/2);
12970 OpLo = DAG.getBitcast(HVT, OpLo);
12971 OpHi = DAG.getBitcast(HVT, OpHi);
12973 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12976 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12977 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12978 MVT VT = Op->getSimpleValueType(0);
12979 SDValue In = Op->getOperand(0);
12980 MVT InVT = In.getSimpleValueType();
12982 unsigned int NumElts = VT.getVectorNumElements();
12983 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12986 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12987 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12989 assert(InVT.getVectorElementType() == MVT::i1);
12990 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12992 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12994 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12996 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12997 if (VT.is512BitVector())
12999 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13002 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13003 SelectionDAG &DAG) {
13004 if (Subtarget->hasFp256())
13005 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13011 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13012 SelectionDAG &DAG) {
13014 MVT VT = Op.getSimpleValueType();
13015 SDValue In = Op.getOperand(0);
13016 MVT SVT = In.getSimpleValueType();
13018 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13019 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13021 if (Subtarget->hasFp256())
13022 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13025 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13026 VT.getVectorNumElements() != SVT.getVectorNumElements());
13030 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13032 MVT VT = Op.getSimpleValueType();
13033 SDValue In = Op.getOperand(0);
13034 MVT InVT = In.getSimpleValueType();
13036 if (VT == MVT::i1) {
13037 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13038 "Invalid scalar TRUNCATE operation");
13039 if (InVT.getSizeInBits() >= 32)
13041 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13042 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13044 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13045 "Invalid TRUNCATE operation");
13047 // move vector to mask - truncate solution for SKX
13048 if (VT.getVectorElementType() == MVT::i1) {
13049 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13050 Subtarget->hasBWI())
13051 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13052 if ((InVT.is256BitVector() || InVT.is128BitVector())
13053 && InVT.getScalarSizeInBits() <= 16 &&
13054 Subtarget->hasBWI() && Subtarget->hasVLX())
13055 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13056 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13057 Subtarget->hasDQI())
13058 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13059 if ((InVT.is256BitVector() || InVT.is128BitVector())
13060 && InVT.getScalarSizeInBits() >= 32 &&
13061 Subtarget->hasDQI() && Subtarget->hasVLX())
13062 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13065 if (VT.getVectorElementType() == MVT::i1) {
13066 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13067 unsigned NumElts = InVT.getVectorNumElements();
13068 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13069 if (InVT.getSizeInBits() < 512) {
13070 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13071 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13076 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13077 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13078 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13081 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13082 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
13083 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
13084 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13086 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13087 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13088 if (Subtarget->hasInt256()) {
13089 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13090 In = DAG.getBitcast(MVT::v8i32, In);
13091 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13093 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13094 DAG.getIntPtrConstant(0, DL));
13097 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13098 DAG.getIntPtrConstant(0, DL));
13099 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13100 DAG.getIntPtrConstant(2, DL));
13101 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13102 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13103 static const int ShufMask[] = {0, 2, 4, 6};
13104 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13107 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13108 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13109 if (Subtarget->hasInt256()) {
13110 In = DAG.getBitcast(MVT::v32i8, In);
13112 SmallVector<SDValue,32> pshufbMask;
13113 for (unsigned i = 0; i < 2; ++i) {
13114 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13115 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13116 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13117 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13118 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13119 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13120 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13121 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13122 for (unsigned j = 0; j < 8; ++j)
13123 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13125 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13126 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13127 In = DAG.getBitcast(MVT::v4i64, In);
13129 static const int ShufMask[] = {0, 2, -1, -1};
13130 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13132 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13133 DAG.getIntPtrConstant(0, DL));
13134 return DAG.getBitcast(VT, In);
13137 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13138 DAG.getIntPtrConstant(0, DL));
13140 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13141 DAG.getIntPtrConstant(4, DL));
13143 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13144 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13146 // The PSHUFB mask:
13147 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13148 -1, -1, -1, -1, -1, -1, -1, -1};
13150 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13151 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13152 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13154 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13155 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13157 // The MOVLHPS Mask:
13158 static const int ShufMask2[] = {0, 1, 4, 5};
13159 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13160 return DAG.getBitcast(MVT::v8i16, res);
13163 // Handle truncation of V256 to V128 using shuffles.
13164 if (!VT.is128BitVector() || !InVT.is256BitVector())
13167 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13169 unsigned NumElems = VT.getVectorNumElements();
13170 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13172 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13173 // Prepare truncation shuffle mask
13174 for (unsigned i = 0; i != NumElems; ++i)
13175 MaskVec[i] = i * 2;
13176 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13177 DAG.getUNDEF(NVT), &MaskVec[0]);
13178 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13179 DAG.getIntPtrConstant(0, DL));
13182 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13183 SelectionDAG &DAG) const {
13184 assert(!Op.getSimpleValueType().isVector());
13186 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13187 /*IsSigned=*/ true, /*IsReplace=*/ false);
13188 SDValue FIST = Vals.first, StackSlot = Vals.second;
13189 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13190 if (!FIST.getNode())
13193 if (StackSlot.getNode())
13194 // Load the result.
13195 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13196 FIST, StackSlot, MachinePointerInfo(),
13197 false, false, false, 0);
13199 // The node is the result.
13203 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13204 SelectionDAG &DAG) const {
13205 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13206 /*IsSigned=*/ false, /*IsReplace=*/ false);
13207 SDValue FIST = Vals.first, StackSlot = Vals.second;
13208 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13209 if (!FIST.getNode())
13212 if (StackSlot.getNode())
13213 // Load the result.
13214 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13215 FIST, StackSlot, MachinePointerInfo(),
13216 false, false, false, 0);
13218 // The node is the result.
13222 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13224 MVT VT = Op.getSimpleValueType();
13225 SDValue In = Op.getOperand(0);
13226 MVT SVT = In.getSimpleValueType();
13228 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13230 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13231 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13232 In, DAG.getUNDEF(SVT)));
13235 /// The only differences between FABS and FNEG are the mask and the logic op.
13236 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13237 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13238 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13239 "Wrong opcode for lowering FABS or FNEG.");
13241 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13243 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13244 // into an FNABS. We'll lower the FABS after that if it is still in use.
13246 for (SDNode *User : Op->uses())
13247 if (User->getOpcode() == ISD::FNEG)
13251 MVT VT = Op.getSimpleValueType();
13253 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13254 // decide if we should generate a 16-byte constant mask when we only need 4 or
13255 // 8 bytes for the scalar case.
13261 if (VT.isVector()) {
13263 EltVT = VT.getVectorElementType();
13264 NumElts = VT.getVectorNumElements();
13266 // There are no scalar bitwise logical SSE/AVX instructions, so we
13267 // generate a 16-byte vector constant and logic op even for the scalar case.
13268 // Using a 16-byte mask allows folding the load of the mask with
13269 // the logic op, so it can save (~4 bytes) on code size.
13270 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13272 NumElts = (VT == MVT::f64) ? 2 : 4;
13275 unsigned EltBits = EltVT.getSizeInBits();
13276 LLVMContext *Context = DAG.getContext();
13277 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13279 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13280 Constant *C = ConstantInt::get(*Context, MaskElt);
13281 C = ConstantVector::getSplat(NumElts, C);
13282 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13283 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13284 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13286 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13287 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13288 false, false, false, Alignment);
13290 SDValue Op0 = Op.getOperand(0);
13291 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13293 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13294 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13297 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13299 // For the scalar case extend to a 128-bit vector, perform the logic op,
13300 // and extract the scalar result back out.
13301 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13302 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13303 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13304 DAG.getIntPtrConstant(0, dl));
13307 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13308 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13309 LLVMContext *Context = DAG.getContext();
13310 SDValue Op0 = Op.getOperand(0);
13311 SDValue Op1 = Op.getOperand(1);
13313 MVT VT = Op.getSimpleValueType();
13314 MVT SrcVT = Op1.getSimpleValueType();
13316 // If second operand is smaller, extend it first.
13317 if (SrcVT.bitsLT(VT)) {
13318 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13321 // And if it is bigger, shrink it first.
13322 if (SrcVT.bitsGT(VT)) {
13323 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13327 // At this point the operands and the result should have the same
13328 // type, and that won't be f80 since that is not custom lowered.
13330 const fltSemantics &Sem =
13331 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13332 const unsigned SizeInBits = VT.getSizeInBits();
13334 SmallVector<Constant *, 4> CV(
13335 VT == MVT::f64 ? 2 : 4,
13336 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13338 // First, clear all bits but the sign bit from the second operand (sign).
13339 CV[0] = ConstantFP::get(*Context,
13340 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13341 Constant *C = ConstantVector::get(CV);
13342 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13343 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13345 // Perform all logic operations as 16-byte vectors because there are no
13346 // scalar FP logic instructions in SSE. This allows load folding of the
13347 // constants into the logic instructions.
13348 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13350 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13351 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13352 false, false, false, 16);
13353 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13354 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13356 // Next, clear the sign bit from the first operand (magnitude).
13357 // If it's a constant, we can clear it here.
13358 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13359 APFloat APF = Op0CN->getValueAPF();
13360 // If the magnitude is a positive zero, the sign bit alone is enough.
13361 if (APF.isPosZero())
13362 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13363 DAG.getIntPtrConstant(0, dl));
13365 CV[0] = ConstantFP::get(*Context, APF);
13367 CV[0] = ConstantFP::get(
13369 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13371 C = ConstantVector::get(CV);
13372 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13374 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13375 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13376 false, false, false, 16);
13377 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13378 if (!isa<ConstantFPSDNode>(Op0)) {
13379 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13380 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13382 // OR the magnitude value with the sign bit.
13383 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13384 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13385 DAG.getIntPtrConstant(0, dl));
13388 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13389 SDValue N0 = Op.getOperand(0);
13391 MVT VT = Op.getSimpleValueType();
13393 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13394 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13395 DAG.getConstant(1, dl, VT));
13396 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13399 // Check whether an OR'd tree is PTEST-able.
13400 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13401 SelectionDAG &DAG) {
13402 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13404 if (!Subtarget->hasSSE41())
13407 if (!Op->hasOneUse())
13410 SDNode *N = Op.getNode();
13413 SmallVector<SDValue, 8> Opnds;
13414 DenseMap<SDValue, unsigned> VecInMap;
13415 SmallVector<SDValue, 8> VecIns;
13416 EVT VT = MVT::Other;
13418 // Recognize a special case where a vector is casted into wide integer to
13420 Opnds.push_back(N->getOperand(0));
13421 Opnds.push_back(N->getOperand(1));
13423 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13424 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13425 // BFS traverse all OR'd operands.
13426 if (I->getOpcode() == ISD::OR) {
13427 Opnds.push_back(I->getOperand(0));
13428 Opnds.push_back(I->getOperand(1));
13429 // Re-evaluate the number of nodes to be traversed.
13430 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13434 // Quit if a non-EXTRACT_VECTOR_ELT
13435 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13438 // Quit if without a constant index.
13439 SDValue Idx = I->getOperand(1);
13440 if (!isa<ConstantSDNode>(Idx))
13443 SDValue ExtractedFromVec = I->getOperand(0);
13444 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13445 if (M == VecInMap.end()) {
13446 VT = ExtractedFromVec.getValueType();
13447 // Quit if not 128/256-bit vector.
13448 if (!VT.is128BitVector() && !VT.is256BitVector())
13450 // Quit if not the same type.
13451 if (VecInMap.begin() != VecInMap.end() &&
13452 VT != VecInMap.begin()->first.getValueType())
13454 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13455 VecIns.push_back(ExtractedFromVec);
13457 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13460 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13461 "Not extracted from 128-/256-bit vector.");
13463 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13465 for (DenseMap<SDValue, unsigned>::const_iterator
13466 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13467 // Quit if not all elements are used.
13468 if (I->second != FullMask)
13472 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13474 // Cast all vectors into TestVT for PTEST.
13475 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13476 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13478 // If more than one full vectors are evaluated, OR them first before PTEST.
13479 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13480 // Each iteration will OR 2 nodes and append the result until there is only
13481 // 1 node left, i.e. the final OR'd value of all vectors.
13482 SDValue LHS = VecIns[Slot];
13483 SDValue RHS = VecIns[Slot + 1];
13484 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13487 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13488 VecIns.back(), VecIns.back());
13491 /// \brief return true if \c Op has a use that doesn't just read flags.
13492 static bool hasNonFlagsUse(SDValue Op) {
13493 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13495 SDNode *User = *UI;
13496 unsigned UOpNo = UI.getOperandNo();
13497 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13498 // Look pass truncate.
13499 UOpNo = User->use_begin().getOperandNo();
13500 User = *User->use_begin();
13503 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13504 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13510 /// Emit nodes that will be selected as "test Op0,Op0", or something
13512 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13513 SelectionDAG &DAG) const {
13514 if (Op.getValueType() == MVT::i1) {
13515 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13516 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13517 DAG.getConstant(0, dl, MVT::i8));
13519 // CF and OF aren't always set the way we want. Determine which
13520 // of these we need.
13521 bool NeedCF = false;
13522 bool NeedOF = false;
13525 case X86::COND_A: case X86::COND_AE:
13526 case X86::COND_B: case X86::COND_BE:
13529 case X86::COND_G: case X86::COND_GE:
13530 case X86::COND_L: case X86::COND_LE:
13531 case X86::COND_O: case X86::COND_NO: {
13532 // Check if we really need to set the
13533 // Overflow flag. If NoSignedWrap is present
13534 // that is not actually needed.
13535 switch (Op->getOpcode()) {
13540 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13541 if (BinNode->Flags.hasNoSignedWrap())
13551 // See if we can use the EFLAGS value from the operand instead of
13552 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13553 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13554 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13555 // Emit a CMP with 0, which is the TEST pattern.
13556 //if (Op.getValueType() == MVT::i1)
13557 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13558 // DAG.getConstant(0, MVT::i1));
13559 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13560 DAG.getConstant(0, dl, Op.getValueType()));
13562 unsigned Opcode = 0;
13563 unsigned NumOperands = 0;
13565 // Truncate operations may prevent the merge of the SETCC instruction
13566 // and the arithmetic instruction before it. Attempt to truncate the operands
13567 // of the arithmetic instruction and use a reduced bit-width instruction.
13568 bool NeedTruncation = false;
13569 SDValue ArithOp = Op;
13570 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13571 SDValue Arith = Op->getOperand(0);
13572 // Both the trunc and the arithmetic op need to have one user each.
13573 if (Arith->hasOneUse())
13574 switch (Arith.getOpcode()) {
13581 NeedTruncation = true;
13587 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13588 // which may be the result of a CAST. We use the variable 'Op', which is the
13589 // non-casted variable when we check for possible users.
13590 switch (ArithOp.getOpcode()) {
13592 // Due to an isel shortcoming, be conservative if this add is likely to be
13593 // selected as part of a load-modify-store instruction. When the root node
13594 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13595 // uses of other nodes in the match, such as the ADD in this case. This
13596 // leads to the ADD being left around and reselected, with the result being
13597 // two adds in the output. Alas, even if none our users are stores, that
13598 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13599 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13600 // climbing the DAG back to the root, and it doesn't seem to be worth the
13602 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13603 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13604 if (UI->getOpcode() != ISD::CopyToReg &&
13605 UI->getOpcode() != ISD::SETCC &&
13606 UI->getOpcode() != ISD::STORE)
13609 if (ConstantSDNode *C =
13610 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13611 // An add of one will be selected as an INC.
13612 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13613 Opcode = X86ISD::INC;
13618 // An add of negative one (subtract of one) will be selected as a DEC.
13619 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13620 Opcode = X86ISD::DEC;
13626 // Otherwise use a regular EFLAGS-setting add.
13627 Opcode = X86ISD::ADD;
13632 // If we have a constant logical shift that's only used in a comparison
13633 // against zero turn it into an equivalent AND. This allows turning it into
13634 // a TEST instruction later.
13635 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13636 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13637 EVT VT = Op.getValueType();
13638 unsigned BitWidth = VT.getSizeInBits();
13639 unsigned ShAmt = Op->getConstantOperandVal(1);
13640 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13642 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13643 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13644 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13645 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13647 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13648 DAG.getConstant(Mask, dl, VT));
13649 DAG.ReplaceAllUsesWith(Op, New);
13655 // If the primary and result isn't used, don't bother using X86ISD::AND,
13656 // because a TEST instruction will be better.
13657 if (!hasNonFlagsUse(Op))
13663 // Due to the ISEL shortcoming noted above, be conservative if this op is
13664 // likely to be selected as part of a load-modify-store instruction.
13665 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13666 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13667 if (UI->getOpcode() == ISD::STORE)
13670 // Otherwise use a regular EFLAGS-setting instruction.
13671 switch (ArithOp.getOpcode()) {
13672 default: llvm_unreachable("unexpected operator!");
13673 case ISD::SUB: Opcode = X86ISD::SUB; break;
13674 case ISD::XOR: Opcode = X86ISD::XOR; break;
13675 case ISD::AND: Opcode = X86ISD::AND; break;
13677 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13678 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13679 if (EFLAGS.getNode())
13682 Opcode = X86ISD::OR;
13696 return SDValue(Op.getNode(), 1);
13702 // If we found that truncation is beneficial, perform the truncation and
13704 if (NeedTruncation) {
13705 EVT VT = Op.getValueType();
13706 SDValue WideVal = Op->getOperand(0);
13707 EVT WideVT = WideVal.getValueType();
13708 unsigned ConvertedOp = 0;
13709 // Use a target machine opcode to prevent further DAGCombine
13710 // optimizations that may separate the arithmetic operations
13711 // from the setcc node.
13712 switch (WideVal.getOpcode()) {
13714 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13715 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13716 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13717 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13718 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13722 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13723 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13724 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13725 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13726 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13732 // Emit a CMP with 0, which is the TEST pattern.
13733 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13734 DAG.getConstant(0, dl, Op.getValueType()));
13736 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13737 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13739 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13740 DAG.ReplaceAllUsesWith(Op, New);
13741 return SDValue(New.getNode(), 1);
13744 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13746 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13747 SDLoc dl, SelectionDAG &DAG) const {
13748 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13749 if (C->getAPIntValue() == 0)
13750 return EmitTest(Op0, X86CC, dl, DAG);
13752 if (Op0.getValueType() == MVT::i1)
13753 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13756 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13757 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13758 // Do the comparison at i32 if it's smaller, besides the Atom case.
13759 // This avoids subregister aliasing issues. Keep the smaller reference
13760 // if we're optimizing for size, however, as that'll allow better folding
13761 // of memory operations.
13762 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13763 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13764 !Subtarget->isAtom()) {
13765 unsigned ExtendOp =
13766 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13767 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13768 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13770 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13771 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13772 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13774 return SDValue(Sub.getNode(), 1);
13776 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13779 /// Convert a comparison if required by the subtarget.
13780 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13781 SelectionDAG &DAG) const {
13782 // If the subtarget does not support the FUCOMI instruction, floating-point
13783 // comparisons have to be converted.
13784 if (Subtarget->hasCMov() ||
13785 Cmp.getOpcode() != X86ISD::CMP ||
13786 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13787 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13790 // The instruction selector will select an FUCOM instruction instead of
13791 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13792 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13793 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13795 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13796 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13797 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13798 DAG.getConstant(8, dl, MVT::i8));
13799 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13800 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13803 /// The minimum architected relative accuracy is 2^-12. We need one
13804 /// Newton-Raphson step to have a good float result (24 bits of precision).
13805 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13806 DAGCombinerInfo &DCI,
13807 unsigned &RefinementSteps,
13808 bool &UseOneConstNR) const {
13809 EVT VT = Op.getValueType();
13810 const char *RecipOp;
13812 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13813 // TODO: Add support for AVX512 (v16f32).
13814 // It is likely not profitable to do this for f64 because a double-precision
13815 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13816 // instructions: convert to single, rsqrtss, convert back to double, refine
13817 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13818 // along with FMA, this could be a throughput win.
13819 if (VT == MVT::f32 && Subtarget->hasSSE1())
13821 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13822 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13823 RecipOp = "vec-sqrtf";
13827 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13828 if (!Recips.isEnabled(RecipOp))
13831 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13832 UseOneConstNR = false;
13833 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13836 /// The minimum architected relative accuracy is 2^-12. We need one
13837 /// Newton-Raphson step to have a good float result (24 bits of precision).
13838 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13839 DAGCombinerInfo &DCI,
13840 unsigned &RefinementSteps) const {
13841 EVT VT = Op.getValueType();
13842 const char *RecipOp;
13844 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13845 // TODO: Add support for AVX512 (v16f32).
13846 // It is likely not profitable to do this for f64 because a double-precision
13847 // reciprocal estimate with refinement on x86 prior to FMA requires
13848 // 15 instructions: convert to single, rcpss, convert back to double, refine
13849 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13850 // along with FMA, this could be a throughput win.
13851 if (VT == MVT::f32 && Subtarget->hasSSE1())
13853 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13854 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13855 RecipOp = "vec-divf";
13859 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13860 if (!Recips.isEnabled(RecipOp))
13863 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13864 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13867 /// If we have at least two divisions that use the same divisor, convert to
13868 /// multplication by a reciprocal. This may need to be adjusted for a given
13869 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13870 /// This is because we still need one division to calculate the reciprocal and
13871 /// then we need two multiplies by that reciprocal as replacements for the
13872 /// original divisions.
13873 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13877 static bool isAllOnes(SDValue V) {
13878 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13879 return C && C->isAllOnesValue();
13882 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13883 /// if it's possible.
13884 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13885 SDLoc dl, SelectionDAG &DAG) const {
13886 SDValue Op0 = And.getOperand(0);
13887 SDValue Op1 = And.getOperand(1);
13888 if (Op0.getOpcode() == ISD::TRUNCATE)
13889 Op0 = Op0.getOperand(0);
13890 if (Op1.getOpcode() == ISD::TRUNCATE)
13891 Op1 = Op1.getOperand(0);
13894 if (Op1.getOpcode() == ISD::SHL)
13895 std::swap(Op0, Op1);
13896 if (Op0.getOpcode() == ISD::SHL) {
13897 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13898 if (And00C->getZExtValue() == 1) {
13899 // If we looked past a truncate, check that it's only truncating away
13901 unsigned BitWidth = Op0.getValueSizeInBits();
13902 unsigned AndBitWidth = And.getValueSizeInBits();
13903 if (BitWidth > AndBitWidth) {
13905 DAG.computeKnownBits(Op0, Zeros, Ones);
13906 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13910 RHS = Op0.getOperand(1);
13912 } else if (Op1.getOpcode() == ISD::Constant) {
13913 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13914 uint64_t AndRHSVal = AndRHS->getZExtValue();
13915 SDValue AndLHS = Op0;
13917 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13918 LHS = AndLHS.getOperand(0);
13919 RHS = AndLHS.getOperand(1);
13922 // Use BT if the immediate can't be encoded in a TEST instruction.
13923 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13925 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13929 if (LHS.getNode()) {
13930 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13931 // instruction. Since the shift amount is in-range-or-undefined, we know
13932 // that doing a bittest on the i32 value is ok. We extend to i32 because
13933 // the encoding for the i16 version is larger than the i32 version.
13934 // Also promote i16 to i32 for performance / code size reason.
13935 if (LHS.getValueType() == MVT::i8 ||
13936 LHS.getValueType() == MVT::i16)
13937 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13939 // If the operand types disagree, extend the shift amount to match. Since
13940 // BT ignores high bits (like shifts) we can use anyextend.
13941 if (LHS.getValueType() != RHS.getValueType())
13942 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13944 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13945 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13946 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13947 DAG.getConstant(Cond, dl, MVT::i8), BT);
13953 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13955 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13960 // SSE Condition code mapping:
13969 switch (SetCCOpcode) {
13970 default: llvm_unreachable("Unexpected SETCC condition");
13972 case ISD::SETEQ: SSECC = 0; break;
13974 case ISD::SETGT: Swap = true; // Fallthrough
13976 case ISD::SETOLT: SSECC = 1; break;
13978 case ISD::SETGE: Swap = true; // Fallthrough
13980 case ISD::SETOLE: SSECC = 2; break;
13981 case ISD::SETUO: SSECC = 3; break;
13983 case ISD::SETNE: SSECC = 4; break;
13984 case ISD::SETULE: Swap = true; // Fallthrough
13985 case ISD::SETUGE: SSECC = 5; break;
13986 case ISD::SETULT: Swap = true; // Fallthrough
13987 case ISD::SETUGT: SSECC = 6; break;
13988 case ISD::SETO: SSECC = 7; break;
13990 case ISD::SETONE: SSECC = 8; break;
13993 std::swap(Op0, Op1);
13998 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13999 // ones, and then concatenate the result back.
14000 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14001 MVT VT = Op.getSimpleValueType();
14003 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14004 "Unsupported value type for operation");
14006 unsigned NumElems = VT.getVectorNumElements();
14008 SDValue CC = Op.getOperand(2);
14010 // Extract the LHS vectors
14011 SDValue LHS = Op.getOperand(0);
14012 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14013 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14015 // Extract the RHS vectors
14016 SDValue RHS = Op.getOperand(1);
14017 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14018 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14020 // Issue the operation on the smaller types and concatenate the result back
14021 MVT EltVT = VT.getVectorElementType();
14022 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14023 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14024 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14025 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14028 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14029 SDValue Op0 = Op.getOperand(0);
14030 SDValue Op1 = Op.getOperand(1);
14031 SDValue CC = Op.getOperand(2);
14032 MVT VT = Op.getSimpleValueType();
14035 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
14036 "Unexpected type for boolean compare operation");
14037 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14038 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14039 DAG.getConstant(-1, dl, VT));
14040 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14041 DAG.getConstant(-1, dl, VT));
14042 switch (SetCCOpcode) {
14043 default: llvm_unreachable("Unexpected SETCC condition");
14045 // (x == y) -> ~(x ^ y)
14046 return DAG.getNode(ISD::XOR, dl, VT,
14047 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14048 DAG.getConstant(-1, dl, VT));
14050 // (x != y) -> (x ^ y)
14051 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14054 // (x > y) -> (x & ~y)
14055 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14058 // (x < y) -> (~x & y)
14059 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14062 // (x <= y) -> (~x | y)
14063 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14066 // (x >=y) -> (x | ~y)
14067 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14071 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14072 const X86Subtarget *Subtarget) {
14073 SDValue Op0 = Op.getOperand(0);
14074 SDValue Op1 = Op.getOperand(1);
14075 SDValue CC = Op.getOperand(2);
14076 MVT VT = Op.getSimpleValueType();
14079 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14080 Op.getValueType().getScalarType() == MVT::i1 &&
14081 "Cannot set masked compare for this operation");
14083 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14085 bool Unsigned = false;
14088 switch (SetCCOpcode) {
14089 default: llvm_unreachable("Unexpected SETCC condition");
14090 case ISD::SETNE: SSECC = 4; break;
14091 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14092 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14093 case ISD::SETLT: Swap = true; //fall-through
14094 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14095 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14096 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14097 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14098 case ISD::SETULE: Unsigned = true; //fall-through
14099 case ISD::SETLE: SSECC = 2; break;
14103 std::swap(Op0, Op1);
14105 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14106 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14107 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14108 DAG.getConstant(SSECC, dl, MVT::i8));
14111 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14112 /// operand \p Op1. If non-trivial (for example because it's not constant)
14113 /// return an empty value.
14114 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14116 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14120 MVT VT = Op1.getSimpleValueType();
14121 MVT EVT = VT.getVectorElementType();
14122 unsigned n = VT.getVectorNumElements();
14123 SmallVector<SDValue, 8> ULTOp1;
14125 for (unsigned i = 0; i < n; ++i) {
14126 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14127 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14130 // Avoid underflow.
14131 APInt Val = Elt->getAPIntValue();
14135 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14138 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14141 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14142 SelectionDAG &DAG) {
14143 SDValue Op0 = Op.getOperand(0);
14144 SDValue Op1 = Op.getOperand(1);
14145 SDValue CC = Op.getOperand(2);
14146 MVT VT = Op.getSimpleValueType();
14147 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14148 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14153 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14154 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14157 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14158 unsigned Opc = X86ISD::CMPP;
14159 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14160 assert(VT.getVectorNumElements() <= 16);
14161 Opc = X86ISD::CMPM;
14163 // In the two special cases we can't handle, emit two comparisons.
14166 unsigned CombineOpc;
14167 if (SetCCOpcode == ISD::SETUEQ) {
14168 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14170 assert(SetCCOpcode == ISD::SETONE);
14171 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14174 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14175 DAG.getConstant(CC0, dl, MVT::i8));
14176 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14177 DAG.getConstant(CC1, dl, MVT::i8));
14178 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14180 // Handle all other FP comparisons here.
14181 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14182 DAG.getConstant(SSECC, dl, MVT::i8));
14185 MVT VTOp0 = Op0.getSimpleValueType();
14186 assert(VTOp0 == Op1.getSimpleValueType() &&
14187 "Expected operands with same type!");
14188 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14189 "Invalid number of packed elements for source and destination!");
14191 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14192 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14193 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14194 // legalizer firstly checks if the first operand in input to the setcc has
14195 // a legal type. If so, then it promotes the return type to that same type.
14196 // Otherwise, the return type is promoted to the 'next legal type' which,
14197 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14199 // We reach this code only if the following two conditions are met:
14200 // 1. Both return type and operand type have been promoted to wider types
14201 // by the type legalizer.
14202 // 2. The original operand type has been promoted to a 256-bit vector.
14204 // Note that condition 2. only applies for AVX targets.
14205 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14206 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14209 // The non-AVX512 code below works under the assumption that source and
14210 // destination types are the same.
14211 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14212 "Value types for source and destination must be the same!");
14214 // Break 256-bit integer vector compare into smaller ones.
14215 if (VT.is256BitVector() && !Subtarget->hasInt256())
14216 return Lower256IntVSETCC(Op, DAG);
14218 EVT OpVT = Op1.getValueType();
14219 if (OpVT.getVectorElementType() == MVT::i1)
14220 return LowerBoolVSETCC_AVX512(Op, DAG);
14222 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14223 if (Subtarget->hasAVX512()) {
14224 if (Op1.getValueType().is512BitVector() ||
14225 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14226 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14227 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14229 // In AVX-512 architecture setcc returns mask with i1 elements,
14230 // But there is no compare instruction for i8 and i16 elements in KNL.
14231 // We are not talking about 512-bit operands in this case, these
14232 // types are illegal.
14234 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14235 OpVT.getVectorElementType().getSizeInBits() >= 8))
14236 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14237 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14240 // Lower using XOP integer comparisons.
14241 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14242 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14243 // Translate compare code to XOP PCOM compare mode.
14244 unsigned CmpMode = 0;
14245 switch (SetCCOpcode) {
14246 default: llvm_unreachable("Unexpected SETCC condition");
14248 case ISD::SETLT: CmpMode = 0x00; break;
14250 case ISD::SETLE: CmpMode = 0x01; break;
14252 case ISD::SETGT: CmpMode = 0x02; break;
14254 case ISD::SETGE: CmpMode = 0x03; break;
14255 case ISD::SETEQ: CmpMode = 0x04; break;
14256 case ISD::SETNE: CmpMode = 0x05; break;
14259 // Are we comparing unsigned or signed integers?
14260 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14261 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14263 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14264 DAG.getConstant(CmpMode, dl, MVT::i8));
14267 // We are handling one of the integer comparisons here. Since SSE only has
14268 // GT and EQ comparisons for integer, swapping operands and multiple
14269 // operations may be required for some comparisons.
14271 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14272 bool Subus = false;
14274 switch (SetCCOpcode) {
14275 default: llvm_unreachable("Unexpected SETCC condition");
14276 case ISD::SETNE: Invert = true;
14277 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14278 case ISD::SETLT: Swap = true;
14279 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14280 case ISD::SETGE: Swap = true;
14281 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14282 Invert = true; break;
14283 case ISD::SETULT: Swap = true;
14284 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14285 FlipSigns = true; break;
14286 case ISD::SETUGE: Swap = true;
14287 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14288 FlipSigns = true; Invert = true; break;
14291 // Special case: Use min/max operations for SETULE/SETUGE
14292 MVT VET = VT.getVectorElementType();
14294 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14295 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14298 switch (SetCCOpcode) {
14300 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14301 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14304 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14307 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14308 if (!MinMax && hasSubus) {
14309 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14311 // t = psubus Op0, Op1
14312 // pcmpeq t, <0..0>
14313 switch (SetCCOpcode) {
14315 case ISD::SETULT: {
14316 // If the comparison is against a constant we can turn this into a
14317 // setule. With psubus, setule does not require a swap. This is
14318 // beneficial because the constant in the register is no longer
14319 // destructed as the destination so it can be hoisted out of a loop.
14320 // Only do this pre-AVX since vpcmp* is no longer destructive.
14321 if (Subtarget->hasAVX())
14323 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14324 if (ULEOp1.getNode()) {
14326 Subus = true; Invert = false; Swap = false;
14330 // Psubus is better than flip-sign because it requires no inversion.
14331 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14332 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14336 Opc = X86ISD::SUBUS;
14342 std::swap(Op0, Op1);
14344 // Check that the operation in question is available (most are plain SSE2,
14345 // but PCMPGTQ and PCMPEQQ have different requirements).
14346 if (VT == MVT::v2i64) {
14347 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14348 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14350 // First cast everything to the right type.
14351 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14352 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14354 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14355 // bits of the inputs before performing those operations. The lower
14356 // compare is always unsigned.
14359 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14361 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14362 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14363 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14364 Sign, Zero, Sign, Zero);
14366 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14367 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14369 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14370 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14371 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14373 // Create masks for only the low parts/high parts of the 64 bit integers.
14374 static const int MaskHi[] = { 1, 1, 3, 3 };
14375 static const int MaskLo[] = { 0, 0, 2, 2 };
14376 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14377 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14378 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14380 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14381 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14384 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14386 return DAG.getBitcast(VT, Result);
14389 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14390 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14391 // pcmpeqd + pshufd + pand.
14392 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14394 // First cast everything to the right type.
14395 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14396 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14399 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14401 // Make sure the lower and upper halves are both all-ones.
14402 static const int Mask[] = { 1, 0, 3, 2 };
14403 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14404 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14407 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14409 return DAG.getBitcast(VT, Result);
14413 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14414 // bits of the inputs before performing those operations.
14416 EVT EltVT = VT.getVectorElementType();
14417 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14419 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14420 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14423 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14425 // If the logical-not of the result is required, perform that now.
14427 Result = DAG.getNOT(dl, Result, VT);
14430 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14433 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14434 getZeroVector(VT, Subtarget, DAG, dl));
14439 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14441 MVT VT = Op.getSimpleValueType();
14443 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14445 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14446 && "SetCC type must be 8-bit or 1-bit integer");
14447 SDValue Op0 = Op.getOperand(0);
14448 SDValue Op1 = Op.getOperand(1);
14450 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14452 // Optimize to BT if possible.
14453 // Lower (X & (1 << N)) == 0 to BT(X, N).
14454 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14455 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14456 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14457 Op1.getOpcode() == ISD::Constant &&
14458 cast<ConstantSDNode>(Op1)->isNullValue() &&
14459 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14460 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14461 if (NewSetCC.getNode()) {
14463 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14468 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14470 if (Op1.getOpcode() == ISD::Constant &&
14471 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14472 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14473 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14475 // If the input is a setcc, then reuse the input setcc or use a new one with
14476 // the inverted condition.
14477 if (Op0.getOpcode() == X86ISD::SETCC) {
14478 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14479 bool Invert = (CC == ISD::SETNE) ^
14480 cast<ConstantSDNode>(Op1)->isNullValue();
14484 CCode = X86::GetOppositeBranchCondition(CCode);
14485 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14486 DAG.getConstant(CCode, dl, MVT::i8),
14487 Op0.getOperand(1));
14489 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14493 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14494 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14495 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14497 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14498 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14501 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14502 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14503 if (X86CC == X86::COND_INVALID)
14506 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14507 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14508 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14509 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14511 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14515 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14516 static bool isX86LogicalCmp(SDValue Op) {
14517 unsigned Opc = Op.getNode()->getOpcode();
14518 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14519 Opc == X86ISD::SAHF)
14521 if (Op.getResNo() == 1 &&
14522 (Opc == X86ISD::ADD ||
14523 Opc == X86ISD::SUB ||
14524 Opc == X86ISD::ADC ||
14525 Opc == X86ISD::SBB ||
14526 Opc == X86ISD::SMUL ||
14527 Opc == X86ISD::UMUL ||
14528 Opc == X86ISD::INC ||
14529 Opc == X86ISD::DEC ||
14530 Opc == X86ISD::OR ||
14531 Opc == X86ISD::XOR ||
14532 Opc == X86ISD::AND))
14535 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14541 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14542 if (V.getOpcode() != ISD::TRUNCATE)
14545 SDValue VOp0 = V.getOperand(0);
14546 unsigned InBits = VOp0.getValueSizeInBits();
14547 unsigned Bits = V.getValueSizeInBits();
14548 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14551 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14552 bool addTest = true;
14553 SDValue Cond = Op.getOperand(0);
14554 SDValue Op1 = Op.getOperand(1);
14555 SDValue Op2 = Op.getOperand(2);
14557 EVT VT = Op1.getValueType();
14560 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14561 // are available or VBLENDV if AVX is available.
14562 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14563 if (Cond.getOpcode() == ISD::SETCC &&
14564 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14565 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14566 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14567 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14568 int SSECC = translateX86FSETCC(
14569 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14572 if (Subtarget->hasAVX512()) {
14573 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14574 DAG.getConstant(SSECC, DL, MVT::i8));
14575 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14578 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14579 DAG.getConstant(SSECC, DL, MVT::i8));
14581 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14582 // of 3 logic instructions for size savings and potentially speed.
14583 // Unfortunately, there is no scalar form of VBLENDV.
14585 // If either operand is a constant, don't try this. We can expect to
14586 // optimize away at least one of the logic instructions later in that
14587 // case, so that sequence would be faster than a variable blend.
14589 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14590 // uses XMM0 as the selection register. That may need just as many
14591 // instructions as the AND/ANDN/OR sequence due to register moves, so
14594 if (Subtarget->hasAVX() &&
14595 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14597 // Convert to vectors, do a VSELECT, and convert back to scalar.
14598 // All of the conversions should be optimized away.
14600 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14601 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14602 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14603 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14605 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14606 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14608 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14610 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14611 VSel, DAG.getIntPtrConstant(0, DL));
14613 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14614 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14615 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14619 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14621 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14622 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14623 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14624 Op1Scalar = Op1.getOperand(0);
14626 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14627 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14628 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14629 Op2Scalar = Op2.getOperand(0);
14630 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14631 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14632 Op1Scalar.getValueType(),
14633 Cond, Op1Scalar, Op2Scalar);
14634 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14635 return DAG.getBitcast(VT, newSelect);
14636 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14637 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14638 DAG.getIntPtrConstant(0, DL));
14642 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14643 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14644 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14645 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14646 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14647 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14648 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14650 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14653 if (Cond.getOpcode() == ISD::SETCC) {
14654 SDValue NewCond = LowerSETCC(Cond, DAG);
14655 if (NewCond.getNode())
14659 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14660 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14661 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14662 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14663 if (Cond.getOpcode() == X86ISD::SETCC &&
14664 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14665 isZero(Cond.getOperand(1).getOperand(1))) {
14666 SDValue Cmp = Cond.getOperand(1);
14668 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14670 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14671 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14672 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14674 SDValue CmpOp0 = Cmp.getOperand(0);
14675 // Apply further optimizations for special cases
14676 // (select (x != 0), -1, 0) -> neg & sbb
14677 // (select (x == 0), 0, -1) -> neg & sbb
14678 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14679 if (YC->isNullValue() &&
14680 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14681 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14682 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14683 DAG.getConstant(0, DL,
14684 CmpOp0.getValueType()),
14686 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14687 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14688 SDValue(Neg.getNode(), 1));
14692 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14693 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14694 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14696 SDValue Res = // Res = 0 or -1.
14697 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14698 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14700 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14701 Res = DAG.getNOT(DL, Res, Res.getValueType());
14703 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14704 if (!N2C || !N2C->isNullValue())
14705 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14710 // Look past (and (setcc_carry (cmp ...)), 1).
14711 if (Cond.getOpcode() == ISD::AND &&
14712 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14713 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14714 if (C && C->getAPIntValue() == 1)
14715 Cond = Cond.getOperand(0);
14718 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14719 // setting operand in place of the X86ISD::SETCC.
14720 unsigned CondOpcode = Cond.getOpcode();
14721 if (CondOpcode == X86ISD::SETCC ||
14722 CondOpcode == X86ISD::SETCC_CARRY) {
14723 CC = Cond.getOperand(0);
14725 SDValue Cmp = Cond.getOperand(1);
14726 unsigned Opc = Cmp.getOpcode();
14727 MVT VT = Op.getSimpleValueType();
14729 bool IllegalFPCMov = false;
14730 if (VT.isFloatingPoint() && !VT.isVector() &&
14731 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14732 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14734 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14735 Opc == X86ISD::BT) { // FIXME
14739 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14740 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14741 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14742 Cond.getOperand(0).getValueType() != MVT::i8)) {
14743 SDValue LHS = Cond.getOperand(0);
14744 SDValue RHS = Cond.getOperand(1);
14745 unsigned X86Opcode;
14748 switch (CondOpcode) {
14749 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14750 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14751 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14752 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14753 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14754 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14755 default: llvm_unreachable("unexpected overflowing operator");
14757 if (CondOpcode == ISD::UMULO)
14758 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14761 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14763 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14765 if (CondOpcode == ISD::UMULO)
14766 Cond = X86Op.getValue(2);
14768 Cond = X86Op.getValue(1);
14770 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14775 // Look past the truncate if the high bits are known zero.
14776 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14777 Cond = Cond.getOperand(0);
14779 // We know the result of AND is compared against zero. Try to match
14781 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14782 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14783 if (NewSetCC.getNode()) {
14784 CC = NewSetCC.getOperand(0);
14785 Cond = NewSetCC.getOperand(1);
14792 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14793 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14796 // a < b ? -1 : 0 -> RES = ~setcc_carry
14797 // a < b ? 0 : -1 -> RES = setcc_carry
14798 // a >= b ? -1 : 0 -> RES = setcc_carry
14799 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14800 if (Cond.getOpcode() == X86ISD::SUB) {
14801 Cond = ConvertCmpIfNecessary(Cond, DAG);
14802 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14804 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14805 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14806 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14807 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14809 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14810 return DAG.getNOT(DL, Res, Res.getValueType());
14815 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14816 // widen the cmov and push the truncate through. This avoids introducing a new
14817 // branch during isel and doesn't add any extensions.
14818 if (Op.getValueType() == MVT::i8 &&
14819 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14820 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14821 if (T1.getValueType() == T2.getValueType() &&
14822 // Blacklist CopyFromReg to avoid partial register stalls.
14823 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14824 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14825 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14826 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14830 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14831 // condition is true.
14832 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14833 SDValue Ops[] = { Op2, Op1, CC, Cond };
14834 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14837 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14838 const X86Subtarget *Subtarget,
14839 SelectionDAG &DAG) {
14840 MVT VT = Op->getSimpleValueType(0);
14841 SDValue In = Op->getOperand(0);
14842 MVT InVT = In.getSimpleValueType();
14843 MVT VTElt = VT.getVectorElementType();
14844 MVT InVTElt = InVT.getVectorElementType();
14848 if ((InVTElt == MVT::i1) &&
14849 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14850 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14852 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14853 VTElt.getSizeInBits() <= 16)) ||
14855 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14856 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14858 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14859 VTElt.getSizeInBits() >= 32))))
14860 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14862 unsigned int NumElts = VT.getVectorNumElements();
14864 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14867 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14868 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14869 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14870 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14873 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14874 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14876 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14879 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14881 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14882 if (VT.is512BitVector())
14884 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14887 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14888 const X86Subtarget *Subtarget,
14889 SelectionDAG &DAG) {
14890 SDValue In = Op->getOperand(0);
14891 MVT VT = Op->getSimpleValueType(0);
14892 MVT InVT = In.getSimpleValueType();
14893 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14895 MVT InSVT = InVT.getScalarType();
14896 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14898 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14900 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14905 // SSE41 targets can use the pmovsx* instructions directly.
14906 if (Subtarget->hasSSE41())
14907 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14909 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14913 // As SRAI is only available on i16/i32 types, we expand only up to i32
14914 // and handle i64 separately.
14915 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14916 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14917 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14918 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14919 Curr = DAG.getBitcast(CurrVT, Curr);
14922 SDValue SignExt = Curr;
14923 if (CurrVT != InVT) {
14924 unsigned SignExtShift =
14925 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14926 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14927 DAG.getConstant(SignExtShift, dl, MVT::i8));
14933 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14934 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14935 DAG.getConstant(31, dl, MVT::i8));
14936 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14937 return DAG.getBitcast(VT, Ext);
14943 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14944 SelectionDAG &DAG) {
14945 MVT VT = Op->getSimpleValueType(0);
14946 SDValue In = Op->getOperand(0);
14947 MVT InVT = In.getSimpleValueType();
14950 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14951 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14953 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14954 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14955 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14958 if (Subtarget->hasInt256())
14959 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14961 // Optimize vectors in AVX mode
14962 // Sign extend v8i16 to v8i32 and
14965 // Divide input vector into two parts
14966 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14967 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14968 // concat the vectors to original VT
14970 unsigned NumElems = InVT.getVectorNumElements();
14971 SDValue Undef = DAG.getUNDEF(InVT);
14973 SmallVector<int,8> ShufMask1(NumElems, -1);
14974 for (unsigned i = 0; i != NumElems/2; ++i)
14977 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14979 SmallVector<int,8> ShufMask2(NumElems, -1);
14980 for (unsigned i = 0; i != NumElems/2; ++i)
14981 ShufMask2[i] = i + NumElems/2;
14983 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14985 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14986 VT.getVectorNumElements()/2);
14988 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14989 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14991 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14994 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14995 // may emit an illegal shuffle but the expansion is still better than scalar
14996 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14997 // we'll emit a shuffle and a arithmetic shift.
14998 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14999 // TODO: It is possible to support ZExt by zeroing the undef values during
15000 // the shuffle phase or after the shuffle.
15001 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15002 SelectionDAG &DAG) {
15003 MVT RegVT = Op.getSimpleValueType();
15004 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15005 assert(RegVT.isInteger() &&
15006 "We only custom lower integer vector sext loads.");
15008 // Nothing useful we can do without SSE2 shuffles.
15009 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15011 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15013 EVT MemVT = Ld->getMemoryVT();
15014 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15015 unsigned RegSz = RegVT.getSizeInBits();
15017 ISD::LoadExtType Ext = Ld->getExtensionType();
15019 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15020 && "Only anyext and sext are currently implemented.");
15021 assert(MemVT != RegVT && "Cannot extend to the same type");
15022 assert(MemVT.isVector() && "Must load a vector from memory");
15024 unsigned NumElems = RegVT.getVectorNumElements();
15025 unsigned MemSz = MemVT.getSizeInBits();
15026 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15028 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15029 // The only way in which we have a legal 256-bit vector result but not the
15030 // integer 256-bit operations needed to directly lower a sextload is if we
15031 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15032 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15033 // correctly legalized. We do this late to allow the canonical form of
15034 // sextload to persist throughout the rest of the DAG combiner -- it wants
15035 // to fold together any extensions it can, and so will fuse a sign_extend
15036 // of an sextload into a sextload targeting a wider value.
15038 if (MemSz == 128) {
15039 // Just switch this to a normal load.
15040 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15041 "it must be a legal 128-bit vector "
15043 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15044 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15045 Ld->isInvariant(), Ld->getAlignment());
15047 assert(MemSz < 128 &&
15048 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15049 // Do an sext load to a 128-bit vector type. We want to use the same
15050 // number of elements, but elements half as wide. This will end up being
15051 // recursively lowered by this routine, but will succeed as we definitely
15052 // have all the necessary features if we're using AVX1.
15054 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15055 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15057 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15058 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15059 Ld->isNonTemporal(), Ld->isInvariant(),
15060 Ld->getAlignment());
15063 // Replace chain users with the new chain.
15064 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15065 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15067 // Finally, do a normal sign-extend to the desired register.
15068 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15071 // All sizes must be a power of two.
15072 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15073 "Non-power-of-two elements are not custom lowered!");
15075 // Attempt to load the original value using scalar loads.
15076 // Find the largest scalar type that divides the total loaded size.
15077 MVT SclrLoadTy = MVT::i8;
15078 for (MVT Tp : MVT::integer_valuetypes()) {
15079 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15084 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15085 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15087 SclrLoadTy = MVT::f64;
15089 // Calculate the number of scalar loads that we need to perform
15090 // in order to load our vector from memory.
15091 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15093 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15094 "Can only lower sext loads with a single scalar load!");
15096 unsigned loadRegZize = RegSz;
15097 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15100 // Represent our vector as a sequence of elements which are the
15101 // largest scalar that we can load.
15102 EVT LoadUnitVecVT = EVT::getVectorVT(
15103 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15105 // Represent the data using the same element type that is stored in
15106 // memory. In practice, we ''widen'' MemVT.
15108 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15109 loadRegZize / MemVT.getScalarType().getSizeInBits());
15111 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15112 "Invalid vector type");
15114 // We can't shuffle using an illegal type.
15115 assert(TLI.isTypeLegal(WideVecVT) &&
15116 "We only lower types that form legal widened vector types");
15118 SmallVector<SDValue, 8> Chains;
15119 SDValue Ptr = Ld->getBasePtr();
15120 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15121 TLI.getPointerTy(DAG.getDataLayout()));
15122 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15124 for (unsigned i = 0; i < NumLoads; ++i) {
15125 // Perform a single load.
15126 SDValue ScalarLoad =
15127 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15128 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15129 Ld->getAlignment());
15130 Chains.push_back(ScalarLoad.getValue(1));
15131 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15132 // another round of DAGCombining.
15134 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15136 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15137 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15139 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15142 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15144 // Bitcast the loaded value to a vector of the original element type, in
15145 // the size of the target vector type.
15146 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15147 unsigned SizeRatio = RegSz / MemSz;
15149 if (Ext == ISD::SEXTLOAD) {
15150 // If we have SSE4.1, we can directly emit a VSEXT node.
15151 if (Subtarget->hasSSE41()) {
15152 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15153 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15157 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15159 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15160 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15162 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15163 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15167 // Redistribute the loaded elements into the different locations.
15168 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15169 for (unsigned i = 0; i != NumElems; ++i)
15170 ShuffleVec[i * SizeRatio] = i;
15172 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15173 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15175 // Bitcast to the requested type.
15176 Shuff = DAG.getBitcast(RegVT, Shuff);
15177 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15181 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15182 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15183 // from the AND / OR.
15184 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15185 Opc = Op.getOpcode();
15186 if (Opc != ISD::OR && Opc != ISD::AND)
15188 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15189 Op.getOperand(0).hasOneUse() &&
15190 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15191 Op.getOperand(1).hasOneUse());
15194 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15195 // 1 and that the SETCC node has a single use.
15196 static bool isXor1OfSetCC(SDValue Op) {
15197 if (Op.getOpcode() != ISD::XOR)
15199 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15200 if (N1C && N1C->getAPIntValue() == 1) {
15201 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15202 Op.getOperand(0).hasOneUse();
15207 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15208 bool addTest = true;
15209 SDValue Chain = Op.getOperand(0);
15210 SDValue Cond = Op.getOperand(1);
15211 SDValue Dest = Op.getOperand(2);
15214 bool Inverted = false;
15216 if (Cond.getOpcode() == ISD::SETCC) {
15217 // Check for setcc([su]{add,sub,mul}o == 0).
15218 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15219 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15220 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15221 Cond.getOperand(0).getResNo() == 1 &&
15222 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15223 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15224 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15225 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15226 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15227 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15229 Cond = Cond.getOperand(0);
15231 SDValue NewCond = LowerSETCC(Cond, DAG);
15232 if (NewCond.getNode())
15237 // FIXME: LowerXALUO doesn't handle these!!
15238 else if (Cond.getOpcode() == X86ISD::ADD ||
15239 Cond.getOpcode() == X86ISD::SUB ||
15240 Cond.getOpcode() == X86ISD::SMUL ||
15241 Cond.getOpcode() == X86ISD::UMUL)
15242 Cond = LowerXALUO(Cond, DAG);
15245 // Look pass (and (setcc_carry (cmp ...)), 1).
15246 if (Cond.getOpcode() == ISD::AND &&
15247 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15248 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15249 if (C && C->getAPIntValue() == 1)
15250 Cond = Cond.getOperand(0);
15253 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15254 // setting operand in place of the X86ISD::SETCC.
15255 unsigned CondOpcode = Cond.getOpcode();
15256 if (CondOpcode == X86ISD::SETCC ||
15257 CondOpcode == X86ISD::SETCC_CARRY) {
15258 CC = Cond.getOperand(0);
15260 SDValue Cmp = Cond.getOperand(1);
15261 unsigned Opc = Cmp.getOpcode();
15262 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15263 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15267 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15271 // These can only come from an arithmetic instruction with overflow,
15272 // e.g. SADDO, UADDO.
15273 Cond = Cond.getNode()->getOperand(1);
15279 CondOpcode = Cond.getOpcode();
15280 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15281 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15282 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15283 Cond.getOperand(0).getValueType() != MVT::i8)) {
15284 SDValue LHS = Cond.getOperand(0);
15285 SDValue RHS = Cond.getOperand(1);
15286 unsigned X86Opcode;
15289 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15290 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15292 switch (CondOpcode) {
15293 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15295 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15297 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15300 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15301 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15303 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15305 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15308 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15309 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15310 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15311 default: llvm_unreachable("unexpected overflowing operator");
15314 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15315 if (CondOpcode == ISD::UMULO)
15316 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15319 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15321 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15323 if (CondOpcode == ISD::UMULO)
15324 Cond = X86Op.getValue(2);
15326 Cond = X86Op.getValue(1);
15328 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15332 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15333 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15334 if (CondOpc == ISD::OR) {
15335 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15336 // two branches instead of an explicit OR instruction with a
15338 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15339 isX86LogicalCmp(Cmp)) {
15340 CC = Cond.getOperand(0).getOperand(0);
15341 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15342 Chain, Dest, CC, Cmp);
15343 CC = Cond.getOperand(1).getOperand(0);
15347 } else { // ISD::AND
15348 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15349 // two branches instead of an explicit AND instruction with a
15350 // separate test. However, we only do this if this block doesn't
15351 // have a fall-through edge, because this requires an explicit
15352 // jmp when the condition is false.
15353 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15354 isX86LogicalCmp(Cmp) &&
15355 Op.getNode()->hasOneUse()) {
15356 X86::CondCode CCode =
15357 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15358 CCode = X86::GetOppositeBranchCondition(CCode);
15359 CC = DAG.getConstant(CCode, dl, MVT::i8);
15360 SDNode *User = *Op.getNode()->use_begin();
15361 // Look for an unconditional branch following this conditional branch.
15362 // We need this because we need to reverse the successors in order
15363 // to implement FCMP_OEQ.
15364 if (User->getOpcode() == ISD::BR) {
15365 SDValue FalseBB = User->getOperand(1);
15367 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15368 assert(NewBR == User);
15372 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15373 Chain, Dest, CC, Cmp);
15374 X86::CondCode CCode =
15375 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15376 CCode = X86::GetOppositeBranchCondition(CCode);
15377 CC = DAG.getConstant(CCode, dl, MVT::i8);
15383 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15384 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15385 // It should be transformed during dag combiner except when the condition
15386 // is set by a arithmetics with overflow node.
15387 X86::CondCode CCode =
15388 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15389 CCode = X86::GetOppositeBranchCondition(CCode);
15390 CC = DAG.getConstant(CCode, dl, MVT::i8);
15391 Cond = Cond.getOperand(0).getOperand(1);
15393 } else if (Cond.getOpcode() == ISD::SETCC &&
15394 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15395 // For FCMP_OEQ, we can emit
15396 // two branches instead of an explicit AND instruction with a
15397 // separate test. However, we only do this if this block doesn't
15398 // have a fall-through edge, because this requires an explicit
15399 // jmp when the condition is false.
15400 if (Op.getNode()->hasOneUse()) {
15401 SDNode *User = *Op.getNode()->use_begin();
15402 // Look for an unconditional branch following this conditional branch.
15403 // We need this because we need to reverse the successors in order
15404 // to implement FCMP_OEQ.
15405 if (User->getOpcode() == ISD::BR) {
15406 SDValue FalseBB = User->getOperand(1);
15408 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15409 assert(NewBR == User);
15413 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15414 Cond.getOperand(0), Cond.getOperand(1));
15415 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15416 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15417 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15418 Chain, Dest, CC, Cmp);
15419 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15424 } else if (Cond.getOpcode() == ISD::SETCC &&
15425 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15426 // For FCMP_UNE, we can emit
15427 // two branches instead of an explicit AND instruction with a
15428 // separate test. However, we only do this if this block doesn't
15429 // have a fall-through edge, because this requires an explicit
15430 // jmp when the condition is false.
15431 if (Op.getNode()->hasOneUse()) {
15432 SDNode *User = *Op.getNode()->use_begin();
15433 // Look for an unconditional branch following this conditional branch.
15434 // We need this because we need to reverse the successors in order
15435 // to implement FCMP_UNE.
15436 if (User->getOpcode() == ISD::BR) {
15437 SDValue FalseBB = User->getOperand(1);
15439 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15440 assert(NewBR == User);
15443 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15444 Cond.getOperand(0), Cond.getOperand(1));
15445 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15446 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15447 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15448 Chain, Dest, CC, Cmp);
15449 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15459 // Look pass the truncate if the high bits are known zero.
15460 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15461 Cond = Cond.getOperand(0);
15463 // We know the result of AND is compared against zero. Try to match
15465 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15466 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15467 if (NewSetCC.getNode()) {
15468 CC = NewSetCC.getOperand(0);
15469 Cond = NewSetCC.getOperand(1);
15476 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15477 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15478 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15480 Cond = ConvertCmpIfNecessary(Cond, DAG);
15481 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15482 Chain, Dest, CC, Cond);
15485 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15486 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15487 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15488 // that the guard pages used by the OS virtual memory manager are allocated in
15489 // correct sequence.
15491 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15492 SelectionDAG &DAG) const {
15493 MachineFunction &MF = DAG.getMachineFunction();
15494 bool SplitStack = MF.shouldSplitStack();
15495 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15500 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15501 SDNode* Node = Op.getNode();
15503 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15504 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15505 " not tell us which reg is the stack pointer!");
15506 EVT VT = Node->getValueType(0);
15507 SDValue Tmp1 = SDValue(Node, 0);
15508 SDValue Tmp2 = SDValue(Node, 1);
15509 SDValue Tmp3 = Node->getOperand(2);
15510 SDValue Chain = Tmp1.getOperand(0);
15512 // Chain the dynamic stack allocation so that it doesn't modify the stack
15513 // pointer when other instructions are using the stack.
15514 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15517 SDValue Size = Tmp2.getOperand(1);
15518 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15519 Chain = SP.getValue(1);
15520 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15521 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15522 unsigned StackAlign = TFI.getStackAlignment();
15523 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15524 if (Align > StackAlign)
15525 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15526 DAG.getConstant(-(uint64_t)Align, dl, VT));
15527 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15529 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15530 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15533 SDValue Ops[2] = { Tmp1, Tmp2 };
15534 return DAG.getMergeValues(Ops, dl);
15538 SDValue Chain = Op.getOperand(0);
15539 SDValue Size = Op.getOperand(1);
15540 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15541 EVT VT = Op.getNode()->getValueType(0);
15543 bool Is64Bit = Subtarget->is64Bit();
15544 MVT SPTy = getPointerTy(DAG.getDataLayout());
15547 MachineRegisterInfo &MRI = MF.getRegInfo();
15550 // The 64 bit implementation of segmented stacks needs to clobber both r10
15551 // r11. This makes it impossible to use it along with nested parameters.
15552 const Function *F = MF.getFunction();
15554 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15556 if (I->hasNestAttr())
15557 report_fatal_error("Cannot use segmented stacks with functions that "
15558 "have nested arguments.");
15561 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15562 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15563 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15564 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15565 DAG.getRegister(Vreg, SPTy));
15566 SDValue Ops1[2] = { Value, Chain };
15567 return DAG.getMergeValues(Ops1, dl);
15570 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15572 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15573 Flag = Chain.getValue(1);
15574 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15576 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15578 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15579 unsigned SPReg = RegInfo->getStackRegister();
15580 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15581 Chain = SP.getValue(1);
15584 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15585 DAG.getConstant(-(uint64_t)Align, dl, VT));
15586 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15589 SDValue Ops1[2] = { SP, Chain };
15590 return DAG.getMergeValues(Ops1, dl);
15594 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15595 MachineFunction &MF = DAG.getMachineFunction();
15596 auto PtrVT = getPointerTy(MF.getDataLayout());
15597 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15599 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15602 if (!Subtarget->is64Bit() ||
15603 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15604 // vastart just stores the address of the VarArgsFrameIndex slot into the
15605 // memory location argument.
15606 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15607 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15608 MachinePointerInfo(SV), false, false, 0);
15612 // gp_offset (0 - 6 * 8)
15613 // fp_offset (48 - 48 + 8 * 16)
15614 // overflow_arg_area (point to parameters coming in memory).
15616 SmallVector<SDValue, 8> MemOps;
15617 SDValue FIN = Op.getOperand(1);
15619 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15620 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15622 FIN, MachinePointerInfo(SV), false, false, 0);
15623 MemOps.push_back(Store);
15626 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15627 Store = DAG.getStore(Op.getOperand(0), DL,
15628 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15630 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15631 MemOps.push_back(Store);
15633 // Store ptr to overflow_arg_area
15634 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15635 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15636 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15637 MachinePointerInfo(SV, 8),
15639 MemOps.push_back(Store);
15641 // Store ptr to reg_save_area.
15642 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15643 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15644 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15645 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15646 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15647 MemOps.push_back(Store);
15648 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15651 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15652 assert(Subtarget->is64Bit() &&
15653 "LowerVAARG only handles 64-bit va_arg!");
15654 assert(Op.getNode()->getNumOperands() == 4);
15656 MachineFunction &MF = DAG.getMachineFunction();
15657 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15658 // The Win64 ABI uses char* instead of a structure.
15659 return DAG.expandVAArg(Op.getNode());
15661 SDValue Chain = Op.getOperand(0);
15662 SDValue SrcPtr = Op.getOperand(1);
15663 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15664 unsigned Align = Op.getConstantOperandVal(3);
15667 EVT ArgVT = Op.getNode()->getValueType(0);
15668 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15669 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15672 // Decide which area this value should be read from.
15673 // TODO: Implement the AMD64 ABI in its entirety. This simple
15674 // selection mechanism works only for the basic types.
15675 if (ArgVT == MVT::f80) {
15676 llvm_unreachable("va_arg for f80 not yet implemented");
15677 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15678 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15679 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15680 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15682 llvm_unreachable("Unhandled argument type in LowerVAARG");
15685 if (ArgMode == 2) {
15686 // Sanity Check: Make sure using fp_offset makes sense.
15687 assert(!Subtarget->useSoftFloat() &&
15688 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15689 Subtarget->hasSSE1());
15692 // Insert VAARG_64 node into the DAG
15693 // VAARG_64 returns two values: Variable Argument Address, Chain
15694 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15695 DAG.getConstant(ArgMode, dl, MVT::i8),
15696 DAG.getConstant(Align, dl, MVT::i32)};
15697 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15698 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15699 VTs, InstOps, MVT::i64,
15700 MachinePointerInfo(SV),
15702 /*Volatile=*/false,
15704 /*WriteMem=*/true);
15705 Chain = VAARG.getValue(1);
15707 // Load the next argument and return it
15708 return DAG.getLoad(ArgVT, dl,
15711 MachinePointerInfo(),
15712 false, false, false, 0);
15715 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15716 SelectionDAG &DAG) {
15717 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15718 // where a va_list is still an i8*.
15719 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15720 if (Subtarget->isCallingConvWin64(
15721 DAG.getMachineFunction().getFunction()->getCallingConv()))
15722 // Probably a Win64 va_copy.
15723 return DAG.expandVACopy(Op.getNode());
15725 SDValue Chain = Op.getOperand(0);
15726 SDValue DstPtr = Op.getOperand(1);
15727 SDValue SrcPtr = Op.getOperand(2);
15728 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15729 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15732 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15733 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15735 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15738 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15739 // amount is a constant. Takes immediate version of shift as input.
15740 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15741 SDValue SrcOp, uint64_t ShiftAmt,
15742 SelectionDAG &DAG) {
15743 MVT ElementType = VT.getVectorElementType();
15745 // Fold this packed shift into its first operand if ShiftAmt is 0.
15749 // Check for ShiftAmt >= element width
15750 if (ShiftAmt >= ElementType.getSizeInBits()) {
15751 if (Opc == X86ISD::VSRAI)
15752 ShiftAmt = ElementType.getSizeInBits() - 1;
15754 return DAG.getConstant(0, dl, VT);
15757 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15758 && "Unknown target vector shift-by-constant node");
15760 // Fold this packed vector shift into a build vector if SrcOp is a
15761 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15762 if (VT == SrcOp.getSimpleValueType() &&
15763 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15764 SmallVector<SDValue, 8> Elts;
15765 unsigned NumElts = SrcOp->getNumOperands();
15766 ConstantSDNode *ND;
15769 default: llvm_unreachable(nullptr);
15770 case X86ISD::VSHLI:
15771 for (unsigned i=0; i!=NumElts; ++i) {
15772 SDValue CurrentOp = SrcOp->getOperand(i);
15773 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15774 Elts.push_back(CurrentOp);
15777 ND = cast<ConstantSDNode>(CurrentOp);
15778 const APInt &C = ND->getAPIntValue();
15779 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15782 case X86ISD::VSRLI:
15783 for (unsigned i=0; i!=NumElts; ++i) {
15784 SDValue CurrentOp = SrcOp->getOperand(i);
15785 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15786 Elts.push_back(CurrentOp);
15789 ND = cast<ConstantSDNode>(CurrentOp);
15790 const APInt &C = ND->getAPIntValue();
15791 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15794 case X86ISD::VSRAI:
15795 for (unsigned i=0; i!=NumElts; ++i) {
15796 SDValue CurrentOp = SrcOp->getOperand(i);
15797 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15798 Elts.push_back(CurrentOp);
15801 ND = cast<ConstantSDNode>(CurrentOp);
15802 const APInt &C = ND->getAPIntValue();
15803 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15808 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15811 return DAG.getNode(Opc, dl, VT, SrcOp,
15812 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15815 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15816 // may or may not be a constant. Takes immediate version of shift as input.
15817 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15818 SDValue SrcOp, SDValue ShAmt,
15819 SelectionDAG &DAG) {
15820 MVT SVT = ShAmt.getSimpleValueType();
15821 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15823 // Catch shift-by-constant.
15824 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15825 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15826 CShAmt->getZExtValue(), DAG);
15828 // Change opcode to non-immediate version
15830 default: llvm_unreachable("Unknown target vector shift node");
15831 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15832 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15833 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15836 const X86Subtarget &Subtarget =
15837 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15838 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15839 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15840 // Let the shuffle legalizer expand this shift amount node.
15841 SDValue Op0 = ShAmt.getOperand(0);
15842 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15843 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15845 // Need to build a vector containing shift amount.
15846 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15847 SmallVector<SDValue, 4> ShOps;
15848 ShOps.push_back(ShAmt);
15849 if (SVT == MVT::i32) {
15850 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15851 ShOps.push_back(DAG.getUNDEF(SVT));
15853 ShOps.push_back(DAG.getUNDEF(SVT));
15855 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15856 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15859 // The return type has to be a 128-bit type with the same element
15860 // type as the input type.
15861 MVT EltVT = VT.getVectorElementType();
15862 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15864 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15865 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15868 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15869 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15870 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15871 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15872 SDValue PreservedSrc,
15873 const X86Subtarget *Subtarget,
15874 SelectionDAG &DAG) {
15875 EVT VT = Op.getValueType();
15876 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15877 MVT::i1, VT.getVectorNumElements());
15878 SDValue VMask = SDValue();
15879 unsigned OpcodeSelect = ISD::VSELECT;
15882 assert(MaskVT.isSimple() && "invalid mask type");
15884 if (isAllOnes(Mask))
15887 if (MaskVT.bitsGT(Mask.getValueType())) {
15888 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15889 MaskVT.getSizeInBits());
15890 VMask = DAG.getBitcast(MaskVT,
15891 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15893 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15894 Mask.getValueType().getSizeInBits());
15895 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15896 // are extracted by EXTRACT_SUBVECTOR.
15897 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15898 DAG.getBitcast(BitcastVT, Mask),
15899 DAG.getIntPtrConstant(0, dl));
15902 switch (Op.getOpcode()) {
15904 case X86ISD::PCMPEQM:
15905 case X86ISD::PCMPGTM:
15907 case X86ISD::CMPMU:
15908 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15909 case X86ISD::VFPCLASS:
15910 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15911 case X86ISD::VTRUNC:
15912 case X86ISD::VTRUNCS:
15913 case X86ISD::VTRUNCUS:
15914 // We can't use ISD::VSELECT here because it is not always "Legal"
15915 // for the destination type. For example vpmovqb require only AVX512
15916 // and vselect that can operate on byte element type require BWI
15917 OpcodeSelect = X86ISD::SELECT;
15920 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15921 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15922 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15925 /// \brief Creates an SDNode for a predicated scalar operation.
15926 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15927 /// The mask is coming as MVT::i8 and it should be truncated
15928 /// to MVT::i1 while lowering masking intrinsics.
15929 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15930 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15931 /// for a scalar instruction.
15932 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15933 SDValue PreservedSrc,
15934 const X86Subtarget *Subtarget,
15935 SelectionDAG &DAG) {
15936 if (isAllOnes(Mask))
15939 EVT VT = Op.getValueType();
15941 // The mask should be of type MVT::i1
15942 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15944 if (Op.getOpcode() == X86ISD::FSETCC)
15945 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
15947 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15948 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15949 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15952 static int getSEHRegistrationNodeSize(const Function *Fn) {
15953 if (!Fn->hasPersonalityFn())
15954 report_fatal_error(
15955 "querying registration node size for function without personality");
15956 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15957 // WinEHStatePass for the full struct definition.
15958 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15959 case EHPersonality::MSVC_X86SEH: return 24;
15960 case EHPersonality::MSVC_CXX: return 16;
15963 report_fatal_error("can only recover FP for MSVC EH personality functions");
15966 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15967 /// function or when returning to a parent frame after catching an exception, we
15968 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15969 /// Here's the math:
15970 /// RegNodeBase = EntryEBP - RegNodeSize
15971 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15972 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15973 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15974 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15975 SDValue EntryEBP) {
15976 MachineFunction &MF = DAG.getMachineFunction();
15979 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15980 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15982 // It's possible that the parent function no longer has a personality function
15983 // if the exceptional code was optimized away, in which case we just return
15984 // the incoming EBP.
15985 if (!Fn->hasPersonalityFn())
15988 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15990 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15992 MCSymbol *OffsetSym =
15993 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15994 GlobalValue::getRealLinkageName(Fn->getName()));
15995 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15996 SDValue RegNodeFrameOffset =
15997 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15999 // RegNodeBase = EntryEBP - RegNodeSize
16000 // ParentFP = RegNodeBase - RegNodeFrameOffset
16001 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16002 DAG.getConstant(RegNodeSize, dl, PtrVT));
16003 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16006 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16007 SelectionDAG &DAG) {
16009 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16010 EVT VT = Op.getValueType();
16011 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16013 switch(IntrData->Type) {
16014 case INTR_TYPE_1OP:
16015 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16016 case INTR_TYPE_2OP:
16017 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16019 case INTR_TYPE_2OP_IMM8:
16020 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16021 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16022 case INTR_TYPE_3OP:
16023 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16024 Op.getOperand(2), Op.getOperand(3));
16025 case INTR_TYPE_4OP:
16026 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16027 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16028 case INTR_TYPE_1OP_MASK_RM: {
16029 SDValue Src = Op.getOperand(1);
16030 SDValue PassThru = Op.getOperand(2);
16031 SDValue Mask = Op.getOperand(3);
16032 SDValue RoundingMode;
16033 // We allways add rounding mode to the Node.
16034 // If the rounding mode is not specified, we add the
16035 // "current direction" mode.
16036 if (Op.getNumOperands() == 4)
16038 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16040 RoundingMode = Op.getOperand(4);
16041 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16042 if (IntrWithRoundingModeOpcode != 0)
16043 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16044 X86::STATIC_ROUNDING::CUR_DIRECTION)
16045 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16046 dl, Op.getValueType(), Src, RoundingMode),
16047 Mask, PassThru, Subtarget, DAG);
16048 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16050 Mask, PassThru, Subtarget, DAG);
16052 case INTR_TYPE_1OP_MASK: {
16053 SDValue Src = Op.getOperand(1);
16054 SDValue PassThru = Op.getOperand(2);
16055 SDValue Mask = Op.getOperand(3);
16056 // We add rounding mode to the Node when
16057 // - RM Opcode is specified and
16058 // - RM is not "current direction".
16059 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16060 if (IntrWithRoundingModeOpcode != 0) {
16061 SDValue Rnd = Op.getOperand(4);
16062 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16063 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16064 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16065 dl, Op.getValueType(),
16067 Mask, PassThru, Subtarget, DAG);
16070 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16071 Mask, PassThru, Subtarget, DAG);
16073 case INTR_TYPE_SCALAR_MASK: {
16074 SDValue Src1 = Op.getOperand(1);
16075 SDValue Src2 = Op.getOperand(2);
16076 SDValue passThru = Op.getOperand(3);
16077 SDValue Mask = Op.getOperand(4);
16078 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16079 Mask, passThru, Subtarget, DAG);
16081 case INTR_TYPE_SCALAR_MASK_RM: {
16082 SDValue Src1 = Op.getOperand(1);
16083 SDValue Src2 = Op.getOperand(2);
16084 SDValue Src0 = Op.getOperand(3);
16085 SDValue Mask = Op.getOperand(4);
16086 // There are 2 kinds of intrinsics in this group:
16087 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16088 // (2) With rounding mode and sae - 7 operands.
16089 if (Op.getNumOperands() == 6) {
16090 SDValue Sae = Op.getOperand(5);
16091 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16092 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16094 Mask, Src0, Subtarget, DAG);
16096 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16097 SDValue RoundingMode = Op.getOperand(5);
16098 SDValue Sae = Op.getOperand(6);
16099 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16100 RoundingMode, Sae),
16101 Mask, Src0, Subtarget, DAG);
16103 case INTR_TYPE_2OP_MASK:
16104 case INTR_TYPE_2OP_IMM8_MASK: {
16105 SDValue Src1 = Op.getOperand(1);
16106 SDValue Src2 = Op.getOperand(2);
16107 SDValue PassThru = Op.getOperand(3);
16108 SDValue Mask = Op.getOperand(4);
16110 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16111 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16113 // We specify 2 possible opcodes for intrinsics with rounding modes.
16114 // First, we check if the intrinsic may have non-default rounding mode,
16115 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16116 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16117 if (IntrWithRoundingModeOpcode != 0) {
16118 SDValue Rnd = Op.getOperand(5);
16119 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16120 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16121 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16122 dl, Op.getValueType(),
16124 Mask, PassThru, Subtarget, DAG);
16127 // TODO: Intrinsics should have fast-math-flags to propagate.
16128 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16129 Mask, PassThru, Subtarget, DAG);
16131 case INTR_TYPE_2OP_MASK_RM: {
16132 SDValue Src1 = Op.getOperand(1);
16133 SDValue Src2 = Op.getOperand(2);
16134 SDValue PassThru = Op.getOperand(3);
16135 SDValue Mask = Op.getOperand(4);
16136 // We specify 2 possible modes for intrinsics, with/without rounding
16138 // First, we check if the intrinsic have rounding mode (6 operands),
16139 // if not, we set rounding mode to "current".
16141 if (Op.getNumOperands() == 6)
16142 Rnd = Op.getOperand(5);
16144 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16145 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16147 Mask, PassThru, Subtarget, DAG);
16149 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16150 SDValue Src1 = Op.getOperand(1);
16151 SDValue Src2 = Op.getOperand(2);
16152 SDValue Src3 = Op.getOperand(3);
16153 SDValue PassThru = Op.getOperand(4);
16154 SDValue Mask = Op.getOperand(5);
16155 SDValue Sae = Op.getOperand(6);
16157 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16159 Mask, PassThru, Subtarget, DAG);
16161 case INTR_TYPE_3OP_MASK_RM: {
16162 SDValue Src1 = Op.getOperand(1);
16163 SDValue Src2 = Op.getOperand(2);
16164 SDValue Imm = Op.getOperand(3);
16165 SDValue PassThru = Op.getOperand(4);
16166 SDValue Mask = Op.getOperand(5);
16167 // We specify 2 possible modes for intrinsics, with/without rounding
16169 // First, we check if the intrinsic have rounding mode (7 operands),
16170 // if not, we set rounding mode to "current".
16172 if (Op.getNumOperands() == 7)
16173 Rnd = Op.getOperand(6);
16175 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16176 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16177 Src1, Src2, Imm, Rnd),
16178 Mask, PassThru, Subtarget, DAG);
16180 case INTR_TYPE_3OP_IMM8_MASK:
16181 case INTR_TYPE_3OP_MASK:
16182 case INSERT_SUBVEC: {
16183 SDValue Src1 = Op.getOperand(1);
16184 SDValue Src2 = Op.getOperand(2);
16185 SDValue Src3 = Op.getOperand(3);
16186 SDValue PassThru = Op.getOperand(4);
16187 SDValue Mask = Op.getOperand(5);
16189 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16190 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16191 else if (IntrData->Type == INSERT_SUBVEC) {
16192 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16193 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16194 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16195 Imm *= Src2.getValueType().getVectorNumElements();
16196 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16199 // We specify 2 possible opcodes for intrinsics with rounding modes.
16200 // First, we check if the intrinsic may have non-default rounding mode,
16201 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16202 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16203 if (IntrWithRoundingModeOpcode != 0) {
16204 SDValue Rnd = Op.getOperand(6);
16205 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16206 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16207 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16208 dl, Op.getValueType(),
16209 Src1, Src2, Src3, Rnd),
16210 Mask, PassThru, Subtarget, DAG);
16213 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16215 Mask, PassThru, Subtarget, DAG);
16217 case VPERM_3OP_MASKZ:
16218 case VPERM_3OP_MASK:
16221 case FMA_OP_MASK: {
16222 SDValue Src1 = Op.getOperand(1);
16223 SDValue Src2 = Op.getOperand(2);
16224 SDValue Src3 = Op.getOperand(3);
16225 SDValue Mask = Op.getOperand(4);
16226 EVT VT = Op.getValueType();
16227 SDValue PassThru = SDValue();
16229 // set PassThru element
16230 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16231 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16232 else if (IntrData->Type == FMA_OP_MASK3)
16237 // We specify 2 possible opcodes for intrinsics with rounding modes.
16238 // First, we check if the intrinsic may have non-default rounding mode,
16239 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16240 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16241 if (IntrWithRoundingModeOpcode != 0) {
16242 SDValue Rnd = Op.getOperand(5);
16243 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16244 X86::STATIC_ROUNDING::CUR_DIRECTION)
16245 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16246 dl, Op.getValueType(),
16247 Src1, Src2, Src3, Rnd),
16248 Mask, PassThru, Subtarget, DAG);
16250 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16251 dl, Op.getValueType(),
16253 Mask, PassThru, Subtarget, DAG);
16255 case TERLOG_OP_MASK:
16256 case TERLOG_OP_MASKZ: {
16257 SDValue Src1 = Op.getOperand(1);
16258 SDValue Src2 = Op.getOperand(2);
16259 SDValue Src3 = Op.getOperand(3);
16260 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16261 SDValue Mask = Op.getOperand(5);
16262 EVT VT = Op.getValueType();
16263 SDValue PassThru = Src1;
16264 // Set PassThru element.
16265 if (IntrData->Type == TERLOG_OP_MASKZ)
16266 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16268 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16269 Src1, Src2, Src3, Src4),
16270 Mask, PassThru, Subtarget, DAG);
16273 // FPclass intrinsics with mask
16274 SDValue Src1 = Op.getOperand(1);
16275 EVT VT = Src1.getValueType();
16276 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16277 VT.getVectorNumElements());
16278 SDValue Imm = Op.getOperand(2);
16279 SDValue Mask = Op.getOperand(3);
16280 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16281 Mask.getValueType().getSizeInBits());
16282 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16283 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16284 DAG.getTargetConstant(0, dl, MaskVT),
16286 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16287 DAG.getUNDEF(BitcastVT), FPclassMask,
16288 DAG.getIntPtrConstant(0, dl));
16289 return DAG.getBitcast(Op.getValueType(), Res);
16292 case CMP_MASK_CC: {
16293 // Comparison intrinsics with masks.
16294 // Example of transformation:
16295 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16296 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16298 // (v8i1 (insert_subvector undef,
16299 // (v2i1 (and (PCMPEQM %a, %b),
16300 // (extract_subvector
16301 // (v8i1 (bitcast %mask)), 0))), 0))))
16302 EVT VT = Op.getOperand(1).getValueType();
16303 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16304 VT.getVectorNumElements());
16305 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16306 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16307 Mask.getValueType().getSizeInBits());
16309 if (IntrData->Type == CMP_MASK_CC) {
16310 SDValue CC = Op.getOperand(3);
16311 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16312 // We specify 2 possible opcodes for intrinsics with rounding modes.
16313 // First, we check if the intrinsic may have non-default rounding mode,
16314 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16315 if (IntrData->Opc1 != 0) {
16316 SDValue Rnd = Op.getOperand(5);
16317 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16318 X86::STATIC_ROUNDING::CUR_DIRECTION)
16319 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16320 Op.getOperand(2), CC, Rnd);
16322 //default rounding mode
16324 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16325 Op.getOperand(2), CC);
16328 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16329 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16332 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16333 DAG.getTargetConstant(0, dl,
16336 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16337 DAG.getUNDEF(BitcastVT), CmpMask,
16338 DAG.getIntPtrConstant(0, dl));
16339 return DAG.getBitcast(Op.getValueType(), Res);
16341 case CMP_MASK_SCALAR_CC: {
16342 SDValue Src1 = Op.getOperand(1);
16343 SDValue Src2 = Op.getOperand(2);
16344 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16345 SDValue Mask = Op.getOperand(4);
16348 if (IntrData->Opc1 != 0) {
16349 SDValue Rnd = Op.getOperand(5);
16350 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16351 X86::STATIC_ROUNDING::CUR_DIRECTION)
16352 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16354 //default rounding mode
16356 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16358 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16359 DAG.getTargetConstant(0, dl,
16363 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16364 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16365 DAG.getValueType(MVT::i1));
16367 case COMI: { // Comparison intrinsics
16368 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16369 SDValue LHS = Op.getOperand(1);
16370 SDValue RHS = Op.getOperand(2);
16371 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16372 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16373 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16374 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16375 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16376 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16379 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16380 Op.getOperand(1), Op.getOperand(2), DAG);
16382 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16383 Op.getSimpleValueType(),
16385 Op.getOperand(2), DAG),
16386 Op.getOperand(4), Op.getOperand(3), Subtarget,
16388 case COMPRESS_EXPAND_IN_REG: {
16389 SDValue Mask = Op.getOperand(3);
16390 SDValue DataToCompress = Op.getOperand(1);
16391 SDValue PassThru = Op.getOperand(2);
16392 if (isAllOnes(Mask)) // return data as is
16393 return Op.getOperand(1);
16395 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16397 Mask, PassThru, Subtarget, DAG);
16400 SDValue Mask = Op.getOperand(3);
16401 EVT VT = Op.getValueType();
16402 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16403 VT.getVectorNumElements());
16404 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16405 Mask.getValueType().getSizeInBits());
16407 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16408 DAG.getBitcast(BitcastVT, Mask),
16409 DAG.getIntPtrConstant(0, dl));
16410 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16419 default: return SDValue(); // Don't custom lower most intrinsics.
16421 case Intrinsic::x86_avx2_permd:
16422 case Intrinsic::x86_avx2_permps:
16423 // Operands intentionally swapped. Mask is last operand to intrinsic,
16424 // but second operand for node/instruction.
16425 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16426 Op.getOperand(2), Op.getOperand(1));
16428 // ptest and testp intrinsics. The intrinsic these come from are designed to
16429 // return an integer value, not just an instruction so lower it to the ptest
16430 // or testp pattern and a setcc for the result.
16431 case Intrinsic::x86_sse41_ptestz:
16432 case Intrinsic::x86_sse41_ptestc:
16433 case Intrinsic::x86_sse41_ptestnzc:
16434 case Intrinsic::x86_avx_ptestz_256:
16435 case Intrinsic::x86_avx_ptestc_256:
16436 case Intrinsic::x86_avx_ptestnzc_256:
16437 case Intrinsic::x86_avx_vtestz_ps:
16438 case Intrinsic::x86_avx_vtestc_ps:
16439 case Intrinsic::x86_avx_vtestnzc_ps:
16440 case Intrinsic::x86_avx_vtestz_pd:
16441 case Intrinsic::x86_avx_vtestc_pd:
16442 case Intrinsic::x86_avx_vtestnzc_pd:
16443 case Intrinsic::x86_avx_vtestz_ps_256:
16444 case Intrinsic::x86_avx_vtestc_ps_256:
16445 case Intrinsic::x86_avx_vtestnzc_ps_256:
16446 case Intrinsic::x86_avx_vtestz_pd_256:
16447 case Intrinsic::x86_avx_vtestc_pd_256:
16448 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16449 bool IsTestPacked = false;
16452 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16453 case Intrinsic::x86_avx_vtestz_ps:
16454 case Intrinsic::x86_avx_vtestz_pd:
16455 case Intrinsic::x86_avx_vtestz_ps_256:
16456 case Intrinsic::x86_avx_vtestz_pd_256:
16457 IsTestPacked = true; // Fallthrough
16458 case Intrinsic::x86_sse41_ptestz:
16459 case Intrinsic::x86_avx_ptestz_256:
16461 X86CC = X86::COND_E;
16463 case Intrinsic::x86_avx_vtestc_ps:
16464 case Intrinsic::x86_avx_vtestc_pd:
16465 case Intrinsic::x86_avx_vtestc_ps_256:
16466 case Intrinsic::x86_avx_vtestc_pd_256:
16467 IsTestPacked = true; // Fallthrough
16468 case Intrinsic::x86_sse41_ptestc:
16469 case Intrinsic::x86_avx_ptestc_256:
16471 X86CC = X86::COND_B;
16473 case Intrinsic::x86_avx_vtestnzc_ps:
16474 case Intrinsic::x86_avx_vtestnzc_pd:
16475 case Intrinsic::x86_avx_vtestnzc_ps_256:
16476 case Intrinsic::x86_avx_vtestnzc_pd_256:
16477 IsTestPacked = true; // Fallthrough
16478 case Intrinsic::x86_sse41_ptestnzc:
16479 case Intrinsic::x86_avx_ptestnzc_256:
16481 X86CC = X86::COND_A;
16485 SDValue LHS = Op.getOperand(1);
16486 SDValue RHS = Op.getOperand(2);
16487 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16488 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16489 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16490 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16491 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16493 case Intrinsic::x86_avx512_kortestz_w:
16494 case Intrinsic::x86_avx512_kortestc_w: {
16495 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16496 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16497 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16498 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16499 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16500 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16501 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16504 case Intrinsic::x86_sse42_pcmpistria128:
16505 case Intrinsic::x86_sse42_pcmpestria128:
16506 case Intrinsic::x86_sse42_pcmpistric128:
16507 case Intrinsic::x86_sse42_pcmpestric128:
16508 case Intrinsic::x86_sse42_pcmpistrio128:
16509 case Intrinsic::x86_sse42_pcmpestrio128:
16510 case Intrinsic::x86_sse42_pcmpistris128:
16511 case Intrinsic::x86_sse42_pcmpestris128:
16512 case Intrinsic::x86_sse42_pcmpistriz128:
16513 case Intrinsic::x86_sse42_pcmpestriz128: {
16517 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16518 case Intrinsic::x86_sse42_pcmpistria128:
16519 Opcode = X86ISD::PCMPISTRI;
16520 X86CC = X86::COND_A;
16522 case Intrinsic::x86_sse42_pcmpestria128:
16523 Opcode = X86ISD::PCMPESTRI;
16524 X86CC = X86::COND_A;
16526 case Intrinsic::x86_sse42_pcmpistric128:
16527 Opcode = X86ISD::PCMPISTRI;
16528 X86CC = X86::COND_B;
16530 case Intrinsic::x86_sse42_pcmpestric128:
16531 Opcode = X86ISD::PCMPESTRI;
16532 X86CC = X86::COND_B;
16534 case Intrinsic::x86_sse42_pcmpistrio128:
16535 Opcode = X86ISD::PCMPISTRI;
16536 X86CC = X86::COND_O;
16538 case Intrinsic::x86_sse42_pcmpestrio128:
16539 Opcode = X86ISD::PCMPESTRI;
16540 X86CC = X86::COND_O;
16542 case Intrinsic::x86_sse42_pcmpistris128:
16543 Opcode = X86ISD::PCMPISTRI;
16544 X86CC = X86::COND_S;
16546 case Intrinsic::x86_sse42_pcmpestris128:
16547 Opcode = X86ISD::PCMPESTRI;
16548 X86CC = X86::COND_S;
16550 case Intrinsic::x86_sse42_pcmpistriz128:
16551 Opcode = X86ISD::PCMPISTRI;
16552 X86CC = X86::COND_E;
16554 case Intrinsic::x86_sse42_pcmpestriz128:
16555 Opcode = X86ISD::PCMPESTRI;
16556 X86CC = X86::COND_E;
16559 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16560 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16561 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16562 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16563 DAG.getConstant(X86CC, dl, MVT::i8),
16564 SDValue(PCMP.getNode(), 1));
16565 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16568 case Intrinsic::x86_sse42_pcmpistri128:
16569 case Intrinsic::x86_sse42_pcmpestri128: {
16571 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16572 Opcode = X86ISD::PCMPISTRI;
16574 Opcode = X86ISD::PCMPESTRI;
16576 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16577 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16578 return DAG.getNode(Opcode, dl, VTs, NewOps);
16581 case Intrinsic::x86_seh_lsda: {
16582 // Compute the symbol for the LSDA. We know it'll get emitted later.
16583 MachineFunction &MF = DAG.getMachineFunction();
16584 SDValue Op1 = Op.getOperand(1);
16585 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16586 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16587 GlobalValue::getRealLinkageName(Fn->getName()));
16589 // Generate a simple absolute symbol reference. This intrinsic is only
16590 // supported on 32-bit Windows, which isn't PIC.
16591 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16592 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16595 case Intrinsic::x86_seh_recoverfp: {
16596 SDValue FnOp = Op.getOperand(1);
16597 SDValue IncomingFPOp = Op.getOperand(2);
16598 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16599 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16601 report_fatal_error(
16602 "llvm.x86.seh.recoverfp must take a function as the first argument");
16603 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16606 case Intrinsic::localaddress: {
16607 // Returns one of the stack, base, or frame pointer registers, depending on
16608 // which is used to reference local variables.
16609 MachineFunction &MF = DAG.getMachineFunction();
16610 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16612 if (RegInfo->hasBasePointer(MF))
16613 Reg = RegInfo->getBaseRegister();
16614 else // This function handles the SP or FP case.
16615 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16616 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16621 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16622 SDValue Src, SDValue Mask, SDValue Base,
16623 SDValue Index, SDValue ScaleOp, SDValue Chain,
16624 const X86Subtarget * Subtarget) {
16626 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16628 llvm_unreachable("Invalid scale type");
16629 unsigned ScaleVal = C->getZExtValue();
16630 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16631 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16633 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16634 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16635 Index.getSimpleValueType().getVectorNumElements());
16637 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16639 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16641 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16642 Mask.getValueType().getSizeInBits());
16644 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16645 // are extracted by EXTRACT_SUBVECTOR.
16646 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16647 DAG.getBitcast(BitcastVT, Mask),
16648 DAG.getIntPtrConstant(0, dl));
16650 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16651 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16652 SDValue Segment = DAG.getRegister(0, MVT::i32);
16653 if (Src.getOpcode() == ISD::UNDEF)
16654 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16655 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16656 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16657 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16658 return DAG.getMergeValues(RetOps, dl);
16661 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16662 SDValue Src, SDValue Mask, SDValue Base,
16663 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16665 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16667 llvm_unreachable("Invalid scale type");
16668 unsigned ScaleVal = C->getZExtValue();
16669 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16670 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16672 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16673 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16674 SDValue Segment = DAG.getRegister(0, MVT::i32);
16675 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16676 Index.getSimpleValueType().getVectorNumElements());
16678 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16680 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16682 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16683 Mask.getValueType().getSizeInBits());
16685 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16686 // are extracted by EXTRACT_SUBVECTOR.
16687 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16688 DAG.getBitcast(BitcastVT, Mask),
16689 DAG.getIntPtrConstant(0, dl));
16691 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16692 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16693 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16694 return SDValue(Res, 1);
16697 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16698 SDValue Mask, SDValue Base, SDValue Index,
16699 SDValue ScaleOp, SDValue Chain) {
16701 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16702 assert(C && "Invalid scale type");
16703 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16704 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16705 SDValue Segment = DAG.getRegister(0, MVT::i32);
16707 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16709 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16711 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16713 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16714 //SDVTList VTs = DAG.getVTList(MVT::Other);
16715 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16716 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16717 return SDValue(Res, 0);
16720 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16721 // read performance monitor counters (x86_rdpmc).
16722 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16723 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16724 SmallVectorImpl<SDValue> &Results) {
16725 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16726 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16729 // The ECX register is used to select the index of the performance counter
16731 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16733 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16735 // Reads the content of a 64-bit performance counter and returns it in the
16736 // registers EDX:EAX.
16737 if (Subtarget->is64Bit()) {
16738 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16739 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16742 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16743 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16746 Chain = HI.getValue(1);
16748 if (Subtarget->is64Bit()) {
16749 // The EAX register is loaded with the low-order 32 bits. The EDX register
16750 // is loaded with the supported high-order bits of the counter.
16751 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16752 DAG.getConstant(32, DL, MVT::i8));
16753 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16754 Results.push_back(Chain);
16758 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16759 SDValue Ops[] = { LO, HI };
16760 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16761 Results.push_back(Pair);
16762 Results.push_back(Chain);
16765 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16766 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16767 // also used to custom lower READCYCLECOUNTER nodes.
16768 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16769 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16770 SmallVectorImpl<SDValue> &Results) {
16771 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16772 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16775 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16776 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16777 // and the EAX register is loaded with the low-order 32 bits.
16778 if (Subtarget->is64Bit()) {
16779 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16780 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16783 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16784 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16787 SDValue Chain = HI.getValue(1);
16789 if (Opcode == X86ISD::RDTSCP_DAG) {
16790 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16792 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16793 // the ECX register. Add 'ecx' explicitly to the chain.
16794 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16796 // Explicitly store the content of ECX at the location passed in input
16797 // to the 'rdtscp' intrinsic.
16798 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16799 MachinePointerInfo(), false, false, 0);
16802 if (Subtarget->is64Bit()) {
16803 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16804 // the EAX register is loaded with the low-order 32 bits.
16805 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16806 DAG.getConstant(32, DL, MVT::i8));
16807 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16808 Results.push_back(Chain);
16812 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16813 SDValue Ops[] = { LO, HI };
16814 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16815 Results.push_back(Pair);
16816 Results.push_back(Chain);
16819 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16820 SelectionDAG &DAG) {
16821 SmallVector<SDValue, 2> Results;
16823 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16825 return DAG.getMergeValues(Results, DL);
16828 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16829 SelectionDAG &DAG) {
16830 MachineFunction &MF = DAG.getMachineFunction();
16831 const Function *Fn = MF.getFunction();
16833 SDValue Chain = Op.getOperand(0);
16835 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16836 "using llvm.x86.seh.restoreframe requires a frame pointer");
16838 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16839 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16841 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16842 unsigned FrameReg =
16843 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16844 unsigned SPReg = RegInfo->getStackRegister();
16845 unsigned SlotSize = RegInfo->getSlotSize();
16847 // Get incoming EBP.
16848 SDValue IncomingEBP =
16849 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16851 // SP is saved in the first field of every registration node, so load
16852 // [EBP-RegNodeSize] into SP.
16853 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16854 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16855 DAG.getConstant(-RegNodeSize, dl, VT));
16857 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16858 false, VT.getScalarSizeInBits() / 8);
16859 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16861 if (!RegInfo->needsStackRealignment(MF)) {
16862 // Adjust EBP to point back to the original frame position.
16863 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16864 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16866 assert(RegInfo->hasBasePointer(MF) &&
16867 "functions with Win32 EH must use frame or base pointer register");
16869 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16870 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16871 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16873 // Reload the spilled EBP value, now that the stack and base pointers are
16875 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16876 X86FI->setHasSEHFramePtrSave(true);
16877 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16878 X86FI->setSEHFramePtrSaveIndex(FI);
16879 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16880 MachinePointerInfo(), false, false, false,
16881 VT.getScalarSizeInBits() / 8);
16882 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16888 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16889 /// return truncate Store/MaskedStore Node
16890 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16894 SDValue Mask = Op.getOperand(4);
16895 SDValue DataToTruncate = Op.getOperand(3);
16896 SDValue Addr = Op.getOperand(2);
16897 SDValue Chain = Op.getOperand(0);
16899 EVT VT = DataToTruncate.getValueType();
16900 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16901 ElementType, VT.getVectorNumElements());
16903 if (isAllOnes(Mask)) // return just a truncate store
16904 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16905 MachinePointerInfo(), SVT, false, false,
16906 SVT.getScalarSizeInBits()/8);
16908 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16909 MVT::i1, VT.getVectorNumElements());
16910 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16911 Mask.getValueType().getSizeInBits());
16912 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16913 // are extracted by EXTRACT_SUBVECTOR.
16914 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16915 DAG.getBitcast(BitcastVT, Mask),
16916 DAG.getIntPtrConstant(0, dl));
16918 MachineMemOperand *MMO = DAG.getMachineFunction().
16919 getMachineMemOperand(MachinePointerInfo(),
16920 MachineMemOperand::MOStore, SVT.getStoreSize(),
16921 SVT.getScalarSizeInBits()/8);
16923 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16924 VMask, SVT, MMO, true);
16927 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16928 SelectionDAG &DAG) {
16929 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16931 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16933 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16934 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16939 switch(IntrData->Type) {
16941 llvm_unreachable("Unknown Intrinsic Type");
16945 // Emit the node with the right value type.
16946 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16947 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16949 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16950 // Otherwise return the value from Rand, which is always 0, casted to i32.
16951 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16952 DAG.getConstant(1, dl, Op->getValueType(1)),
16953 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16954 SDValue(Result.getNode(), 1) };
16955 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16956 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16959 // Return { result, isValid, chain }.
16960 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16961 SDValue(Result.getNode(), 2));
16964 //gather(v1, mask, index, base, scale);
16965 SDValue Chain = Op.getOperand(0);
16966 SDValue Src = Op.getOperand(2);
16967 SDValue Base = Op.getOperand(3);
16968 SDValue Index = Op.getOperand(4);
16969 SDValue Mask = Op.getOperand(5);
16970 SDValue Scale = Op.getOperand(6);
16971 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16975 //scatter(base, mask, index, v1, scale);
16976 SDValue Chain = Op.getOperand(0);
16977 SDValue Base = Op.getOperand(2);
16978 SDValue Mask = Op.getOperand(3);
16979 SDValue Index = Op.getOperand(4);
16980 SDValue Src = Op.getOperand(5);
16981 SDValue Scale = Op.getOperand(6);
16982 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16986 SDValue Hint = Op.getOperand(6);
16987 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16988 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16989 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16990 SDValue Chain = Op.getOperand(0);
16991 SDValue Mask = Op.getOperand(2);
16992 SDValue Index = Op.getOperand(3);
16993 SDValue Base = Op.getOperand(4);
16994 SDValue Scale = Op.getOperand(5);
16995 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16997 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16999 SmallVector<SDValue, 2> Results;
17000 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17002 return DAG.getMergeValues(Results, dl);
17004 // Read Performance Monitoring Counters.
17006 SmallVector<SDValue, 2> Results;
17007 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17008 return DAG.getMergeValues(Results, dl);
17010 // XTEST intrinsics.
17012 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17013 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17014 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17015 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17017 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17018 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17019 Ret, SDValue(InTrans.getNode(), 1));
17023 SmallVector<SDValue, 2> Results;
17024 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17025 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17026 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17027 DAG.getConstant(-1, dl, MVT::i8));
17028 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17029 Op.getOperand(4), GenCF.getValue(1));
17030 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17031 Op.getOperand(5), MachinePointerInfo(),
17033 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17034 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17036 Results.push_back(SetCC);
17037 Results.push_back(Store);
17038 return DAG.getMergeValues(Results, dl);
17040 case COMPRESS_TO_MEM: {
17042 SDValue Mask = Op.getOperand(4);
17043 SDValue DataToCompress = Op.getOperand(3);
17044 SDValue Addr = Op.getOperand(2);
17045 SDValue Chain = Op.getOperand(0);
17047 EVT VT = DataToCompress.getValueType();
17048 if (isAllOnes(Mask)) // return just a store
17049 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17050 MachinePointerInfo(), false, false,
17051 VT.getScalarSizeInBits()/8);
17053 SDValue Compressed =
17054 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17055 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17056 return DAG.getStore(Chain, dl, Compressed, Addr,
17057 MachinePointerInfo(), false, false,
17058 VT.getScalarSizeInBits()/8);
17060 case TRUNCATE_TO_MEM_VI8:
17061 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17062 case TRUNCATE_TO_MEM_VI16:
17063 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17064 case TRUNCATE_TO_MEM_VI32:
17065 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17066 case EXPAND_FROM_MEM: {
17068 SDValue Mask = Op.getOperand(4);
17069 SDValue PassThru = Op.getOperand(3);
17070 SDValue Addr = Op.getOperand(2);
17071 SDValue Chain = Op.getOperand(0);
17072 EVT VT = Op.getValueType();
17074 if (isAllOnes(Mask)) // return just a load
17075 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17076 false, VT.getScalarSizeInBits()/8);
17078 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17079 false, false, false,
17080 VT.getScalarSizeInBits()/8);
17082 SDValue Results[] = {
17083 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17084 Mask, PassThru, Subtarget, DAG), Chain};
17085 return DAG.getMergeValues(Results, dl);
17090 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17091 SelectionDAG &DAG) const {
17092 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17093 MFI->setReturnAddressIsTaken(true);
17095 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17098 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17100 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17103 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17104 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17105 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17106 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17107 DAG.getNode(ISD::ADD, dl, PtrVT,
17108 FrameAddr, Offset),
17109 MachinePointerInfo(), false, false, false, 0);
17112 // Just load the return address.
17113 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17114 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17115 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17118 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17119 MachineFunction &MF = DAG.getMachineFunction();
17120 MachineFrameInfo *MFI = MF.getFrameInfo();
17121 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17122 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17123 EVT VT = Op.getValueType();
17125 MFI->setFrameAddressIsTaken(true);
17127 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17128 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17129 // is not possible to crawl up the stack without looking at the unwind codes
17131 int FrameAddrIndex = FuncInfo->getFAIndex();
17132 if (!FrameAddrIndex) {
17133 // Set up a frame object for the return address.
17134 unsigned SlotSize = RegInfo->getSlotSize();
17135 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17136 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17137 FuncInfo->setFAIndex(FrameAddrIndex);
17139 return DAG.getFrameIndex(FrameAddrIndex, VT);
17142 unsigned FrameReg =
17143 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17144 SDLoc dl(Op); // FIXME probably not meaningful
17145 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17146 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17147 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17148 "Invalid Frame Register!");
17149 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17151 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17152 MachinePointerInfo(),
17153 false, false, false, 0);
17157 // FIXME? Maybe this could be a TableGen attribute on some registers and
17158 // this table could be generated automatically from RegInfo.
17159 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17160 SelectionDAG &DAG) const {
17161 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17162 const MachineFunction &MF = DAG.getMachineFunction();
17164 unsigned Reg = StringSwitch<unsigned>(RegName)
17165 .Case("esp", X86::ESP)
17166 .Case("rsp", X86::RSP)
17167 .Case("ebp", X86::EBP)
17168 .Case("rbp", X86::RBP)
17171 if (Reg == X86::EBP || Reg == X86::RBP) {
17172 if (!TFI.hasFP(MF))
17173 report_fatal_error("register " + StringRef(RegName) +
17174 " is allocatable: function has no frame pointer");
17177 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17178 unsigned FrameReg =
17179 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17180 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17181 "Invalid Frame Register!");
17189 report_fatal_error("Invalid register name global variable");
17192 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17193 SelectionDAG &DAG) const {
17194 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17195 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17198 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17199 SDValue Chain = Op.getOperand(0);
17200 SDValue Offset = Op.getOperand(1);
17201 SDValue Handler = Op.getOperand(2);
17204 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17205 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17206 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17207 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17208 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17209 "Invalid Frame Register!");
17210 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17211 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17213 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17214 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17216 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17217 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17219 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17221 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17222 DAG.getRegister(StoreAddrReg, PtrVT));
17225 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17226 SelectionDAG &DAG) const {
17228 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17229 DAG.getVTList(MVT::i32, MVT::Other),
17230 Op.getOperand(0), Op.getOperand(1));
17233 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17234 SelectionDAG &DAG) const {
17236 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17237 Op.getOperand(0), Op.getOperand(1));
17240 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17241 return Op.getOperand(0);
17244 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17245 SelectionDAG &DAG) const {
17246 SDValue Root = Op.getOperand(0);
17247 SDValue Trmp = Op.getOperand(1); // trampoline
17248 SDValue FPtr = Op.getOperand(2); // nested function
17249 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17252 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17253 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17255 if (Subtarget->is64Bit()) {
17256 SDValue OutChains[6];
17258 // Large code-model.
17259 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17260 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17262 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17263 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17265 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17267 // Load the pointer to the nested function into R11.
17268 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17269 SDValue Addr = Trmp;
17270 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17271 Addr, MachinePointerInfo(TrmpAddr),
17274 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17275 DAG.getConstant(2, dl, MVT::i64));
17276 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17277 MachinePointerInfo(TrmpAddr, 2),
17280 // Load the 'nest' parameter value into R10.
17281 // R10 is specified in X86CallingConv.td
17282 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17283 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17284 DAG.getConstant(10, dl, MVT::i64));
17285 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17286 Addr, MachinePointerInfo(TrmpAddr, 10),
17289 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17290 DAG.getConstant(12, dl, MVT::i64));
17291 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17292 MachinePointerInfo(TrmpAddr, 12),
17295 // Jump to the nested function.
17296 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17297 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17298 DAG.getConstant(20, dl, MVT::i64));
17299 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17300 Addr, MachinePointerInfo(TrmpAddr, 20),
17303 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17304 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17305 DAG.getConstant(22, dl, MVT::i64));
17306 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17307 Addr, MachinePointerInfo(TrmpAddr, 22),
17310 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17312 const Function *Func =
17313 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17314 CallingConv::ID CC = Func->getCallingConv();
17319 llvm_unreachable("Unsupported calling convention");
17320 case CallingConv::C:
17321 case CallingConv::X86_StdCall: {
17322 // Pass 'nest' parameter in ECX.
17323 // Must be kept in sync with X86CallingConv.td
17324 NestReg = X86::ECX;
17326 // Check that ECX wasn't needed by an 'inreg' parameter.
17327 FunctionType *FTy = Func->getFunctionType();
17328 const AttributeSet &Attrs = Func->getAttributes();
17330 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17331 unsigned InRegCount = 0;
17334 for (FunctionType::param_iterator I = FTy->param_begin(),
17335 E = FTy->param_end(); I != E; ++I, ++Idx)
17336 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17337 auto &DL = DAG.getDataLayout();
17338 // FIXME: should only count parameters that are lowered to integers.
17339 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17342 if (InRegCount > 2) {
17343 report_fatal_error("Nest register in use - reduce number of inreg"
17349 case CallingConv::X86_FastCall:
17350 case CallingConv::X86_ThisCall:
17351 case CallingConv::Fast:
17352 // Pass 'nest' parameter in EAX.
17353 // Must be kept in sync with X86CallingConv.td
17354 NestReg = X86::EAX;
17358 SDValue OutChains[4];
17359 SDValue Addr, Disp;
17361 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17362 DAG.getConstant(10, dl, MVT::i32));
17363 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17365 // This is storing the opcode for MOV32ri.
17366 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17367 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17368 OutChains[0] = DAG.getStore(Root, dl,
17369 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17370 Trmp, MachinePointerInfo(TrmpAddr),
17373 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17374 DAG.getConstant(1, dl, MVT::i32));
17375 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17376 MachinePointerInfo(TrmpAddr, 1),
17379 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17380 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17381 DAG.getConstant(5, dl, MVT::i32));
17382 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17383 Addr, MachinePointerInfo(TrmpAddr, 5),
17386 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17387 DAG.getConstant(6, dl, MVT::i32));
17388 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17389 MachinePointerInfo(TrmpAddr, 6),
17392 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17396 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17397 SelectionDAG &DAG) const {
17399 The rounding mode is in bits 11:10 of FPSR, and has the following
17401 00 Round to nearest
17406 FLT_ROUNDS, on the other hand, expects the following:
17413 To perform the conversion, we do:
17414 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17417 MachineFunction &MF = DAG.getMachineFunction();
17418 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17419 unsigned StackAlignment = TFI.getStackAlignment();
17420 MVT VT = Op.getSimpleValueType();
17423 // Save FP Control Word to stack slot
17424 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17425 SDValue StackSlot =
17426 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17428 MachineMemOperand *MMO =
17429 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17430 MachineMemOperand::MOStore, 2, 2);
17432 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17433 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17434 DAG.getVTList(MVT::Other),
17435 Ops, MVT::i16, MMO);
17437 // Load FP Control Word from stack slot
17438 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17439 MachinePointerInfo(), false, false, false, 0);
17441 // Transform as necessary
17443 DAG.getNode(ISD::SRL, DL, MVT::i16,
17444 DAG.getNode(ISD::AND, DL, MVT::i16,
17445 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17446 DAG.getConstant(11, DL, MVT::i8));
17448 DAG.getNode(ISD::SRL, DL, MVT::i16,
17449 DAG.getNode(ISD::AND, DL, MVT::i16,
17450 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17451 DAG.getConstant(9, DL, MVT::i8));
17454 DAG.getNode(ISD::AND, DL, MVT::i16,
17455 DAG.getNode(ISD::ADD, DL, MVT::i16,
17456 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17457 DAG.getConstant(1, DL, MVT::i16)),
17458 DAG.getConstant(3, DL, MVT::i16));
17460 return DAG.getNode((VT.getSizeInBits() < 16 ?
17461 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17464 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17465 MVT VT = Op.getSimpleValueType();
17467 unsigned NumBits = VT.getSizeInBits();
17470 Op = Op.getOperand(0);
17471 if (VT == MVT::i8) {
17472 // Zero extend to i32 since there is not an i8 bsr.
17474 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17477 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17478 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17479 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17481 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17484 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17485 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17488 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17490 // Finally xor with NumBits-1.
17491 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17492 DAG.getConstant(NumBits - 1, dl, OpVT));
17495 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17499 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17500 MVT VT = Op.getSimpleValueType();
17502 unsigned NumBits = VT.getSizeInBits();
17505 Op = Op.getOperand(0);
17506 if (VT == MVT::i8) {
17507 // Zero extend to i32 since there is not an i8 bsr.
17509 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17512 // Issue a bsr (scan bits in reverse).
17513 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17514 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17516 // And xor with NumBits-1.
17517 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17518 DAG.getConstant(NumBits - 1, dl, OpVT));
17521 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17525 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17526 MVT VT = Op.getSimpleValueType();
17527 unsigned NumBits = VT.getScalarSizeInBits();
17530 if (VT.isVector()) {
17531 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17533 SDValue N0 = Op.getOperand(0);
17534 SDValue Zero = DAG.getConstant(0, dl, VT);
17536 // lsb(x) = (x & -x)
17537 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17538 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17540 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17541 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17542 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17543 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17544 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17545 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17548 // cttz(x) = ctpop(lsb - 1)
17549 SDValue One = DAG.getConstant(1, dl, VT);
17550 return DAG.getNode(ISD::CTPOP, dl, VT,
17551 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17554 assert(Op.getOpcode() == ISD::CTTZ &&
17555 "Only scalar CTTZ requires custom lowering");
17557 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17558 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17559 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17561 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17564 DAG.getConstant(NumBits, dl, VT),
17565 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17568 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17571 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17572 // ones, and then concatenate the result back.
17573 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17574 MVT VT = Op.getSimpleValueType();
17576 assert(VT.is256BitVector() && VT.isInteger() &&
17577 "Unsupported value type for operation");
17579 unsigned NumElems = VT.getVectorNumElements();
17582 // Extract the LHS vectors
17583 SDValue LHS = Op.getOperand(0);
17584 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17585 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17587 // Extract the RHS vectors
17588 SDValue RHS = Op.getOperand(1);
17589 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17590 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17592 MVT EltVT = VT.getVectorElementType();
17593 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17595 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17596 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17597 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17600 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17601 if (Op.getValueType() == MVT::i1)
17602 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17603 Op.getOperand(0), Op.getOperand(1));
17604 assert(Op.getSimpleValueType().is256BitVector() &&
17605 Op.getSimpleValueType().isInteger() &&
17606 "Only handle AVX 256-bit vector integer operation");
17607 return Lower256IntArith(Op, DAG);
17610 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17611 if (Op.getValueType() == MVT::i1)
17612 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17613 Op.getOperand(0), Op.getOperand(1));
17614 assert(Op.getSimpleValueType().is256BitVector() &&
17615 Op.getSimpleValueType().isInteger() &&
17616 "Only handle AVX 256-bit vector integer operation");
17617 return Lower256IntArith(Op, DAG);
17620 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17621 assert(Op.getSimpleValueType().is256BitVector() &&
17622 Op.getSimpleValueType().isInteger() &&
17623 "Only handle AVX 256-bit vector integer operation");
17624 return Lower256IntArith(Op, DAG);
17627 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17628 SelectionDAG &DAG) {
17630 MVT VT = Op.getSimpleValueType();
17633 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17635 // Decompose 256-bit ops into smaller 128-bit ops.
17636 if (VT.is256BitVector() && !Subtarget->hasInt256())
17637 return Lower256IntArith(Op, DAG);
17639 SDValue A = Op.getOperand(0);
17640 SDValue B = Op.getOperand(1);
17642 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17643 // pairs, multiply and truncate.
17644 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17645 if (Subtarget->hasInt256()) {
17646 if (VT == MVT::v32i8) {
17647 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17648 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17649 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17650 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17651 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17652 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17653 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17654 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17655 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17656 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17659 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17660 return DAG.getNode(
17661 ISD::TRUNCATE, dl, VT,
17662 DAG.getNode(ISD::MUL, dl, ExVT,
17663 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17664 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17667 assert(VT == MVT::v16i8 &&
17668 "Pre-AVX2 support only supports v16i8 multiplication");
17669 MVT ExVT = MVT::v8i16;
17671 // Extract the lo parts and sign extend to i16
17673 if (Subtarget->hasSSE41()) {
17674 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17675 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17677 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17678 -1, 4, -1, 5, -1, 6, -1, 7};
17679 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17680 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17681 ALo = DAG.getBitcast(ExVT, ALo);
17682 BLo = DAG.getBitcast(ExVT, BLo);
17683 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17684 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17687 // Extract the hi parts and sign extend to i16
17689 if (Subtarget->hasSSE41()) {
17690 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17691 -1, -1, -1, -1, -1, -1, -1, -1};
17692 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17693 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17694 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17695 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17697 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17698 -1, 12, -1, 13, -1, 14, -1, 15};
17699 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17700 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17701 AHi = DAG.getBitcast(ExVT, AHi);
17702 BHi = DAG.getBitcast(ExVT, BHi);
17703 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17704 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17707 // Multiply, mask the lower 8bits of the lo/hi results and pack
17708 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17709 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17710 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17711 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17712 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17715 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17716 if (VT == MVT::v4i32) {
17717 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17718 "Should not custom lower when pmuldq is available!");
17720 // Extract the odd parts.
17721 static const int UnpackMask[] = { 1, -1, 3, -1 };
17722 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17723 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17725 // Multiply the even parts.
17726 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17727 // Now multiply odd parts.
17728 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17730 Evens = DAG.getBitcast(VT, Evens);
17731 Odds = DAG.getBitcast(VT, Odds);
17733 // Merge the two vectors back together with a shuffle. This expands into 2
17735 static const int ShufMask[] = { 0, 4, 2, 6 };
17736 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17739 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17740 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17742 // Ahi = psrlqi(a, 32);
17743 // Bhi = psrlqi(b, 32);
17745 // AloBlo = pmuludq(a, b);
17746 // AloBhi = pmuludq(a, Bhi);
17747 // AhiBlo = pmuludq(Ahi, b);
17749 // AloBhi = psllqi(AloBhi, 32);
17750 // AhiBlo = psllqi(AhiBlo, 32);
17751 // return AloBlo + AloBhi + AhiBlo;
17753 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17754 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17756 SDValue AhiBlo = Ahi;
17757 SDValue AloBhi = Bhi;
17758 // Bit cast to 32-bit vectors for MULUDQ
17759 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17760 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17761 A = DAG.getBitcast(MulVT, A);
17762 B = DAG.getBitcast(MulVT, B);
17763 Ahi = DAG.getBitcast(MulVT, Ahi);
17764 Bhi = DAG.getBitcast(MulVT, Bhi);
17766 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17767 // After shifting right const values the result may be all-zero.
17768 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17769 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17770 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17772 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17773 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17774 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17777 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17778 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17781 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17782 assert(Subtarget->isTargetWin64() && "Unexpected target");
17783 EVT VT = Op.getValueType();
17784 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17785 "Unexpected return type for lowering");
17789 switch (Op->getOpcode()) {
17790 default: llvm_unreachable("Unexpected request for libcall!");
17791 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17792 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17793 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17794 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17795 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17796 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17800 SDValue InChain = DAG.getEntryNode();
17802 TargetLowering::ArgListTy Args;
17803 TargetLowering::ArgListEntry Entry;
17804 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17805 EVT ArgVT = Op->getOperand(i).getValueType();
17806 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17807 "Unexpected argument type for lowering");
17808 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17809 Entry.Node = StackPtr;
17810 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17812 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17813 Entry.Ty = PointerType::get(ArgTy,0);
17814 Entry.isSExt = false;
17815 Entry.isZExt = false;
17816 Args.push_back(Entry);
17819 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17820 getPointerTy(DAG.getDataLayout()));
17822 TargetLowering::CallLoweringInfo CLI(DAG);
17823 CLI.setDebugLoc(dl).setChain(InChain)
17824 .setCallee(getLibcallCallingConv(LC),
17825 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17826 Callee, std::move(Args), 0)
17827 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17829 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17830 return DAG.getBitcast(VT, CallInfo.first);
17833 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17834 SelectionDAG &DAG) {
17835 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17836 EVT VT = Op0.getValueType();
17839 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17840 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17842 // PMULxD operations multiply each even value (starting at 0) of LHS with
17843 // the related value of RHS and produce a widen result.
17844 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17845 // => <2 x i64> <ae|cg>
17847 // In other word, to have all the results, we need to perform two PMULxD:
17848 // 1. one with the even values.
17849 // 2. one with the odd values.
17850 // To achieve #2, with need to place the odd values at an even position.
17852 // Place the odd value at an even position (basically, shift all values 1
17853 // step to the left):
17854 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17855 // <a|b|c|d> => <b|undef|d|undef>
17856 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17857 // <e|f|g|h> => <f|undef|h|undef>
17858 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17860 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17862 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17863 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17865 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17866 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17867 // => <2 x i64> <ae|cg>
17868 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17869 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17870 // => <2 x i64> <bf|dh>
17871 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17873 // Shuffle it back into the right order.
17874 SDValue Highs, Lows;
17875 if (VT == MVT::v8i32) {
17876 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17877 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17878 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17879 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17881 const int HighMask[] = {1, 5, 3, 7};
17882 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17883 const int LowMask[] = {0, 4, 2, 6};
17884 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17887 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17888 // unsigned multiply.
17889 if (IsSigned && !Subtarget->hasSSE41()) {
17890 SDValue ShAmt = DAG.getConstant(
17892 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17893 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17894 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17895 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17896 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17898 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17899 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17902 // The first result of MUL_LOHI is actually the low value, followed by the
17904 SDValue Ops[] = {Lows, Highs};
17905 return DAG.getMergeValues(Ops, dl);
17908 // Return true if the required (according to Opcode) shift-imm form is natively
17909 // supported by the Subtarget
17910 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17912 if (VT.getScalarSizeInBits() < 16)
17915 if (VT.is512BitVector() &&
17916 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17919 bool LShift = VT.is128BitVector() ||
17920 (VT.is256BitVector() && Subtarget->hasInt256());
17922 bool AShift = LShift && (Subtarget->hasVLX() ||
17923 (VT != MVT::v2i64 && VT != MVT::v4i64));
17924 return (Opcode == ISD::SRA) ? AShift : LShift;
17927 // The shift amount is a variable, but it is the same for all vector lanes.
17928 // These instructions are defined together with shift-immediate.
17930 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
17932 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
17935 // Return true if the required (according to Opcode) variable-shift form is
17936 // natively supported by the Subtarget
17937 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
17940 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
17943 // vXi16 supported only on AVX-512, BWI
17944 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
17947 if (VT.is512BitVector() || Subtarget->hasVLX())
17950 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17951 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17952 return (Opcode == ISD::SRA) ? AShift : LShift;
17955 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17956 const X86Subtarget *Subtarget) {
17957 MVT VT = Op.getSimpleValueType();
17959 SDValue R = Op.getOperand(0);
17960 SDValue Amt = Op.getOperand(1);
17962 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17963 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17965 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17966 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17967 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17968 SDValue Ex = DAG.getBitcast(ExVT, R);
17970 if (ShiftAmt >= 32) {
17971 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17973 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17974 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17975 ShiftAmt - 32, DAG);
17976 if (VT == MVT::v2i64)
17977 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17978 if (VT == MVT::v4i64)
17979 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17980 {9, 1, 11, 3, 13, 5, 15, 7});
17982 // SRA upper i32, SHL whole i64 and select lower i32.
17983 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17986 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17987 Lower = DAG.getBitcast(ExVT, Lower);
17988 if (VT == MVT::v2i64)
17989 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17990 if (VT == MVT::v4i64)
17991 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17992 {8, 1, 10, 3, 12, 5, 14, 7});
17994 return DAG.getBitcast(VT, Ex);
17997 // Optimize shl/srl/sra with constant shift amount.
17998 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17999 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18000 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18002 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18003 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18005 // i64 SRA needs to be performed as partial shifts.
18006 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18007 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18008 return ArithmeticShiftRight64(ShiftAmt);
18010 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18011 unsigned NumElts = VT.getVectorNumElements();
18012 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18014 // Simple i8 add case
18015 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18016 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18018 // ashr(R, 7) === cmp_slt(R, 0)
18019 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18020 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18021 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18024 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18025 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18028 if (Op.getOpcode() == ISD::SHL) {
18029 // Make a large shift.
18030 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18032 SHL = DAG.getBitcast(VT, SHL);
18033 // Zero out the rightmost bits.
18034 SmallVector<SDValue, 32> V(
18035 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18036 return DAG.getNode(ISD::AND, dl, VT, SHL,
18037 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18039 if (Op.getOpcode() == ISD::SRL) {
18040 // Make a large shift.
18041 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18043 SRL = DAG.getBitcast(VT, SRL);
18044 // Zero out the leftmost bits.
18045 SmallVector<SDValue, 32> V(
18046 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18047 return DAG.getNode(ISD::AND, dl, VT, SRL,
18048 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18050 if (Op.getOpcode() == ISD::SRA) {
18051 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18052 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18053 SmallVector<SDValue, 32> V(NumElts,
18054 DAG.getConstant(128 >> ShiftAmt, dl,
18056 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18057 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18058 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18061 llvm_unreachable("Unknown shift opcode.");
18066 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18067 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18068 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18070 // Peek through any splat that was introduced for i64 shift vectorization.
18071 int SplatIndex = -1;
18072 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18073 if (SVN->isSplat()) {
18074 SplatIndex = SVN->getSplatIndex();
18075 Amt = Amt.getOperand(0);
18076 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18077 "Splat shuffle referencing second operand");
18080 if (Amt.getOpcode() != ISD::BITCAST ||
18081 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18084 Amt = Amt.getOperand(0);
18085 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18086 VT.getVectorNumElements();
18087 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18088 uint64_t ShiftAmt = 0;
18089 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18090 for (unsigned i = 0; i != Ratio; ++i) {
18091 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18095 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18098 // Check remaining shift amounts (if not a splat).
18099 if (SplatIndex < 0) {
18100 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18101 uint64_t ShAmt = 0;
18102 for (unsigned j = 0; j != Ratio; ++j) {
18103 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18107 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18109 if (ShAmt != ShiftAmt)
18114 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18115 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18117 if (Op.getOpcode() == ISD::SRA)
18118 return ArithmeticShiftRight64(ShiftAmt);
18124 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18125 const X86Subtarget* Subtarget) {
18126 MVT VT = Op.getSimpleValueType();
18128 SDValue R = Op.getOperand(0);
18129 SDValue Amt = Op.getOperand(1);
18131 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18132 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18134 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18135 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18137 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18139 EVT EltVT = VT.getVectorElementType();
18141 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18142 // Check if this build_vector node is doing a splat.
18143 // If so, then set BaseShAmt equal to the splat value.
18144 BaseShAmt = BV->getSplatValue();
18145 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18146 BaseShAmt = SDValue();
18148 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18149 Amt = Amt.getOperand(0);
18151 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18152 if (SVN && SVN->isSplat()) {
18153 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18154 SDValue InVec = Amt.getOperand(0);
18155 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18156 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18157 "Unexpected shuffle index found!");
18158 BaseShAmt = InVec.getOperand(SplatIdx);
18159 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18160 if (ConstantSDNode *C =
18161 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18162 if (C->getZExtValue() == SplatIdx)
18163 BaseShAmt = InVec.getOperand(1);
18168 // Avoid introducing an extract element from a shuffle.
18169 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18170 DAG.getIntPtrConstant(SplatIdx, dl));
18174 if (BaseShAmt.getNode()) {
18175 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18176 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18177 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18178 else if (EltVT.bitsLT(MVT::i32))
18179 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18181 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18185 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18186 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18187 Amt.getOpcode() == ISD::BITCAST &&
18188 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18189 Amt = Amt.getOperand(0);
18190 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18191 VT.getVectorNumElements();
18192 std::vector<SDValue> Vals(Ratio);
18193 for (unsigned i = 0; i != Ratio; ++i)
18194 Vals[i] = Amt.getOperand(i);
18195 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18196 for (unsigned j = 0; j != Ratio; ++j)
18197 if (Vals[j] != Amt.getOperand(i + j))
18201 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18202 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18207 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18208 SelectionDAG &DAG) {
18209 MVT VT = Op.getSimpleValueType();
18211 SDValue R = Op.getOperand(0);
18212 SDValue Amt = Op.getOperand(1);
18214 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18215 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18217 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18220 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18223 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18226 // XOP has 128-bit variable logical/arithmetic shifts.
18227 // +ve/-ve Amt = shift left/right.
18228 if (Subtarget->hasXOP() &&
18229 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18230 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18231 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18232 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18233 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18235 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18236 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18237 if (Op.getOpcode() == ISD::SRA)
18238 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18241 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18242 // shifts per-lane and then shuffle the partial results back together.
18243 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18244 // Splat the shift amounts so the scalar shifts above will catch it.
18245 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18246 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18247 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18248 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18249 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18252 // i64 vector arithmetic shift can be emulated with the transform:
18253 // M = lshr(SIGN_BIT, Amt)
18254 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18255 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18256 Op.getOpcode() == ISD::SRA) {
18257 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18258 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18259 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18260 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18261 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18265 // If possible, lower this packed shift into a vector multiply instead of
18266 // expanding it into a sequence of scalar shifts.
18267 // Do this only if the vector shift count is a constant build_vector.
18268 if (Op.getOpcode() == ISD::SHL &&
18269 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18270 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18271 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18272 SmallVector<SDValue, 8> Elts;
18273 EVT SVT = VT.getScalarType();
18274 unsigned SVTBits = SVT.getSizeInBits();
18275 const APInt &One = APInt(SVTBits, 1);
18276 unsigned NumElems = VT.getVectorNumElements();
18278 for (unsigned i=0; i !=NumElems; ++i) {
18279 SDValue Op = Amt->getOperand(i);
18280 if (Op->getOpcode() == ISD::UNDEF) {
18281 Elts.push_back(Op);
18285 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18286 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18287 uint64_t ShAmt = C.getZExtValue();
18288 if (ShAmt >= SVTBits) {
18289 Elts.push_back(DAG.getUNDEF(SVT));
18292 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18294 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18295 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18298 // Lower SHL with variable shift amount.
18299 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18300 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18302 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18303 DAG.getConstant(0x3f800000U, dl, VT));
18304 Op = DAG.getBitcast(MVT::v4f32, Op);
18305 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18306 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18309 // If possible, lower this shift as a sequence of two shifts by
18310 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18312 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18314 // Could be rewritten as:
18315 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18317 // The advantage is that the two shifts from the example would be
18318 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18319 // the vector shift into four scalar shifts plus four pairs of vector
18321 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18322 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18323 unsigned TargetOpcode = X86ISD::MOVSS;
18324 bool CanBeSimplified;
18325 // The splat value for the first packed shift (the 'X' from the example).
18326 SDValue Amt1 = Amt->getOperand(0);
18327 // The splat value for the second packed shift (the 'Y' from the example).
18328 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18329 Amt->getOperand(2);
18331 // See if it is possible to replace this node with a sequence of
18332 // two shifts followed by a MOVSS/MOVSD
18333 if (VT == MVT::v4i32) {
18334 // Check if it is legal to use a MOVSS.
18335 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18336 Amt2 == Amt->getOperand(3);
18337 if (!CanBeSimplified) {
18338 // Otherwise, check if we can still simplify this node using a MOVSD.
18339 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18340 Amt->getOperand(2) == Amt->getOperand(3);
18341 TargetOpcode = X86ISD::MOVSD;
18342 Amt2 = Amt->getOperand(2);
18345 // Do similar checks for the case where the machine value type
18347 CanBeSimplified = Amt1 == Amt->getOperand(1);
18348 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18349 CanBeSimplified = Amt2 == Amt->getOperand(i);
18351 if (!CanBeSimplified) {
18352 TargetOpcode = X86ISD::MOVSD;
18353 CanBeSimplified = true;
18354 Amt2 = Amt->getOperand(4);
18355 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18356 CanBeSimplified = Amt1 == Amt->getOperand(i);
18357 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18358 CanBeSimplified = Amt2 == Amt->getOperand(j);
18362 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18363 isa<ConstantSDNode>(Amt2)) {
18364 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18365 EVT CastVT = MVT::v4i32;
18367 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18368 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18370 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18371 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18372 if (TargetOpcode == X86ISD::MOVSD)
18373 CastVT = MVT::v2i64;
18374 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18375 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18376 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18378 return DAG.getBitcast(VT, Result);
18382 // v4i32 Non Uniform Shifts.
18383 // If the shift amount is constant we can shift each lane using the SSE2
18384 // immediate shifts, else we need to zero-extend each lane to the lower i64
18385 // and shift using the SSE2 variable shifts.
18386 // The separate results can then be blended together.
18387 if (VT == MVT::v4i32) {
18388 unsigned Opc = Op.getOpcode();
18389 SDValue Amt0, Amt1, Amt2, Amt3;
18390 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18391 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18392 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18393 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18394 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18396 // ISD::SHL is handled above but we include it here for completeness.
18399 llvm_unreachable("Unknown target vector shift node");
18401 Opc = X86ISD::VSHL;
18404 Opc = X86ISD::VSRL;
18407 Opc = X86ISD::VSRA;
18410 // The SSE2 shifts use the lower i64 as the same shift amount for
18411 // all lanes and the upper i64 is ignored. These shuffle masks
18412 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18413 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18414 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18415 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18416 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18417 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18420 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18421 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18422 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18423 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18424 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18425 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18426 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18429 if (VT == MVT::v16i8 ||
18430 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18431 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18432 unsigned ShiftOpcode = Op->getOpcode();
18434 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18435 // On SSE41 targets we make use of the fact that VSELECT lowers
18436 // to PBLENDVB which selects bytes based just on the sign bit.
18437 if (Subtarget->hasSSE41()) {
18438 V0 = DAG.getBitcast(VT, V0);
18439 V1 = DAG.getBitcast(VT, V1);
18440 Sel = DAG.getBitcast(VT, Sel);
18441 return DAG.getBitcast(SelVT,
18442 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18444 // On pre-SSE41 targets we test for the sign bit by comparing to
18445 // zero - a negative value will set all bits of the lanes to true
18446 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18447 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18448 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18449 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18452 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18453 // We can safely do this using i16 shifts as we're only interested in
18454 // the 3 lower bits of each byte.
18455 Amt = DAG.getBitcast(ExtVT, Amt);
18456 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18457 Amt = DAG.getBitcast(VT, Amt);
18459 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18460 // r = VSELECT(r, shift(r, 4), a);
18462 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18463 R = SignBitSelect(VT, Amt, M, R);
18466 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18468 // r = VSELECT(r, shift(r, 2), a);
18469 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18470 R = SignBitSelect(VT, Amt, M, R);
18473 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18475 // return VSELECT(r, shift(r, 1), a);
18476 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18477 R = SignBitSelect(VT, Amt, M, R);
18481 if (Op->getOpcode() == ISD::SRA) {
18482 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18483 // so we can correctly sign extend. We don't care what happens to the
18485 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18486 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18487 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18488 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18489 ALo = DAG.getBitcast(ExtVT, ALo);
18490 AHi = DAG.getBitcast(ExtVT, AHi);
18491 RLo = DAG.getBitcast(ExtVT, RLo);
18492 RHi = DAG.getBitcast(ExtVT, RHi);
18494 // r = VSELECT(r, shift(r, 4), a);
18495 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18496 DAG.getConstant(4, dl, ExtVT));
18497 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18498 DAG.getConstant(4, dl, ExtVT));
18499 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18500 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18503 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18504 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18506 // r = VSELECT(r, shift(r, 2), a);
18507 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18508 DAG.getConstant(2, dl, ExtVT));
18509 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18510 DAG.getConstant(2, dl, ExtVT));
18511 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18512 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18515 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18516 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18518 // r = VSELECT(r, shift(r, 1), a);
18519 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18520 DAG.getConstant(1, dl, ExtVT));
18521 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18522 DAG.getConstant(1, dl, ExtVT));
18523 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18524 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18526 // Logical shift the result back to the lower byte, leaving a zero upper
18528 // meaning that we can safely pack with PACKUSWB.
18530 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18532 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18533 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18537 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18538 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18539 // solution better.
18540 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18541 MVT ExtVT = MVT::v8i32;
18543 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18544 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18545 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18546 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18547 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18550 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18551 MVT ExtVT = MVT::v8i32;
18552 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18553 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18554 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18555 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18556 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18557 ALo = DAG.getBitcast(ExtVT, ALo);
18558 AHi = DAG.getBitcast(ExtVT, AHi);
18559 RLo = DAG.getBitcast(ExtVT, RLo);
18560 RHi = DAG.getBitcast(ExtVT, RHi);
18561 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18562 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18563 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18564 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18565 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18568 if (VT == MVT::v8i16) {
18569 unsigned ShiftOpcode = Op->getOpcode();
18571 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18572 // On SSE41 targets we make use of the fact that VSELECT lowers
18573 // to PBLENDVB which selects bytes based just on the sign bit.
18574 if (Subtarget->hasSSE41()) {
18575 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18576 V0 = DAG.getBitcast(ExtVT, V0);
18577 V1 = DAG.getBitcast(ExtVT, V1);
18578 Sel = DAG.getBitcast(ExtVT, Sel);
18579 return DAG.getBitcast(
18580 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18582 // On pre-SSE41 targets we splat the sign bit - a negative value will
18583 // set all bits of the lanes to true and VSELECT uses that in
18584 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18586 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18587 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18590 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18591 if (Subtarget->hasSSE41()) {
18592 // On SSE41 targets we need to replicate the shift mask in both
18593 // bytes for PBLENDVB.
18596 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18597 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18599 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18602 // r = VSELECT(r, shift(r, 8), a);
18603 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18604 R = SignBitSelect(Amt, M, R);
18607 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18609 // r = VSELECT(r, shift(r, 4), a);
18610 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18611 R = SignBitSelect(Amt, M, R);
18614 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18616 // r = VSELECT(r, shift(r, 2), a);
18617 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18618 R = SignBitSelect(Amt, M, R);
18621 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18623 // return VSELECT(r, shift(r, 1), a);
18624 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18625 R = SignBitSelect(Amt, M, R);
18629 // Decompose 256-bit shifts into smaller 128-bit shifts.
18630 if (VT.is256BitVector()) {
18631 unsigned NumElems = VT.getVectorNumElements();
18632 MVT EltVT = VT.getVectorElementType();
18633 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18635 // Extract the two vectors
18636 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18637 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18639 // Recreate the shift amount vectors
18640 SDValue Amt1, Amt2;
18641 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18642 // Constant shift amount
18643 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18644 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18645 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18647 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18648 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18650 // Variable shift amount
18651 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18652 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18655 // Issue new vector shifts for the smaller types
18656 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18657 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18659 // Concatenate the result back
18660 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18666 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18667 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18668 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18669 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18670 // has only one use.
18671 SDNode *N = Op.getNode();
18672 SDValue LHS = N->getOperand(0);
18673 SDValue RHS = N->getOperand(1);
18674 unsigned BaseOp = 0;
18677 switch (Op.getOpcode()) {
18678 default: llvm_unreachable("Unknown ovf instruction!");
18680 // A subtract of one will be selected as a INC. Note that INC doesn't
18681 // set CF, so we can't do this for UADDO.
18682 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18684 BaseOp = X86ISD::INC;
18685 Cond = X86::COND_O;
18688 BaseOp = X86ISD::ADD;
18689 Cond = X86::COND_O;
18692 BaseOp = X86ISD::ADD;
18693 Cond = X86::COND_B;
18696 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18697 // set CF, so we can't do this for USUBO.
18698 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18700 BaseOp = X86ISD::DEC;
18701 Cond = X86::COND_O;
18704 BaseOp = X86ISD::SUB;
18705 Cond = X86::COND_O;
18708 BaseOp = X86ISD::SUB;
18709 Cond = X86::COND_B;
18712 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18713 Cond = X86::COND_O;
18715 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18716 if (N->getValueType(0) == MVT::i8) {
18717 BaseOp = X86ISD::UMUL8;
18718 Cond = X86::COND_O;
18721 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18723 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18726 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18727 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18728 SDValue(Sum.getNode(), 2));
18730 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18734 // Also sets EFLAGS.
18735 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18736 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18739 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18740 DAG.getConstant(Cond, DL, MVT::i32),
18741 SDValue(Sum.getNode(), 1));
18743 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18746 /// Returns true if the operand type is exactly twice the native width, and
18747 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18748 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18749 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18750 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18751 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18754 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18755 else if (OpWidth == 128)
18756 return Subtarget->hasCmpxchg16b();
18761 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18762 return needsCmpXchgNb(SI->getValueOperand()->getType());
18765 // Note: this turns large loads into lock cmpxchg8b/16b.
18766 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18767 TargetLowering::AtomicExpansionKind
18768 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18769 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18770 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18771 : AtomicExpansionKind::None;
18774 TargetLowering::AtomicExpansionKind
18775 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18776 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18777 Type *MemType = AI->getType();
18779 // If the operand is too big, we must see if cmpxchg8/16b is available
18780 // and default to library calls otherwise.
18781 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18782 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18783 : AtomicExpansionKind::None;
18786 AtomicRMWInst::BinOp Op = AI->getOperation();
18789 llvm_unreachable("Unknown atomic operation");
18790 case AtomicRMWInst::Xchg:
18791 case AtomicRMWInst::Add:
18792 case AtomicRMWInst::Sub:
18793 // It's better to use xadd, xsub or xchg for these in all cases.
18794 return AtomicExpansionKind::None;
18795 case AtomicRMWInst::Or:
18796 case AtomicRMWInst::And:
18797 case AtomicRMWInst::Xor:
18798 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18799 // prefix to a normal instruction for these operations.
18800 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18801 : AtomicExpansionKind::None;
18802 case AtomicRMWInst::Nand:
18803 case AtomicRMWInst::Max:
18804 case AtomicRMWInst::Min:
18805 case AtomicRMWInst::UMax:
18806 case AtomicRMWInst::UMin:
18807 // These always require a non-trivial set of data operations on x86. We must
18808 // use a cmpxchg loop.
18809 return AtomicExpansionKind::CmpXChg;
18813 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18814 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18815 // no-sse2). There isn't any reason to disable it if the target processor
18817 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18821 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18822 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18823 Type *MemType = AI->getType();
18824 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18825 // there is no benefit in turning such RMWs into loads, and it is actually
18826 // harmful as it introduces a mfence.
18827 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18830 auto Builder = IRBuilder<>(AI);
18831 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18832 auto SynchScope = AI->getSynchScope();
18833 // We must restrict the ordering to avoid generating loads with Release or
18834 // ReleaseAcquire orderings.
18835 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18836 auto Ptr = AI->getPointerOperand();
18838 // Before the load we need a fence. Here is an example lifted from
18839 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18842 // x.store(1, relaxed);
18843 // r1 = y.fetch_add(0, release);
18845 // y.fetch_add(42, acquire);
18846 // r2 = x.load(relaxed);
18847 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18848 // lowered to just a load without a fence. A mfence flushes the store buffer,
18849 // making the optimization clearly correct.
18850 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18851 // otherwise, we might be able to be more aggressive on relaxed idempotent
18852 // rmw. In practice, they do not look useful, so we don't try to be
18853 // especially clever.
18854 if (SynchScope == SingleThread)
18855 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18856 // the IR level, so we must wrap it in an intrinsic.
18859 if (!hasMFENCE(*Subtarget))
18860 // FIXME: it might make sense to use a locked operation here but on a
18861 // different cache-line to prevent cache-line bouncing. In practice it
18862 // is probably a small win, and x86 processors without mfence are rare
18863 // enough that we do not bother.
18867 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18868 Builder.CreateCall(MFence, {});
18870 // Finally we can emit the atomic load.
18871 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18872 AI->getType()->getPrimitiveSizeInBits());
18873 Loaded->setAtomic(Order, SynchScope);
18874 AI->replaceAllUsesWith(Loaded);
18875 AI->eraseFromParent();
18879 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18880 SelectionDAG &DAG) {
18882 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18883 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18884 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18885 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18887 // The only fence that needs an instruction is a sequentially-consistent
18888 // cross-thread fence.
18889 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18890 if (hasMFENCE(*Subtarget))
18891 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18893 SDValue Chain = Op.getOperand(0);
18894 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
18896 DAG.getRegister(X86::ESP, MVT::i32), // Base
18897 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
18898 DAG.getRegister(0, MVT::i32), // Index
18899 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
18900 DAG.getRegister(0, MVT::i32), // Segment.
18904 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18905 return SDValue(Res, 0);
18908 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18909 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18912 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18913 SelectionDAG &DAG) {
18914 MVT T = Op.getSimpleValueType();
18918 switch(T.SimpleTy) {
18919 default: llvm_unreachable("Invalid value type!");
18920 case MVT::i8: Reg = X86::AL; size = 1; break;
18921 case MVT::i16: Reg = X86::AX; size = 2; break;
18922 case MVT::i32: Reg = X86::EAX; size = 4; break;
18924 assert(Subtarget->is64Bit() && "Node not type legal!");
18925 Reg = X86::RAX; size = 8;
18928 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18929 Op.getOperand(2), SDValue());
18930 SDValue Ops[] = { cpIn.getValue(0),
18933 DAG.getTargetConstant(size, DL, MVT::i8),
18934 cpIn.getValue(1) };
18935 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18936 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18937 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18941 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18942 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18943 MVT::i32, cpOut.getValue(2));
18944 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18945 DAG.getConstant(X86::COND_E, DL, MVT::i8),
18948 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18949 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18950 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18954 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18955 SelectionDAG &DAG) {
18956 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18957 MVT DstVT = Op.getSimpleValueType();
18959 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18960 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18961 if (DstVT != MVT::f64)
18962 // This conversion needs to be expanded.
18965 SDValue InVec = Op->getOperand(0);
18967 unsigned NumElts = SrcVT.getVectorNumElements();
18968 EVT SVT = SrcVT.getVectorElementType();
18970 // Widen the vector in input in the case of MVT::v2i32.
18971 // Example: from MVT::v2i32 to MVT::v4i32.
18972 SmallVector<SDValue, 16> Elts;
18973 for (unsigned i = 0, e = NumElts; i != e; ++i)
18974 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18975 DAG.getIntPtrConstant(i, dl)));
18977 // Explicitly mark the extra elements as Undef.
18978 Elts.append(NumElts, DAG.getUNDEF(SVT));
18980 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18981 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18982 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
18983 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18984 DAG.getIntPtrConstant(0, dl));
18987 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18988 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18989 assert((DstVT == MVT::i64 ||
18990 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18991 "Unexpected custom BITCAST");
18992 // i64 <=> MMX conversions are Legal.
18993 if (SrcVT==MVT::i64 && DstVT.isVector())
18995 if (DstVT==MVT::i64 && SrcVT.isVector())
18997 // MMX <=> MMX conversions are Legal.
18998 if (SrcVT.isVector() && DstVT.isVector())
19000 // All other conversions need to be expanded.
19004 /// Compute the horizontal sum of bytes in V for the elements of VT.
19006 /// Requires V to be a byte vector and VT to be an integer vector type with
19007 /// wider elements than V's type. The width of the elements of VT determines
19008 /// how many bytes of V are summed horizontally to produce each element of the
19010 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19011 const X86Subtarget *Subtarget,
19012 SelectionDAG &DAG) {
19014 MVT ByteVecVT = V.getSimpleValueType();
19015 MVT EltVT = VT.getVectorElementType();
19016 int NumElts = VT.getVectorNumElements();
19017 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19018 "Expected value to have byte element type.");
19019 assert(EltVT != MVT::i8 &&
19020 "Horizontal byte sum only makes sense for wider elements!");
19021 unsigned VecSize = VT.getSizeInBits();
19022 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19024 // PSADBW instruction horizontally add all bytes and leave the result in i64
19025 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19026 if (EltVT == MVT::i64) {
19027 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19028 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
19029 return DAG.getBitcast(VT, V);
19032 if (EltVT == MVT::i32) {
19033 // We unpack the low half and high half into i32s interleaved with zeros so
19034 // that we can use PSADBW to horizontally sum them. The most useful part of
19035 // this is that it lines up the results of two PSADBW instructions to be
19036 // two v2i64 vectors which concatenated are the 4 population counts. We can
19037 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19038 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19039 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19040 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19042 // Do the horizontal sums into two v2i64s.
19043 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19044 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19045 DAG.getBitcast(ByteVecVT, Low), Zeros);
19046 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19047 DAG.getBitcast(ByteVecVT, High), Zeros);
19049 // Merge them together.
19050 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19051 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19052 DAG.getBitcast(ShortVecVT, Low),
19053 DAG.getBitcast(ShortVecVT, High));
19055 return DAG.getBitcast(VT, V);
19058 // The only element type left is i16.
19059 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19061 // To obtain pop count for each i16 element starting from the pop count for
19062 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19063 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19064 // directly supported.
19065 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19066 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19067 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19068 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19069 DAG.getBitcast(ByteVecVT, V));
19070 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19073 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19074 const X86Subtarget *Subtarget,
19075 SelectionDAG &DAG) {
19076 MVT VT = Op.getSimpleValueType();
19077 MVT EltVT = VT.getVectorElementType();
19078 unsigned VecSize = VT.getSizeInBits();
19080 // Implement a lookup table in register by using an algorithm based on:
19081 // http://wm.ite.pl/articles/sse-popcount.html
19083 // The general idea is that every lower byte nibble in the input vector is an
19084 // index into a in-register pre-computed pop count table. We then split up the
19085 // input vector in two new ones: (1) a vector with only the shifted-right
19086 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19087 // masked out higher ones) for each byte. PSHUB is used separately with both
19088 // to index the in-register table. Next, both are added and the result is a
19089 // i8 vector where each element contains the pop count for input byte.
19091 // To obtain the pop count for elements != i8, we follow up with the same
19092 // approach and use additional tricks as described below.
19094 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19095 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19096 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19097 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19099 int NumByteElts = VecSize / 8;
19100 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19101 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19102 SmallVector<SDValue, 16> LUTVec;
19103 for (int i = 0; i < NumByteElts; ++i)
19104 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19105 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19106 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19107 DAG.getConstant(0x0F, DL, MVT::i8));
19108 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19111 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19112 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19113 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19116 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19118 // The input vector is used as the shuffle mask that index elements into the
19119 // LUT. After counting low and high nibbles, add the vector to obtain the
19120 // final pop count per i8 element.
19121 SDValue HighPopCnt =
19122 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19123 SDValue LowPopCnt =
19124 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19125 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19127 if (EltVT == MVT::i8)
19130 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19133 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19134 const X86Subtarget *Subtarget,
19135 SelectionDAG &DAG) {
19136 MVT VT = Op.getSimpleValueType();
19137 assert(VT.is128BitVector() &&
19138 "Only 128-bit vector bitmath lowering supported.");
19140 int VecSize = VT.getSizeInBits();
19141 MVT EltVT = VT.getVectorElementType();
19142 int Len = EltVT.getSizeInBits();
19144 // This is the vectorized version of the "best" algorithm from
19145 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19146 // with a minor tweak to use a series of adds + shifts instead of vector
19147 // multiplications. Implemented for all integer vector types. We only use
19148 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19149 // much faster, even faster than using native popcnt instructions.
19151 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19152 MVT VT = V.getSimpleValueType();
19153 SmallVector<SDValue, 32> Shifters(
19154 VT.getVectorNumElements(),
19155 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19156 return DAG.getNode(OpCode, DL, VT, V,
19157 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19159 auto GetMask = [&](SDValue V, APInt Mask) {
19160 MVT VT = V.getSimpleValueType();
19161 SmallVector<SDValue, 32> Masks(
19162 VT.getVectorNumElements(),
19163 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19164 return DAG.getNode(ISD::AND, DL, VT, V,
19165 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19168 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19169 // x86, so set the SRL type to have elements at least i16 wide. This is
19170 // correct because all of our SRLs are followed immediately by a mask anyways
19171 // that handles any bits that sneak into the high bits of the byte elements.
19172 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19176 // v = v - ((v >> 1) & 0x55555555...)
19178 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19179 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19180 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19182 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19183 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19184 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19185 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19186 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19188 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19189 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19190 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19191 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19193 // At this point, V contains the byte-wise population count, and we are
19194 // merely doing a horizontal sum if necessary to get the wider element
19196 if (EltVT == MVT::i8)
19199 return LowerHorizontalByteSum(
19200 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19204 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19205 SelectionDAG &DAG) {
19206 MVT VT = Op.getSimpleValueType();
19207 // FIXME: Need to add AVX-512 support here!
19208 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19209 "Unknown CTPOP type to handle");
19210 SDLoc DL(Op.getNode());
19211 SDValue Op0 = Op.getOperand(0);
19213 if (!Subtarget->hasSSSE3()) {
19214 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19215 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19216 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19219 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19220 unsigned NumElems = VT.getVectorNumElements();
19222 // Extract each 128-bit vector, compute pop count and concat the result.
19223 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19224 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19226 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19227 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19228 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19231 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19234 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19235 SelectionDAG &DAG) {
19236 assert(Op.getValueType().isVector() &&
19237 "We only do custom lowering for vector population count.");
19238 return LowerVectorCTPOP(Op, Subtarget, DAG);
19241 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19242 SDNode *Node = Op.getNode();
19244 EVT T = Node->getValueType(0);
19245 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19246 DAG.getConstant(0, dl, T), Node->getOperand(2));
19247 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19248 cast<AtomicSDNode>(Node)->getMemoryVT(),
19249 Node->getOperand(0),
19250 Node->getOperand(1), negOp,
19251 cast<AtomicSDNode>(Node)->getMemOperand(),
19252 cast<AtomicSDNode>(Node)->getOrdering(),
19253 cast<AtomicSDNode>(Node)->getSynchScope());
19256 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19257 SDNode *Node = Op.getNode();
19259 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19261 // Convert seq_cst store -> xchg
19262 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19263 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19264 // (The only way to get a 16-byte store is cmpxchg16b)
19265 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19266 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19267 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19268 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19269 cast<AtomicSDNode>(Node)->getMemoryVT(),
19270 Node->getOperand(0),
19271 Node->getOperand(1), Node->getOperand(2),
19272 cast<AtomicSDNode>(Node)->getMemOperand(),
19273 cast<AtomicSDNode>(Node)->getOrdering(),
19274 cast<AtomicSDNode>(Node)->getSynchScope());
19275 return Swap.getValue(1);
19277 // Other atomic stores have a simple pattern.
19281 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19282 EVT VT = Op.getNode()->getSimpleValueType(0);
19284 // Let legalize expand this if it isn't a legal type yet.
19285 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19288 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19291 bool ExtraOp = false;
19292 switch (Op.getOpcode()) {
19293 default: llvm_unreachable("Invalid code");
19294 case ISD::ADDC: Opc = X86ISD::ADD; break;
19295 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19296 case ISD::SUBC: Opc = X86ISD::SUB; break;
19297 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19301 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19303 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19304 Op.getOperand(1), Op.getOperand(2));
19307 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19308 SelectionDAG &DAG) {
19309 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19311 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19312 // which returns the values as { float, float } (in XMM0) or
19313 // { double, double } (which is returned in XMM0, XMM1).
19315 SDValue Arg = Op.getOperand(0);
19316 EVT ArgVT = Arg.getValueType();
19317 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19319 TargetLowering::ArgListTy Args;
19320 TargetLowering::ArgListEntry Entry;
19324 Entry.isSExt = false;
19325 Entry.isZExt = false;
19326 Args.push_back(Entry);
19328 bool isF64 = ArgVT == MVT::f64;
19329 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19330 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19331 // the results are returned via SRet in memory.
19332 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19333 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19335 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19337 Type *RetTy = isF64
19338 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19339 : (Type*)VectorType::get(ArgTy, 4);
19341 TargetLowering::CallLoweringInfo CLI(DAG);
19342 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19343 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19345 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19348 // Returned in xmm0 and xmm1.
19349 return CallResult.first;
19351 // Returned in bits 0:31 and 32:64 xmm0.
19352 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19353 CallResult.first, DAG.getIntPtrConstant(0, dl));
19354 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19355 CallResult.first, DAG.getIntPtrConstant(1, dl));
19356 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19357 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19360 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19361 SelectionDAG &DAG) {
19362 assert(Subtarget->hasAVX512() &&
19363 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19365 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19366 EVT VT = N->getValue().getValueType();
19367 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19370 // X86 scatter kills mask register, so its type should be added to
19371 // the list of return values
19372 if (N->getNumValues() == 1) {
19373 SDValue Index = N->getIndex();
19374 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19375 !Index.getValueType().is512BitVector())
19376 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19378 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19379 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19380 N->getOperand(3), Index };
19382 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19383 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19384 return SDValue(NewScatter.getNode(), 0);
19389 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19390 SelectionDAG &DAG) {
19391 assert(Subtarget->hasAVX512() &&
19392 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19394 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19395 EVT VT = Op.getValueType();
19396 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19399 SDValue Index = N->getIndex();
19400 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19401 !Index.getValueType().is512BitVector()) {
19402 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19403 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19404 N->getOperand(3), Index };
19405 DAG.UpdateNodeOperands(N, Ops);
19410 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19411 SelectionDAG &DAG) const {
19412 // TODO: Eventually, the lowering of these nodes should be informed by or
19413 // deferred to the GC strategy for the function in which they appear. For
19414 // now, however, they must be lowered to something. Since they are logically
19415 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19416 // require special handling for these nodes), lower them as literal NOOPs for
19418 SmallVector<SDValue, 2> Ops;
19420 Ops.push_back(Op.getOperand(0));
19421 if (Op->getGluedNode())
19422 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19425 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19426 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19431 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19432 SelectionDAG &DAG) const {
19433 // TODO: Eventually, the lowering of these nodes should be informed by or
19434 // deferred to the GC strategy for the function in which they appear. For
19435 // now, however, they must be lowered to something. Since they are logically
19436 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19437 // require special handling for these nodes), lower them as literal NOOPs for
19439 SmallVector<SDValue, 2> Ops;
19441 Ops.push_back(Op.getOperand(0));
19442 if (Op->getGluedNode())
19443 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19446 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19447 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19452 /// LowerOperation - Provide custom lowering hooks for some operations.
19454 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19455 switch (Op.getOpcode()) {
19456 default: llvm_unreachable("Should not custom lower this!");
19457 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19458 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19459 return LowerCMP_SWAP(Op, Subtarget, DAG);
19460 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19461 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19462 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19463 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19464 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19465 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19466 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19467 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19468 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19469 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19470 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19471 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19472 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19473 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19474 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19475 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19476 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19477 case ISD::SHL_PARTS:
19478 case ISD::SRA_PARTS:
19479 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19480 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19481 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19482 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19483 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19484 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19485 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19486 case ISD::SIGN_EXTEND_VECTOR_INREG:
19487 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19488 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19489 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19490 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19491 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19493 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19494 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19495 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19496 case ISD::SETCC: return LowerSETCC(Op, DAG);
19497 case ISD::SELECT: return LowerSELECT(Op, DAG);
19498 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19499 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19500 case ISD::VASTART: return LowerVASTART(Op, DAG);
19501 case ISD::VAARG: return LowerVAARG(Op, DAG);
19502 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19503 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19504 case ISD::INTRINSIC_VOID:
19505 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19506 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19507 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19508 case ISD::FRAME_TO_ARGS_OFFSET:
19509 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19510 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19511 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19512 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19513 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19514 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19515 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19516 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19517 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19518 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19520 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19521 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19522 case ISD::UMUL_LOHI:
19523 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19526 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19532 case ISD::UMULO: return LowerXALUO(Op, DAG);
19533 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19534 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19538 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19539 case ISD::ADD: return LowerADD(Op, DAG);
19540 case ISD::SUB: return LowerSUB(Op, DAG);
19544 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19545 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19546 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19547 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19548 case ISD::GC_TRANSITION_START:
19549 return LowerGC_TRANSITION_START(Op, DAG);
19550 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19554 /// ReplaceNodeResults - Replace a node with an illegal result type
19555 /// with a new node built out of custom code.
19556 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19557 SmallVectorImpl<SDValue>&Results,
19558 SelectionDAG &DAG) const {
19560 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19561 switch (N->getOpcode()) {
19563 llvm_unreachable("Do not know how to custom type legalize this operation!");
19564 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19565 case X86ISD::FMINC:
19567 case X86ISD::FMAXC:
19568 case X86ISD::FMAX: {
19569 EVT VT = N->getValueType(0);
19570 if (VT != MVT::v2f32)
19571 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19572 SDValue UNDEF = DAG.getUNDEF(VT);
19573 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19574 N->getOperand(0), UNDEF);
19575 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19576 N->getOperand(1), UNDEF);
19577 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19580 case ISD::SIGN_EXTEND_INREG:
19585 // We don't want to expand or promote these.
19592 case ISD::UDIVREM: {
19593 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19594 Results.push_back(V);
19597 case ISD::FP_TO_SINT:
19598 case ISD::FP_TO_UINT: {
19599 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19601 std::pair<SDValue,SDValue> Vals =
19602 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19603 SDValue FIST = Vals.first, StackSlot = Vals.second;
19604 if (FIST.getNode()) {
19605 EVT VT = N->getValueType(0);
19606 // Return a load from the stack slot.
19607 if (StackSlot.getNode())
19608 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19609 MachinePointerInfo(),
19610 false, false, false, 0));
19612 Results.push_back(FIST);
19616 case ISD::UINT_TO_FP: {
19617 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19618 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19619 N->getValueType(0) != MVT::v2f32)
19621 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19623 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19625 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19626 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19627 DAG.getBitcast(MVT::v2i64, VBias));
19628 Or = DAG.getBitcast(MVT::v2f64, Or);
19629 // TODO: Are there any fast-math-flags to propagate here?
19630 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19631 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19634 case ISD::FP_ROUND: {
19635 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19637 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19638 Results.push_back(V);
19641 case ISD::FP_EXTEND: {
19642 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19643 // No other ValueType for FP_EXTEND should reach this point.
19644 assert(N->getValueType(0) == MVT::v2f32 &&
19645 "Do not know how to legalize this Node");
19648 case ISD::INTRINSIC_W_CHAIN: {
19649 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19651 default : llvm_unreachable("Do not know how to custom type "
19652 "legalize this intrinsic operation!");
19653 case Intrinsic::x86_rdtsc:
19654 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19656 case Intrinsic::x86_rdtscp:
19657 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19659 case Intrinsic::x86_rdpmc:
19660 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19663 case ISD::READCYCLECOUNTER: {
19664 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19667 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19668 EVT T = N->getValueType(0);
19669 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19670 bool Regs64bit = T == MVT::i128;
19671 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19672 SDValue cpInL, cpInH;
19673 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19674 DAG.getConstant(0, dl, HalfT));
19675 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19676 DAG.getConstant(1, dl, HalfT));
19677 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19678 Regs64bit ? X86::RAX : X86::EAX,
19680 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19681 Regs64bit ? X86::RDX : X86::EDX,
19682 cpInH, cpInL.getValue(1));
19683 SDValue swapInL, swapInH;
19684 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19685 DAG.getConstant(0, dl, HalfT));
19686 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19687 DAG.getConstant(1, dl, HalfT));
19688 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19689 Regs64bit ? X86::RBX : X86::EBX,
19690 swapInL, cpInH.getValue(1));
19691 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19692 Regs64bit ? X86::RCX : X86::ECX,
19693 swapInH, swapInL.getValue(1));
19694 SDValue Ops[] = { swapInH.getValue(0),
19696 swapInH.getValue(1) };
19697 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19698 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19699 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19700 X86ISD::LCMPXCHG8_DAG;
19701 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19702 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19703 Regs64bit ? X86::RAX : X86::EAX,
19704 HalfT, Result.getValue(1));
19705 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19706 Regs64bit ? X86::RDX : X86::EDX,
19707 HalfT, cpOutL.getValue(2));
19708 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19710 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19711 MVT::i32, cpOutH.getValue(2));
19713 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19714 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19715 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19717 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19718 Results.push_back(Success);
19719 Results.push_back(EFLAGS.getValue(1));
19722 case ISD::ATOMIC_SWAP:
19723 case ISD::ATOMIC_LOAD_ADD:
19724 case ISD::ATOMIC_LOAD_SUB:
19725 case ISD::ATOMIC_LOAD_AND:
19726 case ISD::ATOMIC_LOAD_OR:
19727 case ISD::ATOMIC_LOAD_XOR:
19728 case ISD::ATOMIC_LOAD_NAND:
19729 case ISD::ATOMIC_LOAD_MIN:
19730 case ISD::ATOMIC_LOAD_MAX:
19731 case ISD::ATOMIC_LOAD_UMIN:
19732 case ISD::ATOMIC_LOAD_UMAX:
19733 case ISD::ATOMIC_LOAD: {
19734 // Delegate to generic TypeLegalization. Situations we can really handle
19735 // should have already been dealt with by AtomicExpandPass.cpp.
19738 case ISD::BITCAST: {
19739 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19740 EVT DstVT = N->getValueType(0);
19741 EVT SrcVT = N->getOperand(0)->getValueType(0);
19743 if (SrcVT != MVT::f64 ||
19744 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19747 unsigned NumElts = DstVT.getVectorNumElements();
19748 EVT SVT = DstVT.getVectorElementType();
19749 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19750 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19751 MVT::v2f64, N->getOperand(0));
19752 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19754 if (ExperimentalVectorWideningLegalization) {
19755 // If we are legalizing vectors by widening, we already have the desired
19756 // legal vector type, just return it.
19757 Results.push_back(ToVecInt);
19761 SmallVector<SDValue, 8> Elts;
19762 for (unsigned i = 0, e = NumElts; i != e; ++i)
19763 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19764 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19766 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19771 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19772 switch ((X86ISD::NodeType)Opcode) {
19773 case X86ISD::FIRST_NUMBER: break;
19774 case X86ISD::BSF: return "X86ISD::BSF";
19775 case X86ISD::BSR: return "X86ISD::BSR";
19776 case X86ISD::SHLD: return "X86ISD::SHLD";
19777 case X86ISD::SHRD: return "X86ISD::SHRD";
19778 case X86ISD::FAND: return "X86ISD::FAND";
19779 case X86ISD::FANDN: return "X86ISD::FANDN";
19780 case X86ISD::FOR: return "X86ISD::FOR";
19781 case X86ISD::FXOR: return "X86ISD::FXOR";
19782 case X86ISD::FILD: return "X86ISD::FILD";
19783 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19784 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19785 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19786 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19787 case X86ISD::FLD: return "X86ISD::FLD";
19788 case X86ISD::FST: return "X86ISD::FST";
19789 case X86ISD::CALL: return "X86ISD::CALL";
19790 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19791 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19792 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19793 case X86ISD::BT: return "X86ISD::BT";
19794 case X86ISD::CMP: return "X86ISD::CMP";
19795 case X86ISD::COMI: return "X86ISD::COMI";
19796 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19797 case X86ISD::CMPM: return "X86ISD::CMPM";
19798 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19799 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19800 case X86ISD::SETCC: return "X86ISD::SETCC";
19801 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19802 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19803 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19804 case X86ISD::CMOV: return "X86ISD::CMOV";
19805 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19806 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19807 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19808 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19809 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19810 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19811 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19812 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19813 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19814 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19815 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19816 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19817 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19818 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19819 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19820 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19821 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19822 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19823 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19824 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19825 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19826 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19827 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19828 case X86ISD::HADD: return "X86ISD::HADD";
19829 case X86ISD::HSUB: return "X86ISD::HSUB";
19830 case X86ISD::FHADD: return "X86ISD::FHADD";
19831 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19832 case X86ISD::ABS: return "X86ISD::ABS";
19833 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19834 case X86ISD::FMAX: return "X86ISD::FMAX";
19835 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19836 case X86ISD::FMIN: return "X86ISD::FMIN";
19837 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19838 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19839 case X86ISD::FMINC: return "X86ISD::FMINC";
19840 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19841 case X86ISD::FRCP: return "X86ISD::FRCP";
19842 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19843 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19844 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19845 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19846 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19847 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19848 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19849 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19850 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19851 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19852 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19853 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19854 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19855 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19856 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19857 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19858 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19859 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19860 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19861 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19862 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19863 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19864 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19865 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19866 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19867 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19868 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19869 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19870 case X86ISD::VSHL: return "X86ISD::VSHL";
19871 case X86ISD::VSRL: return "X86ISD::VSRL";
19872 case X86ISD::VSRA: return "X86ISD::VSRA";
19873 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19874 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19875 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19876 case X86ISD::CMPP: return "X86ISD::CMPP";
19877 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19878 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19879 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19880 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19881 case X86ISD::ADD: return "X86ISD::ADD";
19882 case X86ISD::SUB: return "X86ISD::SUB";
19883 case X86ISD::ADC: return "X86ISD::ADC";
19884 case X86ISD::SBB: return "X86ISD::SBB";
19885 case X86ISD::SMUL: return "X86ISD::SMUL";
19886 case X86ISD::UMUL: return "X86ISD::UMUL";
19887 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19888 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19889 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19890 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19891 case X86ISD::INC: return "X86ISD::INC";
19892 case X86ISD::DEC: return "X86ISD::DEC";
19893 case X86ISD::OR: return "X86ISD::OR";
19894 case X86ISD::XOR: return "X86ISD::XOR";
19895 case X86ISD::AND: return "X86ISD::AND";
19896 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19897 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19898 case X86ISD::PTEST: return "X86ISD::PTEST";
19899 case X86ISD::TESTP: return "X86ISD::TESTP";
19900 case X86ISD::TESTM: return "X86ISD::TESTM";
19901 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19902 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19903 case X86ISD::KTEST: return "X86ISD::KTEST";
19904 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19905 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19906 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19907 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19908 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19909 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19910 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19911 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19912 case X86ISD::SHUF128: return "X86ISD::SHUF128";
19913 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19914 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19915 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19916 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19917 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19918 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19919 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19920 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19921 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19922 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19923 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19924 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19925 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19926 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
19927 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19928 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
19929 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19930 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19931 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19932 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19933 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19934 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19935 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
19936 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
19937 case X86ISD::VRANGE: return "X86ISD::VRANGE";
19938 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19939 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19940 case X86ISD::PSADBW: return "X86ISD::PSADBW";
19941 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
19942 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19943 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19944 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19945 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19946 case X86ISD::MFENCE: return "X86ISD::MFENCE";
19947 case X86ISD::SFENCE: return "X86ISD::SFENCE";
19948 case X86ISD::LFENCE: return "X86ISD::LFENCE";
19949 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19950 case X86ISD::SAHF: return "X86ISD::SAHF";
19951 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19952 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19953 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
19954 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
19955 case X86ISD::VPSHA: return "X86ISD::VPSHA";
19956 case X86ISD::VPSHL: return "X86ISD::VPSHL";
19957 case X86ISD::VPCOM: return "X86ISD::VPCOM";
19958 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
19959 case X86ISD::FMADD: return "X86ISD::FMADD";
19960 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19961 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19962 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19963 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19964 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19965 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
19966 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
19967 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
19968 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
19969 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
19970 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
19971 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
19972 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
19973 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
19974 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19975 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19976 case X86ISD::XTEST: return "X86ISD::XTEST";
19977 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19978 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19979 case X86ISD::SELECT: return "X86ISD::SELECT";
19980 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
19981 case X86ISD::RCP28: return "X86ISD::RCP28";
19982 case X86ISD::EXP2: return "X86ISD::EXP2";
19983 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
19984 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
19985 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
19986 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
19987 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
19988 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
19989 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
19990 case X86ISD::SCALEF: return "X86ISD::SCALEF";
19991 case X86ISD::ADDS: return "X86ISD::ADDS";
19992 case X86ISD::SUBS: return "X86ISD::SUBS";
19993 case X86ISD::AVG: return "X86ISD::AVG";
19994 case X86ISD::MULHRS: return "X86ISD::MULHRS";
19995 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
19996 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
19997 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
19998 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
19999 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20004 // isLegalAddressingMode - Return true if the addressing mode represented
20005 // by AM is legal for this target, for a load/store of the specified type.
20006 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20007 const AddrMode &AM, Type *Ty,
20008 unsigned AS) const {
20009 // X86 supports extremely general addressing modes.
20010 CodeModel::Model M = getTargetMachine().getCodeModel();
20011 Reloc::Model R = getTargetMachine().getRelocationModel();
20013 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20014 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20019 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20021 // If a reference to this global requires an extra load, we can't fold it.
20022 if (isGlobalStubReference(GVFlags))
20025 // If BaseGV requires a register for the PIC base, we cannot also have a
20026 // BaseReg specified.
20027 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20030 // If lower 4G is not available, then we must use rip-relative addressing.
20031 if ((M != CodeModel::Small || R != Reloc::Static) &&
20032 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20036 switch (AM.Scale) {
20042 // These scales always work.
20047 // These scales are formed with basereg+scalereg. Only accept if there is
20052 default: // Other stuff never works.
20059 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20060 unsigned Bits = Ty->getScalarSizeInBits();
20062 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20063 // particularly cheaper than those without.
20067 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20068 // variable shifts just as cheap as scalar ones.
20069 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20072 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20073 // fully general vector.
20077 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20078 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20080 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20081 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20082 return NumBits1 > NumBits2;
20085 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20086 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20089 if (!isTypeLegal(EVT::getEVT(Ty1)))
20092 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20094 // Assuming the caller doesn't have a zeroext or signext return parameter,
20095 // truncation all the way down to i1 is valid.
20099 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20100 return isInt<32>(Imm);
20103 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20104 // Can also use sub to handle negated immediates.
20105 return isInt<32>(Imm);
20108 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20109 if (!VT1.isInteger() || !VT2.isInteger())
20111 unsigned NumBits1 = VT1.getSizeInBits();
20112 unsigned NumBits2 = VT2.getSizeInBits();
20113 return NumBits1 > NumBits2;
20116 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20117 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20118 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20121 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20122 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20123 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20126 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20127 EVT VT1 = Val.getValueType();
20128 if (isZExtFree(VT1, VT2))
20131 if (Val.getOpcode() != ISD::LOAD)
20134 if (!VT1.isSimple() || !VT1.isInteger() ||
20135 !VT2.isSimple() || !VT2.isInteger())
20138 switch (VT1.getSimpleVT().SimpleTy) {
20143 // X86 has 8, 16, and 32-bit zero-extending loads.
20150 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20153 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20154 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20157 VT = VT.getScalarType();
20159 if (!VT.isSimple())
20162 switch (VT.getSimpleVT().SimpleTy) {
20173 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20174 // i16 instructions are longer (0x66 prefix) and potentially slower.
20175 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20178 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20179 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20180 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20181 /// are assumed to be legal.
20183 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20185 if (!VT.isSimple())
20188 // Not for i1 vectors
20189 if (VT.getScalarType() == MVT::i1)
20192 // Very little shuffling can be done for 64-bit vectors right now.
20193 if (VT.getSizeInBits() == 64)
20196 // We only care that the types being shuffled are legal. The lowering can
20197 // handle any possible shuffle mask that results.
20198 return isTypeLegal(VT.getSimpleVT());
20202 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20204 // Just delegate to the generic legality, clear masks aren't special.
20205 return isShuffleMaskLegal(Mask, VT);
20208 //===----------------------------------------------------------------------===//
20209 // X86 Scheduler Hooks
20210 //===----------------------------------------------------------------------===//
20212 /// Utility function to emit xbegin specifying the start of an RTM region.
20213 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20214 const TargetInstrInfo *TII) {
20215 DebugLoc DL = MI->getDebugLoc();
20217 const BasicBlock *BB = MBB->getBasicBlock();
20218 MachineFunction::iterator I = MBB;
20221 // For the v = xbegin(), we generate
20232 MachineBasicBlock *thisMBB = MBB;
20233 MachineFunction *MF = MBB->getParent();
20234 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20235 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20236 MF->insert(I, mainMBB);
20237 MF->insert(I, sinkMBB);
20239 // Transfer the remainder of BB and its successor edges to sinkMBB.
20240 sinkMBB->splice(sinkMBB->begin(), MBB,
20241 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20242 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20246 // # fallthrough to mainMBB
20247 // # abortion to sinkMBB
20248 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20249 thisMBB->addSuccessor(mainMBB);
20250 thisMBB->addSuccessor(sinkMBB);
20254 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20255 mainMBB->addSuccessor(sinkMBB);
20258 // EAX is live into the sinkMBB
20259 sinkMBB->addLiveIn(X86::EAX);
20260 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20261 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20264 MI->eraseFromParent();
20268 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20269 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20270 // in the .td file.
20271 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20272 const TargetInstrInfo *TII) {
20274 switch (MI->getOpcode()) {
20275 default: llvm_unreachable("illegal opcode!");
20276 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20277 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20278 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20279 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20280 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20281 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20282 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20283 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20286 DebugLoc dl = MI->getDebugLoc();
20287 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20289 unsigned NumArgs = MI->getNumOperands();
20290 for (unsigned i = 1; i < NumArgs; ++i) {
20291 MachineOperand &Op = MI->getOperand(i);
20292 if (!(Op.isReg() && Op.isImplicit()))
20293 MIB.addOperand(Op);
20295 if (MI->hasOneMemOperand())
20296 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20298 BuildMI(*BB, MI, dl,
20299 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20300 .addReg(X86::XMM0);
20302 MI->eraseFromParent();
20306 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20307 // defs in an instruction pattern
20308 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20309 const TargetInstrInfo *TII) {
20311 switch (MI->getOpcode()) {
20312 default: llvm_unreachable("illegal opcode!");
20313 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20314 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20315 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20316 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20317 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20318 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20319 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20320 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20323 DebugLoc dl = MI->getDebugLoc();
20324 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20326 unsigned NumArgs = MI->getNumOperands(); // remove the results
20327 for (unsigned i = 1; i < NumArgs; ++i) {
20328 MachineOperand &Op = MI->getOperand(i);
20329 if (!(Op.isReg() && Op.isImplicit()))
20330 MIB.addOperand(Op);
20332 if (MI->hasOneMemOperand())
20333 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20335 BuildMI(*BB, MI, dl,
20336 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20339 MI->eraseFromParent();
20343 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20344 const X86Subtarget *Subtarget) {
20345 DebugLoc dl = MI->getDebugLoc();
20346 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20347 // Address into RAX/EAX, other two args into ECX, EDX.
20348 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20349 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20350 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20351 for (int i = 0; i < X86::AddrNumOperands; ++i)
20352 MIB.addOperand(MI->getOperand(i));
20354 unsigned ValOps = X86::AddrNumOperands;
20355 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20356 .addReg(MI->getOperand(ValOps).getReg());
20357 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20358 .addReg(MI->getOperand(ValOps+1).getReg());
20360 // The instruction doesn't actually take any operands though.
20361 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20363 MI->eraseFromParent(); // The pseudo is gone now.
20367 MachineBasicBlock *
20368 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20369 MachineBasicBlock *MBB) const {
20370 // Emit va_arg instruction on X86-64.
20372 // Operands to this pseudo-instruction:
20373 // 0 ) Output : destination address (reg)
20374 // 1-5) Input : va_list address (addr, i64mem)
20375 // 6 ) ArgSize : Size (in bytes) of vararg type
20376 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20377 // 8 ) Align : Alignment of type
20378 // 9 ) EFLAGS (implicit-def)
20380 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20381 static_assert(X86::AddrNumOperands == 5,
20382 "VAARG_64 assumes 5 address operands");
20384 unsigned DestReg = MI->getOperand(0).getReg();
20385 MachineOperand &Base = MI->getOperand(1);
20386 MachineOperand &Scale = MI->getOperand(2);
20387 MachineOperand &Index = MI->getOperand(3);
20388 MachineOperand &Disp = MI->getOperand(4);
20389 MachineOperand &Segment = MI->getOperand(5);
20390 unsigned ArgSize = MI->getOperand(6).getImm();
20391 unsigned ArgMode = MI->getOperand(7).getImm();
20392 unsigned Align = MI->getOperand(8).getImm();
20394 // Memory Reference
20395 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20396 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20397 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20399 // Machine Information
20400 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20401 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20402 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20403 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20404 DebugLoc DL = MI->getDebugLoc();
20406 // struct va_list {
20409 // i64 overflow_area (address)
20410 // i64 reg_save_area (address)
20412 // sizeof(va_list) = 24
20413 // alignment(va_list) = 8
20415 unsigned TotalNumIntRegs = 6;
20416 unsigned TotalNumXMMRegs = 8;
20417 bool UseGPOffset = (ArgMode == 1);
20418 bool UseFPOffset = (ArgMode == 2);
20419 unsigned MaxOffset = TotalNumIntRegs * 8 +
20420 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20422 /* Align ArgSize to a multiple of 8 */
20423 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20424 bool NeedsAlign = (Align > 8);
20426 MachineBasicBlock *thisMBB = MBB;
20427 MachineBasicBlock *overflowMBB;
20428 MachineBasicBlock *offsetMBB;
20429 MachineBasicBlock *endMBB;
20431 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20432 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20433 unsigned OffsetReg = 0;
20435 if (!UseGPOffset && !UseFPOffset) {
20436 // If we only pull from the overflow region, we don't create a branch.
20437 // We don't need to alter control flow.
20438 OffsetDestReg = 0; // unused
20439 OverflowDestReg = DestReg;
20441 offsetMBB = nullptr;
20442 overflowMBB = thisMBB;
20445 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20446 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20447 // If not, pull from overflow_area. (branch to overflowMBB)
20452 // offsetMBB overflowMBB
20457 // Registers for the PHI in endMBB
20458 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20459 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20461 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20462 MachineFunction *MF = MBB->getParent();
20463 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20464 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20465 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20467 MachineFunction::iterator MBBIter = MBB;
20470 // Insert the new basic blocks
20471 MF->insert(MBBIter, offsetMBB);
20472 MF->insert(MBBIter, overflowMBB);
20473 MF->insert(MBBIter, endMBB);
20475 // Transfer the remainder of MBB and its successor edges to endMBB.
20476 endMBB->splice(endMBB->begin(), thisMBB,
20477 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20478 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20480 // Make offsetMBB and overflowMBB successors of thisMBB
20481 thisMBB->addSuccessor(offsetMBB);
20482 thisMBB->addSuccessor(overflowMBB);
20484 // endMBB is a successor of both offsetMBB and overflowMBB
20485 offsetMBB->addSuccessor(endMBB);
20486 overflowMBB->addSuccessor(endMBB);
20488 // Load the offset value into a register
20489 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20490 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20494 .addDisp(Disp, UseFPOffset ? 4 : 0)
20495 .addOperand(Segment)
20496 .setMemRefs(MMOBegin, MMOEnd);
20498 // Check if there is enough room left to pull this argument.
20499 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20501 .addImm(MaxOffset + 8 - ArgSizeA8);
20503 // Branch to "overflowMBB" if offset >= max
20504 // Fall through to "offsetMBB" otherwise
20505 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20506 .addMBB(overflowMBB);
20509 // In offsetMBB, emit code to use the reg_save_area.
20511 assert(OffsetReg != 0);
20513 // Read the reg_save_area address.
20514 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20515 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20520 .addOperand(Segment)
20521 .setMemRefs(MMOBegin, MMOEnd);
20523 // Zero-extend the offset
20524 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20525 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20528 .addImm(X86::sub_32bit);
20530 // Add the offset to the reg_save_area to get the final address.
20531 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20532 .addReg(OffsetReg64)
20533 .addReg(RegSaveReg);
20535 // Compute the offset for the next argument
20536 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20537 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20539 .addImm(UseFPOffset ? 16 : 8);
20541 // Store it back into the va_list.
20542 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20546 .addDisp(Disp, UseFPOffset ? 4 : 0)
20547 .addOperand(Segment)
20548 .addReg(NextOffsetReg)
20549 .setMemRefs(MMOBegin, MMOEnd);
20552 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20557 // Emit code to use overflow area
20560 // Load the overflow_area address into a register.
20561 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20562 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20567 .addOperand(Segment)
20568 .setMemRefs(MMOBegin, MMOEnd);
20570 // If we need to align it, do so. Otherwise, just copy the address
20571 // to OverflowDestReg.
20573 // Align the overflow address
20574 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20575 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20577 // aligned_addr = (addr + (align-1)) & ~(align-1)
20578 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20579 .addReg(OverflowAddrReg)
20582 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20584 .addImm(~(uint64_t)(Align-1));
20586 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20587 .addReg(OverflowAddrReg);
20590 // Compute the next overflow address after this argument.
20591 // (the overflow address should be kept 8-byte aligned)
20592 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20593 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20594 .addReg(OverflowDestReg)
20595 .addImm(ArgSizeA8);
20597 // Store the new overflow address.
20598 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20603 .addOperand(Segment)
20604 .addReg(NextAddrReg)
20605 .setMemRefs(MMOBegin, MMOEnd);
20607 // If we branched, emit the PHI to the front of endMBB.
20609 BuildMI(*endMBB, endMBB->begin(), DL,
20610 TII->get(X86::PHI), DestReg)
20611 .addReg(OffsetDestReg).addMBB(offsetMBB)
20612 .addReg(OverflowDestReg).addMBB(overflowMBB);
20615 // Erase the pseudo instruction
20616 MI->eraseFromParent();
20621 MachineBasicBlock *
20622 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20624 MachineBasicBlock *MBB) const {
20625 // Emit code to save XMM registers to the stack. The ABI says that the
20626 // number of registers to save is given in %al, so it's theoretically
20627 // possible to do an indirect jump trick to avoid saving all of them,
20628 // however this code takes a simpler approach and just executes all
20629 // of the stores if %al is non-zero. It's less code, and it's probably
20630 // easier on the hardware branch predictor, and stores aren't all that
20631 // expensive anyway.
20633 // Create the new basic blocks. One block contains all the XMM stores,
20634 // and one block is the final destination regardless of whether any
20635 // stores were performed.
20636 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20637 MachineFunction *F = MBB->getParent();
20638 MachineFunction::iterator MBBIter = MBB;
20640 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20641 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20642 F->insert(MBBIter, XMMSaveMBB);
20643 F->insert(MBBIter, EndMBB);
20645 // Transfer the remainder of MBB and its successor edges to EndMBB.
20646 EndMBB->splice(EndMBB->begin(), MBB,
20647 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20648 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20650 // The original block will now fall through to the XMM save block.
20651 MBB->addSuccessor(XMMSaveMBB);
20652 // The XMMSaveMBB will fall through to the end block.
20653 XMMSaveMBB->addSuccessor(EndMBB);
20655 // Now add the instructions.
20656 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20657 DebugLoc DL = MI->getDebugLoc();
20659 unsigned CountReg = MI->getOperand(0).getReg();
20660 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20661 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20663 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20664 // If %al is 0, branch around the XMM save block.
20665 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20666 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20667 MBB->addSuccessor(EndMBB);
20670 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20671 // that was just emitted, but clearly shouldn't be "saved".
20672 assert((MI->getNumOperands() <= 3 ||
20673 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20674 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20675 && "Expected last argument to be EFLAGS");
20676 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20677 // In the XMM save block, save all the XMM argument registers.
20678 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20679 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20680 MachineMemOperand *MMO = F->getMachineMemOperand(
20681 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20682 MachineMemOperand::MOStore,
20683 /*Size=*/16, /*Align=*/16);
20684 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20685 .addFrameIndex(RegSaveFrameIndex)
20686 .addImm(/*Scale=*/1)
20687 .addReg(/*IndexReg=*/0)
20688 .addImm(/*Disp=*/Offset)
20689 .addReg(/*Segment=*/0)
20690 .addReg(MI->getOperand(i).getReg())
20691 .addMemOperand(MMO);
20694 MI->eraseFromParent(); // The pseudo instruction is gone now.
20699 // The EFLAGS operand of SelectItr might be missing a kill marker
20700 // because there were multiple uses of EFLAGS, and ISel didn't know
20701 // which to mark. Figure out whether SelectItr should have had a
20702 // kill marker, and set it if it should. Returns the correct kill
20704 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20705 MachineBasicBlock* BB,
20706 const TargetRegisterInfo* TRI) {
20707 // Scan forward through BB for a use/def of EFLAGS.
20708 MachineBasicBlock::iterator miI(std::next(SelectItr));
20709 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20710 const MachineInstr& mi = *miI;
20711 if (mi.readsRegister(X86::EFLAGS))
20713 if (mi.definesRegister(X86::EFLAGS))
20714 break; // Should have kill-flag - update below.
20717 // If we hit the end of the block, check whether EFLAGS is live into a
20719 if (miI == BB->end()) {
20720 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20721 sEnd = BB->succ_end();
20722 sItr != sEnd; ++sItr) {
20723 MachineBasicBlock* succ = *sItr;
20724 if (succ->isLiveIn(X86::EFLAGS))
20729 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20730 // out. SelectMI should have a kill flag on EFLAGS.
20731 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20735 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20736 // together with other CMOV pseudo-opcodes into a single basic-block with
20737 // conditional jump around it.
20738 static bool isCMOVPseudo(MachineInstr *MI) {
20739 switch (MI->getOpcode()) {
20740 case X86::CMOV_FR32:
20741 case X86::CMOV_FR64:
20742 case X86::CMOV_GR8:
20743 case X86::CMOV_GR16:
20744 case X86::CMOV_GR32:
20745 case X86::CMOV_RFP32:
20746 case X86::CMOV_RFP64:
20747 case X86::CMOV_RFP80:
20748 case X86::CMOV_V2F64:
20749 case X86::CMOV_V2I64:
20750 case X86::CMOV_V4F32:
20751 case X86::CMOV_V4F64:
20752 case X86::CMOV_V4I64:
20753 case X86::CMOV_V16F32:
20754 case X86::CMOV_V8F32:
20755 case X86::CMOV_V8F64:
20756 case X86::CMOV_V8I64:
20757 case X86::CMOV_V8I1:
20758 case X86::CMOV_V16I1:
20759 case X86::CMOV_V32I1:
20760 case X86::CMOV_V64I1:
20768 MachineBasicBlock *
20769 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20770 MachineBasicBlock *BB) const {
20771 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20772 DebugLoc DL = MI->getDebugLoc();
20774 // To "insert" a SELECT_CC instruction, we actually have to insert the
20775 // diamond control-flow pattern. The incoming instruction knows the
20776 // destination vreg to set, the condition code register to branch on, the
20777 // true/false values to select between, and a branch opcode to use.
20778 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20779 MachineFunction::iterator It = BB;
20785 // cmpTY ccX, r1, r2
20787 // fallthrough --> copy0MBB
20788 MachineBasicBlock *thisMBB = BB;
20789 MachineFunction *F = BB->getParent();
20791 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20792 // as described above, by inserting a BB, and then making a PHI at the join
20793 // point to select the true and false operands of the CMOV in the PHI.
20795 // The code also handles two different cases of multiple CMOV opcodes
20799 // In this case, there are multiple CMOVs in a row, all which are based on
20800 // the same condition setting (or the exact opposite condition setting).
20801 // In this case we can lower all the CMOVs using a single inserted BB, and
20802 // then make a number of PHIs at the join point to model the CMOVs. The only
20803 // trickiness here, is that in a case like:
20805 // t2 = CMOV cond1 t1, f1
20806 // t3 = CMOV cond1 t2, f2
20808 // when rewriting this into PHIs, we have to perform some renaming on the
20809 // temps since you cannot have a PHI operand refer to a PHI result earlier
20810 // in the same block. The "simple" but wrong lowering would be:
20812 // t2 = PHI t1(BB1), f1(BB2)
20813 // t3 = PHI t2(BB1), f2(BB2)
20815 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20816 // renaming is to note that on the path through BB1, t2 is really just a
20817 // copy of t1, and do that renaming, properly generating:
20819 // t2 = PHI t1(BB1), f1(BB2)
20820 // t3 = PHI t1(BB1), f2(BB2)
20822 // Case 2, we lower cascaded CMOVs such as
20824 // (CMOV (CMOV F, T, cc1), T, cc2)
20826 // to two successives branches. For that, we look for another CMOV as the
20827 // following instruction.
20829 // Without this, we would add a PHI between the two jumps, which ends up
20830 // creating a few copies all around. For instance, for
20832 // (sitofp (zext (fcmp une)))
20834 // we would generate:
20836 // ucomiss %xmm1, %xmm0
20837 // movss <1.0f>, %xmm0
20838 // movaps %xmm0, %xmm1
20840 // xorps %xmm1, %xmm1
20843 // movaps %xmm1, %xmm0
20847 // because this custom-inserter would have generated:
20859 // A: X = ...; Y = ...
20861 // C: Z = PHI [X, A], [Y, B]
20863 // E: PHI [X, C], [Z, D]
20865 // If we lower both CMOVs in a single step, we can instead generate:
20877 // A: X = ...; Y = ...
20879 // E: PHI [X, A], [X, C], [Y, D]
20881 // Which, in our sitofp/fcmp example, gives us something like:
20883 // ucomiss %xmm1, %xmm0
20884 // movss <1.0f>, %xmm0
20887 // xorps %xmm0, %xmm0
20891 MachineInstr *CascadedCMOV = nullptr;
20892 MachineInstr *LastCMOV = MI;
20893 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
20894 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
20895 MachineBasicBlock::iterator NextMIIt =
20896 std::next(MachineBasicBlock::iterator(MI));
20898 // Check for case 1, where there are multiple CMOVs with the same condition
20899 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
20900 // number of jumps the most.
20902 if (isCMOVPseudo(MI)) {
20903 // See if we have a string of CMOVS with the same condition.
20904 while (NextMIIt != BB->end() &&
20905 isCMOVPseudo(NextMIIt) &&
20906 (NextMIIt->getOperand(3).getImm() == CC ||
20907 NextMIIt->getOperand(3).getImm() == OppCC)) {
20908 LastCMOV = &*NextMIIt;
20913 // This checks for case 2, but only do this if we didn't already find
20914 // case 1, as indicated by LastCMOV == MI.
20915 if (LastCMOV == MI &&
20916 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
20917 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
20918 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
20919 CascadedCMOV = &*NextMIIt;
20922 MachineBasicBlock *jcc1MBB = nullptr;
20924 // If we have a cascaded CMOV, we lower it to two successive branches to
20925 // the same block. EFLAGS is used by both, so mark it as live in the second.
20926 if (CascadedCMOV) {
20927 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
20928 F->insert(It, jcc1MBB);
20929 jcc1MBB->addLiveIn(X86::EFLAGS);
20932 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20933 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20934 F->insert(It, copy0MBB);
20935 F->insert(It, sinkMBB);
20937 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20938 // live into the sink and copy blocks.
20939 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
20941 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
20942 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
20943 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
20944 copy0MBB->addLiveIn(X86::EFLAGS);
20945 sinkMBB->addLiveIn(X86::EFLAGS);
20948 // Transfer the remainder of BB and its successor edges to sinkMBB.
20949 sinkMBB->splice(sinkMBB->begin(), BB,
20950 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
20951 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20953 // Add the true and fallthrough blocks as its successors.
20954 if (CascadedCMOV) {
20955 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
20956 BB->addSuccessor(jcc1MBB);
20958 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
20959 // jump to the sinkMBB.
20960 jcc1MBB->addSuccessor(copy0MBB);
20961 jcc1MBB->addSuccessor(sinkMBB);
20963 BB->addSuccessor(copy0MBB);
20966 // The true block target of the first (or only) branch is always sinkMBB.
20967 BB->addSuccessor(sinkMBB);
20969 // Create the conditional branch instruction.
20970 unsigned Opc = X86::GetCondBranchFromCond(CC);
20971 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20973 if (CascadedCMOV) {
20974 unsigned Opc2 = X86::GetCondBranchFromCond(
20975 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
20976 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
20980 // %FalseValue = ...
20981 // # fallthrough to sinkMBB
20982 copy0MBB->addSuccessor(sinkMBB);
20985 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20987 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
20988 MachineBasicBlock::iterator MIItEnd =
20989 std::next(MachineBasicBlock::iterator(LastCMOV));
20990 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
20991 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
20992 MachineInstrBuilder MIB;
20994 // As we are creating the PHIs, we have to be careful if there is more than
20995 // one. Later CMOVs may reference the results of earlier CMOVs, but later
20996 // PHIs have to reference the individual true/false inputs from earlier PHIs.
20997 // That also means that PHI construction must work forward from earlier to
20998 // later, and that the code must maintain a mapping from earlier PHI's
20999 // destination registers, and the registers that went into the PHI.
21001 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21002 unsigned DestReg = MIIt->getOperand(0).getReg();
21003 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21004 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21006 // If this CMOV we are generating is the opposite condition from
21007 // the jump we generated, then we have to swap the operands for the
21008 // PHI that is going to be generated.
21009 if (MIIt->getOperand(3).getImm() == OppCC)
21010 std::swap(Op1Reg, Op2Reg);
21012 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21013 Op1Reg = RegRewriteTable[Op1Reg].first;
21015 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21016 Op2Reg = RegRewriteTable[Op2Reg].second;
21018 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21019 TII->get(X86::PHI), DestReg)
21020 .addReg(Op1Reg).addMBB(copy0MBB)
21021 .addReg(Op2Reg).addMBB(thisMBB);
21023 // Add this PHI to the rewrite table.
21024 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21027 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21028 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21029 if (CascadedCMOV) {
21030 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21031 // Copy the PHI result to the register defined by the second CMOV.
21032 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21033 DL, TII->get(TargetOpcode::COPY),
21034 CascadedCMOV->getOperand(0).getReg())
21035 .addReg(MI->getOperand(0).getReg());
21036 CascadedCMOV->eraseFromParent();
21039 // Now remove the CMOV(s).
21040 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21041 (MIIt++)->eraseFromParent();
21046 MachineBasicBlock *
21047 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21048 MachineBasicBlock *BB) const {
21049 // Combine the following atomic floating-point modification pattern:
21050 // a.store(reg OP a.load(acquire), release)
21051 // Transform them into:
21052 // OPss (%gpr), %xmm
21053 // movss %xmm, (%gpr)
21054 // Or sd equivalent for 64-bit operations.
21056 switch (MI->getOpcode()) {
21057 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21058 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21059 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21061 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21062 DebugLoc DL = MI->getDebugLoc();
21063 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21064 unsigned MSrc = MI->getOperand(0).getReg();
21065 unsigned VSrc = MI->getOperand(5).getReg();
21066 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21067 .addReg(/*Base=*/MSrc)
21068 .addImm(/*Scale=*/1)
21069 .addReg(/*Index=*/0)
21072 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21073 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21075 .addReg(/*Base=*/MSrc)
21076 .addImm(/*Scale=*/1)
21077 .addReg(/*Index=*/0)
21078 .addImm(/*Disp=*/0)
21079 .addReg(/*Segment=*/0);
21080 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21081 MI->eraseFromParent(); // The pseudo instruction is gone now.
21085 MachineBasicBlock *
21086 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21087 MachineBasicBlock *BB) const {
21088 MachineFunction *MF = BB->getParent();
21089 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21090 DebugLoc DL = MI->getDebugLoc();
21091 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21093 assert(MF->shouldSplitStack());
21095 const bool Is64Bit = Subtarget->is64Bit();
21096 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21098 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21099 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21102 // ... [Till the alloca]
21103 // If stacklet is not large enough, jump to mallocMBB
21106 // Allocate by subtracting from RSP
21107 // Jump to continueMBB
21110 // Allocate by call to runtime
21114 // [rest of original BB]
21117 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21118 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21119 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21121 MachineRegisterInfo &MRI = MF->getRegInfo();
21122 const TargetRegisterClass *AddrRegClass =
21123 getRegClassFor(getPointerTy(MF->getDataLayout()));
21125 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21126 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21127 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21128 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21129 sizeVReg = MI->getOperand(1).getReg(),
21130 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21132 MachineFunction::iterator MBBIter = BB;
21135 MF->insert(MBBIter, bumpMBB);
21136 MF->insert(MBBIter, mallocMBB);
21137 MF->insert(MBBIter, continueMBB);
21139 continueMBB->splice(continueMBB->begin(), BB,
21140 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21141 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21143 // Add code to the main basic block to check if the stack limit has been hit,
21144 // and if so, jump to mallocMBB otherwise to bumpMBB.
21145 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21146 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21147 .addReg(tmpSPVReg).addReg(sizeVReg);
21148 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21149 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21150 .addReg(SPLimitVReg);
21151 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21153 // bumpMBB simply decreases the stack pointer, since we know the current
21154 // stacklet has enough space.
21155 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21156 .addReg(SPLimitVReg);
21157 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21158 .addReg(SPLimitVReg);
21159 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21161 // Calls into a routine in libgcc to allocate more space from the heap.
21162 const uint32_t *RegMask =
21163 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21165 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21167 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21168 .addExternalSymbol("__morestack_allocate_stack_space")
21169 .addRegMask(RegMask)
21170 .addReg(X86::RDI, RegState::Implicit)
21171 .addReg(X86::RAX, RegState::ImplicitDefine);
21172 } else if (Is64Bit) {
21173 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21175 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21176 .addExternalSymbol("__morestack_allocate_stack_space")
21177 .addRegMask(RegMask)
21178 .addReg(X86::EDI, RegState::Implicit)
21179 .addReg(X86::EAX, RegState::ImplicitDefine);
21181 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21183 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21184 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21185 .addExternalSymbol("__morestack_allocate_stack_space")
21186 .addRegMask(RegMask)
21187 .addReg(X86::EAX, RegState::ImplicitDefine);
21191 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21194 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21195 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21196 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21198 // Set up the CFG correctly.
21199 BB->addSuccessor(bumpMBB);
21200 BB->addSuccessor(mallocMBB);
21201 mallocMBB->addSuccessor(continueMBB);
21202 bumpMBB->addSuccessor(continueMBB);
21204 // Take care of the PHI nodes.
21205 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21206 MI->getOperand(0).getReg())
21207 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21208 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21210 // Delete the original pseudo instruction.
21211 MI->eraseFromParent();
21214 return continueMBB;
21217 MachineBasicBlock *
21218 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21219 MachineBasicBlock *BB) const {
21220 DebugLoc DL = MI->getDebugLoc();
21222 assert(!Subtarget->isTargetMachO());
21224 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21227 MI->eraseFromParent(); // The pseudo instruction is gone now.
21231 MachineBasicBlock *
21232 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21233 MachineBasicBlock *BB) const {
21234 // This is pretty easy. We're taking the value that we received from
21235 // our load from the relocation, sticking it in either RDI (x86-64)
21236 // or EAX and doing an indirect call. The return value will then
21237 // be in the normal return register.
21238 MachineFunction *F = BB->getParent();
21239 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21240 DebugLoc DL = MI->getDebugLoc();
21242 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21243 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21245 // Get a register mask for the lowered call.
21246 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21247 // proper register mask.
21248 const uint32_t *RegMask =
21249 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21250 if (Subtarget->is64Bit()) {
21251 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21252 TII->get(X86::MOV64rm), X86::RDI)
21254 .addImm(0).addReg(0)
21255 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21256 MI->getOperand(3).getTargetFlags())
21258 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21259 addDirectMem(MIB, X86::RDI);
21260 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21261 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21262 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21263 TII->get(X86::MOV32rm), X86::EAX)
21265 .addImm(0).addReg(0)
21266 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21267 MI->getOperand(3).getTargetFlags())
21269 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21270 addDirectMem(MIB, X86::EAX);
21271 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21273 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21274 TII->get(X86::MOV32rm), X86::EAX)
21275 .addReg(TII->getGlobalBaseReg(F))
21276 .addImm(0).addReg(0)
21277 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21278 MI->getOperand(3).getTargetFlags())
21280 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21281 addDirectMem(MIB, X86::EAX);
21282 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21285 MI->eraseFromParent(); // The pseudo instruction is gone now.
21289 MachineBasicBlock *
21290 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21291 MachineBasicBlock *MBB) const {
21292 DebugLoc DL = MI->getDebugLoc();
21293 MachineFunction *MF = MBB->getParent();
21294 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21295 MachineRegisterInfo &MRI = MF->getRegInfo();
21297 const BasicBlock *BB = MBB->getBasicBlock();
21298 MachineFunction::iterator I = MBB;
21301 // Memory Reference
21302 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21303 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21306 unsigned MemOpndSlot = 0;
21308 unsigned CurOp = 0;
21310 DstReg = MI->getOperand(CurOp++).getReg();
21311 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21312 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21313 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21314 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21316 MemOpndSlot = CurOp;
21318 MVT PVT = getPointerTy(MF->getDataLayout());
21319 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21320 "Invalid Pointer Size!");
21322 // For v = setjmp(buf), we generate
21325 // buf[LabelOffset] = restoreMBB
21326 // SjLjSetup restoreMBB
21332 // v = phi(main, restore)
21335 // if base pointer being used, load it from frame
21338 MachineBasicBlock *thisMBB = MBB;
21339 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21340 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21341 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21342 MF->insert(I, mainMBB);
21343 MF->insert(I, sinkMBB);
21344 MF->push_back(restoreMBB);
21346 MachineInstrBuilder MIB;
21348 // Transfer the remainder of BB and its successor edges to sinkMBB.
21349 sinkMBB->splice(sinkMBB->begin(), MBB,
21350 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21351 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21354 unsigned PtrStoreOpc = 0;
21355 unsigned LabelReg = 0;
21356 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21357 Reloc::Model RM = MF->getTarget().getRelocationModel();
21358 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21359 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21361 // Prepare IP either in reg or imm.
21362 if (!UseImmLabel) {
21363 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21364 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21365 LabelReg = MRI.createVirtualRegister(PtrRC);
21366 if (Subtarget->is64Bit()) {
21367 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21371 .addMBB(restoreMBB)
21374 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21375 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21376 .addReg(XII->getGlobalBaseReg(MF))
21379 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21383 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21385 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21386 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21387 if (i == X86::AddrDisp)
21388 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21390 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21393 MIB.addReg(LabelReg);
21395 MIB.addMBB(restoreMBB);
21396 MIB.setMemRefs(MMOBegin, MMOEnd);
21398 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21399 .addMBB(restoreMBB);
21401 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21402 MIB.addRegMask(RegInfo->getNoPreservedMask());
21403 thisMBB->addSuccessor(mainMBB);
21404 thisMBB->addSuccessor(restoreMBB);
21408 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21409 mainMBB->addSuccessor(sinkMBB);
21412 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21413 TII->get(X86::PHI), DstReg)
21414 .addReg(mainDstReg).addMBB(mainMBB)
21415 .addReg(restoreDstReg).addMBB(restoreMBB);
21418 if (RegInfo->hasBasePointer(*MF)) {
21419 const bool Uses64BitFramePtr =
21420 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21421 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21422 X86FI->setRestoreBasePointer(MF);
21423 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21424 unsigned BasePtr = RegInfo->getBaseRegister();
21425 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21426 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21427 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21428 .setMIFlag(MachineInstr::FrameSetup);
21430 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21431 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21432 restoreMBB->addSuccessor(sinkMBB);
21434 MI->eraseFromParent();
21438 MachineBasicBlock *
21439 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21440 MachineBasicBlock *MBB) const {
21441 DebugLoc DL = MI->getDebugLoc();
21442 MachineFunction *MF = MBB->getParent();
21443 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21444 MachineRegisterInfo &MRI = MF->getRegInfo();
21446 // Memory Reference
21447 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21448 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21450 MVT PVT = getPointerTy(MF->getDataLayout());
21451 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21452 "Invalid Pointer Size!");
21454 const TargetRegisterClass *RC =
21455 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21456 unsigned Tmp = MRI.createVirtualRegister(RC);
21457 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21458 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21459 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21460 unsigned SP = RegInfo->getStackRegister();
21462 MachineInstrBuilder MIB;
21464 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21465 const int64_t SPOffset = 2 * PVT.getStoreSize();
21467 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21468 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21471 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21472 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21473 MIB.addOperand(MI->getOperand(i));
21474 MIB.setMemRefs(MMOBegin, MMOEnd);
21476 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21477 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21478 if (i == X86::AddrDisp)
21479 MIB.addDisp(MI->getOperand(i), LabelOffset);
21481 MIB.addOperand(MI->getOperand(i));
21483 MIB.setMemRefs(MMOBegin, MMOEnd);
21485 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21486 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21487 if (i == X86::AddrDisp)
21488 MIB.addDisp(MI->getOperand(i), SPOffset);
21490 MIB.addOperand(MI->getOperand(i));
21492 MIB.setMemRefs(MMOBegin, MMOEnd);
21494 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21496 MI->eraseFromParent();
21500 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21501 // accumulator loops. Writing back to the accumulator allows the coalescer
21502 // to remove extra copies in the loop.
21503 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21504 MachineBasicBlock *
21505 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21506 MachineBasicBlock *MBB) const {
21507 MachineOperand &AddendOp = MI->getOperand(3);
21509 // Bail out early if the addend isn't a register - we can't switch these.
21510 if (!AddendOp.isReg())
21513 MachineFunction &MF = *MBB->getParent();
21514 MachineRegisterInfo &MRI = MF.getRegInfo();
21516 // Check whether the addend is defined by a PHI:
21517 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21518 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21519 if (!AddendDef.isPHI())
21522 // Look for the following pattern:
21524 // %addend = phi [%entry, 0], [%loop, %result]
21526 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21530 // %addend = phi [%entry, 0], [%loop, %result]
21532 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21534 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21535 assert(AddendDef.getOperand(i).isReg());
21536 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21537 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21538 if (&PHISrcInst == MI) {
21539 // Found a matching instruction.
21540 unsigned NewFMAOpc = 0;
21541 switch (MI->getOpcode()) {
21542 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21543 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21544 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21545 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21546 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21547 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21548 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21549 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21550 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21551 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21552 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21553 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21554 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21555 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21556 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21557 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21558 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21559 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21560 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21561 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21563 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21564 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21565 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21566 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21567 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21568 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21569 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21570 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21571 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21572 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21573 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21574 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21575 default: llvm_unreachable("Unrecognized FMA variant.");
21578 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21579 MachineInstrBuilder MIB =
21580 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21581 .addOperand(MI->getOperand(0))
21582 .addOperand(MI->getOperand(3))
21583 .addOperand(MI->getOperand(2))
21584 .addOperand(MI->getOperand(1));
21585 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21586 MI->eraseFromParent();
21593 MachineBasicBlock *
21594 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21595 MachineBasicBlock *BB) const {
21596 switch (MI->getOpcode()) {
21597 default: llvm_unreachable("Unexpected instr type to insert");
21598 case X86::TAILJMPd64:
21599 case X86::TAILJMPr64:
21600 case X86::TAILJMPm64:
21601 case X86::TAILJMPd64_REX:
21602 case X86::TAILJMPr64_REX:
21603 case X86::TAILJMPm64_REX:
21604 llvm_unreachable("TAILJMP64 would not be touched here.");
21605 case X86::TCRETURNdi64:
21606 case X86::TCRETURNri64:
21607 case X86::TCRETURNmi64:
21609 case X86::WIN_ALLOCA:
21610 return EmitLoweredWinAlloca(MI, BB);
21611 case X86::SEG_ALLOCA_32:
21612 case X86::SEG_ALLOCA_64:
21613 return EmitLoweredSegAlloca(MI, BB);
21614 case X86::TLSCall_32:
21615 case X86::TLSCall_64:
21616 return EmitLoweredTLSCall(MI, BB);
21617 case X86::CMOV_FR32:
21618 case X86::CMOV_FR64:
21619 case X86::CMOV_GR8:
21620 case X86::CMOV_GR16:
21621 case X86::CMOV_GR32:
21622 case X86::CMOV_RFP32:
21623 case X86::CMOV_RFP64:
21624 case X86::CMOV_RFP80:
21625 case X86::CMOV_V2F64:
21626 case X86::CMOV_V2I64:
21627 case X86::CMOV_V4F32:
21628 case X86::CMOV_V4F64:
21629 case X86::CMOV_V4I64:
21630 case X86::CMOV_V16F32:
21631 case X86::CMOV_V8F32:
21632 case X86::CMOV_V8F64:
21633 case X86::CMOV_V8I64:
21634 case X86::CMOV_V8I1:
21635 case X86::CMOV_V16I1:
21636 case X86::CMOV_V32I1:
21637 case X86::CMOV_V64I1:
21638 return EmitLoweredSelect(MI, BB);
21640 case X86::RELEASE_FADD32mr:
21641 case X86::RELEASE_FADD64mr:
21642 return EmitLoweredAtomicFP(MI, BB);
21644 case X86::FP32_TO_INT16_IN_MEM:
21645 case X86::FP32_TO_INT32_IN_MEM:
21646 case X86::FP32_TO_INT64_IN_MEM:
21647 case X86::FP64_TO_INT16_IN_MEM:
21648 case X86::FP64_TO_INT32_IN_MEM:
21649 case X86::FP64_TO_INT64_IN_MEM:
21650 case X86::FP80_TO_INT16_IN_MEM:
21651 case X86::FP80_TO_INT32_IN_MEM:
21652 case X86::FP80_TO_INT64_IN_MEM: {
21653 MachineFunction *F = BB->getParent();
21654 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21655 DebugLoc DL = MI->getDebugLoc();
21657 // Change the floating point control register to use "round towards zero"
21658 // mode when truncating to an integer value.
21659 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21660 addFrameReference(BuildMI(*BB, MI, DL,
21661 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21663 // Load the old value of the high byte of the control word...
21665 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21666 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21669 // Set the high part to be round to zero...
21670 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21673 // Reload the modified control word now...
21674 addFrameReference(BuildMI(*BB, MI, DL,
21675 TII->get(X86::FLDCW16m)), CWFrameIdx);
21677 // Restore the memory image of control word to original value
21678 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21681 // Get the X86 opcode to use.
21683 switch (MI->getOpcode()) {
21684 default: llvm_unreachable("illegal opcode!");
21685 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21686 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21687 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21688 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21689 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21690 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21691 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21692 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21693 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21697 MachineOperand &Op = MI->getOperand(0);
21699 AM.BaseType = X86AddressMode::RegBase;
21700 AM.Base.Reg = Op.getReg();
21702 AM.BaseType = X86AddressMode::FrameIndexBase;
21703 AM.Base.FrameIndex = Op.getIndex();
21705 Op = MI->getOperand(1);
21707 AM.Scale = Op.getImm();
21708 Op = MI->getOperand(2);
21710 AM.IndexReg = Op.getImm();
21711 Op = MI->getOperand(3);
21712 if (Op.isGlobal()) {
21713 AM.GV = Op.getGlobal();
21715 AM.Disp = Op.getImm();
21717 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21718 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21720 // Reload the original control word now.
21721 addFrameReference(BuildMI(*BB, MI, DL,
21722 TII->get(X86::FLDCW16m)), CWFrameIdx);
21724 MI->eraseFromParent(); // The pseudo instruction is gone now.
21727 // String/text processing lowering.
21728 case X86::PCMPISTRM128REG:
21729 case X86::VPCMPISTRM128REG:
21730 case X86::PCMPISTRM128MEM:
21731 case X86::VPCMPISTRM128MEM:
21732 case X86::PCMPESTRM128REG:
21733 case X86::VPCMPESTRM128REG:
21734 case X86::PCMPESTRM128MEM:
21735 case X86::VPCMPESTRM128MEM:
21736 assert(Subtarget->hasSSE42() &&
21737 "Target must have SSE4.2 or AVX features enabled");
21738 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21740 // String/text processing lowering.
21741 case X86::PCMPISTRIREG:
21742 case X86::VPCMPISTRIREG:
21743 case X86::PCMPISTRIMEM:
21744 case X86::VPCMPISTRIMEM:
21745 case X86::PCMPESTRIREG:
21746 case X86::VPCMPESTRIREG:
21747 case X86::PCMPESTRIMEM:
21748 case X86::VPCMPESTRIMEM:
21749 assert(Subtarget->hasSSE42() &&
21750 "Target must have SSE4.2 or AVX features enabled");
21751 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21753 // Thread synchronization.
21755 return EmitMonitor(MI, BB, Subtarget);
21759 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21761 case X86::VASTART_SAVE_XMM_REGS:
21762 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21764 case X86::VAARG_64:
21765 return EmitVAARG64WithCustomInserter(MI, BB);
21767 case X86::EH_SjLj_SetJmp32:
21768 case X86::EH_SjLj_SetJmp64:
21769 return emitEHSjLjSetJmp(MI, BB);
21771 case X86::EH_SjLj_LongJmp32:
21772 case X86::EH_SjLj_LongJmp64:
21773 return emitEHSjLjLongJmp(MI, BB);
21775 case TargetOpcode::STATEPOINT:
21776 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21777 // this point in the process. We diverge later.
21778 return emitPatchPoint(MI, BB);
21780 case TargetOpcode::STACKMAP:
21781 case TargetOpcode::PATCHPOINT:
21782 return emitPatchPoint(MI, BB);
21784 case X86::VFMADDPDr213r:
21785 case X86::VFMADDPSr213r:
21786 case X86::VFMADDSDr213r:
21787 case X86::VFMADDSSr213r:
21788 case X86::VFMSUBPDr213r:
21789 case X86::VFMSUBPSr213r:
21790 case X86::VFMSUBSDr213r:
21791 case X86::VFMSUBSSr213r:
21792 case X86::VFNMADDPDr213r:
21793 case X86::VFNMADDPSr213r:
21794 case X86::VFNMADDSDr213r:
21795 case X86::VFNMADDSSr213r:
21796 case X86::VFNMSUBPDr213r:
21797 case X86::VFNMSUBPSr213r:
21798 case X86::VFNMSUBSDr213r:
21799 case X86::VFNMSUBSSr213r:
21800 case X86::VFMADDSUBPDr213r:
21801 case X86::VFMADDSUBPSr213r:
21802 case X86::VFMSUBADDPDr213r:
21803 case X86::VFMSUBADDPSr213r:
21804 case X86::VFMADDPDr213rY:
21805 case X86::VFMADDPSr213rY:
21806 case X86::VFMSUBPDr213rY:
21807 case X86::VFMSUBPSr213rY:
21808 case X86::VFNMADDPDr213rY:
21809 case X86::VFNMADDPSr213rY:
21810 case X86::VFNMSUBPDr213rY:
21811 case X86::VFNMSUBPSr213rY:
21812 case X86::VFMADDSUBPDr213rY:
21813 case X86::VFMADDSUBPSr213rY:
21814 case X86::VFMSUBADDPDr213rY:
21815 case X86::VFMSUBADDPSr213rY:
21816 return emitFMA3Instr(MI, BB);
21820 //===----------------------------------------------------------------------===//
21821 // X86 Optimization Hooks
21822 //===----------------------------------------------------------------------===//
21824 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21827 const SelectionDAG &DAG,
21828 unsigned Depth) const {
21829 unsigned BitWidth = KnownZero.getBitWidth();
21830 unsigned Opc = Op.getOpcode();
21831 assert((Opc >= ISD::BUILTIN_OP_END ||
21832 Opc == ISD::INTRINSIC_WO_CHAIN ||
21833 Opc == ISD::INTRINSIC_W_CHAIN ||
21834 Opc == ISD::INTRINSIC_VOID) &&
21835 "Should use MaskedValueIsZero if you don't know whether Op"
21836 " is a target node!");
21838 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21852 // These nodes' second result is a boolean.
21853 if (Op.getResNo() == 0)
21856 case X86ISD::SETCC:
21857 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21859 case ISD::INTRINSIC_WO_CHAIN: {
21860 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21861 unsigned NumLoBits = 0;
21864 case Intrinsic::x86_sse_movmsk_ps:
21865 case Intrinsic::x86_avx_movmsk_ps_256:
21866 case Intrinsic::x86_sse2_movmsk_pd:
21867 case Intrinsic::x86_avx_movmsk_pd_256:
21868 case Intrinsic::x86_mmx_pmovmskb:
21869 case Intrinsic::x86_sse2_pmovmskb_128:
21870 case Intrinsic::x86_avx2_pmovmskb: {
21871 // High bits of movmskp{s|d}, pmovmskb are known zero.
21873 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21874 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21875 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21876 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21877 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21878 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21879 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21880 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21882 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21891 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21893 const SelectionDAG &,
21894 unsigned Depth) const {
21895 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21896 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21897 return Op.getValueType().getScalarType().getSizeInBits();
21903 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21904 /// node is a GlobalAddress + offset.
21905 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21906 const GlobalValue* &GA,
21907 int64_t &Offset) const {
21908 if (N->getOpcode() == X86ISD::Wrapper) {
21909 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21910 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21911 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21915 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21918 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21919 /// same as extracting the high 128-bit part of 256-bit vector and then
21920 /// inserting the result into the low part of a new 256-bit vector
21921 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21922 EVT VT = SVOp->getValueType(0);
21923 unsigned NumElems = VT.getVectorNumElements();
21925 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21926 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21927 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21928 SVOp->getMaskElt(j) >= 0)
21934 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21935 /// same as extracting the low 128-bit part of 256-bit vector and then
21936 /// inserting the result into the high part of a new 256-bit vector
21937 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21938 EVT VT = SVOp->getValueType(0);
21939 unsigned NumElems = VT.getVectorNumElements();
21941 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21942 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21943 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21944 SVOp->getMaskElt(j) >= 0)
21950 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21951 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21952 TargetLowering::DAGCombinerInfo &DCI,
21953 const X86Subtarget* Subtarget) {
21955 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21956 SDValue V1 = SVOp->getOperand(0);
21957 SDValue V2 = SVOp->getOperand(1);
21958 EVT VT = SVOp->getValueType(0);
21959 unsigned NumElems = VT.getVectorNumElements();
21961 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21962 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21966 // V UNDEF BUILD_VECTOR UNDEF
21968 // CONCAT_VECTOR CONCAT_VECTOR
21971 // RESULT: V + zero extended
21973 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21974 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21975 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21978 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21981 // To match the shuffle mask, the first half of the mask should
21982 // be exactly the first vector, and all the rest a splat with the
21983 // first element of the second one.
21984 for (unsigned i = 0; i != NumElems/2; ++i)
21985 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21986 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21989 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21990 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21991 if (Ld->hasNUsesOfValue(1, 0)) {
21992 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21993 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21995 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21997 Ld->getPointerInfo(),
21998 Ld->getAlignment(),
21999 false/*isVolatile*/, true/*ReadMem*/,
22000 false/*WriteMem*/);
22002 // Make sure the newly-created LOAD is in the same position as Ld in
22003 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22004 // and update uses of Ld's output chain to use the TokenFactor.
22005 if (Ld->hasAnyUseOfValue(1)) {
22006 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22007 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22008 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22009 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22010 SDValue(ResNode.getNode(), 1));
22013 return DAG.getBitcast(VT, ResNode);
22017 // Emit a zeroed vector and insert the desired subvector on its
22019 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22020 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22021 return DCI.CombineTo(N, InsV);
22024 //===--------------------------------------------------------------------===//
22025 // Combine some shuffles into subvector extracts and inserts:
22028 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22029 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22030 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22031 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22032 return DCI.CombineTo(N, InsV);
22035 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22036 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22037 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22038 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22039 return DCI.CombineTo(N, InsV);
22045 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22048 /// This is the leaf of the recursive combinine below. When we have found some
22049 /// chain of single-use x86 shuffle instructions and accumulated the combined
22050 /// shuffle mask represented by them, this will try to pattern match that mask
22051 /// into either a single instruction if there is a special purpose instruction
22052 /// for this operation, or into a PSHUFB instruction which is a fully general
22053 /// instruction but should only be used to replace chains over a certain depth.
22054 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22055 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22056 TargetLowering::DAGCombinerInfo &DCI,
22057 const X86Subtarget *Subtarget) {
22058 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22060 // Find the operand that enters the chain. Note that multiple uses are OK
22061 // here, we're not going to remove the operand we find.
22062 SDValue Input = Op.getOperand(0);
22063 while (Input.getOpcode() == ISD::BITCAST)
22064 Input = Input.getOperand(0);
22066 MVT VT = Input.getSimpleValueType();
22067 MVT RootVT = Root.getSimpleValueType();
22070 if (Mask.size() == 1) {
22071 int Index = Mask[0];
22072 assert((Index >= 0 || Index == SM_SentinelUndef ||
22073 Index == SM_SentinelZero) &&
22074 "Invalid shuffle index found!");
22076 // We may end up with an accumulated mask of size 1 as a result of
22077 // widening of shuffle operands (see function canWidenShuffleElements).
22078 // If the only shuffle index is equal to SM_SentinelZero then propagate
22079 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22080 // mask, and therefore the entire chain of shuffles can be folded away.
22081 if (Index == SM_SentinelZero)
22082 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22084 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22089 // Use the float domain if the operand type is a floating point type.
22090 bool FloatDomain = VT.isFloatingPoint();
22092 // For floating point shuffles, we don't have free copies in the shuffle
22093 // instructions or the ability to load as part of the instruction, so
22094 // canonicalize their shuffles to UNPCK or MOV variants.
22096 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22097 // vectors because it can have a load folded into it that UNPCK cannot. This
22098 // doesn't preclude something switching to the shorter encoding post-RA.
22100 // FIXME: Should teach these routines about AVX vector widths.
22101 if (FloatDomain && VT.getSizeInBits() == 128) {
22102 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22103 bool Lo = Mask.equals({0, 0});
22106 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22107 // is no slower than UNPCKLPD but has the option to fold the input operand
22108 // into even an unaligned memory load.
22109 if (Lo && Subtarget->hasSSE3()) {
22110 Shuffle = X86ISD::MOVDDUP;
22111 ShuffleVT = MVT::v2f64;
22113 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22114 // than the UNPCK variants.
22115 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22116 ShuffleVT = MVT::v4f32;
22118 if (Depth == 1 && Root->getOpcode() == Shuffle)
22119 return false; // Nothing to do!
22120 Op = DAG.getBitcast(ShuffleVT, Input);
22121 DCI.AddToWorklist(Op.getNode());
22122 if (Shuffle == X86ISD::MOVDDUP)
22123 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22125 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22126 DCI.AddToWorklist(Op.getNode());
22127 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22131 if (Subtarget->hasSSE3() &&
22132 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22133 bool Lo = Mask.equals({0, 0, 2, 2});
22134 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22135 MVT ShuffleVT = MVT::v4f32;
22136 if (Depth == 1 && Root->getOpcode() == Shuffle)
22137 return false; // Nothing to do!
22138 Op = DAG.getBitcast(ShuffleVT, Input);
22139 DCI.AddToWorklist(Op.getNode());
22140 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22141 DCI.AddToWorklist(Op.getNode());
22142 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22146 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22147 bool Lo = Mask.equals({0, 0, 1, 1});
22148 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22149 MVT ShuffleVT = MVT::v4f32;
22150 if (Depth == 1 && Root->getOpcode() == Shuffle)
22151 return false; // Nothing to do!
22152 Op = DAG.getBitcast(ShuffleVT, Input);
22153 DCI.AddToWorklist(Op.getNode());
22154 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22155 DCI.AddToWorklist(Op.getNode());
22156 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22162 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22163 // variants as none of these have single-instruction variants that are
22164 // superior to the UNPCK formulation.
22165 if (!FloatDomain && VT.getSizeInBits() == 128 &&
22166 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22167 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22168 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22170 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22171 bool Lo = Mask[0] == 0;
22172 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22173 if (Depth == 1 && Root->getOpcode() == Shuffle)
22174 return false; // Nothing to do!
22176 switch (Mask.size()) {
22178 ShuffleVT = MVT::v8i16;
22181 ShuffleVT = MVT::v16i8;
22184 llvm_unreachable("Impossible mask size!");
22186 Op = DAG.getBitcast(ShuffleVT, Input);
22187 DCI.AddToWorklist(Op.getNode());
22188 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22189 DCI.AddToWorklist(Op.getNode());
22190 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22195 // Don't try to re-form single instruction chains under any circumstances now
22196 // that we've done encoding canonicalization for them.
22200 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22201 // can replace them with a single PSHUFB instruction profitably. Intel's
22202 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22203 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22204 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22205 SmallVector<SDValue, 16> PSHUFBMask;
22206 int NumBytes = VT.getSizeInBits() / 8;
22207 int Ratio = NumBytes / Mask.size();
22208 for (int i = 0; i < NumBytes; ++i) {
22209 if (Mask[i / Ratio] == SM_SentinelUndef) {
22210 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22213 int M = Mask[i / Ratio] != SM_SentinelZero
22214 ? Ratio * Mask[i / Ratio] + i % Ratio
22216 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22218 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22219 Op = DAG.getBitcast(ByteVT, Input);
22220 DCI.AddToWorklist(Op.getNode());
22221 SDValue PSHUFBMaskOp =
22222 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22223 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22224 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22225 DCI.AddToWorklist(Op.getNode());
22226 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22231 // Failed to find any combines.
22235 /// \brief Fully generic combining of x86 shuffle instructions.
22237 /// This should be the last combine run over the x86 shuffle instructions. Once
22238 /// they have been fully optimized, this will recursively consider all chains
22239 /// of single-use shuffle instructions, build a generic model of the cumulative
22240 /// shuffle operation, and check for simpler instructions which implement this
22241 /// operation. We use this primarily for two purposes:
22243 /// 1) Collapse generic shuffles to specialized single instructions when
22244 /// equivalent. In most cases, this is just an encoding size win, but
22245 /// sometimes we will collapse multiple generic shuffles into a single
22246 /// special-purpose shuffle.
22247 /// 2) Look for sequences of shuffle instructions with 3 or more total
22248 /// instructions, and replace them with the slightly more expensive SSSE3
22249 /// PSHUFB instruction if available. We do this as the last combining step
22250 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22251 /// a suitable short sequence of other instructions. The PHUFB will either
22252 /// use a register or have to read from memory and so is slightly (but only
22253 /// slightly) more expensive than the other shuffle instructions.
22255 /// Because this is inherently a quadratic operation (for each shuffle in
22256 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22257 /// This should never be an issue in practice as the shuffle lowering doesn't
22258 /// produce sequences of more than 8 instructions.
22260 /// FIXME: We will currently miss some cases where the redundant shuffling
22261 /// would simplify under the threshold for PSHUFB formation because of
22262 /// combine-ordering. To fix this, we should do the redundant instruction
22263 /// combining in this recursive walk.
22264 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22265 ArrayRef<int> RootMask,
22266 int Depth, bool HasPSHUFB,
22268 TargetLowering::DAGCombinerInfo &DCI,
22269 const X86Subtarget *Subtarget) {
22270 // Bound the depth of our recursive combine because this is ultimately
22271 // quadratic in nature.
22275 // Directly rip through bitcasts to find the underlying operand.
22276 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22277 Op = Op.getOperand(0);
22279 MVT VT = Op.getSimpleValueType();
22280 if (!VT.isVector())
22281 return false; // Bail if we hit a non-vector.
22283 assert(Root.getSimpleValueType().isVector() &&
22284 "Shuffles operate on vector types!");
22285 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22286 "Can only combine shuffles of the same vector register size.");
22288 if (!isTargetShuffle(Op.getOpcode()))
22290 SmallVector<int, 16> OpMask;
22292 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22293 // We only can combine unary shuffles which we can decode the mask for.
22294 if (!HaveMask || !IsUnary)
22297 assert(VT.getVectorNumElements() == OpMask.size() &&
22298 "Different mask size from vector size!");
22299 assert(((RootMask.size() > OpMask.size() &&
22300 RootMask.size() % OpMask.size() == 0) ||
22301 (OpMask.size() > RootMask.size() &&
22302 OpMask.size() % RootMask.size() == 0) ||
22303 OpMask.size() == RootMask.size()) &&
22304 "The smaller number of elements must divide the larger.");
22305 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22306 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22307 assert(((RootRatio == 1 && OpRatio == 1) ||
22308 (RootRatio == 1) != (OpRatio == 1)) &&
22309 "Must not have a ratio for both incoming and op masks!");
22311 SmallVector<int, 16> Mask;
22312 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22314 // Merge this shuffle operation's mask into our accumulated mask. Note that
22315 // this shuffle's mask will be the first applied to the input, followed by the
22316 // root mask to get us all the way to the root value arrangement. The reason
22317 // for this order is that we are recursing up the operation chain.
22318 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22319 int RootIdx = i / RootRatio;
22320 if (RootMask[RootIdx] < 0) {
22321 // This is a zero or undef lane, we're done.
22322 Mask.push_back(RootMask[RootIdx]);
22326 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22327 int OpIdx = RootMaskedIdx / OpRatio;
22328 if (OpMask[OpIdx] < 0) {
22329 // The incoming lanes are zero or undef, it doesn't matter which ones we
22331 Mask.push_back(OpMask[OpIdx]);
22335 // Ok, we have non-zero lanes, map them through.
22336 Mask.push_back(OpMask[OpIdx] * OpRatio +
22337 RootMaskedIdx % OpRatio);
22340 // See if we can recurse into the operand to combine more things.
22341 switch (Op.getOpcode()) {
22342 case X86ISD::PSHUFB:
22344 case X86ISD::PSHUFD:
22345 case X86ISD::PSHUFHW:
22346 case X86ISD::PSHUFLW:
22347 if (Op.getOperand(0).hasOneUse() &&
22348 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22349 HasPSHUFB, DAG, DCI, Subtarget))
22353 case X86ISD::UNPCKL:
22354 case X86ISD::UNPCKH:
22355 assert(Op.getOperand(0) == Op.getOperand(1) &&
22356 "We only combine unary shuffles!");
22357 // We can't check for single use, we have to check that this shuffle is the
22359 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22360 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22361 HasPSHUFB, DAG, DCI, Subtarget))
22366 // Minor canonicalization of the accumulated shuffle mask to make it easier
22367 // to match below. All this does is detect masks with squential pairs of
22368 // elements, and shrink them to the half-width mask. It does this in a loop
22369 // so it will reduce the size of the mask to the minimal width mask which
22370 // performs an equivalent shuffle.
22371 SmallVector<int, 16> WidenedMask;
22372 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22373 Mask = std::move(WidenedMask);
22374 WidenedMask.clear();
22377 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22381 /// \brief Get the PSHUF-style mask from PSHUF node.
22383 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22384 /// PSHUF-style masks that can be reused with such instructions.
22385 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22386 MVT VT = N.getSimpleValueType();
22387 SmallVector<int, 4> Mask;
22389 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22393 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22394 // matter. Check that the upper masks are repeats and remove them.
22395 if (VT.getSizeInBits() > 128) {
22396 int LaneElts = 128 / VT.getScalarSizeInBits();
22398 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22399 for (int j = 0; j < LaneElts; ++j)
22400 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22401 "Mask doesn't repeat in high 128-bit lanes!");
22403 Mask.resize(LaneElts);
22406 switch (N.getOpcode()) {
22407 case X86ISD::PSHUFD:
22409 case X86ISD::PSHUFLW:
22412 case X86ISD::PSHUFHW:
22413 Mask.erase(Mask.begin(), Mask.begin() + 4);
22414 for (int &M : Mask)
22418 llvm_unreachable("No valid shuffle instruction found!");
22422 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22424 /// We walk up the chain and look for a combinable shuffle, skipping over
22425 /// shuffles that we could hoist this shuffle's transformation past without
22426 /// altering anything.
22428 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22430 TargetLowering::DAGCombinerInfo &DCI) {
22431 assert(N.getOpcode() == X86ISD::PSHUFD &&
22432 "Called with something other than an x86 128-bit half shuffle!");
22435 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22436 // of the shuffles in the chain so that we can form a fresh chain to replace
22438 SmallVector<SDValue, 8> Chain;
22439 SDValue V = N.getOperand(0);
22440 for (; V.hasOneUse(); V = V.getOperand(0)) {
22441 switch (V.getOpcode()) {
22443 return SDValue(); // Nothing combined!
22446 // Skip bitcasts as we always know the type for the target specific
22450 case X86ISD::PSHUFD:
22451 // Found another dword shuffle.
22454 case X86ISD::PSHUFLW:
22455 // Check that the low words (being shuffled) are the identity in the
22456 // dword shuffle, and the high words are self-contained.
22457 if (Mask[0] != 0 || Mask[1] != 1 ||
22458 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22461 Chain.push_back(V);
22464 case X86ISD::PSHUFHW:
22465 // Check that the high words (being shuffled) are the identity in the
22466 // dword shuffle, and the low words are self-contained.
22467 if (Mask[2] != 2 || Mask[3] != 3 ||
22468 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22471 Chain.push_back(V);
22474 case X86ISD::UNPCKL:
22475 case X86ISD::UNPCKH:
22476 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22477 // shuffle into a preceding word shuffle.
22478 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22479 V.getSimpleValueType().getScalarType() != MVT::i16)
22482 // Search for a half-shuffle which we can combine with.
22483 unsigned CombineOp =
22484 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22485 if (V.getOperand(0) != V.getOperand(1) ||
22486 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22488 Chain.push_back(V);
22489 V = V.getOperand(0);
22491 switch (V.getOpcode()) {
22493 return SDValue(); // Nothing to combine.
22495 case X86ISD::PSHUFLW:
22496 case X86ISD::PSHUFHW:
22497 if (V.getOpcode() == CombineOp)
22500 Chain.push_back(V);
22504 V = V.getOperand(0);
22508 } while (V.hasOneUse());
22511 // Break out of the loop if we break out of the switch.
22515 if (!V.hasOneUse())
22516 // We fell out of the loop without finding a viable combining instruction.
22519 // Merge this node's mask and our incoming mask.
22520 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22521 for (int &M : Mask)
22523 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22524 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22526 // Rebuild the chain around this new shuffle.
22527 while (!Chain.empty()) {
22528 SDValue W = Chain.pop_back_val();
22530 if (V.getValueType() != W.getOperand(0).getValueType())
22531 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22533 switch (W.getOpcode()) {
22535 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22537 case X86ISD::UNPCKL:
22538 case X86ISD::UNPCKH:
22539 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22542 case X86ISD::PSHUFD:
22543 case X86ISD::PSHUFLW:
22544 case X86ISD::PSHUFHW:
22545 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22549 if (V.getValueType() != N.getValueType())
22550 V = DAG.getBitcast(N.getValueType(), V);
22552 // Return the new chain to replace N.
22556 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22559 /// We walk up the chain, skipping shuffles of the other half and looking
22560 /// through shuffles which switch halves trying to find a shuffle of the same
22561 /// pair of dwords.
22562 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22564 TargetLowering::DAGCombinerInfo &DCI) {
22566 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22567 "Called with something other than an x86 128-bit half shuffle!");
22569 unsigned CombineOpcode = N.getOpcode();
22571 // Walk up a single-use chain looking for a combinable shuffle.
22572 SDValue V = N.getOperand(0);
22573 for (; V.hasOneUse(); V = V.getOperand(0)) {
22574 switch (V.getOpcode()) {
22576 return false; // Nothing combined!
22579 // Skip bitcasts as we always know the type for the target specific
22583 case X86ISD::PSHUFLW:
22584 case X86ISD::PSHUFHW:
22585 if (V.getOpcode() == CombineOpcode)
22588 // Other-half shuffles are no-ops.
22591 // Break out of the loop if we break out of the switch.
22595 if (!V.hasOneUse())
22596 // We fell out of the loop without finding a viable combining instruction.
22599 // Combine away the bottom node as its shuffle will be accumulated into
22600 // a preceding shuffle.
22601 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22603 // Record the old value.
22606 // Merge this node's mask and our incoming mask (adjusted to account for all
22607 // the pshufd instructions encountered).
22608 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22609 for (int &M : Mask)
22611 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22612 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22614 // Check that the shuffles didn't cancel each other out. If not, we need to
22615 // combine to the new one.
22617 // Replace the combinable shuffle with the combined one, updating all users
22618 // so that we re-evaluate the chain here.
22619 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22624 /// \brief Try to combine x86 target specific shuffles.
22625 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22626 TargetLowering::DAGCombinerInfo &DCI,
22627 const X86Subtarget *Subtarget) {
22629 MVT VT = N.getSimpleValueType();
22630 SmallVector<int, 4> Mask;
22632 switch (N.getOpcode()) {
22633 case X86ISD::PSHUFD:
22634 case X86ISD::PSHUFLW:
22635 case X86ISD::PSHUFHW:
22636 Mask = getPSHUFShuffleMask(N);
22637 assert(Mask.size() == 4);
22643 // Nuke no-op shuffles that show up after combining.
22644 if (isNoopShuffleMask(Mask))
22645 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22647 // Look for simplifications involving one or two shuffle instructions.
22648 SDValue V = N.getOperand(0);
22649 switch (N.getOpcode()) {
22652 case X86ISD::PSHUFLW:
22653 case X86ISD::PSHUFHW:
22654 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22656 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22657 return SDValue(); // We combined away this shuffle, so we're done.
22659 // See if this reduces to a PSHUFD which is no more expensive and can
22660 // combine with more operations. Note that it has to at least flip the
22661 // dwords as otherwise it would have been removed as a no-op.
22662 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22663 int DMask[] = {0, 1, 2, 3};
22664 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22665 DMask[DOffset + 0] = DOffset + 1;
22666 DMask[DOffset + 1] = DOffset + 0;
22667 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22668 V = DAG.getBitcast(DVT, V);
22669 DCI.AddToWorklist(V.getNode());
22670 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22671 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22672 DCI.AddToWorklist(V.getNode());
22673 return DAG.getBitcast(VT, V);
22676 // Look for shuffle patterns which can be implemented as a single unpack.
22677 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22678 // only works when we have a PSHUFD followed by two half-shuffles.
22679 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22680 (V.getOpcode() == X86ISD::PSHUFLW ||
22681 V.getOpcode() == X86ISD::PSHUFHW) &&
22682 V.getOpcode() != N.getOpcode() &&
22684 SDValue D = V.getOperand(0);
22685 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22686 D = D.getOperand(0);
22687 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22688 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22689 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22690 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22691 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22693 for (int i = 0; i < 4; ++i) {
22694 WordMask[i + NOffset] = Mask[i] + NOffset;
22695 WordMask[i + VOffset] = VMask[i] + VOffset;
22697 // Map the word mask through the DWord mask.
22699 for (int i = 0; i < 8; ++i)
22700 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22701 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22702 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22703 // We can replace all three shuffles with an unpack.
22704 V = DAG.getBitcast(VT, D.getOperand(0));
22705 DCI.AddToWorklist(V.getNode());
22706 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22715 case X86ISD::PSHUFD:
22716 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22725 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22727 /// We combine this directly on the abstract vector shuffle nodes so it is
22728 /// easier to generically match. We also insert dummy vector shuffle nodes for
22729 /// the operands which explicitly discard the lanes which are unused by this
22730 /// operation to try to flow through the rest of the combiner the fact that
22731 /// they're unused.
22732 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22734 EVT VT = N->getValueType(0);
22736 // We only handle target-independent shuffles.
22737 // FIXME: It would be easy and harmless to use the target shuffle mask
22738 // extraction tool to support more.
22739 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22742 auto *SVN = cast<ShuffleVectorSDNode>(N);
22743 ArrayRef<int> Mask = SVN->getMask();
22744 SDValue V1 = N->getOperand(0);
22745 SDValue V2 = N->getOperand(1);
22747 // We require the first shuffle operand to be the SUB node, and the second to
22748 // be the ADD node.
22749 // FIXME: We should support the commuted patterns.
22750 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22753 // If there are other uses of these operations we can't fold them.
22754 if (!V1->hasOneUse() || !V2->hasOneUse())
22757 // Ensure that both operations have the same operands. Note that we can
22758 // commute the FADD operands.
22759 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22760 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22761 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22764 // We're looking for blends between FADD and FSUB nodes. We insist on these
22765 // nodes being lined up in a specific expected pattern.
22766 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22767 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22768 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22771 // Only specific types are legal at this point, assert so we notice if and
22772 // when these change.
22773 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22774 VT == MVT::v4f64) &&
22775 "Unknown vector type encountered!");
22777 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22780 /// PerformShuffleCombine - Performs several different shuffle combines.
22781 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22782 TargetLowering::DAGCombinerInfo &DCI,
22783 const X86Subtarget *Subtarget) {
22785 SDValue N0 = N->getOperand(0);
22786 SDValue N1 = N->getOperand(1);
22787 EVT VT = N->getValueType(0);
22789 // Don't create instructions with illegal types after legalize types has run.
22790 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22791 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22794 // If we have legalized the vector types, look for blends of FADD and FSUB
22795 // nodes that we can fuse into an ADDSUB node.
22796 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22797 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22800 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22801 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22802 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22803 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22805 // During Type Legalization, when promoting illegal vector types,
22806 // the backend might introduce new shuffle dag nodes and bitcasts.
22808 // This code performs the following transformation:
22809 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22810 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22812 // We do this only if both the bitcast and the BINOP dag nodes have
22813 // one use. Also, perform this transformation only if the new binary
22814 // operation is legal. This is to avoid introducing dag nodes that
22815 // potentially need to be further expanded (or custom lowered) into a
22816 // less optimal sequence of dag nodes.
22817 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22818 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22819 N0.getOpcode() == ISD::BITCAST) {
22820 SDValue BC0 = N0.getOperand(0);
22821 EVT SVT = BC0.getValueType();
22822 unsigned Opcode = BC0.getOpcode();
22823 unsigned NumElts = VT.getVectorNumElements();
22825 if (BC0.hasOneUse() && SVT.isVector() &&
22826 SVT.getVectorNumElements() * 2 == NumElts &&
22827 TLI.isOperationLegal(Opcode, VT)) {
22828 bool CanFold = false;
22840 unsigned SVTNumElts = SVT.getVectorNumElements();
22841 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22842 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22843 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22844 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22845 CanFold = SVOp->getMaskElt(i) < 0;
22848 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22849 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22850 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22851 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22856 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22857 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22858 // consecutive, non-overlapping, and in the right order.
22859 SmallVector<SDValue, 16> Elts;
22860 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22861 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22863 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22866 if (isTargetShuffle(N->getOpcode())) {
22868 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22869 if (Shuffle.getNode())
22872 // Try recursively combining arbitrary sequences of x86 shuffle
22873 // instructions into higher-order shuffles. We do this after combining
22874 // specific PSHUF instruction sequences into their minimal form so that we
22875 // can evaluate how many specialized shuffle instructions are involved in
22876 // a particular chain.
22877 SmallVector<int, 1> NonceMask; // Just a placeholder.
22878 NonceMask.push_back(0);
22879 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22880 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22882 return SDValue(); // This routine will use CombineTo to replace N.
22888 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22889 /// specific shuffle of a load can be folded into a single element load.
22890 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22891 /// shuffles have been custom lowered so we need to handle those here.
22892 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22893 TargetLowering::DAGCombinerInfo &DCI) {
22894 if (DCI.isBeforeLegalizeOps())
22897 SDValue InVec = N->getOperand(0);
22898 SDValue EltNo = N->getOperand(1);
22900 if (!isa<ConstantSDNode>(EltNo))
22903 EVT OriginalVT = InVec.getValueType();
22905 if (InVec.getOpcode() == ISD::BITCAST) {
22906 // Don't duplicate a load with other uses.
22907 if (!InVec.hasOneUse())
22909 EVT BCVT = InVec.getOperand(0).getValueType();
22910 if (!BCVT.isVector() ||
22911 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22913 InVec = InVec.getOperand(0);
22916 EVT CurrentVT = InVec.getValueType();
22918 if (!isTargetShuffle(InVec.getOpcode()))
22921 // Don't duplicate a load with other uses.
22922 if (!InVec.hasOneUse())
22925 SmallVector<int, 16> ShuffleMask;
22927 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22928 ShuffleMask, UnaryShuffle))
22931 // Select the input vector, guarding against out of range extract vector.
22932 unsigned NumElems = CurrentVT.getVectorNumElements();
22933 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22934 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22935 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22936 : InVec.getOperand(1);
22938 // If inputs to shuffle are the same for both ops, then allow 2 uses
22939 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22940 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22942 if (LdNode.getOpcode() == ISD::BITCAST) {
22943 // Don't duplicate a load with other uses.
22944 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22947 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22948 LdNode = LdNode.getOperand(0);
22951 if (!ISD::isNormalLoad(LdNode.getNode()))
22954 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22956 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22959 EVT EltVT = N->getValueType(0);
22960 // If there's a bitcast before the shuffle, check if the load type and
22961 // alignment is valid.
22962 unsigned Align = LN0->getAlignment();
22963 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22964 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
22965 EltVT.getTypeForEVT(*DAG.getContext()));
22967 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22970 // All checks match so transform back to vector_shuffle so that DAG combiner
22971 // can finish the job
22974 // Create shuffle node taking into account the case that its a unary shuffle
22975 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22976 : InVec.getOperand(1);
22977 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22978 InVec.getOperand(0), Shuffle,
22980 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
22981 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22985 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
22986 /// special and don't usually play with other vector types, it's better to
22987 /// handle them early to be sure we emit efficient code by avoiding
22988 /// store-load conversions.
22989 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
22990 if (N->getValueType(0) != MVT::x86mmx ||
22991 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
22992 N->getOperand(0)->getValueType(0) != MVT::v2i32)
22995 SDValue V = N->getOperand(0);
22996 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
22997 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
22998 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
22999 N->getValueType(0), V.getOperand(0));
23004 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23005 /// generation and convert it from being a bunch of shuffles and extracts
23006 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23007 /// storing the value and loading scalars back, while for x64 we should
23008 /// use 64-bit extracts and shifts.
23009 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23010 TargetLowering::DAGCombinerInfo &DCI) {
23011 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23014 SDValue InputVector = N->getOperand(0);
23015 SDLoc dl(InputVector);
23016 // Detect mmx to i32 conversion through a v2i32 elt extract.
23017 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23018 N->getValueType(0) == MVT::i32 &&
23019 InputVector.getValueType() == MVT::v2i32) {
23021 // The bitcast source is a direct mmx result.
23022 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23023 if (MMXSrc.getValueType() == MVT::x86mmx)
23024 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23025 N->getValueType(0),
23026 InputVector.getNode()->getOperand(0));
23028 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23029 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23030 MMXSrc.getValueType() == MVT::i64) {
23031 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23032 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23033 MMXSrcOp.getValueType() == MVT::v1i64 &&
23034 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23035 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23036 N->getValueType(0), MMXSrcOp.getOperand(0));
23040 EVT VT = N->getValueType(0);
23042 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
23043 InputVector.getOpcode() == ISD::BITCAST &&
23044 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
23045 uint64_t ExtractedElt =
23046 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23047 uint64_t InputValue =
23048 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23049 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23050 return DAG.getConstant(Res, dl, MVT::i1);
23052 // Only operate on vectors of 4 elements, where the alternative shuffling
23053 // gets to be more expensive.
23054 if (InputVector.getValueType() != MVT::v4i32)
23057 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23058 // single use which is a sign-extend or zero-extend, and all elements are
23060 SmallVector<SDNode *, 4> Uses;
23061 unsigned ExtractedElements = 0;
23062 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23063 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23064 if (UI.getUse().getResNo() != InputVector.getResNo())
23067 SDNode *Extract = *UI;
23068 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23071 if (Extract->getValueType(0) != MVT::i32)
23073 if (!Extract->hasOneUse())
23075 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23076 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23078 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23081 // Record which element was extracted.
23082 ExtractedElements |=
23083 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23085 Uses.push_back(Extract);
23088 // If not all the elements were used, this may not be worthwhile.
23089 if (ExtractedElements != 15)
23092 // Ok, we've now decided to do the transformation.
23093 // If 64-bit shifts are legal, use the extract-shift sequence,
23094 // otherwise bounce the vector off the cache.
23095 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23098 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23099 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23100 auto &DL = DAG.getDataLayout();
23101 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23102 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23103 DAG.getConstant(0, dl, VecIdxTy));
23104 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23105 DAG.getConstant(1, dl, VecIdxTy));
23107 SDValue ShAmt = DAG.getConstant(
23108 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23109 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23110 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23111 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23112 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23113 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23114 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23116 // Store the value to a temporary stack slot.
23117 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23118 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23119 MachinePointerInfo(), false, false, 0);
23121 EVT ElementType = InputVector.getValueType().getVectorElementType();
23122 unsigned EltSize = ElementType.getSizeInBits() / 8;
23124 // Replace each use (extract) with a load of the appropriate element.
23125 for (unsigned i = 0; i < 4; ++i) {
23126 uint64_t Offset = EltSize * i;
23127 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23128 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23130 SDValue ScalarAddr =
23131 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23133 // Load the scalar.
23134 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23135 ScalarAddr, MachinePointerInfo(),
23136 false, false, false, 0);
23141 // Replace the extracts
23142 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23143 UE = Uses.end(); UI != UE; ++UI) {
23144 SDNode *Extract = *UI;
23146 SDValue Idx = Extract->getOperand(1);
23147 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23148 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23151 // The replacement was made in place; don't return anything.
23156 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23157 const X86Subtarget *Subtarget) {
23159 SDValue Cond = N->getOperand(0);
23160 SDValue LHS = N->getOperand(1);
23161 SDValue RHS = N->getOperand(2);
23163 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23164 SDValue CondSrc = Cond->getOperand(0);
23165 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23166 Cond = CondSrc->getOperand(0);
23169 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23172 // A vselect where all conditions and data are constants can be optimized into
23173 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23174 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23175 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23178 unsigned MaskValue = 0;
23179 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23182 MVT VT = N->getSimpleValueType(0);
23183 unsigned NumElems = VT.getVectorNumElements();
23184 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23185 for (unsigned i = 0; i < NumElems; ++i) {
23186 // Be sure we emit undef where we can.
23187 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23188 ShuffleMask[i] = -1;
23190 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23193 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23194 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23196 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23199 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23201 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23202 TargetLowering::DAGCombinerInfo &DCI,
23203 const X86Subtarget *Subtarget) {
23205 SDValue Cond = N->getOperand(0);
23206 // Get the LHS/RHS of the select.
23207 SDValue LHS = N->getOperand(1);
23208 SDValue RHS = N->getOperand(2);
23209 EVT VT = LHS.getValueType();
23210 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23212 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23213 // instructions match the semantics of the common C idiom x<y?x:y but not
23214 // x<=y?x:y, because of how they handle negative zero (which can be
23215 // ignored in unsafe-math mode).
23216 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23217 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23218 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23219 (Subtarget->hasSSE2() ||
23220 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23221 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23223 unsigned Opcode = 0;
23224 // Check for x CC y ? x : y.
23225 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23226 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23230 // Converting this to a min would handle NaNs incorrectly, and swapping
23231 // the operands would cause it to handle comparisons between positive
23232 // and negative zero incorrectly.
23233 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23234 if (!DAG.getTarget().Options.UnsafeFPMath &&
23235 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23237 std::swap(LHS, RHS);
23239 Opcode = X86ISD::FMIN;
23242 // Converting this to a min would handle comparisons between positive
23243 // and negative zero incorrectly.
23244 if (!DAG.getTarget().Options.UnsafeFPMath &&
23245 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23247 Opcode = X86ISD::FMIN;
23250 // Converting this to a min would handle both negative zeros and NaNs
23251 // incorrectly, but we can swap the operands to fix both.
23252 std::swap(LHS, RHS);
23256 Opcode = X86ISD::FMIN;
23260 // Converting this to a max would handle comparisons between positive
23261 // and negative zero incorrectly.
23262 if (!DAG.getTarget().Options.UnsafeFPMath &&
23263 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23265 Opcode = X86ISD::FMAX;
23268 // Converting this to a max would handle NaNs incorrectly, and swapping
23269 // the operands would cause it to handle comparisons between positive
23270 // and negative zero incorrectly.
23271 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23272 if (!DAG.getTarget().Options.UnsafeFPMath &&
23273 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23275 std::swap(LHS, RHS);
23277 Opcode = X86ISD::FMAX;
23280 // Converting this to a max would handle both negative zeros and NaNs
23281 // incorrectly, but we can swap the operands to fix both.
23282 std::swap(LHS, RHS);
23286 Opcode = X86ISD::FMAX;
23289 // Check for x CC y ? y : x -- a min/max with reversed arms.
23290 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23291 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23295 // Converting this to a min would handle comparisons between positive
23296 // and negative zero incorrectly, and swapping the operands would
23297 // cause it to handle NaNs incorrectly.
23298 if (!DAG.getTarget().Options.UnsafeFPMath &&
23299 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23300 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23302 std::swap(LHS, RHS);
23304 Opcode = X86ISD::FMIN;
23307 // Converting this to a min would handle NaNs incorrectly.
23308 if (!DAG.getTarget().Options.UnsafeFPMath &&
23309 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23311 Opcode = X86ISD::FMIN;
23314 // Converting this to a min would handle both negative zeros and NaNs
23315 // incorrectly, but we can swap the operands to fix both.
23316 std::swap(LHS, RHS);
23320 Opcode = X86ISD::FMIN;
23324 // Converting this to a max would handle NaNs incorrectly.
23325 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23327 Opcode = X86ISD::FMAX;
23330 // Converting this to a max would handle comparisons between positive
23331 // and negative zero incorrectly, and swapping the operands would
23332 // cause it to handle NaNs incorrectly.
23333 if (!DAG.getTarget().Options.UnsafeFPMath &&
23334 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23335 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23337 std::swap(LHS, RHS);
23339 Opcode = X86ISD::FMAX;
23342 // Converting this to a max would handle both negative zeros and NaNs
23343 // incorrectly, but we can swap the operands to fix both.
23344 std::swap(LHS, RHS);
23348 Opcode = X86ISD::FMAX;
23354 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23357 EVT CondVT = Cond.getValueType();
23358 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23359 CondVT.getVectorElementType() == MVT::i1) {
23360 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23361 // lowering on KNL. In this case we convert it to
23362 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23363 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23364 // Since SKX these selects have a proper lowering.
23365 EVT OpVT = LHS.getValueType();
23366 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23367 (OpVT.getVectorElementType() == MVT::i8 ||
23368 OpVT.getVectorElementType() == MVT::i16) &&
23369 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23370 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23371 DCI.AddToWorklist(Cond.getNode());
23372 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23375 // If this is a select between two integer constants, try to do some
23377 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23378 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23379 // Don't do this for crazy integer types.
23380 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23381 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23382 // so that TrueC (the true value) is larger than FalseC.
23383 bool NeedsCondInvert = false;
23385 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23386 // Efficiently invertible.
23387 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23388 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23389 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23390 NeedsCondInvert = true;
23391 std::swap(TrueC, FalseC);
23394 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23395 if (FalseC->getAPIntValue() == 0 &&
23396 TrueC->getAPIntValue().isPowerOf2()) {
23397 if (NeedsCondInvert) // Invert the condition if needed.
23398 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23399 DAG.getConstant(1, DL, Cond.getValueType()));
23401 // Zero extend the condition if needed.
23402 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23404 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23405 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23406 DAG.getConstant(ShAmt, DL, MVT::i8));
23409 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23410 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23411 if (NeedsCondInvert) // Invert the condition if needed.
23412 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23413 DAG.getConstant(1, DL, Cond.getValueType()));
23415 // Zero extend the condition if needed.
23416 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23417 FalseC->getValueType(0), Cond);
23418 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23419 SDValue(FalseC, 0));
23422 // Optimize cases that will turn into an LEA instruction. This requires
23423 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23424 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23425 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23426 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23428 bool isFastMultiplier = false;
23430 switch ((unsigned char)Diff) {
23432 case 1: // result = add base, cond
23433 case 2: // result = lea base( , cond*2)
23434 case 3: // result = lea base(cond, cond*2)
23435 case 4: // result = lea base( , cond*4)
23436 case 5: // result = lea base(cond, cond*4)
23437 case 8: // result = lea base( , cond*8)
23438 case 9: // result = lea base(cond, cond*8)
23439 isFastMultiplier = true;
23444 if (isFastMultiplier) {
23445 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23446 if (NeedsCondInvert) // Invert the condition if needed.
23447 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23448 DAG.getConstant(1, DL, Cond.getValueType()));
23450 // Zero extend the condition if needed.
23451 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23453 // Scale the condition by the difference.
23455 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23456 DAG.getConstant(Diff, DL,
23457 Cond.getValueType()));
23459 // Add the base if non-zero.
23460 if (FalseC->getAPIntValue() != 0)
23461 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23462 SDValue(FalseC, 0));
23469 // Canonicalize max and min:
23470 // (x > y) ? x : y -> (x >= y) ? x : y
23471 // (x < y) ? x : y -> (x <= y) ? x : y
23472 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23473 // the need for an extra compare
23474 // against zero. e.g.
23475 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23477 // testl %edi, %edi
23479 // cmovgl %edi, %eax
23483 // cmovsl %eax, %edi
23484 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23485 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23486 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23487 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23492 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23493 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23494 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23495 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23500 // Early exit check
23501 if (!TLI.isTypeLegal(VT))
23504 // Match VSELECTs into subs with unsigned saturation.
23505 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23506 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23507 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23508 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23509 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23511 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23512 // left side invert the predicate to simplify logic below.
23514 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23516 CC = ISD::getSetCCInverse(CC, true);
23517 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23521 if (Other.getNode() && Other->getNumOperands() == 2 &&
23522 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23523 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23524 SDValue CondRHS = Cond->getOperand(1);
23526 // Look for a general sub with unsigned saturation first.
23527 // x >= y ? x-y : 0 --> subus x, y
23528 // x > y ? x-y : 0 --> subus x, y
23529 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23530 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23531 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23533 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23534 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23535 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23536 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23537 // If the RHS is a constant we have to reverse the const
23538 // canonicalization.
23539 // x > C-1 ? x+-C : 0 --> subus x, C
23540 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23541 CondRHSConst->getAPIntValue() ==
23542 (-OpRHSConst->getAPIntValue() - 1))
23543 return DAG.getNode(
23544 X86ISD::SUBUS, DL, VT, OpLHS,
23545 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23547 // Another special case: If C was a sign bit, the sub has been
23548 // canonicalized into a xor.
23549 // FIXME: Would it be better to use computeKnownBits to determine
23550 // whether it's safe to decanonicalize the xor?
23551 // x s< 0 ? x^C : 0 --> subus x, C
23552 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23553 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23554 OpRHSConst->getAPIntValue().isSignBit())
23555 // Note that we have to rebuild the RHS constant here to ensure we
23556 // don't rely on particular values of undef lanes.
23557 return DAG.getNode(
23558 X86ISD::SUBUS, DL, VT, OpLHS,
23559 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23564 // Simplify vector selection if condition value type matches vselect
23566 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23567 assert(Cond.getValueType().isVector() &&
23568 "vector select expects a vector selector!");
23570 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23571 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23573 // Try invert the condition if true value is not all 1s and false value
23575 if (!TValIsAllOnes && !FValIsAllZeros &&
23576 // Check if the selector will be produced by CMPP*/PCMP*
23577 Cond.getOpcode() == ISD::SETCC &&
23578 // Check if SETCC has already been promoted
23579 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23581 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23582 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23584 if (TValIsAllZeros || FValIsAllOnes) {
23585 SDValue CC = Cond.getOperand(2);
23586 ISD::CondCode NewCC =
23587 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23588 Cond.getOperand(0).getValueType().isInteger());
23589 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23590 std::swap(LHS, RHS);
23591 TValIsAllOnes = FValIsAllOnes;
23592 FValIsAllZeros = TValIsAllZeros;
23596 if (TValIsAllOnes || FValIsAllZeros) {
23599 if (TValIsAllOnes && FValIsAllZeros)
23601 else if (TValIsAllOnes)
23603 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23604 else if (FValIsAllZeros)
23605 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23606 DAG.getBitcast(CondVT, LHS));
23608 return DAG.getBitcast(VT, Ret);
23612 // We should generate an X86ISD::BLENDI from a vselect if its argument
23613 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23614 // constants. This specific pattern gets generated when we split a
23615 // selector for a 512 bit vector in a machine without AVX512 (but with
23616 // 256-bit vectors), during legalization:
23618 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23620 // Iff we find this pattern and the build_vectors are built from
23621 // constants, we translate the vselect into a shuffle_vector that we
23622 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23623 if ((N->getOpcode() == ISD::VSELECT ||
23624 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23625 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23626 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23627 if (Shuffle.getNode())
23631 // If this is a *dynamic* select (non-constant condition) and we can match
23632 // this node with one of the variable blend instructions, restructure the
23633 // condition so that the blends can use the high bit of each element and use
23634 // SimplifyDemandedBits to simplify the condition operand.
23635 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23636 !DCI.isBeforeLegalize() &&
23637 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23638 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23640 // Don't optimize vector selects that map to mask-registers.
23644 // We can only handle the cases where VSELECT is directly legal on the
23645 // subtarget. We custom lower VSELECT nodes with constant conditions and
23646 // this makes it hard to see whether a dynamic VSELECT will correctly
23647 // lower, so we both check the operation's status and explicitly handle the
23648 // cases where a *dynamic* blend will fail even though a constant-condition
23649 // blend could be custom lowered.
23650 // FIXME: We should find a better way to handle this class of problems.
23651 // Potentially, we should combine constant-condition vselect nodes
23652 // pre-legalization into shuffles and not mark as many types as custom
23654 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23656 // FIXME: We don't support i16-element blends currently. We could and
23657 // should support them by making *all* the bits in the condition be set
23658 // rather than just the high bit and using an i8-element blend.
23659 if (VT.getScalarType() == MVT::i16)
23661 // Dynamic blending was only available from SSE4.1 onward.
23662 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23664 // Byte blends are only available in AVX2
23665 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23666 !Subtarget->hasAVX2())
23669 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23670 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23672 APInt KnownZero, KnownOne;
23673 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23674 DCI.isBeforeLegalizeOps());
23675 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23676 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23678 // If we changed the computation somewhere in the DAG, this change
23679 // will affect all users of Cond.
23680 // Make sure it is fine and update all the nodes so that we do not
23681 // use the generic VSELECT anymore. Otherwise, we may perform
23682 // wrong optimizations as we messed up with the actual expectation
23683 // for the vector boolean values.
23684 if (Cond != TLO.Old) {
23685 // Check all uses of that condition operand to check whether it will be
23686 // consumed by non-BLEND instructions, which may depend on all bits are
23688 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23690 if (I->getOpcode() != ISD::VSELECT)
23691 // TODO: Add other opcodes eventually lowered into BLEND.
23694 // Update all the users of the condition, before committing the change,
23695 // so that the VSELECT optimizations that expect the correct vector
23696 // boolean value will not be triggered.
23697 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23699 DAG.ReplaceAllUsesOfValueWith(
23701 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23702 Cond, I->getOperand(1), I->getOperand(2)));
23703 DCI.CommitTargetLoweringOpt(TLO);
23706 // At this point, only Cond is changed. Change the condition
23707 // just for N to keep the opportunity to optimize all other
23708 // users their own way.
23709 DAG.ReplaceAllUsesOfValueWith(
23711 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23712 TLO.New, N->getOperand(1), N->getOperand(2)));
23720 // Check whether a boolean test is testing a boolean value generated by
23721 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23724 // Simplify the following patterns:
23725 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23726 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23727 // to (Op EFLAGS Cond)
23729 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23730 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23731 // to (Op EFLAGS !Cond)
23733 // where Op could be BRCOND or CMOV.
23735 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23736 // Quit if not CMP and SUB with its value result used.
23737 if (Cmp.getOpcode() != X86ISD::CMP &&
23738 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23741 // Quit if not used as a boolean value.
23742 if (CC != X86::COND_E && CC != X86::COND_NE)
23745 // Check CMP operands. One of them should be 0 or 1 and the other should be
23746 // an SetCC or extended from it.
23747 SDValue Op1 = Cmp.getOperand(0);
23748 SDValue Op2 = Cmp.getOperand(1);
23751 const ConstantSDNode* C = nullptr;
23752 bool needOppositeCond = (CC == X86::COND_E);
23753 bool checkAgainstTrue = false; // Is it a comparison against 1?
23755 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23757 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23759 else // Quit if all operands are not constants.
23762 if (C->getZExtValue() == 1) {
23763 needOppositeCond = !needOppositeCond;
23764 checkAgainstTrue = true;
23765 } else if (C->getZExtValue() != 0)
23766 // Quit if the constant is neither 0 or 1.
23769 bool truncatedToBoolWithAnd = false;
23770 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23771 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23772 SetCC.getOpcode() == ISD::TRUNCATE ||
23773 SetCC.getOpcode() == ISD::AND) {
23774 if (SetCC.getOpcode() == ISD::AND) {
23776 ConstantSDNode *CS;
23777 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23778 CS->getZExtValue() == 1)
23780 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23781 CS->getZExtValue() == 1)
23785 SetCC = SetCC.getOperand(OpIdx);
23786 truncatedToBoolWithAnd = true;
23788 SetCC = SetCC.getOperand(0);
23791 switch (SetCC.getOpcode()) {
23792 case X86ISD::SETCC_CARRY:
23793 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23794 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23795 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23796 // truncated to i1 using 'and'.
23797 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23799 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23800 "Invalid use of SETCC_CARRY!");
23802 case X86ISD::SETCC:
23803 // Set the condition code or opposite one if necessary.
23804 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23805 if (needOppositeCond)
23806 CC = X86::GetOppositeBranchCondition(CC);
23807 return SetCC.getOperand(1);
23808 case X86ISD::CMOV: {
23809 // Check whether false/true value has canonical one, i.e. 0 or 1.
23810 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23811 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23812 // Quit if true value is not a constant.
23815 // Quit if false value is not a constant.
23817 SDValue Op = SetCC.getOperand(0);
23818 // Skip 'zext' or 'trunc' node.
23819 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23820 Op.getOpcode() == ISD::TRUNCATE)
23821 Op = Op.getOperand(0);
23822 // A special case for rdrand/rdseed, where 0 is set if false cond is
23824 if ((Op.getOpcode() != X86ISD::RDRAND &&
23825 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23828 // Quit if false value is not the constant 0 or 1.
23829 bool FValIsFalse = true;
23830 if (FVal && FVal->getZExtValue() != 0) {
23831 if (FVal->getZExtValue() != 1)
23833 // If FVal is 1, opposite cond is needed.
23834 needOppositeCond = !needOppositeCond;
23835 FValIsFalse = false;
23837 // Quit if TVal is not the constant opposite of FVal.
23838 if (FValIsFalse && TVal->getZExtValue() != 1)
23840 if (!FValIsFalse && TVal->getZExtValue() != 0)
23842 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23843 if (needOppositeCond)
23844 CC = X86::GetOppositeBranchCondition(CC);
23845 return SetCC.getOperand(3);
23852 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23854 /// (X86or (X86setcc) (X86setcc))
23855 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23856 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23857 X86::CondCode &CC1, SDValue &Flags,
23859 if (Cond->getOpcode() == X86ISD::CMP) {
23860 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23861 if (!CondOp1C || !CondOp1C->isNullValue())
23864 Cond = Cond->getOperand(0);
23869 SDValue SetCC0, SetCC1;
23870 switch (Cond->getOpcode()) {
23871 default: return false;
23878 SetCC0 = Cond->getOperand(0);
23879 SetCC1 = Cond->getOperand(1);
23883 // Make sure we have SETCC nodes, using the same flags value.
23884 if (SetCC0.getOpcode() != X86ISD::SETCC ||
23885 SetCC1.getOpcode() != X86ISD::SETCC ||
23886 SetCC0->getOperand(1) != SetCC1->getOperand(1))
23889 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
23890 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
23891 Flags = SetCC0->getOperand(1);
23895 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23896 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23897 TargetLowering::DAGCombinerInfo &DCI,
23898 const X86Subtarget *Subtarget) {
23901 // If the flag operand isn't dead, don't touch this CMOV.
23902 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23905 SDValue FalseOp = N->getOperand(0);
23906 SDValue TrueOp = N->getOperand(1);
23907 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23908 SDValue Cond = N->getOperand(3);
23910 if (CC == X86::COND_E || CC == X86::COND_NE) {
23911 switch (Cond.getOpcode()) {
23915 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23916 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23917 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23923 Flags = checkBoolTestSetCCCombine(Cond, CC);
23924 if (Flags.getNode() &&
23925 // Extra check as FCMOV only supports a subset of X86 cond.
23926 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23927 SDValue Ops[] = { FalseOp, TrueOp,
23928 DAG.getConstant(CC, DL, MVT::i8), Flags };
23929 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23932 // If this is a select between two integer constants, try to do some
23933 // optimizations. Note that the operands are ordered the opposite of SELECT
23935 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23936 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23937 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23938 // larger than FalseC (the false value).
23939 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23940 CC = X86::GetOppositeBranchCondition(CC);
23941 std::swap(TrueC, FalseC);
23942 std::swap(TrueOp, FalseOp);
23945 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23946 // This is efficient for any integer data type (including i8/i16) and
23948 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23949 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23950 DAG.getConstant(CC, DL, MVT::i8), Cond);
23952 // Zero extend the condition if needed.
23953 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23955 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23956 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23957 DAG.getConstant(ShAmt, DL, MVT::i8));
23958 if (N->getNumValues() == 2) // Dead flag value?
23959 return DCI.CombineTo(N, Cond, SDValue());
23963 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23964 // for any integer data type, including i8/i16.
23965 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23966 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23967 DAG.getConstant(CC, DL, MVT::i8), Cond);
23969 // Zero extend the condition if needed.
23970 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23971 FalseC->getValueType(0), Cond);
23972 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23973 SDValue(FalseC, 0));
23975 if (N->getNumValues() == 2) // Dead flag value?
23976 return DCI.CombineTo(N, Cond, SDValue());
23980 // Optimize cases that will turn into an LEA instruction. This requires
23981 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23982 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23983 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23984 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23986 bool isFastMultiplier = false;
23988 switch ((unsigned char)Diff) {
23990 case 1: // result = add base, cond
23991 case 2: // result = lea base( , cond*2)
23992 case 3: // result = lea base(cond, cond*2)
23993 case 4: // result = lea base( , cond*4)
23994 case 5: // result = lea base(cond, cond*4)
23995 case 8: // result = lea base( , cond*8)
23996 case 9: // result = lea base(cond, cond*8)
23997 isFastMultiplier = true;
24002 if (isFastMultiplier) {
24003 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24004 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24005 DAG.getConstant(CC, DL, MVT::i8), Cond);
24006 // Zero extend the condition if needed.
24007 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24009 // Scale the condition by the difference.
24011 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24012 DAG.getConstant(Diff, DL, Cond.getValueType()));
24014 // Add the base if non-zero.
24015 if (FalseC->getAPIntValue() != 0)
24016 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24017 SDValue(FalseC, 0));
24018 if (N->getNumValues() == 2) // Dead flag value?
24019 return DCI.CombineTo(N, Cond, SDValue());
24026 // Handle these cases:
24027 // (select (x != c), e, c) -> select (x != c), e, x),
24028 // (select (x == c), c, e) -> select (x == c), x, e)
24029 // where the c is an integer constant, and the "select" is the combination
24030 // of CMOV and CMP.
24032 // The rationale for this change is that the conditional-move from a constant
24033 // needs two instructions, however, conditional-move from a register needs
24034 // only one instruction.
24036 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24037 // some instruction-combining opportunities. This opt needs to be
24038 // postponed as late as possible.
24040 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24041 // the DCI.xxxx conditions are provided to postpone the optimization as
24042 // late as possible.
24044 ConstantSDNode *CmpAgainst = nullptr;
24045 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24046 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24047 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24049 if (CC == X86::COND_NE &&
24050 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24051 CC = X86::GetOppositeBranchCondition(CC);
24052 std::swap(TrueOp, FalseOp);
24055 if (CC == X86::COND_E &&
24056 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24057 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24058 DAG.getConstant(CC, DL, MVT::i8), Cond };
24059 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24064 // Fold and/or of setcc's to double CMOV:
24065 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24066 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24068 // This combine lets us generate:
24069 // cmovcc1 (jcc1 if we don't have CMOV)
24075 // cmovne (jne if we don't have CMOV)
24076 // When we can't use the CMOV instruction, it might increase branch
24078 // When we can use CMOV, or when there is no mispredict, this improves
24079 // throughput and reduces register pressure.
24081 if (CC == X86::COND_NE) {
24083 X86::CondCode CC0, CC1;
24085 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24087 std::swap(FalseOp, TrueOp);
24088 CC0 = X86::GetOppositeBranchCondition(CC0);
24089 CC1 = X86::GetOppositeBranchCondition(CC1);
24092 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24094 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24095 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24096 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24097 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24105 /// PerformMulCombine - Optimize a single multiply with constant into two
24106 /// in order to implement it with two cheaper instructions, e.g.
24107 /// LEA + SHL, LEA + LEA.
24108 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24109 TargetLowering::DAGCombinerInfo &DCI) {
24110 // An imul is usually smaller than the alternative sequence.
24111 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24114 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24117 EVT VT = N->getValueType(0);
24118 if (VT != MVT::i64 && VT != MVT::i32)
24121 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24124 uint64_t MulAmt = C->getZExtValue();
24125 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24128 uint64_t MulAmt1 = 0;
24129 uint64_t MulAmt2 = 0;
24130 if ((MulAmt % 9) == 0) {
24132 MulAmt2 = MulAmt / 9;
24133 } else if ((MulAmt % 5) == 0) {
24135 MulAmt2 = MulAmt / 5;
24136 } else if ((MulAmt % 3) == 0) {
24138 MulAmt2 = MulAmt / 3;
24141 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24144 if (isPowerOf2_64(MulAmt2) &&
24145 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24146 // If second multiplifer is pow2, issue it first. We want the multiply by
24147 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24149 std::swap(MulAmt1, MulAmt2);
24152 if (isPowerOf2_64(MulAmt1))
24153 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24154 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24156 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24157 DAG.getConstant(MulAmt1, DL, VT));
24159 if (isPowerOf2_64(MulAmt2))
24160 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24161 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24163 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24164 DAG.getConstant(MulAmt2, DL, VT));
24166 // Do not add new nodes to DAG combiner worklist.
24167 DCI.CombineTo(N, NewMul, false);
24172 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24173 SDValue N0 = N->getOperand(0);
24174 SDValue N1 = N->getOperand(1);
24175 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24176 EVT VT = N0.getValueType();
24178 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24179 // since the result of setcc_c is all zero's or all ones.
24180 if (VT.isInteger() && !VT.isVector() &&
24181 N1C && N0.getOpcode() == ISD::AND &&
24182 N0.getOperand(1).getOpcode() == ISD::Constant) {
24183 SDValue N00 = N0.getOperand(0);
24184 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24185 APInt ShAmt = N1C->getAPIntValue();
24186 Mask = Mask.shl(ShAmt);
24187 bool MaskOK = false;
24188 // We can handle cases concerning bit-widening nodes containing setcc_c if
24189 // we carefully interrogate the mask to make sure we are semantics
24191 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24192 // of the underlying setcc_c operation if the setcc_c was zero extended.
24193 // Consider the following example:
24194 // zext(setcc_c) -> i32 0x0000FFFF
24195 // c1 -> i32 0x0000FFFF
24196 // c2 -> i32 0x00000001
24197 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24198 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24199 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24201 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24202 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24204 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24205 N00.getOpcode() == ISD::ANY_EXTEND) &&
24206 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24207 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24209 if (MaskOK && Mask != 0) {
24211 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24215 // Hardware support for vector shifts is sparse which makes us scalarize the
24216 // vector operations in many cases. Also, on sandybridge ADD is faster than
24218 // (shl V, 1) -> add V,V
24219 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24220 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24221 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24222 // We shift all of the values by one. In many cases we do not have
24223 // hardware support for this operation. This is better expressed as an ADD
24225 if (N1SplatC->getAPIntValue() == 1)
24226 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24232 /// \brief Returns a vector of 0s if the node in input is a vector logical
24233 /// shift by a constant amount which is known to be bigger than or equal
24234 /// to the vector element size in bits.
24235 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24236 const X86Subtarget *Subtarget) {
24237 EVT VT = N->getValueType(0);
24239 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24240 (!Subtarget->hasInt256() ||
24241 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24244 SDValue Amt = N->getOperand(1);
24246 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24247 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24248 APInt ShiftAmt = AmtSplat->getAPIntValue();
24249 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24251 // SSE2/AVX2 logical shifts always return a vector of 0s
24252 // if the shift amount is bigger than or equal to
24253 // the element size. The constant shift amount will be
24254 // encoded as a 8-bit immediate.
24255 if (ShiftAmt.trunc(8).uge(MaxAmount))
24256 return getZeroVector(VT, Subtarget, DAG, DL);
24262 /// PerformShiftCombine - Combine shifts.
24263 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24264 TargetLowering::DAGCombinerInfo &DCI,
24265 const X86Subtarget *Subtarget) {
24266 if (N->getOpcode() == ISD::SHL)
24267 if (SDValue V = PerformSHLCombine(N, DAG))
24270 // Try to fold this logical shift into a zero vector.
24271 if (N->getOpcode() != ISD::SRA)
24272 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24278 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24279 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24280 // and friends. Likewise for OR -> CMPNEQSS.
24281 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24282 TargetLowering::DAGCombinerInfo &DCI,
24283 const X86Subtarget *Subtarget) {
24286 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24287 // we're requiring SSE2 for both.
24288 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24289 SDValue N0 = N->getOperand(0);
24290 SDValue N1 = N->getOperand(1);
24291 SDValue CMP0 = N0->getOperand(1);
24292 SDValue CMP1 = N1->getOperand(1);
24295 // The SETCCs should both refer to the same CMP.
24296 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24299 SDValue CMP00 = CMP0->getOperand(0);
24300 SDValue CMP01 = CMP0->getOperand(1);
24301 EVT VT = CMP00.getValueType();
24303 if (VT == MVT::f32 || VT == MVT::f64) {
24304 bool ExpectingFlags = false;
24305 // Check for any users that want flags:
24306 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24307 !ExpectingFlags && UI != UE; ++UI)
24308 switch (UI->getOpcode()) {
24313 ExpectingFlags = true;
24315 case ISD::CopyToReg:
24316 case ISD::SIGN_EXTEND:
24317 case ISD::ZERO_EXTEND:
24318 case ISD::ANY_EXTEND:
24322 if (!ExpectingFlags) {
24323 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24324 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24326 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24327 X86::CondCode tmp = cc0;
24332 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24333 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24334 // FIXME: need symbolic constants for these magic numbers.
24335 // See X86ATTInstPrinter.cpp:printSSECC().
24336 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24337 if (Subtarget->hasAVX512()) {
24338 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24340 DAG.getConstant(x86cc, DL, MVT::i8));
24341 if (N->getValueType(0) != MVT::i1)
24342 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24346 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24347 CMP00.getValueType(), CMP00, CMP01,
24348 DAG.getConstant(x86cc, DL,
24351 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24352 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24354 if (is64BitFP && !Subtarget->is64Bit()) {
24355 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24356 // 64-bit integer, since that's not a legal type. Since
24357 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24358 // bits, but can do this little dance to extract the lowest 32 bits
24359 // and work with those going forward.
24360 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24362 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24363 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24364 Vector32, DAG.getIntPtrConstant(0, DL));
24368 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24369 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24370 DAG.getConstant(1, DL, IntVT));
24371 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24373 return OneBitOfTruth;
24381 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24382 /// so it can be folded inside ANDNP.
24383 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24384 EVT VT = N->getValueType(0);
24386 // Match direct AllOnes for 128 and 256-bit vectors
24387 if (ISD::isBuildVectorAllOnes(N))
24390 // Look through a bit convert.
24391 if (N->getOpcode() == ISD::BITCAST)
24392 N = N->getOperand(0).getNode();
24394 // Sometimes the operand may come from a insert_subvector building a 256-bit
24396 if (VT.is256BitVector() &&
24397 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24398 SDValue V1 = N->getOperand(0);
24399 SDValue V2 = N->getOperand(1);
24401 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24402 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24403 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24404 ISD::isBuildVectorAllOnes(V2.getNode()))
24411 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24412 // register. In most cases we actually compare or select YMM-sized registers
24413 // and mixing the two types creates horrible code. This method optimizes
24414 // some of the transition sequences.
24415 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24416 TargetLowering::DAGCombinerInfo &DCI,
24417 const X86Subtarget *Subtarget) {
24418 EVT VT = N->getValueType(0);
24419 if (!VT.is256BitVector())
24422 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24423 N->getOpcode() == ISD::ZERO_EXTEND ||
24424 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24426 SDValue Narrow = N->getOperand(0);
24427 EVT NarrowVT = Narrow->getValueType(0);
24428 if (!NarrowVT.is128BitVector())
24431 if (Narrow->getOpcode() != ISD::XOR &&
24432 Narrow->getOpcode() != ISD::AND &&
24433 Narrow->getOpcode() != ISD::OR)
24436 SDValue N0 = Narrow->getOperand(0);
24437 SDValue N1 = Narrow->getOperand(1);
24440 // The Left side has to be a trunc.
24441 if (N0.getOpcode() != ISD::TRUNCATE)
24444 // The type of the truncated inputs.
24445 EVT WideVT = N0->getOperand(0)->getValueType(0);
24449 // The right side has to be a 'trunc' or a constant vector.
24450 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24451 ConstantSDNode *RHSConstSplat = nullptr;
24452 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24453 RHSConstSplat = RHSBV->getConstantSplatNode();
24454 if (!RHSTrunc && !RHSConstSplat)
24457 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24459 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24462 // Set N0 and N1 to hold the inputs to the new wide operation.
24463 N0 = N0->getOperand(0);
24464 if (RHSConstSplat) {
24465 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24466 SDValue(RHSConstSplat, 0));
24467 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24468 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24469 } else if (RHSTrunc) {
24470 N1 = N1->getOperand(0);
24473 // Generate the wide operation.
24474 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24475 unsigned Opcode = N->getOpcode();
24477 case ISD::ANY_EXTEND:
24479 case ISD::ZERO_EXTEND: {
24480 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24481 APInt Mask = APInt::getAllOnesValue(InBits);
24482 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24483 return DAG.getNode(ISD::AND, DL, VT,
24484 Op, DAG.getConstant(Mask, DL, VT));
24486 case ISD::SIGN_EXTEND:
24487 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24488 Op, DAG.getValueType(NarrowVT));
24490 llvm_unreachable("Unexpected opcode");
24494 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24495 TargetLowering::DAGCombinerInfo &DCI,
24496 const X86Subtarget *Subtarget) {
24497 SDValue N0 = N->getOperand(0);
24498 SDValue N1 = N->getOperand(1);
24501 // A vector zext_in_reg may be represented as a shuffle,
24502 // feeding into a bitcast (this represents anyext) feeding into
24503 // an and with a mask.
24504 // We'd like to try to combine that into a shuffle with zero
24505 // plus a bitcast, removing the and.
24506 if (N0.getOpcode() != ISD::BITCAST ||
24507 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24510 // The other side of the AND should be a splat of 2^C, where C
24511 // is the number of bits in the source type.
24512 if (N1.getOpcode() == ISD::BITCAST)
24513 N1 = N1.getOperand(0);
24514 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24516 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24518 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24519 EVT SrcType = Shuffle->getValueType(0);
24521 // We expect a single-source shuffle
24522 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24525 unsigned SrcSize = SrcType.getScalarSizeInBits();
24527 APInt SplatValue, SplatUndef;
24528 unsigned SplatBitSize;
24530 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24531 SplatBitSize, HasAnyUndefs))
24534 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24535 // Make sure the splat matches the mask we expect
24536 if (SplatBitSize > ResSize ||
24537 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24540 // Make sure the input and output size make sense
24541 if (SrcSize >= ResSize || ResSize % SrcSize)
24544 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24545 // The number of u's between each two values depends on the ratio between
24546 // the source and dest type.
24547 unsigned ZextRatio = ResSize / SrcSize;
24548 bool IsZext = true;
24549 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24550 if (i % ZextRatio) {
24551 if (Shuffle->getMaskElt(i) > 0) {
24557 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24558 // Expected element number
24568 // Ok, perform the transformation - replace the shuffle with
24569 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24570 // (instead of undef) where the k elements come from the zero vector.
24571 SmallVector<int, 8> Mask;
24572 unsigned NumElems = SrcType.getVectorNumElements();
24573 for (unsigned i = 0; i < NumElems; ++i)
24575 Mask.push_back(NumElems);
24577 Mask.push_back(i / ZextRatio);
24579 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24580 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24581 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24584 /// If both input operands of a logic op are being cast from floating point
24585 /// types, try to convert this into a floating point logic node to avoid
24586 /// unnecessary moves from SSE to integer registers.
24587 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24588 const X86Subtarget *Subtarget) {
24589 unsigned FPOpcode = ISD::DELETED_NODE;
24590 if (N->getOpcode() == ISD::AND)
24591 FPOpcode = X86ISD::FAND;
24592 else if (N->getOpcode() == ISD::OR)
24593 FPOpcode = X86ISD::FOR;
24594 else if (N->getOpcode() == ISD::XOR)
24595 FPOpcode = X86ISD::FXOR;
24597 assert(FPOpcode != ISD::DELETED_NODE &&
24598 "Unexpected input node for FP logic conversion");
24600 EVT VT = N->getValueType(0);
24601 SDValue N0 = N->getOperand(0);
24602 SDValue N1 = N->getOperand(1);
24604 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24605 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24606 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24607 SDValue N00 = N0.getOperand(0);
24608 SDValue N10 = N1.getOperand(0);
24609 EVT N00Type = N00.getValueType();
24610 EVT N10Type = N10.getValueType();
24611 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24612 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24613 return DAG.getBitcast(VT, FPLogic);
24619 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24620 TargetLowering::DAGCombinerInfo &DCI,
24621 const X86Subtarget *Subtarget) {
24622 if (DCI.isBeforeLegalizeOps())
24625 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24628 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24631 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24634 EVT VT = N->getValueType(0);
24635 SDValue N0 = N->getOperand(0);
24636 SDValue N1 = N->getOperand(1);
24639 // Create BEXTR instructions
24640 // BEXTR is ((X >> imm) & (2**size-1))
24641 if (VT == MVT::i32 || VT == MVT::i64) {
24642 // Check for BEXTR.
24643 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24644 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24645 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24646 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24647 if (MaskNode && ShiftNode) {
24648 uint64_t Mask = MaskNode->getZExtValue();
24649 uint64_t Shift = ShiftNode->getZExtValue();
24650 if (isMask_64(Mask)) {
24651 uint64_t MaskSize = countPopulation(Mask);
24652 if (Shift + MaskSize <= VT.getSizeInBits())
24653 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24654 DAG.getConstant(Shift | (MaskSize << 8), DL,
24663 // Want to form ANDNP nodes:
24664 // 1) In the hopes of then easily combining them with OR and AND nodes
24665 // to form PBLEND/PSIGN.
24666 // 2) To match ANDN packed intrinsics
24667 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24670 // Check LHS for vnot
24671 if (N0.getOpcode() == ISD::XOR &&
24672 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24673 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24674 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24676 // Check RHS for vnot
24677 if (N1.getOpcode() == ISD::XOR &&
24678 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24679 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24680 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24685 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24686 TargetLowering::DAGCombinerInfo &DCI,
24687 const X86Subtarget *Subtarget) {
24688 if (DCI.isBeforeLegalizeOps())
24691 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24694 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24697 SDValue N0 = N->getOperand(0);
24698 SDValue N1 = N->getOperand(1);
24699 EVT VT = N->getValueType(0);
24701 // look for psign/blend
24702 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24703 if (!Subtarget->hasSSSE3() ||
24704 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24707 // Canonicalize pandn to RHS
24708 if (N0.getOpcode() == X86ISD::ANDNP)
24710 // or (and (m, y), (pandn m, x))
24711 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24712 SDValue Mask = N1.getOperand(0);
24713 SDValue X = N1.getOperand(1);
24715 if (N0.getOperand(0) == Mask)
24716 Y = N0.getOperand(1);
24717 if (N0.getOperand(1) == Mask)
24718 Y = N0.getOperand(0);
24720 // Check to see if the mask appeared in both the AND and ANDNP and
24724 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24725 // Look through mask bitcast.
24726 if (Mask.getOpcode() == ISD::BITCAST)
24727 Mask = Mask.getOperand(0);
24728 if (X.getOpcode() == ISD::BITCAST)
24729 X = X.getOperand(0);
24730 if (Y.getOpcode() == ISD::BITCAST)
24731 Y = Y.getOperand(0);
24733 EVT MaskVT = Mask.getValueType();
24735 // Validate that the Mask operand is a vector sra node.
24736 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24737 // there is no psrai.b
24738 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24739 unsigned SraAmt = ~0;
24740 if (Mask.getOpcode() == ISD::SRA) {
24741 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24742 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24743 SraAmt = AmtConst->getZExtValue();
24744 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24745 SDValue SraC = Mask.getOperand(1);
24746 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24748 if ((SraAmt + 1) != EltBits)
24753 // Now we know we at least have a plendvb with the mask val. See if
24754 // we can form a psignb/w/d.
24755 // psign = x.type == y.type == mask.type && y = sub(0, x);
24756 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24757 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24758 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24759 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24760 "Unsupported VT for PSIGN");
24761 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24762 return DAG.getBitcast(VT, Mask);
24764 // PBLENDVB only available on SSE 4.1
24765 if (!Subtarget->hasSSE41())
24768 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24770 X = DAG.getBitcast(BlendVT, X);
24771 Y = DAG.getBitcast(BlendVT, Y);
24772 Mask = DAG.getBitcast(BlendVT, Mask);
24773 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24774 return DAG.getBitcast(VT, Mask);
24778 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24781 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24782 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24784 // SHLD/SHRD instructions have lower register pressure, but on some
24785 // platforms they have higher latency than the equivalent
24786 // series of shifts/or that would otherwise be generated.
24787 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24788 // have higher latencies and we are not optimizing for size.
24789 if (!OptForSize && Subtarget->isSHLDSlow())
24792 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24794 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24796 if (!N0.hasOneUse() || !N1.hasOneUse())
24799 SDValue ShAmt0 = N0.getOperand(1);
24800 if (ShAmt0.getValueType() != MVT::i8)
24802 SDValue ShAmt1 = N1.getOperand(1);
24803 if (ShAmt1.getValueType() != MVT::i8)
24805 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24806 ShAmt0 = ShAmt0.getOperand(0);
24807 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24808 ShAmt1 = ShAmt1.getOperand(0);
24811 unsigned Opc = X86ISD::SHLD;
24812 SDValue Op0 = N0.getOperand(0);
24813 SDValue Op1 = N1.getOperand(0);
24814 if (ShAmt0.getOpcode() == ISD::SUB) {
24815 Opc = X86ISD::SHRD;
24816 std::swap(Op0, Op1);
24817 std::swap(ShAmt0, ShAmt1);
24820 unsigned Bits = VT.getSizeInBits();
24821 if (ShAmt1.getOpcode() == ISD::SUB) {
24822 SDValue Sum = ShAmt1.getOperand(0);
24823 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24824 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24825 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24826 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24827 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24828 return DAG.getNode(Opc, DL, VT,
24830 DAG.getNode(ISD::TRUNCATE, DL,
24833 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24834 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24836 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24837 return DAG.getNode(Opc, DL, VT,
24838 N0.getOperand(0), N1.getOperand(0),
24839 DAG.getNode(ISD::TRUNCATE, DL,
24846 // Generate NEG and CMOV for integer abs.
24847 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24848 EVT VT = N->getValueType(0);
24850 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24851 // 8-bit integer abs to NEG and CMOV.
24852 if (VT.isInteger() && VT.getSizeInBits() == 8)
24855 SDValue N0 = N->getOperand(0);
24856 SDValue N1 = N->getOperand(1);
24859 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24860 // and change it to SUB and CMOV.
24861 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24862 N0.getOpcode() == ISD::ADD &&
24863 N0.getOperand(1) == N1 &&
24864 N1.getOpcode() == ISD::SRA &&
24865 N1.getOperand(0) == N0.getOperand(0))
24866 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24867 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24868 // Generate SUB & CMOV.
24869 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24870 DAG.getConstant(0, DL, VT), N0.getOperand(0));
24872 SDValue Ops[] = { N0.getOperand(0), Neg,
24873 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
24874 SDValue(Neg.getNode(), 1) };
24875 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24880 // Try to turn tests against the signbit in the form of:
24881 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
24884 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
24885 // This is only worth doing if the output type is i8.
24886 if (N->getValueType(0) != MVT::i8)
24889 SDValue N0 = N->getOperand(0);
24890 SDValue N1 = N->getOperand(1);
24892 // We should be performing an xor against a truncated shift.
24893 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
24896 // Make sure we are performing an xor against one.
24897 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
24900 // SetCC on x86 zero extends so only act on this if it's a logical shift.
24901 SDValue Shift = N0.getOperand(0);
24902 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
24905 // Make sure we are truncating from one of i16, i32 or i64.
24906 EVT ShiftTy = Shift.getValueType();
24907 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
24910 // Make sure the shift amount extracts the sign bit.
24911 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
24912 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
24915 // Create a greater-than comparison against -1.
24916 // N.B. Using SETGE against 0 works but we want a canonical looking
24917 // comparison, using SETGT matches up with what TranslateX86CC.
24919 SDValue ShiftOp = Shift.getOperand(0);
24920 EVT ShiftOpTy = ShiftOp.getValueType();
24921 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
24922 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
24926 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24927 TargetLowering::DAGCombinerInfo &DCI,
24928 const X86Subtarget *Subtarget) {
24929 if (DCI.isBeforeLegalizeOps())
24932 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
24935 if (Subtarget->hasCMov())
24936 if (SDValue RV = performIntegerAbsCombine(N, DAG))
24939 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24945 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24946 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24947 TargetLowering::DAGCombinerInfo &DCI,
24948 const X86Subtarget *Subtarget) {
24949 LoadSDNode *Ld = cast<LoadSDNode>(N);
24950 EVT RegVT = Ld->getValueType(0);
24951 EVT MemVT = Ld->getMemoryVT();
24953 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24955 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24956 // into two 16-byte operations.
24957 ISD::LoadExtType Ext = Ld->getExtensionType();
24959 unsigned AddressSpace = Ld->getAddressSpace();
24960 unsigned Alignment = Ld->getAlignment();
24961 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
24962 Ext == ISD::NON_EXTLOAD &&
24963 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
24964 AddressSpace, Alignment, &Fast) && !Fast) {
24965 unsigned NumElems = RegVT.getVectorNumElements();
24969 SDValue Ptr = Ld->getBasePtr();
24970 SDValue Increment =
24971 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24973 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24975 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24976 Ld->getPointerInfo(), Ld->isVolatile(),
24977 Ld->isNonTemporal(), Ld->isInvariant(),
24979 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24980 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24981 Ld->getPointerInfo(), Ld->isVolatile(),
24982 Ld->isNonTemporal(), Ld->isInvariant(),
24983 std::min(16U, Alignment));
24984 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24986 Load2.getValue(1));
24988 SDValue NewVec = DAG.getUNDEF(RegVT);
24989 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24990 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24991 return DCI.CombineTo(N, NewVec, TF, true);
24997 /// PerformMLOADCombine - Resolve extending loads
24998 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
24999 TargetLowering::DAGCombinerInfo &DCI,
25000 const X86Subtarget *Subtarget) {
25001 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25002 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25005 EVT VT = Mld->getValueType(0);
25006 unsigned NumElems = VT.getVectorNumElements();
25007 EVT LdVT = Mld->getMemoryVT();
25010 assert(LdVT != VT && "Cannot extend to the same type");
25011 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25012 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25013 // From, To sizes and ElemCount must be pow of two
25014 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25015 "Unexpected size for extending masked load");
25017 unsigned SizeRatio = ToSz / FromSz;
25018 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25020 // Create a type on which we perform the shuffle
25021 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25022 LdVT.getScalarType(), NumElems*SizeRatio);
25023 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25025 // Convert Src0 value
25026 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25027 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25028 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25029 for (unsigned i = 0; i != NumElems; ++i)
25030 ShuffleVec[i] = i * SizeRatio;
25032 // Can't shuffle using an illegal type.
25033 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25034 "WideVecVT should be legal");
25035 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25036 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25038 // Prepare the new mask
25040 SDValue Mask = Mld->getMask();
25041 if (Mask.getValueType() == VT) {
25042 // Mask and original value have the same type
25043 NewMask = DAG.getBitcast(WideVecVT, Mask);
25044 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25045 for (unsigned i = 0; i != NumElems; ++i)
25046 ShuffleVec[i] = i * SizeRatio;
25047 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25048 ShuffleVec[i] = NumElems*SizeRatio;
25049 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25050 DAG.getConstant(0, dl, WideVecVT),
25054 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25055 unsigned WidenNumElts = NumElems*SizeRatio;
25056 unsigned MaskNumElts = VT.getVectorNumElements();
25057 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25060 unsigned NumConcat = WidenNumElts / MaskNumElts;
25061 SmallVector<SDValue, 16> Ops(NumConcat);
25062 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25064 for (unsigned i = 1; i != NumConcat; ++i)
25067 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25070 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25071 Mld->getBasePtr(), NewMask, WideSrc0,
25072 Mld->getMemoryVT(), Mld->getMemOperand(),
25074 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25075 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25077 /// PerformMSTORECombine - Resolve truncating stores
25078 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25079 const X86Subtarget *Subtarget) {
25080 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25081 if (!Mst->isTruncatingStore())
25084 EVT VT = Mst->getValue().getValueType();
25085 unsigned NumElems = VT.getVectorNumElements();
25086 EVT StVT = Mst->getMemoryVT();
25089 assert(StVT != VT && "Cannot truncate to the same type");
25090 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25091 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25093 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25095 // The truncating store is legal in some cases. For example
25096 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25097 // are designated for truncate store.
25098 // In this case we don't need any further transformations.
25099 if (TLI.isTruncStoreLegal(VT, StVT))
25102 // From, To sizes and ElemCount must be pow of two
25103 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25104 "Unexpected size for truncating masked store");
25105 // We are going to use the original vector elt for storing.
25106 // Accumulated smaller vector elements must be a multiple of the store size.
25107 assert (((NumElems * FromSz) % ToSz) == 0 &&
25108 "Unexpected ratio for truncating masked store");
25110 unsigned SizeRatio = FromSz / ToSz;
25111 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25113 // Create a type on which we perform the shuffle
25114 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25115 StVT.getScalarType(), NumElems*SizeRatio);
25117 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25119 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25120 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25121 for (unsigned i = 0; i != NumElems; ++i)
25122 ShuffleVec[i] = i * SizeRatio;
25124 // Can't shuffle using an illegal type.
25125 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25126 "WideVecVT should be legal");
25128 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25129 DAG.getUNDEF(WideVecVT),
25133 SDValue Mask = Mst->getMask();
25134 if (Mask.getValueType() == VT) {
25135 // Mask and original value have the same type
25136 NewMask = DAG.getBitcast(WideVecVT, Mask);
25137 for (unsigned i = 0; i != NumElems; ++i)
25138 ShuffleVec[i] = i * SizeRatio;
25139 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25140 ShuffleVec[i] = NumElems*SizeRatio;
25141 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25142 DAG.getConstant(0, dl, WideVecVT),
25146 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25147 unsigned WidenNumElts = NumElems*SizeRatio;
25148 unsigned MaskNumElts = VT.getVectorNumElements();
25149 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25152 unsigned NumConcat = WidenNumElts / MaskNumElts;
25153 SmallVector<SDValue, 16> Ops(NumConcat);
25154 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25156 for (unsigned i = 1; i != NumConcat; ++i)
25159 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25162 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25163 NewMask, StVT, Mst->getMemOperand(), false);
25165 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25166 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25167 const X86Subtarget *Subtarget) {
25168 StoreSDNode *St = cast<StoreSDNode>(N);
25169 EVT VT = St->getValue().getValueType();
25170 EVT StVT = St->getMemoryVT();
25172 SDValue StoredVal = St->getOperand(1);
25173 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25175 // If we are saving a concatenation of two XMM registers and 32-byte stores
25176 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25178 unsigned AddressSpace = St->getAddressSpace();
25179 unsigned Alignment = St->getAlignment();
25180 if (VT.is256BitVector() && StVT == VT &&
25181 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25182 AddressSpace, Alignment, &Fast) && !Fast) {
25183 unsigned NumElems = VT.getVectorNumElements();
25187 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25188 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25191 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25192 SDValue Ptr0 = St->getBasePtr();
25193 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25195 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25196 St->getPointerInfo(), St->isVolatile(),
25197 St->isNonTemporal(), Alignment);
25198 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25199 St->getPointerInfo(), St->isVolatile(),
25200 St->isNonTemporal(),
25201 std::min(16U, Alignment));
25202 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25205 // Optimize trunc store (of multiple scalars) to shuffle and store.
25206 // First, pack all of the elements in one place. Next, store to memory
25207 // in fewer chunks.
25208 if (St->isTruncatingStore() && VT.isVector()) {
25209 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25210 unsigned NumElems = VT.getVectorNumElements();
25211 assert(StVT != VT && "Cannot truncate to the same type");
25212 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25213 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25215 // The truncating store is legal in some cases. For example
25216 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25217 // are designated for truncate store.
25218 // In this case we don't need any further transformations.
25219 if (TLI.isTruncStoreLegal(VT, StVT))
25222 // From, To sizes and ElemCount must be pow of two
25223 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25224 // We are going to use the original vector elt for storing.
25225 // Accumulated smaller vector elements must be a multiple of the store size.
25226 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25228 unsigned SizeRatio = FromSz / ToSz;
25230 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25232 // Create a type on which we perform the shuffle
25233 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25234 StVT.getScalarType(), NumElems*SizeRatio);
25236 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25238 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25239 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25240 for (unsigned i = 0; i != NumElems; ++i)
25241 ShuffleVec[i] = i * SizeRatio;
25243 // Can't shuffle using an illegal type.
25244 if (!TLI.isTypeLegal(WideVecVT))
25247 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25248 DAG.getUNDEF(WideVecVT),
25250 // At this point all of the data is stored at the bottom of the
25251 // register. We now need to save it to mem.
25253 // Find the largest store unit
25254 MVT StoreType = MVT::i8;
25255 for (MVT Tp : MVT::integer_valuetypes()) {
25256 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25260 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25261 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25262 (64 <= NumElems * ToSz))
25263 StoreType = MVT::f64;
25265 // Bitcast the original vector into a vector of store-size units
25266 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25267 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25268 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25269 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25270 SmallVector<SDValue, 8> Chains;
25271 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25272 TLI.getPointerTy(DAG.getDataLayout()));
25273 SDValue Ptr = St->getBasePtr();
25275 // Perform one or more big stores into memory.
25276 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25277 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25278 StoreType, ShuffWide,
25279 DAG.getIntPtrConstant(i, dl));
25280 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25281 St->getPointerInfo(), St->isVolatile(),
25282 St->isNonTemporal(), St->getAlignment());
25283 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25284 Chains.push_back(Ch);
25287 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25290 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25291 // the FP state in cases where an emms may be missing.
25292 // A preferable solution to the general problem is to figure out the right
25293 // places to insert EMMS. This qualifies as a quick hack.
25295 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25296 if (VT.getSizeInBits() != 64)
25299 const Function *F = DAG.getMachineFunction().getFunction();
25300 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25302 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25303 if ((VT.isVector() ||
25304 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25305 isa<LoadSDNode>(St->getValue()) &&
25306 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25307 St->getChain().hasOneUse() && !St->isVolatile()) {
25308 SDNode* LdVal = St->getValue().getNode();
25309 LoadSDNode *Ld = nullptr;
25310 int TokenFactorIndex = -1;
25311 SmallVector<SDValue, 8> Ops;
25312 SDNode* ChainVal = St->getChain().getNode();
25313 // Must be a store of a load. We currently handle two cases: the load
25314 // is a direct child, and it's under an intervening TokenFactor. It is
25315 // possible to dig deeper under nested TokenFactors.
25316 if (ChainVal == LdVal)
25317 Ld = cast<LoadSDNode>(St->getChain());
25318 else if (St->getValue().hasOneUse() &&
25319 ChainVal->getOpcode() == ISD::TokenFactor) {
25320 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25321 if (ChainVal->getOperand(i).getNode() == LdVal) {
25322 TokenFactorIndex = i;
25323 Ld = cast<LoadSDNode>(St->getValue());
25325 Ops.push_back(ChainVal->getOperand(i));
25329 if (!Ld || !ISD::isNormalLoad(Ld))
25332 // If this is not the MMX case, i.e. we are just turning i64 load/store
25333 // into f64 load/store, avoid the transformation if there are multiple
25334 // uses of the loaded value.
25335 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25340 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25341 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25343 if (Subtarget->is64Bit() || F64IsLegal) {
25344 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25345 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25346 Ld->getPointerInfo(), Ld->isVolatile(),
25347 Ld->isNonTemporal(), Ld->isInvariant(),
25348 Ld->getAlignment());
25349 SDValue NewChain = NewLd.getValue(1);
25350 if (TokenFactorIndex != -1) {
25351 Ops.push_back(NewChain);
25352 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25354 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25355 St->getPointerInfo(),
25356 St->isVolatile(), St->isNonTemporal(),
25357 St->getAlignment());
25360 // Otherwise, lower to two pairs of 32-bit loads / stores.
25361 SDValue LoAddr = Ld->getBasePtr();
25362 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25363 DAG.getConstant(4, LdDL, MVT::i32));
25365 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25366 Ld->getPointerInfo(),
25367 Ld->isVolatile(), Ld->isNonTemporal(),
25368 Ld->isInvariant(), Ld->getAlignment());
25369 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25370 Ld->getPointerInfo().getWithOffset(4),
25371 Ld->isVolatile(), Ld->isNonTemporal(),
25373 MinAlign(Ld->getAlignment(), 4));
25375 SDValue NewChain = LoLd.getValue(1);
25376 if (TokenFactorIndex != -1) {
25377 Ops.push_back(LoLd);
25378 Ops.push_back(HiLd);
25379 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25382 LoAddr = St->getBasePtr();
25383 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25384 DAG.getConstant(4, StDL, MVT::i32));
25386 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25387 St->getPointerInfo(),
25388 St->isVolatile(), St->isNonTemporal(),
25389 St->getAlignment());
25390 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25391 St->getPointerInfo().getWithOffset(4),
25393 St->isNonTemporal(),
25394 MinAlign(St->getAlignment(), 4));
25395 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25398 // This is similar to the above case, but here we handle a scalar 64-bit
25399 // integer store that is extracted from a vector on a 32-bit target.
25400 // If we have SSE2, then we can treat it like a floating-point double
25401 // to get past legalization. The execution dependencies fixup pass will
25402 // choose the optimal machine instruction for the store if this really is
25403 // an integer or v2f32 rather than an f64.
25404 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25405 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25406 SDValue OldExtract = St->getOperand(1);
25407 SDValue ExtOp0 = OldExtract.getOperand(0);
25408 unsigned VecSize = ExtOp0.getValueSizeInBits();
25409 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25410 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25411 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25412 BitCast, OldExtract.getOperand(1));
25413 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25414 St->getPointerInfo(), St->isVolatile(),
25415 St->isNonTemporal(), St->getAlignment());
25421 /// Return 'true' if this vector operation is "horizontal"
25422 /// and return the operands for the horizontal operation in LHS and RHS. A
25423 /// horizontal operation performs the binary operation on successive elements
25424 /// of its first operand, then on successive elements of its second operand,
25425 /// returning the resulting values in a vector. For example, if
25426 /// A = < float a0, float a1, float a2, float a3 >
25428 /// B = < float b0, float b1, float b2, float b3 >
25429 /// then the result of doing a horizontal operation on A and B is
25430 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25431 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25432 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25433 /// set to A, RHS to B, and the routine returns 'true'.
25434 /// Note that the binary operation should have the property that if one of the
25435 /// operands is UNDEF then the result is UNDEF.
25436 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25437 // Look for the following pattern: if
25438 // A = < float a0, float a1, float a2, float a3 >
25439 // B = < float b0, float b1, float b2, float b3 >
25441 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25442 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25443 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25444 // which is A horizontal-op B.
25446 // At least one of the operands should be a vector shuffle.
25447 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25448 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25451 MVT VT = LHS.getSimpleValueType();
25453 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25454 "Unsupported vector type for horizontal add/sub");
25456 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25457 // operate independently on 128-bit lanes.
25458 unsigned NumElts = VT.getVectorNumElements();
25459 unsigned NumLanes = VT.getSizeInBits()/128;
25460 unsigned NumLaneElts = NumElts / NumLanes;
25461 assert((NumLaneElts % 2 == 0) &&
25462 "Vector type should have an even number of elements in each lane");
25463 unsigned HalfLaneElts = NumLaneElts/2;
25465 // View LHS in the form
25466 // LHS = VECTOR_SHUFFLE A, B, LMask
25467 // If LHS is not a shuffle then pretend it is the shuffle
25468 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25469 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25472 SmallVector<int, 16> LMask(NumElts);
25473 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25474 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25475 A = LHS.getOperand(0);
25476 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25477 B = LHS.getOperand(1);
25478 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25479 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25481 if (LHS.getOpcode() != ISD::UNDEF)
25483 for (unsigned i = 0; i != NumElts; ++i)
25487 // Likewise, view RHS in the form
25488 // RHS = VECTOR_SHUFFLE C, D, RMask
25490 SmallVector<int, 16> RMask(NumElts);
25491 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25492 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25493 C = RHS.getOperand(0);
25494 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25495 D = RHS.getOperand(1);
25496 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25497 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25499 if (RHS.getOpcode() != ISD::UNDEF)
25501 for (unsigned i = 0; i != NumElts; ++i)
25505 // Check that the shuffles are both shuffling the same vectors.
25506 if (!(A == C && B == D) && !(A == D && B == C))
25509 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25510 if (!A.getNode() && !B.getNode())
25513 // If A and B occur in reverse order in RHS, then "swap" them (which means
25514 // rewriting the mask).
25516 ShuffleVectorSDNode::commuteMask(RMask);
25518 // At this point LHS and RHS are equivalent to
25519 // LHS = VECTOR_SHUFFLE A, B, LMask
25520 // RHS = VECTOR_SHUFFLE A, B, RMask
25521 // Check that the masks correspond to performing a horizontal operation.
25522 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25523 for (unsigned i = 0; i != NumLaneElts; ++i) {
25524 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25526 // Ignore any UNDEF components.
25527 if (LIdx < 0 || RIdx < 0 ||
25528 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25529 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25532 // Check that successive elements are being operated on. If not, this is
25533 // not a horizontal operation.
25534 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25535 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25536 if (!(LIdx == Index && RIdx == Index + 1) &&
25537 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25542 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25543 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25547 /// Do target-specific dag combines on floating point adds.
25548 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25549 const X86Subtarget *Subtarget) {
25550 EVT VT = N->getValueType(0);
25551 SDValue LHS = N->getOperand(0);
25552 SDValue RHS = N->getOperand(1);
25554 // Try to synthesize horizontal adds from adds of shuffles.
25555 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25556 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25557 isHorizontalBinOp(LHS, RHS, true))
25558 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25562 /// Do target-specific dag combines on floating point subs.
25563 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25564 const X86Subtarget *Subtarget) {
25565 EVT VT = N->getValueType(0);
25566 SDValue LHS = N->getOperand(0);
25567 SDValue RHS = N->getOperand(1);
25569 // Try to synthesize horizontal subs from subs of shuffles.
25570 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25571 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25572 isHorizontalBinOp(LHS, RHS, false))
25573 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25577 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25578 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25579 const X86Subtarget *Subtarget) {
25580 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25582 // F[X]OR(0.0, x) -> x
25583 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25584 if (C->getValueAPF().isPosZero())
25585 return N->getOperand(1);
25587 // F[X]OR(x, 0.0) -> x
25588 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25589 if (C->getValueAPF().isPosZero())
25590 return N->getOperand(0);
25592 EVT VT = N->getValueType(0);
25593 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25595 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25596 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25598 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25599 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25600 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25601 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25602 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25607 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25608 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25609 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25611 // Only perform optimizations if UnsafeMath is used.
25612 if (!DAG.getTarget().Options.UnsafeFPMath)
25615 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25616 // into FMINC and FMAXC, which are Commutative operations.
25617 unsigned NewOp = 0;
25618 switch (N->getOpcode()) {
25619 default: llvm_unreachable("unknown opcode");
25620 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25621 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25624 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25625 N->getOperand(0), N->getOperand(1));
25628 /// Do target-specific dag combines on X86ISD::FAND nodes.
25629 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25630 // FAND(0.0, x) -> 0.0
25631 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25632 if (C->getValueAPF().isPosZero())
25633 return N->getOperand(0);
25635 // FAND(x, 0.0) -> 0.0
25636 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25637 if (C->getValueAPF().isPosZero())
25638 return N->getOperand(1);
25643 /// Do target-specific dag combines on X86ISD::FANDN nodes
25644 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25645 // FANDN(0.0, x) -> x
25646 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25647 if (C->getValueAPF().isPosZero())
25648 return N->getOperand(1);
25650 // FANDN(x, 0.0) -> 0.0
25651 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25652 if (C->getValueAPF().isPosZero())
25653 return N->getOperand(1);
25658 static SDValue PerformBTCombine(SDNode *N,
25660 TargetLowering::DAGCombinerInfo &DCI) {
25661 // BT ignores high bits in the bit index operand.
25662 SDValue Op1 = N->getOperand(1);
25663 if (Op1.hasOneUse()) {
25664 unsigned BitWidth = Op1.getValueSizeInBits();
25665 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25666 APInt KnownZero, KnownOne;
25667 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25668 !DCI.isBeforeLegalizeOps());
25669 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25670 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25671 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25672 DCI.CommitTargetLoweringOpt(TLO);
25677 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25678 SDValue Op = N->getOperand(0);
25679 if (Op.getOpcode() == ISD::BITCAST)
25680 Op = Op.getOperand(0);
25681 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25682 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25683 VT.getVectorElementType().getSizeInBits() ==
25684 OpVT.getVectorElementType().getSizeInBits()) {
25685 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25690 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25691 const X86Subtarget *Subtarget) {
25692 EVT VT = N->getValueType(0);
25693 if (!VT.isVector())
25696 SDValue N0 = N->getOperand(0);
25697 SDValue N1 = N->getOperand(1);
25698 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25701 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25702 // both SSE and AVX2 since there is no sign-extended shift right
25703 // operation on a vector with 64-bit elements.
25704 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25705 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25706 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25707 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25708 SDValue N00 = N0.getOperand(0);
25710 // EXTLOAD has a better solution on AVX2,
25711 // it may be replaced with X86ISD::VSEXT node.
25712 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25713 if (!ISD::isNormalLoad(N00.getNode()))
25716 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25717 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25719 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25725 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25726 TargetLowering::DAGCombinerInfo &DCI,
25727 const X86Subtarget *Subtarget) {
25728 SDValue N0 = N->getOperand(0);
25729 EVT VT = N->getValueType(0);
25730 EVT SVT = VT.getScalarType();
25731 EVT InVT = N0.getValueType();
25732 EVT InSVT = InVT.getScalarType();
25735 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25736 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25737 // This exposes the sext to the sdivrem lowering, so that it directly extends
25738 // from AH (which we otherwise need to do contortions to access).
25739 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25740 InVT == MVT::i8 && VT == MVT::i32) {
25741 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25742 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25743 N0.getOperand(0), N0.getOperand(1));
25744 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25745 return R.getValue(1);
25748 if (!DCI.isBeforeLegalizeOps()) {
25749 if (InVT == MVT::i1) {
25750 SDValue Zero = DAG.getConstant(0, DL, VT);
25752 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25753 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25758 if (VT.isVector() && Subtarget->hasSSE2()) {
25759 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25760 EVT InVT = N.getValueType();
25761 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25762 Size / InVT.getScalarSizeInBits());
25763 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25764 DAG.getUNDEF(InVT));
25766 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25769 // If target-size is less than 128-bits, extend to a type that would extend
25770 // to 128 bits, extend that and extract the original target vector.
25771 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25772 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25773 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25774 unsigned Scale = 128 / VT.getSizeInBits();
25776 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25777 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25778 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25779 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25780 DAG.getIntPtrConstant(0, DL));
25783 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25784 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25785 if (VT.getSizeInBits() == 128 &&
25786 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25787 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25788 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25789 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25792 // On pre-AVX2 targets, split into 128-bit nodes of
25793 // ISD::SIGN_EXTEND_VECTOR_INREG.
25794 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25795 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25796 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25797 unsigned NumVecs = VT.getSizeInBits() / 128;
25798 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25799 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25800 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25802 SmallVector<SDValue, 8> Opnds;
25803 for (unsigned i = 0, Offset = 0; i != NumVecs;
25804 ++i, Offset += NumSubElts) {
25805 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25806 DAG.getIntPtrConstant(Offset, DL));
25807 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25808 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25809 Opnds.push_back(SrcVec);
25811 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
25815 if (Subtarget->hasAVX() && VT.isVector() && VT.getSizeInBits() == 256)
25816 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25822 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25823 const X86Subtarget* Subtarget) {
25825 EVT VT = N->getValueType(0);
25827 // Let legalize expand this if it isn't a legal type yet.
25828 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25831 EVT ScalarVT = VT.getScalarType();
25832 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25833 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
25834 !Subtarget->hasAVX512()))
25837 SDValue A = N->getOperand(0);
25838 SDValue B = N->getOperand(1);
25839 SDValue C = N->getOperand(2);
25841 bool NegA = (A.getOpcode() == ISD::FNEG);
25842 bool NegB = (B.getOpcode() == ISD::FNEG);
25843 bool NegC = (C.getOpcode() == ISD::FNEG);
25845 // Negative multiplication when NegA xor NegB
25846 bool NegMul = (NegA != NegB);
25848 A = A.getOperand(0);
25850 B = B.getOperand(0);
25852 C = C.getOperand(0);
25856 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25858 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25860 return DAG.getNode(Opcode, dl, VT, A, B, C);
25863 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25864 TargetLowering::DAGCombinerInfo &DCI,
25865 const X86Subtarget *Subtarget) {
25866 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25867 // (and (i32 x86isd::setcc_carry), 1)
25868 // This eliminates the zext. This transformation is necessary because
25869 // ISD::SETCC is always legalized to i8.
25871 SDValue N0 = N->getOperand(0);
25872 EVT VT = N->getValueType(0);
25874 if (N0.getOpcode() == ISD::AND &&
25876 N0.getOperand(0).hasOneUse()) {
25877 SDValue N00 = N0.getOperand(0);
25878 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25879 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25880 if (!C || C->getZExtValue() != 1)
25882 return DAG.getNode(ISD::AND, dl, VT,
25883 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25884 N00.getOperand(0), N00.getOperand(1)),
25885 DAG.getConstant(1, dl, VT));
25889 if (N0.getOpcode() == ISD::TRUNCATE &&
25891 N0.getOperand(0).hasOneUse()) {
25892 SDValue N00 = N0.getOperand(0);
25893 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25894 return DAG.getNode(ISD::AND, dl, VT,
25895 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25896 N00.getOperand(0), N00.getOperand(1)),
25897 DAG.getConstant(1, dl, VT));
25901 if (VT.is256BitVector())
25902 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25905 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25906 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25907 // This exposes the zext to the udivrem lowering, so that it directly extends
25908 // from AH (which we otherwise need to do contortions to access).
25909 if (N0.getOpcode() == ISD::UDIVREM &&
25910 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25911 (VT == MVT::i32 || VT == MVT::i64)) {
25912 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25913 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25914 N0.getOperand(0), N0.getOperand(1));
25915 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25916 return R.getValue(1);
25922 // Optimize x == -y --> x+y == 0
25923 // x != -y --> x+y != 0
25924 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25925 const X86Subtarget* Subtarget) {
25926 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25927 SDValue LHS = N->getOperand(0);
25928 SDValue RHS = N->getOperand(1);
25929 EVT VT = N->getValueType(0);
25932 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25933 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25934 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25935 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
25936 LHS.getOperand(1));
25937 return DAG.getSetCC(DL, N->getValueType(0), addV,
25938 DAG.getConstant(0, DL, addV.getValueType()), CC);
25940 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25941 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25942 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25943 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
25944 RHS.getOperand(1));
25945 return DAG.getSetCC(DL, N->getValueType(0), addV,
25946 DAG.getConstant(0, DL, addV.getValueType()), CC);
25949 if (VT.getScalarType() == MVT::i1 &&
25950 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
25952 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25953 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25954 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25956 if (!IsSEXT0 || !IsVZero1) {
25957 // Swap the operands and update the condition code.
25958 std::swap(LHS, RHS);
25959 CC = ISD::getSetCCSwappedOperands(CC);
25961 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25962 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25963 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25966 if (IsSEXT0 && IsVZero1) {
25967 assert(VT == LHS.getOperand(0).getValueType() &&
25968 "Uexpected operand type");
25969 if (CC == ISD::SETGT)
25970 return DAG.getConstant(0, DL, VT);
25971 if (CC == ISD::SETLE)
25972 return DAG.getConstant(1, DL, VT);
25973 if (CC == ISD::SETEQ || CC == ISD::SETGE)
25974 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25976 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
25977 "Unexpected condition code!");
25978 return LHS.getOperand(0);
25985 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
25986 SelectionDAG &DAG) {
25988 MVT VT = Load->getSimpleValueType(0);
25989 MVT EVT = VT.getVectorElementType();
25990 SDValue Addr = Load->getOperand(1);
25991 SDValue NewAddr = DAG.getNode(
25992 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
25993 DAG.getConstant(Index * EVT.getStoreSize(), dl,
25994 Addr.getSimpleValueType()));
25997 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
25998 DAG.getMachineFunction().getMachineMemOperand(
25999 Load->getMemOperand(), 0, EVT.getStoreSize()));
26003 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
26004 const X86Subtarget *Subtarget) {
26006 MVT VT = N->getOperand(1)->getSimpleValueType(0);
26007 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
26008 "X86insertps is only defined for v4x32");
26010 SDValue Ld = N->getOperand(1);
26011 if (MayFoldLoad(Ld)) {
26012 // Extract the countS bits from the immediate so we can get the proper
26013 // address when narrowing the vector load to a specific element.
26014 // When the second source op is a memory address, insertps doesn't use
26015 // countS and just gets an f32 from that address.
26016 unsigned DestIndex =
26017 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
26019 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
26021 // Create this as a scalar to vector to match the instruction pattern.
26022 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
26023 // countS bits are ignored when loading from memory on insertps, which
26024 // means we don't need to explicitly set them to 0.
26025 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
26026 LoadScalarToVector, N->getOperand(2));
26031 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26032 SDValue V0 = N->getOperand(0);
26033 SDValue V1 = N->getOperand(1);
26035 EVT VT = N->getValueType(0);
26037 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26038 // operands and changing the mask to 1. This saves us a bunch of
26039 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26040 // x86InstrInfo knows how to commute this back after instruction selection
26041 // if it would help register allocation.
26043 // TODO: If optimizing for size or a processor that doesn't suffer from
26044 // partial register update stalls, this should be transformed into a MOVSD
26045 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26047 if (VT == MVT::v2f64)
26048 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26049 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26050 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26051 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26057 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26058 // as "sbb reg,reg", since it can be extended without zext and produces
26059 // an all-ones bit which is more useful than 0/1 in some cases.
26060 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26063 return DAG.getNode(ISD::AND, DL, VT,
26064 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26065 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26067 DAG.getConstant(1, DL, VT));
26068 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26069 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26070 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26071 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26075 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26076 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26077 TargetLowering::DAGCombinerInfo &DCI,
26078 const X86Subtarget *Subtarget) {
26080 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26081 SDValue EFLAGS = N->getOperand(1);
26083 if (CC == X86::COND_A) {
26084 // Try to convert COND_A into COND_B in an attempt to facilitate
26085 // materializing "setb reg".
26087 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26088 // cannot take an immediate as its first operand.
26090 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26091 EFLAGS.getValueType().isInteger() &&
26092 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26093 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26094 EFLAGS.getNode()->getVTList(),
26095 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26096 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26097 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26101 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26102 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26104 if (CC == X86::COND_B)
26105 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26107 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26108 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26109 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26115 // Optimize branch condition evaluation.
26117 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26118 TargetLowering::DAGCombinerInfo &DCI,
26119 const X86Subtarget *Subtarget) {
26121 SDValue Chain = N->getOperand(0);
26122 SDValue Dest = N->getOperand(1);
26123 SDValue EFLAGS = N->getOperand(3);
26124 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26126 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26127 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26128 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26135 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26136 SelectionDAG &DAG) {
26137 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26138 // optimize away operation when it's from a constant.
26140 // The general transformation is:
26141 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26142 // AND(VECTOR_CMP(x,y), constant2)
26143 // constant2 = UNARYOP(constant)
26145 // Early exit if this isn't a vector operation, the operand of the
26146 // unary operation isn't a bitwise AND, or if the sizes of the operations
26147 // aren't the same.
26148 EVT VT = N->getValueType(0);
26149 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26150 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26151 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26154 // Now check that the other operand of the AND is a constant. We could
26155 // make the transformation for non-constant splats as well, but it's unclear
26156 // that would be a benefit as it would not eliminate any operations, just
26157 // perform one more step in scalar code before moving to the vector unit.
26158 if (BuildVectorSDNode *BV =
26159 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26160 // Bail out if the vector isn't a constant.
26161 if (!BV->isConstant())
26164 // Everything checks out. Build up the new and improved node.
26166 EVT IntVT = BV->getValueType(0);
26167 // Create a new constant of the appropriate type for the transformed
26169 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26170 // The AND node needs bitcasts to/from an integer vector type around it.
26171 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26172 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26173 N->getOperand(0)->getOperand(0), MaskConst);
26174 SDValue Res = DAG.getBitcast(VT, NewAnd);
26181 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26182 const X86Subtarget *Subtarget) {
26183 SDValue Op0 = N->getOperand(0);
26184 EVT VT = N->getValueType(0);
26185 EVT InVT = Op0.getValueType();
26186 EVT InSVT = InVT.getScalarType();
26187 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26189 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26190 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26191 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26193 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26194 InVT.getVectorNumElements());
26195 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26197 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26198 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26200 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26206 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26207 const X86Subtarget *Subtarget) {
26208 // First try to optimize away the conversion entirely when it's
26209 // conditionally from a constant. Vectors only.
26210 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26213 // Now move on to more general possibilities.
26214 SDValue Op0 = N->getOperand(0);
26215 EVT VT = N->getValueType(0);
26216 EVT InVT = Op0.getValueType();
26217 EVT InSVT = InVT.getScalarType();
26219 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26220 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26221 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26223 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26224 InVT.getVectorNumElements());
26225 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26226 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26229 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26230 // a 32-bit target where SSE doesn't support i64->FP operations.
26231 if (Op0.getOpcode() == ISD::LOAD) {
26232 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26233 EVT LdVT = Ld->getValueType(0);
26235 // This transformation is not supported if the result type is f16
26236 if (VT == MVT::f16)
26239 if (!Ld->isVolatile() && !VT.isVector() &&
26240 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26241 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26242 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26243 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26244 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26251 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26252 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26253 X86TargetLowering::DAGCombinerInfo &DCI) {
26254 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26255 // the result is either zero or one (depending on the input carry bit).
26256 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26257 if (X86::isZeroNode(N->getOperand(0)) &&
26258 X86::isZeroNode(N->getOperand(1)) &&
26259 // We don't have a good way to replace an EFLAGS use, so only do this when
26261 SDValue(N, 1).use_empty()) {
26263 EVT VT = N->getValueType(0);
26264 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26265 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26266 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26267 DAG.getConstant(X86::COND_B, DL,
26270 DAG.getConstant(1, DL, VT));
26271 return DCI.CombineTo(N, Res1, CarryOut);
26277 // fold (add Y, (sete X, 0)) -> adc 0, Y
26278 // (add Y, (setne X, 0)) -> sbb -1, Y
26279 // (sub (sete X, 0), Y) -> sbb 0, Y
26280 // (sub (setne X, 0), Y) -> adc -1, Y
26281 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26284 // Look through ZExts.
26285 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26286 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26289 SDValue SetCC = Ext.getOperand(0);
26290 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26293 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26294 if (CC != X86::COND_E && CC != X86::COND_NE)
26297 SDValue Cmp = SetCC.getOperand(1);
26298 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26299 !X86::isZeroNode(Cmp.getOperand(1)) ||
26300 !Cmp.getOperand(0).getValueType().isInteger())
26303 SDValue CmpOp0 = Cmp.getOperand(0);
26304 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26305 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26307 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26308 if (CC == X86::COND_NE)
26309 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26310 DL, OtherVal.getValueType(), OtherVal,
26311 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26313 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26314 DL, OtherVal.getValueType(), OtherVal,
26315 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26318 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26319 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26320 const X86Subtarget *Subtarget) {
26321 EVT VT = N->getValueType(0);
26322 SDValue Op0 = N->getOperand(0);
26323 SDValue Op1 = N->getOperand(1);
26325 // Try to synthesize horizontal adds from adds of shuffles.
26326 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26327 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26328 isHorizontalBinOp(Op0, Op1, true))
26329 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26331 return OptimizeConditionalInDecrement(N, DAG);
26334 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26335 const X86Subtarget *Subtarget) {
26336 SDValue Op0 = N->getOperand(0);
26337 SDValue Op1 = N->getOperand(1);
26339 // X86 can't encode an immediate LHS of a sub. See if we can push the
26340 // negation into a preceding instruction.
26341 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26342 // If the RHS of the sub is a XOR with one use and a constant, invert the
26343 // immediate. Then add one to the LHS of the sub so we can turn
26344 // X-Y -> X+~Y+1, saving one register.
26345 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26346 isa<ConstantSDNode>(Op1.getOperand(1))) {
26347 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26348 EVT VT = Op0.getValueType();
26349 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26351 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26352 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26353 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26357 // Try to synthesize horizontal adds from adds of shuffles.
26358 EVT VT = N->getValueType(0);
26359 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26360 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26361 isHorizontalBinOp(Op0, Op1, true))
26362 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26364 return OptimizeConditionalInDecrement(N, DAG);
26367 /// performVZEXTCombine - Performs build vector combines
26368 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26369 TargetLowering::DAGCombinerInfo &DCI,
26370 const X86Subtarget *Subtarget) {
26372 MVT VT = N->getSimpleValueType(0);
26373 SDValue Op = N->getOperand(0);
26374 MVT OpVT = Op.getSimpleValueType();
26375 MVT OpEltVT = OpVT.getVectorElementType();
26376 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26378 // (vzext (bitcast (vzext (x)) -> (vzext x)
26380 while (V.getOpcode() == ISD::BITCAST)
26381 V = V.getOperand(0);
26383 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26384 MVT InnerVT = V.getSimpleValueType();
26385 MVT InnerEltVT = InnerVT.getVectorElementType();
26387 // If the element sizes match exactly, we can just do one larger vzext. This
26388 // is always an exact type match as vzext operates on integer types.
26389 if (OpEltVT == InnerEltVT) {
26390 assert(OpVT == InnerVT && "Types must match for vzext!");
26391 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26394 // The only other way we can combine them is if only a single element of the
26395 // inner vzext is used in the input to the outer vzext.
26396 if (InnerEltVT.getSizeInBits() < InputBits)
26399 // In this case, the inner vzext is completely dead because we're going to
26400 // only look at bits inside of the low element. Just do the outer vzext on
26401 // a bitcast of the input to the inner.
26402 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26405 // Check if we can bypass extracting and re-inserting an element of an input
26406 // vector. Essentially:
26407 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26408 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26409 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26410 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26411 SDValue ExtractedV = V.getOperand(0);
26412 SDValue OrigV = ExtractedV.getOperand(0);
26413 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26414 if (ExtractIdx->getZExtValue() == 0) {
26415 MVT OrigVT = OrigV.getSimpleValueType();
26416 // Extract a subvector if necessary...
26417 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26418 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26419 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26420 OrigVT.getVectorNumElements() / Ratio);
26421 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26422 DAG.getIntPtrConstant(0, DL));
26424 Op = DAG.getBitcast(OpVT, OrigV);
26425 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26432 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26433 DAGCombinerInfo &DCI) const {
26434 SelectionDAG &DAG = DCI.DAG;
26435 switch (N->getOpcode()) {
26437 case ISD::EXTRACT_VECTOR_ELT:
26438 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26441 case X86ISD::SHRUNKBLEND:
26442 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26443 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26444 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26445 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26446 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26447 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26448 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26451 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26452 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26453 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26454 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26455 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26456 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26457 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26458 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26459 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26460 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26461 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26462 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26464 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26466 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26467 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26468 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26469 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26470 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26471 case ISD::ANY_EXTEND:
26472 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26473 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26474 case ISD::SIGN_EXTEND_INREG:
26475 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26476 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26477 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26478 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26479 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26480 case X86ISD::SHUFP: // Handle all target specific shuffles
26481 case X86ISD::PALIGNR:
26482 case X86ISD::UNPCKH:
26483 case X86ISD::UNPCKL:
26484 case X86ISD::MOVHLPS:
26485 case X86ISD::MOVLHPS:
26486 case X86ISD::PSHUFB:
26487 case X86ISD::PSHUFD:
26488 case X86ISD::PSHUFHW:
26489 case X86ISD::PSHUFLW:
26490 case X86ISD::MOVSS:
26491 case X86ISD::MOVSD:
26492 case X86ISD::VPERMILPI:
26493 case X86ISD::VPERM2X128:
26494 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26495 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26496 case X86ISD::INSERTPS: {
26497 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26498 return PerformINSERTPSCombine(N, DAG, Subtarget);
26501 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26507 /// isTypeDesirableForOp - Return true if the target has native support for
26508 /// the specified value type and it is 'desirable' to use the type for the
26509 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26510 /// instruction encodings are longer and some i16 instructions are slow.
26511 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26512 if (!isTypeLegal(VT))
26514 if (VT != MVT::i16)
26521 case ISD::SIGN_EXTEND:
26522 case ISD::ZERO_EXTEND:
26523 case ISD::ANY_EXTEND:
26536 /// IsDesirableToPromoteOp - This method query the target whether it is
26537 /// beneficial for dag combiner to promote the specified node. If true, it
26538 /// should return the desired promotion type by reference.
26539 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26540 EVT VT = Op.getValueType();
26541 if (VT != MVT::i16)
26544 bool Promote = false;
26545 bool Commute = false;
26546 switch (Op.getOpcode()) {
26549 LoadSDNode *LD = cast<LoadSDNode>(Op);
26550 // If the non-extending load has a single use and it's not live out, then it
26551 // might be folded.
26552 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26553 Op.hasOneUse()*/) {
26554 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26555 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26556 // The only case where we'd want to promote LOAD (rather then it being
26557 // promoted as an operand is when it's only use is liveout.
26558 if (UI->getOpcode() != ISD::CopyToReg)
26565 case ISD::SIGN_EXTEND:
26566 case ISD::ZERO_EXTEND:
26567 case ISD::ANY_EXTEND:
26572 SDValue N0 = Op.getOperand(0);
26573 // Look out for (store (shl (load), x)).
26574 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26587 SDValue N0 = Op.getOperand(0);
26588 SDValue N1 = Op.getOperand(1);
26589 if (!Commute && MayFoldLoad(N1))
26591 // Avoid disabling potential load folding opportunities.
26592 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26594 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26604 //===----------------------------------------------------------------------===//
26605 // X86 Inline Assembly Support
26606 //===----------------------------------------------------------------------===//
26608 // Helper to match a string separated by whitespace.
26609 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26610 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26612 for (StringRef Piece : Pieces) {
26613 if (!S.startswith(Piece)) // Check if the piece matches.
26616 S = S.substr(Piece.size());
26617 StringRef::size_type Pos = S.find_first_not_of(" \t");
26618 if (Pos == 0) // We matched a prefix.
26627 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26629 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26630 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26631 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26632 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26634 if (AsmPieces.size() == 3)
26636 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26643 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26644 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26646 std::string AsmStr = IA->getAsmString();
26648 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26649 if (!Ty || Ty->getBitWidth() % 16 != 0)
26652 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26653 SmallVector<StringRef, 4> AsmPieces;
26654 SplitString(AsmStr, AsmPieces, ";\n");
26656 switch (AsmPieces.size()) {
26657 default: return false;
26659 // FIXME: this should verify that we are targeting a 486 or better. If not,
26660 // we will turn this bswap into something that will be lowered to logical
26661 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26662 // lower so don't worry about this.
26664 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26665 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26666 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26667 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26668 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26669 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26670 // No need to check constraints, nothing other than the equivalent of
26671 // "=r,0" would be valid here.
26672 return IntrinsicLowering::LowerToByteSwap(CI);
26675 // rorw $$8, ${0:w} --> llvm.bswap.i16
26676 if (CI->getType()->isIntegerTy(16) &&
26677 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26678 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26679 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26681 StringRef ConstraintsStr = IA->getConstraintString();
26682 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26683 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26684 if (clobbersFlagRegisters(AsmPieces))
26685 return IntrinsicLowering::LowerToByteSwap(CI);
26689 if (CI->getType()->isIntegerTy(32) &&
26690 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26691 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26692 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26693 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26695 StringRef ConstraintsStr = IA->getConstraintString();
26696 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26697 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26698 if (clobbersFlagRegisters(AsmPieces))
26699 return IntrinsicLowering::LowerToByteSwap(CI);
26702 if (CI->getType()->isIntegerTy(64)) {
26703 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26704 if (Constraints.size() >= 2 &&
26705 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26706 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26707 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26708 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26709 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26710 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26711 return IntrinsicLowering::LowerToByteSwap(CI);
26719 /// getConstraintType - Given a constraint letter, return the type of
26720 /// constraint it is for this target.
26721 X86TargetLowering::ConstraintType
26722 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26723 if (Constraint.size() == 1) {
26724 switch (Constraint[0]) {
26735 return C_RegisterClass;
26759 return TargetLowering::getConstraintType(Constraint);
26762 /// Examine constraint type and operand type and determine a weight value.
26763 /// This object must already have been set up with the operand type
26764 /// and the current alternative constraint selected.
26765 TargetLowering::ConstraintWeight
26766 X86TargetLowering::getSingleConstraintMatchWeight(
26767 AsmOperandInfo &info, const char *constraint) const {
26768 ConstraintWeight weight = CW_Invalid;
26769 Value *CallOperandVal = info.CallOperandVal;
26770 // If we don't have a value, we can't do a match,
26771 // but allow it at the lowest weight.
26772 if (!CallOperandVal)
26774 Type *type = CallOperandVal->getType();
26775 // Look at the constraint type.
26776 switch (*constraint) {
26778 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26789 if (CallOperandVal->getType()->isIntegerTy())
26790 weight = CW_SpecificReg;
26795 if (type->isFloatingPointTy())
26796 weight = CW_SpecificReg;
26799 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26800 weight = CW_SpecificReg;
26804 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26805 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26806 weight = CW_Register;
26809 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26810 if (C->getZExtValue() <= 31)
26811 weight = CW_Constant;
26815 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26816 if (C->getZExtValue() <= 63)
26817 weight = CW_Constant;
26821 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26822 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26823 weight = CW_Constant;
26827 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26828 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26829 weight = CW_Constant;
26833 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26834 if (C->getZExtValue() <= 3)
26835 weight = CW_Constant;
26839 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26840 if (C->getZExtValue() <= 0xff)
26841 weight = CW_Constant;
26846 if (isa<ConstantFP>(CallOperandVal)) {
26847 weight = CW_Constant;
26851 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26852 if ((C->getSExtValue() >= -0x80000000LL) &&
26853 (C->getSExtValue() <= 0x7fffffffLL))
26854 weight = CW_Constant;
26858 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26859 if (C->getZExtValue() <= 0xffffffff)
26860 weight = CW_Constant;
26867 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26868 /// with another that has more specific requirements based on the type of the
26869 /// corresponding operand.
26870 const char *X86TargetLowering::
26871 LowerXConstraint(EVT ConstraintVT) const {
26872 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26873 // 'f' like normal targets.
26874 if (ConstraintVT.isFloatingPoint()) {
26875 if (Subtarget->hasSSE2())
26877 if (Subtarget->hasSSE1())
26881 return TargetLowering::LowerXConstraint(ConstraintVT);
26884 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26885 /// vector. If it is invalid, don't add anything to Ops.
26886 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26887 std::string &Constraint,
26888 std::vector<SDValue>&Ops,
26889 SelectionDAG &DAG) const {
26892 // Only support length 1 constraints for now.
26893 if (Constraint.length() > 1) return;
26895 char ConstraintLetter = Constraint[0];
26896 switch (ConstraintLetter) {
26899 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26900 if (C->getZExtValue() <= 31) {
26901 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26902 Op.getValueType());
26908 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26909 if (C->getZExtValue() <= 63) {
26910 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26911 Op.getValueType());
26917 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26918 if (isInt<8>(C->getSExtValue())) {
26919 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26920 Op.getValueType());
26926 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26927 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26928 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26929 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
26930 Op.getValueType());
26936 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26937 if (C->getZExtValue() <= 3) {
26938 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26939 Op.getValueType());
26945 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26946 if (C->getZExtValue() <= 255) {
26947 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26948 Op.getValueType());
26954 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26955 if (C->getZExtValue() <= 127) {
26956 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26957 Op.getValueType());
26963 // 32-bit signed value
26964 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26965 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26966 C->getSExtValue())) {
26967 // Widen to 64 bits here to get it sign extended.
26968 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
26971 // FIXME gcc accepts some relocatable values here too, but only in certain
26972 // memory models; it's complicated.
26977 // 32-bit unsigned value
26978 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26979 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26980 C->getZExtValue())) {
26981 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26982 Op.getValueType());
26986 // FIXME gcc accepts some relocatable values here too, but only in certain
26987 // memory models; it's complicated.
26991 // Literal immediates are always ok.
26992 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26993 // Widen to 64 bits here to get it sign extended.
26994 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
26998 // In any sort of PIC mode addresses need to be computed at runtime by
26999 // adding in a register or some sort of table lookup. These can't
27000 // be used as immediates.
27001 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27004 // If we are in non-pic codegen mode, we allow the address of a global (with
27005 // an optional displacement) to be used with 'i'.
27006 GlobalAddressSDNode *GA = nullptr;
27007 int64_t Offset = 0;
27009 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27011 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27012 Offset += GA->getOffset();
27014 } else if (Op.getOpcode() == ISD::ADD) {
27015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27016 Offset += C->getZExtValue();
27017 Op = Op.getOperand(0);
27020 } else if (Op.getOpcode() == ISD::SUB) {
27021 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27022 Offset += -C->getZExtValue();
27023 Op = Op.getOperand(0);
27028 // Otherwise, this isn't something we can handle, reject it.
27032 const GlobalValue *GV = GA->getGlobal();
27033 // If we require an extra load to get this address, as in PIC mode, we
27034 // can't accept it.
27035 if (isGlobalStubReference(
27036 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27039 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27040 GA->getValueType(0), Offset);
27045 if (Result.getNode()) {
27046 Ops.push_back(Result);
27049 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27052 std::pair<unsigned, const TargetRegisterClass *>
27053 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27054 StringRef Constraint,
27056 // First, see if this is a constraint that directly corresponds to an LLVM
27058 if (Constraint.size() == 1) {
27059 // GCC Constraint Letters
27060 switch (Constraint[0]) {
27062 // TODO: Slight differences here in allocation order and leaving
27063 // RIP in the class. Do they matter any more here than they do
27064 // in the normal allocation?
27065 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27066 if (Subtarget->is64Bit()) {
27067 if (VT == MVT::i32 || VT == MVT::f32)
27068 return std::make_pair(0U, &X86::GR32RegClass);
27069 if (VT == MVT::i16)
27070 return std::make_pair(0U, &X86::GR16RegClass);
27071 if (VT == MVT::i8 || VT == MVT::i1)
27072 return std::make_pair(0U, &X86::GR8RegClass);
27073 if (VT == MVT::i64 || VT == MVT::f64)
27074 return std::make_pair(0U, &X86::GR64RegClass);
27077 // 32-bit fallthrough
27078 case 'Q': // Q_REGS
27079 if (VT == MVT::i32 || VT == MVT::f32)
27080 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27081 if (VT == MVT::i16)
27082 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27083 if (VT == MVT::i8 || VT == MVT::i1)
27084 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27085 if (VT == MVT::i64)
27086 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27088 case 'r': // GENERAL_REGS
27089 case 'l': // INDEX_REGS
27090 if (VT == MVT::i8 || VT == MVT::i1)
27091 return std::make_pair(0U, &X86::GR8RegClass);
27092 if (VT == MVT::i16)
27093 return std::make_pair(0U, &X86::GR16RegClass);
27094 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27095 return std::make_pair(0U, &X86::GR32RegClass);
27096 return std::make_pair(0U, &X86::GR64RegClass);
27097 case 'R': // LEGACY_REGS
27098 if (VT == MVT::i8 || VT == MVT::i1)
27099 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27100 if (VT == MVT::i16)
27101 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27102 if (VT == MVT::i32 || !Subtarget->is64Bit())
27103 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27104 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27105 case 'f': // FP Stack registers.
27106 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27107 // value to the correct fpstack register class.
27108 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27109 return std::make_pair(0U, &X86::RFP32RegClass);
27110 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27111 return std::make_pair(0U, &X86::RFP64RegClass);
27112 return std::make_pair(0U, &X86::RFP80RegClass);
27113 case 'y': // MMX_REGS if MMX allowed.
27114 if (!Subtarget->hasMMX()) break;
27115 return std::make_pair(0U, &X86::VR64RegClass);
27116 case 'Y': // SSE_REGS if SSE2 allowed
27117 if (!Subtarget->hasSSE2()) break;
27119 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27120 if (!Subtarget->hasSSE1()) break;
27122 switch (VT.SimpleTy) {
27124 // Scalar SSE types.
27127 return std::make_pair(0U, &X86::FR32RegClass);
27130 return std::make_pair(0U, &X86::FR64RegClass);
27138 return std::make_pair(0U, &X86::VR128RegClass);
27146 return std::make_pair(0U, &X86::VR256RegClass);
27151 return std::make_pair(0U, &X86::VR512RegClass);
27157 // Use the default implementation in TargetLowering to convert the register
27158 // constraint into a member of a register class.
27159 std::pair<unsigned, const TargetRegisterClass*> Res;
27160 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27162 // Not found as a standard register?
27164 // Map st(0) -> st(7) -> ST0
27165 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27166 tolower(Constraint[1]) == 's' &&
27167 tolower(Constraint[2]) == 't' &&
27168 Constraint[3] == '(' &&
27169 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27170 Constraint[5] == ')' &&
27171 Constraint[6] == '}') {
27173 Res.first = X86::FP0+Constraint[4]-'0';
27174 Res.second = &X86::RFP80RegClass;
27178 // GCC allows "st(0)" to be called just plain "st".
27179 if (StringRef("{st}").equals_lower(Constraint)) {
27180 Res.first = X86::FP0;
27181 Res.second = &X86::RFP80RegClass;
27186 if (StringRef("{flags}").equals_lower(Constraint)) {
27187 Res.first = X86::EFLAGS;
27188 Res.second = &X86::CCRRegClass;
27192 // 'A' means EAX + EDX.
27193 if (Constraint == "A") {
27194 Res.first = X86::EAX;
27195 Res.second = &X86::GR32_ADRegClass;
27201 // Otherwise, check to see if this is a register class of the wrong value
27202 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27203 // turn into {ax},{dx}.
27204 // MVT::Other is used to specify clobber names.
27205 if (Res.second->hasType(VT) || VT == MVT::Other)
27206 return Res; // Correct type already, nothing to do.
27208 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27209 // return "eax". This should even work for things like getting 64bit integer
27210 // registers when given an f64 type.
27211 const TargetRegisterClass *Class = Res.second;
27212 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27213 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27214 unsigned Size = VT.getSizeInBits();
27215 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27216 : Size == 16 ? MVT::i16
27217 : Size == 32 ? MVT::i32
27218 : Size == 64 ? MVT::i64
27220 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27222 Res.first = DestReg;
27223 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27224 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27225 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27226 : &X86::GR64RegClass;
27227 assert(Res.second->contains(Res.first) && "Register in register class");
27229 // No register found/type mismatch.
27231 Res.second = nullptr;
27233 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27234 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27235 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27236 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27237 Class == &X86::VR512RegClass) {
27238 // Handle references to XMM physical registers that got mapped into the
27239 // wrong class. This can happen with constraints like {xmm0} where the
27240 // target independent register mapper will just pick the first match it can
27241 // find, ignoring the required type.
27243 if (VT == MVT::f32 || VT == MVT::i32)
27244 Res.second = &X86::FR32RegClass;
27245 else if (VT == MVT::f64 || VT == MVT::i64)
27246 Res.second = &X86::FR64RegClass;
27247 else if (X86::VR128RegClass.hasType(VT))
27248 Res.second = &X86::VR128RegClass;
27249 else if (X86::VR256RegClass.hasType(VT))
27250 Res.second = &X86::VR256RegClass;
27251 else if (X86::VR512RegClass.hasType(VT))
27252 Res.second = &X86::VR512RegClass;
27254 // Type mismatch and not a clobber: Return an error;
27256 Res.second = nullptr;
27263 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27264 const AddrMode &AM, Type *Ty,
27265 unsigned AS) const {
27266 // Scaling factors are not free at all.
27267 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27268 // will take 2 allocations in the out of order engine instead of 1
27269 // for plain addressing mode, i.e. inst (reg1).
27271 // vaddps (%rsi,%drx), %ymm0, %ymm1
27272 // Requires two allocations (one for the load, one for the computation)
27274 // vaddps (%rsi), %ymm0, %ymm1
27275 // Requires just 1 allocation, i.e., freeing allocations for other operations
27276 // and having less micro operations to execute.
27278 // For some X86 architectures, this is even worse because for instance for
27279 // stores, the complex addressing mode forces the instruction to use the
27280 // "load" ports instead of the dedicated "store" port.
27281 // E.g., on Haswell:
27282 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27283 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27284 if (isLegalAddressingMode(DL, AM, Ty, AS))
27285 // Scale represents reg2 * scale, thus account for 1
27286 // as soon as we use a second register.
27287 return AM.Scale != 0;
27291 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27292 // Integer division on x86 is expensive. However, when aggressively optimizing
27293 // for code size, we prefer to use a div instruction, as it is usually smaller
27294 // than the alternative sequence.
27295 // The exception to this is vector division. Since x86 doesn't have vector
27296 // integer division, leaving the division as-is is a loss even in terms of
27297 // size, because it will have to be scalarized, while the alternative code
27298 // sequence can be performed in vector form.
27299 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27300 Attribute::MinSize);
27301 return OptSize && !VT.isVector();