1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit bounday. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
177 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
178 unsigned IdxVal, SelectionDAG &DAG,
180 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
181 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
184 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
185 /// instructions. This is used because creating CONCAT_VECTOR nodes of
186 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
187 /// large BUILD_VECTORS.
188 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
195 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
196 unsigned NumElems, SelectionDAG &DAG,
198 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
199 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
202 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
203 if (TT.isOSBinFormatMachO()) {
204 if (TT.getArch() == Triple::x86_64)
205 return new X86_64MachoTargetObjectFile();
206 return new TargetLoweringObjectFileMachO();
210 return new X86LinuxTargetObjectFile();
211 if (TT.isOSBinFormatELF())
212 return new TargetLoweringObjectFileELF();
213 if (TT.isKnownWindowsMSVCEnvironment())
214 return new X86WindowsTargetObjectFile();
215 if (TT.isOSBinFormatCOFF())
216 return new TargetLoweringObjectFileCOFF();
217 llvm_unreachable("unknown subtarget type");
220 // FIXME: This should stop caching the target machine as soon as
221 // we can remove resetOperationActions et al.
222 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
223 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
224 Subtarget = &TM.getSubtarget<X86Subtarget>();
225 X86ScalarSSEf64 = Subtarget->hasSSE2();
226 X86ScalarSSEf32 = Subtarget->hasSSE1();
227 TD = getDataLayout();
229 resetOperationActions();
232 void X86TargetLowering::resetOperationActions() {
233 const TargetMachine &TM = getTargetMachine();
234 static bool FirstTimeThrough = true;
236 // If none of the target options have changed, then we don't need to reset the
237 // operation actions.
238 if (!FirstTimeThrough && TO == TM.Options) return;
240 if (!FirstTimeThrough) {
241 // Reinitialize the actions.
243 FirstTimeThrough = false;
248 // Set up the TargetLowering object.
249 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
251 // X86 is weird, it always uses i8 for shift amounts and setcc results.
252 setBooleanContents(ZeroOrOneBooleanContent);
253 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
254 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
256 // For 64-bit since we have so many registers use the ILP scheduler, for
257 // 32-bit code use the register pressure specific scheduling.
258 // For Atom, always use ILP scheduling.
259 if (Subtarget->isAtom())
260 setSchedulingPreference(Sched::ILP);
261 else if (Subtarget->is64Bit())
262 setSchedulingPreference(Sched::ILP);
264 setSchedulingPreference(Sched::RegPressure);
265 const X86RegisterInfo *RegInfo =
266 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
267 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
269 // Bypass expensive divides on Atom when compiling with O2
270 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
271 addBypassSlowDiv(32, 8);
272 if (Subtarget->is64Bit())
273 addBypassSlowDiv(64, 16);
276 if (Subtarget->isTargetKnownWindowsMSVC()) {
277 // Setup Windows compiler runtime calls.
278 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
279 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
280 setLibcallName(RTLIB::SREM_I64, "_allrem");
281 setLibcallName(RTLIB::UREM_I64, "_aullrem");
282 setLibcallName(RTLIB::MUL_I64, "_allmul");
283 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
284 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
285 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
286 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
287 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
289 // The _ftol2 runtime function has an unusual calling conv, which
290 // is modeled by a special pseudo-instruction.
291 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
292 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
293 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
294 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
297 if (Subtarget->isTargetDarwin()) {
298 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
299 setUseUnderscoreSetJmp(false);
300 setUseUnderscoreLongJmp(false);
301 } else if (Subtarget->isTargetWindowsGNU()) {
302 // MS runtime is weird: it exports _setjmp, but longjmp!
303 setUseUnderscoreSetJmp(true);
304 setUseUnderscoreLongJmp(false);
306 setUseUnderscoreSetJmp(true);
307 setUseUnderscoreLongJmp(true);
310 // Set up the register classes.
311 addRegisterClass(MVT::i8, &X86::GR8RegClass);
312 addRegisterClass(MVT::i16, &X86::GR16RegClass);
313 addRegisterClass(MVT::i32, &X86::GR32RegClass);
314 if (Subtarget->is64Bit())
315 addRegisterClass(MVT::i64, &X86::GR64RegClass);
317 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
319 // We don't accept any truncstore of integer registers.
320 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
321 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
322 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
323 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
324 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
325 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
327 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
329 // SETOEQ and SETUNE require checking two conditions.
330 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
331 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
332 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
333 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
334 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
335 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
337 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
339 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
340 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
341 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
343 if (Subtarget->is64Bit()) {
344 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
345 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
346 } else if (!TM.Options.UseSoftFloat) {
347 // We have an algorithm for SSE2->double, and we turn this into a
348 // 64-bit FILD followed by conditional FADD for other targets.
349 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
350 // We have an algorithm for SSE2, and we turn this into a 64-bit
351 // FILD for other targets.
352 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
355 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
357 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
360 if (!TM.Options.UseSoftFloat) {
361 // SSE has no i16 to fp conversion, only i32
362 if (X86ScalarSSEf32) {
363 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
364 // f32 and f64 cases are Legal, f80 case is not
365 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
367 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
371 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
375 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
376 // are Legal, f80 is custom lowered.
377 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
378 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
380 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
382 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
383 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
385 if (X86ScalarSSEf32) {
386 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
387 // f32 and f64 cases are Legal, f80 case is not
388 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
390 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
391 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
394 // Handle FP_TO_UINT by promoting the destination to a larger signed
396 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
397 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
398 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
400 if (Subtarget->is64Bit()) {
401 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
402 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
403 } else if (!TM.Options.UseSoftFloat) {
404 // Since AVX is a superset of SSE3, only check for SSE here.
405 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
406 // Expand FP_TO_UINT into a select.
407 // FIXME: We would like to use a Custom expander here eventually to do
408 // the optimal thing for SSE vs. the default expansion in the legalizer.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
411 // With SSE3 we can use fisttpll to convert to a signed i64; without
412 // SSE, we're stuck with a fistpll.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
416 if (isTargetFTOL()) {
417 // Use the _ftol2 runtime function, which has a pseudo-instruction
418 // to handle its weird calling convention.
419 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
422 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
423 if (!X86ScalarSSEf64) {
424 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
425 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
426 if (Subtarget->is64Bit()) {
427 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
428 // Without SSE, i64->f64 goes through memory.
429 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
433 // Scalar integer divide and remainder are lowered to use operations that
434 // produce two results, to match the available instructions. This exposes
435 // the two-result form to trivial CSE, which is able to combine x/y and x%y
436 // into a single instruction.
438 // Scalar integer multiply-high is also lowered to use two-result
439 // operations, to match the available instructions. However, plain multiply
440 // (low) operations are left as Legal, as there are single-result
441 // instructions for this in x86. Using the two-result multiply instructions
442 // when both high and low results are needed must be arranged by dagcombine.
443 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
445 setOperationAction(ISD::MULHS, VT, Expand);
446 setOperationAction(ISD::MULHU, VT, Expand);
447 setOperationAction(ISD::SDIV, VT, Expand);
448 setOperationAction(ISD::UDIV, VT, Expand);
449 setOperationAction(ISD::SREM, VT, Expand);
450 setOperationAction(ISD::UREM, VT, Expand);
452 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
453 setOperationAction(ISD::ADDC, VT, Custom);
454 setOperationAction(ISD::ADDE, VT, Custom);
455 setOperationAction(ISD::SUBC, VT, Custom);
456 setOperationAction(ISD::SUBE, VT, Custom);
459 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
460 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
461 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
462 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
463 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
464 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
465 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
466 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
467 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
469 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
470 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
471 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
472 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
473 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
474 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
475 if (Subtarget->is64Bit())
476 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
477 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
478 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
479 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
480 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
481 setOperationAction(ISD::FREM , MVT::f32 , Expand);
482 setOperationAction(ISD::FREM , MVT::f64 , Expand);
483 setOperationAction(ISD::FREM , MVT::f80 , Expand);
484 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
486 // Promote the i8 variants and force them on up to i32 which has a shorter
488 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
489 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
491 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
492 if (Subtarget->hasBMI()) {
493 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
494 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
495 if (Subtarget->is64Bit())
496 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
498 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
499 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
500 if (Subtarget->is64Bit())
501 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
504 if (Subtarget->hasLZCNT()) {
505 // When promoting the i8 variants, force them to i32 for a shorter
507 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
508 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
510 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
512 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
513 if (Subtarget->is64Bit())
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
516 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
517 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
518 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
519 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
520 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
521 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
522 if (Subtarget->is64Bit()) {
523 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
524 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
528 // Special handling for half-precision floating point conversions.
529 // If we don't have F16C support, then lower half float conversions
530 // into library calls.
531 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
532 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
536 // There's never any support for operations beyond MVT::f32.
537 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
538 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
539 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
540 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
542 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
543 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
544 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
545 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
547 if (Subtarget->hasPOPCNT()) {
548 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
550 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
551 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
552 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
553 if (Subtarget->is64Bit())
554 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
557 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
559 if (!Subtarget->hasMOVBE())
560 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
562 // These should be promoted to a larger select which is supported.
563 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
564 // X86 wants to expand cmov itself.
565 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
566 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
567 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
568 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
569 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
570 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
571 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
572 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
574 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
575 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
576 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
577 if (Subtarget->is64Bit()) {
578 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
579 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
581 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
582 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
583 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
584 // support continuation, user-level threading, and etc.. As a result, no
585 // other SjLj exception interfaces are implemented and please don't build
586 // your own exception handling based on them.
587 // LLVM/Clang supports zero-cost DWARF exception handling.
588 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
589 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
592 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
593 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
594 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
595 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
596 if (Subtarget->is64Bit())
597 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
598 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
600 if (Subtarget->is64Bit()) {
601 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
602 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
603 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
604 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
605 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
607 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
608 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
609 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
610 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
611 if (Subtarget->is64Bit()) {
612 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
613 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
614 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
617 if (Subtarget->hasSSE1())
618 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
620 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
622 // Expand certain atomics
623 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
626 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
627 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
630 if (Subtarget->hasCmpxchg16b()) {
631 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
634 // FIXME - use subtarget debug flags
635 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
636 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
637 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
640 if (Subtarget->is64Bit()) {
641 setExceptionPointerRegister(X86::RAX);
642 setExceptionSelectorRegister(X86::RDX);
644 setExceptionPointerRegister(X86::EAX);
645 setExceptionSelectorRegister(X86::EDX);
647 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
648 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
650 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
651 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
653 setOperationAction(ISD::TRAP, MVT::Other, Legal);
654 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
656 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
657 setOperationAction(ISD::VASTART , MVT::Other, Custom);
658 setOperationAction(ISD::VAEND , MVT::Other, Expand);
659 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
660 // TargetInfo::X86_64ABIBuiltinVaList
661 setOperationAction(ISD::VAARG , MVT::Other, Custom);
662 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
664 // TargetInfo::CharPtrBuiltinVaList
665 setOperationAction(ISD::VAARG , MVT::Other, Expand);
666 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
669 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
670 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
672 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
674 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
675 // f32 and f64 use SSE.
676 // Set up the FP register classes.
677 addRegisterClass(MVT::f32, &X86::FR32RegClass);
678 addRegisterClass(MVT::f64, &X86::FR64RegClass);
680 // Use ANDPD to simulate FABS.
681 setOperationAction(ISD::FABS , MVT::f64, Custom);
682 setOperationAction(ISD::FABS , MVT::f32, Custom);
684 // Use XORP to simulate FNEG.
685 setOperationAction(ISD::FNEG , MVT::f64, Custom);
686 setOperationAction(ISD::FNEG , MVT::f32, Custom);
688 // Use ANDPD and ORPD to simulate FCOPYSIGN.
689 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
690 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
692 // Lower this to FGETSIGNx86 plus an AND.
693 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
694 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
696 // We don't support sin/cos/fmod
697 setOperationAction(ISD::FSIN , MVT::f64, Expand);
698 setOperationAction(ISD::FCOS , MVT::f64, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
700 setOperationAction(ISD::FSIN , MVT::f32, Expand);
701 setOperationAction(ISD::FCOS , MVT::f32, Expand);
702 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
704 // Expand FP immediates into loads from the stack, except for the special
706 addLegalFPImmediate(APFloat(+0.0)); // xorpd
707 addLegalFPImmediate(APFloat(+0.0f)); // xorps
708 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
709 // Use SSE for f32, x87 for f64.
710 // Set up the FP register classes.
711 addRegisterClass(MVT::f32, &X86::FR32RegClass);
712 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
714 // Use ANDPS to simulate FABS.
715 setOperationAction(ISD::FABS , MVT::f32, Custom);
717 // Use XORP to simulate FNEG.
718 setOperationAction(ISD::FNEG , MVT::f32, Custom);
720 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
722 // Use ANDPS and ORPS to simulate FCOPYSIGN.
723 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
724 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
726 // We don't support sin/cos/fmod
727 setOperationAction(ISD::FSIN , MVT::f32, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
731 // Special cases we handle for FP constants.
732 addLegalFPImmediate(APFloat(+0.0f)); // xorps
733 addLegalFPImmediate(APFloat(+0.0)); // FLD0
734 addLegalFPImmediate(APFloat(+1.0)); // FLD1
735 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
736 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
738 if (!TM.Options.UnsafeFPMath) {
739 setOperationAction(ISD::FSIN , MVT::f64, Expand);
740 setOperationAction(ISD::FCOS , MVT::f64, Expand);
741 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
743 } else if (!TM.Options.UseSoftFloat) {
744 // f32 and f64 in x87.
745 // Set up the FP register classes.
746 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
747 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
750 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
751 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
752 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
754 if (!TM.Options.UnsafeFPMath) {
755 setOperationAction(ISD::FSIN , MVT::f64, Expand);
756 setOperationAction(ISD::FSIN , MVT::f32, Expand);
757 setOperationAction(ISD::FCOS , MVT::f64, Expand);
758 setOperationAction(ISD::FCOS , MVT::f32, Expand);
759 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
760 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
762 addLegalFPImmediate(APFloat(+0.0)); // FLD0
763 addLegalFPImmediate(APFloat(+1.0)); // FLD1
764 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
765 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
766 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
767 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
768 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
769 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
772 // We don't support FMA.
773 setOperationAction(ISD::FMA, MVT::f64, Expand);
774 setOperationAction(ISD::FMA, MVT::f32, Expand);
776 // Long double always uses X87.
777 if (!TM.Options.UseSoftFloat) {
778 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
779 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
780 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
782 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
783 addLegalFPImmediate(TmpFlt); // FLD0
785 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
788 APFloat TmpFlt2(+1.0);
789 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
791 addLegalFPImmediate(TmpFlt2); // FLD1
792 TmpFlt2.changeSign();
793 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
796 if (!TM.Options.UnsafeFPMath) {
797 setOperationAction(ISD::FSIN , MVT::f80, Expand);
798 setOperationAction(ISD::FCOS , MVT::f80, Expand);
799 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
802 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
803 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
804 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
805 setOperationAction(ISD::FRINT, MVT::f80, Expand);
806 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
807 setOperationAction(ISD::FMA, MVT::f80, Expand);
810 // Always use a library call for pow.
811 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
812 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
813 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
815 setOperationAction(ISD::FLOG, MVT::f80, Expand);
816 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
817 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
818 setOperationAction(ISD::FEXP, MVT::f80, Expand);
819 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
820 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
821 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
823 // First set operation action for all vector types to either promote
824 // (for widening) or expand (for scalarization). Then we will selectively
825 // turn on ones that can be effectively codegen'd.
826 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
827 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
828 MVT VT = (MVT::SimpleValueType)i;
829 setOperationAction(ISD::ADD , VT, Expand);
830 setOperationAction(ISD::SUB , VT, Expand);
831 setOperationAction(ISD::FADD, VT, Expand);
832 setOperationAction(ISD::FNEG, VT, Expand);
833 setOperationAction(ISD::FSUB, VT, Expand);
834 setOperationAction(ISD::MUL , VT, Expand);
835 setOperationAction(ISD::FMUL, VT, Expand);
836 setOperationAction(ISD::SDIV, VT, Expand);
837 setOperationAction(ISD::UDIV, VT, Expand);
838 setOperationAction(ISD::FDIV, VT, Expand);
839 setOperationAction(ISD::SREM, VT, Expand);
840 setOperationAction(ISD::UREM, VT, Expand);
841 setOperationAction(ISD::LOAD, VT, Expand);
842 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
843 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
844 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
845 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
846 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
847 setOperationAction(ISD::FABS, VT, Expand);
848 setOperationAction(ISD::FSIN, VT, Expand);
849 setOperationAction(ISD::FSINCOS, VT, Expand);
850 setOperationAction(ISD::FCOS, VT, Expand);
851 setOperationAction(ISD::FSINCOS, VT, Expand);
852 setOperationAction(ISD::FREM, VT, Expand);
853 setOperationAction(ISD::FMA, VT, Expand);
854 setOperationAction(ISD::FPOWI, VT, Expand);
855 setOperationAction(ISD::FSQRT, VT, Expand);
856 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
857 setOperationAction(ISD::FFLOOR, VT, Expand);
858 setOperationAction(ISD::FCEIL, VT, Expand);
859 setOperationAction(ISD::FTRUNC, VT, Expand);
860 setOperationAction(ISD::FRINT, VT, Expand);
861 setOperationAction(ISD::FNEARBYINT, VT, Expand);
862 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
863 setOperationAction(ISD::MULHS, VT, Expand);
864 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
865 setOperationAction(ISD::MULHU, VT, Expand);
866 setOperationAction(ISD::SDIVREM, VT, Expand);
867 setOperationAction(ISD::UDIVREM, VT, Expand);
868 setOperationAction(ISD::FPOW, VT, Expand);
869 setOperationAction(ISD::CTPOP, VT, Expand);
870 setOperationAction(ISD::CTTZ, VT, Expand);
871 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
872 setOperationAction(ISD::CTLZ, VT, Expand);
873 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
874 setOperationAction(ISD::SHL, VT, Expand);
875 setOperationAction(ISD::SRA, VT, Expand);
876 setOperationAction(ISD::SRL, VT, Expand);
877 setOperationAction(ISD::ROTL, VT, Expand);
878 setOperationAction(ISD::ROTR, VT, Expand);
879 setOperationAction(ISD::BSWAP, VT, Expand);
880 setOperationAction(ISD::SETCC, VT, Expand);
881 setOperationAction(ISD::FLOG, VT, Expand);
882 setOperationAction(ISD::FLOG2, VT, Expand);
883 setOperationAction(ISD::FLOG10, VT, Expand);
884 setOperationAction(ISD::FEXP, VT, Expand);
885 setOperationAction(ISD::FEXP2, VT, Expand);
886 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
887 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
888 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
889 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
890 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
891 setOperationAction(ISD::TRUNCATE, VT, Expand);
892 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
893 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
894 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
895 setOperationAction(ISD::VSELECT, VT, Expand);
896 setOperationAction(ISD::SELECT_CC, VT, Expand);
897 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
898 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
899 setTruncStoreAction(VT,
900 (MVT::SimpleValueType)InnerVT, Expand);
901 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
902 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
904 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
905 // we have to deal with them whether we ask for Expansion or not. Setting
906 // Expand causes its own optimisation problems though, so leave them legal.
907 if (VT.getVectorElementType() == MVT::i1)
908 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
911 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
912 // with -msoft-float, disable use of MMX as well.
913 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
914 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
915 // No operations on x86mmx supported, everything uses intrinsics.
918 // MMX-sized vectors (other than x86mmx) are expected to be expanded
919 // into smaller operations.
920 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
921 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
922 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
923 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
924 setOperationAction(ISD::AND, MVT::v8i8, Expand);
925 setOperationAction(ISD::AND, MVT::v4i16, Expand);
926 setOperationAction(ISD::AND, MVT::v2i32, Expand);
927 setOperationAction(ISD::AND, MVT::v1i64, Expand);
928 setOperationAction(ISD::OR, MVT::v8i8, Expand);
929 setOperationAction(ISD::OR, MVT::v4i16, Expand);
930 setOperationAction(ISD::OR, MVT::v2i32, Expand);
931 setOperationAction(ISD::OR, MVT::v1i64, Expand);
932 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
933 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
934 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
935 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
936 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
937 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
938 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
939 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
940 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
941 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
942 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
943 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
944 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
945 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
946 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
947 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
948 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
950 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
951 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
953 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
954 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
955 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
956 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
957 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
958 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
959 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
960 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
961 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
962 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
963 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
964 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
965 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
968 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
969 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
971 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
972 // registers cannot be used even for integer operations.
973 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
974 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
975 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
976 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
978 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
979 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
980 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
981 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
982 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
983 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
984 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
985 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
986 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
987 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
988 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
989 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
990 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
991 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
992 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
993 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
994 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
995 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
996 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
997 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
998 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
999 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
1001 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1002 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
1003 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
1004 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
1006 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
1007 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
1008 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1012 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1013 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1014 MVT VT = (MVT::SimpleValueType)i;
1015 // Do not attempt to custom lower non-power-of-2 vectors
1016 if (!isPowerOf2_32(VT.getVectorNumElements()))
1018 // Do not attempt to custom lower non-128-bit vectors
1019 if (!VT.is128BitVector())
1021 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1022 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1026 // We support custom legalizing of sext and anyext loads for specific
1027 // memory vector types which we can load as a scalar (or sequence of
1028 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1029 // loads these must work with a single scalar load.
1030 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1031 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1032 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1033 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1035 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1036 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1037 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1038 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1040 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1041 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1042 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1043 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1044 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1045 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1047 if (Subtarget->is64Bit()) {
1048 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1049 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1052 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1053 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1054 MVT VT = (MVT::SimpleValueType)i;
1056 // Do not attempt to promote non-128-bit vectors
1057 if (!VT.is128BitVector())
1060 setOperationAction(ISD::AND, VT, Promote);
1061 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1062 setOperationAction(ISD::OR, VT, Promote);
1063 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1064 setOperationAction(ISD::XOR, VT, Promote);
1065 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1066 setOperationAction(ISD::LOAD, VT, Promote);
1067 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1068 setOperationAction(ISD::SELECT, VT, Promote);
1069 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1072 // Custom lower v2i64 and v2f64 selects.
1073 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1074 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1075 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1076 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1078 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1079 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1081 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1082 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1083 // As there is no 64-bit GPR available, we need build a special custom
1084 // sequence to convert from v2i32 to v2f32.
1085 if (!Subtarget->is64Bit())
1086 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1088 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1089 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1091 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1093 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1094 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1095 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1098 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1099 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1100 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1101 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1102 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1103 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1104 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1105 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1106 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1107 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1108 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1110 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1111 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1112 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1113 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1114 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1115 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1116 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1117 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1118 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1119 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1121 // FIXME: Do we need to handle scalar-to-vector here?
1122 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1124 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1125 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1126 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1127 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1128 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1129 // There is no BLENDI for byte vectors. We don't need to custom lower
1130 // some vselects for now.
1131 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1133 // SSE41 brings specific instructions for doing vector sign extend even in
1134 // cases where we don't have SRA.
1135 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1136 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1137 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1139 // i8 and i16 vectors are custom because the source register and source
1140 // source memory operand types are not the same width. f32 vectors are
1141 // custom since the immediate controlling the insert encodes additional
1143 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1144 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1145 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1146 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1149 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1150 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1151 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1153 // FIXME: these should be Legal, but that's only for the case where
1154 // the index is constant. For now custom expand to deal with that.
1155 if (Subtarget->is64Bit()) {
1156 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1157 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1161 if (Subtarget->hasSSE2()) {
1162 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1163 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1165 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1166 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1168 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1169 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1171 // In the customized shift lowering, the legal cases in AVX2 will be
1173 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1174 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1176 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1177 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1179 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1182 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1183 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1184 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1185 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1186 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1187 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1188 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1190 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1191 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1192 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1194 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1196 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1197 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1198 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1199 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1200 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1201 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1202 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1203 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1204 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1205 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1207 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1209 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1210 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1211 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1212 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1213 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1214 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1215 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1216 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1217 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1218 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1220 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1221 // even though v8i16 is a legal type.
1222 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1223 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1224 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1226 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1227 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1228 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1230 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1231 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1233 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1235 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1236 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1239 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1241 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1242 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1244 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1245 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1246 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1247 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1250 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1253 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1254 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1255 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1256 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1258 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1259 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1260 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1261 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1262 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1263 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1264 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1265 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1266 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1267 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1268 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1269 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1271 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1272 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1273 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1274 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1275 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1276 setOperationAction(ISD::FMA, MVT::f32, Legal);
1277 setOperationAction(ISD::FMA, MVT::f64, Legal);
1280 if (Subtarget->hasInt256()) {
1281 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1282 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1283 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1284 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1286 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1287 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1288 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1289 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1291 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1292 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1293 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1294 // Don't lower v32i8 because there is no 128-bit byte mul
1296 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1297 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1298 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1299 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1301 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1302 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1304 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1305 // when we have a 256bit-wide blend with immediate.
1306 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1308 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1309 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1310 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1311 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1313 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1315 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1316 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1318 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1319 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1320 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1321 // Don't lower v32i8 because there is no 128-bit byte mul
1324 // In the customized shift lowering, the legal cases in AVX2 will be
1326 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1327 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1329 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1330 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1332 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1334 // Custom lower several nodes for 256-bit types.
1335 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1336 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1337 MVT VT = (MVT::SimpleValueType)i;
1339 // Extract subvector is special because the value type
1340 // (result) is 128-bit but the source is 256-bit wide.
1341 if (VT.is128BitVector())
1342 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1344 // Do not attempt to custom lower other non-256-bit vectors
1345 if (!VT.is256BitVector())
1348 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1349 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1350 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1351 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1352 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1353 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1354 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1357 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1358 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1359 MVT VT = (MVT::SimpleValueType)i;
1361 // Do not attempt to promote non-256-bit vectors
1362 if (!VT.is256BitVector())
1365 setOperationAction(ISD::AND, VT, Promote);
1366 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1367 setOperationAction(ISD::OR, VT, Promote);
1368 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1369 setOperationAction(ISD::XOR, VT, Promote);
1370 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1371 setOperationAction(ISD::LOAD, VT, Promote);
1372 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1373 setOperationAction(ISD::SELECT, VT, Promote);
1374 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1378 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1379 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1380 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1381 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1382 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1384 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1385 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1386 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1388 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1389 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1390 setOperationAction(ISD::XOR, MVT::i1, Legal);
1391 setOperationAction(ISD::OR, MVT::i1, Legal);
1392 setOperationAction(ISD::AND, MVT::i1, Legal);
1393 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1394 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1395 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1396 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1397 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1398 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1400 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1401 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1402 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1404 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1405 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1407 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1408 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1409 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1410 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1411 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1412 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1413 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1414 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1416 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1418 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1420 if (Subtarget->is64Bit()) {
1421 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1422 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1427 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1428 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1429 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1430 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1431 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1432 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1433 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1434 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1435 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1437 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1438 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1439 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1440 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1441 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1442 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1443 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1444 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1445 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1446 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1447 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1448 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1451 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1452 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1453 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1454 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1458 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1459 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1461 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1463 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1464 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1465 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1466 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1467 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1468 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1469 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1470 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1471 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1473 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1474 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1476 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1477 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1479 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1481 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1482 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1484 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1485 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1487 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1488 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1490 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1491 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1492 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1493 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1494 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1495 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1497 if (Subtarget->hasCDI()) {
1498 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1499 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1502 // Custom lower several nodes.
1503 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1504 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1505 MVT VT = (MVT::SimpleValueType)i;
1507 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1508 // Extract subvector is special because the value type
1509 // (result) is 256/128-bit but the source is 512-bit wide.
1510 if (VT.is128BitVector() || VT.is256BitVector())
1511 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1513 if (VT.getVectorElementType() == MVT::i1)
1514 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1516 // Do not attempt to custom lower other non-512-bit vectors
1517 if (!VT.is512BitVector())
1520 if ( EltSize >= 32) {
1521 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1522 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1523 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1524 setOperationAction(ISD::VSELECT, VT, Legal);
1525 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1526 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1527 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1530 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1531 MVT VT = (MVT::SimpleValueType)i;
1533 // Do not attempt to promote non-256-bit vectors
1534 if (!VT.is512BitVector())
1537 setOperationAction(ISD::SELECT, VT, Promote);
1538 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1542 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1543 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1544 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1546 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1547 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1549 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1550 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1551 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1552 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1554 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1555 const MVT VT = (MVT::SimpleValueType)i;
1557 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1559 // Do not attempt to promote non-256-bit vectors
1560 if (!VT.is512BitVector())
1563 if ( EltSize < 32) {
1564 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1565 setOperationAction(ISD::VSELECT, VT, Legal);
1570 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1571 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1572 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1574 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1575 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1576 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1579 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1580 // of this type with custom code.
1581 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1582 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1583 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1587 // We want to custom lower some of our intrinsics.
1588 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1589 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1590 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1591 if (!Subtarget->is64Bit())
1592 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1594 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1595 // handle type legalization for these operations here.
1597 // FIXME: We really should do custom legalization for addition and
1598 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1599 // than generic legalization for 64-bit multiplication-with-overflow, though.
1600 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1601 // Add/Sub/Mul with overflow operations are custom lowered.
1603 setOperationAction(ISD::SADDO, VT, Custom);
1604 setOperationAction(ISD::UADDO, VT, Custom);
1605 setOperationAction(ISD::SSUBO, VT, Custom);
1606 setOperationAction(ISD::USUBO, VT, Custom);
1607 setOperationAction(ISD::SMULO, VT, Custom);
1608 setOperationAction(ISD::UMULO, VT, Custom);
1612 if (!Subtarget->is64Bit()) {
1613 // These libcalls are not available in 32-bit.
1614 setLibcallName(RTLIB::SHL_I128, nullptr);
1615 setLibcallName(RTLIB::SRL_I128, nullptr);
1616 setLibcallName(RTLIB::SRA_I128, nullptr);
1619 // Combine sin / cos into one node or libcall if possible.
1620 if (Subtarget->hasSinCos()) {
1621 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1622 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1623 if (Subtarget->isTargetDarwin()) {
1624 // For MacOSX, we don't want to the normal expansion of a libcall to
1625 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1627 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1628 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1632 if (Subtarget->isTargetWin64()) {
1633 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1634 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1635 setOperationAction(ISD::SREM, MVT::i128, Custom);
1636 setOperationAction(ISD::UREM, MVT::i128, Custom);
1637 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1638 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1641 // We have target-specific dag combine patterns for the following nodes:
1642 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1643 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1644 setTargetDAGCombine(ISD::VSELECT);
1645 setTargetDAGCombine(ISD::SELECT);
1646 setTargetDAGCombine(ISD::SHL);
1647 setTargetDAGCombine(ISD::SRA);
1648 setTargetDAGCombine(ISD::SRL);
1649 setTargetDAGCombine(ISD::OR);
1650 setTargetDAGCombine(ISD::AND);
1651 setTargetDAGCombine(ISD::ADD);
1652 setTargetDAGCombine(ISD::FADD);
1653 setTargetDAGCombine(ISD::FSUB);
1654 setTargetDAGCombine(ISD::FMA);
1655 setTargetDAGCombine(ISD::SUB);
1656 setTargetDAGCombine(ISD::LOAD);
1657 setTargetDAGCombine(ISD::STORE);
1658 setTargetDAGCombine(ISD::ZERO_EXTEND);
1659 setTargetDAGCombine(ISD::ANY_EXTEND);
1660 setTargetDAGCombine(ISD::SIGN_EXTEND);
1661 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1662 setTargetDAGCombine(ISD::TRUNCATE);
1663 setTargetDAGCombine(ISD::SINT_TO_FP);
1664 setTargetDAGCombine(ISD::SETCC);
1665 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1666 setTargetDAGCombine(ISD::BUILD_VECTOR);
1667 if (Subtarget->is64Bit())
1668 setTargetDAGCombine(ISD::MUL);
1669 setTargetDAGCombine(ISD::XOR);
1671 computeRegisterProperties();
1673 // On Darwin, -Os means optimize for size without hurting performance,
1674 // do not reduce the limit.
1675 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1676 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1677 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1678 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1679 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1680 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1681 setPrefLoopAlignment(4); // 2^4 bytes.
1683 // Predictable cmov don't hurt on atom because it's in-order.
1684 PredictableSelectIsExpensive = !Subtarget->isAtom();
1686 setPrefFunctionAlignment(4); // 2^4 bytes.
1688 verifyIntrinsicTables();
1691 // This has so far only been implemented for 64-bit MachO.
1692 bool X86TargetLowering::useLoadStackGuardNode() const {
1693 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1694 Subtarget->is64Bit();
1697 TargetLoweringBase::LegalizeTypeAction
1698 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1699 if (ExperimentalVectorWideningLegalization &&
1700 VT.getVectorNumElements() != 1 &&
1701 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1702 return TypeWidenVector;
1704 return TargetLoweringBase::getPreferredVectorAction(VT);
1707 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1709 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1711 const unsigned NumElts = VT.getVectorNumElements();
1712 const EVT EltVT = VT.getVectorElementType();
1713 if (VT.is512BitVector()) {
1714 if (Subtarget->hasAVX512())
1715 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1716 EltVT == MVT::f32 || EltVT == MVT::f64)
1718 case 8: return MVT::v8i1;
1719 case 16: return MVT::v16i1;
1721 if (Subtarget->hasBWI())
1722 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1724 case 32: return MVT::v32i1;
1725 case 64: return MVT::v64i1;
1729 if (VT.is256BitVector() || VT.is128BitVector()) {
1730 if (Subtarget->hasVLX())
1731 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1732 EltVT == MVT::f32 || EltVT == MVT::f64)
1734 case 2: return MVT::v2i1;
1735 case 4: return MVT::v4i1;
1736 case 8: return MVT::v8i1;
1738 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1739 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1741 case 8: return MVT::v8i1;
1742 case 16: return MVT::v16i1;
1743 case 32: return MVT::v32i1;
1747 return VT.changeVectorElementTypeToInteger();
1750 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1751 /// the desired ByVal argument alignment.
1752 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1755 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1756 if (VTy->getBitWidth() == 128)
1758 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1759 unsigned EltAlign = 0;
1760 getMaxByValAlign(ATy->getElementType(), EltAlign);
1761 if (EltAlign > MaxAlign)
1762 MaxAlign = EltAlign;
1763 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1764 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1765 unsigned EltAlign = 0;
1766 getMaxByValAlign(STy->getElementType(i), EltAlign);
1767 if (EltAlign > MaxAlign)
1768 MaxAlign = EltAlign;
1775 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1776 /// function arguments in the caller parameter area. For X86, aggregates
1777 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1778 /// are at 4-byte boundaries.
1779 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1780 if (Subtarget->is64Bit()) {
1781 // Max of 8 and alignment of type.
1782 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1789 if (Subtarget->hasSSE1())
1790 getMaxByValAlign(Ty, Align);
1794 /// getOptimalMemOpType - Returns the target specific optimal type for load
1795 /// and store operations as a result of memset, memcpy, and memmove
1796 /// lowering. If DstAlign is zero that means it's safe to destination
1797 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1798 /// means there isn't a need to check it against alignment requirement,
1799 /// probably because the source does not need to be loaded. If 'IsMemset' is
1800 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1801 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1802 /// source is constant so it does not need to be loaded.
1803 /// It returns EVT::Other if the type should be determined using generic
1804 /// target-independent logic.
1806 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1807 unsigned DstAlign, unsigned SrcAlign,
1808 bool IsMemset, bool ZeroMemset,
1810 MachineFunction &MF) const {
1811 const Function *F = MF.getFunction();
1812 if ((!IsMemset || ZeroMemset) &&
1813 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1814 Attribute::NoImplicitFloat)) {
1816 (Subtarget->isUnalignedMemAccessFast() ||
1817 ((DstAlign == 0 || DstAlign >= 16) &&
1818 (SrcAlign == 0 || SrcAlign >= 16)))) {
1820 if (Subtarget->hasInt256())
1822 if (Subtarget->hasFp256())
1825 if (Subtarget->hasSSE2())
1827 if (Subtarget->hasSSE1())
1829 } else if (!MemcpyStrSrc && Size >= 8 &&
1830 !Subtarget->is64Bit() &&
1831 Subtarget->hasSSE2()) {
1832 // Do not use f64 to lower memcpy if source is string constant. It's
1833 // better to use i32 to avoid the loads.
1837 if (Subtarget->is64Bit() && Size >= 8)
1842 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1844 return X86ScalarSSEf32;
1845 else if (VT == MVT::f64)
1846 return X86ScalarSSEf64;
1851 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1856 *Fast = Subtarget->isUnalignedMemAccessFast();
1860 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1861 /// current function. The returned value is a member of the
1862 /// MachineJumpTableInfo::JTEntryKind enum.
1863 unsigned X86TargetLowering::getJumpTableEncoding() const {
1864 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1866 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1867 Subtarget->isPICStyleGOT())
1868 return MachineJumpTableInfo::EK_Custom32;
1870 // Otherwise, use the normal jump table encoding heuristics.
1871 return TargetLowering::getJumpTableEncoding();
1875 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1876 const MachineBasicBlock *MBB,
1877 unsigned uid,MCContext &Ctx) const{
1878 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1879 Subtarget->isPICStyleGOT());
1880 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1882 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1883 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1886 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1888 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1889 SelectionDAG &DAG) const {
1890 if (!Subtarget->is64Bit())
1891 // This doesn't have SDLoc associated with it, but is not really the
1892 // same as a Register.
1893 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1897 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1898 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1900 const MCExpr *X86TargetLowering::
1901 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1902 MCContext &Ctx) const {
1903 // X86-64 uses RIP relative addressing based on the jump table label.
1904 if (Subtarget->isPICStyleRIPRel())
1905 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1907 // Otherwise, the reference is relative to the PIC base.
1908 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1911 // FIXME: Why this routine is here? Move to RegInfo!
1912 std::pair<const TargetRegisterClass*, uint8_t>
1913 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1914 const TargetRegisterClass *RRC = nullptr;
1916 switch (VT.SimpleTy) {
1918 return TargetLowering::findRepresentativeClass(VT);
1919 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1920 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1923 RRC = &X86::VR64RegClass;
1925 case MVT::f32: case MVT::f64:
1926 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1927 case MVT::v4f32: case MVT::v2f64:
1928 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1930 RRC = &X86::VR128RegClass;
1933 return std::make_pair(RRC, Cost);
1936 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1937 unsigned &Offset) const {
1938 if (!Subtarget->isTargetLinux())
1941 if (Subtarget->is64Bit()) {
1942 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1944 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1956 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1957 unsigned DestAS) const {
1958 assert(SrcAS != DestAS && "Expected different address spaces!");
1960 return SrcAS < 256 && DestAS < 256;
1963 //===----------------------------------------------------------------------===//
1964 // Return Value Calling Convention Implementation
1965 //===----------------------------------------------------------------------===//
1967 #include "X86GenCallingConv.inc"
1970 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1971 MachineFunction &MF, bool isVarArg,
1972 const SmallVectorImpl<ISD::OutputArg> &Outs,
1973 LLVMContext &Context) const {
1974 SmallVector<CCValAssign, 16> RVLocs;
1975 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1976 return CCInfo.CheckReturn(Outs, RetCC_X86);
1979 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1980 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1985 X86TargetLowering::LowerReturn(SDValue Chain,
1986 CallingConv::ID CallConv, bool isVarArg,
1987 const SmallVectorImpl<ISD::OutputArg> &Outs,
1988 const SmallVectorImpl<SDValue> &OutVals,
1989 SDLoc dl, SelectionDAG &DAG) const {
1990 MachineFunction &MF = DAG.getMachineFunction();
1991 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1993 SmallVector<CCValAssign, 16> RVLocs;
1994 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1995 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1998 SmallVector<SDValue, 6> RetOps;
1999 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2000 // Operand #1 = Bytes To Pop
2001 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2004 // Copy the result values into the output registers.
2005 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2006 CCValAssign &VA = RVLocs[i];
2007 assert(VA.isRegLoc() && "Can only return in registers!");
2008 SDValue ValToCopy = OutVals[i];
2009 EVT ValVT = ValToCopy.getValueType();
2011 // Promote values to the appropriate types
2012 if (VA.getLocInfo() == CCValAssign::SExt)
2013 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2014 else if (VA.getLocInfo() == CCValAssign::ZExt)
2015 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2016 else if (VA.getLocInfo() == CCValAssign::AExt)
2017 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2018 else if (VA.getLocInfo() == CCValAssign::BCvt)
2019 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2021 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2022 "Unexpected FP-extend for return value.");
2024 // If this is x86-64, and we disabled SSE, we can't return FP values,
2025 // or SSE or MMX vectors.
2026 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2027 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2028 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2029 report_fatal_error("SSE register return with SSE disabled");
2031 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2032 // llvm-gcc has never done it right and no one has noticed, so this
2033 // should be OK for now.
2034 if (ValVT == MVT::f64 &&
2035 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2036 report_fatal_error("SSE2 register return with SSE2 disabled");
2038 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2039 // the RET instruction and handled by the FP Stackifier.
2040 if (VA.getLocReg() == X86::FP0 ||
2041 VA.getLocReg() == X86::FP1) {
2042 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2043 // change the value to the FP stack register class.
2044 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2045 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2046 RetOps.push_back(ValToCopy);
2047 // Don't emit a copytoreg.
2051 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2052 // which is returned in RAX / RDX.
2053 if (Subtarget->is64Bit()) {
2054 if (ValVT == MVT::x86mmx) {
2055 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2056 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2057 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2059 // If we don't have SSE2 available, convert to v4f32 so the generated
2060 // register is legal.
2061 if (!Subtarget->hasSSE2())
2062 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2067 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2068 Flag = Chain.getValue(1);
2069 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2072 // The x86-64 ABIs require that for returning structs by value we copy
2073 // the sret argument into %rax/%eax (depending on ABI) for the return.
2074 // Win32 requires us to put the sret argument to %eax as well.
2075 // We saved the argument into a virtual register in the entry block,
2076 // so now we copy the value out and into %rax/%eax.
2077 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2078 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2079 MachineFunction &MF = DAG.getMachineFunction();
2080 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2081 unsigned Reg = FuncInfo->getSRetReturnReg();
2083 "SRetReturnReg should have been set in LowerFormalArguments().");
2084 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2087 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2088 X86::RAX : X86::EAX;
2089 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2090 Flag = Chain.getValue(1);
2092 // RAX/EAX now acts like a return value.
2093 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2096 RetOps[0] = Chain; // Update chain.
2098 // Add the flag if we have it.
2100 RetOps.push_back(Flag);
2102 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2105 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2106 if (N->getNumValues() != 1)
2108 if (!N->hasNUsesOfValue(1, 0))
2111 SDValue TCChain = Chain;
2112 SDNode *Copy = *N->use_begin();
2113 if (Copy->getOpcode() == ISD::CopyToReg) {
2114 // If the copy has a glue operand, we conservatively assume it isn't safe to
2115 // perform a tail call.
2116 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2118 TCChain = Copy->getOperand(0);
2119 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2122 bool HasRet = false;
2123 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2125 if (UI->getOpcode() != X86ISD::RET_FLAG)
2127 // If we are returning more than one value, we can definitely
2128 // not make a tail call see PR19530
2129 if (UI->getNumOperands() > 4)
2131 if (UI->getNumOperands() == 4 &&
2132 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2145 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2146 ISD::NodeType ExtendKind) const {
2148 // TODO: Is this also valid on 32-bit?
2149 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2150 ReturnMVT = MVT::i8;
2152 ReturnMVT = MVT::i32;
2154 EVT MinVT = getRegisterType(Context, ReturnMVT);
2155 return VT.bitsLT(MinVT) ? MinVT : VT;
2158 /// LowerCallResult - Lower the result values of a call into the
2159 /// appropriate copies out of appropriate physical registers.
2162 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2163 CallingConv::ID CallConv, bool isVarArg,
2164 const SmallVectorImpl<ISD::InputArg> &Ins,
2165 SDLoc dl, SelectionDAG &DAG,
2166 SmallVectorImpl<SDValue> &InVals) const {
2168 // Assign locations to each value returned by this call.
2169 SmallVector<CCValAssign, 16> RVLocs;
2170 bool Is64Bit = Subtarget->is64Bit();
2171 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2173 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2175 // Copy all of the result registers out of their specified physreg.
2176 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2177 CCValAssign &VA = RVLocs[i];
2178 EVT CopyVT = VA.getValVT();
2180 // If this is x86-64, and we disabled SSE, we can't return FP values
2181 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2182 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2183 report_fatal_error("SSE register return with SSE disabled");
2186 // If we prefer to use the value in xmm registers, copy it out as f80 and
2187 // use a truncate to move it from fp stack reg to xmm reg.
2188 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2189 isScalarFPTypeInSSEReg(VA.getValVT()))
2192 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2193 CopyVT, InFlag).getValue(1);
2194 SDValue Val = Chain.getValue(0);
2196 if (CopyVT != VA.getValVT())
2197 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2198 // This truncation won't change the value.
2199 DAG.getIntPtrConstant(1));
2201 InFlag = Chain.getValue(2);
2202 InVals.push_back(Val);
2208 //===----------------------------------------------------------------------===//
2209 // C & StdCall & Fast Calling Convention implementation
2210 //===----------------------------------------------------------------------===//
2211 // StdCall calling convention seems to be standard for many Windows' API
2212 // routines and around. It differs from C calling convention just a little:
2213 // callee should clean up the stack, not caller. Symbols should be also
2214 // decorated in some fancy way :) It doesn't support any vector arguments.
2215 // For info on fast calling convention see Fast Calling Convention (tail call)
2216 // implementation LowerX86_32FastCCCallTo.
2218 /// CallIsStructReturn - Determines whether a call uses struct return
2220 enum StructReturnType {
2225 static StructReturnType
2226 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2228 return NotStructReturn;
2230 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2231 if (!Flags.isSRet())
2232 return NotStructReturn;
2233 if (Flags.isInReg())
2234 return RegStructReturn;
2235 return StackStructReturn;
2238 /// ArgsAreStructReturn - Determines whether a function uses struct
2239 /// return semantics.
2240 static StructReturnType
2241 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2243 return NotStructReturn;
2245 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2246 if (!Flags.isSRet())
2247 return NotStructReturn;
2248 if (Flags.isInReg())
2249 return RegStructReturn;
2250 return StackStructReturn;
2253 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2254 /// by "Src" to address "Dst" with size and alignment information specified by
2255 /// the specific parameter attribute. The copy will be passed as a byval
2256 /// function parameter.
2258 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2259 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2261 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2263 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2264 /*isVolatile*/false, /*AlwaysInline=*/true,
2265 MachinePointerInfo(), MachinePointerInfo());
2268 /// IsTailCallConvention - Return true if the calling convention is one that
2269 /// supports tail call optimization.
2270 static bool IsTailCallConvention(CallingConv::ID CC) {
2271 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2272 CC == CallingConv::HiPE);
2275 /// \brief Return true if the calling convention is a C calling convention.
2276 static bool IsCCallConvention(CallingConv::ID CC) {
2277 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2278 CC == CallingConv::X86_64_SysV);
2281 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2282 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2286 CallingConv::ID CalleeCC = CS.getCallingConv();
2287 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2293 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2294 /// a tailcall target by changing its ABI.
2295 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2296 bool GuaranteedTailCallOpt) {
2297 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2301 X86TargetLowering::LowerMemArgument(SDValue Chain,
2302 CallingConv::ID CallConv,
2303 const SmallVectorImpl<ISD::InputArg> &Ins,
2304 SDLoc dl, SelectionDAG &DAG,
2305 const CCValAssign &VA,
2306 MachineFrameInfo *MFI,
2308 // Create the nodes corresponding to a load from this parameter slot.
2309 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2310 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2311 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2312 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2315 // If value is passed by pointer we have address passed instead of the value
2317 if (VA.getLocInfo() == CCValAssign::Indirect)
2318 ValVT = VA.getLocVT();
2320 ValVT = VA.getValVT();
2322 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2323 // changed with more analysis.
2324 // In case of tail call optimization mark all arguments mutable. Since they
2325 // could be overwritten by lowering of arguments in case of a tail call.
2326 if (Flags.isByVal()) {
2327 unsigned Bytes = Flags.getByValSize();
2328 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2329 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2330 return DAG.getFrameIndex(FI, getPointerTy());
2332 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2333 VA.getLocMemOffset(), isImmutable);
2334 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2335 return DAG.getLoad(ValVT, dl, Chain, FIN,
2336 MachinePointerInfo::getFixedStack(FI),
2337 false, false, false, 0);
2341 // FIXME: Get this from tablegen.
2342 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2343 const X86Subtarget *Subtarget) {
2344 assert(Subtarget->is64Bit());
2346 if (Subtarget->isCallingConvWin64(CallConv)) {
2347 static const MCPhysReg GPR64ArgRegsWin64[] = {
2348 X86::RCX, X86::RDX, X86::R8, X86::R9
2350 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2353 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2354 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2356 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2359 // FIXME: Get this from tablegen.
2360 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2361 CallingConv::ID CallConv,
2362 const X86Subtarget *Subtarget) {
2363 assert(Subtarget->is64Bit());
2364 if (Subtarget->isCallingConvWin64(CallConv)) {
2365 // The XMM registers which might contain var arg parameters are shadowed
2366 // in their paired GPR. So we only need to save the GPR to their home
2368 // TODO: __vectorcall will change this.
2372 const Function *Fn = MF.getFunction();
2373 bool NoImplicitFloatOps = Fn->getAttributes().
2374 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2375 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2376 "SSE register cannot be used when SSE is disabled!");
2377 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2378 !Subtarget->hasSSE1())
2379 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2383 static const MCPhysReg XMMArgRegs64Bit[] = {
2384 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2385 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2387 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2391 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2392 CallingConv::ID CallConv,
2394 const SmallVectorImpl<ISD::InputArg> &Ins,
2397 SmallVectorImpl<SDValue> &InVals)
2399 MachineFunction &MF = DAG.getMachineFunction();
2400 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2402 const Function* Fn = MF.getFunction();
2403 if (Fn->hasExternalLinkage() &&
2404 Subtarget->isTargetCygMing() &&
2405 Fn->getName() == "main")
2406 FuncInfo->setForceFramePointer(true);
2408 MachineFrameInfo *MFI = MF.getFrameInfo();
2409 bool Is64Bit = Subtarget->is64Bit();
2410 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2412 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2413 "Var args not supported with calling convention fastcc, ghc or hipe");
2415 // Assign locations to all of the incoming arguments.
2416 SmallVector<CCValAssign, 16> ArgLocs;
2417 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2419 // Allocate shadow area for Win64
2421 CCInfo.AllocateStack(32, 8);
2423 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2425 unsigned LastVal = ~0U;
2427 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2428 CCValAssign &VA = ArgLocs[i];
2429 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2431 assert(VA.getValNo() != LastVal &&
2432 "Don't support value assigned to multiple locs yet");
2434 LastVal = VA.getValNo();
2436 if (VA.isRegLoc()) {
2437 EVT RegVT = VA.getLocVT();
2438 const TargetRegisterClass *RC;
2439 if (RegVT == MVT::i32)
2440 RC = &X86::GR32RegClass;
2441 else if (Is64Bit && RegVT == MVT::i64)
2442 RC = &X86::GR64RegClass;
2443 else if (RegVT == MVT::f32)
2444 RC = &X86::FR32RegClass;
2445 else if (RegVT == MVT::f64)
2446 RC = &X86::FR64RegClass;
2447 else if (RegVT.is512BitVector())
2448 RC = &X86::VR512RegClass;
2449 else if (RegVT.is256BitVector())
2450 RC = &X86::VR256RegClass;
2451 else if (RegVT.is128BitVector())
2452 RC = &X86::VR128RegClass;
2453 else if (RegVT == MVT::x86mmx)
2454 RC = &X86::VR64RegClass;
2455 else if (RegVT == MVT::i1)
2456 RC = &X86::VK1RegClass;
2457 else if (RegVT == MVT::v8i1)
2458 RC = &X86::VK8RegClass;
2459 else if (RegVT == MVT::v16i1)
2460 RC = &X86::VK16RegClass;
2461 else if (RegVT == MVT::v32i1)
2462 RC = &X86::VK32RegClass;
2463 else if (RegVT == MVT::v64i1)
2464 RC = &X86::VK64RegClass;
2466 llvm_unreachable("Unknown argument type!");
2468 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2469 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2471 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2472 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2474 if (VA.getLocInfo() == CCValAssign::SExt)
2475 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2476 DAG.getValueType(VA.getValVT()));
2477 else if (VA.getLocInfo() == CCValAssign::ZExt)
2478 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2479 DAG.getValueType(VA.getValVT()));
2480 else if (VA.getLocInfo() == CCValAssign::BCvt)
2481 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2483 if (VA.isExtInLoc()) {
2484 // Handle MMX values passed in XMM regs.
2485 if (RegVT.isVector())
2486 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2488 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2491 assert(VA.isMemLoc());
2492 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2495 // If value is passed via pointer - do a load.
2496 if (VA.getLocInfo() == CCValAssign::Indirect)
2497 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2498 MachinePointerInfo(), false, false, false, 0);
2500 InVals.push_back(ArgValue);
2503 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2504 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2505 // The x86-64 ABIs require that for returning structs by value we copy
2506 // the sret argument into %rax/%eax (depending on ABI) for the return.
2507 // Win32 requires us to put the sret argument to %eax as well.
2508 // Save the argument into a virtual register so that we can access it
2509 // from the return points.
2510 if (Ins[i].Flags.isSRet()) {
2511 unsigned Reg = FuncInfo->getSRetReturnReg();
2513 MVT PtrTy = getPointerTy();
2514 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2515 FuncInfo->setSRetReturnReg(Reg);
2517 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2518 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2524 unsigned StackSize = CCInfo.getNextStackOffset();
2525 // Align stack specially for tail calls.
2526 if (FuncIsMadeTailCallSafe(CallConv,
2527 MF.getTarget().Options.GuaranteedTailCallOpt))
2528 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2530 // If the function takes variable number of arguments, make a frame index for
2531 // the start of the first vararg value... for expansion of llvm.va_start. We
2532 // can skip this if there are no va_start calls.
2533 if (MFI->hasVAStart() &&
2534 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2535 CallConv != CallingConv::X86_ThisCall))) {
2536 FuncInfo->setVarArgsFrameIndex(
2537 MFI->CreateFixedObject(1, StackSize, true));
2540 // 64-bit calling conventions support varargs and register parameters, so we
2541 // have to do extra work to spill them in the prologue or forward them to
2543 if (Is64Bit && isVarArg &&
2544 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2545 // Find the first unallocated argument registers.
2546 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2547 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2548 unsigned NumIntRegs =
2549 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2550 unsigned NumXMMRegs =
2551 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2552 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2553 "SSE register cannot be used when SSE is disabled!");
2555 // Gather all the live in physical registers.
2556 SmallVector<SDValue, 6> LiveGPRs;
2557 SmallVector<SDValue, 8> LiveXMMRegs;
2559 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2560 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2562 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2564 if (!ArgXMMs.empty()) {
2565 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2566 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2567 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2568 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2569 LiveXMMRegs.push_back(
2570 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2574 // Store them to the va_list returned by va_start.
2575 if (MFI->hasVAStart()) {
2577 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2578 // Get to the caller-allocated home save location. Add 8 to account
2579 // for the return address.
2580 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2581 FuncInfo->setRegSaveFrameIndex(
2582 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2583 // Fixup to set vararg frame on shadow area (4 x i64).
2585 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2587 // For X86-64, if there are vararg parameters that are passed via
2588 // registers, then we must store them to their spots on the stack so
2589 // they may be loaded by deferencing the result of va_next.
2590 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2591 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2592 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2593 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2596 // Store the integer parameter registers.
2597 SmallVector<SDValue, 8> MemOps;
2598 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2600 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2601 for (SDValue Val : LiveGPRs) {
2602 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2603 DAG.getIntPtrConstant(Offset));
2605 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2606 MachinePointerInfo::getFixedStack(
2607 FuncInfo->getRegSaveFrameIndex(), Offset),
2609 MemOps.push_back(Store);
2613 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2614 // Now store the XMM (fp + vector) parameter registers.
2615 SmallVector<SDValue, 12> SaveXMMOps;
2616 SaveXMMOps.push_back(Chain);
2617 SaveXMMOps.push_back(ALVal);
2618 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2619 FuncInfo->getRegSaveFrameIndex()));
2620 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2621 FuncInfo->getVarArgsFPOffset()));
2622 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2624 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2625 MVT::Other, SaveXMMOps));
2628 if (!MemOps.empty())
2629 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2631 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2632 // to the liveout set on a musttail call.
2633 assert(MFI->hasMustTailInVarArgFunc());
2634 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2635 typedef X86MachineFunctionInfo::Forward Forward;
2637 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2639 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2640 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2641 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2644 if (!ArgXMMs.empty()) {
2646 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2647 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2648 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2650 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2652 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2653 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2655 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2661 // Some CCs need callee pop.
2662 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2663 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2664 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2666 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2667 // If this is an sret function, the return should pop the hidden pointer.
2668 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2669 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2670 argsAreStructReturn(Ins) == StackStructReturn)
2671 FuncInfo->setBytesToPopOnReturn(4);
2675 // RegSaveFrameIndex is X86-64 only.
2676 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2677 if (CallConv == CallingConv::X86_FastCall ||
2678 CallConv == CallingConv::X86_ThisCall)
2679 // fastcc functions can't have varargs.
2680 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2683 FuncInfo->setArgumentStackSize(StackSize);
2689 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2690 SDValue StackPtr, SDValue Arg,
2691 SDLoc dl, SelectionDAG &DAG,
2692 const CCValAssign &VA,
2693 ISD::ArgFlagsTy Flags) const {
2694 unsigned LocMemOffset = VA.getLocMemOffset();
2695 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2696 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2697 if (Flags.isByVal())
2698 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2700 return DAG.getStore(Chain, dl, Arg, PtrOff,
2701 MachinePointerInfo::getStack(LocMemOffset),
2705 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2706 /// optimization is performed and it is required.
2708 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2709 SDValue &OutRetAddr, SDValue Chain,
2710 bool IsTailCall, bool Is64Bit,
2711 int FPDiff, SDLoc dl) const {
2712 // Adjust the Return address stack slot.
2713 EVT VT = getPointerTy();
2714 OutRetAddr = getReturnAddressFrameIndex(DAG);
2716 // Load the "old" Return address.
2717 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2718 false, false, false, 0);
2719 return SDValue(OutRetAddr.getNode(), 1);
2722 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2723 /// optimization is performed and it is required (FPDiff!=0).
2724 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2725 SDValue Chain, SDValue RetAddrFrIdx,
2726 EVT PtrVT, unsigned SlotSize,
2727 int FPDiff, SDLoc dl) {
2728 // Store the return address to the appropriate stack slot.
2729 if (!FPDiff) return Chain;
2730 // Calculate the new stack slot for the return address.
2731 int NewReturnAddrFI =
2732 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2734 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2735 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2736 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2742 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2743 SmallVectorImpl<SDValue> &InVals) const {
2744 SelectionDAG &DAG = CLI.DAG;
2746 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2747 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2748 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2749 SDValue Chain = CLI.Chain;
2750 SDValue Callee = CLI.Callee;
2751 CallingConv::ID CallConv = CLI.CallConv;
2752 bool &isTailCall = CLI.IsTailCall;
2753 bool isVarArg = CLI.IsVarArg;
2755 MachineFunction &MF = DAG.getMachineFunction();
2756 bool Is64Bit = Subtarget->is64Bit();
2757 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2758 StructReturnType SR = callIsStructReturn(Outs);
2759 bool IsSibcall = false;
2760 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2762 if (MF.getTarget().Options.DisableTailCalls)
2765 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2767 // Force this to be a tail call. The verifier rules are enough to ensure
2768 // that we can lower this successfully without moving the return address
2771 } else if (isTailCall) {
2772 // Check if it's really possible to do a tail call.
2773 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2774 isVarArg, SR != NotStructReturn,
2775 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2776 Outs, OutVals, Ins, DAG);
2778 // Sibcalls are automatically detected tailcalls which do not require
2780 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2787 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2788 "Var args not supported with calling convention fastcc, ghc or hipe");
2790 // Analyze operands of the call, assigning locations to each operand.
2791 SmallVector<CCValAssign, 16> ArgLocs;
2792 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2794 // Allocate shadow area for Win64
2796 CCInfo.AllocateStack(32, 8);
2798 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2800 // Get a count of how many bytes are to be pushed on the stack.
2801 unsigned NumBytes = CCInfo.getNextStackOffset();
2803 // This is a sibcall. The memory operands are available in caller's
2804 // own caller's stack.
2806 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2807 IsTailCallConvention(CallConv))
2808 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2811 if (isTailCall && !IsSibcall && !IsMustTail) {
2812 // Lower arguments at fp - stackoffset + fpdiff.
2813 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2815 FPDiff = NumBytesCallerPushed - NumBytes;
2817 // Set the delta of movement of the returnaddr stackslot.
2818 // But only set if delta is greater than previous delta.
2819 if (FPDiff < X86Info->getTCReturnAddrDelta())
2820 X86Info->setTCReturnAddrDelta(FPDiff);
2823 unsigned NumBytesToPush = NumBytes;
2824 unsigned NumBytesToPop = NumBytes;
2826 // If we have an inalloca argument, all stack space has already been allocated
2827 // for us and be right at the top of the stack. We don't support multiple
2828 // arguments passed in memory when using inalloca.
2829 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2831 if (!ArgLocs.back().isMemLoc())
2832 report_fatal_error("cannot use inalloca attribute on a register "
2834 if (ArgLocs.back().getLocMemOffset() != 0)
2835 report_fatal_error("any parameter with the inalloca attribute must be "
2836 "the only memory argument");
2840 Chain = DAG.getCALLSEQ_START(
2841 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2843 SDValue RetAddrFrIdx;
2844 // Load return address for tail calls.
2845 if (isTailCall && FPDiff)
2846 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2847 Is64Bit, FPDiff, dl);
2849 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2850 SmallVector<SDValue, 8> MemOpChains;
2853 // Walk the register/memloc assignments, inserting copies/loads. In the case
2854 // of tail call optimization arguments are handle later.
2855 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2856 DAG.getSubtarget().getRegisterInfo());
2857 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2858 // Skip inalloca arguments, they have already been written.
2859 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2860 if (Flags.isInAlloca())
2863 CCValAssign &VA = ArgLocs[i];
2864 EVT RegVT = VA.getLocVT();
2865 SDValue Arg = OutVals[i];
2866 bool isByVal = Flags.isByVal();
2868 // Promote the value if needed.
2869 switch (VA.getLocInfo()) {
2870 default: llvm_unreachable("Unknown loc info!");
2871 case CCValAssign::Full: break;
2872 case CCValAssign::SExt:
2873 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2875 case CCValAssign::ZExt:
2876 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2878 case CCValAssign::AExt:
2879 if (RegVT.is128BitVector()) {
2880 // Special case: passing MMX values in XMM registers.
2881 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2882 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2883 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2885 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2887 case CCValAssign::BCvt:
2888 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2890 case CCValAssign::Indirect: {
2891 // Store the argument.
2892 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2893 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2894 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2895 MachinePointerInfo::getFixedStack(FI),
2902 if (VA.isRegLoc()) {
2903 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2904 if (isVarArg && IsWin64) {
2905 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2906 // shadow reg if callee is a varargs function.
2907 unsigned ShadowReg = 0;
2908 switch (VA.getLocReg()) {
2909 case X86::XMM0: ShadowReg = X86::RCX; break;
2910 case X86::XMM1: ShadowReg = X86::RDX; break;
2911 case X86::XMM2: ShadowReg = X86::R8; break;
2912 case X86::XMM3: ShadowReg = X86::R9; break;
2915 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2917 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2918 assert(VA.isMemLoc());
2919 if (!StackPtr.getNode())
2920 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2922 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2923 dl, DAG, VA, Flags));
2927 if (!MemOpChains.empty())
2928 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2930 if (Subtarget->isPICStyleGOT()) {
2931 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2934 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2935 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2937 // If we are tail calling and generating PIC/GOT style code load the
2938 // address of the callee into ECX. The value in ecx is used as target of
2939 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2940 // for tail calls on PIC/GOT architectures. Normally we would just put the
2941 // address of GOT into ebx and then call target@PLT. But for tail calls
2942 // ebx would be restored (since ebx is callee saved) before jumping to the
2945 // Note: The actual moving to ECX is done further down.
2946 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2947 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2948 !G->getGlobal()->hasProtectedVisibility())
2949 Callee = LowerGlobalAddress(Callee, DAG);
2950 else if (isa<ExternalSymbolSDNode>(Callee))
2951 Callee = LowerExternalSymbol(Callee, DAG);
2955 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2956 // From AMD64 ABI document:
2957 // For calls that may call functions that use varargs or stdargs
2958 // (prototype-less calls or calls to functions containing ellipsis (...) in
2959 // the declaration) %al is used as hidden argument to specify the number
2960 // of SSE registers used. The contents of %al do not need to match exactly
2961 // the number of registers, but must be an ubound on the number of SSE
2962 // registers used and is in the range 0 - 8 inclusive.
2964 // Count the number of XMM registers allocated.
2965 static const MCPhysReg XMMArgRegs[] = {
2966 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2967 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2969 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2970 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2971 && "SSE registers cannot be used when SSE is disabled");
2973 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2974 DAG.getConstant(NumXMMRegs, MVT::i8)));
2977 if (Is64Bit && isVarArg && IsMustTail) {
2978 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2979 for (const auto &F : Forwards) {
2980 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2981 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2985 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2986 // don't need this because the eligibility check rejects calls that require
2987 // shuffling arguments passed in memory.
2988 if (!IsSibcall && isTailCall) {
2989 // Force all the incoming stack arguments to be loaded from the stack
2990 // before any new outgoing arguments are stored to the stack, because the
2991 // outgoing stack slots may alias the incoming argument stack slots, and
2992 // the alias isn't otherwise explicit. This is slightly more conservative
2993 // than necessary, because it means that each store effectively depends
2994 // on every argument instead of just those arguments it would clobber.
2995 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2997 SmallVector<SDValue, 8> MemOpChains2;
3000 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3001 CCValAssign &VA = ArgLocs[i];
3004 assert(VA.isMemLoc());
3005 SDValue Arg = OutVals[i];
3006 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3007 // Skip inalloca arguments. They don't require any work.
3008 if (Flags.isInAlloca())
3010 // Create frame index.
3011 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3012 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3013 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3014 FIN = DAG.getFrameIndex(FI, getPointerTy());
3016 if (Flags.isByVal()) {
3017 // Copy relative to framepointer.
3018 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3019 if (!StackPtr.getNode())
3020 StackPtr = DAG.getCopyFromReg(Chain, dl,
3021 RegInfo->getStackRegister(),
3023 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3025 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3029 // Store relative to framepointer.
3030 MemOpChains2.push_back(
3031 DAG.getStore(ArgChain, dl, Arg, FIN,
3032 MachinePointerInfo::getFixedStack(FI),
3037 if (!MemOpChains2.empty())
3038 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3040 // Store the return address to the appropriate stack slot.
3041 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3042 getPointerTy(), RegInfo->getSlotSize(),
3046 // Build a sequence of copy-to-reg nodes chained together with token chain
3047 // and flag operands which copy the outgoing args into registers.
3049 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3050 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3051 RegsToPass[i].second, InFlag);
3052 InFlag = Chain.getValue(1);
3055 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3056 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3057 // In the 64-bit large code model, we have to make all calls
3058 // through a register, since the call instruction's 32-bit
3059 // pc-relative offset may not be large enough to hold the whole
3061 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3062 // If the callee is a GlobalAddress node (quite common, every direct call
3063 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3066 // We should use extra load for direct calls to dllimported functions in
3068 const GlobalValue *GV = G->getGlobal();
3069 if (!GV->hasDLLImportStorageClass()) {
3070 unsigned char OpFlags = 0;
3071 bool ExtraLoad = false;
3072 unsigned WrapperKind = ISD::DELETED_NODE;
3074 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3075 // external symbols most go through the PLT in PIC mode. If the symbol
3076 // has hidden or protected visibility, or if it is static or local, then
3077 // we don't need to use the PLT - we can directly call it.
3078 if (Subtarget->isTargetELF() &&
3079 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3080 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3081 OpFlags = X86II::MO_PLT;
3082 } else if (Subtarget->isPICStyleStubAny() &&
3083 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3084 (!Subtarget->getTargetTriple().isMacOSX() ||
3085 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3086 // PC-relative references to external symbols should go through $stub,
3087 // unless we're building with the leopard linker or later, which
3088 // automatically synthesizes these stubs.
3089 OpFlags = X86II::MO_DARWIN_STUB;
3090 } else if (Subtarget->isPICStyleRIPRel() &&
3091 isa<Function>(GV) &&
3092 cast<Function>(GV)->getAttributes().
3093 hasAttribute(AttributeSet::FunctionIndex,
3094 Attribute::NonLazyBind)) {
3095 // If the function is marked as non-lazy, generate an indirect call
3096 // which loads from the GOT directly. This avoids runtime overhead
3097 // at the cost of eager binding (and one extra byte of encoding).
3098 OpFlags = X86II::MO_GOTPCREL;
3099 WrapperKind = X86ISD::WrapperRIP;
3103 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3104 G->getOffset(), OpFlags);
3106 // Add a wrapper if needed.
3107 if (WrapperKind != ISD::DELETED_NODE)
3108 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3109 // Add extra indirection if needed.
3111 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3112 MachinePointerInfo::getGOT(),
3113 false, false, false, 0);
3115 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3116 unsigned char OpFlags = 0;
3118 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3119 // external symbols should go through the PLT.
3120 if (Subtarget->isTargetELF() &&
3121 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3122 OpFlags = X86II::MO_PLT;
3123 } else if (Subtarget->isPICStyleStubAny() &&
3124 (!Subtarget->getTargetTriple().isMacOSX() ||
3125 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3126 // PC-relative references to external symbols should go through $stub,
3127 // unless we're building with the leopard linker or later, which
3128 // automatically synthesizes these stubs.
3129 OpFlags = X86II::MO_DARWIN_STUB;
3132 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3134 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3135 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3136 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3139 // Returns a chain & a flag for retval copy to use.
3140 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3141 SmallVector<SDValue, 8> Ops;
3143 if (!IsSibcall && isTailCall) {
3144 Chain = DAG.getCALLSEQ_END(Chain,
3145 DAG.getIntPtrConstant(NumBytesToPop, true),
3146 DAG.getIntPtrConstant(0, true), InFlag, dl);
3147 InFlag = Chain.getValue(1);
3150 Ops.push_back(Chain);
3151 Ops.push_back(Callee);
3154 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3156 // Add argument registers to the end of the list so that they are known live
3158 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3159 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3160 RegsToPass[i].second.getValueType()));
3162 // Add a register mask operand representing the call-preserved registers.
3163 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3164 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3165 assert(Mask && "Missing call preserved mask for calling convention");
3166 Ops.push_back(DAG.getRegisterMask(Mask));
3168 if (InFlag.getNode())
3169 Ops.push_back(InFlag);
3173 //// If this is the first return lowered for this function, add the regs
3174 //// to the liveout set for the function.
3175 // This isn't right, although it's probably harmless on x86; liveouts
3176 // should be computed from returns not tail calls. Consider a void
3177 // function making a tail call to a function returning int.
3178 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3181 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3182 InFlag = Chain.getValue(1);
3184 // Create the CALLSEQ_END node.
3185 unsigned NumBytesForCalleeToPop;
3186 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3187 DAG.getTarget().Options.GuaranteedTailCallOpt))
3188 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3189 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3190 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3191 SR == StackStructReturn)
3192 // If this is a call to a struct-return function, the callee
3193 // pops the hidden struct pointer, so we have to push it back.
3194 // This is common for Darwin/X86, Linux & Mingw32 targets.
3195 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3196 NumBytesForCalleeToPop = 4;
3198 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3200 // Returns a flag for retval copy to use.
3202 Chain = DAG.getCALLSEQ_END(Chain,
3203 DAG.getIntPtrConstant(NumBytesToPop, true),
3204 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3207 InFlag = Chain.getValue(1);
3210 // Handle result values, copying them out of physregs into vregs that we
3212 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3213 Ins, dl, DAG, InVals);
3216 //===----------------------------------------------------------------------===//
3217 // Fast Calling Convention (tail call) implementation
3218 //===----------------------------------------------------------------------===//
3220 // Like std call, callee cleans arguments, convention except that ECX is
3221 // reserved for storing the tail called function address. Only 2 registers are
3222 // free for argument passing (inreg). Tail call optimization is performed
3224 // * tailcallopt is enabled
3225 // * caller/callee are fastcc
3226 // On X86_64 architecture with GOT-style position independent code only local
3227 // (within module) calls are supported at the moment.
3228 // To keep the stack aligned according to platform abi the function
3229 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3230 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3231 // If a tail called function callee has more arguments than the caller the
3232 // caller needs to make sure that there is room to move the RETADDR to. This is
3233 // achieved by reserving an area the size of the argument delta right after the
3234 // original RETADDR, but before the saved framepointer or the spilled registers
3235 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3247 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3248 /// for a 16 byte align requirement.
3250 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3251 SelectionDAG& DAG) const {
3252 MachineFunction &MF = DAG.getMachineFunction();
3253 const TargetMachine &TM = MF.getTarget();
3254 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3255 TM.getSubtargetImpl()->getRegisterInfo());
3256 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3257 unsigned StackAlignment = TFI.getStackAlignment();
3258 uint64_t AlignMask = StackAlignment - 1;
3259 int64_t Offset = StackSize;
3260 unsigned SlotSize = RegInfo->getSlotSize();
3261 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3262 // Number smaller than 12 so just add the difference.
3263 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3265 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3266 Offset = ((~AlignMask) & Offset) + StackAlignment +
3267 (StackAlignment-SlotSize);
3272 /// MatchingStackOffset - Return true if the given stack call argument is
3273 /// already available in the same position (relatively) of the caller's
3274 /// incoming argument stack.
3276 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3277 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3278 const X86InstrInfo *TII) {
3279 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3281 if (Arg.getOpcode() == ISD::CopyFromReg) {
3282 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3283 if (!TargetRegisterInfo::isVirtualRegister(VR))
3285 MachineInstr *Def = MRI->getVRegDef(VR);
3288 if (!Flags.isByVal()) {
3289 if (!TII->isLoadFromStackSlot(Def, FI))
3292 unsigned Opcode = Def->getOpcode();
3293 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3294 Def->getOperand(1).isFI()) {
3295 FI = Def->getOperand(1).getIndex();
3296 Bytes = Flags.getByValSize();
3300 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3301 if (Flags.isByVal())
3302 // ByVal argument is passed in as a pointer but it's now being
3303 // dereferenced. e.g.
3304 // define @foo(%struct.X* %A) {
3305 // tail call @bar(%struct.X* byval %A)
3308 SDValue Ptr = Ld->getBasePtr();
3309 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3312 FI = FINode->getIndex();
3313 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3314 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3315 FI = FINode->getIndex();
3316 Bytes = Flags.getByValSize();
3320 assert(FI != INT_MAX);
3321 if (!MFI->isFixedObjectIndex(FI))
3323 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3326 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3327 /// for tail call optimization. Targets which want to do tail call
3328 /// optimization should implement this function.
3330 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3331 CallingConv::ID CalleeCC,
3333 bool isCalleeStructRet,
3334 bool isCallerStructRet,
3336 const SmallVectorImpl<ISD::OutputArg> &Outs,
3337 const SmallVectorImpl<SDValue> &OutVals,
3338 const SmallVectorImpl<ISD::InputArg> &Ins,
3339 SelectionDAG &DAG) const {
3340 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3343 // If -tailcallopt is specified, make fastcc functions tail-callable.
3344 const MachineFunction &MF = DAG.getMachineFunction();
3345 const Function *CallerF = MF.getFunction();
3347 // If the function return type is x86_fp80 and the callee return type is not,
3348 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3349 // perform a tailcall optimization here.
3350 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3353 CallingConv::ID CallerCC = CallerF->getCallingConv();
3354 bool CCMatch = CallerCC == CalleeCC;
3355 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3356 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3358 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3359 if (IsTailCallConvention(CalleeCC) && CCMatch)
3364 // Look for obvious safe cases to perform tail call optimization that do not
3365 // require ABI changes. This is what gcc calls sibcall.
3367 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3368 // emit a special epilogue.
3369 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3370 DAG.getSubtarget().getRegisterInfo());
3371 if (RegInfo->needsStackRealignment(MF))
3374 // Also avoid sibcall optimization if either caller or callee uses struct
3375 // return semantics.
3376 if (isCalleeStructRet || isCallerStructRet)
3379 // An stdcall/thiscall caller is expected to clean up its arguments; the
3380 // callee isn't going to do that.
3381 // FIXME: this is more restrictive than needed. We could produce a tailcall
3382 // when the stack adjustment matches. For example, with a thiscall that takes
3383 // only one argument.
3384 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3385 CallerCC == CallingConv::X86_ThisCall))
3388 // Do not sibcall optimize vararg calls unless all arguments are passed via
3390 if (isVarArg && !Outs.empty()) {
3392 // Optimizing for varargs on Win64 is unlikely to be safe without
3393 // additional testing.
3394 if (IsCalleeWin64 || IsCallerWin64)
3397 SmallVector<CCValAssign, 16> ArgLocs;
3398 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3401 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3402 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3403 if (!ArgLocs[i].isRegLoc())
3407 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3408 // stack. Therefore, if it's not used by the call it is not safe to optimize
3409 // this into a sibcall.
3410 bool Unused = false;
3411 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3418 SmallVector<CCValAssign, 16> RVLocs;
3419 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3421 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3422 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3423 CCValAssign &VA = RVLocs[i];
3424 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3429 // If the calling conventions do not match, then we'd better make sure the
3430 // results are returned in the same way as what the caller expects.
3432 SmallVector<CCValAssign, 16> RVLocs1;
3433 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3435 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3437 SmallVector<CCValAssign, 16> RVLocs2;
3438 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3440 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3442 if (RVLocs1.size() != RVLocs2.size())
3444 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3445 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3447 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3449 if (RVLocs1[i].isRegLoc()) {
3450 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3453 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3459 // If the callee takes no arguments then go on to check the results of the
3461 if (!Outs.empty()) {
3462 // Check if stack adjustment is needed. For now, do not do this if any
3463 // argument is passed on the stack.
3464 SmallVector<CCValAssign, 16> ArgLocs;
3465 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3468 // Allocate shadow area for Win64
3470 CCInfo.AllocateStack(32, 8);
3472 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3473 if (CCInfo.getNextStackOffset()) {
3474 MachineFunction &MF = DAG.getMachineFunction();
3475 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3478 // Check if the arguments are already laid out in the right way as
3479 // the caller's fixed stack objects.
3480 MachineFrameInfo *MFI = MF.getFrameInfo();
3481 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3482 const X86InstrInfo *TII =
3483 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3484 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3485 CCValAssign &VA = ArgLocs[i];
3486 SDValue Arg = OutVals[i];
3487 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3488 if (VA.getLocInfo() == CCValAssign::Indirect)
3490 if (!VA.isRegLoc()) {
3491 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3498 // If the tailcall address may be in a register, then make sure it's
3499 // possible to register allocate for it. In 32-bit, the call address can
3500 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3501 // callee-saved registers are restored. These happen to be the same
3502 // registers used to pass 'inreg' arguments so watch out for those.
3503 if (!Subtarget->is64Bit() &&
3504 ((!isa<GlobalAddressSDNode>(Callee) &&
3505 !isa<ExternalSymbolSDNode>(Callee)) ||
3506 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3507 unsigned NumInRegs = 0;
3508 // In PIC we need an extra register to formulate the address computation
3510 unsigned MaxInRegs =
3511 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3513 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3514 CCValAssign &VA = ArgLocs[i];
3517 unsigned Reg = VA.getLocReg();
3520 case X86::EAX: case X86::EDX: case X86::ECX:
3521 if (++NumInRegs == MaxInRegs)
3533 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3534 const TargetLibraryInfo *libInfo) const {
3535 return X86::createFastISel(funcInfo, libInfo);
3538 //===----------------------------------------------------------------------===//
3539 // Other Lowering Hooks
3540 //===----------------------------------------------------------------------===//
3542 static bool MayFoldLoad(SDValue Op) {
3543 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3546 static bool MayFoldIntoStore(SDValue Op) {
3547 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3550 static bool isTargetShuffle(unsigned Opcode) {
3552 default: return false;
3553 case X86ISD::BLENDI:
3554 case X86ISD::PSHUFB:
3555 case X86ISD::PSHUFD:
3556 case X86ISD::PSHUFHW:
3557 case X86ISD::PSHUFLW:
3559 case X86ISD::PALIGNR:
3560 case X86ISD::MOVLHPS:
3561 case X86ISD::MOVLHPD:
3562 case X86ISD::MOVHLPS:
3563 case X86ISD::MOVLPS:
3564 case X86ISD::MOVLPD:
3565 case X86ISD::MOVSHDUP:
3566 case X86ISD::MOVSLDUP:
3567 case X86ISD::MOVDDUP:
3570 case X86ISD::UNPCKL:
3571 case X86ISD::UNPCKH:
3572 case X86ISD::VPERMILPI:
3573 case X86ISD::VPERM2X128:
3574 case X86ISD::VPERMI:
3579 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3580 SDValue V1, SelectionDAG &DAG) {
3582 default: llvm_unreachable("Unknown x86 shuffle node");
3583 case X86ISD::MOVSHDUP:
3584 case X86ISD::MOVSLDUP:
3585 case X86ISD::MOVDDUP:
3586 return DAG.getNode(Opc, dl, VT, V1);
3590 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3591 SDValue V1, unsigned TargetMask,
3592 SelectionDAG &DAG) {
3594 default: llvm_unreachable("Unknown x86 shuffle node");
3595 case X86ISD::PSHUFD:
3596 case X86ISD::PSHUFHW:
3597 case X86ISD::PSHUFLW:
3598 case X86ISD::VPERMILPI:
3599 case X86ISD::VPERMI:
3600 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3604 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3605 SDValue V1, SDValue V2, unsigned TargetMask,
3606 SelectionDAG &DAG) {
3608 default: llvm_unreachable("Unknown x86 shuffle node");
3609 case X86ISD::PALIGNR:
3610 case X86ISD::VALIGN:
3612 case X86ISD::VPERM2X128:
3613 return DAG.getNode(Opc, dl, VT, V1, V2,
3614 DAG.getConstant(TargetMask, MVT::i8));
3618 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3619 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3621 default: llvm_unreachable("Unknown x86 shuffle node");
3622 case X86ISD::MOVLHPS:
3623 case X86ISD::MOVLHPD:
3624 case X86ISD::MOVHLPS:
3625 case X86ISD::MOVLPS:
3626 case X86ISD::MOVLPD:
3629 case X86ISD::UNPCKL:
3630 case X86ISD::UNPCKH:
3631 return DAG.getNode(Opc, dl, VT, V1, V2);
3635 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3636 MachineFunction &MF = DAG.getMachineFunction();
3637 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3638 DAG.getSubtarget().getRegisterInfo());
3639 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3640 int ReturnAddrIndex = FuncInfo->getRAIndex();
3642 if (ReturnAddrIndex == 0) {
3643 // Set up a frame object for the return address.
3644 unsigned SlotSize = RegInfo->getSlotSize();
3645 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3648 FuncInfo->setRAIndex(ReturnAddrIndex);
3651 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3654 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3655 bool hasSymbolicDisplacement) {
3656 // Offset should fit into 32 bit immediate field.
3657 if (!isInt<32>(Offset))
3660 // If we don't have a symbolic displacement - we don't have any extra
3662 if (!hasSymbolicDisplacement)
3665 // FIXME: Some tweaks might be needed for medium code model.
3666 if (M != CodeModel::Small && M != CodeModel::Kernel)
3669 // For small code model we assume that latest object is 16MB before end of 31
3670 // bits boundary. We may also accept pretty large negative constants knowing
3671 // that all objects are in the positive half of address space.
3672 if (M == CodeModel::Small && Offset < 16*1024*1024)
3675 // For kernel code model we know that all object resist in the negative half
3676 // of 32bits address space. We may not accept negative offsets, since they may
3677 // be just off and we may accept pretty large positive ones.
3678 if (M == CodeModel::Kernel && Offset > 0)
3684 /// isCalleePop - Determines whether the callee is required to pop its
3685 /// own arguments. Callee pop is necessary to support tail calls.
3686 bool X86::isCalleePop(CallingConv::ID CallingConv,
3687 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3688 switch (CallingConv) {
3691 case CallingConv::X86_StdCall:
3692 case CallingConv::X86_FastCall:
3693 case CallingConv::X86_ThisCall:
3695 case CallingConv::Fast:
3696 case CallingConv::GHC:
3697 case CallingConv::HiPE:
3704 /// \brief Return true if the condition is an unsigned comparison operation.
3705 static bool isX86CCUnsigned(unsigned X86CC) {
3707 default: llvm_unreachable("Invalid integer condition!");
3708 case X86::COND_E: return true;
3709 case X86::COND_G: return false;
3710 case X86::COND_GE: return false;
3711 case X86::COND_L: return false;
3712 case X86::COND_LE: return false;
3713 case X86::COND_NE: return true;
3714 case X86::COND_B: return true;
3715 case X86::COND_A: return true;
3716 case X86::COND_BE: return true;
3717 case X86::COND_AE: return true;
3719 llvm_unreachable("covered switch fell through?!");
3722 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3723 /// specific condition code, returning the condition code and the LHS/RHS of the
3724 /// comparison to make.
3725 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3726 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3728 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3729 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3730 // X > -1 -> X == 0, jump !sign.
3731 RHS = DAG.getConstant(0, RHS.getValueType());
3732 return X86::COND_NS;
3734 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3735 // X < 0 -> X == 0, jump on sign.
3738 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3740 RHS = DAG.getConstant(0, RHS.getValueType());
3741 return X86::COND_LE;
3745 switch (SetCCOpcode) {
3746 default: llvm_unreachable("Invalid integer condition!");
3747 case ISD::SETEQ: return X86::COND_E;
3748 case ISD::SETGT: return X86::COND_G;
3749 case ISD::SETGE: return X86::COND_GE;
3750 case ISD::SETLT: return X86::COND_L;
3751 case ISD::SETLE: return X86::COND_LE;
3752 case ISD::SETNE: return X86::COND_NE;
3753 case ISD::SETULT: return X86::COND_B;
3754 case ISD::SETUGT: return X86::COND_A;
3755 case ISD::SETULE: return X86::COND_BE;
3756 case ISD::SETUGE: return X86::COND_AE;
3760 // First determine if it is required or is profitable to flip the operands.
3762 // If LHS is a foldable load, but RHS is not, flip the condition.
3763 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3764 !ISD::isNON_EXTLoad(RHS.getNode())) {
3765 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3766 std::swap(LHS, RHS);
3769 switch (SetCCOpcode) {
3775 std::swap(LHS, RHS);
3779 // On a floating point condition, the flags are set as follows:
3781 // 0 | 0 | 0 | X > Y
3782 // 0 | 0 | 1 | X < Y
3783 // 1 | 0 | 0 | X == Y
3784 // 1 | 1 | 1 | unordered
3785 switch (SetCCOpcode) {
3786 default: llvm_unreachable("Condcode should be pre-legalized away");
3788 case ISD::SETEQ: return X86::COND_E;
3789 case ISD::SETOLT: // flipped
3791 case ISD::SETGT: return X86::COND_A;
3792 case ISD::SETOLE: // flipped
3794 case ISD::SETGE: return X86::COND_AE;
3795 case ISD::SETUGT: // flipped
3797 case ISD::SETLT: return X86::COND_B;
3798 case ISD::SETUGE: // flipped
3800 case ISD::SETLE: return X86::COND_BE;
3802 case ISD::SETNE: return X86::COND_NE;
3803 case ISD::SETUO: return X86::COND_P;
3804 case ISD::SETO: return X86::COND_NP;
3806 case ISD::SETUNE: return X86::COND_INVALID;
3810 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3811 /// code. Current x86 isa includes the following FP cmov instructions:
3812 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3813 static bool hasFPCMov(unsigned X86CC) {
3829 /// isFPImmLegal - Returns true if the target can instruction select the
3830 /// specified FP immediate natively. If false, the legalizer will
3831 /// materialize the FP immediate as a load from a constant pool.
3832 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3833 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3834 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3840 /// \brief Returns true if it is beneficial to convert a load of a constant
3841 /// to just the constant itself.
3842 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3844 assert(Ty->isIntegerTy());
3846 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3847 if (BitSize == 0 || BitSize > 64)
3852 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3853 /// the specified range (L, H].
3854 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3855 return (Val < 0) || (Val >= Low && Val < Hi);
3858 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3859 /// specified value.
3860 static bool isUndefOrEqual(int Val, int CmpVal) {
3861 return (Val < 0 || Val == CmpVal);
3864 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3865 /// from position Pos and ending in Pos+Size, falls within the specified
3866 /// sequential range (L, L+Pos]. or is undef.
3867 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3868 unsigned Pos, unsigned Size, int Low) {
3869 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3870 if (!isUndefOrEqual(Mask[i], Low))
3875 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3876 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3877 /// the second operand.
3878 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3879 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3880 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3881 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3882 return (Mask[0] < 2 && Mask[1] < 2);
3886 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3887 /// is suitable for input to PSHUFHW.
3888 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3889 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3892 // Lower quadword copied in order or undef.
3893 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3896 // Upper quadword shuffled.
3897 for (unsigned i = 4; i != 8; ++i)
3898 if (!isUndefOrInRange(Mask[i], 4, 8))
3901 if (VT == MVT::v16i16) {
3902 // Lower quadword copied in order or undef.
3903 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3906 // Upper quadword shuffled.
3907 for (unsigned i = 12; i != 16; ++i)
3908 if (!isUndefOrInRange(Mask[i], 12, 16))
3915 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3916 /// is suitable for input to PSHUFLW.
3917 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3918 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3921 // Upper quadword copied in order.
3922 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3925 // Lower quadword shuffled.
3926 for (unsigned i = 0; i != 4; ++i)
3927 if (!isUndefOrInRange(Mask[i], 0, 4))
3930 if (VT == MVT::v16i16) {
3931 // Upper quadword copied in order.
3932 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3935 // Lower quadword shuffled.
3936 for (unsigned i = 8; i != 12; ++i)
3937 if (!isUndefOrInRange(Mask[i], 8, 12))
3944 /// \brief Return true if the mask specifies a shuffle of elements that is
3945 /// suitable for input to intralane (palignr) or interlane (valign) vector
3947 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3948 unsigned NumElts = VT.getVectorNumElements();
3949 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3950 unsigned NumLaneElts = NumElts/NumLanes;
3952 // Do not handle 64-bit element shuffles with palignr.
3953 if (NumLaneElts == 2)
3956 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3958 for (i = 0; i != NumLaneElts; ++i) {
3963 // Lane is all undef, go to next lane
3964 if (i == NumLaneElts)
3967 int Start = Mask[i+l];
3969 // Make sure its in this lane in one of the sources
3970 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3971 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3974 // If not lane 0, then we must match lane 0
3975 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3978 // Correct second source to be contiguous with first source
3979 if (Start >= (int)NumElts)
3980 Start -= NumElts - NumLaneElts;
3982 // Make sure we're shifting in the right direction.
3983 if (Start <= (int)(i+l))
3988 // Check the rest of the elements to see if they are consecutive.
3989 for (++i; i != NumLaneElts; ++i) {
3990 int Idx = Mask[i+l];
3992 // Make sure its in this lane
3993 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3994 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3997 // If not lane 0, then we must match lane 0
3998 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4001 if (Idx >= (int)NumElts)
4002 Idx -= NumElts - NumLaneElts;
4004 if (!isUndefOrEqual(Idx, Start+i))
4013 /// \brief Return true if the node specifies a shuffle of elements that is
4014 /// suitable for input to PALIGNR.
4015 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4016 const X86Subtarget *Subtarget) {
4017 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4018 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4019 VT.is512BitVector())
4020 // FIXME: Add AVX512BW.
4023 return isAlignrMask(Mask, VT, false);
4026 /// \brief Return true if the node specifies a shuffle of elements that is
4027 /// suitable for input to VALIGN.
4028 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4029 const X86Subtarget *Subtarget) {
4030 // FIXME: Add AVX512VL.
4031 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4033 return isAlignrMask(Mask, VT, true);
4036 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4037 /// the two vector operands have swapped position.
4038 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4039 unsigned NumElems) {
4040 for (unsigned i = 0; i != NumElems; ++i) {
4044 else if (idx < (int)NumElems)
4045 Mask[i] = idx + NumElems;
4047 Mask[i] = idx - NumElems;
4051 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4052 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4053 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4054 /// reverse of what x86 shuffles want.
4055 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4057 unsigned NumElems = VT.getVectorNumElements();
4058 unsigned NumLanes = VT.getSizeInBits()/128;
4059 unsigned NumLaneElems = NumElems/NumLanes;
4061 if (NumLaneElems != 2 && NumLaneElems != 4)
4064 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4065 bool symetricMaskRequired =
4066 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4068 // VSHUFPSY divides the resulting vector into 4 chunks.
4069 // The sources are also splitted into 4 chunks, and each destination
4070 // chunk must come from a different source chunk.
4072 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4073 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4075 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4076 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4078 // VSHUFPDY divides the resulting vector into 4 chunks.
4079 // The sources are also splitted into 4 chunks, and each destination
4080 // chunk must come from a different source chunk.
4082 // SRC1 => X3 X2 X1 X0
4083 // SRC2 => Y3 Y2 Y1 Y0
4085 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4087 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4088 unsigned HalfLaneElems = NumLaneElems/2;
4089 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4090 for (unsigned i = 0; i != NumLaneElems; ++i) {
4091 int Idx = Mask[i+l];
4092 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4093 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4095 // For VSHUFPSY, the mask of the second half must be the same as the
4096 // first but with the appropriate offsets. This works in the same way as
4097 // VPERMILPS works with masks.
4098 if (!symetricMaskRequired || Idx < 0)
4100 if (MaskVal[i] < 0) {
4101 MaskVal[i] = Idx - l;
4104 if ((signed)(Idx - l) != MaskVal[i])
4112 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4113 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4114 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4115 if (!VT.is128BitVector())
4118 unsigned NumElems = VT.getVectorNumElements();
4123 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4124 return isUndefOrEqual(Mask[0], 6) &&
4125 isUndefOrEqual(Mask[1], 7) &&
4126 isUndefOrEqual(Mask[2], 2) &&
4127 isUndefOrEqual(Mask[3], 3);
4130 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4131 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4133 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4134 if (!VT.is128BitVector())
4137 unsigned NumElems = VT.getVectorNumElements();
4142 return isUndefOrEqual(Mask[0], 2) &&
4143 isUndefOrEqual(Mask[1], 3) &&
4144 isUndefOrEqual(Mask[2], 2) &&
4145 isUndefOrEqual(Mask[3], 3);
4148 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4149 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4150 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4151 if (!VT.is128BitVector())
4154 unsigned NumElems = VT.getVectorNumElements();
4156 if (NumElems != 2 && NumElems != 4)
4159 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4160 if (!isUndefOrEqual(Mask[i], i + NumElems))
4163 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4164 if (!isUndefOrEqual(Mask[i], i))
4170 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4171 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4172 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4173 if (!VT.is128BitVector())
4176 unsigned NumElems = VT.getVectorNumElements();
4178 if (NumElems != 2 && NumElems != 4)
4181 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4182 if (!isUndefOrEqual(Mask[i], i))
4185 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4186 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4192 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4193 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4194 /// i. e: If all but one element come from the same vector.
4195 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4196 // TODO: Deal with AVX's VINSERTPS
4197 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4200 unsigned CorrectPosV1 = 0;
4201 unsigned CorrectPosV2 = 0;
4202 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4203 if (Mask[i] == -1) {
4211 else if (Mask[i] == i + 4)
4215 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4216 // We have 3 elements (undefs count as elements from any vector) from one
4217 // vector, and one from another.
4224 // Some special combinations that can be optimized.
4227 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4228 SelectionDAG &DAG) {
4229 MVT VT = SVOp->getSimpleValueType(0);
4232 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4235 ArrayRef<int> Mask = SVOp->getMask();
4237 // These are the special masks that may be optimized.
4238 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4239 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4240 bool MatchEvenMask = true;
4241 bool MatchOddMask = true;
4242 for (int i=0; i<8; ++i) {
4243 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4244 MatchEvenMask = false;
4245 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4246 MatchOddMask = false;
4249 if (!MatchEvenMask && !MatchOddMask)
4252 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4254 SDValue Op0 = SVOp->getOperand(0);
4255 SDValue Op1 = SVOp->getOperand(1);
4257 if (MatchEvenMask) {
4258 // Shift the second operand right to 32 bits.
4259 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4260 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4262 // Shift the first operand left to 32 bits.
4263 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4264 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4266 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4267 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4270 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4271 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4272 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4273 bool HasInt256, bool V2IsSplat = false) {
4275 assert(VT.getSizeInBits() >= 128 &&
4276 "Unsupported vector type for unpckl");
4278 unsigned NumElts = VT.getVectorNumElements();
4279 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4280 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4283 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4284 "Unsupported vector type for unpckh");
4286 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4287 unsigned NumLanes = VT.getSizeInBits()/128;
4288 unsigned NumLaneElts = NumElts/NumLanes;
4290 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4291 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4292 int BitI = Mask[l+i];
4293 int BitI1 = Mask[l+i+1];
4294 if (!isUndefOrEqual(BitI, j))
4297 if (!isUndefOrEqual(BitI1, NumElts))
4300 if (!isUndefOrEqual(BitI1, j + NumElts))
4309 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4310 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4311 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4312 bool HasInt256, bool V2IsSplat = false) {
4313 assert(VT.getSizeInBits() >= 128 &&
4314 "Unsupported vector type for unpckh");
4316 unsigned NumElts = VT.getVectorNumElements();
4317 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4318 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4321 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4322 "Unsupported vector type for unpckh");
4324 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4325 unsigned NumLanes = VT.getSizeInBits()/128;
4326 unsigned NumLaneElts = NumElts/NumLanes;
4328 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4329 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4330 int BitI = Mask[l+i];
4331 int BitI1 = Mask[l+i+1];
4332 if (!isUndefOrEqual(BitI, j))
4335 if (isUndefOrEqual(BitI1, NumElts))
4338 if (!isUndefOrEqual(BitI1, j+NumElts))
4346 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4347 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4349 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4350 unsigned NumElts = VT.getVectorNumElements();
4351 bool Is256BitVec = VT.is256BitVector();
4353 if (VT.is512BitVector())
4355 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4356 "Unsupported vector type for unpckh");
4358 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4359 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4362 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4363 // FIXME: Need a better way to get rid of this, there's no latency difference
4364 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4365 // the former later. We should also remove the "_undef" special mask.
4366 if (NumElts == 4 && Is256BitVec)
4369 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4370 // independently on 128-bit lanes.
4371 unsigned NumLanes = VT.getSizeInBits()/128;
4372 unsigned NumLaneElts = NumElts/NumLanes;
4374 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4375 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4376 int BitI = Mask[l+i];
4377 int BitI1 = Mask[l+i+1];
4379 if (!isUndefOrEqual(BitI, j))
4381 if (!isUndefOrEqual(BitI1, j))
4389 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4390 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4392 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4393 unsigned NumElts = VT.getVectorNumElements();
4395 if (VT.is512BitVector())
4398 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4399 "Unsupported vector type for unpckh");
4401 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4402 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4405 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4406 // independently on 128-bit lanes.
4407 unsigned NumLanes = VT.getSizeInBits()/128;
4408 unsigned NumLaneElts = NumElts/NumLanes;
4410 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4411 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4412 int BitI = Mask[l+i];
4413 int BitI1 = Mask[l+i+1];
4414 if (!isUndefOrEqual(BitI, j))
4416 if (!isUndefOrEqual(BitI1, j))
4423 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4424 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4425 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4426 if (!VT.is512BitVector())
4429 unsigned NumElts = VT.getVectorNumElements();
4430 unsigned HalfSize = NumElts/2;
4431 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4432 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4437 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4438 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4446 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4447 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4448 /// MOVSD, and MOVD, i.e. setting the lowest element.
4449 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4450 if (VT.getVectorElementType().getSizeInBits() < 32)
4452 if (!VT.is128BitVector())
4455 unsigned NumElts = VT.getVectorNumElements();
4457 if (!isUndefOrEqual(Mask[0], NumElts))
4460 for (unsigned i = 1; i != NumElts; ++i)
4461 if (!isUndefOrEqual(Mask[i], i))
4467 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4468 /// as permutations between 128-bit chunks or halves. As an example: this
4470 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4471 /// The first half comes from the second half of V1 and the second half from the
4472 /// the second half of V2.
4473 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4474 if (!HasFp256 || !VT.is256BitVector())
4477 // The shuffle result is divided into half A and half B. In total the two
4478 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4479 // B must come from C, D, E or F.
4480 unsigned HalfSize = VT.getVectorNumElements()/2;
4481 bool MatchA = false, MatchB = false;
4483 // Check if A comes from one of C, D, E, F.
4484 for (unsigned Half = 0; Half != 4; ++Half) {
4485 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4491 // Check if B comes from one of C, D, E, F.
4492 for (unsigned Half = 0; Half != 4; ++Half) {
4493 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4499 return MatchA && MatchB;
4502 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4503 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4504 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4505 MVT VT = SVOp->getSimpleValueType(0);
4507 unsigned HalfSize = VT.getVectorNumElements()/2;
4509 unsigned FstHalf = 0, SndHalf = 0;
4510 for (unsigned i = 0; i < HalfSize; ++i) {
4511 if (SVOp->getMaskElt(i) > 0) {
4512 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4516 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4517 if (SVOp->getMaskElt(i) > 0) {
4518 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4523 return (FstHalf | (SndHalf << 4));
4526 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4527 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4528 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4532 unsigned NumElts = VT.getVectorNumElements();
4534 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4535 for (unsigned i = 0; i != NumElts; ++i) {
4538 Imm8 |= Mask[i] << (i*2);
4543 unsigned LaneSize = 4;
4544 SmallVector<int, 4> MaskVal(LaneSize, -1);
4546 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4547 for (unsigned i = 0; i != LaneSize; ++i) {
4548 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4552 if (MaskVal[i] < 0) {
4553 MaskVal[i] = Mask[i+l] - l;
4554 Imm8 |= MaskVal[i] << (i*2);
4557 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4564 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4565 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4566 /// Note that VPERMIL mask matching is different depending whether theunderlying
4567 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4568 /// to the same elements of the low, but to the higher half of the source.
4569 /// In VPERMILPD the two lanes could be shuffled independently of each other
4570 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4571 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4572 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4573 if (VT.getSizeInBits() < 256 || EltSize < 32)
4575 bool symetricMaskRequired = (EltSize == 32);
4576 unsigned NumElts = VT.getVectorNumElements();
4578 unsigned NumLanes = VT.getSizeInBits()/128;
4579 unsigned LaneSize = NumElts/NumLanes;
4580 // 2 or 4 elements in one lane
4582 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4583 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4584 for (unsigned i = 0; i != LaneSize; ++i) {
4585 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4587 if (symetricMaskRequired) {
4588 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4589 ExpectedMaskVal[i] = Mask[i+l] - l;
4592 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4600 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4601 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4602 /// element of vector 2 and the other elements to come from vector 1 in order.
4603 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4604 bool V2IsSplat = false, bool V2IsUndef = false) {
4605 if (!VT.is128BitVector())
4608 unsigned NumOps = VT.getVectorNumElements();
4609 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4612 if (!isUndefOrEqual(Mask[0], 0))
4615 for (unsigned i = 1; i != NumOps; ++i)
4616 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4617 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4618 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4624 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4625 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4626 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4627 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4628 const X86Subtarget *Subtarget) {
4629 if (!Subtarget->hasSSE3())
4632 unsigned NumElems = VT.getVectorNumElements();
4634 if ((VT.is128BitVector() && NumElems != 4) ||
4635 (VT.is256BitVector() && NumElems != 8) ||
4636 (VT.is512BitVector() && NumElems != 16))
4639 // "i+1" is the value the indexed mask element must have
4640 for (unsigned i = 0; i != NumElems; i += 2)
4641 if (!isUndefOrEqual(Mask[i], i+1) ||
4642 !isUndefOrEqual(Mask[i+1], i+1))
4648 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4649 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4650 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4651 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4652 const X86Subtarget *Subtarget) {
4653 if (!Subtarget->hasSSE3())
4656 unsigned NumElems = VT.getVectorNumElements();
4658 if ((VT.is128BitVector() && NumElems != 4) ||
4659 (VT.is256BitVector() && NumElems != 8) ||
4660 (VT.is512BitVector() && NumElems != 16))
4663 // "i" is the value the indexed mask element must have
4664 for (unsigned i = 0; i != NumElems; i += 2)
4665 if (!isUndefOrEqual(Mask[i], i) ||
4666 !isUndefOrEqual(Mask[i+1], i))
4672 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4673 /// specifies a shuffle of elements that is suitable for input to 256-bit
4674 /// version of MOVDDUP.
4675 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4676 if (!HasFp256 || !VT.is256BitVector())
4679 unsigned NumElts = VT.getVectorNumElements();
4683 for (unsigned i = 0; i != NumElts/2; ++i)
4684 if (!isUndefOrEqual(Mask[i], 0))
4686 for (unsigned i = NumElts/2; i != NumElts; ++i)
4687 if (!isUndefOrEqual(Mask[i], NumElts/2))
4692 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4693 /// specifies a shuffle of elements that is suitable for input to 128-bit
4694 /// version of MOVDDUP.
4695 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4696 if (!VT.is128BitVector())
4699 unsigned e = VT.getVectorNumElements() / 2;
4700 for (unsigned i = 0; i != e; ++i)
4701 if (!isUndefOrEqual(Mask[i], i))
4703 for (unsigned i = 0; i != e; ++i)
4704 if (!isUndefOrEqual(Mask[e+i], i))
4709 /// isVEXTRACTIndex - Return true if the specified
4710 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4711 /// suitable for instruction that extract 128 or 256 bit vectors
4712 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4713 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4714 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4717 // The index should be aligned on a vecWidth-bit boundary.
4719 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4721 MVT VT = N->getSimpleValueType(0);
4722 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4723 bool Result = (Index * ElSize) % vecWidth == 0;
4728 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4729 /// operand specifies a subvector insert that is suitable for input to
4730 /// insertion of 128 or 256-bit subvectors
4731 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4732 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4733 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4735 // The index should be aligned on a vecWidth-bit boundary.
4737 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4739 MVT VT = N->getSimpleValueType(0);
4740 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4741 bool Result = (Index * ElSize) % vecWidth == 0;
4746 bool X86::isVINSERT128Index(SDNode *N) {
4747 return isVINSERTIndex(N, 128);
4750 bool X86::isVINSERT256Index(SDNode *N) {
4751 return isVINSERTIndex(N, 256);
4754 bool X86::isVEXTRACT128Index(SDNode *N) {
4755 return isVEXTRACTIndex(N, 128);
4758 bool X86::isVEXTRACT256Index(SDNode *N) {
4759 return isVEXTRACTIndex(N, 256);
4762 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4763 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4764 /// Handles 128-bit and 256-bit.
4765 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4766 MVT VT = N->getSimpleValueType(0);
4768 assert((VT.getSizeInBits() >= 128) &&
4769 "Unsupported vector type for PSHUF/SHUFP");
4771 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4772 // independently on 128-bit lanes.
4773 unsigned NumElts = VT.getVectorNumElements();
4774 unsigned NumLanes = VT.getSizeInBits()/128;
4775 unsigned NumLaneElts = NumElts/NumLanes;
4777 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4778 "Only supports 2, 4 or 8 elements per lane");
4780 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4782 for (unsigned i = 0; i != NumElts; ++i) {
4783 int Elt = N->getMaskElt(i);
4784 if (Elt < 0) continue;
4785 Elt &= NumLaneElts - 1;
4786 unsigned ShAmt = (i << Shift) % 8;
4787 Mask |= Elt << ShAmt;
4793 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4794 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4795 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4796 MVT VT = N->getSimpleValueType(0);
4798 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4799 "Unsupported vector type for PSHUFHW");
4801 unsigned NumElts = VT.getVectorNumElements();
4804 for (unsigned l = 0; l != NumElts; l += 8) {
4805 // 8 nodes per lane, but we only care about the last 4.
4806 for (unsigned i = 0; i < 4; ++i) {
4807 int Elt = N->getMaskElt(l+i+4);
4808 if (Elt < 0) continue;
4809 Elt &= 0x3; // only 2-bits.
4810 Mask |= Elt << (i * 2);
4817 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4818 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4819 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4820 MVT VT = N->getSimpleValueType(0);
4822 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4823 "Unsupported vector type for PSHUFHW");
4825 unsigned NumElts = VT.getVectorNumElements();
4828 for (unsigned l = 0; l != NumElts; l += 8) {
4829 // 8 nodes per lane, but we only care about the first 4.
4830 for (unsigned i = 0; i < 4; ++i) {
4831 int Elt = N->getMaskElt(l+i);
4832 if (Elt < 0) continue;
4833 Elt &= 0x3; // only 2-bits
4834 Mask |= Elt << (i * 2);
4841 /// \brief Return the appropriate immediate to shuffle the specified
4842 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4843 /// VALIGN (if Interlane is true) instructions.
4844 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4846 MVT VT = SVOp->getSimpleValueType(0);
4847 unsigned EltSize = InterLane ? 1 :
4848 VT.getVectorElementType().getSizeInBits() >> 3;
4850 unsigned NumElts = VT.getVectorNumElements();
4851 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4852 unsigned NumLaneElts = NumElts/NumLanes;
4856 for (i = 0; i != NumElts; ++i) {
4857 Val = SVOp->getMaskElt(i);
4861 if (Val >= (int)NumElts)
4862 Val -= NumElts - NumLaneElts;
4864 assert(Val - i > 0 && "PALIGNR imm should be positive");
4865 return (Val - i) * EltSize;
4868 /// \brief Return the appropriate immediate to shuffle the specified
4869 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4870 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4871 return getShuffleAlignrImmediate(SVOp, false);
4874 /// \brief Return the appropriate immediate to shuffle the specified
4875 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4876 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4877 return getShuffleAlignrImmediate(SVOp, true);
4881 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4882 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4883 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4884 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4887 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4889 MVT VecVT = N->getOperand(0).getSimpleValueType();
4890 MVT ElVT = VecVT.getVectorElementType();
4892 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4893 return Index / NumElemsPerChunk;
4896 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4897 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4898 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4899 llvm_unreachable("Illegal insert subvector for VINSERT");
4902 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4904 MVT VecVT = N->getSimpleValueType(0);
4905 MVT ElVT = VecVT.getVectorElementType();
4907 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4908 return Index / NumElemsPerChunk;
4911 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4912 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4913 /// and VINSERTI128 instructions.
4914 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4915 return getExtractVEXTRACTImmediate(N, 128);
4918 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4919 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4920 /// and VINSERTI64x4 instructions.
4921 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4922 return getExtractVEXTRACTImmediate(N, 256);
4925 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4926 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4927 /// and VINSERTI128 instructions.
4928 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4929 return getInsertVINSERTImmediate(N, 128);
4932 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4933 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4934 /// and VINSERTI64x4 instructions.
4935 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4936 return getInsertVINSERTImmediate(N, 256);
4939 /// isZero - Returns true if Elt is a constant integer zero
4940 static bool isZero(SDValue V) {
4941 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4942 return C && C->isNullValue();
4945 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4947 bool X86::isZeroNode(SDValue Elt) {
4950 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4951 return CFP->getValueAPF().isPosZero();
4955 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4956 /// match movhlps. The lower half elements should come from upper half of
4957 /// V1 (and in order), and the upper half elements should come from the upper
4958 /// half of V2 (and in order).
4959 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4960 if (!VT.is128BitVector())
4962 if (VT.getVectorNumElements() != 4)
4964 for (unsigned i = 0, e = 2; i != e; ++i)
4965 if (!isUndefOrEqual(Mask[i], i+2))
4967 for (unsigned i = 2; i != 4; ++i)
4968 if (!isUndefOrEqual(Mask[i], i+4))
4973 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4974 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4976 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4977 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4979 N = N->getOperand(0).getNode();
4980 if (!ISD::isNON_EXTLoad(N))
4983 *LD = cast<LoadSDNode>(N);
4987 // Test whether the given value is a vector value which will be legalized
4989 static bool WillBeConstantPoolLoad(SDNode *N) {
4990 if (N->getOpcode() != ISD::BUILD_VECTOR)
4993 // Check for any non-constant elements.
4994 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4995 switch (N->getOperand(i).getNode()->getOpcode()) {
4997 case ISD::ConstantFP:
5004 // Vectors of all-zeros and all-ones are materialized with special
5005 // instructions rather than being loaded.
5006 return !ISD::isBuildVectorAllZeros(N) &&
5007 !ISD::isBuildVectorAllOnes(N);
5010 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5011 /// match movlp{s|d}. The lower half elements should come from lower half of
5012 /// V1 (and in order), and the upper half elements should come from the upper
5013 /// half of V2 (and in order). And since V1 will become the source of the
5014 /// MOVLP, it must be either a vector load or a scalar load to vector.
5015 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5016 ArrayRef<int> Mask, MVT VT) {
5017 if (!VT.is128BitVector())
5020 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5022 // Is V2 is a vector load, don't do this transformation. We will try to use
5023 // load folding shufps op.
5024 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5027 unsigned NumElems = VT.getVectorNumElements();
5029 if (NumElems != 2 && NumElems != 4)
5031 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5032 if (!isUndefOrEqual(Mask[i], i))
5034 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5035 if (!isUndefOrEqual(Mask[i], i+NumElems))
5040 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5041 /// to an zero vector.
5042 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5043 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5044 SDValue V1 = N->getOperand(0);
5045 SDValue V2 = N->getOperand(1);
5046 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5047 for (unsigned i = 0; i != NumElems; ++i) {
5048 int Idx = N->getMaskElt(i);
5049 if (Idx >= (int)NumElems) {
5050 unsigned Opc = V2.getOpcode();
5051 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5053 if (Opc != ISD::BUILD_VECTOR ||
5054 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5056 } else if (Idx >= 0) {
5057 unsigned Opc = V1.getOpcode();
5058 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5060 if (Opc != ISD::BUILD_VECTOR ||
5061 !X86::isZeroNode(V1.getOperand(Idx)))
5068 /// getZeroVector - Returns a vector of specified type with all zero elements.
5070 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5071 SelectionDAG &DAG, SDLoc dl) {
5072 assert(VT.isVector() && "Expected a vector type");
5074 // Always build SSE zero vectors as <4 x i32> bitcasted
5075 // to their dest type. This ensures they get CSE'd.
5077 if (VT.is128BitVector()) { // SSE
5078 if (Subtarget->hasSSE2()) { // SSE2
5079 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5080 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5082 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5085 } else if (VT.is256BitVector()) { // AVX
5086 if (Subtarget->hasInt256()) { // AVX2
5087 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5088 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5089 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5091 // 256-bit logic and arithmetic instructions in AVX are all
5092 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5093 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5094 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5095 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5097 } else if (VT.is512BitVector()) { // AVX-512
5098 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5099 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5100 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5101 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5102 } else if (VT.getScalarType() == MVT::i1) {
5103 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5104 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5105 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5106 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5108 llvm_unreachable("Unexpected vector type");
5110 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5113 /// getOnesVector - Returns a vector of specified type with all bits set.
5114 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5115 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5116 /// Then bitcast to their original type, ensuring they get CSE'd.
5117 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5119 assert(VT.isVector() && "Expected a vector type");
5121 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5123 if (VT.is256BitVector()) {
5124 if (HasInt256) { // AVX2
5125 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5126 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5128 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5129 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5131 } else if (VT.is128BitVector()) {
5132 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5134 llvm_unreachable("Unexpected vector type");
5136 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5139 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5140 /// that point to V2 points to its first element.
5141 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5142 for (unsigned i = 0; i != NumElems; ++i) {
5143 if (Mask[i] > (int)NumElems) {
5149 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5150 /// operation of specified width.
5151 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5153 unsigned NumElems = VT.getVectorNumElements();
5154 SmallVector<int, 8> Mask;
5155 Mask.push_back(NumElems);
5156 for (unsigned i = 1; i != NumElems; ++i)
5158 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5161 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5162 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5164 unsigned NumElems = VT.getVectorNumElements();
5165 SmallVector<int, 8> Mask;
5166 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5168 Mask.push_back(i + NumElems);
5170 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5173 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5174 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5176 unsigned NumElems = VT.getVectorNumElements();
5177 SmallVector<int, 8> Mask;
5178 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5179 Mask.push_back(i + Half);
5180 Mask.push_back(i + NumElems + Half);
5182 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5185 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5186 // a generic shuffle instruction because the target has no such instructions.
5187 // Generate shuffles which repeat i16 and i8 several times until they can be
5188 // represented by v4f32 and then be manipulated by target suported shuffles.
5189 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5190 MVT VT = V.getSimpleValueType();
5191 int NumElems = VT.getVectorNumElements();
5194 while (NumElems > 4) {
5195 if (EltNo < NumElems/2) {
5196 V = getUnpackl(DAG, dl, VT, V, V);
5198 V = getUnpackh(DAG, dl, VT, V, V);
5199 EltNo -= NumElems/2;
5206 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5207 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5208 MVT VT = V.getSimpleValueType();
5211 if (VT.is128BitVector()) {
5212 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5213 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5214 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5216 } else if (VT.is256BitVector()) {
5217 // To use VPERMILPS to splat scalars, the second half of indicies must
5218 // refer to the higher part, which is a duplication of the lower one,
5219 // because VPERMILPS can only handle in-lane permutations.
5220 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5221 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5223 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5224 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5227 llvm_unreachable("Vector size not supported");
5229 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5232 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5233 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5234 MVT SrcVT = SV->getSimpleValueType(0);
5235 SDValue V1 = SV->getOperand(0);
5238 int EltNo = SV->getSplatIndex();
5239 int NumElems = SrcVT.getVectorNumElements();
5240 bool Is256BitVec = SrcVT.is256BitVector();
5242 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5243 "Unknown how to promote splat for type");
5245 // Extract the 128-bit part containing the splat element and update
5246 // the splat element index when it refers to the higher register.
5248 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5249 if (EltNo >= NumElems/2)
5250 EltNo -= NumElems/2;
5253 // All i16 and i8 vector types can't be used directly by a generic shuffle
5254 // instruction because the target has no such instruction. Generate shuffles
5255 // which repeat i16 and i8 several times until they fit in i32, and then can
5256 // be manipulated by target suported shuffles.
5257 MVT EltVT = SrcVT.getVectorElementType();
5258 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5259 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5261 // Recreate the 256-bit vector and place the same 128-bit vector
5262 // into the low and high part. This is necessary because we want
5263 // to use VPERM* to shuffle the vectors
5265 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5268 return getLegalSplat(DAG, V1, EltNo);
5271 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5272 /// vector of zero or undef vector. This produces a shuffle where the low
5273 /// element of V2 is swizzled into the zero/undef vector, landing at element
5274 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5275 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5277 const X86Subtarget *Subtarget,
5278 SelectionDAG &DAG) {
5279 MVT VT = V2.getSimpleValueType();
5281 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5282 unsigned NumElems = VT.getVectorNumElements();
5283 SmallVector<int, 16> MaskVec;
5284 for (unsigned i = 0; i != NumElems; ++i)
5285 // If this is the insertion idx, put the low elt of V2 here.
5286 MaskVec.push_back(i == Idx ? NumElems : i);
5287 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5290 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5291 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5292 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5293 /// shuffles which use a single input multiple times, and in those cases it will
5294 /// adjust the mask to only have indices within that single input.
5295 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5296 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5297 unsigned NumElems = VT.getVectorNumElements();
5301 bool IsFakeUnary = false;
5302 switch(N->getOpcode()) {
5303 case X86ISD::BLENDI:
5304 ImmN = N->getOperand(N->getNumOperands()-1);
5305 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5308 ImmN = N->getOperand(N->getNumOperands()-1);
5309 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 case X86ISD::UNPCKH:
5313 DecodeUNPCKHMask(VT, Mask);
5314 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5316 case X86ISD::UNPCKL:
5317 DecodeUNPCKLMask(VT, Mask);
5318 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5320 case X86ISD::MOVHLPS:
5321 DecodeMOVHLPSMask(NumElems, Mask);
5322 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5324 case X86ISD::MOVLHPS:
5325 DecodeMOVLHPSMask(NumElems, Mask);
5326 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5328 case X86ISD::PALIGNR:
5329 ImmN = N->getOperand(N->getNumOperands()-1);
5330 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFD:
5333 case X86ISD::VPERMILPI:
5334 ImmN = N->getOperand(N->getNumOperands()-1);
5335 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5338 case X86ISD::PSHUFHW:
5339 ImmN = N->getOperand(N->getNumOperands()-1);
5340 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5343 case X86ISD::PSHUFLW:
5344 ImmN = N->getOperand(N->getNumOperands()-1);
5345 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5348 case X86ISD::PSHUFB: {
5350 SDValue MaskNode = N->getOperand(1);
5351 while (MaskNode->getOpcode() == ISD::BITCAST)
5352 MaskNode = MaskNode->getOperand(0);
5354 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5355 // If we have a build-vector, then things are easy.
5356 EVT VT = MaskNode.getValueType();
5357 assert(VT.isVector() &&
5358 "Can't produce a non-vector with a build_vector!");
5359 if (!VT.isInteger())
5362 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5364 SmallVector<uint64_t, 32> RawMask;
5365 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5366 SDValue Op = MaskNode->getOperand(i);
5367 if (Op->getOpcode() == ISD::UNDEF) {
5368 RawMask.push_back((uint64_t)SM_SentinelUndef);
5371 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5374 APInt MaskElement = CN->getAPIntValue();
5376 // We now have to decode the element which could be any integer size and
5377 // extract each byte of it.
5378 for (int j = 0; j < NumBytesPerElement; ++j) {
5379 // Note that this is x86 and so always little endian: the low byte is
5380 // the first byte of the mask.
5381 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5382 MaskElement = MaskElement.lshr(8);
5385 DecodePSHUFBMask(RawMask, Mask);
5389 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5393 SDValue Ptr = MaskLoad->getBasePtr();
5394 if (Ptr->getOpcode() == X86ISD::Wrapper)
5395 Ptr = Ptr->getOperand(0);
5397 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5398 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5401 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5402 // FIXME: Support AVX-512 here.
5403 Type *Ty = C->getType();
5404 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5405 Ty->getVectorNumElements() != 32))
5408 DecodePSHUFBMask(C, Mask);
5414 case X86ISD::VPERMI:
5415 ImmN = N->getOperand(N->getNumOperands()-1);
5416 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5420 case X86ISD::MOVSD: {
5421 // The index 0 always comes from the first element of the second source,
5422 // this is why MOVSS and MOVSD are used in the first place. The other
5423 // elements come from the other positions of the first source vector
5424 Mask.push_back(NumElems);
5425 for (unsigned i = 1; i != NumElems; ++i) {
5430 case X86ISD::VPERM2X128:
5431 ImmN = N->getOperand(N->getNumOperands()-1);
5432 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5433 if (Mask.empty()) return false;
5435 case X86ISD::MOVSLDUP:
5436 DecodeMOVSLDUPMask(VT, Mask);
5438 case X86ISD::MOVSHDUP:
5439 DecodeMOVSHDUPMask(VT, Mask);
5441 case X86ISD::MOVDDUP:
5442 case X86ISD::MOVLHPD:
5443 case X86ISD::MOVLPD:
5444 case X86ISD::MOVLPS:
5445 // Not yet implemented
5447 default: llvm_unreachable("unknown target shuffle node");
5450 // If we have a fake unary shuffle, the shuffle mask is spread across two
5451 // inputs that are actually the same node. Re-map the mask to always point
5452 // into the first input.
5455 if (M >= (int)Mask.size())
5461 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5462 /// element of the result of the vector shuffle.
5463 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5466 return SDValue(); // Limit search depth.
5468 SDValue V = SDValue(N, 0);
5469 EVT VT = V.getValueType();
5470 unsigned Opcode = V.getOpcode();
5472 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5473 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5474 int Elt = SV->getMaskElt(Index);
5477 return DAG.getUNDEF(VT.getVectorElementType());
5479 unsigned NumElems = VT.getVectorNumElements();
5480 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5481 : SV->getOperand(1);
5482 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5485 // Recurse into target specific vector shuffles to find scalars.
5486 if (isTargetShuffle(Opcode)) {
5487 MVT ShufVT = V.getSimpleValueType();
5488 unsigned NumElems = ShufVT.getVectorNumElements();
5489 SmallVector<int, 16> ShuffleMask;
5492 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5495 int Elt = ShuffleMask[Index];
5497 return DAG.getUNDEF(ShufVT.getVectorElementType());
5499 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5501 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5505 // Actual nodes that may contain scalar elements
5506 if (Opcode == ISD::BITCAST) {
5507 V = V.getOperand(0);
5508 EVT SrcVT = V.getValueType();
5509 unsigned NumElems = VT.getVectorNumElements();
5511 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5515 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5516 return (Index == 0) ? V.getOperand(0)
5517 : DAG.getUNDEF(VT.getVectorElementType());
5519 if (V.getOpcode() == ISD::BUILD_VECTOR)
5520 return V.getOperand(Index);
5525 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5526 /// shuffle operation which come from a consecutively from a zero. The
5527 /// search can start in two different directions, from left or right.
5528 /// We count undefs as zeros until PreferredNum is reached.
5529 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5530 unsigned NumElems, bool ZerosFromLeft,
5532 unsigned PreferredNum = -1U) {
5533 unsigned NumZeros = 0;
5534 for (unsigned i = 0; i != NumElems; ++i) {
5535 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5536 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5540 if (X86::isZeroNode(Elt))
5542 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5543 NumZeros = std::min(NumZeros + 1, PreferredNum);
5551 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5552 /// correspond consecutively to elements from one of the vector operands,
5553 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5555 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5556 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5557 unsigned NumElems, unsigned &OpNum) {
5558 bool SeenV1 = false;
5559 bool SeenV2 = false;
5561 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5562 int Idx = SVOp->getMaskElt(i);
5563 // Ignore undef indicies
5567 if (Idx < (int)NumElems)
5572 // Only accept consecutive elements from the same vector
5573 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5577 OpNum = SeenV1 ? 0 : 1;
5581 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5582 /// logical left shift of a vector.
5583 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5584 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5586 SVOp->getSimpleValueType(0).getVectorNumElements();
5587 unsigned NumZeros = getNumOfConsecutiveZeros(
5588 SVOp, NumElems, false /* check zeros from right */, DAG,
5589 SVOp->getMaskElt(0));
5595 // Considering the elements in the mask that are not consecutive zeros,
5596 // check if they consecutively come from only one of the source vectors.
5598 // V1 = {X, A, B, C} 0
5600 // vector_shuffle V1, V2 <1, 2, 3, X>
5602 if (!isShuffleMaskConsecutive(SVOp,
5603 0, // Mask Start Index
5604 NumElems-NumZeros, // Mask End Index(exclusive)
5605 NumZeros, // Where to start looking in the src vector
5606 NumElems, // Number of elements in vector
5607 OpSrc)) // Which source operand ?
5612 ShVal = SVOp->getOperand(OpSrc);
5616 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5617 /// logical left shift of a vector.
5618 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5619 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5621 SVOp->getSimpleValueType(0).getVectorNumElements();
5622 unsigned NumZeros = getNumOfConsecutiveZeros(
5623 SVOp, NumElems, true /* check zeros from left */, DAG,
5624 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5630 // Considering the elements in the mask that are not consecutive zeros,
5631 // check if they consecutively come from only one of the source vectors.
5633 // 0 { A, B, X, X } = V2
5635 // vector_shuffle V1, V2 <X, X, 4, 5>
5637 if (!isShuffleMaskConsecutive(SVOp,
5638 NumZeros, // Mask Start Index
5639 NumElems, // Mask End Index(exclusive)
5640 0, // Where to start looking in the src vector
5641 NumElems, // Number of elements in vector
5642 OpSrc)) // Which source operand ?
5647 ShVal = SVOp->getOperand(OpSrc);
5651 /// isVectorShift - Returns true if the shuffle can be implemented as a
5652 /// logical left or right shift of a vector.
5653 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5654 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5655 // Although the logic below support any bitwidth size, there are no
5656 // shift instructions which handle more than 128-bit vectors.
5657 if (!SVOp->getSimpleValueType(0).is128BitVector())
5660 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5661 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5667 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5669 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5670 unsigned NumNonZero, unsigned NumZero,
5672 const X86Subtarget* Subtarget,
5673 const TargetLowering &TLI) {
5680 for (unsigned i = 0; i < 16; ++i) {
5681 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5682 if (ThisIsNonZero && First) {
5684 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5686 V = DAG.getUNDEF(MVT::v8i16);
5691 SDValue ThisElt, LastElt;
5692 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5693 if (LastIsNonZero) {
5694 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5695 MVT::i16, Op.getOperand(i-1));
5697 if (ThisIsNonZero) {
5698 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5699 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5700 ThisElt, DAG.getConstant(8, MVT::i8));
5702 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5706 if (ThisElt.getNode())
5707 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5708 DAG.getIntPtrConstant(i/2));
5712 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5715 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5717 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5718 unsigned NumNonZero, unsigned NumZero,
5720 const X86Subtarget* Subtarget,
5721 const TargetLowering &TLI) {
5728 for (unsigned i = 0; i < 8; ++i) {
5729 bool isNonZero = (NonZeros & (1 << i)) != 0;
5733 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5735 V = DAG.getUNDEF(MVT::v8i16);
5738 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5739 MVT::v8i16, V, Op.getOperand(i),
5740 DAG.getIntPtrConstant(i));
5747 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5748 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5749 unsigned NonZeros, unsigned NumNonZero,
5750 unsigned NumZero, SelectionDAG &DAG,
5751 const X86Subtarget *Subtarget,
5752 const TargetLowering &TLI) {
5753 // We know there's at least one non-zero element
5754 unsigned FirstNonZeroIdx = 0;
5755 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5756 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5757 X86::isZeroNode(FirstNonZero)) {
5759 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5762 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5763 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5766 SDValue V = FirstNonZero.getOperand(0);
5767 MVT VVT = V.getSimpleValueType();
5768 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5771 unsigned FirstNonZeroDst =
5772 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5773 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5774 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5775 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5777 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5778 SDValue Elem = Op.getOperand(Idx);
5779 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5782 // TODO: What else can be here? Deal with it.
5783 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5786 // TODO: Some optimizations are still possible here
5787 // ex: Getting one element from a vector, and the rest from another.
5788 if (Elem.getOperand(0) != V)
5791 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5794 else if (IncorrectIdx == -1U) {
5798 // There was already one element with an incorrect index.
5799 // We can't optimize this case to an insertps.
5803 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5805 EVT VT = Op.getSimpleValueType();
5806 unsigned ElementMoveMask = 0;
5807 if (IncorrectIdx == -1U)
5808 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5810 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5812 SDValue InsertpsMask =
5813 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5814 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5820 /// getVShift - Return a vector logical shift node.
5822 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5823 unsigned NumBits, SelectionDAG &DAG,
5824 const TargetLowering &TLI, SDLoc dl) {
5825 assert(VT.is128BitVector() && "Unknown type for VShift");
5826 EVT ShVT = MVT::v2i64;
5827 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5828 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5829 return DAG.getNode(ISD::BITCAST, dl, VT,
5830 DAG.getNode(Opc, dl, ShVT, SrcOp,
5831 DAG.getConstant(NumBits,
5832 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5836 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5838 // Check if the scalar load can be widened into a vector load. And if
5839 // the address is "base + cst" see if the cst can be "absorbed" into
5840 // the shuffle mask.
5841 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5842 SDValue Ptr = LD->getBasePtr();
5843 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5845 EVT PVT = LD->getValueType(0);
5846 if (PVT != MVT::i32 && PVT != MVT::f32)
5851 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5852 FI = FINode->getIndex();
5854 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5855 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5856 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5857 Offset = Ptr.getConstantOperandVal(1);
5858 Ptr = Ptr.getOperand(0);
5863 // FIXME: 256-bit vector instructions don't require a strict alignment,
5864 // improve this code to support it better.
5865 unsigned RequiredAlign = VT.getSizeInBits()/8;
5866 SDValue Chain = LD->getChain();
5867 // Make sure the stack object alignment is at least 16 or 32.
5868 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5869 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5870 if (MFI->isFixedObjectIndex(FI)) {
5871 // Can't change the alignment. FIXME: It's possible to compute
5872 // the exact stack offset and reference FI + adjust offset instead.
5873 // If someone *really* cares about this. That's the way to implement it.
5876 MFI->setObjectAlignment(FI, RequiredAlign);
5880 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5881 // Ptr + (Offset & ~15).
5884 if ((Offset % RequiredAlign) & 3)
5886 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5888 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5889 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5891 int EltNo = (Offset - StartOffset) >> 2;
5892 unsigned NumElems = VT.getVectorNumElements();
5894 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5895 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5896 LD->getPointerInfo().getWithOffset(StartOffset),
5897 false, false, false, 0);
5899 SmallVector<int, 8> Mask;
5900 for (unsigned i = 0; i != NumElems; ++i)
5901 Mask.push_back(EltNo);
5903 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5909 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5910 /// vector of type 'VT', see if the elements can be replaced by a single large
5911 /// load which has the same value as a build_vector whose operands are 'elts'.
5913 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5915 /// FIXME: we'd also like to handle the case where the last elements are zero
5916 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5917 /// There's even a handy isZeroNode for that purpose.
5918 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5919 SDLoc &DL, SelectionDAG &DAG,
5920 bool isAfterLegalize) {
5921 EVT EltVT = VT.getVectorElementType();
5922 unsigned NumElems = Elts.size();
5924 LoadSDNode *LDBase = nullptr;
5925 unsigned LastLoadedElt = -1U;
5927 // For each element in the initializer, see if we've found a load or an undef.
5928 // If we don't find an initial load element, or later load elements are
5929 // non-consecutive, bail out.
5930 for (unsigned i = 0; i < NumElems; ++i) {
5931 SDValue Elt = Elts[i];
5933 if (!Elt.getNode() ||
5934 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5937 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5939 LDBase = cast<LoadSDNode>(Elt.getNode());
5943 if (Elt.getOpcode() == ISD::UNDEF)
5946 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5947 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5952 // If we have found an entire vector of loads and undefs, then return a large
5953 // load of the entire vector width starting at the base pointer. If we found
5954 // consecutive loads for the low half, generate a vzext_load node.
5955 if (LastLoadedElt == NumElems - 1) {
5957 if (isAfterLegalize &&
5958 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5961 SDValue NewLd = SDValue();
5963 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5964 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5965 LDBase->getPointerInfo(),
5966 LDBase->isVolatile(), LDBase->isNonTemporal(),
5967 LDBase->isInvariant(), 0);
5968 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5969 LDBase->getPointerInfo(),
5970 LDBase->isVolatile(), LDBase->isNonTemporal(),
5971 LDBase->isInvariant(), LDBase->getAlignment());
5973 if (LDBase->hasAnyUseOfValue(1)) {
5974 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5976 SDValue(NewLd.getNode(), 1));
5977 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5978 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5979 SDValue(NewLd.getNode(), 1));
5984 if (NumElems == 4 && LastLoadedElt == 1 &&
5985 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5986 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5987 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5989 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5990 LDBase->getPointerInfo(),
5991 LDBase->getAlignment(),
5992 false/*isVolatile*/, true/*ReadMem*/,
5995 // Make sure the newly-created LOAD is in the same position as LDBase in
5996 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5997 // update uses of LDBase's output chain to use the TokenFactor.
5998 if (LDBase->hasAnyUseOfValue(1)) {
5999 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6000 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6001 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6002 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6003 SDValue(ResNode.getNode(), 1));
6006 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6011 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6012 /// to generate a splat value for the following cases:
6013 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6014 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6015 /// a scalar load, or a constant.
6016 /// The VBROADCAST node is returned when a pattern is found,
6017 /// or SDValue() otherwise.
6018 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6019 SelectionDAG &DAG) {
6020 // VBROADCAST requires AVX.
6021 // TODO: Splats could be generated for non-AVX CPUs using SSE
6022 // instructions, but there's less potential gain for only 128-bit vectors.
6023 if (!Subtarget->hasAVX())
6026 MVT VT = Op.getSimpleValueType();
6029 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6030 "Unsupported vector type for broadcast.");
6035 switch (Op.getOpcode()) {
6037 // Unknown pattern found.
6040 case ISD::BUILD_VECTOR: {
6041 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6042 BitVector UndefElements;
6043 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6045 // We need a splat of a single value to use broadcast, and it doesn't
6046 // make any sense if the value is only in one element of the vector.
6047 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6051 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6052 Ld.getOpcode() == ISD::ConstantFP);
6054 // Make sure that all of the users of a non-constant load are from the
6055 // BUILD_VECTOR node.
6056 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6061 case ISD::VECTOR_SHUFFLE: {
6062 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6064 // Shuffles must have a splat mask where the first element is
6066 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6069 SDValue Sc = Op.getOperand(0);
6070 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6071 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6073 if (!Subtarget->hasInt256())
6076 // Use the register form of the broadcast instruction available on AVX2.
6077 if (VT.getSizeInBits() >= 256)
6078 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6079 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6082 Ld = Sc.getOperand(0);
6083 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6084 Ld.getOpcode() == ISD::ConstantFP);
6086 // The scalar_to_vector node and the suspected
6087 // load node must have exactly one user.
6088 // Constants may have multiple users.
6090 // AVX-512 has register version of the broadcast
6091 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6092 Ld.getValueType().getSizeInBits() >= 32;
6093 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6100 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6101 bool IsGE256 = (VT.getSizeInBits() >= 256);
6103 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6104 // instruction to save 8 or more bytes of constant pool data.
6105 // TODO: If multiple splats are generated to load the same constant,
6106 // it may be detrimental to overall size. There needs to be a way to detect
6107 // that condition to know if this is truly a size win.
6108 const Function *F = DAG.getMachineFunction().getFunction();
6109 bool OptForSize = F->getAttributes().
6110 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6112 // Handle broadcasting a single constant scalar from the constant pool
6114 // On Sandybridge (no AVX2), it is still better to load a constant vector
6115 // from the constant pool and not to broadcast it from a scalar.
6116 // But override that restriction when optimizing for size.
6117 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6118 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6119 EVT CVT = Ld.getValueType();
6120 assert(!CVT.isVector() && "Must not broadcast a vector type");
6122 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6123 // For size optimization, also splat v2f64 and v2i64, and for size opt
6124 // with AVX2, also splat i8 and i16.
6125 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6126 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6127 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6128 const Constant *C = nullptr;
6129 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6130 C = CI->getConstantIntValue();
6131 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6132 C = CF->getConstantFPValue();
6134 assert(C && "Invalid constant type");
6136 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6137 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6138 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6139 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6140 MachinePointerInfo::getConstantPool(),
6141 false, false, false, Alignment);
6143 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6147 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6149 // Handle AVX2 in-register broadcasts.
6150 if (!IsLoad && Subtarget->hasInt256() &&
6151 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6152 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6154 // The scalar source must be a normal load.
6158 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6159 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6161 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6162 // double since there is no vbroadcastsd xmm
6163 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6164 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6165 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6168 // Unsupported broadcast.
6172 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6173 /// underlying vector and index.
6175 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6177 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6179 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6180 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6183 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6185 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6187 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6188 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6191 // In this case the vector is the extract_subvector expression and the index
6192 // is 2, as specified by the shuffle.
6193 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6194 SDValue ShuffleVec = SVOp->getOperand(0);
6195 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6196 assert(ShuffleVecVT.getVectorElementType() ==
6197 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6199 int ShuffleIdx = SVOp->getMaskElt(Idx);
6200 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6201 ExtractedFromVec = ShuffleVec;
6207 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6208 MVT VT = Op.getSimpleValueType();
6210 // Skip if insert_vec_elt is not supported.
6211 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6212 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6216 unsigned NumElems = Op.getNumOperands();
6220 SmallVector<unsigned, 4> InsertIndices;
6221 SmallVector<int, 8> Mask(NumElems, -1);
6223 for (unsigned i = 0; i != NumElems; ++i) {
6224 unsigned Opc = Op.getOperand(i).getOpcode();
6226 if (Opc == ISD::UNDEF)
6229 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6230 // Quit if more than 1 elements need inserting.
6231 if (InsertIndices.size() > 1)
6234 InsertIndices.push_back(i);
6238 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6239 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6240 // Quit if non-constant index.
6241 if (!isa<ConstantSDNode>(ExtIdx))
6243 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6245 // Quit if extracted from vector of different type.
6246 if (ExtractedFromVec.getValueType() != VT)
6249 if (!VecIn1.getNode())
6250 VecIn1 = ExtractedFromVec;
6251 else if (VecIn1 != ExtractedFromVec) {
6252 if (!VecIn2.getNode())
6253 VecIn2 = ExtractedFromVec;
6254 else if (VecIn2 != ExtractedFromVec)
6255 // Quit if more than 2 vectors to shuffle
6259 if (ExtractedFromVec == VecIn1)
6261 else if (ExtractedFromVec == VecIn2)
6262 Mask[i] = Idx + NumElems;
6265 if (!VecIn1.getNode())
6268 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6269 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6270 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6271 unsigned Idx = InsertIndices[i];
6272 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6273 DAG.getIntPtrConstant(Idx));
6279 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6281 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6283 MVT VT = Op.getSimpleValueType();
6284 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6285 "Unexpected type in LowerBUILD_VECTORvXi1!");
6288 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6289 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6290 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6291 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6294 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6295 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6296 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6297 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6300 bool AllContants = true;
6301 uint64_t Immediate = 0;
6302 int NonConstIdx = -1;
6303 bool IsSplat = true;
6304 unsigned NumNonConsts = 0;
6305 unsigned NumConsts = 0;
6306 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6307 SDValue In = Op.getOperand(idx);
6308 if (In.getOpcode() == ISD::UNDEF)
6310 if (!isa<ConstantSDNode>(In)) {
6311 AllContants = false;
6317 if (cast<ConstantSDNode>(In)->getZExtValue())
6318 Immediate |= (1ULL << idx);
6320 if (In != Op.getOperand(0))
6325 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6326 DAG.getConstant(Immediate, MVT::i16));
6327 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6328 DAG.getIntPtrConstant(0));
6331 if (NumNonConsts == 1 && NonConstIdx != 0) {
6334 SDValue VecAsImm = DAG.getConstant(Immediate,
6335 MVT::getIntegerVT(VT.getSizeInBits()));
6336 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6339 DstVec = DAG.getUNDEF(VT);
6340 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6341 Op.getOperand(NonConstIdx),
6342 DAG.getIntPtrConstant(NonConstIdx));
6344 if (!IsSplat && (NonConstIdx != 0))
6345 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6346 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6349 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6350 DAG.getConstant(-1, SelectVT),
6351 DAG.getConstant(0, SelectVT));
6353 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6354 DAG.getConstant((Immediate | 1), SelectVT),
6355 DAG.getConstant(Immediate, SelectVT));
6356 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6359 /// \brief Return true if \p N implements a horizontal binop and return the
6360 /// operands for the horizontal binop into V0 and V1.
6362 /// This is a helper function of PerformBUILD_VECTORCombine.
6363 /// This function checks that the build_vector \p N in input implements a
6364 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6365 /// operation to match.
6366 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6367 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6368 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6371 /// This function only analyzes elements of \p N whose indices are
6372 /// in range [BaseIdx, LastIdx).
6373 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6375 unsigned BaseIdx, unsigned LastIdx,
6376 SDValue &V0, SDValue &V1) {
6377 EVT VT = N->getValueType(0);
6379 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6380 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6381 "Invalid Vector in input!");
6383 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6384 bool CanFold = true;
6385 unsigned ExpectedVExtractIdx = BaseIdx;
6386 unsigned NumElts = LastIdx - BaseIdx;
6387 V0 = DAG.getUNDEF(VT);
6388 V1 = DAG.getUNDEF(VT);
6390 // Check if N implements a horizontal binop.
6391 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6392 SDValue Op = N->getOperand(i + BaseIdx);
6395 if (Op->getOpcode() == ISD::UNDEF) {
6396 // Update the expected vector extract index.
6397 if (i * 2 == NumElts)
6398 ExpectedVExtractIdx = BaseIdx;
6399 ExpectedVExtractIdx += 2;
6403 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6408 SDValue Op0 = Op.getOperand(0);
6409 SDValue Op1 = Op.getOperand(1);
6411 // Try to match the following pattern:
6412 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6413 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6414 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6415 Op0.getOperand(0) == Op1.getOperand(0) &&
6416 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6417 isa<ConstantSDNode>(Op1.getOperand(1)));
6421 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6422 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6424 if (i * 2 < NumElts) {
6425 if (V0.getOpcode() == ISD::UNDEF)
6426 V0 = Op0.getOperand(0);
6428 if (V1.getOpcode() == ISD::UNDEF)
6429 V1 = Op0.getOperand(0);
6430 if (i * 2 == NumElts)
6431 ExpectedVExtractIdx = BaseIdx;
6434 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6435 if (I0 == ExpectedVExtractIdx)
6436 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6437 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6438 // Try to match the following dag sequence:
6439 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6440 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6444 ExpectedVExtractIdx += 2;
6450 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6451 /// a concat_vector.
6453 /// This is a helper function of PerformBUILD_VECTORCombine.
6454 /// This function expects two 256-bit vectors called V0 and V1.
6455 /// At first, each vector is split into two separate 128-bit vectors.
6456 /// Then, the resulting 128-bit vectors are used to implement two
6457 /// horizontal binary operations.
6459 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6461 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6462 /// the two new horizontal binop.
6463 /// When Mode is set, the first horizontal binop dag node would take as input
6464 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6465 /// horizontal binop dag node would take as input the lower 128-bit of V1
6466 /// and the upper 128-bit of V1.
6468 /// HADD V0_LO, V0_HI
6469 /// HADD V1_LO, V1_HI
6471 /// Otherwise, the first horizontal binop dag node takes as input the lower
6472 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6473 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6475 /// HADD V0_LO, V1_LO
6476 /// HADD V0_HI, V1_HI
6478 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6479 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6480 /// the upper 128-bits of the result.
6481 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6482 SDLoc DL, SelectionDAG &DAG,
6483 unsigned X86Opcode, bool Mode,
6484 bool isUndefLO, bool isUndefHI) {
6485 EVT VT = V0.getValueType();
6486 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6487 "Invalid nodes in input!");
6489 unsigned NumElts = VT.getVectorNumElements();
6490 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6491 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6492 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6493 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6494 EVT NewVT = V0_LO.getValueType();
6496 SDValue LO = DAG.getUNDEF(NewVT);
6497 SDValue HI = DAG.getUNDEF(NewVT);
6500 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6501 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6502 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6503 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6504 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6506 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6507 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6508 V1_LO->getOpcode() != ISD::UNDEF))
6509 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6511 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6512 V1_HI->getOpcode() != ISD::UNDEF))
6513 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6516 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6519 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6520 /// sequence of 'vadd + vsub + blendi'.
6521 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6522 const X86Subtarget *Subtarget) {
6524 EVT VT = BV->getValueType(0);
6525 unsigned NumElts = VT.getVectorNumElements();
6526 SDValue InVec0 = DAG.getUNDEF(VT);
6527 SDValue InVec1 = DAG.getUNDEF(VT);
6529 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6530 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6532 // Odd-numbered elements in the input build vector are obtained from
6533 // adding two integer/float elements.
6534 // Even-numbered elements in the input build vector are obtained from
6535 // subtracting two integer/float elements.
6536 unsigned ExpectedOpcode = ISD::FSUB;
6537 unsigned NextExpectedOpcode = ISD::FADD;
6538 bool AddFound = false;
6539 bool SubFound = false;
6541 for (unsigned i = 0, e = NumElts; i != e; i++) {
6542 SDValue Op = BV->getOperand(i);
6544 // Skip 'undef' values.
6545 unsigned Opcode = Op.getOpcode();
6546 if (Opcode == ISD::UNDEF) {
6547 std::swap(ExpectedOpcode, NextExpectedOpcode);
6551 // Early exit if we found an unexpected opcode.
6552 if (Opcode != ExpectedOpcode)
6555 SDValue Op0 = Op.getOperand(0);
6556 SDValue Op1 = Op.getOperand(1);
6558 // Try to match the following pattern:
6559 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6560 // Early exit if we cannot match that sequence.
6561 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6562 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6563 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6564 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6565 Op0.getOperand(1) != Op1.getOperand(1))
6568 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6572 // We found a valid add/sub node. Update the information accordingly.
6578 // Update InVec0 and InVec1.
6579 if (InVec0.getOpcode() == ISD::UNDEF)
6580 InVec0 = Op0.getOperand(0);
6581 if (InVec1.getOpcode() == ISD::UNDEF)
6582 InVec1 = Op1.getOperand(0);
6584 // Make sure that operands in input to each add/sub node always
6585 // come from a same pair of vectors.
6586 if (InVec0 != Op0.getOperand(0)) {
6587 if (ExpectedOpcode == ISD::FSUB)
6590 // FADD is commutable. Try to commute the operands
6591 // and then test again.
6592 std::swap(Op0, Op1);
6593 if (InVec0 != Op0.getOperand(0))
6597 if (InVec1 != Op1.getOperand(0))
6600 // Update the pair of expected opcodes.
6601 std::swap(ExpectedOpcode, NextExpectedOpcode);
6604 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6605 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6606 InVec1.getOpcode() != ISD::UNDEF)
6607 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6612 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6613 const X86Subtarget *Subtarget) {
6615 EVT VT = N->getValueType(0);
6616 unsigned NumElts = VT.getVectorNumElements();
6617 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6618 SDValue InVec0, InVec1;
6620 // Try to match an ADDSUB.
6621 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6622 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6623 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6624 if (Value.getNode())
6628 // Try to match horizontal ADD/SUB.
6629 unsigned NumUndefsLO = 0;
6630 unsigned NumUndefsHI = 0;
6631 unsigned Half = NumElts/2;
6633 // Count the number of UNDEF operands in the build_vector in input.
6634 for (unsigned i = 0, e = Half; i != e; ++i)
6635 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6638 for (unsigned i = Half, e = NumElts; i != e; ++i)
6639 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6642 // Early exit if this is either a build_vector of all UNDEFs or all the
6643 // operands but one are UNDEF.
6644 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6647 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6648 // Try to match an SSE3 float HADD/HSUB.
6649 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6650 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6652 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6653 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6654 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6655 // Try to match an SSSE3 integer HADD/HSUB.
6656 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6657 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6659 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6660 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6663 if (!Subtarget->hasAVX())
6666 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6667 // Try to match an AVX horizontal add/sub of packed single/double
6668 // precision floating point values from 256-bit vectors.
6669 SDValue InVec2, InVec3;
6670 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6671 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6672 ((InVec0.getOpcode() == ISD::UNDEF ||
6673 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6674 ((InVec1.getOpcode() == ISD::UNDEF ||
6675 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6676 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6678 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6679 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6680 ((InVec0.getOpcode() == ISD::UNDEF ||
6681 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6682 ((InVec1.getOpcode() == ISD::UNDEF ||
6683 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6684 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6685 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6686 // Try to match an AVX2 horizontal add/sub of signed integers.
6687 SDValue InVec2, InVec3;
6689 bool CanFold = true;
6691 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6692 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6693 ((InVec0.getOpcode() == ISD::UNDEF ||
6694 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6695 ((InVec1.getOpcode() == ISD::UNDEF ||
6696 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6697 X86Opcode = X86ISD::HADD;
6698 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6699 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6700 ((InVec0.getOpcode() == ISD::UNDEF ||
6701 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6702 ((InVec1.getOpcode() == ISD::UNDEF ||
6703 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6704 X86Opcode = X86ISD::HSUB;
6709 // Fold this build_vector into a single horizontal add/sub.
6710 // Do this only if the target has AVX2.
6711 if (Subtarget->hasAVX2())
6712 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6714 // Do not try to expand this build_vector into a pair of horizontal
6715 // add/sub if we can emit a pair of scalar add/sub.
6716 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6719 // Convert this build_vector into a pair of horizontal binop followed by
6721 bool isUndefLO = NumUndefsLO == Half;
6722 bool isUndefHI = NumUndefsHI == Half;
6723 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6724 isUndefLO, isUndefHI);
6728 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6729 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6731 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6732 X86Opcode = X86ISD::HADD;
6733 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6734 X86Opcode = X86ISD::HSUB;
6735 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6736 X86Opcode = X86ISD::FHADD;
6737 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6738 X86Opcode = X86ISD::FHSUB;
6742 // Don't try to expand this build_vector into a pair of horizontal add/sub
6743 // if we can simply emit a pair of scalar add/sub.
6744 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6747 // Convert this build_vector into two horizontal add/sub followed by
6749 bool isUndefLO = NumUndefsLO == Half;
6750 bool isUndefHI = NumUndefsHI == Half;
6751 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6752 isUndefLO, isUndefHI);
6759 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6762 MVT VT = Op.getSimpleValueType();
6763 MVT ExtVT = VT.getVectorElementType();
6764 unsigned NumElems = Op.getNumOperands();
6766 // Generate vectors for predicate vectors.
6767 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6768 return LowerBUILD_VECTORvXi1(Op, DAG);
6770 // Vectors containing all zeros can be matched by pxor and xorps later
6771 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6772 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6773 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6774 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6777 return getZeroVector(VT, Subtarget, DAG, dl);
6780 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6781 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6782 // vpcmpeqd on 256-bit vectors.
6783 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6784 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6787 if (!VT.is512BitVector())
6788 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6791 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6792 if (Broadcast.getNode())
6795 unsigned EVTBits = ExtVT.getSizeInBits();
6797 unsigned NumZero = 0;
6798 unsigned NumNonZero = 0;
6799 unsigned NonZeros = 0;
6800 bool IsAllConstants = true;
6801 SmallSet<SDValue, 8> Values;
6802 for (unsigned i = 0; i < NumElems; ++i) {
6803 SDValue Elt = Op.getOperand(i);
6804 if (Elt.getOpcode() == ISD::UNDEF)
6807 if (Elt.getOpcode() != ISD::Constant &&
6808 Elt.getOpcode() != ISD::ConstantFP)
6809 IsAllConstants = false;
6810 if (X86::isZeroNode(Elt))
6813 NonZeros |= (1 << i);
6818 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6819 if (NumNonZero == 0)
6820 return DAG.getUNDEF(VT);
6822 // Special case for single non-zero, non-undef, element.
6823 if (NumNonZero == 1) {
6824 unsigned Idx = countTrailingZeros(NonZeros);
6825 SDValue Item = Op.getOperand(Idx);
6827 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6828 // the value are obviously zero, truncate the value to i32 and do the
6829 // insertion that way. Only do this if the value is non-constant or if the
6830 // value is a constant being inserted into element 0. It is cheaper to do
6831 // a constant pool load than it is to do a movd + shuffle.
6832 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6833 (!IsAllConstants || Idx == 0)) {
6834 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6836 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6837 EVT VecVT = MVT::v4i32;
6838 unsigned VecElts = 4;
6840 // Truncate the value (which may itself be a constant) to i32, and
6841 // convert it to a vector with movd (S2V+shuffle to zero extend).
6842 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6843 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6845 // If using the new shuffle lowering, just directly insert this.
6846 if (ExperimentalVectorShuffleLowering)
6848 ISD::BITCAST, dl, VT,
6849 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6851 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6853 // Now we have our 32-bit value zero extended in the low element of
6854 // a vector. If Idx != 0, swizzle it into place.
6856 SmallVector<int, 4> Mask;
6857 Mask.push_back(Idx);
6858 for (unsigned i = 1; i != VecElts; ++i)
6860 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6863 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6867 // If we have a constant or non-constant insertion into the low element of
6868 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6869 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6870 // depending on what the source datatype is.
6873 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6875 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6876 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6877 if (VT.is256BitVector() || VT.is512BitVector()) {
6878 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6879 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6880 Item, DAG.getIntPtrConstant(0));
6882 assert(VT.is128BitVector() && "Expected an SSE value type!");
6883 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6884 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6885 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6888 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6889 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6890 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6891 if (VT.is256BitVector()) {
6892 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6893 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6895 assert(VT.is128BitVector() && "Expected an SSE value type!");
6896 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6898 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6902 // Is it a vector logical left shift?
6903 if (NumElems == 2 && Idx == 1 &&
6904 X86::isZeroNode(Op.getOperand(0)) &&
6905 !X86::isZeroNode(Op.getOperand(1))) {
6906 unsigned NumBits = VT.getSizeInBits();
6907 return getVShift(true, VT,
6908 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6909 VT, Op.getOperand(1)),
6910 NumBits/2, DAG, *this, dl);
6913 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6916 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6917 // is a non-constant being inserted into an element other than the low one,
6918 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6919 // movd/movss) to move this into the low element, then shuffle it into
6921 if (EVTBits == 32) {
6922 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6924 // If using the new shuffle lowering, just directly insert this.
6925 if (ExperimentalVectorShuffleLowering)
6926 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6928 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6929 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6930 SmallVector<int, 8> MaskVec;
6931 for (unsigned i = 0; i != NumElems; ++i)
6932 MaskVec.push_back(i == Idx ? 0 : 1);
6933 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6937 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6938 if (Values.size() == 1) {
6939 if (EVTBits == 32) {
6940 // Instead of a shuffle like this:
6941 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6942 // Check if it's possible to issue this instead.
6943 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6944 unsigned Idx = countTrailingZeros(NonZeros);
6945 SDValue Item = Op.getOperand(Idx);
6946 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6947 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6952 // A vector full of immediates; various special cases are already
6953 // handled, so this is best done with a single constant-pool load.
6957 // For AVX-length vectors, build the individual 128-bit pieces and use
6958 // shuffles to put them in place.
6959 if (VT.is256BitVector() || VT.is512BitVector()) {
6960 SmallVector<SDValue, 64> V;
6961 for (unsigned i = 0; i != NumElems; ++i)
6962 V.push_back(Op.getOperand(i));
6964 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6966 // Build both the lower and upper subvector.
6967 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6968 makeArrayRef(&V[0], NumElems/2));
6969 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6970 makeArrayRef(&V[NumElems / 2], NumElems/2));
6972 // Recreate the wider vector with the lower and upper part.
6973 if (VT.is256BitVector())
6974 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6975 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6978 // Let legalizer expand 2-wide build_vectors.
6979 if (EVTBits == 64) {
6980 if (NumNonZero == 1) {
6981 // One half is zero or undef.
6982 unsigned Idx = countTrailingZeros(NonZeros);
6983 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6984 Op.getOperand(Idx));
6985 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6990 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6991 if (EVTBits == 8 && NumElems == 16) {
6992 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6994 if (V.getNode()) return V;
6997 if (EVTBits == 16 && NumElems == 8) {
6998 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7000 if (V.getNode()) return V;
7003 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7004 if (EVTBits == 32 && NumElems == 4) {
7005 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
7006 NumZero, DAG, Subtarget, *this);
7011 // If element VT is == 32 bits, turn it into a number of shuffles.
7012 SmallVector<SDValue, 8> V(NumElems);
7013 if (NumElems == 4 && NumZero > 0) {
7014 for (unsigned i = 0; i < 4; ++i) {
7015 bool isZero = !(NonZeros & (1 << i));
7017 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7019 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7022 for (unsigned i = 0; i < 2; ++i) {
7023 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7026 V[i] = V[i*2]; // Must be a zero vector.
7029 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7032 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7035 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7040 bool Reverse1 = (NonZeros & 0x3) == 2;
7041 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7045 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7046 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7048 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7051 if (Values.size() > 1 && VT.is128BitVector()) {
7052 // Check for a build vector of consecutive loads.
7053 for (unsigned i = 0; i < NumElems; ++i)
7054 V[i] = Op.getOperand(i);
7056 // Check for elements which are consecutive loads.
7057 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7061 // Check for a build vector from mostly shuffle plus few inserting.
7062 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7066 // For SSE 4.1, use insertps to put the high elements into the low element.
7067 if (getSubtarget()->hasSSE41()) {
7069 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7070 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7072 Result = DAG.getUNDEF(VT);
7074 for (unsigned i = 1; i < NumElems; ++i) {
7075 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7076 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7077 Op.getOperand(i), DAG.getIntPtrConstant(i));
7082 // Otherwise, expand into a number of unpckl*, start by extending each of
7083 // our (non-undef) elements to the full vector width with the element in the
7084 // bottom slot of the vector (which generates no code for SSE).
7085 for (unsigned i = 0; i < NumElems; ++i) {
7086 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7087 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7089 V[i] = DAG.getUNDEF(VT);
7092 // Next, we iteratively mix elements, e.g. for v4f32:
7093 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7094 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7095 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7096 unsigned EltStride = NumElems >> 1;
7097 while (EltStride != 0) {
7098 for (unsigned i = 0; i < EltStride; ++i) {
7099 // If V[i+EltStride] is undef and this is the first round of mixing,
7100 // then it is safe to just drop this shuffle: V[i] is already in the
7101 // right place, the one element (since it's the first round) being
7102 // inserted as undef can be dropped. This isn't safe for successive
7103 // rounds because they will permute elements within both vectors.
7104 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7105 EltStride == NumElems/2)
7108 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7117 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7118 // to create 256-bit vectors from two other 128-bit ones.
7119 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7121 MVT ResVT = Op.getSimpleValueType();
7123 assert((ResVT.is256BitVector() ||
7124 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7126 SDValue V1 = Op.getOperand(0);
7127 SDValue V2 = Op.getOperand(1);
7128 unsigned NumElems = ResVT.getVectorNumElements();
7129 if(ResVT.is256BitVector())
7130 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7132 if (Op.getNumOperands() == 4) {
7133 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7134 ResVT.getVectorNumElements()/2);
7135 SDValue V3 = Op.getOperand(2);
7136 SDValue V4 = Op.getOperand(3);
7137 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7138 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7140 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7143 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7144 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7145 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7146 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7147 Op.getNumOperands() == 4)));
7149 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7150 // from two other 128-bit ones.
7152 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7153 return LowerAVXCONCAT_VECTORS(Op, DAG);
7157 //===----------------------------------------------------------------------===//
7158 // Vector shuffle lowering
7160 // This is an experimental code path for lowering vector shuffles on x86. It is
7161 // designed to handle arbitrary vector shuffles and blends, gracefully
7162 // degrading performance as necessary. It works hard to recognize idiomatic
7163 // shuffles and lower them to optimal instruction patterns without leaving
7164 // a framework that allows reasonably efficient handling of all vector shuffle
7166 //===----------------------------------------------------------------------===//
7168 /// \brief Tiny helper function to identify a no-op mask.
7170 /// This is a somewhat boring predicate function. It checks whether the mask
7171 /// array input, which is assumed to be a single-input shuffle mask of the kind
7172 /// used by the X86 shuffle instructions (not a fully general
7173 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7174 /// in-place shuffle are 'no-op's.
7175 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7176 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7177 if (Mask[i] != -1 && Mask[i] != i)
7182 /// \brief Helper function to classify a mask as a single-input mask.
7184 /// This isn't a generic single-input test because in the vector shuffle
7185 /// lowering we canonicalize single inputs to be the first input operand. This
7186 /// means we can more quickly test for a single input by only checking whether
7187 /// an input from the second operand exists. We also assume that the size of
7188 /// mask corresponds to the size of the input vectors which isn't true in the
7189 /// fully general case.
7190 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7192 if (M >= (int)Mask.size())
7197 /// \brief Test whether there are elements crossing 128-bit lanes in this
7200 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7201 /// and we routinely test for these.
7202 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7203 int LaneSize = 128 / VT.getScalarSizeInBits();
7204 int Size = Mask.size();
7205 for (int i = 0; i < Size; ++i)
7206 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7211 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7213 /// This checks a shuffle mask to see if it is performing the same
7214 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7215 /// that it is also not lane-crossing. It may however involve a blend from the
7216 /// same lane of a second vector.
7218 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7219 /// non-trivial to compute in the face of undef lanes. The representation is
7220 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7221 /// entries from both V1 and V2 inputs to the wider mask.
7223 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7224 SmallVectorImpl<int> &RepeatedMask) {
7225 int LaneSize = 128 / VT.getScalarSizeInBits();
7226 RepeatedMask.resize(LaneSize, -1);
7227 int Size = Mask.size();
7228 for (int i = 0; i < Size; ++i) {
7231 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7232 // This entry crosses lanes, so there is no way to model this shuffle.
7235 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7236 if (RepeatedMask[i % LaneSize] == -1)
7237 // This is the first non-undef entry in this slot of a 128-bit lane.
7238 RepeatedMask[i % LaneSize] =
7239 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7240 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7241 // Found a mismatch with the repeated mask.
7247 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7248 // 2013 will allow us to use it as a non-type template parameter.
7251 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7253 /// See its documentation for details.
7254 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7255 if (Mask.size() != Args.size())
7257 for (int i = 0, e = Mask.size(); i < e; ++i) {
7258 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7259 if (Mask[i] != -1 && Mask[i] != *Args[i])
7267 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7270 /// This is a fast way to test a shuffle mask against a fixed pattern:
7272 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7274 /// It returns true if the mask is exactly as wide as the argument list, and
7275 /// each element of the mask is either -1 (signifying undef) or the value given
7276 /// in the argument.
7277 static const VariadicFunction1<
7278 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7280 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7282 /// This helper function produces an 8-bit shuffle immediate corresponding to
7283 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7284 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7287 /// NB: We rely heavily on "undef" masks preserving the input lane.
7288 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7289 SelectionDAG &DAG) {
7290 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7291 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7292 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7293 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7294 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7297 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7298 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7299 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7300 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7301 return DAG.getConstant(Imm, MVT::i8);
7304 /// \brief Try to emit a blend instruction for a shuffle.
7306 /// This doesn't do any checks for the availability of instructions for blending
7307 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7308 /// be matched in the backend with the type given. What it does check for is
7309 /// that the shuffle mask is in fact a blend.
7310 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7311 SDValue V2, ArrayRef<int> Mask,
7312 const X86Subtarget *Subtarget,
7313 SelectionDAG &DAG) {
7315 unsigned BlendMask = 0;
7316 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7317 if (Mask[i] >= Size) {
7318 if (Mask[i] != i + Size)
7319 return SDValue(); // Shuffled V2 input!
7320 BlendMask |= 1u << i;
7323 if (Mask[i] >= 0 && Mask[i] != i)
7324 return SDValue(); // Shuffled V1 input!
7326 switch (VT.SimpleTy) {
7331 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7332 DAG.getConstant(BlendMask, MVT::i8));
7336 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7340 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7341 // that instruction.
7342 if (Subtarget->hasAVX2()) {
7343 // Scale the blend by the number of 32-bit dwords per element.
7344 int Scale = VT.getScalarSizeInBits() / 32;
7346 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7347 if (Mask[i] >= Size)
7348 for (int j = 0; j < Scale; ++j)
7349 BlendMask |= 1u << (i * Scale + j);
7351 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7352 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7353 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7354 return DAG.getNode(ISD::BITCAST, DL, VT,
7355 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7356 DAG.getConstant(BlendMask, MVT::i8)));
7360 // For integer shuffles we need to expand the mask and cast the inputs to
7361 // v8i16s prior to blending.
7362 int Scale = 8 / VT.getVectorNumElements();
7364 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7365 if (Mask[i] >= Size)
7366 for (int j = 0; j < Scale; ++j)
7367 BlendMask |= 1u << (i * Scale + j);
7369 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7370 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7371 return DAG.getNode(ISD::BITCAST, DL, VT,
7372 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7373 DAG.getConstant(BlendMask, MVT::i8)));
7377 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7378 SmallVector<int, 8> RepeatedMask;
7379 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7380 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7381 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7383 for (int i = 0; i < 8; ++i)
7384 if (RepeatedMask[i] >= 16)
7385 BlendMask |= 1u << i;
7386 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7387 DAG.getConstant(BlendMask, MVT::i8));
7392 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7393 // Scale the blend by the number of bytes per element.
7394 int Scale = VT.getScalarSizeInBits() / 8;
7395 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7397 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7398 // mix of LLVM's code generator and the x86 backend. We tell the code
7399 // generator that boolean values in the elements of an x86 vector register
7400 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7401 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7402 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7403 // of the element (the remaining are ignored) and 0 in that high bit would
7404 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7405 // the LLVM model for boolean values in vector elements gets the relevant
7406 // bit set, it is set backwards and over constrained relative to x86's
7408 SDValue VSELECTMask[32];
7409 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7410 for (int j = 0; j < Scale; ++j)
7411 VSELECTMask[Scale * i + j] =
7412 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7413 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7415 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7416 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7418 ISD::BITCAST, DL, VT,
7419 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7420 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7425 llvm_unreachable("Not a supported integer vector type!");
7429 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7430 /// unblended shuffles followed by an unshuffled blend.
7432 /// This matches the extremely common pattern for handling combined
7433 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7435 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7439 SelectionDAG &DAG) {
7440 // Shuffle the input elements into the desired positions in V1 and V2 and
7441 // blend them together.
7442 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7443 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7444 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7445 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7446 if (Mask[i] >= 0 && Mask[i] < Size) {
7447 V1Mask[i] = Mask[i];
7449 } else if (Mask[i] >= Size) {
7450 V2Mask[i] = Mask[i] - Size;
7451 BlendMask[i] = i + Size;
7454 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7455 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7456 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7459 /// \brief Try to lower a vector shuffle as a byte rotation.
7461 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7462 /// byte-rotation of the concatenation of two vectors. This routine will
7463 /// try to generically lower a vector shuffle through such an instruction. It
7464 /// does not check for the availability of PALIGNR-based lowerings, only the
7465 /// applicability of this strategy to the given mask. This matches shuffle
7466 /// vectors that look like:
7468 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7470 /// Essentially it concatenates V1 and V2, shifts right by some number of
7471 /// elements, and takes the low elements as the result. Note that while this is
7472 /// specified as a *right shift* because x86 is little-endian, it is a *left
7473 /// rotate* of the vector lanes.
7475 /// Note that this only handles 128-bit vector widths currently.
7476 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7479 SelectionDAG &DAG) {
7480 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7482 // We need to detect various ways of spelling a rotation:
7483 // [11, 12, 13, 14, 15, 0, 1, 2]
7484 // [-1, 12, 13, 14, -1, -1, 1, -1]
7485 // [-1, -1, -1, -1, -1, -1, 1, 2]
7486 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7487 // [-1, 4, 5, 6, -1, -1, 9, -1]
7488 // [-1, 4, 5, 6, -1, -1, -1, -1]
7491 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7494 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7496 // Based on the mod-Size value of this mask element determine where
7497 // a rotated vector would have started.
7498 int StartIdx = i - (Mask[i] % Size);
7500 // The identity rotation isn't interesting, stop.
7503 // If we found the tail of a vector the rotation must be the missing
7504 // front. If we found the head of a vector, it must be how much of the head.
7505 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7508 Rotation = CandidateRotation;
7509 else if (Rotation != CandidateRotation)
7510 // The rotations don't match, so we can't match this mask.
7513 // Compute which value this mask is pointing at.
7514 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7516 // Compute which of the two target values this index should be assigned to.
7517 // This reflects whether the high elements are remaining or the low elements
7519 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7521 // Either set up this value if we've not encountered it before, or check
7522 // that it remains consistent.
7525 else if (TargetV != MaskV)
7526 // This may be a rotation, but it pulls from the inputs in some
7527 // unsupported interleaving.
7531 // Check that we successfully analyzed the mask, and normalize the results.
7532 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7533 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7539 // Cast the inputs to v16i8 to match PALIGNR.
7540 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7541 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7543 assert(VT.getSizeInBits() == 128 &&
7544 "Rotate-based lowering only supports 128-bit lowering!");
7545 assert(Mask.size() <= 16 &&
7546 "Can shuffle at most 16 bytes in a 128-bit vector!");
7547 // The actual rotate instruction rotates bytes, so we need to scale the
7548 // rotation based on how many bytes are in the vector.
7549 int Scale = 16 / Mask.size();
7551 return DAG.getNode(ISD::BITCAST, DL, VT,
7552 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7553 DAG.getConstant(Rotation * Scale, MVT::i8)));
7556 /// \brief Compute whether each element of a shuffle is zeroable.
7558 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7559 /// Either it is an undef element in the shuffle mask, the element of the input
7560 /// referenced is undef, or the element of the input referenced is known to be
7561 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7562 /// as many lanes with this technique as possible to simplify the remaining
7564 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7565 SDValue V1, SDValue V2) {
7566 SmallBitVector Zeroable(Mask.size(), false);
7568 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7569 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7571 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7573 // Handle the easy cases.
7574 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7579 // If this is an index into a build_vector node, dig out the input value and
7581 SDValue V = M < Size ? V1 : V2;
7582 if (V.getOpcode() != ISD::BUILD_VECTOR)
7585 SDValue Input = V.getOperand(M % Size);
7586 // The UNDEF opcode check really should be dead code here, but not quite
7587 // worth asserting on (it isn't invalid, just unexpected).
7588 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7595 /// \brief Lower a vector shuffle as a zero or any extension.
7597 /// Given a specific number of elements, element bit width, and extension
7598 /// stride, produce either a zero or any extension based on the available
7599 /// features of the subtarget.
7600 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7601 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7602 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7603 assert(Scale > 1 && "Need a scale to extend.");
7604 int EltBits = VT.getSizeInBits() / NumElements;
7605 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7606 "Only 8, 16, and 32 bit elements can be extended.");
7607 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7609 // Found a valid zext mask! Try various lowering strategies based on the
7610 // input type and available ISA extensions.
7611 if (Subtarget->hasSSE41()) {
7612 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7613 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7614 NumElements / Scale);
7615 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7616 return DAG.getNode(ISD::BITCAST, DL, VT,
7617 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7620 // For any extends we can cheat for larger element sizes and use shuffle
7621 // instructions that can fold with a load and/or copy.
7622 if (AnyExt && EltBits == 32) {
7623 int PSHUFDMask[4] = {0, -1, 1, -1};
7625 ISD::BITCAST, DL, VT,
7626 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7627 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7628 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7630 if (AnyExt && EltBits == 16 && Scale > 2) {
7631 int PSHUFDMask[4] = {0, -1, 0, -1};
7632 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7633 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7634 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7635 int PSHUFHWMask[4] = {1, -1, -1, -1};
7637 ISD::BITCAST, DL, VT,
7638 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7639 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7640 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7643 // If this would require more than 2 unpack instructions to expand, use
7644 // pshufb when available. We can only use more than 2 unpack instructions
7645 // when zero extending i8 elements which also makes it easier to use pshufb.
7646 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7647 assert(NumElements == 16 && "Unexpected byte vector width!");
7648 SDValue PSHUFBMask[16];
7649 for (int i = 0; i < 16; ++i)
7651 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7652 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7653 return DAG.getNode(ISD::BITCAST, DL, VT,
7654 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7655 DAG.getNode(ISD::BUILD_VECTOR, DL,
7656 MVT::v16i8, PSHUFBMask)));
7659 // Otherwise emit a sequence of unpacks.
7661 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7662 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7663 : getZeroVector(InputVT, Subtarget, DAG, DL);
7664 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7665 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7669 } while (Scale > 1);
7670 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7673 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7675 /// This routine will try to do everything in its power to cleverly lower
7676 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7677 /// check for the profitability of this lowering, it tries to aggressively
7678 /// match this pattern. It will use all of the micro-architectural details it
7679 /// can to emit an efficient lowering. It handles both blends with all-zero
7680 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7681 /// masking out later).
7683 /// The reason we have dedicated lowering for zext-style shuffles is that they
7684 /// are both incredibly common and often quite performance sensitive.
7685 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7686 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7687 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7688 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7690 int Bits = VT.getSizeInBits();
7691 int NumElements = Mask.size();
7693 // Define a helper function to check a particular ext-scale and lower to it if
7695 auto Lower = [&](int Scale) -> SDValue {
7698 for (int i = 0; i < NumElements; ++i) {
7700 continue; // Valid anywhere but doesn't tell us anything.
7701 if (i % Scale != 0) {
7702 // Each of the extend elements needs to be zeroable.
7706 // We no lorger are in the anyext case.
7711 // Each of the base elements needs to be consecutive indices into the
7712 // same input vector.
7713 SDValue V = Mask[i] < NumElements ? V1 : V2;
7716 else if (InputV != V)
7717 return SDValue(); // Flip-flopping inputs.
7719 if (Mask[i] % NumElements != i / Scale)
7720 return SDValue(); // Non-consecutive strided elemenst.
7723 // If we fail to find an input, we have a zero-shuffle which should always
7724 // have already been handled.
7725 // FIXME: Maybe handle this here in case during blending we end up with one?
7729 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7730 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7733 // The widest scale possible for extending is to a 64-bit integer.
7734 assert(Bits % 64 == 0 &&
7735 "The number of bits in a vector must be divisible by 64 on x86!");
7736 int NumExtElements = Bits / 64;
7738 // Each iteration, try extending the elements half as much, but into twice as
7740 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7741 assert(NumElements % NumExtElements == 0 &&
7742 "The input vector size must be divisble by the extended size.");
7743 if (SDValue V = Lower(NumElements / NumExtElements))
7747 // No viable ext lowering found.
7751 /// \brief Try to get a scalar value for a specific element of a vector.
7753 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7754 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7755 SelectionDAG &DAG) {
7756 MVT VT = V.getSimpleValueType();
7757 MVT EltVT = VT.getVectorElementType();
7758 while (V.getOpcode() == ISD::BITCAST)
7759 V = V.getOperand(0);
7760 // If the bitcasts shift the element size, we can't extract an equivalent
7762 MVT NewVT = V.getSimpleValueType();
7763 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7766 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7767 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7768 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7773 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7775 /// This is particularly important because the set of instructions varies
7776 /// significantly based on whether the operand is a load or not.
7777 static bool isShuffleFoldableLoad(SDValue V) {
7778 while (V.getOpcode() == ISD::BITCAST)
7779 V = V.getOperand(0);
7781 return ISD::isNON_EXTLoad(V.getNode());
7784 /// \brief Try to lower insertion of a single element into a zero vector.
7786 /// This is a common pattern that we have especially efficient patterns to lower
7787 /// across all subtarget feature sets.
7788 static SDValue lowerVectorShuffleAsElementInsertion(
7789 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7790 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7791 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7793 MVT EltVT = VT.getVectorElementType();
7795 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7796 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7798 bool IsV1Zeroable = true;
7799 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7800 if (i != V2Index && !Zeroable[i]) {
7801 IsV1Zeroable = false;
7805 // Check for a single input from a SCALAR_TO_VECTOR node.
7806 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7807 // all the smarts here sunk into that routine. However, the current
7808 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7809 // vector shuffle lowering is dead.
7810 if (SDValue V2S = getScalarValueForVectorElement(
7811 V2, Mask[V2Index] - Mask.size(), DAG)) {
7812 // We need to zext the scalar if it is smaller than an i32.
7813 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7814 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7815 // Using zext to expand a narrow element won't work for non-zero
7820 // Zero-extend directly to i32.
7822 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7824 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7825 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7826 EltVT == MVT::i16) {
7827 // Either not inserting from the low element of the input or the input
7828 // element size is too small to use VZEXT_MOVL to clear the high bits.
7832 if (!IsV1Zeroable) {
7833 // If V1 can't be treated as a zero vector we have fewer options to lower
7834 // this. We can't support integer vectors or non-zero targets cheaply, and
7835 // the V1 elements can't be permuted in any way.
7836 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7837 if (!VT.isFloatingPoint() || V2Index != 0)
7839 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7840 V1Mask[V2Index] = -1;
7841 if (!isNoopShuffleMask(V1Mask))
7843 // This is essentially a special case blend operation, but if we have
7844 // general purpose blend operations, they are always faster. Bail and let
7845 // the rest of the lowering handle these as blends.
7846 if (Subtarget->hasSSE41())
7849 // Otherwise, use MOVSD or MOVSS.
7850 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7851 "Only two types of floating point element types to handle!");
7852 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7856 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7858 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7861 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7862 // the desired position. Otherwise it is more efficient to do a vector
7863 // shift left. We know that we can do a vector shift left because all
7864 // the inputs are zero.
7865 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7866 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7867 V2Shuffle[V2Index] = 0;
7868 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7870 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7872 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7874 V2Index * EltVT.getSizeInBits(),
7875 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7876 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7882 /// \brief Try to lower broadcast of a single element.
7884 /// For convenience, this code also bundles all of the subtarget feature set
7885 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7886 /// a convenient way to factor it out.
7887 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7889 const X86Subtarget *Subtarget,
7890 SelectionDAG &DAG) {
7891 if (!Subtarget->hasAVX())
7893 if (VT.isInteger() && !Subtarget->hasAVX2())
7896 // Check that the mask is a broadcast.
7897 int BroadcastIdx = -1;
7899 if (M >= 0 && BroadcastIdx == -1)
7901 else if (M >= 0 && M != BroadcastIdx)
7904 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7905 "a sorted mask where the broadcast "
7908 // Go up the chain of (vector) values to try and find a scalar load that
7909 // we can combine with the broadcast.
7911 switch (V.getOpcode()) {
7912 case ISD::CONCAT_VECTORS: {
7913 int OperandSize = Mask.size() / V.getNumOperands();
7914 V = V.getOperand(BroadcastIdx / OperandSize);
7915 BroadcastIdx %= OperandSize;
7919 case ISD::INSERT_SUBVECTOR: {
7920 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7921 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7925 int BeginIdx = (int)ConstantIdx->getZExtValue();
7927 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7928 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7929 BroadcastIdx -= BeginIdx;
7940 // Check if this is a broadcast of a scalar. We special case lowering
7941 // for scalars so that we can more effectively fold with loads.
7942 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7943 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7944 V = V.getOperand(BroadcastIdx);
7946 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
7948 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7950 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7951 // We can't broadcast from a vector register w/o AVX2, and we can only
7952 // broadcast from the zero-element of a vector register.
7956 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7959 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7961 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7962 /// support for floating point shuffles but not integer shuffles. These
7963 /// instructions will incur a domain crossing penalty on some chips though so
7964 /// it is better to avoid lowering through this for integer vectors where
7966 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7967 const X86Subtarget *Subtarget,
7968 SelectionDAG &DAG) {
7970 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7971 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7972 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7973 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7974 ArrayRef<int> Mask = SVOp->getMask();
7975 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7977 if (isSingleInputShuffleMask(Mask)) {
7978 // Straight shuffle of a single input vector. Simulate this by using the
7979 // single input as both of the "inputs" to this instruction..
7980 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7982 if (Subtarget->hasAVX()) {
7983 // If we have AVX, we can use VPERMILPS which will allow folding a load
7984 // into the shuffle.
7985 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7986 DAG.getConstant(SHUFPDMask, MVT::i8));
7989 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7990 DAG.getConstant(SHUFPDMask, MVT::i8));
7992 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7993 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7995 // Use dedicated unpack instructions for masks that match their pattern.
7996 if (isShuffleEquivalent(Mask, 0, 2))
7997 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7998 if (isShuffleEquivalent(Mask, 1, 3))
7999 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8001 // If we have a single input, insert that into V1 if we can do so cheaply.
8002 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8003 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8004 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8006 // Try inverting the insertion since for v2 masks it is easy to do and we
8007 // can't reliably sort the mask one way or the other.
8008 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8009 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8010 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8011 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8015 // Try to use one of the special instruction patterns to handle two common
8016 // blend patterns if a zero-blend above didn't work.
8017 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8018 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8019 // We can either use a special instruction to load over the low double or
8020 // to move just the low double.
8022 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8024 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8026 if (Subtarget->hasSSE41())
8027 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8031 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8032 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8033 DAG.getConstant(SHUFPDMask, MVT::i8));
8036 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8038 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8039 /// the integer unit to minimize domain crossing penalties. However, for blends
8040 /// it falls back to the floating point shuffle operation with appropriate bit
8042 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8043 const X86Subtarget *Subtarget,
8044 SelectionDAG &DAG) {
8046 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8047 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8048 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8049 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8050 ArrayRef<int> Mask = SVOp->getMask();
8051 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8053 if (isSingleInputShuffleMask(Mask)) {
8054 // Check for being able to broadcast a single element.
8055 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8056 Mask, Subtarget, DAG))
8059 // Straight shuffle of a single input vector. For everything from SSE2
8060 // onward this has a single fast instruction with no scary immediates.
8061 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8062 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8063 int WidenedMask[4] = {
8064 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8065 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8067 ISD::BITCAST, DL, MVT::v2i64,
8068 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8069 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8072 // If we have a single input from V2 insert that into V1 if we can do so
8074 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8075 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8076 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8078 // Try inverting the insertion since for v2 masks it is easy to do and we
8079 // can't reliably sort the mask one way or the other.
8080 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8081 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8082 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8083 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8087 // Use dedicated unpack instructions for masks that match their pattern.
8088 if (isShuffleEquivalent(Mask, 0, 2))
8089 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8090 if (isShuffleEquivalent(Mask, 1, 3))
8091 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8093 if (Subtarget->hasSSE41())
8094 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8098 // Try to use rotation instructions if available.
8099 if (Subtarget->hasSSSE3())
8100 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8101 DL, MVT::v2i64, V1, V2, Mask, DAG))
8104 // We implement this with SHUFPD which is pretty lame because it will likely
8105 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8106 // However, all the alternatives are still more cycles and newer chips don't
8107 // have this problem. It would be really nice if x86 had better shuffles here.
8108 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8109 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8110 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8111 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8114 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8116 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8117 /// It makes no assumptions about whether this is the *best* lowering, it simply
8119 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8120 ArrayRef<int> Mask, SDValue V1,
8121 SDValue V2, SelectionDAG &DAG) {
8122 SDValue LowV = V1, HighV = V2;
8123 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8126 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8128 if (NumV2Elements == 1) {
8130 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8133 // Compute the index adjacent to V2Index and in the same half by toggling
8135 int V2AdjIndex = V2Index ^ 1;
8137 if (Mask[V2AdjIndex] == -1) {
8138 // Handles all the cases where we have a single V2 element and an undef.
8139 // This will only ever happen in the high lanes because we commute the
8140 // vector otherwise.
8142 std::swap(LowV, HighV);
8143 NewMask[V2Index] -= 4;
8145 // Handle the case where the V2 element ends up adjacent to a V1 element.
8146 // To make this work, blend them together as the first step.
8147 int V1Index = V2AdjIndex;
8148 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8149 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8150 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8152 // Now proceed to reconstruct the final blend as we have the necessary
8153 // high or low half formed.
8160 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8161 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8163 } else if (NumV2Elements == 2) {
8164 if (Mask[0] < 4 && Mask[1] < 4) {
8165 // Handle the easy case where we have V1 in the low lanes and V2 in the
8169 } else if (Mask[2] < 4 && Mask[3] < 4) {
8170 // We also handle the reversed case because this utility may get called
8171 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8172 // arrange things in the right direction.
8178 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8179 // trying to place elements directly, just blend them and set up the final
8180 // shuffle to place them.
8182 // The first two blend mask elements are for V1, the second two are for
8184 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8185 Mask[2] < 4 ? Mask[2] : Mask[3],
8186 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8187 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8188 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8189 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8191 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8194 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8195 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8196 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8197 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8200 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8201 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8204 /// \brief Lower 4-lane 32-bit floating point shuffles.
8206 /// Uses instructions exclusively from the floating point unit to minimize
8207 /// domain crossing penalties, as these are sufficient to implement all v4f32
8209 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8210 const X86Subtarget *Subtarget,
8211 SelectionDAG &DAG) {
8213 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8214 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8215 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8216 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8217 ArrayRef<int> Mask = SVOp->getMask();
8218 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8221 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8223 if (NumV2Elements == 0) {
8224 // Check for being able to broadcast a single element.
8225 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8226 Mask, Subtarget, DAG))
8229 if (Subtarget->hasAVX()) {
8230 // If we have AVX, we can use VPERMILPS which will allow folding a load
8231 // into the shuffle.
8232 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8233 getV4X86ShuffleImm8ForMask(Mask, DAG));
8236 // Otherwise, use a straight shuffle of a single input vector. We pass the
8237 // input vector to both operands to simulate this with a SHUFPS.
8238 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8239 getV4X86ShuffleImm8ForMask(Mask, DAG));
8242 // Use dedicated unpack instructions for masks that match their pattern.
8243 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8244 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8245 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8246 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8248 // There are special ways we can lower some single-element blends. However, we
8249 // have custom ways we can lower more complex single-element blends below that
8250 // we defer to if both this and BLENDPS fail to match, so restrict this to
8251 // when the V2 input is targeting element 0 of the mask -- that is the fast
8253 if (NumV2Elements == 1 && Mask[0] >= 4)
8254 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8255 Mask, Subtarget, DAG))
8258 if (Subtarget->hasSSE41())
8259 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8263 // Check for whether we can use INSERTPS to perform the blend. We only use
8264 // INSERTPS when the V1 elements are already in the correct locations
8265 // because otherwise we can just always use two SHUFPS instructions which
8266 // are much smaller to encode than a SHUFPS and an INSERTPS.
8267 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8269 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8272 // When using INSERTPS we can zero any lane of the destination. Collect
8273 // the zero inputs into a mask and drop them from the lanes of V1 which
8274 // actually need to be present as inputs to the INSERTPS.
8275 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8277 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8278 bool InsertNeedsShuffle = false;
8280 for (int i = 0; i < 4; ++i)
8284 } else if (Mask[i] != i) {
8285 InsertNeedsShuffle = true;
8290 // We don't want to use INSERTPS or other insertion techniques if it will
8291 // require shuffling anyways.
8292 if (!InsertNeedsShuffle) {
8293 // If all of V1 is zeroable, replace it with undef.
8294 if ((ZMask | 1 << V2Index) == 0xF)
8295 V1 = DAG.getUNDEF(MVT::v4f32);
8297 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8298 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8300 // Insert the V2 element into the desired position.
8301 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8302 DAG.getConstant(InsertPSMask, MVT::i8));
8306 // Otherwise fall back to a SHUFPS lowering strategy.
8307 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8310 /// \brief Lower 4-lane i32 vector shuffles.
8312 /// We try to handle these with integer-domain shuffles where we can, but for
8313 /// blends we use the floating point domain blend instructions.
8314 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8315 const X86Subtarget *Subtarget,
8316 SelectionDAG &DAG) {
8318 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8319 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8320 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8321 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8322 ArrayRef<int> Mask = SVOp->getMask();
8323 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8325 // Whenever we can lower this as a zext, that instruction is strictly faster
8326 // than any alternative. It also allows us to fold memory operands into the
8327 // shuffle in many cases.
8328 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8329 Mask, Subtarget, DAG))
8333 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8335 if (NumV2Elements == 0) {
8336 // Check for being able to broadcast a single element.
8337 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8338 Mask, Subtarget, DAG))
8341 // Straight shuffle of a single input vector. For everything from SSE2
8342 // onward this has a single fast instruction with no scary immediates.
8343 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8344 // but we aren't actually going to use the UNPCK instruction because doing
8345 // so prevents folding a load into this instruction or making a copy.
8346 const int UnpackLoMask[] = {0, 0, 1, 1};
8347 const int UnpackHiMask[] = {2, 2, 3, 3};
8348 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8349 Mask = UnpackLoMask;
8350 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8351 Mask = UnpackHiMask;
8353 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8354 getV4X86ShuffleImm8ForMask(Mask, DAG));
8357 // There are special ways we can lower some single-element blends.
8358 if (NumV2Elements == 1)
8359 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8360 Mask, Subtarget, DAG))
8363 // Use dedicated unpack instructions for masks that match their pattern.
8364 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8365 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8366 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8367 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8369 if (Subtarget->hasSSE41())
8370 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8374 // Try to use rotation instructions if available.
8375 if (Subtarget->hasSSSE3())
8376 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8377 DL, MVT::v4i32, V1, V2, Mask, DAG))
8380 // We implement this with SHUFPS because it can blend from two vectors.
8381 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8382 // up the inputs, bypassing domain shift penalties that we would encur if we
8383 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8385 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8386 DAG.getVectorShuffle(
8388 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8389 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8392 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8393 /// shuffle lowering, and the most complex part.
8395 /// The lowering strategy is to try to form pairs of input lanes which are
8396 /// targeted at the same half of the final vector, and then use a dword shuffle
8397 /// to place them onto the right half, and finally unpack the paired lanes into
8398 /// their final position.
8400 /// The exact breakdown of how to form these dword pairs and align them on the
8401 /// correct sides is really tricky. See the comments within the function for
8402 /// more of the details.
8403 static SDValue lowerV8I16SingleInputVectorShuffle(
8404 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8405 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8406 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8407 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8408 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8410 SmallVector<int, 4> LoInputs;
8411 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8412 [](int M) { return M >= 0; });
8413 std::sort(LoInputs.begin(), LoInputs.end());
8414 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8415 SmallVector<int, 4> HiInputs;
8416 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8417 [](int M) { return M >= 0; });
8418 std::sort(HiInputs.begin(), HiInputs.end());
8419 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8421 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8422 int NumHToL = LoInputs.size() - NumLToL;
8424 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8425 int NumHToH = HiInputs.size() - NumLToH;
8426 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8427 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8428 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8429 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8431 // Check for being able to broadcast a single element.
8432 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8433 Mask, Subtarget, DAG))
8436 // Use dedicated unpack instructions for masks that match their pattern.
8437 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8438 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8439 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8440 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8442 // Try to use rotation instructions if available.
8443 if (Subtarget->hasSSSE3())
8444 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8445 DL, MVT::v8i16, V, V, Mask, DAG))
8448 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8449 // such inputs we can swap two of the dwords across the half mark and end up
8450 // with <=2 inputs to each half in each half. Once there, we can fall through
8451 // to the generic code below. For example:
8453 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8454 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8456 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8457 // and an existing 2-into-2 on the other half. In this case we may have to
8458 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8459 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8460 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8461 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8462 // half than the one we target for fixing) will be fixed when we re-enter this
8463 // path. We will also combine away any sequence of PSHUFD instructions that
8464 // result into a single instruction. Here is an example of the tricky case:
8466 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8467 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8469 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8471 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8472 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8474 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8475 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8477 // The result is fine to be handled by the generic logic.
8478 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8479 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8480 int AOffset, int BOffset) {
8481 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8482 "Must call this with A having 3 or 1 inputs from the A half.");
8483 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8484 "Must call this with B having 1 or 3 inputs from the B half.");
8485 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8486 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8488 // Compute the index of dword with only one word among the three inputs in
8489 // a half by taking the sum of the half with three inputs and subtracting
8490 // the sum of the actual three inputs. The difference is the remaining
8493 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8494 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8495 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8496 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8497 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8498 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8499 int TripleNonInputIdx =
8500 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8501 TripleDWord = TripleNonInputIdx / 2;
8503 // We use xor with one to compute the adjacent DWord to whichever one the
8505 OneInputDWord = (OneInput / 2) ^ 1;
8507 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8508 // and BToA inputs. If there is also such a problem with the BToB and AToB
8509 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8510 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8511 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8512 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8513 // Compute how many inputs will be flipped by swapping these DWords. We
8515 // to balance this to ensure we don't form a 3-1 shuffle in the other
8517 int NumFlippedAToBInputs =
8518 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8519 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8520 int NumFlippedBToBInputs =
8521 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8522 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8523 if ((NumFlippedAToBInputs == 1 &&
8524 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8525 (NumFlippedBToBInputs == 1 &&
8526 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8527 // We choose whether to fix the A half or B half based on whether that
8528 // half has zero flipped inputs. At zero, we may not be able to fix it
8529 // with that half. We also bias towards fixing the B half because that
8530 // will more commonly be the high half, and we have to bias one way.
8531 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8532 ArrayRef<int> Inputs) {
8533 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8534 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8535 PinnedIdx ^ 1) != Inputs.end();
8536 // Determine whether the free index is in the flipped dword or the
8537 // unflipped dword based on where the pinned index is. We use this bit
8538 // in an xor to conditionally select the adjacent dword.
8539 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8540 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8541 FixFreeIdx) != Inputs.end();
8542 if (IsFixIdxInput == IsFixFreeIdxInput)
8544 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8545 FixFreeIdx) != Inputs.end();
8546 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8547 "We need to be changing the number of flipped inputs!");
8548 int PSHUFHalfMask[] = {0, 1, 2, 3};
8549 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8550 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8552 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8555 if (M != -1 && M == FixIdx)
8557 else if (M != -1 && M == FixFreeIdx)
8560 if (NumFlippedBToBInputs != 0) {
8562 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8563 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8565 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8567 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8568 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8573 int PSHUFDMask[] = {0, 1, 2, 3};
8574 PSHUFDMask[ADWord] = BDWord;
8575 PSHUFDMask[BDWord] = ADWord;
8576 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8577 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8578 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8579 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8581 // Adjust the mask to match the new locations of A and B.
8583 if (M != -1 && M/2 == ADWord)
8584 M = 2 * BDWord + M % 2;
8585 else if (M != -1 && M/2 == BDWord)
8586 M = 2 * ADWord + M % 2;
8588 // Recurse back into this routine to re-compute state now that this isn't
8589 // a 3 and 1 problem.
8590 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8593 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8594 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8595 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8596 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8598 // At this point there are at most two inputs to the low and high halves from
8599 // each half. That means the inputs can always be grouped into dwords and
8600 // those dwords can then be moved to the correct half with a dword shuffle.
8601 // We use at most one low and one high word shuffle to collect these paired
8602 // inputs into dwords, and finally a dword shuffle to place them.
8603 int PSHUFLMask[4] = {-1, -1, -1, -1};
8604 int PSHUFHMask[4] = {-1, -1, -1, -1};
8605 int PSHUFDMask[4] = {-1, -1, -1, -1};
8607 // First fix the masks for all the inputs that are staying in their
8608 // original halves. This will then dictate the targets of the cross-half
8610 auto fixInPlaceInputs =
8611 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8612 MutableArrayRef<int> SourceHalfMask,
8613 MutableArrayRef<int> HalfMask, int HalfOffset) {
8614 if (InPlaceInputs.empty())
8616 if (InPlaceInputs.size() == 1) {
8617 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8618 InPlaceInputs[0] - HalfOffset;
8619 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8622 if (IncomingInputs.empty()) {
8623 // Just fix all of the in place inputs.
8624 for (int Input : InPlaceInputs) {
8625 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8626 PSHUFDMask[Input / 2] = Input / 2;
8631 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8632 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8633 InPlaceInputs[0] - HalfOffset;
8634 // Put the second input next to the first so that they are packed into
8635 // a dword. We find the adjacent index by toggling the low bit.
8636 int AdjIndex = InPlaceInputs[0] ^ 1;
8637 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8638 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8639 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8641 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8642 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8644 // Now gather the cross-half inputs and place them into a free dword of
8645 // their target half.
8646 // FIXME: This operation could almost certainly be simplified dramatically to
8647 // look more like the 3-1 fixing operation.
8648 auto moveInputsToRightHalf = [&PSHUFDMask](
8649 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8650 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8651 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8653 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8654 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8656 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8658 int LowWord = Word & ~1;
8659 int HighWord = Word | 1;
8660 return isWordClobbered(SourceHalfMask, LowWord) ||
8661 isWordClobbered(SourceHalfMask, HighWord);
8664 if (IncomingInputs.empty())
8667 if (ExistingInputs.empty()) {
8668 // Map any dwords with inputs from them into the right half.
8669 for (int Input : IncomingInputs) {
8670 // If the source half mask maps over the inputs, turn those into
8671 // swaps and use the swapped lane.
8672 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8673 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8674 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8675 Input - SourceOffset;
8676 // We have to swap the uses in our half mask in one sweep.
8677 for (int &M : HalfMask)
8678 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8680 else if (M == Input)
8681 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8683 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8684 Input - SourceOffset &&
8685 "Previous placement doesn't match!");
8687 // Note that this correctly re-maps both when we do a swap and when
8688 // we observe the other side of the swap above. We rely on that to
8689 // avoid swapping the members of the input list directly.
8690 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8693 // Map the input's dword into the correct half.
8694 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8695 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8697 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8699 "Previous placement doesn't match!");
8702 // And just directly shift any other-half mask elements to be same-half
8703 // as we will have mirrored the dword containing the element into the
8704 // same position within that half.
8705 for (int &M : HalfMask)
8706 if (M >= SourceOffset && M < SourceOffset + 4) {
8707 M = M - SourceOffset + DestOffset;
8708 assert(M >= 0 && "This should never wrap below zero!");
8713 // Ensure we have the input in a viable dword of its current half. This
8714 // is particularly tricky because the original position may be clobbered
8715 // by inputs being moved and *staying* in that half.
8716 if (IncomingInputs.size() == 1) {
8717 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8718 int InputFixed = std::find(std::begin(SourceHalfMask),
8719 std::end(SourceHalfMask), -1) -
8720 std::begin(SourceHalfMask) + SourceOffset;
8721 SourceHalfMask[InputFixed - SourceOffset] =
8722 IncomingInputs[0] - SourceOffset;
8723 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8725 IncomingInputs[0] = InputFixed;
8727 } else if (IncomingInputs.size() == 2) {
8728 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8729 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8730 // We have two non-adjacent or clobbered inputs we need to extract from
8731 // the source half. To do this, we need to map them into some adjacent
8732 // dword slot in the source mask.
8733 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8734 IncomingInputs[1] - SourceOffset};
8736 // If there is a free slot in the source half mask adjacent to one of
8737 // the inputs, place the other input in it. We use (Index XOR 1) to
8738 // compute an adjacent index.
8739 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8740 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8741 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8742 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8743 InputsFixed[1] = InputsFixed[0] ^ 1;
8744 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8745 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8746 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8747 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8748 InputsFixed[0] = InputsFixed[1] ^ 1;
8749 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8750 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8751 // The two inputs are in the same DWord but it is clobbered and the
8752 // adjacent DWord isn't used at all. Move both inputs to the free
8754 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8755 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8756 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8757 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8759 // The only way we hit this point is if there is no clobbering
8760 // (because there are no off-half inputs to this half) and there is no
8761 // free slot adjacent to one of the inputs. In this case, we have to
8762 // swap an input with a non-input.
8763 for (int i = 0; i < 4; ++i)
8764 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8765 "We can't handle any clobbers here!");
8766 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8767 "Cannot have adjacent inputs here!");
8769 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8770 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8772 // We also have to update the final source mask in this case because
8773 // it may need to undo the above swap.
8774 for (int &M : FinalSourceHalfMask)
8775 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8776 M = InputsFixed[1] + SourceOffset;
8777 else if (M == InputsFixed[1] + SourceOffset)
8778 M = (InputsFixed[0] ^ 1) + SourceOffset;
8780 InputsFixed[1] = InputsFixed[0] ^ 1;
8783 // Point everything at the fixed inputs.
8784 for (int &M : HalfMask)
8785 if (M == IncomingInputs[0])
8786 M = InputsFixed[0] + SourceOffset;
8787 else if (M == IncomingInputs[1])
8788 M = InputsFixed[1] + SourceOffset;
8790 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8791 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8794 llvm_unreachable("Unhandled input size!");
8797 // Now hoist the DWord down to the right half.
8798 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8799 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8800 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8801 for (int &M : HalfMask)
8802 for (int Input : IncomingInputs)
8804 M = FreeDWord * 2 + Input % 2;
8806 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8807 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8808 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8809 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8811 // Now enact all the shuffles we've computed to move the inputs into their
8813 if (!isNoopShuffleMask(PSHUFLMask))
8814 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8815 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8816 if (!isNoopShuffleMask(PSHUFHMask))
8817 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8818 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8819 if (!isNoopShuffleMask(PSHUFDMask))
8820 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8821 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8822 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8823 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8825 // At this point, each half should contain all its inputs, and we can then
8826 // just shuffle them into their final position.
8827 assert(std::count_if(LoMask.begin(), LoMask.end(),
8828 [](int M) { return M >= 4; }) == 0 &&
8829 "Failed to lift all the high half inputs to the low mask!");
8830 assert(std::count_if(HiMask.begin(), HiMask.end(),
8831 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8832 "Failed to lift all the low half inputs to the high mask!");
8834 // Do a half shuffle for the low mask.
8835 if (!isNoopShuffleMask(LoMask))
8836 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8837 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8839 // Do a half shuffle with the high mask after shifting its values down.
8840 for (int &M : HiMask)
8843 if (!isNoopShuffleMask(HiMask))
8844 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8845 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8850 /// \brief Detect whether the mask pattern should be lowered through
8853 /// This essentially tests whether viewing the mask as an interleaving of two
8854 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8855 /// lowering it through interleaving is a significantly better strategy.
8856 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8857 int NumEvenInputs[2] = {0, 0};
8858 int NumOddInputs[2] = {0, 0};
8859 int NumLoInputs[2] = {0, 0};
8860 int NumHiInputs[2] = {0, 0};
8861 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8865 int InputIdx = Mask[i] >= Size;
8868 ++NumLoInputs[InputIdx];
8870 ++NumHiInputs[InputIdx];
8873 ++NumEvenInputs[InputIdx];
8875 ++NumOddInputs[InputIdx];
8878 // The minimum number of cross-input results for both the interleaved and
8879 // split cases. If interleaving results in fewer cross-input results, return
8881 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8882 NumEvenInputs[0] + NumOddInputs[1]);
8883 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8884 NumLoInputs[0] + NumHiInputs[1]);
8885 return InterleavedCrosses < SplitCrosses;
8888 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8890 /// This strategy only works when the inputs from each vector fit into a single
8891 /// half of that vector, and generally there are not so many inputs as to leave
8892 /// the in-place shuffles required highly constrained (and thus expensive). It
8893 /// shifts all the inputs into a single side of both input vectors and then
8894 /// uses an unpack to interleave these inputs in a single vector. At that
8895 /// point, we will fall back on the generic single input shuffle lowering.
8896 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8898 MutableArrayRef<int> Mask,
8899 const X86Subtarget *Subtarget,
8900 SelectionDAG &DAG) {
8901 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8902 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8903 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8904 for (int i = 0; i < 8; ++i)
8905 if (Mask[i] >= 0 && Mask[i] < 4)
8906 LoV1Inputs.push_back(i);
8907 else if (Mask[i] >= 4 && Mask[i] < 8)
8908 HiV1Inputs.push_back(i);
8909 else if (Mask[i] >= 8 && Mask[i] < 12)
8910 LoV2Inputs.push_back(i);
8911 else if (Mask[i] >= 12)
8912 HiV2Inputs.push_back(i);
8914 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8915 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8918 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8919 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8920 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8922 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8923 HiV1Inputs.size() + HiV2Inputs.size();
8925 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8926 ArrayRef<int> HiInputs, bool MoveToLo,
8928 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8929 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8930 if (BadInputs.empty())
8933 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8934 int MoveOffset = MoveToLo ? 0 : 4;
8936 if (GoodInputs.empty()) {
8937 for (int BadInput : BadInputs) {
8938 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8939 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8942 if (GoodInputs.size() == 2) {
8943 // If the low inputs are spread across two dwords, pack them into
8945 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8946 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8947 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8948 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8950 // Otherwise pin the good inputs.
8951 for (int GoodInput : GoodInputs)
8952 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8955 if (BadInputs.size() == 2) {
8956 // If we have two bad inputs then there may be either one or two good
8957 // inputs fixed in place. Find a fixed input, and then find the *other*
8958 // two adjacent indices by using modular arithmetic.
8960 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8961 [](int M) { return M >= 0; }) -
8962 std::begin(MoveMask);
8964 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8965 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8966 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8967 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8968 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8969 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8970 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8972 assert(BadInputs.size() == 1 && "All sizes handled");
8973 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8974 std::end(MoveMask), -1) -
8975 std::begin(MoveMask);
8976 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8977 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8981 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8984 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8986 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8989 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8990 // cross-half traffic in the final shuffle.
8992 // Munge the mask to be a single-input mask after the unpack merges the
8996 M = 2 * (M % 4) + (M / 8);
8998 return DAG.getVectorShuffle(
8999 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9000 DL, MVT::v8i16, V1, V2),
9001 DAG.getUNDEF(MVT::v8i16), Mask);
9004 /// \brief Generic lowering of 8-lane i16 shuffles.
9006 /// This handles both single-input shuffles and combined shuffle/blends with
9007 /// two inputs. The single input shuffles are immediately delegated to
9008 /// a dedicated lowering routine.
9010 /// The blends are lowered in one of three fundamental ways. If there are few
9011 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9012 /// of the input is significantly cheaper when lowered as an interleaving of
9013 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9014 /// halves of the inputs separately (making them have relatively few inputs)
9015 /// and then concatenate them.
9016 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9017 const X86Subtarget *Subtarget,
9018 SelectionDAG &DAG) {
9020 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9021 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9022 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9023 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9024 ArrayRef<int> OrigMask = SVOp->getMask();
9025 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9026 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9027 MutableArrayRef<int> Mask(MaskStorage);
9029 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9031 // Whenever we can lower this as a zext, that instruction is strictly faster
9032 // than any alternative.
9033 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9034 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9037 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9038 auto isV2 = [](int M) { return M >= 8; };
9040 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9041 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9043 if (NumV2Inputs == 0)
9044 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9046 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9047 "to be V1-input shuffles.");
9049 // There are special ways we can lower some single-element blends.
9050 if (NumV2Inputs == 1)
9051 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9052 Mask, Subtarget, DAG))
9055 // Use dedicated unpack instructions for masks that match their pattern.
9056 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9057 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9058 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9059 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9061 if (Subtarget->hasSSE41())
9062 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9066 // Try to use rotation instructions if available.
9067 if (Subtarget->hasSSSE3())
9068 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9069 DL, MVT::v8i16, V1, V2, Mask, DAG))
9072 if (NumV1Inputs + NumV2Inputs <= 4)
9073 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9075 // Check whether an interleaving lowering is likely to be more efficient.
9076 // This isn't perfect but it is a strong heuristic that tends to work well on
9077 // the kinds of shuffles that show up in practice.
9079 // FIXME: Handle 1x, 2x, and 4x interleaving.
9080 if (shouldLowerAsInterleaving(Mask)) {
9081 // FIXME: Figure out whether we should pack these into the low or high
9084 int EMask[8], OMask[8];
9085 for (int i = 0; i < 4; ++i) {
9086 EMask[i] = Mask[2*i];
9087 OMask[i] = Mask[2*i + 1];
9092 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9093 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9095 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9098 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9099 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9101 for (int i = 0; i < 4; ++i) {
9102 LoBlendMask[i] = Mask[i];
9103 HiBlendMask[i] = Mask[i + 4];
9106 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9107 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9108 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9109 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9111 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9112 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9115 /// \brief Check whether a compaction lowering can be done by dropping even
9116 /// elements and compute how many times even elements must be dropped.
9118 /// This handles shuffles which take every Nth element where N is a power of
9119 /// two. Example shuffle masks:
9121 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9122 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9123 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9124 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9125 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9126 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9128 /// Any of these lanes can of course be undef.
9130 /// This routine only supports N <= 3.
9131 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9134 /// \returns N above, or the number of times even elements must be dropped if
9135 /// there is such a number. Otherwise returns zero.
9136 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9137 // Figure out whether we're looping over two inputs or just one.
9138 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9140 // The modulus for the shuffle vector entries is based on whether this is
9141 // a single input or not.
9142 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9143 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9144 "We should only be called with masks with a power-of-2 size!");
9146 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9148 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9149 // and 2^3 simultaneously. This is because we may have ambiguity with
9150 // partially undef inputs.
9151 bool ViableForN[3] = {true, true, true};
9153 for (int i = 0, e = Mask.size(); i < e; ++i) {
9154 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9159 bool IsAnyViable = false;
9160 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9161 if (ViableForN[j]) {
9164 // The shuffle mask must be equal to (i * 2^N) % M.
9165 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9168 ViableForN[j] = false;
9170 // Early exit if we exhaust the possible powers of two.
9175 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9179 // Return 0 as there is no viable power of two.
9183 /// \brief Generic lowering of v16i8 shuffles.
9185 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9186 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9187 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9188 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9190 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9191 const X86Subtarget *Subtarget,
9192 SelectionDAG &DAG) {
9194 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9195 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9196 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9197 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9198 ArrayRef<int> OrigMask = SVOp->getMask();
9199 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9201 // Try to use rotation instructions if available.
9202 if (Subtarget->hasSSSE3())
9203 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9204 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9207 // Try to use a zext lowering.
9208 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9209 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9212 int MaskStorage[16] = {
9213 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9214 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9215 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9216 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9217 MutableArrayRef<int> Mask(MaskStorage);
9218 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9219 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9222 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9224 // For single-input shuffles, there are some nicer lowering tricks we can use.
9225 if (NumV2Elements == 0) {
9226 // Check for being able to broadcast a single element.
9227 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9228 Mask, Subtarget, DAG))
9231 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9232 // Notably, this handles splat and partial-splat shuffles more efficiently.
9233 // However, it only makes sense if the pre-duplication shuffle simplifies
9234 // things significantly. Currently, this means we need to be able to
9235 // express the pre-duplication shuffle as an i16 shuffle.
9237 // FIXME: We should check for other patterns which can be widened into an
9238 // i16 shuffle as well.
9239 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9240 for (int i = 0; i < 16; i += 2)
9241 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9246 auto tryToWidenViaDuplication = [&]() -> SDValue {
9247 if (!canWidenViaDuplication(Mask))
9249 SmallVector<int, 4> LoInputs;
9250 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9251 [](int M) { return M >= 0 && M < 8; });
9252 std::sort(LoInputs.begin(), LoInputs.end());
9253 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9255 SmallVector<int, 4> HiInputs;
9256 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9257 [](int M) { return M >= 8; });
9258 std::sort(HiInputs.begin(), HiInputs.end());
9259 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9262 bool TargetLo = LoInputs.size() >= HiInputs.size();
9263 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9264 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9266 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9267 SmallDenseMap<int, int, 8> LaneMap;
9268 for (int I : InPlaceInputs) {
9269 PreDupI16Shuffle[I/2] = I/2;
9272 int j = TargetLo ? 0 : 4, je = j + 4;
9273 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9274 // Check if j is already a shuffle of this input. This happens when
9275 // there are two adjacent bytes after we move the low one.
9276 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9277 // If we haven't yet mapped the input, search for a slot into which
9279 while (j < je && PreDupI16Shuffle[j] != -1)
9283 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9286 // Map this input with the i16 shuffle.
9287 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9290 // Update the lane map based on the mapping we ended up with.
9291 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9294 ISD::BITCAST, DL, MVT::v16i8,
9295 DAG.getVectorShuffle(MVT::v8i16, DL,
9296 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9297 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9299 // Unpack the bytes to form the i16s that will be shuffled into place.
9300 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9301 MVT::v16i8, V1, V1);
9303 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9304 for (int i = 0; i < 16; ++i)
9305 if (Mask[i] != -1) {
9306 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9307 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9308 if (PostDupI16Shuffle[i / 2] == -1)
9309 PostDupI16Shuffle[i / 2] = MappedMask;
9311 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9312 "Conflicting entrties in the original shuffle!");
9315 ISD::BITCAST, DL, MVT::v16i8,
9316 DAG.getVectorShuffle(MVT::v8i16, DL,
9317 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9318 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9320 if (SDValue V = tryToWidenViaDuplication())
9324 // Check whether an interleaving lowering is likely to be more efficient.
9325 // This isn't perfect but it is a strong heuristic that tends to work well on
9326 // the kinds of shuffles that show up in practice.
9328 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9329 if (shouldLowerAsInterleaving(Mask)) {
9330 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9331 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9333 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9334 return (M >= 8 && M < 16) || M >= 24;
9336 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9337 -1, -1, -1, -1, -1, -1, -1, -1};
9338 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9339 -1, -1, -1, -1, -1, -1, -1, -1};
9340 bool UnpackLo = NumLoHalf >= NumHiHalf;
9341 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9342 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9343 for (int i = 0; i < 8; ++i) {
9344 TargetEMask[i] = Mask[2 * i];
9345 TargetOMask[i] = Mask[2 * i + 1];
9348 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9349 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9351 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9352 MVT::v16i8, Evens, Odds);
9355 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9356 // with PSHUFB. It is important to do this before we attempt to generate any
9357 // blends but after all of the single-input lowerings. If the single input
9358 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9359 // want to preserve that and we can DAG combine any longer sequences into
9360 // a PSHUFB in the end. But once we start blending from multiple inputs,
9361 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9362 // and there are *very* few patterns that would actually be faster than the
9363 // PSHUFB approach because of its ability to zero lanes.
9365 // FIXME: The only exceptions to the above are blends which are exact
9366 // interleavings with direct instructions supporting them. We currently don't
9367 // handle those well here.
9368 if (Subtarget->hasSSSE3()) {
9371 for (int i = 0; i < 16; ++i)
9372 if (Mask[i] == -1) {
9373 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9375 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9377 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9379 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9380 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9381 if (isSingleInputShuffleMask(Mask))
9382 return V1; // Single inputs are easy.
9384 // Otherwise, blend the two.
9385 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9386 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9387 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9390 // There are special ways we can lower some single-element blends.
9391 if (NumV2Elements == 1)
9392 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9393 Mask, Subtarget, DAG))
9396 // Check whether a compaction lowering can be done. This handles shuffles
9397 // which take every Nth element for some even N. See the helper function for
9400 // We special case these as they can be particularly efficiently handled with
9401 // the PACKUSB instruction on x86 and they show up in common patterns of
9402 // rearranging bytes to truncate wide elements.
9403 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9404 // NumEvenDrops is the power of two stride of the elements. Another way of
9405 // thinking about it is that we need to drop the even elements this many
9406 // times to get the original input.
9407 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9409 // First we need to zero all the dropped bytes.
9410 assert(NumEvenDrops <= 3 &&
9411 "No support for dropping even elements more than 3 times.");
9412 // We use the mask type to pick which bytes are preserved based on how many
9413 // elements are dropped.
9414 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9415 SDValue ByteClearMask =
9416 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9417 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9418 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9420 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9422 // Now pack things back together.
9423 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9424 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9425 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9426 for (int i = 1; i < NumEvenDrops; ++i) {
9427 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9428 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9434 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9435 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9436 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9437 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9439 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9440 MutableArrayRef<int> V1HalfBlendMask,
9441 MutableArrayRef<int> V2HalfBlendMask) {
9442 for (int i = 0; i < 8; ++i)
9443 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9444 V1HalfBlendMask[i] = HalfMask[i];
9446 } else if (HalfMask[i] >= 16) {
9447 V2HalfBlendMask[i] = HalfMask[i] - 16;
9448 HalfMask[i] = i + 8;
9451 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9452 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9454 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9456 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9457 MutableArrayRef<int> HiBlendMask) {
9459 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9460 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9462 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9463 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9464 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9465 [](int M) { return M >= 0 && M % 2 == 1; })) {
9466 // Use a mask to drop the high bytes.
9467 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9468 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9469 DAG.getConstant(0x00FF, MVT::v8i16));
9471 // This will be a single vector shuffle instead of a blend so nuke V2.
9472 V2 = DAG.getUNDEF(MVT::v8i16);
9474 // Squash the masks to point directly into V1.
9475 for (int &M : LoBlendMask)
9478 for (int &M : HiBlendMask)
9482 // Otherwise just unpack the low half of V into V1 and the high half into
9483 // V2 so that we can blend them as i16s.
9484 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9485 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9486 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9487 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9490 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9491 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9492 return std::make_pair(BlendedLo, BlendedHi);
9494 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9495 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9496 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9498 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9499 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9501 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9504 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9506 /// This routine breaks down the specific type of 128-bit shuffle and
9507 /// dispatches to the lowering routines accordingly.
9508 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9509 MVT VT, const X86Subtarget *Subtarget,
9510 SelectionDAG &DAG) {
9511 switch (VT.SimpleTy) {
9513 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9515 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9517 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9519 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9521 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9523 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9526 llvm_unreachable("Unimplemented!");
9530 /// \brief Helper function to test whether a shuffle mask could be
9531 /// simplified by widening the elements being shuffled.
9533 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9534 /// leaves it in an unspecified state.
9536 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9537 /// shuffle masks. The latter have the special property of a '-2' representing
9538 /// a zero-ed lane of a vector.
9539 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9540 SmallVectorImpl<int> &WidenedMask) {
9541 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9542 // If both elements are undef, its trivial.
9543 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9544 WidenedMask.push_back(SM_SentinelUndef);
9548 // Check for an undef mask and a mask value properly aligned to fit with
9549 // a pair of values. If we find such a case, use the non-undef mask's value.
9550 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9551 WidenedMask.push_back(Mask[i + 1] / 2);
9554 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9555 WidenedMask.push_back(Mask[i] / 2);
9559 // When zeroing, we need to spread the zeroing across both lanes to widen.
9560 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9561 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9562 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9563 WidenedMask.push_back(SM_SentinelZero);
9569 // Finally check if the two mask values are adjacent and aligned with
9571 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9572 WidenedMask.push_back(Mask[i] / 2);
9576 // Otherwise we can't safely widen the elements used in this shuffle.
9579 assert(WidenedMask.size() == Mask.size() / 2 &&
9580 "Incorrect size of mask after widening the elements!");
9585 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9587 /// This routine just extracts two subvectors, shuffles them independently, and
9588 /// then concatenates them back together. This should work effectively with all
9589 /// AVX vector shuffle types.
9590 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9591 SDValue V2, ArrayRef<int> Mask,
9592 SelectionDAG &DAG) {
9593 assert(VT.getSizeInBits() >= 256 &&
9594 "Only for 256-bit or wider vector shuffles!");
9595 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9596 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9598 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9599 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9601 int NumElements = VT.getVectorNumElements();
9602 int SplitNumElements = NumElements / 2;
9603 MVT ScalarVT = VT.getScalarType();
9604 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9606 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9607 DAG.getIntPtrConstant(0));
9608 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9609 DAG.getIntPtrConstant(SplitNumElements));
9610 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9611 DAG.getIntPtrConstant(0));
9612 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9613 DAG.getIntPtrConstant(SplitNumElements));
9615 // Now create two 4-way blends of these half-width vectors.
9616 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9617 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9618 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9619 for (int i = 0; i < SplitNumElements; ++i) {
9620 int M = HalfMask[i];
9621 if (M >= NumElements) {
9622 if (M >= NumElements + SplitNumElements)
9626 V2BlendMask.push_back(M - NumElements);
9627 V1BlendMask.push_back(-1);
9628 BlendMask.push_back(SplitNumElements + i);
9629 } else if (M >= 0) {
9630 if (M >= SplitNumElements)
9634 V2BlendMask.push_back(-1);
9635 V1BlendMask.push_back(M);
9636 BlendMask.push_back(i);
9638 V2BlendMask.push_back(-1);
9639 V1BlendMask.push_back(-1);
9640 BlendMask.push_back(-1);
9644 // Because the lowering happens after all combining takes place, we need to
9645 // manually combine these blend masks as much as possible so that we create
9646 // a minimal number of high-level vector shuffle nodes.
9648 // First try just blending the halves of V1 or V2.
9649 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9650 return DAG.getUNDEF(SplitVT);
9651 if (!UseLoV2 && !UseHiV2)
9652 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9653 if (!UseLoV1 && !UseHiV1)
9654 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9656 SDValue V1Blend, V2Blend;
9657 if (UseLoV1 && UseHiV1) {
9659 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9661 // We only use half of V1 so map the usage down into the final blend mask.
9662 V1Blend = UseLoV1 ? LoV1 : HiV1;
9663 for (int i = 0; i < SplitNumElements; ++i)
9664 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9665 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9667 if (UseLoV2 && UseHiV2) {
9669 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9671 // We only use half of V2 so map the usage down into the final blend mask.
9672 V2Blend = UseLoV2 ? LoV2 : HiV2;
9673 for (int i = 0; i < SplitNumElements; ++i)
9674 if (BlendMask[i] >= SplitNumElements)
9675 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9677 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9679 SDValue Lo = HalfBlend(LoMask);
9680 SDValue Hi = HalfBlend(HiMask);
9681 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9684 /// \brief Either split a vector in halves or decompose the shuffles and the
9687 /// This is provided as a good fallback for many lowerings of non-single-input
9688 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9689 /// between splitting the shuffle into 128-bit components and stitching those
9690 /// back together vs. extracting the single-input shuffles and blending those
9692 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9693 SDValue V2, ArrayRef<int> Mask,
9694 SelectionDAG &DAG) {
9695 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9696 "lower single-input shuffles as it "
9697 "could then recurse on itself.");
9698 int Size = Mask.size();
9700 // If this can be modeled as a broadcast of two elements followed by a blend,
9701 // prefer that lowering. This is especially important because broadcasts can
9702 // often fold with memory operands.
9703 auto DoBothBroadcast = [&] {
9704 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9707 if (V2BroadcastIdx == -1)
9708 V2BroadcastIdx = M - Size;
9709 else if (M - Size != V2BroadcastIdx)
9711 } else if (M >= 0) {
9712 if (V1BroadcastIdx == -1)
9714 else if (M != V1BroadcastIdx)
9719 if (DoBothBroadcast())
9720 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9723 // If the inputs all stem from a single 128-bit lane of each input, then we
9724 // split them rather than blending because the split will decompose to
9725 // unusually few instructions.
9726 int LaneCount = VT.getSizeInBits() / 128;
9727 int LaneSize = Size / LaneCount;
9728 SmallBitVector LaneInputs[2];
9729 LaneInputs[0].resize(LaneCount, false);
9730 LaneInputs[1].resize(LaneCount, false);
9731 for (int i = 0; i < Size; ++i)
9733 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9734 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9735 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9737 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9738 // that the decomposed single-input shuffles don't end up here.
9739 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9742 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9743 /// a permutation and blend of those lanes.
9745 /// This essentially blends the out-of-lane inputs to each lane into the lane
9746 /// from a permuted copy of the vector. This lowering strategy results in four
9747 /// instructions in the worst case for a single-input cross lane shuffle which
9748 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9749 /// of. Special cases for each particular shuffle pattern should be handled
9750 /// prior to trying this lowering.
9751 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9752 SDValue V1, SDValue V2,
9754 SelectionDAG &DAG) {
9755 // FIXME: This should probably be generalized for 512-bit vectors as well.
9756 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9757 int LaneSize = Mask.size() / 2;
9759 // If there are only inputs from one 128-bit lane, splitting will in fact be
9760 // less expensive. The flags track wether the given lane contains an element
9761 // that crosses to another lane.
9762 bool LaneCrossing[2] = {false, false};
9763 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9764 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9765 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9766 if (!LaneCrossing[0] || !LaneCrossing[1])
9767 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9769 if (isSingleInputShuffleMask(Mask)) {
9770 SmallVector<int, 32> FlippedBlendMask;
9771 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9772 FlippedBlendMask.push_back(
9773 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9775 : Mask[i] % LaneSize +
9776 (i / LaneSize) * LaneSize + Size));
9778 // Flip the vector, and blend the results which should now be in-lane. The
9779 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9780 // 5 for the high source. The value 3 selects the high half of source 2 and
9781 // the value 2 selects the low half of source 2. We only use source 2 to
9782 // allow folding it into a memory operand.
9783 unsigned PERMMask = 3 | 2 << 4;
9784 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9785 V1, DAG.getConstant(PERMMask, MVT::i8));
9786 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9789 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9790 // will be handled by the above logic and a blend of the results, much like
9791 // other patterns in AVX.
9792 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9795 /// \brief Handle lowering 2-lane 128-bit shuffles.
9796 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9797 SDValue V2, ArrayRef<int> Mask,
9798 const X86Subtarget *Subtarget,
9799 SelectionDAG &DAG) {
9800 // Blends are faster and handle all the non-lane-crossing cases.
9801 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9805 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9806 VT.getVectorNumElements() / 2);
9807 // Check for patterns which can be matched with a single insert of a 128-bit
9809 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9810 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9811 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9812 DAG.getIntPtrConstant(0));
9813 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9814 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9815 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9817 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9818 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9819 DAG.getIntPtrConstant(0));
9820 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9821 DAG.getIntPtrConstant(2));
9822 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9825 // Otherwise form a 128-bit permutation.
9826 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9827 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9828 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9829 DAG.getConstant(PermMask, MVT::i8));
9832 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9834 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9835 /// isn't available.
9836 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9837 const X86Subtarget *Subtarget,
9838 SelectionDAG &DAG) {
9840 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9841 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9842 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9843 ArrayRef<int> Mask = SVOp->getMask();
9844 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9846 SmallVector<int, 4> WidenedMask;
9847 if (canWidenShuffleElements(Mask, WidenedMask))
9848 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9851 if (isSingleInputShuffleMask(Mask)) {
9852 // Check for being able to broadcast a single element.
9853 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9854 Mask, Subtarget, DAG))
9857 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9858 // Non-half-crossing single input shuffles can be lowerid with an
9859 // interleaved permutation.
9860 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9861 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9862 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9863 DAG.getConstant(VPERMILPMask, MVT::i8));
9866 // With AVX2 we have direct support for this permutation.
9867 if (Subtarget->hasAVX2())
9868 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9869 getV4X86ShuffleImm8ForMask(Mask, DAG));
9871 // Otherwise, fall back.
9872 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9876 // X86 has dedicated unpack instructions that can handle specific blend
9877 // operations: UNPCKH and UNPCKL.
9878 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9879 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9880 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9881 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9883 // If we have a single input to the zero element, insert that into V1 if we
9884 // can do so cheaply.
9886 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9887 if (NumV2Elements == 1 && Mask[0] >= 4)
9888 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9889 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9892 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9896 // Check if the blend happens to exactly fit that of SHUFPD.
9897 if ((Mask[0] == -1 || Mask[0] < 2) &&
9898 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9899 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9900 (Mask[3] == -1 || Mask[3] >= 6)) {
9901 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9902 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9903 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9904 DAG.getConstant(SHUFPDMask, MVT::i8));
9906 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9907 (Mask[1] == -1 || Mask[1] < 2) &&
9908 (Mask[2] == -1 || Mask[2] >= 6) &&
9909 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9910 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9911 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9912 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9913 DAG.getConstant(SHUFPDMask, MVT::i8));
9916 // If we have AVX2 then we always want to lower with a blend because an v4 we
9917 // can fully permute the elements.
9918 if (Subtarget->hasAVX2())
9919 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9922 // Otherwise fall back on generic lowering.
9923 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9926 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9928 /// This routine is only called when we have AVX2 and thus a reasonable
9929 /// instruction set for v4i64 shuffling..
9930 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9931 const X86Subtarget *Subtarget,
9932 SelectionDAG &DAG) {
9934 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9935 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9936 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9937 ArrayRef<int> Mask = SVOp->getMask();
9938 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9939 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9941 SmallVector<int, 4> WidenedMask;
9942 if (canWidenShuffleElements(Mask, WidenedMask))
9943 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9946 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9950 // Check for being able to broadcast a single element.
9951 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9952 Mask, Subtarget, DAG))
9955 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9956 // use lower latency instructions that will operate on both 128-bit lanes.
9957 SmallVector<int, 2> RepeatedMask;
9958 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9959 if (isSingleInputShuffleMask(Mask)) {
9960 int PSHUFDMask[] = {-1, -1, -1, -1};
9961 for (int i = 0; i < 2; ++i)
9962 if (RepeatedMask[i] >= 0) {
9963 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9964 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9967 ISD::BITCAST, DL, MVT::v4i64,
9968 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9969 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9970 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9973 // Use dedicated unpack instructions for masks that match their pattern.
9974 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9975 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9976 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9977 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9980 // AVX2 provides a direct instruction for permuting a single input across
9982 if (isSingleInputShuffleMask(Mask))
9983 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9984 getV4X86ShuffleImm8ForMask(Mask, DAG));
9986 // Otherwise fall back on generic blend lowering.
9987 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9991 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9993 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9994 /// isn't available.
9995 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9996 const X86Subtarget *Subtarget,
9997 SelectionDAG &DAG) {
9999 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10000 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10001 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10002 ArrayRef<int> Mask = SVOp->getMask();
10003 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10005 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10009 // Check for being able to broadcast a single element.
10010 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10011 Mask, Subtarget, DAG))
10014 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10015 // options to efficiently lower the shuffle.
10016 SmallVector<int, 4> RepeatedMask;
10017 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10018 assert(RepeatedMask.size() == 4 &&
10019 "Repeated masks must be half the mask width!");
10020 if (isSingleInputShuffleMask(Mask))
10021 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10022 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10024 // Use dedicated unpack instructions for masks that match their pattern.
10025 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10026 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10027 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10028 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10030 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10031 // have already handled any direct blends. We also need to squash the
10032 // repeated mask into a simulated v4f32 mask.
10033 for (int i = 0; i < 4; ++i)
10034 if (RepeatedMask[i] >= 8)
10035 RepeatedMask[i] -= 4;
10036 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10039 // If we have a single input shuffle with different shuffle patterns in the
10040 // two 128-bit lanes use the variable mask to VPERMILPS.
10041 if (isSingleInputShuffleMask(Mask)) {
10042 SDValue VPermMask[8];
10043 for (int i = 0; i < 8; ++i)
10044 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10045 : DAG.getConstant(Mask[i], MVT::i32);
10046 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10047 return DAG.getNode(
10048 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10049 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10051 if (Subtarget->hasAVX2())
10052 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10053 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10054 DAG.getNode(ISD::BUILD_VECTOR, DL,
10055 MVT::v8i32, VPermMask)),
10058 // Otherwise, fall back.
10059 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10063 // If we have AVX2 then we always want to lower with a blend because at v8 we
10064 // can fully permute the elements.
10065 if (Subtarget->hasAVX2())
10066 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10069 // Otherwise fall back on generic lowering.
10070 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10073 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10075 /// This routine is only called when we have AVX2 and thus a reasonable
10076 /// instruction set for v8i32 shuffling..
10077 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10078 const X86Subtarget *Subtarget,
10079 SelectionDAG &DAG) {
10081 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10082 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10083 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10084 ArrayRef<int> Mask = SVOp->getMask();
10085 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10086 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10088 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10092 // Check for being able to broadcast a single element.
10093 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10094 Mask, Subtarget, DAG))
10097 // If the shuffle mask is repeated in each 128-bit lane we can use more
10098 // efficient instructions that mirror the shuffles across the two 128-bit
10100 SmallVector<int, 4> RepeatedMask;
10101 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10102 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10103 if (isSingleInputShuffleMask(Mask))
10104 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10105 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10107 // Use dedicated unpack instructions for masks that match their pattern.
10108 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10109 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10110 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10111 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10114 // If the shuffle patterns aren't repeated but it is a single input, directly
10115 // generate a cross-lane VPERMD instruction.
10116 if (isSingleInputShuffleMask(Mask)) {
10117 SDValue VPermMask[8];
10118 for (int i = 0; i < 8; ++i)
10119 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10120 : DAG.getConstant(Mask[i], MVT::i32);
10121 return DAG.getNode(
10122 X86ISD::VPERMV, DL, MVT::v8i32,
10123 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10126 // Otherwise fall back on generic blend lowering.
10127 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10131 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10133 /// This routine is only called when we have AVX2 and thus a reasonable
10134 /// instruction set for v16i16 shuffling..
10135 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10136 const X86Subtarget *Subtarget,
10137 SelectionDAG &DAG) {
10139 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10140 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10141 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10142 ArrayRef<int> Mask = SVOp->getMask();
10143 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10144 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10146 // Check for being able to broadcast a single element.
10147 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10148 Mask, Subtarget, DAG))
10151 // There are no generalized cross-lane shuffle operations available on i16
10153 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10154 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10157 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10161 // Use dedicated unpack instructions for masks that match their pattern.
10162 if (isShuffleEquivalent(Mask,
10163 // First 128-bit lane:
10164 0, 16, 1, 17, 2, 18, 3, 19,
10165 // Second 128-bit lane:
10166 8, 24, 9, 25, 10, 26, 11, 27))
10167 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10168 if (isShuffleEquivalent(Mask,
10169 // First 128-bit lane:
10170 4, 20, 5, 21, 6, 22, 7, 23,
10171 // Second 128-bit lane:
10172 12, 28, 13, 29, 14, 30, 15, 31))
10173 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10175 if (isSingleInputShuffleMask(Mask)) {
10176 SDValue PSHUFBMask[32];
10177 for (int i = 0; i < 16; ++i) {
10178 if (Mask[i] == -1) {
10179 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10183 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10184 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10185 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10186 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10188 return DAG.getNode(
10189 ISD::BITCAST, DL, MVT::v16i16,
10191 X86ISD::PSHUFB, DL, MVT::v32i8,
10192 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10193 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10196 // Otherwise fall back on generic lowering.
10197 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10200 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10202 /// This routine is only called when we have AVX2 and thus a reasonable
10203 /// instruction set for v32i8 shuffling..
10204 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10205 const X86Subtarget *Subtarget,
10206 SelectionDAG &DAG) {
10208 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10209 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10210 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10211 ArrayRef<int> Mask = SVOp->getMask();
10212 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10213 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10215 // Check for being able to broadcast a single element.
10216 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10217 Mask, Subtarget, DAG))
10220 // There are no generalized cross-lane shuffle operations available on i8
10222 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10223 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10226 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10230 // Use dedicated unpack instructions for masks that match their pattern.
10231 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10233 if (isShuffleEquivalent(
10235 // First 128-bit lane:
10236 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10237 // Second 128-bit lane:
10238 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10239 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10240 if (isShuffleEquivalent(
10242 // First 128-bit lane:
10243 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10244 // Second 128-bit lane:
10245 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10246 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10248 if (isSingleInputShuffleMask(Mask)) {
10249 SDValue PSHUFBMask[32];
10250 for (int i = 0; i < 32; ++i)
10253 ? DAG.getUNDEF(MVT::i8)
10254 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10256 return DAG.getNode(
10257 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10258 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10261 // Otherwise fall back on generic lowering.
10262 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10265 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10267 /// This routine either breaks down the specific type of a 256-bit x86 vector
10268 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10269 /// together based on the available instructions.
10270 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10271 MVT VT, const X86Subtarget *Subtarget,
10272 SelectionDAG &DAG) {
10274 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10275 ArrayRef<int> Mask = SVOp->getMask();
10277 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10278 // check for those subtargets here and avoid much of the subtarget querying in
10279 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10280 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10281 // floating point types there eventually, just immediately cast everything to
10282 // a float and operate entirely in that domain.
10283 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10284 int ElementBits = VT.getScalarSizeInBits();
10285 if (ElementBits < 32)
10286 // No floating point type available, decompose into 128-bit vectors.
10287 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10289 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10290 VT.getVectorNumElements());
10291 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10292 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10293 return DAG.getNode(ISD::BITCAST, DL, VT,
10294 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10297 switch (VT.SimpleTy) {
10299 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10301 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10303 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10305 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10307 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10309 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10312 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10316 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10317 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10318 const X86Subtarget *Subtarget,
10319 SelectionDAG &DAG) {
10321 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10322 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10323 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10324 ArrayRef<int> Mask = SVOp->getMask();
10325 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10327 // FIXME: Implement direct support for this type!
10328 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10331 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10332 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10333 const X86Subtarget *Subtarget,
10334 SelectionDAG &DAG) {
10336 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10337 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10338 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10339 ArrayRef<int> Mask = SVOp->getMask();
10340 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10342 // FIXME: Implement direct support for this type!
10343 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10346 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10347 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10348 const X86Subtarget *Subtarget,
10349 SelectionDAG &DAG) {
10351 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10352 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10353 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10354 ArrayRef<int> Mask = SVOp->getMask();
10355 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10357 // FIXME: Implement direct support for this type!
10358 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10361 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10362 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10363 const X86Subtarget *Subtarget,
10364 SelectionDAG &DAG) {
10366 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10367 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10368 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10369 ArrayRef<int> Mask = SVOp->getMask();
10370 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10372 // FIXME: Implement direct support for this type!
10373 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10376 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10377 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10378 const X86Subtarget *Subtarget,
10379 SelectionDAG &DAG) {
10381 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10382 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10383 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10384 ArrayRef<int> Mask = SVOp->getMask();
10385 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10386 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10388 // FIXME: Implement direct support for this type!
10389 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10392 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10393 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10394 const X86Subtarget *Subtarget,
10395 SelectionDAG &DAG) {
10397 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10398 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10399 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10400 ArrayRef<int> Mask = SVOp->getMask();
10401 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10402 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10404 // FIXME: Implement direct support for this type!
10405 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10408 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10410 /// This routine either breaks down the specific type of a 512-bit x86 vector
10411 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10412 /// together based on the available instructions.
10413 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10414 MVT VT, const X86Subtarget *Subtarget,
10415 SelectionDAG &DAG) {
10417 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10418 ArrayRef<int> Mask = SVOp->getMask();
10419 assert(Subtarget->hasAVX512() &&
10420 "Cannot lower 512-bit vectors w/ basic ISA!");
10422 // Check for being able to broadcast a single element.
10423 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10424 Mask, Subtarget, DAG))
10427 // Dispatch to each element type for lowering. If we don't have supprot for
10428 // specific element type shuffles at 512 bits, immediately split them and
10429 // lower them. Each lowering routine of a given type is allowed to assume that
10430 // the requisite ISA extensions for that element type are available.
10431 switch (VT.SimpleTy) {
10433 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10435 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10437 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10439 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10441 if (Subtarget->hasBWI())
10442 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10445 if (Subtarget->hasBWI())
10446 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10450 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10453 // Otherwise fall back on splitting.
10454 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10457 /// \brief Top-level lowering for x86 vector shuffles.
10459 /// This handles decomposition, canonicalization, and lowering of all x86
10460 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10461 /// above in helper routines. The canonicalization attempts to widen shuffles
10462 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10463 /// s.t. only one of the two inputs needs to be tested, etc.
10464 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10465 SelectionDAG &DAG) {
10466 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10467 ArrayRef<int> Mask = SVOp->getMask();
10468 SDValue V1 = Op.getOperand(0);
10469 SDValue V2 = Op.getOperand(1);
10470 MVT VT = Op.getSimpleValueType();
10471 int NumElements = VT.getVectorNumElements();
10474 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10476 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10477 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10478 if (V1IsUndef && V2IsUndef)
10479 return DAG.getUNDEF(VT);
10481 // When we create a shuffle node we put the UNDEF node to second operand,
10482 // but in some cases the first operand may be transformed to UNDEF.
10483 // In this case we should just commute the node.
10485 return DAG.getCommutedVectorShuffle(*SVOp);
10487 // Check for non-undef masks pointing at an undef vector and make the masks
10488 // undef as well. This makes it easier to match the shuffle based solely on
10492 if (M >= NumElements) {
10493 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10494 for (int &M : NewMask)
10495 if (M >= NumElements)
10497 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10500 // Try to collapse shuffles into using a vector type with fewer elements but
10501 // wider element types. We cap this to not form integers or floating point
10502 // elements wider than 64 bits, but it might be interesting to form i128
10503 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10504 SmallVector<int, 16> WidenedMask;
10505 if (VT.getScalarSizeInBits() < 64 &&
10506 canWidenShuffleElements(Mask, WidenedMask)) {
10507 MVT NewEltVT = VT.isFloatingPoint()
10508 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10509 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10510 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10511 // Make sure that the new vector type is legal. For example, v2f64 isn't
10513 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10514 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10515 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10516 return DAG.getNode(ISD::BITCAST, dl, VT,
10517 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10521 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10522 for (int M : SVOp->getMask())
10524 ++NumUndefElements;
10525 else if (M < NumElements)
10530 // Commute the shuffle as needed such that more elements come from V1 than
10531 // V2. This allows us to match the shuffle pattern strictly on how many
10532 // elements come from V1 without handling the symmetric cases.
10533 if (NumV2Elements > NumV1Elements)
10534 return DAG.getCommutedVectorShuffle(*SVOp);
10536 // When the number of V1 and V2 elements are the same, try to minimize the
10537 // number of uses of V2 in the low half of the vector. When that is tied,
10538 // ensure that the sum of indices for V1 is equal to or lower than the sum
10540 if (NumV1Elements == NumV2Elements) {
10541 int LowV1Elements = 0, LowV2Elements = 0;
10542 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10543 if (M >= NumElements)
10547 if (LowV2Elements > LowV1Elements) {
10548 return DAG.getCommutedVectorShuffle(*SVOp);
10549 } else if (LowV2Elements == LowV1Elements) {
10550 int SumV1Indices = 0, SumV2Indices = 0;
10551 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10552 if (SVOp->getMask()[i] >= NumElements)
10554 else if (SVOp->getMask()[i] >= 0)
10556 if (SumV2Indices < SumV1Indices)
10557 return DAG.getCommutedVectorShuffle(*SVOp);
10561 // For each vector width, delegate to a specialized lowering routine.
10562 if (VT.getSizeInBits() == 128)
10563 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10565 if (VT.getSizeInBits() == 256)
10566 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10568 // Force AVX-512 vectors to be scalarized for now.
10569 // FIXME: Implement AVX-512 support!
10570 if (VT.getSizeInBits() == 512)
10571 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10573 llvm_unreachable("Unimplemented!");
10577 //===----------------------------------------------------------------------===//
10578 // Legacy vector shuffle lowering
10580 // This code is the legacy code handling vector shuffles until the above
10581 // replaces its functionality and performance.
10582 //===----------------------------------------------------------------------===//
10584 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10585 bool hasInt256, unsigned *MaskOut = nullptr) {
10586 MVT EltVT = VT.getVectorElementType();
10588 // There is no blend with immediate in AVX-512.
10589 if (VT.is512BitVector())
10592 if (!hasSSE41 || EltVT == MVT::i8)
10594 if (!hasInt256 && VT == MVT::v16i16)
10597 unsigned MaskValue = 0;
10598 unsigned NumElems = VT.getVectorNumElements();
10599 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10600 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10601 unsigned NumElemsInLane = NumElems / NumLanes;
10603 // Blend for v16i16 should be symetric for the both lanes.
10604 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10606 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10607 int EltIdx = MaskVals[i];
10609 if ((EltIdx < 0 || EltIdx == (int)i) &&
10610 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10613 if (((unsigned)EltIdx == (i + NumElems)) &&
10614 (SndLaneEltIdx < 0 ||
10615 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10616 MaskValue |= (1 << i);
10622 *MaskOut = MaskValue;
10626 // Try to lower a shuffle node into a simple blend instruction.
10627 // This function assumes isBlendMask returns true for this
10628 // SuffleVectorSDNode
10629 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10630 unsigned MaskValue,
10631 const X86Subtarget *Subtarget,
10632 SelectionDAG &DAG) {
10633 MVT VT = SVOp->getSimpleValueType(0);
10634 MVT EltVT = VT.getVectorElementType();
10635 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10636 Subtarget->hasInt256() && "Trying to lower a "
10637 "VECTOR_SHUFFLE to a Blend but "
10638 "with the wrong mask"));
10639 SDValue V1 = SVOp->getOperand(0);
10640 SDValue V2 = SVOp->getOperand(1);
10642 unsigned NumElems = VT.getVectorNumElements();
10644 // Convert i32 vectors to floating point if it is not AVX2.
10645 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10647 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10648 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10650 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10651 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10654 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10655 DAG.getConstant(MaskValue, MVT::i32));
10656 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10659 /// In vector type \p VT, return true if the element at index \p InputIdx
10660 /// falls on a different 128-bit lane than \p OutputIdx.
10661 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10662 unsigned OutputIdx) {
10663 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10664 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10667 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10668 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10669 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10670 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10672 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10673 SelectionDAG &DAG) {
10674 MVT VT = V1.getSimpleValueType();
10675 assert(VT.is128BitVector() || VT.is256BitVector());
10677 MVT EltVT = VT.getVectorElementType();
10678 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10679 unsigned NumElts = VT.getVectorNumElements();
10681 SmallVector<SDValue, 32> PshufbMask;
10682 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10683 int InputIdx = MaskVals[OutputIdx];
10684 unsigned InputByteIdx;
10686 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10687 InputByteIdx = 0x80;
10689 // Cross lane is not allowed.
10690 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10692 InputByteIdx = InputIdx * EltSizeInBytes;
10693 // Index is an byte offset within the 128-bit lane.
10694 InputByteIdx &= 0xf;
10697 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10698 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10699 if (InputByteIdx != 0x80)
10704 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10706 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10707 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10708 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10711 // v8i16 shuffles - Prefer shuffles in the following order:
10712 // 1. [all] pshuflw, pshufhw, optional move
10713 // 2. [ssse3] 1 x pshufb
10714 // 3. [ssse3] 2 x pshufb + 1 x por
10715 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10717 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10718 SelectionDAG &DAG) {
10719 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10720 SDValue V1 = SVOp->getOperand(0);
10721 SDValue V2 = SVOp->getOperand(1);
10723 SmallVector<int, 8> MaskVals;
10725 // Determine if more than 1 of the words in each of the low and high quadwords
10726 // of the result come from the same quadword of one of the two inputs. Undef
10727 // mask values count as coming from any quadword, for better codegen.
10729 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10730 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10731 unsigned LoQuad[] = { 0, 0, 0, 0 };
10732 unsigned HiQuad[] = { 0, 0, 0, 0 };
10733 // Indices of quads used.
10734 std::bitset<4> InputQuads;
10735 for (unsigned i = 0; i < 8; ++i) {
10736 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10737 int EltIdx = SVOp->getMaskElt(i);
10738 MaskVals.push_back(EltIdx);
10746 ++Quad[EltIdx / 4];
10747 InputQuads.set(EltIdx / 4);
10750 int BestLoQuad = -1;
10751 unsigned MaxQuad = 1;
10752 for (unsigned i = 0; i < 4; ++i) {
10753 if (LoQuad[i] > MaxQuad) {
10755 MaxQuad = LoQuad[i];
10759 int BestHiQuad = -1;
10761 for (unsigned i = 0; i < 4; ++i) {
10762 if (HiQuad[i] > MaxQuad) {
10764 MaxQuad = HiQuad[i];
10768 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10769 // of the two input vectors, shuffle them into one input vector so only a
10770 // single pshufb instruction is necessary. If there are more than 2 input
10771 // quads, disable the next transformation since it does not help SSSE3.
10772 bool V1Used = InputQuads[0] || InputQuads[1];
10773 bool V2Used = InputQuads[2] || InputQuads[3];
10774 if (Subtarget->hasSSSE3()) {
10775 if (InputQuads.count() == 2 && V1Used && V2Used) {
10776 BestLoQuad = InputQuads[0] ? 0 : 1;
10777 BestHiQuad = InputQuads[2] ? 2 : 3;
10779 if (InputQuads.count() > 2) {
10785 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10786 // the shuffle mask. If a quad is scored as -1, that means that it contains
10787 // words from all 4 input quadwords.
10789 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10791 BestLoQuad < 0 ? 0 : BestLoQuad,
10792 BestHiQuad < 0 ? 1 : BestHiQuad
10794 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10795 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10796 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10797 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10799 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10800 // source words for the shuffle, to aid later transformations.
10801 bool AllWordsInNewV = true;
10802 bool InOrder[2] = { true, true };
10803 for (unsigned i = 0; i != 8; ++i) {
10804 int idx = MaskVals[i];
10806 InOrder[i/4] = false;
10807 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10809 AllWordsInNewV = false;
10813 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10814 if (AllWordsInNewV) {
10815 for (int i = 0; i != 8; ++i) {
10816 int idx = MaskVals[i];
10819 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10820 if ((idx != i) && idx < 4)
10822 if ((idx != i) && idx > 3)
10831 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10832 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10833 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10834 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10835 unsigned TargetMask = 0;
10836 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10837 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10838 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10839 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10840 getShufflePSHUFLWImmediate(SVOp);
10841 V1 = NewV.getOperand(0);
10842 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10846 // Promote splats to a larger type which usually leads to more efficient code.
10847 // FIXME: Is this true if pshufb is available?
10848 if (SVOp->isSplat())
10849 return PromoteSplat(SVOp, DAG);
10851 // If we have SSSE3, and all words of the result are from 1 input vector,
10852 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10853 // is present, fall back to case 4.
10854 if (Subtarget->hasSSSE3()) {
10855 SmallVector<SDValue,16> pshufbMask;
10857 // If we have elements from both input vectors, set the high bit of the
10858 // shuffle mask element to zero out elements that come from V2 in the V1
10859 // mask, and elements that come from V1 in the V2 mask, so that the two
10860 // results can be OR'd together.
10861 bool TwoInputs = V1Used && V2Used;
10862 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10864 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10866 // Calculate the shuffle mask for the second input, shuffle it, and
10867 // OR it with the first shuffled input.
10868 CommuteVectorShuffleMask(MaskVals, 8);
10869 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10870 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10871 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10874 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10875 // and update MaskVals with new element order.
10876 std::bitset<8> InOrder;
10877 if (BestLoQuad >= 0) {
10878 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10879 for (int i = 0; i != 4; ++i) {
10880 int idx = MaskVals[i];
10883 } else if ((idx / 4) == BestLoQuad) {
10884 MaskV[i] = idx & 3;
10888 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10891 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10892 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10893 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10894 NewV.getOperand(0),
10895 getShufflePSHUFLWImmediate(SVOp), DAG);
10899 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10900 // and update MaskVals with the new element order.
10901 if (BestHiQuad >= 0) {
10902 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10903 for (unsigned i = 4; i != 8; ++i) {
10904 int idx = MaskVals[i];
10907 } else if ((idx / 4) == BestHiQuad) {
10908 MaskV[i] = (idx & 3) + 4;
10912 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10915 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10916 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10917 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10918 NewV.getOperand(0),
10919 getShufflePSHUFHWImmediate(SVOp), DAG);
10923 // In case BestHi & BestLo were both -1, which means each quadword has a word
10924 // from each of the four input quadwords, calculate the InOrder bitvector now
10925 // before falling through to the insert/extract cleanup.
10926 if (BestLoQuad == -1 && BestHiQuad == -1) {
10928 for (int i = 0; i != 8; ++i)
10929 if (MaskVals[i] < 0 || MaskVals[i] == i)
10933 // The other elements are put in the right place using pextrw and pinsrw.
10934 for (unsigned i = 0; i != 8; ++i) {
10937 int EltIdx = MaskVals[i];
10940 SDValue ExtOp = (EltIdx < 8) ?
10941 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10942 DAG.getIntPtrConstant(EltIdx)) :
10943 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10944 DAG.getIntPtrConstant(EltIdx - 8));
10945 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10946 DAG.getIntPtrConstant(i));
10951 /// \brief v16i16 shuffles
10953 /// FIXME: We only support generation of a single pshufb currently. We can
10954 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10955 /// well (e.g 2 x pshufb + 1 x por).
10957 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10958 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10959 SDValue V1 = SVOp->getOperand(0);
10960 SDValue V2 = SVOp->getOperand(1);
10963 if (V2.getOpcode() != ISD::UNDEF)
10966 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10967 return getPSHUFB(MaskVals, V1, dl, DAG);
10970 // v16i8 shuffles - Prefer shuffles in the following order:
10971 // 1. [ssse3] 1 x pshufb
10972 // 2. [ssse3] 2 x pshufb + 1 x por
10973 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10974 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10975 const X86Subtarget* Subtarget,
10976 SelectionDAG &DAG) {
10977 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10978 SDValue V1 = SVOp->getOperand(0);
10979 SDValue V2 = SVOp->getOperand(1);
10981 ArrayRef<int> MaskVals = SVOp->getMask();
10983 // Promote splats to a larger type which usually leads to more efficient code.
10984 // FIXME: Is this true if pshufb is available?
10985 if (SVOp->isSplat())
10986 return PromoteSplat(SVOp, DAG);
10988 // If we have SSSE3, case 1 is generated when all result bytes come from
10989 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10990 // present, fall back to case 3.
10992 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10993 if (Subtarget->hasSSSE3()) {
10994 SmallVector<SDValue,16> pshufbMask;
10996 // If all result elements are from one input vector, then only translate
10997 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10999 // Otherwise, we have elements from both input vectors, and must zero out
11000 // elements that come from V2 in the first mask, and V1 in the second mask
11001 // so that we can OR them together.
11002 for (unsigned i = 0; i != 16; ++i) {
11003 int EltIdx = MaskVals[i];
11004 if (EltIdx < 0 || EltIdx >= 16)
11006 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11008 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11009 DAG.getNode(ISD::BUILD_VECTOR, dl,
11010 MVT::v16i8, pshufbMask));
11012 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11013 // the 2nd operand if it's undefined or zero.
11014 if (V2.getOpcode() == ISD::UNDEF ||
11015 ISD::isBuildVectorAllZeros(V2.getNode()))
11018 // Calculate the shuffle mask for the second input, shuffle it, and
11019 // OR it with the first shuffled input.
11020 pshufbMask.clear();
11021 for (unsigned i = 0; i != 16; ++i) {
11022 int EltIdx = MaskVals[i];
11023 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11024 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11026 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11027 DAG.getNode(ISD::BUILD_VECTOR, dl,
11028 MVT::v16i8, pshufbMask));
11029 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11032 // No SSSE3 - Calculate in place words and then fix all out of place words
11033 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11034 // the 16 different words that comprise the two doublequadword input vectors.
11035 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11036 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11038 for (int i = 0; i != 8; ++i) {
11039 int Elt0 = MaskVals[i*2];
11040 int Elt1 = MaskVals[i*2+1];
11042 // This word of the result is all undef, skip it.
11043 if (Elt0 < 0 && Elt1 < 0)
11046 // This word of the result is already in the correct place, skip it.
11047 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11050 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11051 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11054 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11055 // using a single extract together, load it and store it.
11056 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11057 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11058 DAG.getIntPtrConstant(Elt1 / 2));
11059 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11060 DAG.getIntPtrConstant(i));
11064 // If Elt1 is defined, extract it from the appropriate source. If the
11065 // source byte is not also odd, shift the extracted word left 8 bits
11066 // otherwise clear the bottom 8 bits if we need to do an or.
11068 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11069 DAG.getIntPtrConstant(Elt1 / 2));
11070 if ((Elt1 & 1) == 0)
11071 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11073 TLI.getShiftAmountTy(InsElt.getValueType())));
11074 else if (Elt0 >= 0)
11075 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11076 DAG.getConstant(0xFF00, MVT::i16));
11078 // If Elt0 is defined, extract it from the appropriate source. If the
11079 // source byte is not also even, shift the extracted word right 8 bits. If
11080 // Elt1 was also defined, OR the extracted values together before
11081 // inserting them in the result.
11083 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11084 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11085 if ((Elt0 & 1) != 0)
11086 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11088 TLI.getShiftAmountTy(InsElt0.getValueType())));
11089 else if (Elt1 >= 0)
11090 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11091 DAG.getConstant(0x00FF, MVT::i16));
11092 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11095 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11096 DAG.getIntPtrConstant(i));
11098 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11101 // v32i8 shuffles - Translate to VPSHUFB if possible.
11103 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11104 const X86Subtarget *Subtarget,
11105 SelectionDAG &DAG) {
11106 MVT VT = SVOp->getSimpleValueType(0);
11107 SDValue V1 = SVOp->getOperand(0);
11108 SDValue V2 = SVOp->getOperand(1);
11110 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11112 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11113 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11114 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11116 // VPSHUFB may be generated if
11117 // (1) one of input vector is undefined or zeroinitializer.
11118 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11119 // And (2) the mask indexes don't cross the 128-bit lane.
11120 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11121 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11124 if (V1IsAllZero && !V2IsAllZero) {
11125 CommuteVectorShuffleMask(MaskVals, 32);
11128 return getPSHUFB(MaskVals, V1, dl, DAG);
11131 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11132 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11133 /// done when every pair / quad of shuffle mask elements point to elements in
11134 /// the right sequence. e.g.
11135 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11137 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11138 SelectionDAG &DAG) {
11139 MVT VT = SVOp->getSimpleValueType(0);
11141 unsigned NumElems = VT.getVectorNumElements();
11144 switch (VT.SimpleTy) {
11145 default: llvm_unreachable("Unexpected!");
11148 return SDValue(SVOp, 0);
11149 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11150 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11151 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11152 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11153 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11154 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11157 SmallVector<int, 8> MaskVec;
11158 for (unsigned i = 0; i != NumElems; i += Scale) {
11160 for (unsigned j = 0; j != Scale; ++j) {
11161 int EltIdx = SVOp->getMaskElt(i+j);
11165 StartIdx = (EltIdx / Scale);
11166 if (EltIdx != (int)(StartIdx*Scale + j))
11169 MaskVec.push_back(StartIdx);
11172 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11173 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11174 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11177 /// getVZextMovL - Return a zero-extending vector move low node.
11179 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11180 SDValue SrcOp, SelectionDAG &DAG,
11181 const X86Subtarget *Subtarget, SDLoc dl) {
11182 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11183 LoadSDNode *LD = nullptr;
11184 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11185 LD = dyn_cast<LoadSDNode>(SrcOp);
11187 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11189 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11190 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11191 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11192 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11193 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11195 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11196 return DAG.getNode(ISD::BITCAST, dl, VT,
11197 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11198 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11200 SrcOp.getOperand(0)
11206 return DAG.getNode(ISD::BITCAST, dl, VT,
11207 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11208 DAG.getNode(ISD::BITCAST, dl,
11212 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11213 /// which could not be matched by any known target speficic shuffle
11215 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11217 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11218 if (NewOp.getNode())
11221 MVT VT = SVOp->getSimpleValueType(0);
11223 unsigned NumElems = VT.getVectorNumElements();
11224 unsigned NumLaneElems = NumElems / 2;
11227 MVT EltVT = VT.getVectorElementType();
11228 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11231 SmallVector<int, 16> Mask;
11232 for (unsigned l = 0; l < 2; ++l) {
11233 // Build a shuffle mask for the output, discovering on the fly which
11234 // input vectors to use as shuffle operands (recorded in InputUsed).
11235 // If building a suitable shuffle vector proves too hard, then bail
11236 // out with UseBuildVector set.
11237 bool UseBuildVector = false;
11238 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11239 unsigned LaneStart = l * NumLaneElems;
11240 for (unsigned i = 0; i != NumLaneElems; ++i) {
11241 // The mask element. This indexes into the input.
11242 int Idx = SVOp->getMaskElt(i+LaneStart);
11244 // the mask element does not index into any input vector.
11245 Mask.push_back(-1);
11249 // The input vector this mask element indexes into.
11250 int Input = Idx / NumLaneElems;
11252 // Turn the index into an offset from the start of the input vector.
11253 Idx -= Input * NumLaneElems;
11255 // Find or create a shuffle vector operand to hold this input.
11257 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11258 if (InputUsed[OpNo] == Input)
11259 // This input vector is already an operand.
11261 if (InputUsed[OpNo] < 0) {
11262 // Create a new operand for this input vector.
11263 InputUsed[OpNo] = Input;
11268 if (OpNo >= array_lengthof(InputUsed)) {
11269 // More than two input vectors used! Give up on trying to create a
11270 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11271 UseBuildVector = true;
11275 // Add the mask index for the new shuffle vector.
11276 Mask.push_back(Idx + OpNo * NumLaneElems);
11279 if (UseBuildVector) {
11280 SmallVector<SDValue, 16> SVOps;
11281 for (unsigned i = 0; i != NumLaneElems; ++i) {
11282 // The mask element. This indexes into the input.
11283 int Idx = SVOp->getMaskElt(i+LaneStart);
11285 SVOps.push_back(DAG.getUNDEF(EltVT));
11289 // The input vector this mask element indexes into.
11290 int Input = Idx / NumElems;
11292 // Turn the index into an offset from the start of the input vector.
11293 Idx -= Input * NumElems;
11295 // Extract the vector element by hand.
11296 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11297 SVOp->getOperand(Input),
11298 DAG.getIntPtrConstant(Idx)));
11301 // Construct the output using a BUILD_VECTOR.
11302 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11303 } else if (InputUsed[0] < 0) {
11304 // No input vectors were used! The result is undefined.
11305 Output[l] = DAG.getUNDEF(NVT);
11307 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11308 (InputUsed[0] % 2) * NumLaneElems,
11310 // If only one input was used, use an undefined vector for the other.
11311 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11312 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11313 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11314 // At least one input vector was used. Create a new shuffle vector.
11315 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11321 // Concatenate the result back
11322 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11325 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11326 /// 4 elements, and match them with several different shuffle types.
11328 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11329 SDValue V1 = SVOp->getOperand(0);
11330 SDValue V2 = SVOp->getOperand(1);
11332 MVT VT = SVOp->getSimpleValueType(0);
11334 assert(VT.is128BitVector() && "Unsupported vector size");
11336 std::pair<int, int> Locs[4];
11337 int Mask1[] = { -1, -1, -1, -1 };
11338 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11340 unsigned NumHi = 0;
11341 unsigned NumLo = 0;
11342 for (unsigned i = 0; i != 4; ++i) {
11343 int Idx = PermMask[i];
11345 Locs[i] = std::make_pair(-1, -1);
11347 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11349 Locs[i] = std::make_pair(0, NumLo);
11350 Mask1[NumLo] = Idx;
11353 Locs[i] = std::make_pair(1, NumHi);
11355 Mask1[2+NumHi] = Idx;
11361 if (NumLo <= 2 && NumHi <= 2) {
11362 // If no more than two elements come from either vector. This can be
11363 // implemented with two shuffles. First shuffle gather the elements.
11364 // The second shuffle, which takes the first shuffle as both of its
11365 // vector operands, put the elements into the right order.
11366 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11368 int Mask2[] = { -1, -1, -1, -1 };
11370 for (unsigned i = 0; i != 4; ++i)
11371 if (Locs[i].first != -1) {
11372 unsigned Idx = (i < 2) ? 0 : 4;
11373 Idx += Locs[i].first * 2 + Locs[i].second;
11377 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11380 if (NumLo == 3 || NumHi == 3) {
11381 // Otherwise, we must have three elements from one vector, call it X, and
11382 // one element from the other, call it Y. First, use a shufps to build an
11383 // intermediate vector with the one element from Y and the element from X
11384 // that will be in the same half in the final destination (the indexes don't
11385 // matter). Then, use a shufps to build the final vector, taking the half
11386 // containing the element from Y from the intermediate, and the other half
11389 // Normalize it so the 3 elements come from V1.
11390 CommuteVectorShuffleMask(PermMask, 4);
11394 // Find the element from V2.
11396 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11397 int Val = PermMask[HiIndex];
11404 Mask1[0] = PermMask[HiIndex];
11406 Mask1[2] = PermMask[HiIndex^1];
11408 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11410 if (HiIndex >= 2) {
11411 Mask1[0] = PermMask[0];
11412 Mask1[1] = PermMask[1];
11413 Mask1[2] = HiIndex & 1 ? 6 : 4;
11414 Mask1[3] = HiIndex & 1 ? 4 : 6;
11415 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11418 Mask1[0] = HiIndex & 1 ? 2 : 0;
11419 Mask1[1] = HiIndex & 1 ? 0 : 2;
11420 Mask1[2] = PermMask[2];
11421 Mask1[3] = PermMask[3];
11426 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11429 // Break it into (shuffle shuffle_hi, shuffle_lo).
11430 int LoMask[] = { -1, -1, -1, -1 };
11431 int HiMask[] = { -1, -1, -1, -1 };
11433 int *MaskPtr = LoMask;
11434 unsigned MaskIdx = 0;
11435 unsigned LoIdx = 0;
11436 unsigned HiIdx = 2;
11437 for (unsigned i = 0; i != 4; ++i) {
11444 int Idx = PermMask[i];
11446 Locs[i] = std::make_pair(-1, -1);
11447 } else if (Idx < 4) {
11448 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11449 MaskPtr[LoIdx] = Idx;
11452 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11453 MaskPtr[HiIdx] = Idx;
11458 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11459 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11460 int MaskOps[] = { -1, -1, -1, -1 };
11461 for (unsigned i = 0; i != 4; ++i)
11462 if (Locs[i].first != -1)
11463 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11464 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11467 static bool MayFoldVectorLoad(SDValue V) {
11468 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11469 V = V.getOperand(0);
11471 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11472 V = V.getOperand(0);
11473 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11474 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11475 // BUILD_VECTOR (load), undef
11476 V = V.getOperand(0);
11478 return MayFoldLoad(V);
11482 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11483 MVT VT = Op.getSimpleValueType();
11485 // Canonizalize to v2f64.
11486 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11487 return DAG.getNode(ISD::BITCAST, dl, VT,
11488 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11493 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11495 SDValue V1 = Op.getOperand(0);
11496 SDValue V2 = Op.getOperand(1);
11497 MVT VT = Op.getSimpleValueType();
11499 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11501 if (HasSSE2 && VT == MVT::v2f64)
11502 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11504 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11505 return DAG.getNode(ISD::BITCAST, dl, VT,
11506 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11507 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11508 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11512 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11513 SDValue V1 = Op.getOperand(0);
11514 SDValue V2 = Op.getOperand(1);
11515 MVT VT = Op.getSimpleValueType();
11517 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11518 "unsupported shuffle type");
11520 if (V2.getOpcode() == ISD::UNDEF)
11524 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11528 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11529 SDValue V1 = Op.getOperand(0);
11530 SDValue V2 = Op.getOperand(1);
11531 MVT VT = Op.getSimpleValueType();
11532 unsigned NumElems = VT.getVectorNumElements();
11534 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11535 // operand of these instructions is only memory, so check if there's a
11536 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11538 bool CanFoldLoad = false;
11540 // Trivial case, when V2 comes from a load.
11541 if (MayFoldVectorLoad(V2))
11542 CanFoldLoad = true;
11544 // When V1 is a load, it can be folded later into a store in isel, example:
11545 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11547 // (MOVLPSmr addr:$src1, VR128:$src2)
11548 // So, recognize this potential and also use MOVLPS or MOVLPD
11549 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11550 CanFoldLoad = true;
11552 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11554 if (HasSSE2 && NumElems == 2)
11555 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11558 // If we don't care about the second element, proceed to use movss.
11559 if (SVOp->getMaskElt(1) != -1)
11560 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11563 // movl and movlp will both match v2i64, but v2i64 is never matched by
11564 // movl earlier because we make it strict to avoid messing with the movlp load
11565 // folding logic (see the code above getMOVLP call). Match it here then,
11566 // this is horrible, but will stay like this until we move all shuffle
11567 // matching to x86 specific nodes. Note that for the 1st condition all
11568 // types are matched with movsd.
11570 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11571 // as to remove this logic from here, as much as possible
11572 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11573 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11574 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11577 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11579 // Invert the operand order and use SHUFPS to match it.
11580 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11581 getShuffleSHUFImmediate(SVOp), DAG);
11584 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11585 SelectionDAG &DAG) {
11587 MVT VT = Load->getSimpleValueType(0);
11588 MVT EVT = VT.getVectorElementType();
11589 SDValue Addr = Load->getOperand(1);
11590 SDValue NewAddr = DAG.getNode(
11591 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11592 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11595 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11596 DAG.getMachineFunction().getMachineMemOperand(
11597 Load->getMemOperand(), 0, EVT.getStoreSize()));
11601 // It is only safe to call this function if isINSERTPSMask is true for
11602 // this shufflevector mask.
11603 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11604 SelectionDAG &DAG) {
11605 // Generate an insertps instruction when inserting an f32 from memory onto a
11606 // v4f32 or when copying a member from one v4f32 to another.
11607 // We also use it for transferring i32 from one register to another,
11608 // since it simply copies the same bits.
11609 // If we're transferring an i32 from memory to a specific element in a
11610 // register, we output a generic DAG that will match the PINSRD
11612 MVT VT = SVOp->getSimpleValueType(0);
11613 MVT EVT = VT.getVectorElementType();
11614 SDValue V1 = SVOp->getOperand(0);
11615 SDValue V2 = SVOp->getOperand(1);
11616 auto Mask = SVOp->getMask();
11617 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11618 "unsupported vector type for insertps/pinsrd");
11620 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11621 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11622 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11626 unsigned DestIndex;
11630 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11633 // If we have 1 element from each vector, we have to check if we're
11634 // changing V1's element's place. If so, we're done. Otherwise, we
11635 // should assume we're changing V2's element's place and behave
11637 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11638 assert(DestIndex <= INT32_MAX && "truncated destination index");
11639 if (FromV1 == FromV2 &&
11640 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11644 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11647 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11648 "More than one element from V1 and from V2, or no elements from one "
11649 "of the vectors. This case should not have returned true from "
11654 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11657 // Get an index into the source vector in the range [0,4) (the mask is
11658 // in the range [0,8) because it can address V1 and V2)
11659 unsigned SrcIndex = Mask[DestIndex] % 4;
11660 if (MayFoldLoad(From)) {
11661 // Trivial case, when From comes from a load and is only used by the
11662 // shuffle. Make it use insertps from the vector that we need from that
11665 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11666 if (!NewLoad.getNode())
11669 if (EVT == MVT::f32) {
11670 // Create this as a scalar to vector to match the instruction pattern.
11671 SDValue LoadScalarToVector =
11672 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11673 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11674 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11676 } else { // EVT == MVT::i32
11677 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11678 // instruction, to match the PINSRD instruction, which loads an i32 to a
11679 // certain vector element.
11680 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11681 DAG.getConstant(DestIndex, MVT::i32));
11685 // Vector-element-to-vector
11686 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11687 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11690 // Reduce a vector shuffle to zext.
11691 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11692 SelectionDAG &DAG) {
11693 // PMOVZX is only available from SSE41.
11694 if (!Subtarget->hasSSE41())
11697 MVT VT = Op.getSimpleValueType();
11699 // Only AVX2 support 256-bit vector integer extending.
11700 if (!Subtarget->hasInt256() && VT.is256BitVector())
11703 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11705 SDValue V1 = Op.getOperand(0);
11706 SDValue V2 = Op.getOperand(1);
11707 unsigned NumElems = VT.getVectorNumElements();
11709 // Extending is an unary operation and the element type of the source vector
11710 // won't be equal to or larger than i64.
11711 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11712 VT.getVectorElementType() == MVT::i64)
11715 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11716 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11717 while ((1U << Shift) < NumElems) {
11718 if (SVOp->getMaskElt(1U << Shift) == 1)
11721 // The maximal ratio is 8, i.e. from i8 to i64.
11726 // Check the shuffle mask.
11727 unsigned Mask = (1U << Shift) - 1;
11728 for (unsigned i = 0; i != NumElems; ++i) {
11729 int EltIdx = SVOp->getMaskElt(i);
11730 if ((i & Mask) != 0 && EltIdx != -1)
11732 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11736 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11737 MVT NeVT = MVT::getIntegerVT(NBits);
11738 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11740 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11743 return DAG.getNode(ISD::BITCAST, DL, VT,
11744 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11747 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11748 SelectionDAG &DAG) {
11749 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11750 MVT VT = Op.getSimpleValueType();
11752 SDValue V1 = Op.getOperand(0);
11753 SDValue V2 = Op.getOperand(1);
11755 if (isZeroShuffle(SVOp))
11756 return getZeroVector(VT, Subtarget, DAG, dl);
11758 // Handle splat operations
11759 if (SVOp->isSplat()) {
11760 // Use vbroadcast whenever the splat comes from a foldable load
11761 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11762 if (Broadcast.getNode())
11766 // Check integer expanding shuffles.
11767 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11768 if (NewOp.getNode())
11771 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11773 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11774 VT == MVT::v32i8) {
11775 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11776 if (NewOp.getNode())
11777 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11778 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11779 // FIXME: Figure out a cleaner way to do this.
11780 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11781 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11782 if (NewOp.getNode()) {
11783 MVT NewVT = NewOp.getSimpleValueType();
11784 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11785 NewVT, true, false))
11786 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11789 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11790 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11791 if (NewOp.getNode()) {
11792 MVT NewVT = NewOp.getSimpleValueType();
11793 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11794 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11803 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11804 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11805 SDValue V1 = Op.getOperand(0);
11806 SDValue V2 = Op.getOperand(1);
11807 MVT VT = Op.getSimpleValueType();
11809 unsigned NumElems = VT.getVectorNumElements();
11810 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11811 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11812 bool V1IsSplat = false;
11813 bool V2IsSplat = false;
11814 bool HasSSE2 = Subtarget->hasSSE2();
11815 bool HasFp256 = Subtarget->hasFp256();
11816 bool HasInt256 = Subtarget->hasInt256();
11817 MachineFunction &MF = DAG.getMachineFunction();
11818 bool OptForSize = MF.getFunction()->getAttributes().
11819 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11821 // Check if we should use the experimental vector shuffle lowering. If so,
11822 // delegate completely to that code path.
11823 if (ExperimentalVectorShuffleLowering)
11824 return lowerVectorShuffle(Op, Subtarget, DAG);
11826 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11828 if (V1IsUndef && V2IsUndef)
11829 return DAG.getUNDEF(VT);
11831 // When we create a shuffle node we put the UNDEF node to second operand,
11832 // but in some cases the first operand may be transformed to UNDEF.
11833 // In this case we should just commute the node.
11835 return DAG.getCommutedVectorShuffle(*SVOp);
11837 // Vector shuffle lowering takes 3 steps:
11839 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11840 // narrowing and commutation of operands should be handled.
11841 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11843 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11844 // so the shuffle can be broken into other shuffles and the legalizer can
11845 // try the lowering again.
11847 // The general idea is that no vector_shuffle operation should be left to
11848 // be matched during isel, all of them must be converted to a target specific
11851 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11852 // narrowing and commutation of operands should be handled. The actual code
11853 // doesn't include all of those, work in progress...
11854 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11855 if (NewOp.getNode())
11858 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11860 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11861 // unpckh_undef). Only use pshufd if speed is more important than size.
11862 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11863 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11864 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11865 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11867 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11868 V2IsUndef && MayFoldVectorLoad(V1))
11869 return getMOVDDup(Op, dl, V1, DAG);
11871 if (isMOVHLPS_v_undef_Mask(M, VT))
11872 return getMOVHighToLow(Op, dl, DAG);
11874 // Use to match splats
11875 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11876 (VT == MVT::v2f64 || VT == MVT::v2i64))
11877 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11879 if (isPSHUFDMask(M, VT)) {
11880 // The actual implementation will match the mask in the if above and then
11881 // during isel it can match several different instructions, not only pshufd
11882 // as its name says, sad but true, emulate the behavior for now...
11883 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11884 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11886 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11888 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11889 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11891 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11892 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11895 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11899 if (isPALIGNRMask(M, VT, Subtarget))
11900 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11901 getShufflePALIGNRImmediate(SVOp),
11904 if (isVALIGNMask(M, VT, Subtarget))
11905 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11906 getShuffleVALIGNImmediate(SVOp),
11909 // Check if this can be converted into a logical shift.
11910 bool isLeft = false;
11911 unsigned ShAmt = 0;
11913 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11914 if (isShift && ShVal.hasOneUse()) {
11915 // If the shifted value has multiple uses, it may be cheaper to use
11916 // v_set0 + movlhps or movhlps, etc.
11917 MVT EltVT = VT.getVectorElementType();
11918 ShAmt *= EltVT.getSizeInBits();
11919 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11922 if (isMOVLMask(M, VT)) {
11923 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11924 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11925 if (!isMOVLPMask(M, VT)) {
11926 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11927 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11929 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11930 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11934 // FIXME: fold these into legal mask.
11935 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11936 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11938 if (isMOVHLPSMask(M, VT))
11939 return getMOVHighToLow(Op, dl, DAG);
11941 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11942 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11944 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11945 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11947 if (isMOVLPMask(M, VT))
11948 return getMOVLP(Op, dl, DAG, HasSSE2);
11950 if (ShouldXformToMOVHLPS(M, VT) ||
11951 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11952 return DAG.getCommutedVectorShuffle(*SVOp);
11955 // No better options. Use a vshldq / vsrldq.
11956 MVT EltVT = VT.getVectorElementType();
11957 ShAmt *= EltVT.getSizeInBits();
11958 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11961 bool Commuted = false;
11962 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11963 // 1,1,1,1 -> v8i16 though.
11964 BitVector UndefElements;
11965 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11966 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11968 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11969 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11972 // Canonicalize the splat or undef, if present, to be on the RHS.
11973 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11974 CommuteVectorShuffleMask(M, NumElems);
11976 std::swap(V1IsSplat, V2IsSplat);
11980 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11981 // Shuffling low element of v1 into undef, just return v1.
11984 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11985 // the instruction selector will not match, so get a canonical MOVL with
11986 // swapped operands to undo the commute.
11987 return getMOVL(DAG, dl, VT, V2, V1);
11990 if (isUNPCKLMask(M, VT, HasInt256))
11991 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11993 if (isUNPCKHMask(M, VT, HasInt256))
11994 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11997 // Normalize mask so all entries that point to V2 points to its first
11998 // element then try to match unpck{h|l} again. If match, return a
11999 // new vector_shuffle with the corrected mask.p
12000 SmallVector<int, 8> NewMask(M.begin(), M.end());
12001 NormalizeMask(NewMask, NumElems);
12002 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12003 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12004 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12005 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12009 // Commute is back and try unpck* again.
12010 // FIXME: this seems wrong.
12011 CommuteVectorShuffleMask(M, NumElems);
12013 std::swap(V1IsSplat, V2IsSplat);
12015 if (isUNPCKLMask(M, VT, HasInt256))
12016 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12018 if (isUNPCKHMask(M, VT, HasInt256))
12019 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12022 // Normalize the node to match x86 shuffle ops if needed
12023 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12024 return DAG.getCommutedVectorShuffle(*SVOp);
12026 // The checks below are all present in isShuffleMaskLegal, but they are
12027 // inlined here right now to enable us to directly emit target specific
12028 // nodes, and remove one by one until they don't return Op anymore.
12030 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12031 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12032 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12033 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12036 if (isPSHUFHWMask(M, VT, HasInt256))
12037 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12038 getShufflePSHUFHWImmediate(SVOp),
12041 if (isPSHUFLWMask(M, VT, HasInt256))
12042 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12043 getShufflePSHUFLWImmediate(SVOp),
12046 unsigned MaskValue;
12047 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12049 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12051 if (isSHUFPMask(M, VT))
12052 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12053 getShuffleSHUFImmediate(SVOp), DAG);
12055 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12056 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12057 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12058 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12060 //===--------------------------------------------------------------------===//
12061 // Generate target specific nodes for 128 or 256-bit shuffles only
12062 // supported in the AVX instruction set.
12065 // Handle VMOVDDUPY permutations
12066 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12067 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12069 // Handle VPERMILPS/D* permutations
12070 if (isVPERMILPMask(M, VT)) {
12071 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12072 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12073 getShuffleSHUFImmediate(SVOp), DAG);
12074 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12075 getShuffleSHUFImmediate(SVOp), DAG);
12079 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12080 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12081 Idx*(NumElems/2), DAG, dl);
12083 // Handle VPERM2F128/VPERM2I128 permutations
12084 if (isVPERM2X128Mask(M, VT, HasFp256))
12085 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12086 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12088 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12089 return getINSERTPS(SVOp, dl, DAG);
12092 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12093 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12095 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12096 VT.is512BitVector()) {
12097 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12098 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12099 SmallVector<SDValue, 16> permclMask;
12100 for (unsigned i = 0; i != NumElems; ++i) {
12101 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12104 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12106 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12107 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12108 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12109 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12110 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12113 //===--------------------------------------------------------------------===//
12114 // Since no target specific shuffle was selected for this generic one,
12115 // lower it into other known shuffles. FIXME: this isn't true yet, but
12116 // this is the plan.
12119 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12120 if (VT == MVT::v8i16) {
12121 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12122 if (NewOp.getNode())
12126 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12127 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12128 if (NewOp.getNode())
12132 if (VT == MVT::v16i8) {
12133 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12134 if (NewOp.getNode())
12138 if (VT == MVT::v32i8) {
12139 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12140 if (NewOp.getNode())
12144 // Handle all 128-bit wide vectors with 4 elements, and match them with
12145 // several different shuffle types.
12146 if (NumElems == 4 && VT.is128BitVector())
12147 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12149 // Handle general 256-bit shuffles
12150 if (VT.is256BitVector())
12151 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12156 // This function assumes its argument is a BUILD_VECTOR of constants or
12157 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12159 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12160 unsigned &MaskValue) {
12162 unsigned NumElems = BuildVector->getNumOperands();
12163 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12164 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12165 unsigned NumElemsInLane = NumElems / NumLanes;
12167 // Blend for v16i16 should be symetric for the both lanes.
12168 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12169 SDValue EltCond = BuildVector->getOperand(i);
12170 SDValue SndLaneEltCond =
12171 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12173 int Lane1Cond = -1, Lane2Cond = -1;
12174 if (isa<ConstantSDNode>(EltCond))
12175 Lane1Cond = !isZero(EltCond);
12176 if (isa<ConstantSDNode>(SndLaneEltCond))
12177 Lane2Cond = !isZero(SndLaneEltCond);
12179 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12180 // Lane1Cond != 0, means we want the first argument.
12181 // Lane1Cond == 0, means we want the second argument.
12182 // The encoding of this argument is 0 for the first argument, 1
12183 // for the second. Therefore, invert the condition.
12184 MaskValue |= !Lane1Cond << i;
12185 else if (Lane1Cond < 0)
12186 MaskValue |= !Lane2Cond << i;
12193 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12195 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12196 SelectionDAG &DAG) {
12197 SDValue Cond = Op.getOperand(0);
12198 SDValue LHS = Op.getOperand(1);
12199 SDValue RHS = Op.getOperand(2);
12201 MVT VT = Op.getSimpleValueType();
12202 MVT EltVT = VT.getVectorElementType();
12203 unsigned NumElems = VT.getVectorNumElements();
12205 // There is no blend with immediate in AVX-512.
12206 if (VT.is512BitVector())
12209 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12211 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12214 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12217 // Check the mask for BLEND and build the value.
12218 unsigned MaskValue = 0;
12219 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12222 // Convert i32 vectors to floating point if it is not AVX2.
12223 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12225 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12226 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12228 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12229 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12232 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12233 DAG.getConstant(MaskValue, MVT::i32));
12234 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12237 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12238 // A vselect where all conditions and data are constants can be optimized into
12239 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12240 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12241 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12242 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12245 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12246 if (BlendOp.getNode())
12249 // Some types for vselect were previously set to Expand, not Legal or
12250 // Custom. Return an empty SDValue so we fall-through to Expand, after
12251 // the Custom lowering phase.
12252 MVT VT = Op.getSimpleValueType();
12253 switch (VT.SimpleTy) {
12258 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12263 // We couldn't create a "Blend with immediate" node.
12264 // This node should still be legal, but we'll have to emit a blendv*
12269 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12270 MVT VT = Op.getSimpleValueType();
12273 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12276 if (VT.getSizeInBits() == 8) {
12277 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12278 Op.getOperand(0), Op.getOperand(1));
12279 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12280 DAG.getValueType(VT));
12281 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12284 if (VT.getSizeInBits() == 16) {
12285 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12286 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12288 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12289 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12290 DAG.getNode(ISD::BITCAST, dl,
12293 Op.getOperand(1)));
12294 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12295 Op.getOperand(0), Op.getOperand(1));
12296 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12297 DAG.getValueType(VT));
12298 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12301 if (VT == MVT::f32) {
12302 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12303 // the result back to FR32 register. It's only worth matching if the
12304 // result has a single use which is a store or a bitcast to i32. And in
12305 // the case of a store, it's not worth it if the index is a constant 0,
12306 // because a MOVSSmr can be used instead, which is smaller and faster.
12307 if (!Op.hasOneUse())
12309 SDNode *User = *Op.getNode()->use_begin();
12310 if ((User->getOpcode() != ISD::STORE ||
12311 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12312 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12313 (User->getOpcode() != ISD::BITCAST ||
12314 User->getValueType(0) != MVT::i32))
12316 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12317 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12320 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12323 if (VT == MVT::i32 || VT == MVT::i64) {
12324 // ExtractPS/pextrq works with constant index.
12325 if (isa<ConstantSDNode>(Op.getOperand(1)))
12331 /// Extract one bit from mask vector, like v16i1 or v8i1.
12332 /// AVX-512 feature.
12334 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12335 SDValue Vec = Op.getOperand(0);
12337 MVT VecVT = Vec.getSimpleValueType();
12338 SDValue Idx = Op.getOperand(1);
12339 MVT EltVT = Op.getSimpleValueType();
12341 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12343 // variable index can't be handled in mask registers,
12344 // extend vector to VR512
12345 if (!isa<ConstantSDNode>(Idx)) {
12346 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12347 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12348 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12349 ExtVT.getVectorElementType(), Ext, Idx);
12350 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12353 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12354 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12355 unsigned MaxSift = rc->getSize()*8 - 1;
12356 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12357 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12358 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12359 DAG.getConstant(MaxSift, MVT::i8));
12360 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12361 DAG.getIntPtrConstant(0));
12365 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12366 SelectionDAG &DAG) const {
12368 SDValue Vec = Op.getOperand(0);
12369 MVT VecVT = Vec.getSimpleValueType();
12370 SDValue Idx = Op.getOperand(1);
12372 if (Op.getSimpleValueType() == MVT::i1)
12373 return ExtractBitFromMaskVector(Op, DAG);
12375 if (!isa<ConstantSDNode>(Idx)) {
12376 if (VecVT.is512BitVector() ||
12377 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12378 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12381 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12382 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12383 MaskEltVT.getSizeInBits());
12385 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12386 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12387 getZeroVector(MaskVT, Subtarget, DAG, dl),
12388 Idx, DAG.getConstant(0, getPointerTy()));
12389 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12390 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12391 Perm, DAG.getConstant(0, getPointerTy()));
12396 // If this is a 256-bit vector result, first extract the 128-bit vector and
12397 // then extract the element from the 128-bit vector.
12398 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12400 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12401 // Get the 128-bit vector.
12402 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12403 MVT EltVT = VecVT.getVectorElementType();
12405 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12407 //if (IdxVal >= NumElems/2)
12408 // IdxVal -= NumElems/2;
12409 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12410 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12411 DAG.getConstant(IdxVal, MVT::i32));
12414 assert(VecVT.is128BitVector() && "Unexpected vector length");
12416 if (Subtarget->hasSSE41()) {
12417 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12422 MVT VT = Op.getSimpleValueType();
12423 // TODO: handle v16i8.
12424 if (VT.getSizeInBits() == 16) {
12425 SDValue Vec = Op.getOperand(0);
12426 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12428 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12429 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12430 DAG.getNode(ISD::BITCAST, dl,
12432 Op.getOperand(1)));
12433 // Transform it so it match pextrw which produces a 32-bit result.
12434 MVT EltVT = MVT::i32;
12435 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12436 Op.getOperand(0), Op.getOperand(1));
12437 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12438 DAG.getValueType(VT));
12439 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12442 if (VT.getSizeInBits() == 32) {
12443 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12447 // SHUFPS the element to the lowest double word, then movss.
12448 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12449 MVT VVT = Op.getOperand(0).getSimpleValueType();
12450 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12451 DAG.getUNDEF(VVT), Mask);
12452 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12453 DAG.getIntPtrConstant(0));
12456 if (VT.getSizeInBits() == 64) {
12457 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12458 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12459 // to match extract_elt for f64.
12460 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12464 // UNPCKHPD the element to the lowest double word, then movsd.
12465 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12466 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12467 int Mask[2] = { 1, -1 };
12468 MVT VVT = Op.getOperand(0).getSimpleValueType();
12469 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12470 DAG.getUNDEF(VVT), Mask);
12471 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12472 DAG.getIntPtrConstant(0));
12478 /// Insert one bit to mask vector, like v16i1 or v8i1.
12479 /// AVX-512 feature.
12481 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12483 SDValue Vec = Op.getOperand(0);
12484 SDValue Elt = Op.getOperand(1);
12485 SDValue Idx = Op.getOperand(2);
12486 MVT VecVT = Vec.getSimpleValueType();
12488 if (!isa<ConstantSDNode>(Idx)) {
12489 // Non constant index. Extend source and destination,
12490 // insert element and then truncate the result.
12491 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12492 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12493 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12494 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12495 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12496 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12499 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12500 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12501 if (Vec.getOpcode() == ISD::UNDEF)
12502 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12503 DAG.getConstant(IdxVal, MVT::i8));
12504 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12505 unsigned MaxSift = rc->getSize()*8 - 1;
12506 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12507 DAG.getConstant(MaxSift, MVT::i8));
12508 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12509 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12510 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12513 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12514 SelectionDAG &DAG) const {
12515 MVT VT = Op.getSimpleValueType();
12516 MVT EltVT = VT.getVectorElementType();
12518 if (EltVT == MVT::i1)
12519 return InsertBitToMaskVector(Op, DAG);
12522 SDValue N0 = Op.getOperand(0);
12523 SDValue N1 = Op.getOperand(1);
12524 SDValue N2 = Op.getOperand(2);
12525 if (!isa<ConstantSDNode>(N2))
12527 auto *N2C = cast<ConstantSDNode>(N2);
12528 unsigned IdxVal = N2C->getZExtValue();
12530 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12531 // into that, and then insert the subvector back into the result.
12532 if (VT.is256BitVector() || VT.is512BitVector()) {
12533 // Get the desired 128-bit vector half.
12534 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12536 // Insert the element into the desired half.
12537 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12538 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12540 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12541 DAG.getConstant(IdxIn128, MVT::i32));
12543 // Insert the changed part back to the 256-bit vector
12544 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12546 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12548 if (Subtarget->hasSSE41()) {
12549 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12551 if (VT == MVT::v8i16) {
12552 Opc = X86ISD::PINSRW;
12554 assert(VT == MVT::v16i8);
12555 Opc = X86ISD::PINSRB;
12558 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12560 if (N1.getValueType() != MVT::i32)
12561 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12562 if (N2.getValueType() != MVT::i32)
12563 N2 = DAG.getIntPtrConstant(IdxVal);
12564 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12567 if (EltVT == MVT::f32) {
12568 // Bits [7:6] of the constant are the source select. This will always be
12569 // zero here. The DAG Combiner may combine an extract_elt index into
12571 // bits. For example (insert (extract, 3), 2) could be matched by
12573 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12574 // Bits [5:4] of the constant are the destination select. This is the
12575 // value of the incoming immediate.
12576 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12577 // combine either bitwise AND or insert of float 0.0 to set these bits.
12578 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12579 // Create this as a scalar to vector..
12580 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12581 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12584 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12585 // PINSR* works with constant index.
12590 if (EltVT == MVT::i8)
12593 if (EltVT.getSizeInBits() == 16) {
12594 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12595 // as its second argument.
12596 if (N1.getValueType() != MVT::i32)
12597 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12598 if (N2.getValueType() != MVT::i32)
12599 N2 = DAG.getIntPtrConstant(IdxVal);
12600 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12605 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12607 MVT OpVT = Op.getSimpleValueType();
12609 // If this is a 256-bit vector result, first insert into a 128-bit
12610 // vector and then insert into the 256-bit vector.
12611 if (!OpVT.is128BitVector()) {
12612 // Insert into a 128-bit vector.
12613 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12614 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12615 OpVT.getVectorNumElements() / SizeFactor);
12617 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12619 // Insert the 128-bit vector.
12620 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12623 if (OpVT == MVT::v1i64 &&
12624 Op.getOperand(0).getValueType() == MVT::i64)
12625 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12627 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12628 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12629 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12630 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12633 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12634 // a simple subregister reference or explicit instructions to grab
12635 // upper bits of a vector.
12636 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12637 SelectionDAG &DAG) {
12639 SDValue In = Op.getOperand(0);
12640 SDValue Idx = Op.getOperand(1);
12641 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12642 MVT ResVT = Op.getSimpleValueType();
12643 MVT InVT = In.getSimpleValueType();
12645 if (Subtarget->hasFp256()) {
12646 if (ResVT.is128BitVector() &&
12647 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12648 isa<ConstantSDNode>(Idx)) {
12649 return Extract128BitVector(In, IdxVal, DAG, dl);
12651 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12652 isa<ConstantSDNode>(Idx)) {
12653 return Extract256BitVector(In, IdxVal, DAG, dl);
12659 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12660 // simple superregister reference or explicit instructions to insert
12661 // the upper bits of a vector.
12662 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12663 SelectionDAG &DAG) {
12664 if (Subtarget->hasFp256()) {
12665 SDLoc dl(Op.getNode());
12666 SDValue Vec = Op.getNode()->getOperand(0);
12667 SDValue SubVec = Op.getNode()->getOperand(1);
12668 SDValue Idx = Op.getNode()->getOperand(2);
12670 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12671 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12672 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12673 isa<ConstantSDNode>(Idx)) {
12674 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12675 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12678 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12679 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12680 isa<ConstantSDNode>(Idx)) {
12681 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12682 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12688 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12689 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12690 // one of the above mentioned nodes. It has to be wrapped because otherwise
12691 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12692 // be used to form addressing mode. These wrapped nodes will be selected
12695 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12696 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12698 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12699 // global base reg.
12700 unsigned char OpFlag = 0;
12701 unsigned WrapperKind = X86ISD::Wrapper;
12702 CodeModel::Model M = DAG.getTarget().getCodeModel();
12704 if (Subtarget->isPICStyleRIPRel() &&
12705 (M == CodeModel::Small || M == CodeModel::Kernel))
12706 WrapperKind = X86ISD::WrapperRIP;
12707 else if (Subtarget->isPICStyleGOT())
12708 OpFlag = X86II::MO_GOTOFF;
12709 else if (Subtarget->isPICStyleStubPIC())
12710 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12712 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12713 CP->getAlignment(),
12714 CP->getOffset(), OpFlag);
12716 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12717 // With PIC, the address is actually $g + Offset.
12719 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12720 DAG.getNode(X86ISD::GlobalBaseReg,
12721 SDLoc(), getPointerTy()),
12728 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12729 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12731 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12732 // global base reg.
12733 unsigned char OpFlag = 0;
12734 unsigned WrapperKind = X86ISD::Wrapper;
12735 CodeModel::Model M = DAG.getTarget().getCodeModel();
12737 if (Subtarget->isPICStyleRIPRel() &&
12738 (M == CodeModel::Small || M == CodeModel::Kernel))
12739 WrapperKind = X86ISD::WrapperRIP;
12740 else if (Subtarget->isPICStyleGOT())
12741 OpFlag = X86II::MO_GOTOFF;
12742 else if (Subtarget->isPICStyleStubPIC())
12743 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12745 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12748 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12750 // With PIC, the address is actually $g + Offset.
12752 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12753 DAG.getNode(X86ISD::GlobalBaseReg,
12754 SDLoc(), getPointerTy()),
12761 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12762 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12764 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12765 // global base reg.
12766 unsigned char OpFlag = 0;
12767 unsigned WrapperKind = X86ISD::Wrapper;
12768 CodeModel::Model M = DAG.getTarget().getCodeModel();
12770 if (Subtarget->isPICStyleRIPRel() &&
12771 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12772 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12773 OpFlag = X86II::MO_GOTPCREL;
12774 WrapperKind = X86ISD::WrapperRIP;
12775 } else if (Subtarget->isPICStyleGOT()) {
12776 OpFlag = X86II::MO_GOT;
12777 } else if (Subtarget->isPICStyleStubPIC()) {
12778 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12779 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12780 OpFlag = X86II::MO_DARWIN_NONLAZY;
12783 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12786 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12788 // With PIC, the address is actually $g + Offset.
12789 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12790 !Subtarget->is64Bit()) {
12791 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12792 DAG.getNode(X86ISD::GlobalBaseReg,
12793 SDLoc(), getPointerTy()),
12797 // For symbols that require a load from a stub to get the address, emit the
12799 if (isGlobalStubReference(OpFlag))
12800 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12801 MachinePointerInfo::getGOT(), false, false, false, 0);
12807 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12808 // Create the TargetBlockAddressAddress node.
12809 unsigned char OpFlags =
12810 Subtarget->ClassifyBlockAddressReference();
12811 CodeModel::Model M = DAG.getTarget().getCodeModel();
12812 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12813 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12815 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12818 if (Subtarget->isPICStyleRIPRel() &&
12819 (M == CodeModel::Small || M == CodeModel::Kernel))
12820 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12822 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12824 // With PIC, the address is actually $g + Offset.
12825 if (isGlobalRelativeToPICBase(OpFlags)) {
12826 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12827 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12835 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12836 int64_t Offset, SelectionDAG &DAG) const {
12837 // Create the TargetGlobalAddress node, folding in the constant
12838 // offset if it is legal.
12839 unsigned char OpFlags =
12840 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12841 CodeModel::Model M = DAG.getTarget().getCodeModel();
12843 if (OpFlags == X86II::MO_NO_FLAG &&
12844 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12845 // A direct static reference to a global.
12846 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12849 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12852 if (Subtarget->isPICStyleRIPRel() &&
12853 (M == CodeModel::Small || M == CodeModel::Kernel))
12854 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12856 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12858 // With PIC, the address is actually $g + Offset.
12859 if (isGlobalRelativeToPICBase(OpFlags)) {
12860 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12861 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12865 // For globals that require a load from a stub to get the address, emit the
12867 if (isGlobalStubReference(OpFlags))
12868 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12869 MachinePointerInfo::getGOT(), false, false, false, 0);
12871 // If there was a non-zero offset that we didn't fold, create an explicit
12872 // addition for it.
12874 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12875 DAG.getConstant(Offset, getPointerTy()));
12881 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12882 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12883 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12884 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12888 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12889 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12890 unsigned char OperandFlags, bool LocalDynamic = false) {
12891 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12892 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12894 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12895 GA->getValueType(0),
12899 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12903 SDValue Ops[] = { Chain, TGA, *InFlag };
12904 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12906 SDValue Ops[] = { Chain, TGA };
12907 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12910 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12911 MFI->setAdjustsStack(true);
12912 MFI->setHasCalls(true);
12914 SDValue Flag = Chain.getValue(1);
12915 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12918 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12920 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12923 SDLoc dl(GA); // ? function entry point might be better
12924 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12925 DAG.getNode(X86ISD::GlobalBaseReg,
12926 SDLoc(), PtrVT), InFlag);
12927 InFlag = Chain.getValue(1);
12929 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12932 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12934 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12936 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12937 X86::RAX, X86II::MO_TLSGD);
12940 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12946 // Get the start address of the TLS block for this module.
12947 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12948 .getInfo<X86MachineFunctionInfo>();
12949 MFI->incNumLocalDynamicTLSAccesses();
12953 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12954 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12957 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12958 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12959 InFlag = Chain.getValue(1);
12960 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12961 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12964 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12968 unsigned char OperandFlags = X86II::MO_DTPOFF;
12969 unsigned WrapperKind = X86ISD::Wrapper;
12970 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12971 GA->getValueType(0),
12972 GA->getOffset(), OperandFlags);
12973 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12975 // Add x@dtpoff with the base.
12976 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12979 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12980 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12981 const EVT PtrVT, TLSModel::Model model,
12982 bool is64Bit, bool isPIC) {
12985 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12986 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12987 is64Bit ? 257 : 256));
12989 SDValue ThreadPointer =
12990 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12991 MachinePointerInfo(Ptr), false, false, false, 0);
12993 unsigned char OperandFlags = 0;
12994 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12996 unsigned WrapperKind = X86ISD::Wrapper;
12997 if (model == TLSModel::LocalExec) {
12998 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12999 } else if (model == TLSModel::InitialExec) {
13001 OperandFlags = X86II::MO_GOTTPOFF;
13002 WrapperKind = X86ISD::WrapperRIP;
13004 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13007 llvm_unreachable("Unexpected model");
13010 // emit "addl x@ntpoff,%eax" (local exec)
13011 // or "addl x@indntpoff,%eax" (initial exec)
13012 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13014 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13015 GA->getOffset(), OperandFlags);
13016 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13018 if (model == TLSModel::InitialExec) {
13019 if (isPIC && !is64Bit) {
13020 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13021 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13025 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13026 MachinePointerInfo::getGOT(), false, false, false, 0);
13029 // The address of the thread local variable is the add of the thread
13030 // pointer with the offset of the variable.
13031 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13035 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13037 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13038 const GlobalValue *GV = GA->getGlobal();
13040 if (Subtarget->isTargetELF()) {
13041 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13044 case TLSModel::GeneralDynamic:
13045 if (Subtarget->is64Bit())
13046 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13047 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13048 case TLSModel::LocalDynamic:
13049 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13050 Subtarget->is64Bit());
13051 case TLSModel::InitialExec:
13052 case TLSModel::LocalExec:
13053 return LowerToTLSExecModel(
13054 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13055 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13057 llvm_unreachable("Unknown TLS model.");
13060 if (Subtarget->isTargetDarwin()) {
13061 // Darwin only has one model of TLS. Lower to that.
13062 unsigned char OpFlag = 0;
13063 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13064 X86ISD::WrapperRIP : X86ISD::Wrapper;
13066 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13067 // global base reg.
13068 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13069 !Subtarget->is64Bit();
13071 OpFlag = X86II::MO_TLVP_PIC_BASE;
13073 OpFlag = X86II::MO_TLVP;
13075 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13076 GA->getValueType(0),
13077 GA->getOffset(), OpFlag);
13078 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13080 // With PIC32, the address is actually $g + Offset.
13082 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13083 DAG.getNode(X86ISD::GlobalBaseReg,
13084 SDLoc(), getPointerTy()),
13087 // Lowering the machine isd will make sure everything is in the right
13089 SDValue Chain = DAG.getEntryNode();
13090 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13091 SDValue Args[] = { Chain, Offset };
13092 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13094 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13095 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13096 MFI->setAdjustsStack(true);
13098 // And our return value (tls address) is in the standard call return value
13100 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13101 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13102 Chain.getValue(1));
13105 if (Subtarget->isTargetKnownWindowsMSVC() ||
13106 Subtarget->isTargetWindowsGNU()) {
13107 // Just use the implicit TLS architecture
13108 // Need to generate someting similar to:
13109 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13111 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13112 // mov rcx, qword [rdx+rcx*8]
13113 // mov eax, .tls$:tlsvar
13114 // [rax+rcx] contains the address
13115 // Windows 64bit: gs:0x58
13116 // Windows 32bit: fs:__tls_array
13119 SDValue Chain = DAG.getEntryNode();
13121 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13122 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13123 // use its literal value of 0x2C.
13124 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13125 ? Type::getInt8PtrTy(*DAG.getContext(),
13127 : Type::getInt32PtrTy(*DAG.getContext(),
13131 Subtarget->is64Bit()
13132 ? DAG.getIntPtrConstant(0x58)
13133 : (Subtarget->isTargetWindowsGNU()
13134 ? DAG.getIntPtrConstant(0x2C)
13135 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13137 SDValue ThreadPointer =
13138 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13139 MachinePointerInfo(Ptr), false, false, false, 0);
13141 // Load the _tls_index variable
13142 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13143 if (Subtarget->is64Bit())
13144 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13145 IDX, MachinePointerInfo(), MVT::i32,
13146 false, false, false, 0);
13148 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13149 false, false, false, 0);
13151 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13153 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13155 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13156 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13157 false, false, false, 0);
13159 // Get the offset of start of .tls section
13160 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13161 GA->getValueType(0),
13162 GA->getOffset(), X86II::MO_SECREL);
13163 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13165 // The address of the thread local variable is the add of the thread
13166 // pointer with the offset of the variable.
13167 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13170 llvm_unreachable("TLS not implemented for this target.");
13173 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13174 /// and take a 2 x i32 value to shift plus a shift amount.
13175 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13176 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13177 MVT VT = Op.getSimpleValueType();
13178 unsigned VTBits = VT.getSizeInBits();
13180 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13181 SDValue ShOpLo = Op.getOperand(0);
13182 SDValue ShOpHi = Op.getOperand(1);
13183 SDValue ShAmt = Op.getOperand(2);
13184 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13185 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13187 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13188 DAG.getConstant(VTBits - 1, MVT::i8));
13189 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13190 DAG.getConstant(VTBits - 1, MVT::i8))
13191 : DAG.getConstant(0, VT);
13193 SDValue Tmp2, Tmp3;
13194 if (Op.getOpcode() == ISD::SHL_PARTS) {
13195 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13196 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13198 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13199 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13202 // If the shift amount is larger or equal than the width of a part we can't
13203 // rely on the results of shld/shrd. Insert a test and select the appropriate
13204 // values for large shift amounts.
13205 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13206 DAG.getConstant(VTBits, MVT::i8));
13207 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13208 AndNode, DAG.getConstant(0, MVT::i8));
13211 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13212 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13213 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13215 if (Op.getOpcode() == ISD::SHL_PARTS) {
13216 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13217 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13219 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13220 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13223 SDValue Ops[2] = { Lo, Hi };
13224 return DAG.getMergeValues(Ops, dl);
13227 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13228 SelectionDAG &DAG) const {
13229 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13231 if (SrcVT.isVector())
13234 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13235 "Unknown SINT_TO_FP to lower!");
13237 // These are really Legal; return the operand so the caller accepts it as
13239 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13241 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13242 Subtarget->is64Bit()) {
13247 unsigned Size = SrcVT.getSizeInBits()/8;
13248 MachineFunction &MF = DAG.getMachineFunction();
13249 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13250 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13251 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13253 MachinePointerInfo::getFixedStack(SSFI),
13255 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13258 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13260 SelectionDAG &DAG) const {
13264 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13266 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13268 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13270 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13272 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13273 MachineMemOperand *MMO;
13275 int SSFI = FI->getIndex();
13277 DAG.getMachineFunction()
13278 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13279 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13281 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13282 StackSlot = StackSlot.getOperand(1);
13284 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13285 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13287 Tys, Ops, SrcVT, MMO);
13290 Chain = Result.getValue(1);
13291 SDValue InFlag = Result.getValue(2);
13293 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13294 // shouldn't be necessary except that RFP cannot be live across
13295 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13296 MachineFunction &MF = DAG.getMachineFunction();
13297 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13298 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13299 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13300 Tys = DAG.getVTList(MVT::Other);
13302 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13304 MachineMemOperand *MMO =
13305 DAG.getMachineFunction()
13306 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13307 MachineMemOperand::MOStore, SSFISize, SSFISize);
13309 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13310 Ops, Op.getValueType(), MMO);
13311 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13312 MachinePointerInfo::getFixedStack(SSFI),
13313 false, false, false, 0);
13319 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13320 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13321 SelectionDAG &DAG) const {
13322 // This algorithm is not obvious. Here it is what we're trying to output:
13325 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13326 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13328 haddpd %xmm0, %xmm0
13330 pshufd $0x4e, %xmm0, %xmm1
13336 LLVMContext *Context = DAG.getContext();
13338 // Build some magic constants.
13339 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13340 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13341 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13343 SmallVector<Constant*,2> CV1;
13345 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13346 APInt(64, 0x4330000000000000ULL))));
13348 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13349 APInt(64, 0x4530000000000000ULL))));
13350 Constant *C1 = ConstantVector::get(CV1);
13351 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13353 // Load the 64-bit value into an XMM register.
13354 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13356 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13357 MachinePointerInfo::getConstantPool(),
13358 false, false, false, 16);
13359 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13360 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13363 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13364 MachinePointerInfo::getConstantPool(),
13365 false, false, false, 16);
13366 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13367 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13370 if (Subtarget->hasSSE3()) {
13371 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13372 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13374 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13375 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13377 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13378 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13382 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13383 DAG.getIntPtrConstant(0));
13386 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13387 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13388 SelectionDAG &DAG) const {
13390 // FP constant to bias correct the final result.
13391 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13394 // Load the 32-bit value into an XMM register.
13395 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13398 // Zero out the upper parts of the register.
13399 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13401 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13402 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13403 DAG.getIntPtrConstant(0));
13405 // Or the load with the bias.
13406 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13407 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13408 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13409 MVT::v2f64, Load)),
13410 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13411 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13412 MVT::v2f64, Bias)));
13413 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13414 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13415 DAG.getIntPtrConstant(0));
13417 // Subtract the bias.
13418 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13420 // Handle final rounding.
13421 EVT DestVT = Op.getValueType();
13423 if (DestVT.bitsLT(MVT::f64))
13424 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13425 DAG.getIntPtrConstant(0));
13426 if (DestVT.bitsGT(MVT::f64))
13427 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13429 // Handle final rounding.
13433 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13434 const X86Subtarget &Subtarget) {
13435 // The algorithm is the following:
13436 // #ifdef __SSE4_1__
13437 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13438 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13439 // (uint4) 0x53000000, 0xaa);
13441 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13442 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13444 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13445 // return (float4) lo + fhi;
13448 SDValue V = Op->getOperand(0);
13449 EVT VecIntVT = V.getValueType();
13450 bool Is128 = VecIntVT == MVT::v4i32;
13451 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13452 unsigned NumElts = VecIntVT.getVectorNumElements();
13453 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13454 "Unsupported custom type");
13455 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13457 // In the #idef/#else code, we have in common:
13458 // - The vector of constants:
13464 // Create the splat vector for 0x4b000000.
13465 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13466 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13467 CstLow, CstLow, CstLow, CstLow};
13468 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13469 makeArrayRef(&CstLowArray[0], NumElts));
13470 // Create the splat vector for 0x53000000.
13471 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13472 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13473 CstHigh, CstHigh, CstHigh, CstHigh};
13474 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13475 makeArrayRef(&CstHighArray[0], NumElts));
13477 // Create the right shift.
13478 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13479 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13480 CstShift, CstShift, CstShift, CstShift};
13481 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13482 makeArrayRef(&CstShiftArray[0], NumElts));
13483 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13486 if (Subtarget.hasSSE41()) {
13487 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13488 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13489 SDValue VecCstLowBitcast =
13490 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13491 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13492 // Low will be bitcasted right away, so do not bother bitcasting back to its
13494 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13495 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13496 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13497 // (uint4) 0x53000000, 0xaa);
13498 SDValue VecCstHighBitcast =
13499 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13500 SDValue VecShiftBitcast =
13501 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13502 // High will be bitcasted right away, so do not bother bitcasting back to
13503 // its original type.
13504 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13505 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13507 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13508 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13509 CstMask, CstMask, CstMask);
13510 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13511 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13512 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13514 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13515 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13518 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13519 SDValue CstFAdd = DAG.getConstantFP(
13520 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13521 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13522 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13523 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13524 makeArrayRef(&CstFAddArray[0], NumElts));
13526 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13527 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13529 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13530 // return (float4) lo + fhi;
13531 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13532 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13535 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13536 SelectionDAG &DAG) const {
13537 SDValue N0 = Op.getOperand(0);
13538 MVT SVT = N0.getSimpleValueType();
13541 switch (SVT.SimpleTy) {
13543 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13548 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13549 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13550 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13554 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13556 llvm_unreachable(nullptr);
13559 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13560 SelectionDAG &DAG) const {
13561 SDValue N0 = Op.getOperand(0);
13564 if (Op.getValueType().isVector())
13565 return lowerUINT_TO_FP_vec(Op, DAG);
13567 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13568 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13569 // the optimization here.
13570 if (DAG.SignBitIsZero(N0))
13571 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13573 MVT SrcVT = N0.getSimpleValueType();
13574 MVT DstVT = Op.getSimpleValueType();
13575 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13576 return LowerUINT_TO_FP_i64(Op, DAG);
13577 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13578 return LowerUINT_TO_FP_i32(Op, DAG);
13579 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13582 // Make a 64-bit buffer, and use it to build an FILD.
13583 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13584 if (SrcVT == MVT::i32) {
13585 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13586 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13587 getPointerTy(), StackSlot, WordOff);
13588 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13589 StackSlot, MachinePointerInfo(),
13591 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13592 OffsetSlot, MachinePointerInfo(),
13594 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13598 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13599 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13600 StackSlot, MachinePointerInfo(),
13602 // For i64 source, we need to add the appropriate power of 2 if the input
13603 // was negative. This is the same as the optimization in
13604 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13605 // we must be careful to do the computation in x87 extended precision, not
13606 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13607 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13608 MachineMemOperand *MMO =
13609 DAG.getMachineFunction()
13610 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13611 MachineMemOperand::MOLoad, 8, 8);
13613 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13614 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13615 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13618 APInt FF(32, 0x5F800000ULL);
13620 // Check whether the sign bit is set.
13621 SDValue SignSet = DAG.getSetCC(dl,
13622 getSetCCResultType(*DAG.getContext(), MVT::i64),
13623 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13626 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13627 SDValue FudgePtr = DAG.getConstantPool(
13628 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13631 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13632 SDValue Zero = DAG.getIntPtrConstant(0);
13633 SDValue Four = DAG.getIntPtrConstant(4);
13634 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13636 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13638 // Load the value out, extending it from f32 to f80.
13639 // FIXME: Avoid the extend by constructing the right constant pool?
13640 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13641 FudgePtr, MachinePointerInfo::getConstantPool(),
13642 MVT::f32, false, false, false, 4);
13643 // Extend everything to 80 bits to force it to be done on x87.
13644 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13645 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13648 std::pair<SDValue,SDValue>
13649 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13650 bool IsSigned, bool IsReplace) const {
13653 EVT DstTy = Op.getValueType();
13655 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13656 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13660 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13661 DstTy.getSimpleVT() >= MVT::i16 &&
13662 "Unknown FP_TO_INT to lower!");
13664 // These are really Legal.
13665 if (DstTy == MVT::i32 &&
13666 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13667 return std::make_pair(SDValue(), SDValue());
13668 if (Subtarget->is64Bit() &&
13669 DstTy == MVT::i64 &&
13670 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13671 return std::make_pair(SDValue(), SDValue());
13673 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13674 // stack slot, or into the FTOL runtime function.
13675 MachineFunction &MF = DAG.getMachineFunction();
13676 unsigned MemSize = DstTy.getSizeInBits()/8;
13677 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13678 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13681 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13682 Opc = X86ISD::WIN_FTOL;
13684 switch (DstTy.getSimpleVT().SimpleTy) {
13685 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13686 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13687 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13688 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13691 SDValue Chain = DAG.getEntryNode();
13692 SDValue Value = Op.getOperand(0);
13693 EVT TheVT = Op.getOperand(0).getValueType();
13694 // FIXME This causes a redundant load/store if the SSE-class value is already
13695 // in memory, such as if it is on the callstack.
13696 if (isScalarFPTypeInSSEReg(TheVT)) {
13697 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13698 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13699 MachinePointerInfo::getFixedStack(SSFI),
13701 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13703 Chain, StackSlot, DAG.getValueType(TheVT)
13706 MachineMemOperand *MMO =
13707 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13708 MachineMemOperand::MOLoad, MemSize, MemSize);
13709 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13710 Chain = Value.getValue(1);
13711 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13712 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13715 MachineMemOperand *MMO =
13716 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13717 MachineMemOperand::MOStore, MemSize, MemSize);
13719 if (Opc != X86ISD::WIN_FTOL) {
13720 // Build the FP_TO_INT*_IN_MEM
13721 SDValue Ops[] = { Chain, Value, StackSlot };
13722 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13724 return std::make_pair(FIST, StackSlot);
13726 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13727 DAG.getVTList(MVT::Other, MVT::Glue),
13729 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13730 MVT::i32, ftol.getValue(1));
13731 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13732 MVT::i32, eax.getValue(2));
13733 SDValue Ops[] = { eax, edx };
13734 SDValue pair = IsReplace
13735 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13736 : DAG.getMergeValues(Ops, DL);
13737 return std::make_pair(pair, SDValue());
13741 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13742 const X86Subtarget *Subtarget) {
13743 MVT VT = Op->getSimpleValueType(0);
13744 SDValue In = Op->getOperand(0);
13745 MVT InVT = In.getSimpleValueType();
13748 // Optimize vectors in AVX mode:
13751 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13752 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13753 // Concat upper and lower parts.
13756 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13757 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13758 // Concat upper and lower parts.
13761 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13762 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13763 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13766 if (Subtarget->hasInt256())
13767 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13769 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13770 SDValue Undef = DAG.getUNDEF(InVT);
13771 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13772 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13773 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13775 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13776 VT.getVectorNumElements()/2);
13778 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13779 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13781 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13784 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13785 SelectionDAG &DAG) {
13786 MVT VT = Op->getSimpleValueType(0);
13787 SDValue In = Op->getOperand(0);
13788 MVT InVT = In.getSimpleValueType();
13790 unsigned int NumElts = VT.getVectorNumElements();
13791 if (NumElts != 8 && NumElts != 16)
13794 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13795 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13797 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13798 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13799 // Now we have only mask extension
13800 assert(InVT.getVectorElementType() == MVT::i1);
13801 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13802 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13803 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13804 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13805 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13806 MachinePointerInfo::getConstantPool(),
13807 false, false, false, Alignment);
13809 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13810 if (VT.is512BitVector())
13812 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13815 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13816 SelectionDAG &DAG) {
13817 if (Subtarget->hasFp256()) {
13818 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13826 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13827 SelectionDAG &DAG) {
13829 MVT VT = Op.getSimpleValueType();
13830 SDValue In = Op.getOperand(0);
13831 MVT SVT = In.getSimpleValueType();
13833 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13834 return LowerZERO_EXTEND_AVX512(Op, DAG);
13836 if (Subtarget->hasFp256()) {
13837 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13842 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13843 VT.getVectorNumElements() != SVT.getVectorNumElements());
13847 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13849 MVT VT = Op.getSimpleValueType();
13850 SDValue In = Op.getOperand(0);
13851 MVT InVT = In.getSimpleValueType();
13853 if (VT == MVT::i1) {
13854 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13855 "Invalid scalar TRUNCATE operation");
13856 if (InVT.getSizeInBits() >= 32)
13858 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13859 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13861 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13862 "Invalid TRUNCATE operation");
13864 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13865 if (VT.getVectorElementType().getSizeInBits() >=8)
13866 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13868 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13869 unsigned NumElts = InVT.getVectorNumElements();
13870 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13871 if (InVT.getSizeInBits() < 512) {
13872 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13873 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13877 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13878 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13879 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13880 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13881 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13882 MachinePointerInfo::getConstantPool(),
13883 false, false, false, Alignment);
13884 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13885 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13886 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13889 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13890 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13891 if (Subtarget->hasInt256()) {
13892 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13893 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13894 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13896 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13897 DAG.getIntPtrConstant(0));
13900 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13901 DAG.getIntPtrConstant(0));
13902 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13903 DAG.getIntPtrConstant(2));
13904 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13905 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13906 static const int ShufMask[] = {0, 2, 4, 6};
13907 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13910 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13911 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13912 if (Subtarget->hasInt256()) {
13913 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13915 SmallVector<SDValue,32> pshufbMask;
13916 for (unsigned i = 0; i < 2; ++i) {
13917 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13918 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13919 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13920 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13921 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13922 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13923 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13924 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13925 for (unsigned j = 0; j < 8; ++j)
13926 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13928 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13929 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13930 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13932 static const int ShufMask[] = {0, 2, -1, -1};
13933 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13935 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13936 DAG.getIntPtrConstant(0));
13937 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13940 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13941 DAG.getIntPtrConstant(0));
13943 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13944 DAG.getIntPtrConstant(4));
13946 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13947 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13949 // The PSHUFB mask:
13950 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13951 -1, -1, -1, -1, -1, -1, -1, -1};
13953 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13954 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13955 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13957 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13958 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13960 // The MOVLHPS Mask:
13961 static const int ShufMask2[] = {0, 1, 4, 5};
13962 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13963 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13966 // Handle truncation of V256 to V128 using shuffles.
13967 if (!VT.is128BitVector() || !InVT.is256BitVector())
13970 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13972 unsigned NumElems = VT.getVectorNumElements();
13973 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13975 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13976 // Prepare truncation shuffle mask
13977 for (unsigned i = 0; i != NumElems; ++i)
13978 MaskVec[i] = i * 2;
13979 SDValue V = DAG.getVectorShuffle(NVT, DL,
13980 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13981 DAG.getUNDEF(NVT), &MaskVec[0]);
13982 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13983 DAG.getIntPtrConstant(0));
13986 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13987 SelectionDAG &DAG) const {
13988 assert(!Op.getSimpleValueType().isVector());
13990 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13991 /*IsSigned=*/ true, /*IsReplace=*/ false);
13992 SDValue FIST = Vals.first, StackSlot = Vals.second;
13993 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13994 if (!FIST.getNode()) return Op;
13996 if (StackSlot.getNode())
13997 // Load the result.
13998 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13999 FIST, StackSlot, MachinePointerInfo(),
14000 false, false, false, 0);
14002 // The node is the result.
14006 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14007 SelectionDAG &DAG) const {
14008 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14009 /*IsSigned=*/ false, /*IsReplace=*/ false);
14010 SDValue FIST = Vals.first, StackSlot = Vals.second;
14011 assert(FIST.getNode() && "Unexpected failure");
14013 if (StackSlot.getNode())
14014 // Load the result.
14015 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14016 FIST, StackSlot, MachinePointerInfo(),
14017 false, false, false, 0);
14019 // The node is the result.
14023 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14025 MVT VT = Op.getSimpleValueType();
14026 SDValue In = Op.getOperand(0);
14027 MVT SVT = In.getSimpleValueType();
14029 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14031 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14032 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14033 In, DAG.getUNDEF(SVT)));
14036 /// The only differences between FABS and FNEG are the mask and the logic op.
14037 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14038 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14039 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14040 "Wrong opcode for lowering FABS or FNEG.");
14042 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14044 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14045 // into an FNABS. We'll lower the FABS after that if it is still in use.
14047 for (SDNode *User : Op->uses())
14048 if (User->getOpcode() == ISD::FNEG)
14051 SDValue Op0 = Op.getOperand(0);
14052 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14055 MVT VT = Op.getSimpleValueType();
14056 // Assume scalar op for initialization; update for vector if needed.
14057 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14058 // generate a 16-byte vector constant and logic op even for the scalar case.
14059 // Using a 16-byte mask allows folding the load of the mask with
14060 // the logic op, so it can save (~4 bytes) on code size.
14062 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14063 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14064 // decide if we should generate a 16-byte constant mask when we only need 4 or
14065 // 8 bytes for the scalar case.
14066 if (VT.isVector()) {
14067 EltVT = VT.getVectorElementType();
14068 NumElts = VT.getVectorNumElements();
14071 unsigned EltBits = EltVT.getSizeInBits();
14072 LLVMContext *Context = DAG.getContext();
14073 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14075 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14076 Constant *C = ConstantInt::get(*Context, MaskElt);
14077 C = ConstantVector::getSplat(NumElts, C);
14078 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14079 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14080 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14081 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14082 MachinePointerInfo::getConstantPool(),
14083 false, false, false, Alignment);
14085 if (VT.isVector()) {
14086 // For a vector, cast operands to a vector type, perform the logic op,
14087 // and cast the result back to the original value type.
14088 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14089 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14090 SDValue Operand = IsFNABS ?
14091 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14092 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14093 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14094 return DAG.getNode(ISD::BITCAST, dl, VT,
14095 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14098 // If not vector, then scalar.
14099 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14100 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14101 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14104 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14106 LLVMContext *Context = DAG.getContext();
14107 SDValue Op0 = Op.getOperand(0);
14108 SDValue Op1 = Op.getOperand(1);
14110 MVT VT = Op.getSimpleValueType();
14111 MVT SrcVT = Op1.getSimpleValueType();
14113 // If second operand is smaller, extend it first.
14114 if (SrcVT.bitsLT(VT)) {
14115 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14118 // And if it is bigger, shrink it first.
14119 if (SrcVT.bitsGT(VT)) {
14120 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14124 // At this point the operands and the result should have the same
14125 // type, and that won't be f80 since that is not custom lowered.
14127 // First get the sign bit of second operand.
14128 SmallVector<Constant*,4> CV;
14129 if (SrcVT == MVT::f64) {
14130 const fltSemantics &Sem = APFloat::IEEEdouble;
14131 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14132 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14134 const fltSemantics &Sem = APFloat::IEEEsingle;
14135 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14136 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14137 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14138 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14140 Constant *C = ConstantVector::get(CV);
14141 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14142 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14143 MachinePointerInfo::getConstantPool(),
14144 false, false, false, 16);
14145 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14147 // Shift sign bit right or left if the two operands have different types.
14148 if (SrcVT.bitsGT(VT)) {
14149 // Op0 is MVT::f32, Op1 is MVT::f64.
14150 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14151 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14152 DAG.getConstant(32, MVT::i32));
14153 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14154 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14155 DAG.getIntPtrConstant(0));
14158 // Clear first operand sign bit.
14160 if (VT == MVT::f64) {
14161 const fltSemantics &Sem = APFloat::IEEEdouble;
14162 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14163 APInt(64, ~(1ULL << 63)))));
14164 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14166 const fltSemantics &Sem = APFloat::IEEEsingle;
14167 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14168 APInt(32, ~(1U << 31)))));
14169 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14170 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14171 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14173 C = ConstantVector::get(CV);
14174 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14175 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14176 MachinePointerInfo::getConstantPool(),
14177 false, false, false, 16);
14178 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14180 // Or the value with the sign bit.
14181 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14184 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14185 SDValue N0 = Op.getOperand(0);
14187 MVT VT = Op.getSimpleValueType();
14189 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14190 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14191 DAG.getConstant(1, VT));
14192 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14195 // Check whether an OR'd tree is PTEST-able.
14196 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14197 SelectionDAG &DAG) {
14198 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14200 if (!Subtarget->hasSSE41())
14203 if (!Op->hasOneUse())
14206 SDNode *N = Op.getNode();
14209 SmallVector<SDValue, 8> Opnds;
14210 DenseMap<SDValue, unsigned> VecInMap;
14211 SmallVector<SDValue, 8> VecIns;
14212 EVT VT = MVT::Other;
14214 // Recognize a special case where a vector is casted into wide integer to
14216 Opnds.push_back(N->getOperand(0));
14217 Opnds.push_back(N->getOperand(1));
14219 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14220 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14221 // BFS traverse all OR'd operands.
14222 if (I->getOpcode() == ISD::OR) {
14223 Opnds.push_back(I->getOperand(0));
14224 Opnds.push_back(I->getOperand(1));
14225 // Re-evaluate the number of nodes to be traversed.
14226 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14230 // Quit if a non-EXTRACT_VECTOR_ELT
14231 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14234 // Quit if without a constant index.
14235 SDValue Idx = I->getOperand(1);
14236 if (!isa<ConstantSDNode>(Idx))
14239 SDValue ExtractedFromVec = I->getOperand(0);
14240 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14241 if (M == VecInMap.end()) {
14242 VT = ExtractedFromVec.getValueType();
14243 // Quit if not 128/256-bit vector.
14244 if (!VT.is128BitVector() && !VT.is256BitVector())
14246 // Quit if not the same type.
14247 if (VecInMap.begin() != VecInMap.end() &&
14248 VT != VecInMap.begin()->first.getValueType())
14250 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14251 VecIns.push_back(ExtractedFromVec);
14253 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14256 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14257 "Not extracted from 128-/256-bit vector.");
14259 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14261 for (DenseMap<SDValue, unsigned>::const_iterator
14262 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14263 // Quit if not all elements are used.
14264 if (I->second != FullMask)
14268 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14270 // Cast all vectors into TestVT for PTEST.
14271 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14272 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14274 // If more than one full vectors are evaluated, OR them first before PTEST.
14275 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14276 // Each iteration will OR 2 nodes and append the result until there is only
14277 // 1 node left, i.e. the final OR'd value of all vectors.
14278 SDValue LHS = VecIns[Slot];
14279 SDValue RHS = VecIns[Slot + 1];
14280 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14283 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14284 VecIns.back(), VecIns.back());
14287 /// \brief return true if \c Op has a use that doesn't just read flags.
14288 static bool hasNonFlagsUse(SDValue Op) {
14289 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14291 SDNode *User = *UI;
14292 unsigned UOpNo = UI.getOperandNo();
14293 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14294 // Look pass truncate.
14295 UOpNo = User->use_begin().getOperandNo();
14296 User = *User->use_begin();
14299 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14300 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14306 /// Emit nodes that will be selected as "test Op0,Op0", or something
14308 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14309 SelectionDAG &DAG) const {
14310 if (Op.getValueType() == MVT::i1)
14311 // KORTEST instruction should be selected
14312 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14313 DAG.getConstant(0, Op.getValueType()));
14315 // CF and OF aren't always set the way we want. Determine which
14316 // of these we need.
14317 bool NeedCF = false;
14318 bool NeedOF = false;
14321 case X86::COND_A: case X86::COND_AE:
14322 case X86::COND_B: case X86::COND_BE:
14325 case X86::COND_G: case X86::COND_GE:
14326 case X86::COND_L: case X86::COND_LE:
14327 case X86::COND_O: case X86::COND_NO: {
14328 // Check if we really need to set the
14329 // Overflow flag. If NoSignedWrap is present
14330 // that is not actually needed.
14331 switch (Op->getOpcode()) {
14336 const BinaryWithFlagsSDNode *BinNode =
14337 cast<BinaryWithFlagsSDNode>(Op.getNode());
14338 if (BinNode->hasNoSignedWrap())
14348 // See if we can use the EFLAGS value from the operand instead of
14349 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14350 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14351 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14352 // Emit a CMP with 0, which is the TEST pattern.
14353 //if (Op.getValueType() == MVT::i1)
14354 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14355 // DAG.getConstant(0, MVT::i1));
14356 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14357 DAG.getConstant(0, Op.getValueType()));
14359 unsigned Opcode = 0;
14360 unsigned NumOperands = 0;
14362 // Truncate operations may prevent the merge of the SETCC instruction
14363 // and the arithmetic instruction before it. Attempt to truncate the operands
14364 // of the arithmetic instruction and use a reduced bit-width instruction.
14365 bool NeedTruncation = false;
14366 SDValue ArithOp = Op;
14367 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14368 SDValue Arith = Op->getOperand(0);
14369 // Both the trunc and the arithmetic op need to have one user each.
14370 if (Arith->hasOneUse())
14371 switch (Arith.getOpcode()) {
14378 NeedTruncation = true;
14384 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14385 // which may be the result of a CAST. We use the variable 'Op', which is the
14386 // non-casted variable when we check for possible users.
14387 switch (ArithOp.getOpcode()) {
14389 // Due to an isel shortcoming, be conservative if this add is likely to be
14390 // selected as part of a load-modify-store instruction. When the root node
14391 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14392 // uses of other nodes in the match, such as the ADD in this case. This
14393 // leads to the ADD being left around and reselected, with the result being
14394 // two adds in the output. Alas, even if none our users are stores, that
14395 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14396 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14397 // climbing the DAG back to the root, and it doesn't seem to be worth the
14399 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14400 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14401 if (UI->getOpcode() != ISD::CopyToReg &&
14402 UI->getOpcode() != ISD::SETCC &&
14403 UI->getOpcode() != ISD::STORE)
14406 if (ConstantSDNode *C =
14407 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14408 // An add of one will be selected as an INC.
14409 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14410 Opcode = X86ISD::INC;
14415 // An add of negative one (subtract of one) will be selected as a DEC.
14416 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14417 Opcode = X86ISD::DEC;
14423 // Otherwise use a regular EFLAGS-setting add.
14424 Opcode = X86ISD::ADD;
14429 // If we have a constant logical shift that's only used in a comparison
14430 // against zero turn it into an equivalent AND. This allows turning it into
14431 // a TEST instruction later.
14432 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14433 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14434 EVT VT = Op.getValueType();
14435 unsigned BitWidth = VT.getSizeInBits();
14436 unsigned ShAmt = Op->getConstantOperandVal(1);
14437 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14439 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14440 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14441 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14442 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14444 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14445 DAG.getConstant(Mask, VT));
14446 DAG.ReplaceAllUsesWith(Op, New);
14452 // If the primary and result isn't used, don't bother using X86ISD::AND,
14453 // because a TEST instruction will be better.
14454 if (!hasNonFlagsUse(Op))
14460 // Due to the ISEL shortcoming noted above, be conservative if this op is
14461 // likely to be selected as part of a load-modify-store instruction.
14462 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14463 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14464 if (UI->getOpcode() == ISD::STORE)
14467 // Otherwise use a regular EFLAGS-setting instruction.
14468 switch (ArithOp.getOpcode()) {
14469 default: llvm_unreachable("unexpected operator!");
14470 case ISD::SUB: Opcode = X86ISD::SUB; break;
14471 case ISD::XOR: Opcode = X86ISD::XOR; break;
14472 case ISD::AND: Opcode = X86ISD::AND; break;
14474 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14475 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14476 if (EFLAGS.getNode())
14479 Opcode = X86ISD::OR;
14493 return SDValue(Op.getNode(), 1);
14499 // If we found that truncation is beneficial, perform the truncation and
14501 if (NeedTruncation) {
14502 EVT VT = Op.getValueType();
14503 SDValue WideVal = Op->getOperand(0);
14504 EVT WideVT = WideVal.getValueType();
14505 unsigned ConvertedOp = 0;
14506 // Use a target machine opcode to prevent further DAGCombine
14507 // optimizations that may separate the arithmetic operations
14508 // from the setcc node.
14509 switch (WideVal.getOpcode()) {
14511 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14512 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14513 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14514 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14515 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14519 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14520 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14521 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14522 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14523 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14529 // Emit a CMP with 0, which is the TEST pattern.
14530 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14531 DAG.getConstant(0, Op.getValueType()));
14533 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14534 SmallVector<SDValue, 4> Ops;
14535 for (unsigned i = 0; i != NumOperands; ++i)
14536 Ops.push_back(Op.getOperand(i));
14538 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14539 DAG.ReplaceAllUsesWith(Op, New);
14540 return SDValue(New.getNode(), 1);
14543 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14545 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14546 SDLoc dl, SelectionDAG &DAG) const {
14547 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14548 if (C->getAPIntValue() == 0)
14549 return EmitTest(Op0, X86CC, dl, DAG);
14551 if (Op0.getValueType() == MVT::i1)
14552 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14555 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14556 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14557 // Do the comparison at i32 if it's smaller, besides the Atom case.
14558 // This avoids subregister aliasing issues. Keep the smaller reference
14559 // if we're optimizing for size, however, as that'll allow better folding
14560 // of memory operations.
14561 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14562 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14563 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14564 !Subtarget->isAtom()) {
14565 unsigned ExtendOp =
14566 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14567 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14568 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14570 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14571 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14572 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14574 return SDValue(Sub.getNode(), 1);
14576 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14579 /// Convert a comparison if required by the subtarget.
14580 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14581 SelectionDAG &DAG) const {
14582 // If the subtarget does not support the FUCOMI instruction, floating-point
14583 // comparisons have to be converted.
14584 if (Subtarget->hasCMov() ||
14585 Cmp.getOpcode() != X86ISD::CMP ||
14586 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14587 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14590 // The instruction selector will select an FUCOM instruction instead of
14591 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14592 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14593 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14595 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14596 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14597 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14598 DAG.getConstant(8, MVT::i8));
14599 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14600 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14603 /// The minimum architected relative accuracy is 2^-12. We need one
14604 /// Newton-Raphson step to have a good float result (24 bits of precision).
14605 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14606 DAGCombinerInfo &DCI,
14607 unsigned &RefinementSteps,
14608 bool &UseOneConstNR) const {
14609 // FIXME: We should use instruction latency models to calculate the cost of
14610 // each potential sequence, but this is very hard to do reliably because
14611 // at least Intel's Core* chips have variable timing based on the number of
14612 // significant digits in the divisor and/or sqrt operand.
14613 if (!Subtarget->useSqrtEst())
14616 EVT VT = Op.getValueType();
14618 // SSE1 has rsqrtss and rsqrtps.
14619 // TODO: Add support for AVX512 (v16f32).
14620 // It is likely not profitable to do this for f64 because a double-precision
14621 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14622 // instructions: convert to single, rsqrtss, convert back to double, refine
14623 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14624 // along with FMA, this could be a throughput win.
14625 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14626 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14627 RefinementSteps = 1;
14628 UseOneConstNR = false;
14629 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14634 /// The minimum architected relative accuracy is 2^-12. We need one
14635 /// Newton-Raphson step to have a good float result (24 bits of precision).
14636 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14637 DAGCombinerInfo &DCI,
14638 unsigned &RefinementSteps) const {
14639 // FIXME: We should use instruction latency models to calculate the cost of
14640 // each potential sequence, but this is very hard to do reliably because
14641 // at least Intel's Core* chips have variable timing based on the number of
14642 // significant digits in the divisor.
14643 if (!Subtarget->useReciprocalEst())
14646 EVT VT = Op.getValueType();
14648 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14649 // TODO: Add support for AVX512 (v16f32).
14650 // It is likely not profitable to do this for f64 because a double-precision
14651 // reciprocal estimate with refinement on x86 prior to FMA requires
14652 // 15 instructions: convert to single, rcpss, convert back to double, refine
14653 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14654 // along with FMA, this could be a throughput win.
14655 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14656 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14657 RefinementSteps = ReciprocalEstimateRefinementSteps;
14658 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14663 static bool isAllOnes(SDValue V) {
14664 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14665 return C && C->isAllOnesValue();
14668 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14669 /// if it's possible.
14670 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14671 SDLoc dl, SelectionDAG &DAG) const {
14672 SDValue Op0 = And.getOperand(0);
14673 SDValue Op1 = And.getOperand(1);
14674 if (Op0.getOpcode() == ISD::TRUNCATE)
14675 Op0 = Op0.getOperand(0);
14676 if (Op1.getOpcode() == ISD::TRUNCATE)
14677 Op1 = Op1.getOperand(0);
14680 if (Op1.getOpcode() == ISD::SHL)
14681 std::swap(Op0, Op1);
14682 if (Op0.getOpcode() == ISD::SHL) {
14683 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14684 if (And00C->getZExtValue() == 1) {
14685 // If we looked past a truncate, check that it's only truncating away
14687 unsigned BitWidth = Op0.getValueSizeInBits();
14688 unsigned AndBitWidth = And.getValueSizeInBits();
14689 if (BitWidth > AndBitWidth) {
14691 DAG.computeKnownBits(Op0, Zeros, Ones);
14692 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14696 RHS = Op0.getOperand(1);
14698 } else if (Op1.getOpcode() == ISD::Constant) {
14699 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14700 uint64_t AndRHSVal = AndRHS->getZExtValue();
14701 SDValue AndLHS = Op0;
14703 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14704 LHS = AndLHS.getOperand(0);
14705 RHS = AndLHS.getOperand(1);
14708 // Use BT if the immediate can't be encoded in a TEST instruction.
14709 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14711 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14715 if (LHS.getNode()) {
14716 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14717 // instruction. Since the shift amount is in-range-or-undefined, we know
14718 // that doing a bittest on the i32 value is ok. We extend to i32 because
14719 // the encoding for the i16 version is larger than the i32 version.
14720 // Also promote i16 to i32 for performance / code size reason.
14721 if (LHS.getValueType() == MVT::i8 ||
14722 LHS.getValueType() == MVT::i16)
14723 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14725 // If the operand types disagree, extend the shift amount to match. Since
14726 // BT ignores high bits (like shifts) we can use anyextend.
14727 if (LHS.getValueType() != RHS.getValueType())
14728 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14730 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14731 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14732 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14733 DAG.getConstant(Cond, MVT::i8), BT);
14739 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14741 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14746 // SSE Condition code mapping:
14755 switch (SetCCOpcode) {
14756 default: llvm_unreachable("Unexpected SETCC condition");
14758 case ISD::SETEQ: SSECC = 0; break;
14760 case ISD::SETGT: Swap = true; // Fallthrough
14762 case ISD::SETOLT: SSECC = 1; break;
14764 case ISD::SETGE: Swap = true; // Fallthrough
14766 case ISD::SETOLE: SSECC = 2; break;
14767 case ISD::SETUO: SSECC = 3; break;
14769 case ISD::SETNE: SSECC = 4; break;
14770 case ISD::SETULE: Swap = true; // Fallthrough
14771 case ISD::SETUGE: SSECC = 5; break;
14772 case ISD::SETULT: Swap = true; // Fallthrough
14773 case ISD::SETUGT: SSECC = 6; break;
14774 case ISD::SETO: SSECC = 7; break;
14776 case ISD::SETONE: SSECC = 8; break;
14779 std::swap(Op0, Op1);
14784 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14785 // ones, and then concatenate the result back.
14786 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14787 MVT VT = Op.getSimpleValueType();
14789 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14790 "Unsupported value type for operation");
14792 unsigned NumElems = VT.getVectorNumElements();
14794 SDValue CC = Op.getOperand(2);
14796 // Extract the LHS vectors
14797 SDValue LHS = Op.getOperand(0);
14798 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14799 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14801 // Extract the RHS vectors
14802 SDValue RHS = Op.getOperand(1);
14803 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14804 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14806 // Issue the operation on the smaller types and concatenate the result back
14807 MVT EltVT = VT.getVectorElementType();
14808 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14809 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14810 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14811 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14814 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14815 const X86Subtarget *Subtarget) {
14816 SDValue Op0 = Op.getOperand(0);
14817 SDValue Op1 = Op.getOperand(1);
14818 SDValue CC = Op.getOperand(2);
14819 MVT VT = Op.getSimpleValueType();
14822 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14823 Op.getValueType().getScalarType() == MVT::i1 &&
14824 "Cannot set masked compare for this operation");
14826 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14828 bool Unsigned = false;
14831 switch (SetCCOpcode) {
14832 default: llvm_unreachable("Unexpected SETCC condition");
14833 case ISD::SETNE: SSECC = 4; break;
14834 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14835 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14836 case ISD::SETLT: Swap = true; //fall-through
14837 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14838 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14839 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14840 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14841 case ISD::SETULE: Unsigned = true; //fall-through
14842 case ISD::SETLE: SSECC = 2; break;
14846 std::swap(Op0, Op1);
14848 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14849 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14850 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14851 DAG.getConstant(SSECC, MVT::i8));
14854 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14855 /// operand \p Op1. If non-trivial (for example because it's not constant)
14856 /// return an empty value.
14857 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14859 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14863 MVT VT = Op1.getSimpleValueType();
14864 MVT EVT = VT.getVectorElementType();
14865 unsigned n = VT.getVectorNumElements();
14866 SmallVector<SDValue, 8> ULTOp1;
14868 for (unsigned i = 0; i < n; ++i) {
14869 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14870 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14873 // Avoid underflow.
14874 APInt Val = Elt->getAPIntValue();
14878 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14881 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14884 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14885 SelectionDAG &DAG) {
14886 SDValue Op0 = Op.getOperand(0);
14887 SDValue Op1 = Op.getOperand(1);
14888 SDValue CC = Op.getOperand(2);
14889 MVT VT = Op.getSimpleValueType();
14890 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14891 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14896 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14897 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14900 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14901 unsigned Opc = X86ISD::CMPP;
14902 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14903 assert(VT.getVectorNumElements() <= 16);
14904 Opc = X86ISD::CMPM;
14906 // In the two special cases we can't handle, emit two comparisons.
14909 unsigned CombineOpc;
14910 if (SetCCOpcode == ISD::SETUEQ) {
14911 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14913 assert(SetCCOpcode == ISD::SETONE);
14914 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14917 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14918 DAG.getConstant(CC0, MVT::i8));
14919 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14920 DAG.getConstant(CC1, MVT::i8));
14921 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14923 // Handle all other FP comparisons here.
14924 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14925 DAG.getConstant(SSECC, MVT::i8));
14928 // Break 256-bit integer vector compare into smaller ones.
14929 if (VT.is256BitVector() && !Subtarget->hasInt256())
14930 return Lower256IntVSETCC(Op, DAG);
14932 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14933 EVT OpVT = Op1.getValueType();
14934 if (Subtarget->hasAVX512()) {
14935 if (Op1.getValueType().is512BitVector() ||
14936 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14937 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14938 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14940 // In AVX-512 architecture setcc returns mask with i1 elements,
14941 // But there is no compare instruction for i8 and i16 elements in KNL.
14942 // We are not talking about 512-bit operands in this case, these
14943 // types are illegal.
14945 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14946 OpVT.getVectorElementType().getSizeInBits() >= 8))
14947 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14948 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14951 // We are handling one of the integer comparisons here. Since SSE only has
14952 // GT and EQ comparisons for integer, swapping operands and multiple
14953 // operations may be required for some comparisons.
14955 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14956 bool Subus = false;
14958 switch (SetCCOpcode) {
14959 default: llvm_unreachable("Unexpected SETCC condition");
14960 case ISD::SETNE: Invert = true;
14961 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14962 case ISD::SETLT: Swap = true;
14963 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14964 case ISD::SETGE: Swap = true;
14965 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14966 Invert = true; break;
14967 case ISD::SETULT: Swap = true;
14968 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14969 FlipSigns = true; break;
14970 case ISD::SETUGE: Swap = true;
14971 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14972 FlipSigns = true; Invert = true; break;
14975 // Special case: Use min/max operations for SETULE/SETUGE
14976 MVT VET = VT.getVectorElementType();
14978 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14979 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14982 switch (SetCCOpcode) {
14984 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14985 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14988 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14991 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14992 if (!MinMax && hasSubus) {
14993 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14995 // t = psubus Op0, Op1
14996 // pcmpeq t, <0..0>
14997 switch (SetCCOpcode) {
14999 case ISD::SETULT: {
15000 // If the comparison is against a constant we can turn this into a
15001 // setule. With psubus, setule does not require a swap. This is
15002 // beneficial because the constant in the register is no longer
15003 // destructed as the destination so it can be hoisted out of a loop.
15004 // Only do this pre-AVX since vpcmp* is no longer destructive.
15005 if (Subtarget->hasAVX())
15007 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15008 if (ULEOp1.getNode()) {
15010 Subus = true; Invert = false; Swap = false;
15014 // Psubus is better than flip-sign because it requires no inversion.
15015 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15016 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15020 Opc = X86ISD::SUBUS;
15026 std::swap(Op0, Op1);
15028 // Check that the operation in question is available (most are plain SSE2,
15029 // but PCMPGTQ and PCMPEQQ have different requirements).
15030 if (VT == MVT::v2i64) {
15031 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15032 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15034 // First cast everything to the right type.
15035 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15036 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15038 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15039 // bits of the inputs before performing those operations. The lower
15040 // compare is always unsigned.
15043 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15045 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15046 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15047 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15048 Sign, Zero, Sign, Zero);
15050 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15051 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15053 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15054 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15055 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15057 // Create masks for only the low parts/high parts of the 64 bit integers.
15058 static const int MaskHi[] = { 1, 1, 3, 3 };
15059 static const int MaskLo[] = { 0, 0, 2, 2 };
15060 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15061 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15062 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15064 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15065 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15068 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15070 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15073 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15074 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15075 // pcmpeqd + pshufd + pand.
15076 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15078 // First cast everything to the right type.
15079 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15080 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15083 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15085 // Make sure the lower and upper halves are both all-ones.
15086 static const int Mask[] = { 1, 0, 3, 2 };
15087 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15088 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15091 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15093 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15097 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15098 // bits of the inputs before performing those operations.
15100 EVT EltVT = VT.getVectorElementType();
15101 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15102 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15103 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15106 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15108 // If the logical-not of the result is required, perform that now.
15110 Result = DAG.getNOT(dl, Result, VT);
15113 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15116 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15117 getZeroVector(VT, Subtarget, DAG, dl));
15122 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15124 MVT VT = Op.getSimpleValueType();
15126 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15128 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15129 && "SetCC type must be 8-bit or 1-bit integer");
15130 SDValue Op0 = Op.getOperand(0);
15131 SDValue Op1 = Op.getOperand(1);
15133 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15135 // Optimize to BT if possible.
15136 // Lower (X & (1 << N)) == 0 to BT(X, N).
15137 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15138 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15139 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15140 Op1.getOpcode() == ISD::Constant &&
15141 cast<ConstantSDNode>(Op1)->isNullValue() &&
15142 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15143 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15144 if (NewSetCC.getNode())
15148 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15150 if (Op1.getOpcode() == ISD::Constant &&
15151 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15152 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15153 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15155 // If the input is a setcc, then reuse the input setcc or use a new one with
15156 // the inverted condition.
15157 if (Op0.getOpcode() == X86ISD::SETCC) {
15158 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15159 bool Invert = (CC == ISD::SETNE) ^
15160 cast<ConstantSDNode>(Op1)->isNullValue();
15164 CCode = X86::GetOppositeBranchCondition(CCode);
15165 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15166 DAG.getConstant(CCode, MVT::i8),
15167 Op0.getOperand(1));
15169 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15173 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15174 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15175 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15177 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15178 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15181 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15182 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15183 if (X86CC == X86::COND_INVALID)
15186 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15187 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15188 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15189 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15191 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15195 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15196 static bool isX86LogicalCmp(SDValue Op) {
15197 unsigned Opc = Op.getNode()->getOpcode();
15198 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15199 Opc == X86ISD::SAHF)
15201 if (Op.getResNo() == 1 &&
15202 (Opc == X86ISD::ADD ||
15203 Opc == X86ISD::SUB ||
15204 Opc == X86ISD::ADC ||
15205 Opc == X86ISD::SBB ||
15206 Opc == X86ISD::SMUL ||
15207 Opc == X86ISD::UMUL ||
15208 Opc == X86ISD::INC ||
15209 Opc == X86ISD::DEC ||
15210 Opc == X86ISD::OR ||
15211 Opc == X86ISD::XOR ||
15212 Opc == X86ISD::AND))
15215 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15221 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15222 if (V.getOpcode() != ISD::TRUNCATE)
15225 SDValue VOp0 = V.getOperand(0);
15226 unsigned InBits = VOp0.getValueSizeInBits();
15227 unsigned Bits = V.getValueSizeInBits();
15228 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15231 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15232 bool addTest = true;
15233 SDValue Cond = Op.getOperand(0);
15234 SDValue Op1 = Op.getOperand(1);
15235 SDValue Op2 = Op.getOperand(2);
15237 EVT VT = Op1.getValueType();
15240 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15241 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15242 // sequence later on.
15243 if (Cond.getOpcode() == ISD::SETCC &&
15244 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15245 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15246 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15247 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15248 int SSECC = translateX86FSETCC(
15249 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15252 if (Subtarget->hasAVX512()) {
15253 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15254 DAG.getConstant(SSECC, MVT::i8));
15255 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15257 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15258 DAG.getConstant(SSECC, MVT::i8));
15259 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15260 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15261 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15265 if (Cond.getOpcode() == ISD::SETCC) {
15266 SDValue NewCond = LowerSETCC(Cond, DAG);
15267 if (NewCond.getNode())
15271 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15272 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15273 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15274 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15275 if (Cond.getOpcode() == X86ISD::SETCC &&
15276 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15277 isZero(Cond.getOperand(1).getOperand(1))) {
15278 SDValue Cmp = Cond.getOperand(1);
15280 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15282 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15283 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15284 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15286 SDValue CmpOp0 = Cmp.getOperand(0);
15287 // Apply further optimizations for special cases
15288 // (select (x != 0), -1, 0) -> neg & sbb
15289 // (select (x == 0), 0, -1) -> neg & sbb
15290 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15291 if (YC->isNullValue() &&
15292 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15293 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15294 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15295 DAG.getConstant(0, CmpOp0.getValueType()),
15297 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15298 DAG.getConstant(X86::COND_B, MVT::i8),
15299 SDValue(Neg.getNode(), 1));
15303 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15304 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15305 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15307 SDValue Res = // Res = 0 or -1.
15308 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15309 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15311 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15312 Res = DAG.getNOT(DL, Res, Res.getValueType());
15314 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15315 if (!N2C || !N2C->isNullValue())
15316 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15321 // Look past (and (setcc_carry (cmp ...)), 1).
15322 if (Cond.getOpcode() == ISD::AND &&
15323 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15324 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15325 if (C && C->getAPIntValue() == 1)
15326 Cond = Cond.getOperand(0);
15329 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15330 // setting operand in place of the X86ISD::SETCC.
15331 unsigned CondOpcode = Cond.getOpcode();
15332 if (CondOpcode == X86ISD::SETCC ||
15333 CondOpcode == X86ISD::SETCC_CARRY) {
15334 CC = Cond.getOperand(0);
15336 SDValue Cmp = Cond.getOperand(1);
15337 unsigned Opc = Cmp.getOpcode();
15338 MVT VT = Op.getSimpleValueType();
15340 bool IllegalFPCMov = false;
15341 if (VT.isFloatingPoint() && !VT.isVector() &&
15342 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15343 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15345 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15346 Opc == X86ISD::BT) { // FIXME
15350 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15351 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15352 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15353 Cond.getOperand(0).getValueType() != MVT::i8)) {
15354 SDValue LHS = Cond.getOperand(0);
15355 SDValue RHS = Cond.getOperand(1);
15356 unsigned X86Opcode;
15359 switch (CondOpcode) {
15360 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15361 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15362 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15363 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15364 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15365 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15366 default: llvm_unreachable("unexpected overflowing operator");
15368 if (CondOpcode == ISD::UMULO)
15369 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15372 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15374 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15376 if (CondOpcode == ISD::UMULO)
15377 Cond = X86Op.getValue(2);
15379 Cond = X86Op.getValue(1);
15381 CC = DAG.getConstant(X86Cond, MVT::i8);
15386 // Look pass the truncate if the high bits are known zero.
15387 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15388 Cond = Cond.getOperand(0);
15390 // We know the result of AND is compared against zero. Try to match
15392 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15393 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15394 if (NewSetCC.getNode()) {
15395 CC = NewSetCC.getOperand(0);
15396 Cond = NewSetCC.getOperand(1);
15403 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15404 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15407 // a < b ? -1 : 0 -> RES = ~setcc_carry
15408 // a < b ? 0 : -1 -> RES = setcc_carry
15409 // a >= b ? -1 : 0 -> RES = setcc_carry
15410 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15411 if (Cond.getOpcode() == X86ISD::SUB) {
15412 Cond = ConvertCmpIfNecessary(Cond, DAG);
15413 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15415 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15416 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15417 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15418 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15419 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15420 return DAG.getNOT(DL, Res, Res.getValueType());
15425 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15426 // widen the cmov and push the truncate through. This avoids introducing a new
15427 // branch during isel and doesn't add any extensions.
15428 if (Op.getValueType() == MVT::i8 &&
15429 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15430 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15431 if (T1.getValueType() == T2.getValueType() &&
15432 // Blacklist CopyFromReg to avoid partial register stalls.
15433 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15434 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15435 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15436 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15440 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15441 // condition is true.
15442 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15443 SDValue Ops[] = { Op2, Op1, CC, Cond };
15444 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15447 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15448 SelectionDAG &DAG) {
15449 MVT VT = Op->getSimpleValueType(0);
15450 SDValue In = Op->getOperand(0);
15451 MVT InVT = In.getSimpleValueType();
15452 MVT VTElt = VT.getVectorElementType();
15453 MVT InVTElt = InVT.getVectorElementType();
15457 if ((InVTElt == MVT::i1) &&
15458 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15459 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15461 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15462 VTElt.getSizeInBits() <= 16)) ||
15464 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15465 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15467 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15468 VTElt.getSizeInBits() >= 32))))
15469 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15471 unsigned int NumElts = VT.getVectorNumElements();
15473 if (NumElts != 8 && NumElts != 16)
15476 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
15477 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15479 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15480 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15482 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15483 Constant *C = ConstantInt::get(*DAG.getContext(),
15484 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15486 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15487 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15488 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15489 MachinePointerInfo::getConstantPool(),
15490 false, false, false, Alignment);
15491 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15492 if (VT.is512BitVector())
15494 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15497 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15498 SelectionDAG &DAG) {
15499 MVT VT = Op->getSimpleValueType(0);
15500 SDValue In = Op->getOperand(0);
15501 MVT InVT = In.getSimpleValueType();
15504 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15505 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15507 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15508 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15509 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15512 if (Subtarget->hasInt256())
15513 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15515 // Optimize vectors in AVX mode
15516 // Sign extend v8i16 to v8i32 and
15519 // Divide input vector into two parts
15520 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15521 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15522 // concat the vectors to original VT
15524 unsigned NumElems = InVT.getVectorNumElements();
15525 SDValue Undef = DAG.getUNDEF(InVT);
15527 SmallVector<int,8> ShufMask1(NumElems, -1);
15528 for (unsigned i = 0; i != NumElems/2; ++i)
15531 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15533 SmallVector<int,8> ShufMask2(NumElems, -1);
15534 for (unsigned i = 0; i != NumElems/2; ++i)
15535 ShufMask2[i] = i + NumElems/2;
15537 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15539 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15540 VT.getVectorNumElements()/2);
15542 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15543 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15545 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15548 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15549 // may emit an illegal shuffle but the expansion is still better than scalar
15550 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15551 // we'll emit a shuffle and a arithmetic shift.
15552 // TODO: It is possible to support ZExt by zeroing the undef values during
15553 // the shuffle phase or after the shuffle.
15554 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15555 SelectionDAG &DAG) {
15556 MVT RegVT = Op.getSimpleValueType();
15557 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15558 assert(RegVT.isInteger() &&
15559 "We only custom lower integer vector sext loads.");
15561 // Nothing useful we can do without SSE2 shuffles.
15562 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15564 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15566 EVT MemVT = Ld->getMemoryVT();
15567 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15568 unsigned RegSz = RegVT.getSizeInBits();
15570 ISD::LoadExtType Ext = Ld->getExtensionType();
15572 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15573 && "Only anyext and sext are currently implemented.");
15574 assert(MemVT != RegVT && "Cannot extend to the same type");
15575 assert(MemVT.isVector() && "Must load a vector from memory");
15577 unsigned NumElems = RegVT.getVectorNumElements();
15578 unsigned MemSz = MemVT.getSizeInBits();
15579 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15581 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15582 // The only way in which we have a legal 256-bit vector result but not the
15583 // integer 256-bit operations needed to directly lower a sextload is if we
15584 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15585 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15586 // correctly legalized. We do this late to allow the canonical form of
15587 // sextload to persist throughout the rest of the DAG combiner -- it wants
15588 // to fold together any extensions it can, and so will fuse a sign_extend
15589 // of an sextload into a sextload targeting a wider value.
15591 if (MemSz == 128) {
15592 // Just switch this to a normal load.
15593 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15594 "it must be a legal 128-bit vector "
15596 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15597 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15598 Ld->isInvariant(), Ld->getAlignment());
15600 assert(MemSz < 128 &&
15601 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15602 // Do an sext load to a 128-bit vector type. We want to use the same
15603 // number of elements, but elements half as wide. This will end up being
15604 // recursively lowered by this routine, but will succeed as we definitely
15605 // have all the necessary features if we're using AVX1.
15607 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15608 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15610 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15611 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15612 Ld->isNonTemporal(), Ld->isInvariant(),
15613 Ld->getAlignment());
15616 // Replace chain users with the new chain.
15617 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15618 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15620 // Finally, do a normal sign-extend to the desired register.
15621 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15624 // All sizes must be a power of two.
15625 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15626 "Non-power-of-two elements are not custom lowered!");
15628 // Attempt to load the original value using scalar loads.
15629 // Find the largest scalar type that divides the total loaded size.
15630 MVT SclrLoadTy = MVT::i8;
15631 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15632 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15633 MVT Tp = (MVT::SimpleValueType)tp;
15634 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15639 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15640 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15642 SclrLoadTy = MVT::f64;
15644 // Calculate the number of scalar loads that we need to perform
15645 // in order to load our vector from memory.
15646 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15648 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15649 "Can only lower sext loads with a single scalar load!");
15651 unsigned loadRegZize = RegSz;
15652 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15655 // Represent our vector as a sequence of elements which are the
15656 // largest scalar that we can load.
15657 EVT LoadUnitVecVT = EVT::getVectorVT(
15658 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15660 // Represent the data using the same element type that is stored in
15661 // memory. In practice, we ''widen'' MemVT.
15663 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15664 loadRegZize / MemVT.getScalarType().getSizeInBits());
15666 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15667 "Invalid vector type");
15669 // We can't shuffle using an illegal type.
15670 assert(TLI.isTypeLegal(WideVecVT) &&
15671 "We only lower types that form legal widened vector types");
15673 SmallVector<SDValue, 8> Chains;
15674 SDValue Ptr = Ld->getBasePtr();
15675 SDValue Increment =
15676 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15677 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15679 for (unsigned i = 0; i < NumLoads; ++i) {
15680 // Perform a single load.
15681 SDValue ScalarLoad =
15682 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15683 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15684 Ld->getAlignment());
15685 Chains.push_back(ScalarLoad.getValue(1));
15686 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15687 // another round of DAGCombining.
15689 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15691 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15692 ScalarLoad, DAG.getIntPtrConstant(i));
15694 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15697 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15699 // Bitcast the loaded value to a vector of the original element type, in
15700 // the size of the target vector type.
15701 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15702 unsigned SizeRatio = RegSz / MemSz;
15704 if (Ext == ISD::SEXTLOAD) {
15705 // If we have SSE4.1, we can directly emit a VSEXT node.
15706 if (Subtarget->hasSSE41()) {
15707 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15708 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15712 // Otherwise we'll shuffle the small elements in the high bits of the
15713 // larger type and perform an arithmetic shift. If the shift is not legal
15714 // it's better to scalarize.
15715 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15716 "We can't implement a sext load without an arithmetic right shift!");
15718 // Redistribute the loaded elements into the different locations.
15719 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15720 for (unsigned i = 0; i != NumElems; ++i)
15721 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15723 SDValue Shuff = DAG.getVectorShuffle(
15724 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15726 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15728 // Build the arithmetic shift.
15729 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15730 MemVT.getVectorElementType().getSizeInBits();
15732 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15734 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15738 // Redistribute the loaded elements into the different locations.
15739 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15740 for (unsigned i = 0; i != NumElems; ++i)
15741 ShuffleVec[i * SizeRatio] = i;
15743 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15744 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15746 // Bitcast to the requested type.
15747 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15748 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15752 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15753 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15754 // from the AND / OR.
15755 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15756 Opc = Op.getOpcode();
15757 if (Opc != ISD::OR && Opc != ISD::AND)
15759 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15760 Op.getOperand(0).hasOneUse() &&
15761 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15762 Op.getOperand(1).hasOneUse());
15765 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15766 // 1 and that the SETCC node has a single use.
15767 static bool isXor1OfSetCC(SDValue Op) {
15768 if (Op.getOpcode() != ISD::XOR)
15770 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15771 if (N1C && N1C->getAPIntValue() == 1) {
15772 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15773 Op.getOperand(0).hasOneUse();
15778 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15779 bool addTest = true;
15780 SDValue Chain = Op.getOperand(0);
15781 SDValue Cond = Op.getOperand(1);
15782 SDValue Dest = Op.getOperand(2);
15785 bool Inverted = false;
15787 if (Cond.getOpcode() == ISD::SETCC) {
15788 // Check for setcc([su]{add,sub,mul}o == 0).
15789 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15790 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15791 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15792 Cond.getOperand(0).getResNo() == 1 &&
15793 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15794 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15795 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15796 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15797 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15798 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15800 Cond = Cond.getOperand(0);
15802 SDValue NewCond = LowerSETCC(Cond, DAG);
15803 if (NewCond.getNode())
15808 // FIXME: LowerXALUO doesn't handle these!!
15809 else if (Cond.getOpcode() == X86ISD::ADD ||
15810 Cond.getOpcode() == X86ISD::SUB ||
15811 Cond.getOpcode() == X86ISD::SMUL ||
15812 Cond.getOpcode() == X86ISD::UMUL)
15813 Cond = LowerXALUO(Cond, DAG);
15816 // Look pass (and (setcc_carry (cmp ...)), 1).
15817 if (Cond.getOpcode() == ISD::AND &&
15818 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15819 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15820 if (C && C->getAPIntValue() == 1)
15821 Cond = Cond.getOperand(0);
15824 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15825 // setting operand in place of the X86ISD::SETCC.
15826 unsigned CondOpcode = Cond.getOpcode();
15827 if (CondOpcode == X86ISD::SETCC ||
15828 CondOpcode == X86ISD::SETCC_CARRY) {
15829 CC = Cond.getOperand(0);
15831 SDValue Cmp = Cond.getOperand(1);
15832 unsigned Opc = Cmp.getOpcode();
15833 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15834 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15838 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15842 // These can only come from an arithmetic instruction with overflow,
15843 // e.g. SADDO, UADDO.
15844 Cond = Cond.getNode()->getOperand(1);
15850 CondOpcode = Cond.getOpcode();
15851 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15852 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15853 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15854 Cond.getOperand(0).getValueType() != MVT::i8)) {
15855 SDValue LHS = Cond.getOperand(0);
15856 SDValue RHS = Cond.getOperand(1);
15857 unsigned X86Opcode;
15860 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15861 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15863 switch (CondOpcode) {
15864 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15866 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15868 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15871 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15872 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15874 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15876 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15879 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15880 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15881 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15882 default: llvm_unreachable("unexpected overflowing operator");
15885 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15886 if (CondOpcode == ISD::UMULO)
15887 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15890 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15892 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15894 if (CondOpcode == ISD::UMULO)
15895 Cond = X86Op.getValue(2);
15897 Cond = X86Op.getValue(1);
15899 CC = DAG.getConstant(X86Cond, MVT::i8);
15903 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15904 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15905 if (CondOpc == ISD::OR) {
15906 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15907 // two branches instead of an explicit OR instruction with a
15909 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15910 isX86LogicalCmp(Cmp)) {
15911 CC = Cond.getOperand(0).getOperand(0);
15912 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15913 Chain, Dest, CC, Cmp);
15914 CC = Cond.getOperand(1).getOperand(0);
15918 } else { // ISD::AND
15919 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15920 // two branches instead of an explicit AND instruction with a
15921 // separate test. However, we only do this if this block doesn't
15922 // have a fall-through edge, because this requires an explicit
15923 // jmp when the condition is false.
15924 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15925 isX86LogicalCmp(Cmp) &&
15926 Op.getNode()->hasOneUse()) {
15927 X86::CondCode CCode =
15928 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15929 CCode = X86::GetOppositeBranchCondition(CCode);
15930 CC = DAG.getConstant(CCode, MVT::i8);
15931 SDNode *User = *Op.getNode()->use_begin();
15932 // Look for an unconditional branch following this conditional branch.
15933 // We need this because we need to reverse the successors in order
15934 // to implement FCMP_OEQ.
15935 if (User->getOpcode() == ISD::BR) {
15936 SDValue FalseBB = User->getOperand(1);
15938 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15939 assert(NewBR == User);
15943 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15944 Chain, Dest, CC, Cmp);
15945 X86::CondCode CCode =
15946 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15947 CCode = X86::GetOppositeBranchCondition(CCode);
15948 CC = DAG.getConstant(CCode, MVT::i8);
15954 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15955 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15956 // It should be transformed during dag combiner except when the condition
15957 // is set by a arithmetics with overflow node.
15958 X86::CondCode CCode =
15959 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15960 CCode = X86::GetOppositeBranchCondition(CCode);
15961 CC = DAG.getConstant(CCode, MVT::i8);
15962 Cond = Cond.getOperand(0).getOperand(1);
15964 } else if (Cond.getOpcode() == ISD::SETCC &&
15965 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15966 // For FCMP_OEQ, we can emit
15967 // two branches instead of an explicit AND instruction with a
15968 // separate test. However, we only do this if this block doesn't
15969 // have a fall-through edge, because this requires an explicit
15970 // jmp when the condition is false.
15971 if (Op.getNode()->hasOneUse()) {
15972 SDNode *User = *Op.getNode()->use_begin();
15973 // Look for an unconditional branch following this conditional branch.
15974 // We need this because we need to reverse the successors in order
15975 // to implement FCMP_OEQ.
15976 if (User->getOpcode() == ISD::BR) {
15977 SDValue FalseBB = User->getOperand(1);
15979 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15980 assert(NewBR == User);
15984 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15985 Cond.getOperand(0), Cond.getOperand(1));
15986 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15987 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15988 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15989 Chain, Dest, CC, Cmp);
15990 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15995 } else if (Cond.getOpcode() == ISD::SETCC &&
15996 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15997 // For FCMP_UNE, we can emit
15998 // two branches instead of an explicit AND instruction with a
15999 // separate test. However, we only do this if this block doesn't
16000 // have a fall-through edge, because this requires an explicit
16001 // jmp when the condition is false.
16002 if (Op.getNode()->hasOneUse()) {
16003 SDNode *User = *Op.getNode()->use_begin();
16004 // Look for an unconditional branch following this conditional branch.
16005 // We need this because we need to reverse the successors in order
16006 // to implement FCMP_UNE.
16007 if (User->getOpcode() == ISD::BR) {
16008 SDValue FalseBB = User->getOperand(1);
16010 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16011 assert(NewBR == User);
16014 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16015 Cond.getOperand(0), Cond.getOperand(1));
16016 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16017 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16018 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16019 Chain, Dest, CC, Cmp);
16020 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16030 // Look pass the truncate if the high bits are known zero.
16031 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16032 Cond = Cond.getOperand(0);
16034 // We know the result of AND is compared against zero. Try to match
16036 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16037 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16038 if (NewSetCC.getNode()) {
16039 CC = NewSetCC.getOperand(0);
16040 Cond = NewSetCC.getOperand(1);
16047 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16048 CC = DAG.getConstant(X86Cond, MVT::i8);
16049 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16051 Cond = ConvertCmpIfNecessary(Cond, DAG);
16052 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16053 Chain, Dest, CC, Cond);
16056 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16057 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16058 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16059 // that the guard pages used by the OS virtual memory manager are allocated in
16060 // correct sequence.
16062 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16063 SelectionDAG &DAG) const {
16064 MachineFunction &MF = DAG.getMachineFunction();
16065 bool SplitStack = MF.shouldSplitStack();
16066 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16071 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16072 SDNode* Node = Op.getNode();
16074 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16075 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16076 " not tell us which reg is the stack pointer!");
16077 EVT VT = Node->getValueType(0);
16078 SDValue Tmp1 = SDValue(Node, 0);
16079 SDValue Tmp2 = SDValue(Node, 1);
16080 SDValue Tmp3 = Node->getOperand(2);
16081 SDValue Chain = Tmp1.getOperand(0);
16083 // Chain the dynamic stack allocation so that it doesn't modify the stack
16084 // pointer when other instructions are using the stack.
16085 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16088 SDValue Size = Tmp2.getOperand(1);
16089 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16090 Chain = SP.getValue(1);
16091 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16092 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16093 unsigned StackAlign = TFI.getStackAlignment();
16094 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16095 if (Align > StackAlign)
16096 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16097 DAG.getConstant(-(uint64_t)Align, VT));
16098 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16100 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16101 DAG.getIntPtrConstant(0, true), SDValue(),
16104 SDValue Ops[2] = { Tmp1, Tmp2 };
16105 return DAG.getMergeValues(Ops, dl);
16109 SDValue Chain = Op.getOperand(0);
16110 SDValue Size = Op.getOperand(1);
16111 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16112 EVT VT = Op.getNode()->getValueType(0);
16114 bool Is64Bit = Subtarget->is64Bit();
16115 EVT SPTy = getPointerTy();
16118 MachineRegisterInfo &MRI = MF.getRegInfo();
16121 // The 64 bit implementation of segmented stacks needs to clobber both r10
16122 // r11. This makes it impossible to use it along with nested parameters.
16123 const Function *F = MF.getFunction();
16125 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16127 if (I->hasNestAttr())
16128 report_fatal_error("Cannot use segmented stacks with functions that "
16129 "have nested arguments.");
16132 const TargetRegisterClass *AddrRegClass =
16133 getRegClassFor(getPointerTy());
16134 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16135 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16136 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16137 DAG.getRegister(Vreg, SPTy));
16138 SDValue Ops1[2] = { Value, Chain };
16139 return DAG.getMergeValues(Ops1, dl);
16142 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16144 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16145 Flag = Chain.getValue(1);
16146 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16148 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16150 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16151 DAG.getSubtarget().getRegisterInfo());
16152 unsigned SPReg = RegInfo->getStackRegister();
16153 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16154 Chain = SP.getValue(1);
16157 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16158 DAG.getConstant(-(uint64_t)Align, VT));
16159 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16162 SDValue Ops1[2] = { SP, Chain };
16163 return DAG.getMergeValues(Ops1, dl);
16167 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16168 MachineFunction &MF = DAG.getMachineFunction();
16169 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16171 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16174 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16175 // vastart just stores the address of the VarArgsFrameIndex slot into the
16176 // memory location argument.
16177 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16179 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16180 MachinePointerInfo(SV), false, false, 0);
16184 // gp_offset (0 - 6 * 8)
16185 // fp_offset (48 - 48 + 8 * 16)
16186 // overflow_arg_area (point to parameters coming in memory).
16188 SmallVector<SDValue, 8> MemOps;
16189 SDValue FIN = Op.getOperand(1);
16191 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16192 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16194 FIN, MachinePointerInfo(SV), false, false, 0);
16195 MemOps.push_back(Store);
16198 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16199 FIN, DAG.getIntPtrConstant(4));
16200 Store = DAG.getStore(Op.getOperand(0), DL,
16201 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16203 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16204 MemOps.push_back(Store);
16206 // Store ptr to overflow_arg_area
16207 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16208 FIN, DAG.getIntPtrConstant(4));
16209 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16211 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16212 MachinePointerInfo(SV, 8),
16214 MemOps.push_back(Store);
16216 // Store ptr to reg_save_area.
16217 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16218 FIN, DAG.getIntPtrConstant(8));
16219 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16221 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16222 MachinePointerInfo(SV, 16), false, false, 0);
16223 MemOps.push_back(Store);
16224 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16227 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16228 assert(Subtarget->is64Bit() &&
16229 "LowerVAARG only handles 64-bit va_arg!");
16230 assert((Subtarget->isTargetLinux() ||
16231 Subtarget->isTargetDarwin()) &&
16232 "Unhandled target in LowerVAARG");
16233 assert(Op.getNode()->getNumOperands() == 4);
16234 SDValue Chain = Op.getOperand(0);
16235 SDValue SrcPtr = Op.getOperand(1);
16236 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16237 unsigned Align = Op.getConstantOperandVal(3);
16240 EVT ArgVT = Op.getNode()->getValueType(0);
16241 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16242 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16245 // Decide which area this value should be read from.
16246 // TODO: Implement the AMD64 ABI in its entirety. This simple
16247 // selection mechanism works only for the basic types.
16248 if (ArgVT == MVT::f80) {
16249 llvm_unreachable("va_arg for f80 not yet implemented");
16250 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16251 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16252 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16253 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16255 llvm_unreachable("Unhandled argument type in LowerVAARG");
16258 if (ArgMode == 2) {
16259 // Sanity Check: Make sure using fp_offset makes sense.
16260 assert(!DAG.getTarget().Options.UseSoftFloat &&
16261 !(DAG.getMachineFunction()
16262 .getFunction()->getAttributes()
16263 .hasAttribute(AttributeSet::FunctionIndex,
16264 Attribute::NoImplicitFloat)) &&
16265 Subtarget->hasSSE1());
16268 // Insert VAARG_64 node into the DAG
16269 // VAARG_64 returns two values: Variable Argument Address, Chain
16270 SmallVector<SDValue, 11> InstOps;
16271 InstOps.push_back(Chain);
16272 InstOps.push_back(SrcPtr);
16273 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16274 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16275 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16276 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16277 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16278 VTs, InstOps, MVT::i64,
16279 MachinePointerInfo(SV),
16281 /*Volatile=*/false,
16283 /*WriteMem=*/true);
16284 Chain = VAARG.getValue(1);
16286 // Load the next argument and return it
16287 return DAG.getLoad(ArgVT, dl,
16290 MachinePointerInfo(),
16291 false, false, false, 0);
16294 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16295 SelectionDAG &DAG) {
16296 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16297 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16298 SDValue Chain = Op.getOperand(0);
16299 SDValue DstPtr = Op.getOperand(1);
16300 SDValue SrcPtr = Op.getOperand(2);
16301 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16302 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16305 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16306 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16308 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16311 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16312 // amount is a constant. Takes immediate version of shift as input.
16313 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16314 SDValue SrcOp, uint64_t ShiftAmt,
16315 SelectionDAG &DAG) {
16316 MVT ElementType = VT.getVectorElementType();
16318 // Fold this packed shift into its first operand if ShiftAmt is 0.
16322 // Check for ShiftAmt >= element width
16323 if (ShiftAmt >= ElementType.getSizeInBits()) {
16324 if (Opc == X86ISD::VSRAI)
16325 ShiftAmt = ElementType.getSizeInBits() - 1;
16327 return DAG.getConstant(0, VT);
16330 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16331 && "Unknown target vector shift-by-constant node");
16333 // Fold this packed vector shift into a build vector if SrcOp is a
16334 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16335 if (VT == SrcOp.getSimpleValueType() &&
16336 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16337 SmallVector<SDValue, 8> Elts;
16338 unsigned NumElts = SrcOp->getNumOperands();
16339 ConstantSDNode *ND;
16342 default: llvm_unreachable(nullptr);
16343 case X86ISD::VSHLI:
16344 for (unsigned i=0; i!=NumElts; ++i) {
16345 SDValue CurrentOp = SrcOp->getOperand(i);
16346 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16347 Elts.push_back(CurrentOp);
16350 ND = cast<ConstantSDNode>(CurrentOp);
16351 const APInt &C = ND->getAPIntValue();
16352 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16355 case X86ISD::VSRLI:
16356 for (unsigned i=0; i!=NumElts; ++i) {
16357 SDValue CurrentOp = SrcOp->getOperand(i);
16358 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16359 Elts.push_back(CurrentOp);
16362 ND = cast<ConstantSDNode>(CurrentOp);
16363 const APInt &C = ND->getAPIntValue();
16364 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16367 case X86ISD::VSRAI:
16368 for (unsigned i=0; i!=NumElts; ++i) {
16369 SDValue CurrentOp = SrcOp->getOperand(i);
16370 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16371 Elts.push_back(CurrentOp);
16374 ND = cast<ConstantSDNode>(CurrentOp);
16375 const APInt &C = ND->getAPIntValue();
16376 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16381 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16384 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16387 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16388 // may or may not be a constant. Takes immediate version of shift as input.
16389 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16390 SDValue SrcOp, SDValue ShAmt,
16391 SelectionDAG &DAG) {
16392 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16394 // Catch shift-by-constant.
16395 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16396 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16397 CShAmt->getZExtValue(), DAG);
16399 // Change opcode to non-immediate version
16401 default: llvm_unreachable("Unknown target vector shift node");
16402 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16403 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16404 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16407 // Need to build a vector containing shift amount
16408 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16411 ShOps[1] = DAG.getConstant(0, MVT::i32);
16412 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16413 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16415 // The return type has to be a 128-bit type with the same element
16416 // type as the input type.
16417 MVT EltVT = VT.getVectorElementType();
16418 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16420 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16421 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16424 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16425 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16426 /// necessary casting for \p Mask when lowering masking intrinsics.
16427 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16428 SDValue PreservedSrc,
16429 const X86Subtarget *Subtarget,
16430 SelectionDAG &DAG) {
16431 EVT VT = Op.getValueType();
16432 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16433 MVT::i1, VT.getVectorNumElements());
16434 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16435 Mask.getValueType().getSizeInBits());
16438 assert(MaskVT.isSimple() && "invalid mask type");
16440 if (isAllOnes(Mask))
16443 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16444 // are extracted by EXTRACT_SUBVECTOR.
16445 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16446 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16447 DAG.getIntPtrConstant(0));
16449 switch (Op.getOpcode()) {
16451 case X86ISD::PCMPEQM:
16452 case X86ISD::PCMPGTM:
16454 case X86ISD::CMPMU:
16455 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16457 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16458 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16459 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16462 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16464 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16465 case Intrinsic::x86_fma_vfmadd_ps:
16466 case Intrinsic::x86_fma_vfmadd_pd:
16467 case Intrinsic::x86_fma_vfmadd_ps_256:
16468 case Intrinsic::x86_fma_vfmadd_pd_256:
16469 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16470 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16471 return X86ISD::FMADD;
16472 case Intrinsic::x86_fma_vfmsub_ps:
16473 case Intrinsic::x86_fma_vfmsub_pd:
16474 case Intrinsic::x86_fma_vfmsub_ps_256:
16475 case Intrinsic::x86_fma_vfmsub_pd_256:
16476 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16477 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16478 return X86ISD::FMSUB;
16479 case Intrinsic::x86_fma_vfnmadd_ps:
16480 case Intrinsic::x86_fma_vfnmadd_pd:
16481 case Intrinsic::x86_fma_vfnmadd_ps_256:
16482 case Intrinsic::x86_fma_vfnmadd_pd_256:
16483 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16484 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16485 return X86ISD::FNMADD;
16486 case Intrinsic::x86_fma_vfnmsub_ps:
16487 case Intrinsic::x86_fma_vfnmsub_pd:
16488 case Intrinsic::x86_fma_vfnmsub_ps_256:
16489 case Intrinsic::x86_fma_vfnmsub_pd_256:
16490 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16491 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16492 return X86ISD::FNMSUB;
16493 case Intrinsic::x86_fma_vfmaddsub_ps:
16494 case Intrinsic::x86_fma_vfmaddsub_pd:
16495 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16496 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16497 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16498 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16499 return X86ISD::FMADDSUB;
16500 case Intrinsic::x86_fma_vfmsubadd_ps:
16501 case Intrinsic::x86_fma_vfmsubadd_pd:
16502 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16503 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16504 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16505 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16506 return X86ISD::FMSUBADD;
16510 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16511 SelectionDAG &DAG) {
16513 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16514 EVT VT = Op.getValueType();
16515 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16517 switch(IntrData->Type) {
16518 case INTR_TYPE_1OP:
16519 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16520 case INTR_TYPE_2OP:
16521 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16523 case INTR_TYPE_3OP:
16524 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16525 Op.getOperand(2), Op.getOperand(3));
16526 case INTR_TYPE_1OP_MASK_RM: {
16527 SDValue Src = Op.getOperand(1);
16528 SDValue Src0 = Op.getOperand(2);
16529 SDValue Mask = Op.getOperand(3);
16530 SDValue RoundingMode = Op.getOperand(4);
16531 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16533 Mask, Src0, Subtarget, DAG);
16537 case CMP_MASK_CC: {
16538 // Comparison intrinsics with masks.
16539 // Example of transformation:
16540 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16541 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16543 // (v8i1 (insert_subvector undef,
16544 // (v2i1 (and (PCMPEQM %a, %b),
16545 // (extract_subvector
16546 // (v8i1 (bitcast %mask)), 0))), 0))))
16547 EVT VT = Op.getOperand(1).getValueType();
16548 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16549 VT.getVectorNumElements());
16550 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16551 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16552 Mask.getValueType().getSizeInBits());
16554 if (IntrData->Type == CMP_MASK_CC) {
16555 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16556 Op.getOperand(2), Op.getOperand(3));
16558 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16559 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16562 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16563 DAG.getTargetConstant(0, MaskVT),
16565 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16566 DAG.getUNDEF(BitcastVT), CmpMask,
16567 DAG.getIntPtrConstant(0));
16568 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16570 case COMI: { // Comparison intrinsics
16571 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16572 SDValue LHS = Op.getOperand(1);
16573 SDValue RHS = Op.getOperand(2);
16574 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16575 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16576 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16577 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16578 DAG.getConstant(X86CC, MVT::i8), Cond);
16579 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16582 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16583 Op.getOperand(1), Op.getOperand(2), DAG);
16585 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16586 Op.getOperand(1), Op.getOperand(2), DAG),
16587 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);;
16594 default: return SDValue(); // Don't custom lower most intrinsics.
16596 // Arithmetic intrinsics.
16597 case Intrinsic::x86_sse2_pmulu_dq:
16598 case Intrinsic::x86_avx2_pmulu_dq:
16599 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16600 Op.getOperand(1), Op.getOperand(2));
16602 case Intrinsic::x86_sse41_pmuldq:
16603 case Intrinsic::x86_avx2_pmul_dq:
16604 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16605 Op.getOperand(1), Op.getOperand(2));
16607 case Intrinsic::x86_sse2_pmulhu_w:
16608 case Intrinsic::x86_avx2_pmulhu_w:
16609 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16610 Op.getOperand(1), Op.getOperand(2));
16612 case Intrinsic::x86_sse2_pmulh_w:
16613 case Intrinsic::x86_avx2_pmulh_w:
16614 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16615 Op.getOperand(1), Op.getOperand(2));
16617 // SSE/SSE2/AVX floating point max/min intrinsics.
16618 case Intrinsic::x86_sse_max_ps:
16619 case Intrinsic::x86_sse2_max_pd:
16620 case Intrinsic::x86_avx_max_ps_256:
16621 case Intrinsic::x86_avx_max_pd_256:
16622 case Intrinsic::x86_sse_min_ps:
16623 case Intrinsic::x86_sse2_min_pd:
16624 case Intrinsic::x86_avx_min_ps_256:
16625 case Intrinsic::x86_avx_min_pd_256: {
16628 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16629 case Intrinsic::x86_sse_max_ps:
16630 case Intrinsic::x86_sse2_max_pd:
16631 case Intrinsic::x86_avx_max_ps_256:
16632 case Intrinsic::x86_avx_max_pd_256:
16633 Opcode = X86ISD::FMAX;
16635 case Intrinsic::x86_sse_min_ps:
16636 case Intrinsic::x86_sse2_min_pd:
16637 case Intrinsic::x86_avx_min_ps_256:
16638 case Intrinsic::x86_avx_min_pd_256:
16639 Opcode = X86ISD::FMIN;
16642 return DAG.getNode(Opcode, dl, Op.getValueType(),
16643 Op.getOperand(1), Op.getOperand(2));
16646 // AVX2 variable shift intrinsics
16647 case Intrinsic::x86_avx2_psllv_d:
16648 case Intrinsic::x86_avx2_psllv_q:
16649 case Intrinsic::x86_avx2_psllv_d_256:
16650 case Intrinsic::x86_avx2_psllv_q_256:
16651 case Intrinsic::x86_avx2_psrlv_d:
16652 case Intrinsic::x86_avx2_psrlv_q:
16653 case Intrinsic::x86_avx2_psrlv_d_256:
16654 case Intrinsic::x86_avx2_psrlv_q_256:
16655 case Intrinsic::x86_avx2_psrav_d:
16656 case Intrinsic::x86_avx2_psrav_d_256: {
16659 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16660 case Intrinsic::x86_avx2_psllv_d:
16661 case Intrinsic::x86_avx2_psllv_q:
16662 case Intrinsic::x86_avx2_psllv_d_256:
16663 case Intrinsic::x86_avx2_psllv_q_256:
16666 case Intrinsic::x86_avx2_psrlv_d:
16667 case Intrinsic::x86_avx2_psrlv_q:
16668 case Intrinsic::x86_avx2_psrlv_d_256:
16669 case Intrinsic::x86_avx2_psrlv_q_256:
16672 case Intrinsic::x86_avx2_psrav_d:
16673 case Intrinsic::x86_avx2_psrav_d_256:
16677 return DAG.getNode(Opcode, dl, Op.getValueType(),
16678 Op.getOperand(1), Op.getOperand(2));
16681 case Intrinsic::x86_sse2_packssdw_128:
16682 case Intrinsic::x86_sse2_packsswb_128:
16683 case Intrinsic::x86_avx2_packssdw:
16684 case Intrinsic::x86_avx2_packsswb:
16685 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16686 Op.getOperand(1), Op.getOperand(2));
16688 case Intrinsic::x86_sse2_packuswb_128:
16689 case Intrinsic::x86_sse41_packusdw:
16690 case Intrinsic::x86_avx2_packuswb:
16691 case Intrinsic::x86_avx2_packusdw:
16692 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16693 Op.getOperand(1), Op.getOperand(2));
16695 case Intrinsic::x86_ssse3_pshuf_b_128:
16696 case Intrinsic::x86_avx2_pshuf_b:
16697 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16698 Op.getOperand(1), Op.getOperand(2));
16700 case Intrinsic::x86_sse2_pshuf_d:
16701 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16702 Op.getOperand(1), Op.getOperand(2));
16704 case Intrinsic::x86_sse2_pshufl_w:
16705 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16706 Op.getOperand(1), Op.getOperand(2));
16708 case Intrinsic::x86_sse2_pshufh_w:
16709 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16710 Op.getOperand(1), Op.getOperand(2));
16712 case Intrinsic::x86_ssse3_psign_b_128:
16713 case Intrinsic::x86_ssse3_psign_w_128:
16714 case Intrinsic::x86_ssse3_psign_d_128:
16715 case Intrinsic::x86_avx2_psign_b:
16716 case Intrinsic::x86_avx2_psign_w:
16717 case Intrinsic::x86_avx2_psign_d:
16718 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16719 Op.getOperand(1), Op.getOperand(2));
16721 case Intrinsic::x86_avx2_permd:
16722 case Intrinsic::x86_avx2_permps:
16723 // Operands intentionally swapped. Mask is last operand to intrinsic,
16724 // but second operand for node/instruction.
16725 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16726 Op.getOperand(2), Op.getOperand(1));
16728 case Intrinsic::x86_avx512_mask_valign_q_512:
16729 case Intrinsic::x86_avx512_mask_valign_d_512:
16730 // Vector source operands are swapped.
16731 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16732 Op.getValueType(), Op.getOperand(2),
16735 Op.getOperand(5), Op.getOperand(4),
16738 // ptest and testp intrinsics. The intrinsic these come from are designed to
16739 // return an integer value, not just an instruction so lower it to the ptest
16740 // or testp pattern and a setcc for the result.
16741 case Intrinsic::x86_sse41_ptestz:
16742 case Intrinsic::x86_sse41_ptestc:
16743 case Intrinsic::x86_sse41_ptestnzc:
16744 case Intrinsic::x86_avx_ptestz_256:
16745 case Intrinsic::x86_avx_ptestc_256:
16746 case Intrinsic::x86_avx_ptestnzc_256:
16747 case Intrinsic::x86_avx_vtestz_ps:
16748 case Intrinsic::x86_avx_vtestc_ps:
16749 case Intrinsic::x86_avx_vtestnzc_ps:
16750 case Intrinsic::x86_avx_vtestz_pd:
16751 case Intrinsic::x86_avx_vtestc_pd:
16752 case Intrinsic::x86_avx_vtestnzc_pd:
16753 case Intrinsic::x86_avx_vtestz_ps_256:
16754 case Intrinsic::x86_avx_vtestc_ps_256:
16755 case Intrinsic::x86_avx_vtestnzc_ps_256:
16756 case Intrinsic::x86_avx_vtestz_pd_256:
16757 case Intrinsic::x86_avx_vtestc_pd_256:
16758 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16759 bool IsTestPacked = false;
16762 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16763 case Intrinsic::x86_avx_vtestz_ps:
16764 case Intrinsic::x86_avx_vtestz_pd:
16765 case Intrinsic::x86_avx_vtestz_ps_256:
16766 case Intrinsic::x86_avx_vtestz_pd_256:
16767 IsTestPacked = true; // Fallthrough
16768 case Intrinsic::x86_sse41_ptestz:
16769 case Intrinsic::x86_avx_ptestz_256:
16771 X86CC = X86::COND_E;
16773 case Intrinsic::x86_avx_vtestc_ps:
16774 case Intrinsic::x86_avx_vtestc_pd:
16775 case Intrinsic::x86_avx_vtestc_ps_256:
16776 case Intrinsic::x86_avx_vtestc_pd_256:
16777 IsTestPacked = true; // Fallthrough
16778 case Intrinsic::x86_sse41_ptestc:
16779 case Intrinsic::x86_avx_ptestc_256:
16781 X86CC = X86::COND_B;
16783 case Intrinsic::x86_avx_vtestnzc_ps:
16784 case Intrinsic::x86_avx_vtestnzc_pd:
16785 case Intrinsic::x86_avx_vtestnzc_ps_256:
16786 case Intrinsic::x86_avx_vtestnzc_pd_256:
16787 IsTestPacked = true; // Fallthrough
16788 case Intrinsic::x86_sse41_ptestnzc:
16789 case Intrinsic::x86_avx_ptestnzc_256:
16791 X86CC = X86::COND_A;
16795 SDValue LHS = Op.getOperand(1);
16796 SDValue RHS = Op.getOperand(2);
16797 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16798 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16799 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16800 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16801 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16803 case Intrinsic::x86_avx512_kortestz_w:
16804 case Intrinsic::x86_avx512_kortestc_w: {
16805 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16806 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16807 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16808 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16809 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16810 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16811 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16814 case Intrinsic::x86_sse42_pcmpistria128:
16815 case Intrinsic::x86_sse42_pcmpestria128:
16816 case Intrinsic::x86_sse42_pcmpistric128:
16817 case Intrinsic::x86_sse42_pcmpestric128:
16818 case Intrinsic::x86_sse42_pcmpistrio128:
16819 case Intrinsic::x86_sse42_pcmpestrio128:
16820 case Intrinsic::x86_sse42_pcmpistris128:
16821 case Intrinsic::x86_sse42_pcmpestris128:
16822 case Intrinsic::x86_sse42_pcmpistriz128:
16823 case Intrinsic::x86_sse42_pcmpestriz128: {
16827 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16828 case Intrinsic::x86_sse42_pcmpistria128:
16829 Opcode = X86ISD::PCMPISTRI;
16830 X86CC = X86::COND_A;
16832 case Intrinsic::x86_sse42_pcmpestria128:
16833 Opcode = X86ISD::PCMPESTRI;
16834 X86CC = X86::COND_A;
16836 case Intrinsic::x86_sse42_pcmpistric128:
16837 Opcode = X86ISD::PCMPISTRI;
16838 X86CC = X86::COND_B;
16840 case Intrinsic::x86_sse42_pcmpestric128:
16841 Opcode = X86ISD::PCMPESTRI;
16842 X86CC = X86::COND_B;
16844 case Intrinsic::x86_sse42_pcmpistrio128:
16845 Opcode = X86ISD::PCMPISTRI;
16846 X86CC = X86::COND_O;
16848 case Intrinsic::x86_sse42_pcmpestrio128:
16849 Opcode = X86ISD::PCMPESTRI;
16850 X86CC = X86::COND_O;
16852 case Intrinsic::x86_sse42_pcmpistris128:
16853 Opcode = X86ISD::PCMPISTRI;
16854 X86CC = X86::COND_S;
16856 case Intrinsic::x86_sse42_pcmpestris128:
16857 Opcode = X86ISD::PCMPESTRI;
16858 X86CC = X86::COND_S;
16860 case Intrinsic::x86_sse42_pcmpistriz128:
16861 Opcode = X86ISD::PCMPISTRI;
16862 X86CC = X86::COND_E;
16864 case Intrinsic::x86_sse42_pcmpestriz128:
16865 Opcode = X86ISD::PCMPESTRI;
16866 X86CC = X86::COND_E;
16869 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16870 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16871 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16872 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16873 DAG.getConstant(X86CC, MVT::i8),
16874 SDValue(PCMP.getNode(), 1));
16875 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16878 case Intrinsic::x86_sse42_pcmpistri128:
16879 case Intrinsic::x86_sse42_pcmpestri128: {
16881 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16882 Opcode = X86ISD::PCMPISTRI;
16884 Opcode = X86ISD::PCMPESTRI;
16886 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16887 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16888 return DAG.getNode(Opcode, dl, VTs, NewOps);
16891 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16892 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16893 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16894 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16895 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16896 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16897 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16898 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16899 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16900 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16901 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16902 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16903 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16904 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16905 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16906 dl, Op.getValueType(),
16910 Op.getOperand(4), Op.getOperand(1),
16916 case Intrinsic::x86_fma_vfmadd_ps:
16917 case Intrinsic::x86_fma_vfmadd_pd:
16918 case Intrinsic::x86_fma_vfmsub_ps:
16919 case Intrinsic::x86_fma_vfmsub_pd:
16920 case Intrinsic::x86_fma_vfnmadd_ps:
16921 case Intrinsic::x86_fma_vfnmadd_pd:
16922 case Intrinsic::x86_fma_vfnmsub_ps:
16923 case Intrinsic::x86_fma_vfnmsub_pd:
16924 case Intrinsic::x86_fma_vfmaddsub_ps:
16925 case Intrinsic::x86_fma_vfmaddsub_pd:
16926 case Intrinsic::x86_fma_vfmsubadd_ps:
16927 case Intrinsic::x86_fma_vfmsubadd_pd:
16928 case Intrinsic::x86_fma_vfmadd_ps_256:
16929 case Intrinsic::x86_fma_vfmadd_pd_256:
16930 case Intrinsic::x86_fma_vfmsub_ps_256:
16931 case Intrinsic::x86_fma_vfmsub_pd_256:
16932 case Intrinsic::x86_fma_vfnmadd_ps_256:
16933 case Intrinsic::x86_fma_vfnmadd_pd_256:
16934 case Intrinsic::x86_fma_vfnmsub_ps_256:
16935 case Intrinsic::x86_fma_vfnmsub_pd_256:
16936 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16937 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16938 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16939 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16940 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16941 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16945 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16946 SDValue Src, SDValue Mask, SDValue Base,
16947 SDValue Index, SDValue ScaleOp, SDValue Chain,
16948 const X86Subtarget * Subtarget) {
16950 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16951 assert(C && "Invalid scale type");
16952 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16953 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16954 Index.getSimpleValueType().getVectorNumElements());
16956 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16958 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16960 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16961 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16962 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16963 SDValue Segment = DAG.getRegister(0, MVT::i32);
16964 if (Src.getOpcode() == ISD::UNDEF)
16965 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16966 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16967 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16968 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16969 return DAG.getMergeValues(RetOps, dl);
16972 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16973 SDValue Src, SDValue Mask, SDValue Base,
16974 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16976 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16977 assert(C && "Invalid scale type");
16978 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16979 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16980 SDValue Segment = DAG.getRegister(0, MVT::i32);
16981 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16982 Index.getSimpleValueType().getVectorNumElements());
16984 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16986 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16988 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16989 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16990 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16991 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16992 return SDValue(Res, 1);
16995 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16996 SDValue Mask, SDValue Base, SDValue Index,
16997 SDValue ScaleOp, SDValue Chain) {
16999 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17000 assert(C && "Invalid scale type");
17001 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17002 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17003 SDValue Segment = DAG.getRegister(0, MVT::i32);
17005 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17007 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17009 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17011 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17012 //SDVTList VTs = DAG.getVTList(MVT::Other);
17013 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17014 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17015 return SDValue(Res, 0);
17018 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17019 // read performance monitor counters (x86_rdpmc).
17020 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17021 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17022 SmallVectorImpl<SDValue> &Results) {
17023 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17024 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17027 // The ECX register is used to select the index of the performance counter
17029 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17031 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17033 // Reads the content of a 64-bit performance counter and returns it in the
17034 // registers EDX:EAX.
17035 if (Subtarget->is64Bit()) {
17036 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17037 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17040 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17041 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17044 Chain = HI.getValue(1);
17046 if (Subtarget->is64Bit()) {
17047 // The EAX register is loaded with the low-order 32 bits. The EDX register
17048 // is loaded with the supported high-order bits of the counter.
17049 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17050 DAG.getConstant(32, MVT::i8));
17051 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17052 Results.push_back(Chain);
17056 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17057 SDValue Ops[] = { LO, HI };
17058 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17059 Results.push_back(Pair);
17060 Results.push_back(Chain);
17063 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17064 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17065 // also used to custom lower READCYCLECOUNTER nodes.
17066 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17067 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17068 SmallVectorImpl<SDValue> &Results) {
17069 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17070 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17073 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17074 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17075 // and the EAX register is loaded with the low-order 32 bits.
17076 if (Subtarget->is64Bit()) {
17077 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17078 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17081 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17082 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17085 SDValue Chain = HI.getValue(1);
17087 if (Opcode == X86ISD::RDTSCP_DAG) {
17088 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17090 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17091 // the ECX register. Add 'ecx' explicitly to the chain.
17092 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17094 // Explicitly store the content of ECX at the location passed in input
17095 // to the 'rdtscp' intrinsic.
17096 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17097 MachinePointerInfo(), false, false, 0);
17100 if (Subtarget->is64Bit()) {
17101 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17102 // the EAX register is loaded with the low-order 32 bits.
17103 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17104 DAG.getConstant(32, MVT::i8));
17105 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17106 Results.push_back(Chain);
17110 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17111 SDValue Ops[] = { LO, HI };
17112 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17113 Results.push_back(Pair);
17114 Results.push_back(Chain);
17117 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17118 SelectionDAG &DAG) {
17119 SmallVector<SDValue, 2> Results;
17121 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17123 return DAG.getMergeValues(Results, DL);
17127 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17128 SelectionDAG &DAG) {
17129 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17131 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17136 switch(IntrData->Type) {
17138 llvm_unreachable("Unknown Intrinsic Type");
17142 // Emit the node with the right value type.
17143 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17144 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17146 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17147 // Otherwise return the value from Rand, which is always 0, casted to i32.
17148 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17149 DAG.getConstant(1, Op->getValueType(1)),
17150 DAG.getConstant(X86::COND_B, MVT::i32),
17151 SDValue(Result.getNode(), 1) };
17152 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17153 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17156 // Return { result, isValid, chain }.
17157 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17158 SDValue(Result.getNode(), 2));
17161 //gather(v1, mask, index, base, scale);
17162 SDValue Chain = Op.getOperand(0);
17163 SDValue Src = Op.getOperand(2);
17164 SDValue Base = Op.getOperand(3);
17165 SDValue Index = Op.getOperand(4);
17166 SDValue Mask = Op.getOperand(5);
17167 SDValue Scale = Op.getOperand(6);
17168 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17172 //scatter(base, mask, index, v1, scale);
17173 SDValue Chain = Op.getOperand(0);
17174 SDValue Base = Op.getOperand(2);
17175 SDValue Mask = Op.getOperand(3);
17176 SDValue Index = Op.getOperand(4);
17177 SDValue Src = Op.getOperand(5);
17178 SDValue Scale = Op.getOperand(6);
17179 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17182 SDValue Hint = Op.getOperand(6);
17184 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17185 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17186 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17187 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17188 SDValue Chain = Op.getOperand(0);
17189 SDValue Mask = Op.getOperand(2);
17190 SDValue Index = Op.getOperand(3);
17191 SDValue Base = Op.getOperand(4);
17192 SDValue Scale = Op.getOperand(5);
17193 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17195 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17197 SmallVector<SDValue, 2> Results;
17198 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17199 return DAG.getMergeValues(Results, dl);
17201 // Read Performance Monitoring Counters.
17203 SmallVector<SDValue, 2> Results;
17204 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17205 return DAG.getMergeValues(Results, dl);
17207 // XTEST intrinsics.
17209 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17210 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17211 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17212 DAG.getConstant(X86::COND_NE, MVT::i8),
17214 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17215 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17216 Ret, SDValue(InTrans.getNode(), 1));
17220 SmallVector<SDValue, 2> Results;
17221 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17222 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17223 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17224 DAG.getConstant(-1, MVT::i8));
17225 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17226 Op.getOperand(4), GenCF.getValue(1));
17227 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17228 Op.getOperand(5), MachinePointerInfo(),
17230 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17231 DAG.getConstant(X86::COND_B, MVT::i8),
17233 Results.push_back(SetCC);
17234 Results.push_back(Store);
17235 return DAG.getMergeValues(Results, dl);
17240 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17241 SelectionDAG &DAG) const {
17242 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17243 MFI->setReturnAddressIsTaken(true);
17245 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17248 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17250 EVT PtrVT = getPointerTy();
17253 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17254 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17255 DAG.getSubtarget().getRegisterInfo());
17256 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17257 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17258 DAG.getNode(ISD::ADD, dl, PtrVT,
17259 FrameAddr, Offset),
17260 MachinePointerInfo(), false, false, false, 0);
17263 // Just load the return address.
17264 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17265 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17266 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17269 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17270 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17271 MFI->setFrameAddressIsTaken(true);
17273 EVT VT = Op.getValueType();
17274 SDLoc dl(Op); // FIXME probably not meaningful
17275 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17276 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17277 DAG.getSubtarget().getRegisterInfo());
17278 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17279 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17280 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17281 "Invalid Frame Register!");
17282 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17284 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17285 MachinePointerInfo(),
17286 false, false, false, 0);
17290 // FIXME? Maybe this could be a TableGen attribute on some registers and
17291 // this table could be generated automatically from RegInfo.
17292 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17294 unsigned Reg = StringSwitch<unsigned>(RegName)
17295 .Case("esp", X86::ESP)
17296 .Case("rsp", X86::RSP)
17300 report_fatal_error("Invalid register name global variable");
17303 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17304 SelectionDAG &DAG) const {
17305 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17306 DAG.getSubtarget().getRegisterInfo());
17307 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17310 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17311 SDValue Chain = Op.getOperand(0);
17312 SDValue Offset = Op.getOperand(1);
17313 SDValue Handler = Op.getOperand(2);
17316 EVT PtrVT = getPointerTy();
17317 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17318 DAG.getSubtarget().getRegisterInfo());
17319 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17320 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17321 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17322 "Invalid Frame Register!");
17323 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17324 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17326 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17327 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17328 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17329 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17331 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17333 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17334 DAG.getRegister(StoreAddrReg, PtrVT));
17337 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17338 SelectionDAG &DAG) const {
17340 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17341 DAG.getVTList(MVT::i32, MVT::Other),
17342 Op.getOperand(0), Op.getOperand(1));
17345 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17346 SelectionDAG &DAG) const {
17348 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17349 Op.getOperand(0), Op.getOperand(1));
17352 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17353 return Op.getOperand(0);
17356 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17357 SelectionDAG &DAG) const {
17358 SDValue Root = Op.getOperand(0);
17359 SDValue Trmp = Op.getOperand(1); // trampoline
17360 SDValue FPtr = Op.getOperand(2); // nested function
17361 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17364 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17365 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17367 if (Subtarget->is64Bit()) {
17368 SDValue OutChains[6];
17370 // Large code-model.
17371 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17372 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17374 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17375 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17377 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17379 // Load the pointer to the nested function into R11.
17380 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17381 SDValue Addr = Trmp;
17382 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17383 Addr, MachinePointerInfo(TrmpAddr),
17386 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17387 DAG.getConstant(2, MVT::i64));
17388 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17389 MachinePointerInfo(TrmpAddr, 2),
17392 // Load the 'nest' parameter value into R10.
17393 // R10 is specified in X86CallingConv.td
17394 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17395 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17396 DAG.getConstant(10, MVT::i64));
17397 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17398 Addr, MachinePointerInfo(TrmpAddr, 10),
17401 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17402 DAG.getConstant(12, MVT::i64));
17403 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17404 MachinePointerInfo(TrmpAddr, 12),
17407 // Jump to the nested function.
17408 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17409 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17410 DAG.getConstant(20, MVT::i64));
17411 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17412 Addr, MachinePointerInfo(TrmpAddr, 20),
17415 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17416 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17417 DAG.getConstant(22, MVT::i64));
17418 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17419 MachinePointerInfo(TrmpAddr, 22),
17422 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17424 const Function *Func =
17425 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17426 CallingConv::ID CC = Func->getCallingConv();
17431 llvm_unreachable("Unsupported calling convention");
17432 case CallingConv::C:
17433 case CallingConv::X86_StdCall: {
17434 // Pass 'nest' parameter in ECX.
17435 // Must be kept in sync with X86CallingConv.td
17436 NestReg = X86::ECX;
17438 // Check that ECX wasn't needed by an 'inreg' parameter.
17439 FunctionType *FTy = Func->getFunctionType();
17440 const AttributeSet &Attrs = Func->getAttributes();
17442 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17443 unsigned InRegCount = 0;
17446 for (FunctionType::param_iterator I = FTy->param_begin(),
17447 E = FTy->param_end(); I != E; ++I, ++Idx)
17448 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17449 // FIXME: should only count parameters that are lowered to integers.
17450 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17452 if (InRegCount > 2) {
17453 report_fatal_error("Nest register in use - reduce number of inreg"
17459 case CallingConv::X86_FastCall:
17460 case CallingConv::X86_ThisCall:
17461 case CallingConv::Fast:
17462 // Pass 'nest' parameter in EAX.
17463 // Must be kept in sync with X86CallingConv.td
17464 NestReg = X86::EAX;
17468 SDValue OutChains[4];
17469 SDValue Addr, Disp;
17471 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17472 DAG.getConstant(10, MVT::i32));
17473 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17475 // This is storing the opcode for MOV32ri.
17476 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17477 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17478 OutChains[0] = DAG.getStore(Root, dl,
17479 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17480 Trmp, MachinePointerInfo(TrmpAddr),
17483 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17484 DAG.getConstant(1, MVT::i32));
17485 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17486 MachinePointerInfo(TrmpAddr, 1),
17489 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17490 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17491 DAG.getConstant(5, MVT::i32));
17492 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17493 MachinePointerInfo(TrmpAddr, 5),
17496 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17497 DAG.getConstant(6, MVT::i32));
17498 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17499 MachinePointerInfo(TrmpAddr, 6),
17502 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17506 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17507 SelectionDAG &DAG) const {
17509 The rounding mode is in bits 11:10 of FPSR, and has the following
17511 00 Round to nearest
17516 FLT_ROUNDS, on the other hand, expects the following:
17523 To perform the conversion, we do:
17524 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17527 MachineFunction &MF = DAG.getMachineFunction();
17528 const TargetMachine &TM = MF.getTarget();
17529 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17530 unsigned StackAlignment = TFI.getStackAlignment();
17531 MVT VT = Op.getSimpleValueType();
17534 // Save FP Control Word to stack slot
17535 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17536 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17538 MachineMemOperand *MMO =
17539 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17540 MachineMemOperand::MOStore, 2, 2);
17542 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17543 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17544 DAG.getVTList(MVT::Other),
17545 Ops, MVT::i16, MMO);
17547 // Load FP Control Word from stack slot
17548 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17549 MachinePointerInfo(), false, false, false, 0);
17551 // Transform as necessary
17553 DAG.getNode(ISD::SRL, DL, MVT::i16,
17554 DAG.getNode(ISD::AND, DL, MVT::i16,
17555 CWD, DAG.getConstant(0x800, MVT::i16)),
17556 DAG.getConstant(11, MVT::i8));
17558 DAG.getNode(ISD::SRL, DL, MVT::i16,
17559 DAG.getNode(ISD::AND, DL, MVT::i16,
17560 CWD, DAG.getConstant(0x400, MVT::i16)),
17561 DAG.getConstant(9, MVT::i8));
17564 DAG.getNode(ISD::AND, DL, MVT::i16,
17565 DAG.getNode(ISD::ADD, DL, MVT::i16,
17566 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17567 DAG.getConstant(1, MVT::i16)),
17568 DAG.getConstant(3, MVT::i16));
17570 return DAG.getNode((VT.getSizeInBits() < 16 ?
17571 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17574 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17575 MVT VT = Op.getSimpleValueType();
17577 unsigned NumBits = VT.getSizeInBits();
17580 Op = Op.getOperand(0);
17581 if (VT == MVT::i8) {
17582 // Zero extend to i32 since there is not an i8 bsr.
17584 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17587 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17588 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17589 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17591 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17594 DAG.getConstant(NumBits+NumBits-1, OpVT),
17595 DAG.getConstant(X86::COND_E, MVT::i8),
17598 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17600 // Finally xor with NumBits-1.
17601 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17604 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17608 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17609 MVT VT = Op.getSimpleValueType();
17611 unsigned NumBits = VT.getSizeInBits();
17614 Op = Op.getOperand(0);
17615 if (VT == MVT::i8) {
17616 // Zero extend to i32 since there is not an i8 bsr.
17618 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17621 // Issue a bsr (scan bits in reverse).
17622 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17623 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17625 // And xor with NumBits-1.
17626 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17629 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17633 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17634 MVT VT = Op.getSimpleValueType();
17635 unsigned NumBits = VT.getSizeInBits();
17637 Op = Op.getOperand(0);
17639 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17640 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17641 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17643 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17646 DAG.getConstant(NumBits, VT),
17647 DAG.getConstant(X86::COND_E, MVT::i8),
17650 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17653 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17654 // ones, and then concatenate the result back.
17655 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17656 MVT VT = Op.getSimpleValueType();
17658 assert(VT.is256BitVector() && VT.isInteger() &&
17659 "Unsupported value type for operation");
17661 unsigned NumElems = VT.getVectorNumElements();
17664 // Extract the LHS vectors
17665 SDValue LHS = Op.getOperand(0);
17666 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17667 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17669 // Extract the RHS vectors
17670 SDValue RHS = Op.getOperand(1);
17671 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17672 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17674 MVT EltVT = VT.getVectorElementType();
17675 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17677 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17678 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17679 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17682 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17683 assert(Op.getSimpleValueType().is256BitVector() &&
17684 Op.getSimpleValueType().isInteger() &&
17685 "Only handle AVX 256-bit vector integer operation");
17686 return Lower256IntArith(Op, DAG);
17689 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17690 assert(Op.getSimpleValueType().is256BitVector() &&
17691 Op.getSimpleValueType().isInteger() &&
17692 "Only handle AVX 256-bit vector integer operation");
17693 return Lower256IntArith(Op, DAG);
17696 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17697 SelectionDAG &DAG) {
17699 MVT VT = Op.getSimpleValueType();
17701 // Decompose 256-bit ops into smaller 128-bit ops.
17702 if (VT.is256BitVector() && !Subtarget->hasInt256())
17703 return Lower256IntArith(Op, DAG);
17705 SDValue A = Op.getOperand(0);
17706 SDValue B = Op.getOperand(1);
17708 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17709 if (VT == MVT::v4i32) {
17710 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17711 "Should not custom lower when pmuldq is available!");
17713 // Extract the odd parts.
17714 static const int UnpackMask[] = { 1, -1, 3, -1 };
17715 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17716 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17718 // Multiply the even parts.
17719 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17720 // Now multiply odd parts.
17721 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17723 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17724 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17726 // Merge the two vectors back together with a shuffle. This expands into 2
17728 static const int ShufMask[] = { 0, 4, 2, 6 };
17729 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17732 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17733 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17735 // Ahi = psrlqi(a, 32);
17736 // Bhi = psrlqi(b, 32);
17738 // AloBlo = pmuludq(a, b);
17739 // AloBhi = pmuludq(a, Bhi);
17740 // AhiBlo = pmuludq(Ahi, b);
17742 // AloBhi = psllqi(AloBhi, 32);
17743 // AhiBlo = psllqi(AhiBlo, 32);
17744 // return AloBlo + AloBhi + AhiBlo;
17746 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17747 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17749 // Bit cast to 32-bit vectors for MULUDQ
17750 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17751 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17752 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17753 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17754 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17755 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17757 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17758 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17759 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17761 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17762 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17764 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17765 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17768 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17769 assert(Subtarget->isTargetWin64() && "Unexpected target");
17770 EVT VT = Op.getValueType();
17771 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17772 "Unexpected return type for lowering");
17776 switch (Op->getOpcode()) {
17777 default: llvm_unreachable("Unexpected request for libcall!");
17778 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17779 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17780 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17781 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17782 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17783 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17787 SDValue InChain = DAG.getEntryNode();
17789 TargetLowering::ArgListTy Args;
17790 TargetLowering::ArgListEntry Entry;
17791 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17792 EVT ArgVT = Op->getOperand(i).getValueType();
17793 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17794 "Unexpected argument type for lowering");
17795 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17796 Entry.Node = StackPtr;
17797 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17799 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17800 Entry.Ty = PointerType::get(ArgTy,0);
17801 Entry.isSExt = false;
17802 Entry.isZExt = false;
17803 Args.push_back(Entry);
17806 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17809 TargetLowering::CallLoweringInfo CLI(DAG);
17810 CLI.setDebugLoc(dl).setChain(InChain)
17811 .setCallee(getLibcallCallingConv(LC),
17812 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17813 Callee, std::move(Args), 0)
17814 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17816 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17817 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17820 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17821 SelectionDAG &DAG) {
17822 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17823 EVT VT = Op0.getValueType();
17826 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17827 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17829 // PMULxD operations multiply each even value (starting at 0) of LHS with
17830 // the related value of RHS and produce a widen result.
17831 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17832 // => <2 x i64> <ae|cg>
17834 // In other word, to have all the results, we need to perform two PMULxD:
17835 // 1. one with the even values.
17836 // 2. one with the odd values.
17837 // To achieve #2, with need to place the odd values at an even position.
17839 // Place the odd value at an even position (basically, shift all values 1
17840 // step to the left):
17841 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17842 // <a|b|c|d> => <b|undef|d|undef>
17843 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17844 // <e|f|g|h> => <f|undef|h|undef>
17845 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17847 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17849 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17850 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17852 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17853 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17854 // => <2 x i64> <ae|cg>
17855 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17856 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17857 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17858 // => <2 x i64> <bf|dh>
17859 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17860 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17862 // Shuffle it back into the right order.
17863 SDValue Highs, Lows;
17864 if (VT == MVT::v8i32) {
17865 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17866 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17867 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17868 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17870 const int HighMask[] = {1, 5, 3, 7};
17871 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17872 const int LowMask[] = {0, 4, 2, 6};
17873 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17876 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17877 // unsigned multiply.
17878 if (IsSigned && !Subtarget->hasSSE41()) {
17880 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17881 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17882 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17883 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17884 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17886 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17887 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17890 // The first result of MUL_LOHI is actually the low value, followed by the
17892 SDValue Ops[] = {Lows, Highs};
17893 return DAG.getMergeValues(Ops, dl);
17896 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17897 const X86Subtarget *Subtarget) {
17898 MVT VT = Op.getSimpleValueType();
17900 SDValue R = Op.getOperand(0);
17901 SDValue Amt = Op.getOperand(1);
17903 // Optimize shl/srl/sra with constant shift amount.
17904 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17905 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17906 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17908 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17909 (Subtarget->hasInt256() &&
17910 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17911 (Subtarget->hasAVX512() &&
17912 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17913 if (Op.getOpcode() == ISD::SHL)
17914 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17916 if (Op.getOpcode() == ISD::SRL)
17917 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17919 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17920 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17924 if (VT == MVT::v16i8) {
17925 if (Op.getOpcode() == ISD::SHL) {
17926 // Make a large shift.
17927 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17928 MVT::v8i16, R, ShiftAmt,
17930 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17931 // Zero out the rightmost bits.
17932 SmallVector<SDValue, 16> V(16,
17933 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17935 return DAG.getNode(ISD::AND, dl, VT, SHL,
17936 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17938 if (Op.getOpcode() == ISD::SRL) {
17939 // Make a large shift.
17940 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17941 MVT::v8i16, R, ShiftAmt,
17943 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17944 // Zero out the leftmost bits.
17945 SmallVector<SDValue, 16> V(16,
17946 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17948 return DAG.getNode(ISD::AND, dl, VT, SRL,
17949 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17951 if (Op.getOpcode() == ISD::SRA) {
17952 if (ShiftAmt == 7) {
17953 // R s>> 7 === R s< 0
17954 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17955 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17958 // R s>> a === ((R u>> a) ^ m) - m
17959 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17960 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17962 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17963 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17964 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17967 llvm_unreachable("Unknown shift opcode.");
17970 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17971 if (Op.getOpcode() == ISD::SHL) {
17972 // Make a large shift.
17973 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17974 MVT::v16i16, R, ShiftAmt,
17976 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17977 // Zero out the rightmost bits.
17978 SmallVector<SDValue, 32> V(32,
17979 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17981 return DAG.getNode(ISD::AND, dl, VT, SHL,
17982 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17984 if (Op.getOpcode() == ISD::SRL) {
17985 // Make a large shift.
17986 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17987 MVT::v16i16, R, ShiftAmt,
17989 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17990 // Zero out the leftmost bits.
17991 SmallVector<SDValue, 32> V(32,
17992 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17994 return DAG.getNode(ISD::AND, dl, VT, SRL,
17995 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17997 if (Op.getOpcode() == ISD::SRA) {
17998 if (ShiftAmt == 7) {
17999 // R s>> 7 === R s< 0
18000 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18001 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18004 // R s>> a === ((R u>> a) ^ m) - m
18005 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18006 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18008 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18009 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18010 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18013 llvm_unreachable("Unknown shift opcode.");
18018 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18019 if (!Subtarget->is64Bit() &&
18020 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18021 Amt.getOpcode() == ISD::BITCAST &&
18022 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18023 Amt = Amt.getOperand(0);
18024 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18025 VT.getVectorNumElements();
18026 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18027 uint64_t ShiftAmt = 0;
18028 for (unsigned i = 0; i != Ratio; ++i) {
18029 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18033 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18035 // Check remaining shift amounts.
18036 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18037 uint64_t ShAmt = 0;
18038 for (unsigned j = 0; j != Ratio; ++j) {
18039 ConstantSDNode *C =
18040 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18044 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18046 if (ShAmt != ShiftAmt)
18049 switch (Op.getOpcode()) {
18051 llvm_unreachable("Unknown shift opcode!");
18053 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18056 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18059 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18067 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18068 const X86Subtarget* Subtarget) {
18069 MVT VT = Op.getSimpleValueType();
18071 SDValue R = Op.getOperand(0);
18072 SDValue Amt = Op.getOperand(1);
18074 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18075 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18076 (Subtarget->hasInt256() &&
18077 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18078 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18079 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18081 EVT EltVT = VT.getVectorElementType();
18083 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18084 unsigned NumElts = VT.getVectorNumElements();
18086 for (i = 0; i != NumElts; ++i) {
18087 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18091 for (j = i; j != NumElts; ++j) {
18092 SDValue Arg = Amt.getOperand(j);
18093 if (Arg.getOpcode() == ISD::UNDEF) continue;
18094 if (Arg != Amt.getOperand(i))
18097 if (i != NumElts && j == NumElts)
18098 BaseShAmt = Amt.getOperand(i);
18100 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18101 Amt = Amt.getOperand(0);
18102 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18103 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18104 SDValue InVec = Amt.getOperand(0);
18105 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18106 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18108 for (; i != NumElts; ++i) {
18109 SDValue Arg = InVec.getOperand(i);
18110 if (Arg.getOpcode() == ISD::UNDEF) continue;
18114 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18115 if (ConstantSDNode *C =
18116 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18117 unsigned SplatIdx =
18118 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18119 if (C->getZExtValue() == SplatIdx)
18120 BaseShAmt = InVec.getOperand(1);
18123 if (!BaseShAmt.getNode())
18124 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18125 DAG.getIntPtrConstant(0));
18129 if (BaseShAmt.getNode()) {
18130 if (EltVT.bitsGT(MVT::i32))
18131 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18132 else if (EltVT.bitsLT(MVT::i32))
18133 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18135 switch (Op.getOpcode()) {
18137 llvm_unreachable("Unknown shift opcode!");
18139 switch (VT.SimpleTy) {
18140 default: return SDValue();
18149 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18152 switch (VT.SimpleTy) {
18153 default: return SDValue();
18160 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18163 switch (VT.SimpleTy) {
18164 default: return SDValue();
18173 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18179 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18180 if (!Subtarget->is64Bit() &&
18181 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18182 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18183 Amt.getOpcode() == ISD::BITCAST &&
18184 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18185 Amt = Amt.getOperand(0);
18186 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18187 VT.getVectorNumElements();
18188 std::vector<SDValue> Vals(Ratio);
18189 for (unsigned i = 0; i != Ratio; ++i)
18190 Vals[i] = Amt.getOperand(i);
18191 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18192 for (unsigned j = 0; j != Ratio; ++j)
18193 if (Vals[j] != Amt.getOperand(i + j))
18196 switch (Op.getOpcode()) {
18198 llvm_unreachable("Unknown shift opcode!");
18200 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18202 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18204 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18211 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18212 SelectionDAG &DAG) {
18213 MVT VT = Op.getSimpleValueType();
18215 SDValue R = Op.getOperand(0);
18216 SDValue Amt = Op.getOperand(1);
18219 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18220 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18222 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18226 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18230 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18232 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18233 if (Subtarget->hasInt256()) {
18234 if (Op.getOpcode() == ISD::SRL &&
18235 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18236 VT == MVT::v4i64 || VT == MVT::v8i32))
18238 if (Op.getOpcode() == ISD::SHL &&
18239 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18240 VT == MVT::v4i64 || VT == MVT::v8i32))
18242 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18246 // If possible, lower this packed shift into a vector multiply instead of
18247 // expanding it into a sequence of scalar shifts.
18248 // Do this only if the vector shift count is a constant build_vector.
18249 if (Op.getOpcode() == ISD::SHL &&
18250 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18251 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18252 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18253 SmallVector<SDValue, 8> Elts;
18254 EVT SVT = VT.getScalarType();
18255 unsigned SVTBits = SVT.getSizeInBits();
18256 const APInt &One = APInt(SVTBits, 1);
18257 unsigned NumElems = VT.getVectorNumElements();
18259 for (unsigned i=0; i !=NumElems; ++i) {
18260 SDValue Op = Amt->getOperand(i);
18261 if (Op->getOpcode() == ISD::UNDEF) {
18262 Elts.push_back(Op);
18266 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18267 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18268 uint64_t ShAmt = C.getZExtValue();
18269 if (ShAmt >= SVTBits) {
18270 Elts.push_back(DAG.getUNDEF(SVT));
18273 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18275 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18276 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18279 // Lower SHL with variable shift amount.
18280 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18281 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18283 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18284 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18285 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18286 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18289 // If possible, lower this shift as a sequence of two shifts by
18290 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18292 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18294 // Could be rewritten as:
18295 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18297 // The advantage is that the two shifts from the example would be
18298 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18299 // the vector shift into four scalar shifts plus four pairs of vector
18301 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18302 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18303 unsigned TargetOpcode = X86ISD::MOVSS;
18304 bool CanBeSimplified;
18305 // The splat value for the first packed shift (the 'X' from the example).
18306 SDValue Amt1 = Amt->getOperand(0);
18307 // The splat value for the second packed shift (the 'Y' from the example).
18308 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18309 Amt->getOperand(2);
18311 // See if it is possible to replace this node with a sequence of
18312 // two shifts followed by a MOVSS/MOVSD
18313 if (VT == MVT::v4i32) {
18314 // Check if it is legal to use a MOVSS.
18315 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18316 Amt2 == Amt->getOperand(3);
18317 if (!CanBeSimplified) {
18318 // Otherwise, check if we can still simplify this node using a MOVSD.
18319 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18320 Amt->getOperand(2) == Amt->getOperand(3);
18321 TargetOpcode = X86ISD::MOVSD;
18322 Amt2 = Amt->getOperand(2);
18325 // Do similar checks for the case where the machine value type
18327 CanBeSimplified = Amt1 == Amt->getOperand(1);
18328 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18329 CanBeSimplified = Amt2 == Amt->getOperand(i);
18331 if (!CanBeSimplified) {
18332 TargetOpcode = X86ISD::MOVSD;
18333 CanBeSimplified = true;
18334 Amt2 = Amt->getOperand(4);
18335 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18336 CanBeSimplified = Amt1 == Amt->getOperand(i);
18337 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18338 CanBeSimplified = Amt2 == Amt->getOperand(j);
18342 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18343 isa<ConstantSDNode>(Amt2)) {
18344 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18345 EVT CastVT = MVT::v4i32;
18347 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18348 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18350 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18351 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18352 if (TargetOpcode == X86ISD::MOVSD)
18353 CastVT = MVT::v2i64;
18354 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18355 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18356 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18358 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18362 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18363 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18366 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18367 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18369 // Turn 'a' into a mask suitable for VSELECT
18370 SDValue VSelM = DAG.getConstant(0x80, VT);
18371 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18372 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18374 SDValue CM1 = DAG.getConstant(0x0f, VT);
18375 SDValue CM2 = DAG.getConstant(0x3f, VT);
18377 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18378 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18379 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18380 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18381 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18384 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18385 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18386 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18388 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18389 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18390 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18391 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18392 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18395 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18396 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18397 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18399 // return VSELECT(r, r+r, a);
18400 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18401 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18405 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18406 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18407 // solution better.
18408 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18409 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18411 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18412 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18413 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18414 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18415 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18418 // Decompose 256-bit shifts into smaller 128-bit shifts.
18419 if (VT.is256BitVector()) {
18420 unsigned NumElems = VT.getVectorNumElements();
18421 MVT EltVT = VT.getVectorElementType();
18422 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18424 // Extract the two vectors
18425 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18426 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18428 // Recreate the shift amount vectors
18429 SDValue Amt1, Amt2;
18430 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18431 // Constant shift amount
18432 SmallVector<SDValue, 4> Amt1Csts;
18433 SmallVector<SDValue, 4> Amt2Csts;
18434 for (unsigned i = 0; i != NumElems/2; ++i)
18435 Amt1Csts.push_back(Amt->getOperand(i));
18436 for (unsigned i = NumElems/2; i != NumElems; ++i)
18437 Amt2Csts.push_back(Amt->getOperand(i));
18439 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18440 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18442 // Variable shift amount
18443 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18444 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18447 // Issue new vector shifts for the smaller types
18448 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18449 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18451 // Concatenate the result back
18452 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18458 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18459 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18460 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18461 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18462 // has only one use.
18463 SDNode *N = Op.getNode();
18464 SDValue LHS = N->getOperand(0);
18465 SDValue RHS = N->getOperand(1);
18466 unsigned BaseOp = 0;
18469 switch (Op.getOpcode()) {
18470 default: llvm_unreachable("Unknown ovf instruction!");
18472 // A subtract of one will be selected as a INC. Note that INC doesn't
18473 // set CF, so we can't do this for UADDO.
18474 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18476 BaseOp = X86ISD::INC;
18477 Cond = X86::COND_O;
18480 BaseOp = X86ISD::ADD;
18481 Cond = X86::COND_O;
18484 BaseOp = X86ISD::ADD;
18485 Cond = X86::COND_B;
18488 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18489 // set CF, so we can't do this for USUBO.
18490 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18492 BaseOp = X86ISD::DEC;
18493 Cond = X86::COND_O;
18496 BaseOp = X86ISD::SUB;
18497 Cond = X86::COND_O;
18500 BaseOp = X86ISD::SUB;
18501 Cond = X86::COND_B;
18504 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18505 Cond = X86::COND_O;
18507 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18508 if (N->getValueType(0) == MVT::i8) {
18509 BaseOp = X86ISD::UMUL8;
18510 Cond = X86::COND_O;
18513 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18515 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18518 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18519 DAG.getConstant(X86::COND_O, MVT::i32),
18520 SDValue(Sum.getNode(), 2));
18522 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18526 // Also sets EFLAGS.
18527 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18528 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18531 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18532 DAG.getConstant(Cond, MVT::i32),
18533 SDValue(Sum.getNode(), 1));
18535 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18538 // Sign extension of the low part of vector elements. This may be used either
18539 // when sign extend instructions are not available or if the vector element
18540 // sizes already match the sign-extended size. If the vector elements are in
18541 // their pre-extended size and sign extend instructions are available, that will
18542 // be handled by LowerSIGN_EXTEND.
18543 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18544 SelectionDAG &DAG) const {
18546 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18547 MVT VT = Op.getSimpleValueType();
18549 if (!Subtarget->hasSSE2() || !VT.isVector())
18552 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18553 ExtraVT.getScalarType().getSizeInBits();
18555 switch (VT.SimpleTy) {
18556 default: return SDValue();
18559 if (!Subtarget->hasFp256())
18561 if (!Subtarget->hasInt256()) {
18562 // needs to be split
18563 unsigned NumElems = VT.getVectorNumElements();
18565 // Extract the LHS vectors
18566 SDValue LHS = Op.getOperand(0);
18567 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18568 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18570 MVT EltVT = VT.getVectorElementType();
18571 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18573 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18574 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18575 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18577 SDValue Extra = DAG.getValueType(ExtraVT);
18579 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18580 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18582 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18587 SDValue Op0 = Op.getOperand(0);
18589 // This is a sign extension of some low part of vector elements without
18590 // changing the size of the vector elements themselves:
18591 // Shift-Left + Shift-Right-Algebraic.
18592 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18594 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18600 /// Returns true if the operand type is exactly twice the native width, and
18601 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18602 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18603 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18604 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18605 const X86Subtarget &Subtarget =
18606 getTargetMachine().getSubtarget<X86Subtarget>();
18607 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18610 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18611 else if (OpWidth == 128)
18612 return Subtarget.hasCmpxchg16b();
18617 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18618 return needsCmpXchgNb(SI->getValueOperand()->getType());
18621 // Note: this turns large loads into lock cmpxchg8b/16b.
18622 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18623 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18624 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18625 return needsCmpXchgNb(PTy->getElementType());
18628 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18629 const X86Subtarget &Subtarget =
18630 getTargetMachine().getSubtarget<X86Subtarget>();
18631 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18632 const Type *MemType = AI->getType();
18634 // If the operand is too big, we must see if cmpxchg8/16b is available
18635 // and default to library calls otherwise.
18636 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18637 return needsCmpXchgNb(MemType);
18639 AtomicRMWInst::BinOp Op = AI->getOperation();
18642 llvm_unreachable("Unknown atomic operation");
18643 case AtomicRMWInst::Xchg:
18644 case AtomicRMWInst::Add:
18645 case AtomicRMWInst::Sub:
18646 // It's better to use xadd, xsub or xchg for these in all cases.
18648 case AtomicRMWInst::Or:
18649 case AtomicRMWInst::And:
18650 case AtomicRMWInst::Xor:
18651 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18652 // prefix to a normal instruction for these operations.
18653 return !AI->use_empty();
18654 case AtomicRMWInst::Nand:
18655 case AtomicRMWInst::Max:
18656 case AtomicRMWInst::Min:
18657 case AtomicRMWInst::UMax:
18658 case AtomicRMWInst::UMin:
18659 // These always require a non-trivial set of data operations on x86. We must
18660 // use a cmpxchg loop.
18665 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18666 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18667 // no-sse2). There isn't any reason to disable it if the target processor
18669 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18673 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18674 const X86Subtarget &Subtarget =
18675 getTargetMachine().getSubtarget<X86Subtarget>();
18676 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18677 const Type *MemType = AI->getType();
18678 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18679 // there is no benefit in turning such RMWs into loads, and it is actually
18680 // harmful as it introduces a mfence.
18681 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18684 auto Builder = IRBuilder<>(AI);
18685 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18686 auto SynchScope = AI->getSynchScope();
18687 // We must restrict the ordering to avoid generating loads with Release or
18688 // ReleaseAcquire orderings.
18689 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18690 auto Ptr = AI->getPointerOperand();
18692 // Before the load we need a fence. Here is an example lifted from
18693 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18696 // x.store(1, relaxed);
18697 // r1 = y.fetch_add(0, release);
18699 // y.fetch_add(42, acquire);
18700 // r2 = x.load(relaxed);
18701 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18702 // lowered to just a load without a fence. A mfence flushes the store buffer,
18703 // making the optimization clearly correct.
18704 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18705 // otherwise, we might be able to be more agressive on relaxed idempotent
18706 // rmw. In practice, they do not look useful, so we don't try to be
18707 // especially clever.
18708 if (SynchScope == SingleThread) {
18709 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18710 // the IR level, so we must wrap it in an intrinsic.
18712 } else if (hasMFENCE(Subtarget)) {
18713 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18714 Intrinsic::x86_sse2_mfence);
18715 Builder.CreateCall(MFence);
18717 // FIXME: it might make sense to use a locked operation here but on a
18718 // different cache-line to prevent cache-line bouncing. In practice it
18719 // is probably a small win, and x86 processors without mfence are rare
18720 // enough that we do not bother.
18724 // Finally we can emit the atomic load.
18725 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18726 AI->getType()->getPrimitiveSizeInBits());
18727 Loaded->setAtomic(Order, SynchScope);
18728 AI->replaceAllUsesWith(Loaded);
18729 AI->eraseFromParent();
18733 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18734 SelectionDAG &DAG) {
18736 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18737 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18738 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18739 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18741 // The only fence that needs an instruction is a sequentially-consistent
18742 // cross-thread fence.
18743 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18744 if (hasMFENCE(*Subtarget))
18745 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18747 SDValue Chain = Op.getOperand(0);
18748 SDValue Zero = DAG.getConstant(0, MVT::i32);
18750 DAG.getRegister(X86::ESP, MVT::i32), // Base
18751 DAG.getTargetConstant(1, MVT::i8), // Scale
18752 DAG.getRegister(0, MVT::i32), // Index
18753 DAG.getTargetConstant(0, MVT::i32), // Disp
18754 DAG.getRegister(0, MVT::i32), // Segment.
18758 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18759 return SDValue(Res, 0);
18762 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18763 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18766 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18767 SelectionDAG &DAG) {
18768 MVT T = Op.getSimpleValueType();
18772 switch(T.SimpleTy) {
18773 default: llvm_unreachable("Invalid value type!");
18774 case MVT::i8: Reg = X86::AL; size = 1; break;
18775 case MVT::i16: Reg = X86::AX; size = 2; break;
18776 case MVT::i32: Reg = X86::EAX; size = 4; break;
18778 assert(Subtarget->is64Bit() && "Node not type legal!");
18779 Reg = X86::RAX; size = 8;
18782 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18783 Op.getOperand(2), SDValue());
18784 SDValue Ops[] = { cpIn.getValue(0),
18787 DAG.getTargetConstant(size, MVT::i8),
18788 cpIn.getValue(1) };
18789 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18790 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18791 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18795 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18796 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18797 MVT::i32, cpOut.getValue(2));
18798 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18799 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18801 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18802 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18803 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18807 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18808 SelectionDAG &DAG) {
18809 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18810 MVT DstVT = Op.getSimpleValueType();
18812 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18813 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18814 if (DstVT != MVT::f64)
18815 // This conversion needs to be expanded.
18818 SDValue InVec = Op->getOperand(0);
18820 unsigned NumElts = SrcVT.getVectorNumElements();
18821 EVT SVT = SrcVT.getVectorElementType();
18823 // Widen the vector in input in the case of MVT::v2i32.
18824 // Example: from MVT::v2i32 to MVT::v4i32.
18825 SmallVector<SDValue, 16> Elts;
18826 for (unsigned i = 0, e = NumElts; i != e; ++i)
18827 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18828 DAG.getIntPtrConstant(i)));
18830 // Explicitly mark the extra elements as Undef.
18831 SDValue Undef = DAG.getUNDEF(SVT);
18832 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18833 Elts.push_back(Undef);
18835 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18836 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18837 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18838 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18839 DAG.getIntPtrConstant(0));
18842 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18843 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18844 assert((DstVT == MVT::i64 ||
18845 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18846 "Unexpected custom BITCAST");
18847 // i64 <=> MMX conversions are Legal.
18848 if (SrcVT==MVT::i64 && DstVT.isVector())
18850 if (DstVT==MVT::i64 && SrcVT.isVector())
18852 // MMX <=> MMX conversions are Legal.
18853 if (SrcVT.isVector() && DstVT.isVector())
18855 // All other conversions need to be expanded.
18859 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18860 SDNode *Node = Op.getNode();
18862 EVT T = Node->getValueType(0);
18863 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18864 DAG.getConstant(0, T), Node->getOperand(2));
18865 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18866 cast<AtomicSDNode>(Node)->getMemoryVT(),
18867 Node->getOperand(0),
18868 Node->getOperand(1), negOp,
18869 cast<AtomicSDNode>(Node)->getMemOperand(),
18870 cast<AtomicSDNode>(Node)->getOrdering(),
18871 cast<AtomicSDNode>(Node)->getSynchScope());
18874 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18875 SDNode *Node = Op.getNode();
18877 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18879 // Convert seq_cst store -> xchg
18880 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18881 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18882 // (The only way to get a 16-byte store is cmpxchg16b)
18883 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18884 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18885 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18886 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18887 cast<AtomicSDNode>(Node)->getMemoryVT(),
18888 Node->getOperand(0),
18889 Node->getOperand(1), Node->getOperand(2),
18890 cast<AtomicSDNode>(Node)->getMemOperand(),
18891 cast<AtomicSDNode>(Node)->getOrdering(),
18892 cast<AtomicSDNode>(Node)->getSynchScope());
18893 return Swap.getValue(1);
18895 // Other atomic stores have a simple pattern.
18899 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18900 EVT VT = Op.getNode()->getSimpleValueType(0);
18902 // Let legalize expand this if it isn't a legal type yet.
18903 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18906 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18909 bool ExtraOp = false;
18910 switch (Op.getOpcode()) {
18911 default: llvm_unreachable("Invalid code");
18912 case ISD::ADDC: Opc = X86ISD::ADD; break;
18913 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18914 case ISD::SUBC: Opc = X86ISD::SUB; break;
18915 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18919 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18921 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18922 Op.getOperand(1), Op.getOperand(2));
18925 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18926 SelectionDAG &DAG) {
18927 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18929 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18930 // which returns the values as { float, float } (in XMM0) or
18931 // { double, double } (which is returned in XMM0, XMM1).
18933 SDValue Arg = Op.getOperand(0);
18934 EVT ArgVT = Arg.getValueType();
18935 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18937 TargetLowering::ArgListTy Args;
18938 TargetLowering::ArgListEntry Entry;
18942 Entry.isSExt = false;
18943 Entry.isZExt = false;
18944 Args.push_back(Entry);
18946 bool isF64 = ArgVT == MVT::f64;
18947 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18948 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18949 // the results are returned via SRet in memory.
18950 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18951 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18952 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18954 Type *RetTy = isF64
18955 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18956 : (Type*)VectorType::get(ArgTy, 4);
18958 TargetLowering::CallLoweringInfo CLI(DAG);
18959 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18960 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18962 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18965 // Returned in xmm0 and xmm1.
18966 return CallResult.first;
18968 // Returned in bits 0:31 and 32:64 xmm0.
18969 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18970 CallResult.first, DAG.getIntPtrConstant(0));
18971 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18972 CallResult.first, DAG.getIntPtrConstant(1));
18973 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18974 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18977 /// LowerOperation - Provide custom lowering hooks for some operations.
18979 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18980 switch (Op.getOpcode()) {
18981 default: llvm_unreachable("Should not custom lower this!");
18982 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18983 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18984 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18985 return LowerCMP_SWAP(Op, Subtarget, DAG);
18986 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18987 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18988 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18989 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18990 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18991 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18992 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18993 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18994 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18995 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18996 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18997 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18998 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18999 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19000 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19001 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19002 case ISD::SHL_PARTS:
19003 case ISD::SRA_PARTS:
19004 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19005 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19006 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19007 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19008 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19009 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19010 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19011 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19012 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19013 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19014 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19016 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19017 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19018 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19019 case ISD::SETCC: return LowerSETCC(Op, DAG);
19020 case ISD::SELECT: return LowerSELECT(Op, DAG);
19021 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19022 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19023 case ISD::VASTART: return LowerVASTART(Op, DAG);
19024 case ISD::VAARG: return LowerVAARG(Op, DAG);
19025 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19026 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19027 case ISD::INTRINSIC_VOID:
19028 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19029 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19030 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19031 case ISD::FRAME_TO_ARGS_OFFSET:
19032 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19033 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19034 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19035 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19036 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19037 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19038 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19039 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19040 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19041 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19042 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19043 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19044 case ISD::UMUL_LOHI:
19045 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19048 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19054 case ISD::UMULO: return LowerXALUO(Op, DAG);
19055 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19056 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19060 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19061 case ISD::ADD: return LowerADD(Op, DAG);
19062 case ISD::SUB: return LowerSUB(Op, DAG);
19063 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19067 /// ReplaceNodeResults - Replace a node with an illegal result type
19068 /// with a new node built out of custom code.
19069 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19070 SmallVectorImpl<SDValue>&Results,
19071 SelectionDAG &DAG) const {
19073 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19074 switch (N->getOpcode()) {
19076 llvm_unreachable("Do not know how to custom type legalize this operation!");
19077 case ISD::SIGN_EXTEND_INREG:
19082 // We don't want to expand or promote these.
19089 case ISD::UDIVREM: {
19090 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19091 Results.push_back(V);
19094 case ISD::FP_TO_SINT:
19095 case ISD::FP_TO_UINT: {
19096 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19098 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19101 std::pair<SDValue,SDValue> Vals =
19102 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19103 SDValue FIST = Vals.first, StackSlot = Vals.second;
19104 if (FIST.getNode()) {
19105 EVT VT = N->getValueType(0);
19106 // Return a load from the stack slot.
19107 if (StackSlot.getNode())
19108 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19109 MachinePointerInfo(),
19110 false, false, false, 0));
19112 Results.push_back(FIST);
19116 case ISD::UINT_TO_FP: {
19117 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19118 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19119 N->getValueType(0) != MVT::v2f32)
19121 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19123 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19125 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19126 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19127 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19128 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19129 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19130 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19133 case ISD::FP_ROUND: {
19134 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19136 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19137 Results.push_back(V);
19140 case ISD::INTRINSIC_W_CHAIN: {
19141 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19143 default : llvm_unreachable("Do not know how to custom type "
19144 "legalize this intrinsic operation!");
19145 case Intrinsic::x86_rdtsc:
19146 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19148 case Intrinsic::x86_rdtscp:
19149 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19151 case Intrinsic::x86_rdpmc:
19152 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19155 case ISD::READCYCLECOUNTER: {
19156 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19159 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19160 EVT T = N->getValueType(0);
19161 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19162 bool Regs64bit = T == MVT::i128;
19163 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19164 SDValue cpInL, cpInH;
19165 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19166 DAG.getConstant(0, HalfT));
19167 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19168 DAG.getConstant(1, HalfT));
19169 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19170 Regs64bit ? X86::RAX : X86::EAX,
19172 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19173 Regs64bit ? X86::RDX : X86::EDX,
19174 cpInH, cpInL.getValue(1));
19175 SDValue swapInL, swapInH;
19176 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19177 DAG.getConstant(0, HalfT));
19178 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19179 DAG.getConstant(1, HalfT));
19180 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19181 Regs64bit ? X86::RBX : X86::EBX,
19182 swapInL, cpInH.getValue(1));
19183 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19184 Regs64bit ? X86::RCX : X86::ECX,
19185 swapInH, swapInL.getValue(1));
19186 SDValue Ops[] = { swapInH.getValue(0),
19188 swapInH.getValue(1) };
19189 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19190 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19191 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19192 X86ISD::LCMPXCHG8_DAG;
19193 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19194 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19195 Regs64bit ? X86::RAX : X86::EAX,
19196 HalfT, Result.getValue(1));
19197 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19198 Regs64bit ? X86::RDX : X86::EDX,
19199 HalfT, cpOutL.getValue(2));
19200 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19202 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19203 MVT::i32, cpOutH.getValue(2));
19205 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19206 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19207 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19209 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19210 Results.push_back(Success);
19211 Results.push_back(EFLAGS.getValue(1));
19214 case ISD::ATOMIC_SWAP:
19215 case ISD::ATOMIC_LOAD_ADD:
19216 case ISD::ATOMIC_LOAD_SUB:
19217 case ISD::ATOMIC_LOAD_AND:
19218 case ISD::ATOMIC_LOAD_OR:
19219 case ISD::ATOMIC_LOAD_XOR:
19220 case ISD::ATOMIC_LOAD_NAND:
19221 case ISD::ATOMIC_LOAD_MIN:
19222 case ISD::ATOMIC_LOAD_MAX:
19223 case ISD::ATOMIC_LOAD_UMIN:
19224 case ISD::ATOMIC_LOAD_UMAX:
19225 case ISD::ATOMIC_LOAD: {
19226 // Delegate to generic TypeLegalization. Situations we can really handle
19227 // should have already been dealt with by AtomicExpandPass.cpp.
19230 case ISD::BITCAST: {
19231 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19232 EVT DstVT = N->getValueType(0);
19233 EVT SrcVT = N->getOperand(0)->getValueType(0);
19235 if (SrcVT != MVT::f64 ||
19236 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19239 unsigned NumElts = DstVT.getVectorNumElements();
19240 EVT SVT = DstVT.getVectorElementType();
19241 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19242 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19243 MVT::v2f64, N->getOperand(0));
19244 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19246 if (ExperimentalVectorWideningLegalization) {
19247 // If we are legalizing vectors by widening, we already have the desired
19248 // legal vector type, just return it.
19249 Results.push_back(ToVecInt);
19253 SmallVector<SDValue, 8> Elts;
19254 for (unsigned i = 0, e = NumElts; i != e; ++i)
19255 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19256 ToVecInt, DAG.getIntPtrConstant(i)));
19258 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19263 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19265 default: return nullptr;
19266 case X86ISD::BSF: return "X86ISD::BSF";
19267 case X86ISD::BSR: return "X86ISD::BSR";
19268 case X86ISD::SHLD: return "X86ISD::SHLD";
19269 case X86ISD::SHRD: return "X86ISD::SHRD";
19270 case X86ISD::FAND: return "X86ISD::FAND";
19271 case X86ISD::FANDN: return "X86ISD::FANDN";
19272 case X86ISD::FOR: return "X86ISD::FOR";
19273 case X86ISD::FXOR: return "X86ISD::FXOR";
19274 case X86ISD::FSRL: return "X86ISD::FSRL";
19275 case X86ISD::FILD: return "X86ISD::FILD";
19276 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19277 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19278 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19279 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19280 case X86ISD::FLD: return "X86ISD::FLD";
19281 case X86ISD::FST: return "X86ISD::FST";
19282 case X86ISD::CALL: return "X86ISD::CALL";
19283 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19284 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19285 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19286 case X86ISD::BT: return "X86ISD::BT";
19287 case X86ISD::CMP: return "X86ISD::CMP";
19288 case X86ISD::COMI: return "X86ISD::COMI";
19289 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19290 case X86ISD::CMPM: return "X86ISD::CMPM";
19291 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19292 case X86ISD::SETCC: return "X86ISD::SETCC";
19293 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19294 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19295 case X86ISD::CMOV: return "X86ISD::CMOV";
19296 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19297 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19298 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19299 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19300 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19301 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19302 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19303 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19304 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19305 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19306 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19307 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19308 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19309 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19310 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19311 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19312 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19313 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19314 case X86ISD::HADD: return "X86ISD::HADD";
19315 case X86ISD::HSUB: return "X86ISD::HSUB";
19316 case X86ISD::FHADD: return "X86ISD::FHADD";
19317 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19318 case X86ISD::UMAX: return "X86ISD::UMAX";
19319 case X86ISD::UMIN: return "X86ISD::UMIN";
19320 case X86ISD::SMAX: return "X86ISD::SMAX";
19321 case X86ISD::SMIN: return "X86ISD::SMIN";
19322 case X86ISD::FMAX: return "X86ISD::FMAX";
19323 case X86ISD::FMIN: return "X86ISD::FMIN";
19324 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19325 case X86ISD::FMINC: return "X86ISD::FMINC";
19326 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19327 case X86ISD::FRCP: return "X86ISD::FRCP";
19328 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19329 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19330 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19331 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19332 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19333 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19334 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19335 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19336 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19337 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19338 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19339 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19340 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19341 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19342 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19343 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19344 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19345 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19346 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19347 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19348 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19349 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19350 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19351 case X86ISD::VSHL: return "X86ISD::VSHL";
19352 case X86ISD::VSRL: return "X86ISD::VSRL";
19353 case X86ISD::VSRA: return "X86ISD::VSRA";
19354 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19355 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19356 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19357 case X86ISD::CMPP: return "X86ISD::CMPP";
19358 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19359 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19360 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19361 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19362 case X86ISD::ADD: return "X86ISD::ADD";
19363 case X86ISD::SUB: return "X86ISD::SUB";
19364 case X86ISD::ADC: return "X86ISD::ADC";
19365 case X86ISD::SBB: return "X86ISD::SBB";
19366 case X86ISD::SMUL: return "X86ISD::SMUL";
19367 case X86ISD::UMUL: return "X86ISD::UMUL";
19368 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19369 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19370 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19371 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19372 case X86ISD::INC: return "X86ISD::INC";
19373 case X86ISD::DEC: return "X86ISD::DEC";
19374 case X86ISD::OR: return "X86ISD::OR";
19375 case X86ISD::XOR: return "X86ISD::XOR";
19376 case X86ISD::AND: return "X86ISD::AND";
19377 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19378 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19379 case X86ISD::PTEST: return "X86ISD::PTEST";
19380 case X86ISD::TESTP: return "X86ISD::TESTP";
19381 case X86ISD::TESTM: return "X86ISD::TESTM";
19382 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19383 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19384 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19385 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19386 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19387 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19388 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19389 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19390 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19391 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19392 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19393 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19394 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19395 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19396 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19397 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19398 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19399 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19400 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19401 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19402 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19403 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19404 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19405 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19406 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19407 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19408 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19409 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19410 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19411 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19412 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19413 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19414 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19415 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19416 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19417 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19418 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19419 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19420 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19421 case X86ISD::SAHF: return "X86ISD::SAHF";
19422 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19423 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19424 case X86ISD::FMADD: return "X86ISD::FMADD";
19425 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19426 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19427 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19428 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19429 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19430 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19431 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19432 case X86ISD::XTEST: return "X86ISD::XTEST";
19436 // isLegalAddressingMode - Return true if the addressing mode represented
19437 // by AM is legal for this target, for a load/store of the specified type.
19438 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19440 // X86 supports extremely general addressing modes.
19441 CodeModel::Model M = getTargetMachine().getCodeModel();
19442 Reloc::Model R = getTargetMachine().getRelocationModel();
19444 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19445 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19450 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19452 // If a reference to this global requires an extra load, we can't fold it.
19453 if (isGlobalStubReference(GVFlags))
19456 // If BaseGV requires a register for the PIC base, we cannot also have a
19457 // BaseReg specified.
19458 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19461 // If lower 4G is not available, then we must use rip-relative addressing.
19462 if ((M != CodeModel::Small || R != Reloc::Static) &&
19463 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19467 switch (AM.Scale) {
19473 // These scales always work.
19478 // These scales are formed with basereg+scalereg. Only accept if there is
19483 default: // Other stuff never works.
19490 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19491 unsigned Bits = Ty->getScalarSizeInBits();
19493 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19494 // particularly cheaper than those without.
19498 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19499 // variable shifts just as cheap as scalar ones.
19500 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19503 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19504 // fully general vector.
19508 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19509 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19511 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19512 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19513 return NumBits1 > NumBits2;
19516 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19517 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19520 if (!isTypeLegal(EVT::getEVT(Ty1)))
19523 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19525 // Assuming the caller doesn't have a zeroext or signext return parameter,
19526 // truncation all the way down to i1 is valid.
19530 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19531 return isInt<32>(Imm);
19534 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19535 // Can also use sub to handle negated immediates.
19536 return isInt<32>(Imm);
19539 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19540 if (!VT1.isInteger() || !VT2.isInteger())
19542 unsigned NumBits1 = VT1.getSizeInBits();
19543 unsigned NumBits2 = VT2.getSizeInBits();
19544 return NumBits1 > NumBits2;
19547 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19548 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19549 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19552 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19553 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19554 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19557 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19558 EVT VT1 = Val.getValueType();
19559 if (isZExtFree(VT1, VT2))
19562 if (Val.getOpcode() != ISD::LOAD)
19565 if (!VT1.isSimple() || !VT1.isInteger() ||
19566 !VT2.isSimple() || !VT2.isInteger())
19569 switch (VT1.getSimpleVT().SimpleTy) {
19574 // X86 has 8, 16, and 32-bit zero-extending loads.
19582 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19583 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19586 VT = VT.getScalarType();
19588 if (!VT.isSimple())
19591 switch (VT.getSimpleVT().SimpleTy) {
19602 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19603 // i16 instructions are longer (0x66 prefix) and potentially slower.
19604 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19607 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19608 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19609 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19610 /// are assumed to be legal.
19612 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19614 if (!VT.isSimple())
19617 MVT SVT = VT.getSimpleVT();
19619 // Very little shuffling can be done for 64-bit vectors right now.
19620 if (VT.getSizeInBits() == 64)
19623 // If this is a single-input shuffle with no 128 bit lane crossings we can
19624 // lower it into pshufb.
19625 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19626 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19627 bool isLegal = true;
19628 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19629 if (M[I] >= (int)SVT.getVectorNumElements() ||
19630 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19639 // FIXME: blends, shifts.
19640 return (SVT.getVectorNumElements() == 2 ||
19641 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19642 isMOVLMask(M, SVT) ||
19643 isMOVHLPSMask(M, SVT) ||
19644 isSHUFPMask(M, SVT) ||
19645 isPSHUFDMask(M, SVT) ||
19646 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19647 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19648 isPALIGNRMask(M, SVT, Subtarget) ||
19649 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19650 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19651 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19652 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19653 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19654 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19658 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19660 if (!VT.isSimple())
19663 MVT SVT = VT.getSimpleVT();
19664 unsigned NumElts = SVT.getVectorNumElements();
19665 // FIXME: This collection of masks seems suspect.
19668 if (NumElts == 4 && SVT.is128BitVector()) {
19669 return (isMOVLMask(Mask, SVT) ||
19670 isCommutedMOVLMask(Mask, SVT, true) ||
19671 isSHUFPMask(Mask, SVT) ||
19672 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19673 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19674 Subtarget->hasInt256()));
19679 //===----------------------------------------------------------------------===//
19680 // X86 Scheduler Hooks
19681 //===----------------------------------------------------------------------===//
19683 /// Utility function to emit xbegin specifying the start of an RTM region.
19684 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19685 const TargetInstrInfo *TII) {
19686 DebugLoc DL = MI->getDebugLoc();
19688 const BasicBlock *BB = MBB->getBasicBlock();
19689 MachineFunction::iterator I = MBB;
19692 // For the v = xbegin(), we generate
19703 MachineBasicBlock *thisMBB = MBB;
19704 MachineFunction *MF = MBB->getParent();
19705 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19706 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19707 MF->insert(I, mainMBB);
19708 MF->insert(I, sinkMBB);
19710 // Transfer the remainder of BB and its successor edges to sinkMBB.
19711 sinkMBB->splice(sinkMBB->begin(), MBB,
19712 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19713 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19717 // # fallthrough to mainMBB
19718 // # abortion to sinkMBB
19719 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19720 thisMBB->addSuccessor(mainMBB);
19721 thisMBB->addSuccessor(sinkMBB);
19725 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19726 mainMBB->addSuccessor(sinkMBB);
19729 // EAX is live into the sinkMBB
19730 sinkMBB->addLiveIn(X86::EAX);
19731 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19732 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19735 MI->eraseFromParent();
19739 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19740 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19741 // in the .td file.
19742 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19743 const TargetInstrInfo *TII) {
19745 switch (MI->getOpcode()) {
19746 default: llvm_unreachable("illegal opcode!");
19747 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19748 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19749 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19750 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19751 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19752 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19753 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19754 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19757 DebugLoc dl = MI->getDebugLoc();
19758 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19760 unsigned NumArgs = MI->getNumOperands();
19761 for (unsigned i = 1; i < NumArgs; ++i) {
19762 MachineOperand &Op = MI->getOperand(i);
19763 if (!(Op.isReg() && Op.isImplicit()))
19764 MIB.addOperand(Op);
19766 if (MI->hasOneMemOperand())
19767 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19769 BuildMI(*BB, MI, dl,
19770 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19771 .addReg(X86::XMM0);
19773 MI->eraseFromParent();
19777 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19778 // defs in an instruction pattern
19779 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19780 const TargetInstrInfo *TII) {
19782 switch (MI->getOpcode()) {
19783 default: llvm_unreachable("illegal opcode!");
19784 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19785 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19786 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19787 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19788 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19789 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19790 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19791 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19794 DebugLoc dl = MI->getDebugLoc();
19795 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19797 unsigned NumArgs = MI->getNumOperands(); // remove the results
19798 for (unsigned i = 1; i < NumArgs; ++i) {
19799 MachineOperand &Op = MI->getOperand(i);
19800 if (!(Op.isReg() && Op.isImplicit()))
19801 MIB.addOperand(Op);
19803 if (MI->hasOneMemOperand())
19804 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19806 BuildMI(*BB, MI, dl,
19807 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19810 MI->eraseFromParent();
19814 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19815 const TargetInstrInfo *TII,
19816 const X86Subtarget* Subtarget) {
19817 DebugLoc dl = MI->getDebugLoc();
19819 // Address into RAX/EAX, other two args into ECX, EDX.
19820 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19821 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19822 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19823 for (int i = 0; i < X86::AddrNumOperands; ++i)
19824 MIB.addOperand(MI->getOperand(i));
19826 unsigned ValOps = X86::AddrNumOperands;
19827 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19828 .addReg(MI->getOperand(ValOps).getReg());
19829 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19830 .addReg(MI->getOperand(ValOps+1).getReg());
19832 // The instruction doesn't actually take any operands though.
19833 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19835 MI->eraseFromParent(); // The pseudo is gone now.
19839 MachineBasicBlock *
19840 X86TargetLowering::EmitVAARG64WithCustomInserter(
19842 MachineBasicBlock *MBB) const {
19843 // Emit va_arg instruction on X86-64.
19845 // Operands to this pseudo-instruction:
19846 // 0 ) Output : destination address (reg)
19847 // 1-5) Input : va_list address (addr, i64mem)
19848 // 6 ) ArgSize : Size (in bytes) of vararg type
19849 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19850 // 8 ) Align : Alignment of type
19851 // 9 ) EFLAGS (implicit-def)
19853 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19854 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19856 unsigned DestReg = MI->getOperand(0).getReg();
19857 MachineOperand &Base = MI->getOperand(1);
19858 MachineOperand &Scale = MI->getOperand(2);
19859 MachineOperand &Index = MI->getOperand(3);
19860 MachineOperand &Disp = MI->getOperand(4);
19861 MachineOperand &Segment = MI->getOperand(5);
19862 unsigned ArgSize = MI->getOperand(6).getImm();
19863 unsigned ArgMode = MI->getOperand(7).getImm();
19864 unsigned Align = MI->getOperand(8).getImm();
19866 // Memory Reference
19867 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19868 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19869 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19871 // Machine Information
19872 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19873 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19874 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19875 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19876 DebugLoc DL = MI->getDebugLoc();
19878 // struct va_list {
19881 // i64 overflow_area (address)
19882 // i64 reg_save_area (address)
19884 // sizeof(va_list) = 24
19885 // alignment(va_list) = 8
19887 unsigned TotalNumIntRegs = 6;
19888 unsigned TotalNumXMMRegs = 8;
19889 bool UseGPOffset = (ArgMode == 1);
19890 bool UseFPOffset = (ArgMode == 2);
19891 unsigned MaxOffset = TotalNumIntRegs * 8 +
19892 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19894 /* Align ArgSize to a multiple of 8 */
19895 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19896 bool NeedsAlign = (Align > 8);
19898 MachineBasicBlock *thisMBB = MBB;
19899 MachineBasicBlock *overflowMBB;
19900 MachineBasicBlock *offsetMBB;
19901 MachineBasicBlock *endMBB;
19903 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19904 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19905 unsigned OffsetReg = 0;
19907 if (!UseGPOffset && !UseFPOffset) {
19908 // If we only pull from the overflow region, we don't create a branch.
19909 // We don't need to alter control flow.
19910 OffsetDestReg = 0; // unused
19911 OverflowDestReg = DestReg;
19913 offsetMBB = nullptr;
19914 overflowMBB = thisMBB;
19917 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19918 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19919 // If not, pull from overflow_area. (branch to overflowMBB)
19924 // offsetMBB overflowMBB
19929 // Registers for the PHI in endMBB
19930 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19931 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19933 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19934 MachineFunction *MF = MBB->getParent();
19935 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19936 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19937 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19939 MachineFunction::iterator MBBIter = MBB;
19942 // Insert the new basic blocks
19943 MF->insert(MBBIter, offsetMBB);
19944 MF->insert(MBBIter, overflowMBB);
19945 MF->insert(MBBIter, endMBB);
19947 // Transfer the remainder of MBB and its successor edges to endMBB.
19948 endMBB->splice(endMBB->begin(), thisMBB,
19949 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19950 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19952 // Make offsetMBB and overflowMBB successors of thisMBB
19953 thisMBB->addSuccessor(offsetMBB);
19954 thisMBB->addSuccessor(overflowMBB);
19956 // endMBB is a successor of both offsetMBB and overflowMBB
19957 offsetMBB->addSuccessor(endMBB);
19958 overflowMBB->addSuccessor(endMBB);
19960 // Load the offset value into a register
19961 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19962 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19966 .addDisp(Disp, UseFPOffset ? 4 : 0)
19967 .addOperand(Segment)
19968 .setMemRefs(MMOBegin, MMOEnd);
19970 // Check if there is enough room left to pull this argument.
19971 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19973 .addImm(MaxOffset + 8 - ArgSizeA8);
19975 // Branch to "overflowMBB" if offset >= max
19976 // Fall through to "offsetMBB" otherwise
19977 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19978 .addMBB(overflowMBB);
19981 // In offsetMBB, emit code to use the reg_save_area.
19983 assert(OffsetReg != 0);
19985 // Read the reg_save_area address.
19986 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19987 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19992 .addOperand(Segment)
19993 .setMemRefs(MMOBegin, MMOEnd);
19995 // Zero-extend the offset
19996 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19997 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20000 .addImm(X86::sub_32bit);
20002 // Add the offset to the reg_save_area to get the final address.
20003 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20004 .addReg(OffsetReg64)
20005 .addReg(RegSaveReg);
20007 // Compute the offset for the next argument
20008 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20009 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20011 .addImm(UseFPOffset ? 16 : 8);
20013 // Store it back into the va_list.
20014 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20018 .addDisp(Disp, UseFPOffset ? 4 : 0)
20019 .addOperand(Segment)
20020 .addReg(NextOffsetReg)
20021 .setMemRefs(MMOBegin, MMOEnd);
20024 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20029 // Emit code to use overflow area
20032 // Load the overflow_area address into a register.
20033 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20034 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20039 .addOperand(Segment)
20040 .setMemRefs(MMOBegin, MMOEnd);
20042 // If we need to align it, do so. Otherwise, just copy the address
20043 // to OverflowDestReg.
20045 // Align the overflow address
20046 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20047 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20049 // aligned_addr = (addr + (align-1)) & ~(align-1)
20050 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20051 .addReg(OverflowAddrReg)
20054 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20056 .addImm(~(uint64_t)(Align-1));
20058 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20059 .addReg(OverflowAddrReg);
20062 // Compute the next overflow address after this argument.
20063 // (the overflow address should be kept 8-byte aligned)
20064 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20065 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20066 .addReg(OverflowDestReg)
20067 .addImm(ArgSizeA8);
20069 // Store the new overflow address.
20070 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20075 .addOperand(Segment)
20076 .addReg(NextAddrReg)
20077 .setMemRefs(MMOBegin, MMOEnd);
20079 // If we branched, emit the PHI to the front of endMBB.
20081 BuildMI(*endMBB, endMBB->begin(), DL,
20082 TII->get(X86::PHI), DestReg)
20083 .addReg(OffsetDestReg).addMBB(offsetMBB)
20084 .addReg(OverflowDestReg).addMBB(overflowMBB);
20087 // Erase the pseudo instruction
20088 MI->eraseFromParent();
20093 MachineBasicBlock *
20094 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20096 MachineBasicBlock *MBB) const {
20097 // Emit code to save XMM registers to the stack. The ABI says that the
20098 // number of registers to save is given in %al, so it's theoretically
20099 // possible to do an indirect jump trick to avoid saving all of them,
20100 // however this code takes a simpler approach and just executes all
20101 // of the stores if %al is non-zero. It's less code, and it's probably
20102 // easier on the hardware branch predictor, and stores aren't all that
20103 // expensive anyway.
20105 // Create the new basic blocks. One block contains all the XMM stores,
20106 // and one block is the final destination regardless of whether any
20107 // stores were performed.
20108 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20109 MachineFunction *F = MBB->getParent();
20110 MachineFunction::iterator MBBIter = MBB;
20112 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20113 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20114 F->insert(MBBIter, XMMSaveMBB);
20115 F->insert(MBBIter, EndMBB);
20117 // Transfer the remainder of MBB and its successor edges to EndMBB.
20118 EndMBB->splice(EndMBB->begin(), MBB,
20119 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20120 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20122 // The original block will now fall through to the XMM save block.
20123 MBB->addSuccessor(XMMSaveMBB);
20124 // The XMMSaveMBB will fall through to the end block.
20125 XMMSaveMBB->addSuccessor(EndMBB);
20127 // Now add the instructions.
20128 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20129 DebugLoc DL = MI->getDebugLoc();
20131 unsigned CountReg = MI->getOperand(0).getReg();
20132 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20133 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20135 if (!Subtarget->isTargetWin64()) {
20136 // If %al is 0, branch around the XMM save block.
20137 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20138 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20139 MBB->addSuccessor(EndMBB);
20142 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20143 // that was just emitted, but clearly shouldn't be "saved".
20144 assert((MI->getNumOperands() <= 3 ||
20145 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20146 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20147 && "Expected last argument to be EFLAGS");
20148 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20149 // In the XMM save block, save all the XMM argument registers.
20150 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20151 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20152 MachineMemOperand *MMO =
20153 F->getMachineMemOperand(
20154 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20155 MachineMemOperand::MOStore,
20156 /*Size=*/16, /*Align=*/16);
20157 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20158 .addFrameIndex(RegSaveFrameIndex)
20159 .addImm(/*Scale=*/1)
20160 .addReg(/*IndexReg=*/0)
20161 .addImm(/*Disp=*/Offset)
20162 .addReg(/*Segment=*/0)
20163 .addReg(MI->getOperand(i).getReg())
20164 .addMemOperand(MMO);
20167 MI->eraseFromParent(); // The pseudo instruction is gone now.
20172 // The EFLAGS operand of SelectItr might be missing a kill marker
20173 // because there were multiple uses of EFLAGS, and ISel didn't know
20174 // which to mark. Figure out whether SelectItr should have had a
20175 // kill marker, and set it if it should. Returns the correct kill
20177 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20178 MachineBasicBlock* BB,
20179 const TargetRegisterInfo* TRI) {
20180 // Scan forward through BB for a use/def of EFLAGS.
20181 MachineBasicBlock::iterator miI(std::next(SelectItr));
20182 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20183 const MachineInstr& mi = *miI;
20184 if (mi.readsRegister(X86::EFLAGS))
20186 if (mi.definesRegister(X86::EFLAGS))
20187 break; // Should have kill-flag - update below.
20190 // If we hit the end of the block, check whether EFLAGS is live into a
20192 if (miI == BB->end()) {
20193 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20194 sEnd = BB->succ_end();
20195 sItr != sEnd; ++sItr) {
20196 MachineBasicBlock* succ = *sItr;
20197 if (succ->isLiveIn(X86::EFLAGS))
20202 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20203 // out. SelectMI should have a kill flag on EFLAGS.
20204 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20208 MachineBasicBlock *
20209 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20210 MachineBasicBlock *BB) const {
20211 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20212 DebugLoc DL = MI->getDebugLoc();
20214 // To "insert" a SELECT_CC instruction, we actually have to insert the
20215 // diamond control-flow pattern. The incoming instruction knows the
20216 // destination vreg to set, the condition code register to branch on, the
20217 // true/false values to select between, and a branch opcode to use.
20218 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20219 MachineFunction::iterator It = BB;
20225 // cmpTY ccX, r1, r2
20227 // fallthrough --> copy0MBB
20228 MachineBasicBlock *thisMBB = BB;
20229 MachineFunction *F = BB->getParent();
20230 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20231 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20232 F->insert(It, copy0MBB);
20233 F->insert(It, sinkMBB);
20235 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20236 // live into the sink and copy blocks.
20237 const TargetRegisterInfo *TRI =
20238 BB->getParent()->getSubtarget().getRegisterInfo();
20239 if (!MI->killsRegister(X86::EFLAGS) &&
20240 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20241 copy0MBB->addLiveIn(X86::EFLAGS);
20242 sinkMBB->addLiveIn(X86::EFLAGS);
20245 // Transfer the remainder of BB and its successor edges to sinkMBB.
20246 sinkMBB->splice(sinkMBB->begin(), BB,
20247 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20248 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20250 // Add the true and fallthrough blocks as its successors.
20251 BB->addSuccessor(copy0MBB);
20252 BB->addSuccessor(sinkMBB);
20254 // Create the conditional branch instruction.
20256 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20257 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20260 // %FalseValue = ...
20261 // # fallthrough to sinkMBB
20262 copy0MBB->addSuccessor(sinkMBB);
20265 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20267 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20268 TII->get(X86::PHI), MI->getOperand(0).getReg())
20269 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20270 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20272 MI->eraseFromParent(); // The pseudo instruction is gone now.
20276 MachineBasicBlock *
20277 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20278 MachineBasicBlock *BB) const {
20279 MachineFunction *MF = BB->getParent();
20280 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20281 DebugLoc DL = MI->getDebugLoc();
20282 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20284 assert(MF->shouldSplitStack());
20286 const bool Is64Bit = Subtarget->is64Bit();
20287 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20289 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20290 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20293 // ... [Till the alloca]
20294 // If stacklet is not large enough, jump to mallocMBB
20297 // Allocate by subtracting from RSP
20298 // Jump to continueMBB
20301 // Allocate by call to runtime
20305 // [rest of original BB]
20308 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20309 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20310 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20312 MachineRegisterInfo &MRI = MF->getRegInfo();
20313 const TargetRegisterClass *AddrRegClass =
20314 getRegClassFor(getPointerTy());
20316 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20317 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20318 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20319 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20320 sizeVReg = MI->getOperand(1).getReg(),
20321 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20323 MachineFunction::iterator MBBIter = BB;
20326 MF->insert(MBBIter, bumpMBB);
20327 MF->insert(MBBIter, mallocMBB);
20328 MF->insert(MBBIter, continueMBB);
20330 continueMBB->splice(continueMBB->begin(), BB,
20331 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20332 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20334 // Add code to the main basic block to check if the stack limit has been hit,
20335 // and if so, jump to mallocMBB otherwise to bumpMBB.
20336 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20337 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20338 .addReg(tmpSPVReg).addReg(sizeVReg);
20339 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20340 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20341 .addReg(SPLimitVReg);
20342 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20344 // bumpMBB simply decreases the stack pointer, since we know the current
20345 // stacklet has enough space.
20346 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20347 .addReg(SPLimitVReg);
20348 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20349 .addReg(SPLimitVReg);
20350 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20352 // Calls into a routine in libgcc to allocate more space from the heap.
20353 const uint32_t *RegMask = MF->getTarget()
20354 .getSubtargetImpl()
20355 ->getRegisterInfo()
20356 ->getCallPreservedMask(CallingConv::C);
20358 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20360 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20361 .addExternalSymbol("__morestack_allocate_stack_space")
20362 .addRegMask(RegMask)
20363 .addReg(X86::RDI, RegState::Implicit)
20364 .addReg(X86::RAX, RegState::ImplicitDefine);
20365 } else if (Is64Bit) {
20366 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20368 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20369 .addExternalSymbol("__morestack_allocate_stack_space")
20370 .addRegMask(RegMask)
20371 .addReg(X86::EDI, RegState::Implicit)
20372 .addReg(X86::EAX, RegState::ImplicitDefine);
20374 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20376 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20377 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20378 .addExternalSymbol("__morestack_allocate_stack_space")
20379 .addRegMask(RegMask)
20380 .addReg(X86::EAX, RegState::ImplicitDefine);
20384 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20387 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20388 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20389 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20391 // Set up the CFG correctly.
20392 BB->addSuccessor(bumpMBB);
20393 BB->addSuccessor(mallocMBB);
20394 mallocMBB->addSuccessor(continueMBB);
20395 bumpMBB->addSuccessor(continueMBB);
20397 // Take care of the PHI nodes.
20398 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20399 MI->getOperand(0).getReg())
20400 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20401 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20403 // Delete the original pseudo instruction.
20404 MI->eraseFromParent();
20407 return continueMBB;
20410 MachineBasicBlock *
20411 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20412 MachineBasicBlock *BB) const {
20413 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20414 DebugLoc DL = MI->getDebugLoc();
20416 assert(!Subtarget->isTargetMacho());
20418 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20419 // non-trivial part is impdef of ESP.
20421 if (Subtarget->isTargetWin64()) {
20422 if (Subtarget->isTargetCygMing()) {
20423 // ___chkstk(Mingw64):
20424 // Clobbers R10, R11, RAX and EFLAGS.
20426 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20427 .addExternalSymbol("___chkstk")
20428 .addReg(X86::RAX, RegState::Implicit)
20429 .addReg(X86::RSP, RegState::Implicit)
20430 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20431 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20432 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20434 // __chkstk(MSVCRT): does not update stack pointer.
20435 // Clobbers R10, R11 and EFLAGS.
20436 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20437 .addExternalSymbol("__chkstk")
20438 .addReg(X86::RAX, RegState::Implicit)
20439 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20440 // RAX has the offset to be subtracted from RSP.
20441 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20446 const char *StackProbeSymbol =
20447 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
20449 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20450 .addExternalSymbol(StackProbeSymbol)
20451 .addReg(X86::EAX, RegState::Implicit)
20452 .addReg(X86::ESP, RegState::Implicit)
20453 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20454 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20455 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20458 MI->eraseFromParent(); // The pseudo instruction is gone now.
20462 MachineBasicBlock *
20463 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20464 MachineBasicBlock *BB) const {
20465 // This is pretty easy. We're taking the value that we received from
20466 // our load from the relocation, sticking it in either RDI (x86-64)
20467 // or EAX and doing an indirect call. The return value will then
20468 // be in the normal return register.
20469 MachineFunction *F = BB->getParent();
20470 const X86InstrInfo *TII =
20471 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20472 DebugLoc DL = MI->getDebugLoc();
20474 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20475 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20477 // Get a register mask for the lowered call.
20478 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20479 // proper register mask.
20480 const uint32_t *RegMask = F->getTarget()
20481 .getSubtargetImpl()
20482 ->getRegisterInfo()
20483 ->getCallPreservedMask(CallingConv::C);
20484 if (Subtarget->is64Bit()) {
20485 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20486 TII->get(X86::MOV64rm), X86::RDI)
20488 .addImm(0).addReg(0)
20489 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20490 MI->getOperand(3).getTargetFlags())
20492 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20493 addDirectMem(MIB, X86::RDI);
20494 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20495 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20496 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20497 TII->get(X86::MOV32rm), X86::EAX)
20499 .addImm(0).addReg(0)
20500 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20501 MI->getOperand(3).getTargetFlags())
20503 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20504 addDirectMem(MIB, X86::EAX);
20505 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20507 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20508 TII->get(X86::MOV32rm), X86::EAX)
20509 .addReg(TII->getGlobalBaseReg(F))
20510 .addImm(0).addReg(0)
20511 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20512 MI->getOperand(3).getTargetFlags())
20514 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20515 addDirectMem(MIB, X86::EAX);
20516 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20519 MI->eraseFromParent(); // The pseudo instruction is gone now.
20523 MachineBasicBlock *
20524 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20525 MachineBasicBlock *MBB) const {
20526 DebugLoc DL = MI->getDebugLoc();
20527 MachineFunction *MF = MBB->getParent();
20528 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20529 MachineRegisterInfo &MRI = MF->getRegInfo();
20531 const BasicBlock *BB = MBB->getBasicBlock();
20532 MachineFunction::iterator I = MBB;
20535 // Memory Reference
20536 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20537 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20540 unsigned MemOpndSlot = 0;
20542 unsigned CurOp = 0;
20544 DstReg = MI->getOperand(CurOp++).getReg();
20545 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20546 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20547 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20548 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20550 MemOpndSlot = CurOp;
20552 MVT PVT = getPointerTy();
20553 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20554 "Invalid Pointer Size!");
20556 // For v = setjmp(buf), we generate
20559 // buf[LabelOffset] = restoreMBB
20560 // SjLjSetup restoreMBB
20566 // v = phi(main, restore)
20571 MachineBasicBlock *thisMBB = MBB;
20572 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20573 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20574 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20575 MF->insert(I, mainMBB);
20576 MF->insert(I, sinkMBB);
20577 MF->push_back(restoreMBB);
20579 MachineInstrBuilder MIB;
20581 // Transfer the remainder of BB and its successor edges to sinkMBB.
20582 sinkMBB->splice(sinkMBB->begin(), MBB,
20583 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20584 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20587 unsigned PtrStoreOpc = 0;
20588 unsigned LabelReg = 0;
20589 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20590 Reloc::Model RM = MF->getTarget().getRelocationModel();
20591 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20592 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20594 // Prepare IP either in reg or imm.
20595 if (!UseImmLabel) {
20596 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20597 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20598 LabelReg = MRI.createVirtualRegister(PtrRC);
20599 if (Subtarget->is64Bit()) {
20600 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20604 .addMBB(restoreMBB)
20607 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20608 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20609 .addReg(XII->getGlobalBaseReg(MF))
20612 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20616 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20618 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20619 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20620 if (i == X86::AddrDisp)
20621 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20623 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20626 MIB.addReg(LabelReg);
20628 MIB.addMBB(restoreMBB);
20629 MIB.setMemRefs(MMOBegin, MMOEnd);
20631 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20632 .addMBB(restoreMBB);
20634 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20635 MF->getSubtarget().getRegisterInfo());
20636 MIB.addRegMask(RegInfo->getNoPreservedMask());
20637 thisMBB->addSuccessor(mainMBB);
20638 thisMBB->addSuccessor(restoreMBB);
20642 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20643 mainMBB->addSuccessor(sinkMBB);
20646 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20647 TII->get(X86::PHI), DstReg)
20648 .addReg(mainDstReg).addMBB(mainMBB)
20649 .addReg(restoreDstReg).addMBB(restoreMBB);
20652 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20653 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20654 restoreMBB->addSuccessor(sinkMBB);
20656 MI->eraseFromParent();
20660 MachineBasicBlock *
20661 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20662 MachineBasicBlock *MBB) const {
20663 DebugLoc DL = MI->getDebugLoc();
20664 MachineFunction *MF = MBB->getParent();
20665 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20666 MachineRegisterInfo &MRI = MF->getRegInfo();
20668 // Memory Reference
20669 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20670 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20672 MVT PVT = getPointerTy();
20673 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20674 "Invalid Pointer Size!");
20676 const TargetRegisterClass *RC =
20677 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20678 unsigned Tmp = MRI.createVirtualRegister(RC);
20679 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20680 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20681 MF->getSubtarget().getRegisterInfo());
20682 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20683 unsigned SP = RegInfo->getStackRegister();
20685 MachineInstrBuilder MIB;
20687 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20688 const int64_t SPOffset = 2 * PVT.getStoreSize();
20690 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20691 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20694 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20695 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20696 MIB.addOperand(MI->getOperand(i));
20697 MIB.setMemRefs(MMOBegin, MMOEnd);
20699 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20700 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20701 if (i == X86::AddrDisp)
20702 MIB.addDisp(MI->getOperand(i), LabelOffset);
20704 MIB.addOperand(MI->getOperand(i));
20706 MIB.setMemRefs(MMOBegin, MMOEnd);
20708 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20709 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20710 if (i == X86::AddrDisp)
20711 MIB.addDisp(MI->getOperand(i), SPOffset);
20713 MIB.addOperand(MI->getOperand(i));
20715 MIB.setMemRefs(MMOBegin, MMOEnd);
20717 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20719 MI->eraseFromParent();
20723 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20724 // accumulator loops. Writing back to the accumulator allows the coalescer
20725 // to remove extra copies in the loop.
20726 MachineBasicBlock *
20727 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20728 MachineBasicBlock *MBB) const {
20729 MachineOperand &AddendOp = MI->getOperand(3);
20731 // Bail out early if the addend isn't a register - we can't switch these.
20732 if (!AddendOp.isReg())
20735 MachineFunction &MF = *MBB->getParent();
20736 MachineRegisterInfo &MRI = MF.getRegInfo();
20738 // Check whether the addend is defined by a PHI:
20739 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20740 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20741 if (!AddendDef.isPHI())
20744 // Look for the following pattern:
20746 // %addend = phi [%entry, 0], [%loop, %result]
20748 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20752 // %addend = phi [%entry, 0], [%loop, %result]
20754 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20756 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20757 assert(AddendDef.getOperand(i).isReg());
20758 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20759 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20760 if (&PHISrcInst == MI) {
20761 // Found a matching instruction.
20762 unsigned NewFMAOpc = 0;
20763 switch (MI->getOpcode()) {
20764 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20765 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20766 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20767 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20768 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20769 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20770 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20771 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20772 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20773 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20774 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20775 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20776 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20777 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20778 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20779 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20780 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20781 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20782 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20783 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20785 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20786 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20787 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20788 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20789 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20790 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20791 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20792 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20793 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20794 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20795 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20796 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20797 default: llvm_unreachable("Unrecognized FMA variant.");
20800 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20801 MachineInstrBuilder MIB =
20802 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20803 .addOperand(MI->getOperand(0))
20804 .addOperand(MI->getOperand(3))
20805 .addOperand(MI->getOperand(2))
20806 .addOperand(MI->getOperand(1));
20807 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20808 MI->eraseFromParent();
20815 MachineBasicBlock *
20816 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20817 MachineBasicBlock *BB) const {
20818 switch (MI->getOpcode()) {
20819 default: llvm_unreachable("Unexpected instr type to insert");
20820 case X86::TAILJMPd64:
20821 case X86::TAILJMPr64:
20822 case X86::TAILJMPm64:
20823 llvm_unreachable("TAILJMP64 would not be touched here.");
20824 case X86::TCRETURNdi64:
20825 case X86::TCRETURNri64:
20826 case X86::TCRETURNmi64:
20828 case X86::WIN_ALLOCA:
20829 return EmitLoweredWinAlloca(MI, BB);
20830 case X86::SEG_ALLOCA_32:
20831 case X86::SEG_ALLOCA_64:
20832 return EmitLoweredSegAlloca(MI, BB);
20833 case X86::TLSCall_32:
20834 case X86::TLSCall_64:
20835 return EmitLoweredTLSCall(MI, BB);
20836 case X86::CMOV_GR8:
20837 case X86::CMOV_FR32:
20838 case X86::CMOV_FR64:
20839 case X86::CMOV_V4F32:
20840 case X86::CMOV_V2F64:
20841 case X86::CMOV_V2I64:
20842 case X86::CMOV_V8F32:
20843 case X86::CMOV_V4F64:
20844 case X86::CMOV_V4I64:
20845 case X86::CMOV_V16F32:
20846 case X86::CMOV_V8F64:
20847 case X86::CMOV_V8I64:
20848 case X86::CMOV_GR16:
20849 case X86::CMOV_GR32:
20850 case X86::CMOV_RFP32:
20851 case X86::CMOV_RFP64:
20852 case X86::CMOV_RFP80:
20853 return EmitLoweredSelect(MI, BB);
20855 case X86::FP32_TO_INT16_IN_MEM:
20856 case X86::FP32_TO_INT32_IN_MEM:
20857 case X86::FP32_TO_INT64_IN_MEM:
20858 case X86::FP64_TO_INT16_IN_MEM:
20859 case X86::FP64_TO_INT32_IN_MEM:
20860 case X86::FP64_TO_INT64_IN_MEM:
20861 case X86::FP80_TO_INT16_IN_MEM:
20862 case X86::FP80_TO_INT32_IN_MEM:
20863 case X86::FP80_TO_INT64_IN_MEM: {
20864 MachineFunction *F = BB->getParent();
20865 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20866 DebugLoc DL = MI->getDebugLoc();
20868 // Change the floating point control register to use "round towards zero"
20869 // mode when truncating to an integer value.
20870 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20871 addFrameReference(BuildMI(*BB, MI, DL,
20872 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20874 // Load the old value of the high byte of the control word...
20876 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20877 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20880 // Set the high part to be round to zero...
20881 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20884 // Reload the modified control word now...
20885 addFrameReference(BuildMI(*BB, MI, DL,
20886 TII->get(X86::FLDCW16m)), CWFrameIdx);
20888 // Restore the memory image of control word to original value
20889 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20892 // Get the X86 opcode to use.
20894 switch (MI->getOpcode()) {
20895 default: llvm_unreachable("illegal opcode!");
20896 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20897 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20898 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20899 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20900 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20901 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20902 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20903 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20904 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20908 MachineOperand &Op = MI->getOperand(0);
20910 AM.BaseType = X86AddressMode::RegBase;
20911 AM.Base.Reg = Op.getReg();
20913 AM.BaseType = X86AddressMode::FrameIndexBase;
20914 AM.Base.FrameIndex = Op.getIndex();
20916 Op = MI->getOperand(1);
20918 AM.Scale = Op.getImm();
20919 Op = MI->getOperand(2);
20921 AM.IndexReg = Op.getImm();
20922 Op = MI->getOperand(3);
20923 if (Op.isGlobal()) {
20924 AM.GV = Op.getGlobal();
20926 AM.Disp = Op.getImm();
20928 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20929 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20931 // Reload the original control word now.
20932 addFrameReference(BuildMI(*BB, MI, DL,
20933 TII->get(X86::FLDCW16m)), CWFrameIdx);
20935 MI->eraseFromParent(); // The pseudo instruction is gone now.
20938 // String/text processing lowering.
20939 case X86::PCMPISTRM128REG:
20940 case X86::VPCMPISTRM128REG:
20941 case X86::PCMPISTRM128MEM:
20942 case X86::VPCMPISTRM128MEM:
20943 case X86::PCMPESTRM128REG:
20944 case X86::VPCMPESTRM128REG:
20945 case X86::PCMPESTRM128MEM:
20946 case X86::VPCMPESTRM128MEM:
20947 assert(Subtarget->hasSSE42() &&
20948 "Target must have SSE4.2 or AVX features enabled");
20949 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20951 // String/text processing lowering.
20952 case X86::PCMPISTRIREG:
20953 case X86::VPCMPISTRIREG:
20954 case X86::PCMPISTRIMEM:
20955 case X86::VPCMPISTRIMEM:
20956 case X86::PCMPESTRIREG:
20957 case X86::VPCMPESTRIREG:
20958 case X86::PCMPESTRIMEM:
20959 case X86::VPCMPESTRIMEM:
20960 assert(Subtarget->hasSSE42() &&
20961 "Target must have SSE4.2 or AVX features enabled");
20962 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20964 // Thread synchronization.
20966 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20971 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20973 case X86::VASTART_SAVE_XMM_REGS:
20974 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20976 case X86::VAARG_64:
20977 return EmitVAARG64WithCustomInserter(MI, BB);
20979 case X86::EH_SjLj_SetJmp32:
20980 case X86::EH_SjLj_SetJmp64:
20981 return emitEHSjLjSetJmp(MI, BB);
20983 case X86::EH_SjLj_LongJmp32:
20984 case X86::EH_SjLj_LongJmp64:
20985 return emitEHSjLjLongJmp(MI, BB);
20987 case TargetOpcode::STACKMAP:
20988 case TargetOpcode::PATCHPOINT:
20989 return emitPatchPoint(MI, BB);
20991 case X86::VFMADDPDr213r:
20992 case X86::VFMADDPSr213r:
20993 case X86::VFMADDSDr213r:
20994 case X86::VFMADDSSr213r:
20995 case X86::VFMSUBPDr213r:
20996 case X86::VFMSUBPSr213r:
20997 case X86::VFMSUBSDr213r:
20998 case X86::VFMSUBSSr213r:
20999 case X86::VFNMADDPDr213r:
21000 case X86::VFNMADDPSr213r:
21001 case X86::VFNMADDSDr213r:
21002 case X86::VFNMADDSSr213r:
21003 case X86::VFNMSUBPDr213r:
21004 case X86::VFNMSUBPSr213r:
21005 case X86::VFNMSUBSDr213r:
21006 case X86::VFNMSUBSSr213r:
21007 case X86::VFMADDSUBPDr213r:
21008 case X86::VFMADDSUBPSr213r:
21009 case X86::VFMSUBADDPDr213r:
21010 case X86::VFMSUBADDPSr213r:
21011 case X86::VFMADDPDr213rY:
21012 case X86::VFMADDPSr213rY:
21013 case X86::VFMSUBPDr213rY:
21014 case X86::VFMSUBPSr213rY:
21015 case X86::VFNMADDPDr213rY:
21016 case X86::VFNMADDPSr213rY:
21017 case X86::VFNMSUBPDr213rY:
21018 case X86::VFNMSUBPSr213rY:
21019 case X86::VFMADDSUBPDr213rY:
21020 case X86::VFMADDSUBPSr213rY:
21021 case X86::VFMSUBADDPDr213rY:
21022 case X86::VFMSUBADDPSr213rY:
21023 return emitFMA3Instr(MI, BB);
21027 //===----------------------------------------------------------------------===//
21028 // X86 Optimization Hooks
21029 //===----------------------------------------------------------------------===//
21031 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21034 const SelectionDAG &DAG,
21035 unsigned Depth) const {
21036 unsigned BitWidth = KnownZero.getBitWidth();
21037 unsigned Opc = Op.getOpcode();
21038 assert((Opc >= ISD::BUILTIN_OP_END ||
21039 Opc == ISD::INTRINSIC_WO_CHAIN ||
21040 Opc == ISD::INTRINSIC_W_CHAIN ||
21041 Opc == ISD::INTRINSIC_VOID) &&
21042 "Should use MaskedValueIsZero if you don't know whether Op"
21043 " is a target node!");
21045 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21059 // These nodes' second result is a boolean.
21060 if (Op.getResNo() == 0)
21063 case X86ISD::SETCC:
21064 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21066 case ISD::INTRINSIC_WO_CHAIN: {
21067 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21068 unsigned NumLoBits = 0;
21071 case Intrinsic::x86_sse_movmsk_ps:
21072 case Intrinsic::x86_avx_movmsk_ps_256:
21073 case Intrinsic::x86_sse2_movmsk_pd:
21074 case Intrinsic::x86_avx_movmsk_pd_256:
21075 case Intrinsic::x86_mmx_pmovmskb:
21076 case Intrinsic::x86_sse2_pmovmskb_128:
21077 case Intrinsic::x86_avx2_pmovmskb: {
21078 // High bits of movmskp{s|d}, pmovmskb are known zero.
21080 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21081 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21082 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21083 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21084 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21085 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21086 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21087 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21089 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21098 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21100 const SelectionDAG &,
21101 unsigned Depth) const {
21102 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21103 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21104 return Op.getValueType().getScalarType().getSizeInBits();
21110 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21111 /// node is a GlobalAddress + offset.
21112 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21113 const GlobalValue* &GA,
21114 int64_t &Offset) const {
21115 if (N->getOpcode() == X86ISD::Wrapper) {
21116 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21117 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21118 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21122 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21125 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21126 /// same as extracting the high 128-bit part of 256-bit vector and then
21127 /// inserting the result into the low part of a new 256-bit vector
21128 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21129 EVT VT = SVOp->getValueType(0);
21130 unsigned NumElems = VT.getVectorNumElements();
21132 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21133 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21134 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21135 SVOp->getMaskElt(j) >= 0)
21141 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21142 /// same as extracting the low 128-bit part of 256-bit vector and then
21143 /// inserting the result into the high part of a new 256-bit vector
21144 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21145 EVT VT = SVOp->getValueType(0);
21146 unsigned NumElems = VT.getVectorNumElements();
21148 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21149 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21150 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21151 SVOp->getMaskElt(j) >= 0)
21157 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21158 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21159 TargetLowering::DAGCombinerInfo &DCI,
21160 const X86Subtarget* Subtarget) {
21162 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21163 SDValue V1 = SVOp->getOperand(0);
21164 SDValue V2 = SVOp->getOperand(1);
21165 EVT VT = SVOp->getValueType(0);
21166 unsigned NumElems = VT.getVectorNumElements();
21168 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21169 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21173 // V UNDEF BUILD_VECTOR UNDEF
21175 // CONCAT_VECTOR CONCAT_VECTOR
21178 // RESULT: V + zero extended
21180 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21181 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21182 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21185 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21188 // To match the shuffle mask, the first half of the mask should
21189 // be exactly the first vector, and all the rest a splat with the
21190 // first element of the second one.
21191 for (unsigned i = 0; i != NumElems/2; ++i)
21192 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21193 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21196 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21197 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21198 if (Ld->hasNUsesOfValue(1, 0)) {
21199 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21200 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21202 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21204 Ld->getPointerInfo(),
21205 Ld->getAlignment(),
21206 false/*isVolatile*/, true/*ReadMem*/,
21207 false/*WriteMem*/);
21209 // Make sure the newly-created LOAD is in the same position as Ld in
21210 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21211 // and update uses of Ld's output chain to use the TokenFactor.
21212 if (Ld->hasAnyUseOfValue(1)) {
21213 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21214 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21215 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21216 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21217 SDValue(ResNode.getNode(), 1));
21220 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21224 // Emit a zeroed vector and insert the desired subvector on its
21226 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21227 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21228 return DCI.CombineTo(N, InsV);
21231 //===--------------------------------------------------------------------===//
21232 // Combine some shuffles into subvector extracts and inserts:
21235 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21236 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21237 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21238 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21239 return DCI.CombineTo(N, InsV);
21242 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21243 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21244 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21245 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21246 return DCI.CombineTo(N, InsV);
21252 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21255 /// This is the leaf of the recursive combinine below. When we have found some
21256 /// chain of single-use x86 shuffle instructions and accumulated the combined
21257 /// shuffle mask represented by them, this will try to pattern match that mask
21258 /// into either a single instruction if there is a special purpose instruction
21259 /// for this operation, or into a PSHUFB instruction which is a fully general
21260 /// instruction but should only be used to replace chains over a certain depth.
21261 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21262 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21263 TargetLowering::DAGCombinerInfo &DCI,
21264 const X86Subtarget *Subtarget) {
21265 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21267 // Find the operand that enters the chain. Note that multiple uses are OK
21268 // here, we're not going to remove the operand we find.
21269 SDValue Input = Op.getOperand(0);
21270 while (Input.getOpcode() == ISD::BITCAST)
21271 Input = Input.getOperand(0);
21273 MVT VT = Input.getSimpleValueType();
21274 MVT RootVT = Root.getSimpleValueType();
21277 // Just remove no-op shuffle masks.
21278 if (Mask.size() == 1) {
21279 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21284 // Use the float domain if the operand type is a floating point type.
21285 bool FloatDomain = VT.isFloatingPoint();
21287 // For floating point shuffles, we don't have free copies in the shuffle
21288 // instructions or the ability to load as part of the instruction, so
21289 // canonicalize their shuffles to UNPCK or MOV variants.
21291 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21292 // vectors because it can have a load folded into it that UNPCK cannot. This
21293 // doesn't preclude something switching to the shorter encoding post-RA.
21295 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21296 bool Lo = Mask.equals(0, 0);
21299 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21300 // is no slower than UNPCKLPD but has the option to fold the input operand
21301 // into even an unaligned memory load.
21302 if (Lo && Subtarget->hasSSE3()) {
21303 Shuffle = X86ISD::MOVDDUP;
21304 ShuffleVT = MVT::v2f64;
21306 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21307 // than the UNPCK variants.
21308 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21309 ShuffleVT = MVT::v4f32;
21311 if (Depth == 1 && Root->getOpcode() == Shuffle)
21312 return false; // Nothing to do!
21313 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21314 DCI.AddToWorklist(Op.getNode());
21315 if (Shuffle == X86ISD::MOVDDUP)
21316 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21318 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21319 DCI.AddToWorklist(Op.getNode());
21320 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21324 if (Subtarget->hasSSE3() &&
21325 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21326 bool Lo = Mask.equals(0, 0, 2, 2);
21327 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21328 MVT ShuffleVT = MVT::v4f32;
21329 if (Depth == 1 && Root->getOpcode() == Shuffle)
21330 return false; // Nothing to do!
21331 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21332 DCI.AddToWorklist(Op.getNode());
21333 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21334 DCI.AddToWorklist(Op.getNode());
21335 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21339 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21340 bool Lo = Mask.equals(0, 0, 1, 1);
21341 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21342 MVT ShuffleVT = MVT::v4f32;
21343 if (Depth == 1 && Root->getOpcode() == Shuffle)
21344 return false; // Nothing to do!
21345 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21346 DCI.AddToWorklist(Op.getNode());
21347 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21348 DCI.AddToWorklist(Op.getNode());
21349 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21355 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21356 // variants as none of these have single-instruction variants that are
21357 // superior to the UNPCK formulation.
21358 if (!FloatDomain &&
21359 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21360 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21361 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21362 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21364 bool Lo = Mask[0] == 0;
21365 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21366 if (Depth == 1 && Root->getOpcode() == Shuffle)
21367 return false; // Nothing to do!
21369 switch (Mask.size()) {
21371 ShuffleVT = MVT::v8i16;
21374 ShuffleVT = MVT::v16i8;
21377 llvm_unreachable("Impossible mask size!");
21379 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21380 DCI.AddToWorklist(Op.getNode());
21381 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21382 DCI.AddToWorklist(Op.getNode());
21383 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21388 // Don't try to re-form single instruction chains under any circumstances now
21389 // that we've done encoding canonicalization for them.
21393 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21394 // can replace them with a single PSHUFB instruction profitably. Intel's
21395 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21396 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21397 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21398 SmallVector<SDValue, 16> PSHUFBMask;
21399 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21400 int Ratio = 16 / Mask.size();
21401 for (unsigned i = 0; i < 16; ++i) {
21402 if (Mask[i / Ratio] == SM_SentinelUndef) {
21403 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21406 int M = Mask[i / Ratio] != SM_SentinelZero
21407 ? Ratio * Mask[i / Ratio] + i % Ratio
21409 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21411 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21412 DCI.AddToWorklist(Op.getNode());
21413 SDValue PSHUFBMaskOp =
21414 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21415 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21416 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21417 DCI.AddToWorklist(Op.getNode());
21418 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21423 // Failed to find any combines.
21427 /// \brief Fully generic combining of x86 shuffle instructions.
21429 /// This should be the last combine run over the x86 shuffle instructions. Once
21430 /// they have been fully optimized, this will recursively consider all chains
21431 /// of single-use shuffle instructions, build a generic model of the cumulative
21432 /// shuffle operation, and check for simpler instructions which implement this
21433 /// operation. We use this primarily for two purposes:
21435 /// 1) Collapse generic shuffles to specialized single instructions when
21436 /// equivalent. In most cases, this is just an encoding size win, but
21437 /// sometimes we will collapse multiple generic shuffles into a single
21438 /// special-purpose shuffle.
21439 /// 2) Look for sequences of shuffle instructions with 3 or more total
21440 /// instructions, and replace them with the slightly more expensive SSSE3
21441 /// PSHUFB instruction if available. We do this as the last combining step
21442 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21443 /// a suitable short sequence of other instructions. The PHUFB will either
21444 /// use a register or have to read from memory and so is slightly (but only
21445 /// slightly) more expensive than the other shuffle instructions.
21447 /// Because this is inherently a quadratic operation (for each shuffle in
21448 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21449 /// This should never be an issue in practice as the shuffle lowering doesn't
21450 /// produce sequences of more than 8 instructions.
21452 /// FIXME: We will currently miss some cases where the redundant shuffling
21453 /// would simplify under the threshold for PSHUFB formation because of
21454 /// combine-ordering. To fix this, we should do the redundant instruction
21455 /// combining in this recursive walk.
21456 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21457 ArrayRef<int> RootMask,
21458 int Depth, bool HasPSHUFB,
21460 TargetLowering::DAGCombinerInfo &DCI,
21461 const X86Subtarget *Subtarget) {
21462 // Bound the depth of our recursive combine because this is ultimately
21463 // quadratic in nature.
21467 // Directly rip through bitcasts to find the underlying operand.
21468 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21469 Op = Op.getOperand(0);
21471 MVT VT = Op.getSimpleValueType();
21472 if (!VT.isVector())
21473 return false; // Bail if we hit a non-vector.
21474 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21475 // version should be added.
21476 if (VT.getSizeInBits() != 128)
21479 assert(Root.getSimpleValueType().isVector() &&
21480 "Shuffles operate on vector types!");
21481 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21482 "Can only combine shuffles of the same vector register size.");
21484 if (!isTargetShuffle(Op.getOpcode()))
21486 SmallVector<int, 16> OpMask;
21488 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21489 // We only can combine unary shuffles which we can decode the mask for.
21490 if (!HaveMask || !IsUnary)
21493 assert(VT.getVectorNumElements() == OpMask.size() &&
21494 "Different mask size from vector size!");
21495 assert(((RootMask.size() > OpMask.size() &&
21496 RootMask.size() % OpMask.size() == 0) ||
21497 (OpMask.size() > RootMask.size() &&
21498 OpMask.size() % RootMask.size() == 0) ||
21499 OpMask.size() == RootMask.size()) &&
21500 "The smaller number of elements must divide the larger.");
21501 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21502 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21503 assert(((RootRatio == 1 && OpRatio == 1) ||
21504 (RootRatio == 1) != (OpRatio == 1)) &&
21505 "Must not have a ratio for both incoming and op masks!");
21507 SmallVector<int, 16> Mask;
21508 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21510 // Merge this shuffle operation's mask into our accumulated mask. Note that
21511 // this shuffle's mask will be the first applied to the input, followed by the
21512 // root mask to get us all the way to the root value arrangement. The reason
21513 // for this order is that we are recursing up the operation chain.
21514 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21515 int RootIdx = i / RootRatio;
21516 if (RootMask[RootIdx] < 0) {
21517 // This is a zero or undef lane, we're done.
21518 Mask.push_back(RootMask[RootIdx]);
21522 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21523 int OpIdx = RootMaskedIdx / OpRatio;
21524 if (OpMask[OpIdx] < 0) {
21525 // The incoming lanes are zero or undef, it doesn't matter which ones we
21527 Mask.push_back(OpMask[OpIdx]);
21531 // Ok, we have non-zero lanes, map them through.
21532 Mask.push_back(OpMask[OpIdx] * OpRatio +
21533 RootMaskedIdx % OpRatio);
21536 // See if we can recurse into the operand to combine more things.
21537 switch (Op.getOpcode()) {
21538 case X86ISD::PSHUFB:
21540 case X86ISD::PSHUFD:
21541 case X86ISD::PSHUFHW:
21542 case X86ISD::PSHUFLW:
21543 if (Op.getOperand(0).hasOneUse() &&
21544 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21545 HasPSHUFB, DAG, DCI, Subtarget))
21549 case X86ISD::UNPCKL:
21550 case X86ISD::UNPCKH:
21551 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21552 // We can't check for single use, we have to check that this shuffle is the only user.
21553 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21554 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21555 HasPSHUFB, DAG, DCI, Subtarget))
21560 // Minor canonicalization of the accumulated shuffle mask to make it easier
21561 // to match below. All this does is detect masks with squential pairs of
21562 // elements, and shrink them to the half-width mask. It does this in a loop
21563 // so it will reduce the size of the mask to the minimal width mask which
21564 // performs an equivalent shuffle.
21565 SmallVector<int, 16> WidenedMask;
21566 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21567 Mask = std::move(WidenedMask);
21568 WidenedMask.clear();
21571 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21575 /// \brief Get the PSHUF-style mask from PSHUF node.
21577 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21578 /// PSHUF-style masks that can be reused with such instructions.
21579 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21580 SmallVector<int, 4> Mask;
21582 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21586 switch (N.getOpcode()) {
21587 case X86ISD::PSHUFD:
21589 case X86ISD::PSHUFLW:
21592 case X86ISD::PSHUFHW:
21593 Mask.erase(Mask.begin(), Mask.begin() + 4);
21594 for (int &M : Mask)
21598 llvm_unreachable("No valid shuffle instruction found!");
21602 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21604 /// We walk up the chain and look for a combinable shuffle, skipping over
21605 /// shuffles that we could hoist this shuffle's transformation past without
21606 /// altering anything.
21608 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21610 TargetLowering::DAGCombinerInfo &DCI) {
21611 assert(N.getOpcode() == X86ISD::PSHUFD &&
21612 "Called with something other than an x86 128-bit half shuffle!");
21615 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21616 // of the shuffles in the chain so that we can form a fresh chain to replace
21618 SmallVector<SDValue, 8> Chain;
21619 SDValue V = N.getOperand(0);
21620 for (; V.hasOneUse(); V = V.getOperand(0)) {
21621 switch (V.getOpcode()) {
21623 return SDValue(); // Nothing combined!
21626 // Skip bitcasts as we always know the type for the target specific
21630 case X86ISD::PSHUFD:
21631 // Found another dword shuffle.
21634 case X86ISD::PSHUFLW:
21635 // Check that the low words (being shuffled) are the identity in the
21636 // dword shuffle, and the high words are self-contained.
21637 if (Mask[0] != 0 || Mask[1] != 1 ||
21638 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21641 Chain.push_back(V);
21644 case X86ISD::PSHUFHW:
21645 // Check that the high words (being shuffled) are the identity in the
21646 // dword shuffle, and the low words are self-contained.
21647 if (Mask[2] != 2 || Mask[3] != 3 ||
21648 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21651 Chain.push_back(V);
21654 case X86ISD::UNPCKL:
21655 case X86ISD::UNPCKH:
21656 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21657 // shuffle into a preceding word shuffle.
21658 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21661 // Search for a half-shuffle which we can combine with.
21662 unsigned CombineOp =
21663 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21664 if (V.getOperand(0) != V.getOperand(1) ||
21665 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21667 Chain.push_back(V);
21668 V = V.getOperand(0);
21670 switch (V.getOpcode()) {
21672 return SDValue(); // Nothing to combine.
21674 case X86ISD::PSHUFLW:
21675 case X86ISD::PSHUFHW:
21676 if (V.getOpcode() == CombineOp)
21679 Chain.push_back(V);
21683 V = V.getOperand(0);
21687 } while (V.hasOneUse());
21690 // Break out of the loop if we break out of the switch.
21694 if (!V.hasOneUse())
21695 // We fell out of the loop without finding a viable combining instruction.
21698 // Merge this node's mask and our incoming mask.
21699 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21700 for (int &M : Mask)
21702 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21703 getV4X86ShuffleImm8ForMask(Mask, DAG));
21705 // Rebuild the chain around this new shuffle.
21706 while (!Chain.empty()) {
21707 SDValue W = Chain.pop_back_val();
21709 if (V.getValueType() != W.getOperand(0).getValueType())
21710 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21712 switch (W.getOpcode()) {
21714 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21716 case X86ISD::UNPCKL:
21717 case X86ISD::UNPCKH:
21718 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21721 case X86ISD::PSHUFD:
21722 case X86ISD::PSHUFLW:
21723 case X86ISD::PSHUFHW:
21724 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21728 if (V.getValueType() != N.getValueType())
21729 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21731 // Return the new chain to replace N.
21735 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21737 /// We walk up the chain, skipping shuffles of the other half and looking
21738 /// through shuffles which switch halves trying to find a shuffle of the same
21739 /// pair of dwords.
21740 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21742 TargetLowering::DAGCombinerInfo &DCI) {
21744 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21745 "Called with something other than an x86 128-bit half shuffle!");
21747 unsigned CombineOpcode = N.getOpcode();
21749 // Walk up a single-use chain looking for a combinable shuffle.
21750 SDValue V = N.getOperand(0);
21751 for (; V.hasOneUse(); V = V.getOperand(0)) {
21752 switch (V.getOpcode()) {
21754 return false; // Nothing combined!
21757 // Skip bitcasts as we always know the type for the target specific
21761 case X86ISD::PSHUFLW:
21762 case X86ISD::PSHUFHW:
21763 if (V.getOpcode() == CombineOpcode)
21766 // Other-half shuffles are no-ops.
21769 // Break out of the loop if we break out of the switch.
21773 if (!V.hasOneUse())
21774 // We fell out of the loop without finding a viable combining instruction.
21777 // Combine away the bottom node as its shuffle will be accumulated into
21778 // a preceding shuffle.
21779 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21781 // Record the old value.
21784 // Merge this node's mask and our incoming mask (adjusted to account for all
21785 // the pshufd instructions encountered).
21786 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21787 for (int &M : Mask)
21789 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21790 getV4X86ShuffleImm8ForMask(Mask, DAG));
21792 // Check that the shuffles didn't cancel each other out. If not, we need to
21793 // combine to the new one.
21795 // Replace the combinable shuffle with the combined one, updating all users
21796 // so that we re-evaluate the chain here.
21797 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21802 /// \brief Try to combine x86 target specific shuffles.
21803 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21804 TargetLowering::DAGCombinerInfo &DCI,
21805 const X86Subtarget *Subtarget) {
21807 MVT VT = N.getSimpleValueType();
21808 SmallVector<int, 4> Mask;
21810 switch (N.getOpcode()) {
21811 case X86ISD::PSHUFD:
21812 case X86ISD::PSHUFLW:
21813 case X86ISD::PSHUFHW:
21814 Mask = getPSHUFShuffleMask(N);
21815 assert(Mask.size() == 4);
21821 // Nuke no-op shuffles that show up after combining.
21822 if (isNoopShuffleMask(Mask))
21823 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21825 // Look for simplifications involving one or two shuffle instructions.
21826 SDValue V = N.getOperand(0);
21827 switch (N.getOpcode()) {
21830 case X86ISD::PSHUFLW:
21831 case X86ISD::PSHUFHW:
21832 assert(VT == MVT::v8i16);
21835 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21836 return SDValue(); // We combined away this shuffle, so we're done.
21838 // See if this reduces to a PSHUFD which is no more expensive and can
21839 // combine with more operations. Note that it has to at least flip the
21840 // dwords as otherwise it would have been removed as a no-op.
21841 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21842 int DMask[] = {0, 1, 2, 3};
21843 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21844 DMask[DOffset + 0] = DOffset + 1;
21845 DMask[DOffset + 1] = DOffset + 0;
21846 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21847 DCI.AddToWorklist(V.getNode());
21848 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21849 getV4X86ShuffleImm8ForMask(DMask, DAG));
21850 DCI.AddToWorklist(V.getNode());
21851 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21854 // Look for shuffle patterns which can be implemented as a single unpack.
21855 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21856 // only works when we have a PSHUFD followed by two half-shuffles.
21857 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21858 (V.getOpcode() == X86ISD::PSHUFLW ||
21859 V.getOpcode() == X86ISD::PSHUFHW) &&
21860 V.getOpcode() != N.getOpcode() &&
21862 SDValue D = V.getOperand(0);
21863 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21864 D = D.getOperand(0);
21865 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21866 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21867 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21868 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21869 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21871 for (int i = 0; i < 4; ++i) {
21872 WordMask[i + NOffset] = Mask[i] + NOffset;
21873 WordMask[i + VOffset] = VMask[i] + VOffset;
21875 // Map the word mask through the DWord mask.
21877 for (int i = 0; i < 8; ++i)
21878 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21879 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21880 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21881 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21882 std::begin(UnpackLoMask)) ||
21883 std::equal(std::begin(MappedMask), std::end(MappedMask),
21884 std::begin(UnpackHiMask))) {
21885 // We can replace all three shuffles with an unpack.
21886 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21887 DCI.AddToWorklist(V.getNode());
21888 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21890 DL, MVT::v8i16, V, V);
21897 case X86ISD::PSHUFD:
21898 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21907 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21909 /// We combine this directly on the abstract vector shuffle nodes so it is
21910 /// easier to generically match. We also insert dummy vector shuffle nodes for
21911 /// the operands which explicitly discard the lanes which are unused by this
21912 /// operation to try to flow through the rest of the combiner the fact that
21913 /// they're unused.
21914 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21916 EVT VT = N->getValueType(0);
21918 // We only handle target-independent shuffles.
21919 // FIXME: It would be easy and harmless to use the target shuffle mask
21920 // extraction tool to support more.
21921 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21924 auto *SVN = cast<ShuffleVectorSDNode>(N);
21925 ArrayRef<int> Mask = SVN->getMask();
21926 SDValue V1 = N->getOperand(0);
21927 SDValue V2 = N->getOperand(1);
21929 // We require the first shuffle operand to be the SUB node, and the second to
21930 // be the ADD node.
21931 // FIXME: We should support the commuted patterns.
21932 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21935 // If there are other uses of these operations we can't fold them.
21936 if (!V1->hasOneUse() || !V2->hasOneUse())
21939 // Ensure that both operations have the same operands. Note that we can
21940 // commute the FADD operands.
21941 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21942 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21943 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21946 // We're looking for blends between FADD and FSUB nodes. We insist on these
21947 // nodes being lined up in a specific expected pattern.
21948 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21949 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21950 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21953 // Only specific types are legal at this point, assert so we notice if and
21954 // when these change.
21955 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21956 VT == MVT::v4f64) &&
21957 "Unknown vector type encountered!");
21959 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21962 /// PerformShuffleCombine - Performs several different shuffle combines.
21963 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21964 TargetLowering::DAGCombinerInfo &DCI,
21965 const X86Subtarget *Subtarget) {
21967 SDValue N0 = N->getOperand(0);
21968 SDValue N1 = N->getOperand(1);
21969 EVT VT = N->getValueType(0);
21971 // Don't create instructions with illegal types after legalize types has run.
21972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21973 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21976 // If we have legalized the vector types, look for blends of FADD and FSUB
21977 // nodes that we can fuse into an ADDSUB node.
21978 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21979 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21982 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21983 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21984 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21985 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21987 // During Type Legalization, when promoting illegal vector types,
21988 // the backend might introduce new shuffle dag nodes and bitcasts.
21990 // This code performs the following transformation:
21991 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21992 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21994 // We do this only if both the bitcast and the BINOP dag nodes have
21995 // one use. Also, perform this transformation only if the new binary
21996 // operation is legal. This is to avoid introducing dag nodes that
21997 // potentially need to be further expanded (or custom lowered) into a
21998 // less optimal sequence of dag nodes.
21999 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22000 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22001 N0.getOpcode() == ISD::BITCAST) {
22002 SDValue BC0 = N0.getOperand(0);
22003 EVT SVT = BC0.getValueType();
22004 unsigned Opcode = BC0.getOpcode();
22005 unsigned NumElts = VT.getVectorNumElements();
22007 if (BC0.hasOneUse() && SVT.isVector() &&
22008 SVT.getVectorNumElements() * 2 == NumElts &&
22009 TLI.isOperationLegal(Opcode, VT)) {
22010 bool CanFold = false;
22022 unsigned SVTNumElts = SVT.getVectorNumElements();
22023 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22024 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22025 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22026 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22027 CanFold = SVOp->getMaskElt(i) < 0;
22030 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22031 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22032 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22033 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22038 // Only handle 128 wide vector from here on.
22039 if (!VT.is128BitVector())
22042 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22043 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22044 // consecutive, non-overlapping, and in the right order.
22045 SmallVector<SDValue, 16> Elts;
22046 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22047 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22049 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22053 if (isTargetShuffle(N->getOpcode())) {
22055 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22056 if (Shuffle.getNode())
22059 // Try recursively combining arbitrary sequences of x86 shuffle
22060 // instructions into higher-order shuffles. We do this after combining
22061 // specific PSHUF instruction sequences into their minimal form so that we
22062 // can evaluate how many specialized shuffle instructions are involved in
22063 // a particular chain.
22064 SmallVector<int, 1> NonceMask; // Just a placeholder.
22065 NonceMask.push_back(0);
22066 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22067 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22069 return SDValue(); // This routine will use CombineTo to replace N.
22075 /// PerformTruncateCombine - Converts truncate operation to
22076 /// a sequence of vector shuffle operations.
22077 /// It is possible when we truncate 256-bit vector to 128-bit vector
22078 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22079 TargetLowering::DAGCombinerInfo &DCI,
22080 const X86Subtarget *Subtarget) {
22084 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22085 /// specific shuffle of a load can be folded into a single element load.
22086 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22087 /// shuffles have been custom lowered so we need to handle those here.
22088 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22089 TargetLowering::DAGCombinerInfo &DCI) {
22090 if (DCI.isBeforeLegalizeOps())
22093 SDValue InVec = N->getOperand(0);
22094 SDValue EltNo = N->getOperand(1);
22096 if (!isa<ConstantSDNode>(EltNo))
22099 EVT OriginalVT = InVec.getValueType();
22101 if (InVec.getOpcode() == ISD::BITCAST) {
22102 // Don't duplicate a load with other uses.
22103 if (!InVec.hasOneUse())
22105 EVT BCVT = InVec.getOperand(0).getValueType();
22106 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22108 InVec = InVec.getOperand(0);
22111 EVT CurrentVT = InVec.getValueType();
22113 if (!isTargetShuffle(InVec.getOpcode()))
22116 // Don't duplicate a load with other uses.
22117 if (!InVec.hasOneUse())
22120 SmallVector<int, 16> ShuffleMask;
22122 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22123 ShuffleMask, UnaryShuffle))
22126 // Select the input vector, guarding against out of range extract vector.
22127 unsigned NumElems = CurrentVT.getVectorNumElements();
22128 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22129 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22130 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22131 : InVec.getOperand(1);
22133 // If inputs to shuffle are the same for both ops, then allow 2 uses
22134 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22136 if (LdNode.getOpcode() == ISD::BITCAST) {
22137 // Don't duplicate a load with other uses.
22138 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22141 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22142 LdNode = LdNode.getOperand(0);
22145 if (!ISD::isNormalLoad(LdNode.getNode()))
22148 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22150 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22153 EVT EltVT = N->getValueType(0);
22154 // If there's a bitcast before the shuffle, check if the load type and
22155 // alignment is valid.
22156 unsigned Align = LN0->getAlignment();
22157 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22158 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22159 EltVT.getTypeForEVT(*DAG.getContext()));
22161 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22164 // All checks match so transform back to vector_shuffle so that DAG combiner
22165 // can finish the job
22168 // Create shuffle node taking into account the case that its a unary shuffle
22169 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22170 : InVec.getOperand(1);
22171 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22172 InVec.getOperand(0), Shuffle,
22174 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22175 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22179 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22180 /// generation and convert it from being a bunch of shuffles and extracts
22181 /// to a simple store and scalar loads to extract the elements.
22182 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22183 TargetLowering::DAGCombinerInfo &DCI) {
22184 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22185 if (NewOp.getNode())
22188 SDValue InputVector = N->getOperand(0);
22190 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22191 // from mmx to v2i32 has a single usage.
22192 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22193 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22194 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22195 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22196 N->getValueType(0),
22197 InputVector.getNode()->getOperand(0));
22199 // Only operate on vectors of 4 elements, where the alternative shuffling
22200 // gets to be more expensive.
22201 if (InputVector.getValueType() != MVT::v4i32)
22204 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22205 // single use which is a sign-extend or zero-extend, and all elements are
22207 SmallVector<SDNode *, 4> Uses;
22208 unsigned ExtractedElements = 0;
22209 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22210 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22211 if (UI.getUse().getResNo() != InputVector.getResNo())
22214 SDNode *Extract = *UI;
22215 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22218 if (Extract->getValueType(0) != MVT::i32)
22220 if (!Extract->hasOneUse())
22222 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22223 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22225 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22228 // Record which element was extracted.
22229 ExtractedElements |=
22230 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22232 Uses.push_back(Extract);
22235 // If not all the elements were used, this may not be worthwhile.
22236 if (ExtractedElements != 15)
22239 // Ok, we've now decided to do the transformation.
22240 SDLoc dl(InputVector);
22242 // Store the value to a temporary stack slot.
22243 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22244 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22245 MachinePointerInfo(), false, false, 0);
22247 // Replace each use (extract) with a load of the appropriate element.
22248 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22249 UE = Uses.end(); UI != UE; ++UI) {
22250 SDNode *Extract = *UI;
22252 // cOMpute the element's address.
22253 SDValue Idx = Extract->getOperand(1);
22255 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22256 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22257 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22258 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22260 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22261 StackPtr, OffsetVal);
22263 // Load the scalar.
22264 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22265 ScalarAddr, MachinePointerInfo(),
22266 false, false, false, 0);
22268 // Replace the exact with the load.
22269 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22272 // The replacement was made in place; don't return anything.
22276 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22277 static std::pair<unsigned, bool>
22278 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22279 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22280 if (!VT.isVector())
22281 return std::make_pair(0, false);
22283 bool NeedSplit = false;
22284 switch (VT.getSimpleVT().SimpleTy) {
22285 default: return std::make_pair(0, false);
22289 if (!Subtarget->hasAVX2())
22291 if (!Subtarget->hasAVX())
22292 return std::make_pair(0, false);
22297 if (!Subtarget->hasSSE2())
22298 return std::make_pair(0, false);
22301 // SSE2 has only a small subset of the operations.
22302 bool hasUnsigned = Subtarget->hasSSE41() ||
22303 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22304 bool hasSigned = Subtarget->hasSSE41() ||
22305 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22307 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22310 // Check for x CC y ? x : y.
22311 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22312 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22317 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22320 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22323 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22326 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22328 // Check for x CC y ? y : x -- a min/max with reversed arms.
22329 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22330 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22335 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22338 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22341 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22344 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22348 return std::make_pair(Opc, NeedSplit);
22352 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22353 const X86Subtarget *Subtarget) {
22355 SDValue Cond = N->getOperand(0);
22356 SDValue LHS = N->getOperand(1);
22357 SDValue RHS = N->getOperand(2);
22359 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22360 SDValue CondSrc = Cond->getOperand(0);
22361 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22362 Cond = CondSrc->getOperand(0);
22365 MVT VT = N->getSimpleValueType(0);
22366 MVT EltVT = VT.getVectorElementType();
22367 unsigned NumElems = VT.getVectorNumElements();
22368 // There is no blend with immediate in AVX-512.
22369 if (VT.is512BitVector())
22372 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22374 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22377 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22380 // A vselect where all conditions and data are constants can be optimized into
22381 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22382 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22383 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22386 unsigned MaskValue = 0;
22387 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22390 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22391 for (unsigned i = 0; i < NumElems; ++i) {
22392 // Be sure we emit undef where we can.
22393 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22394 ShuffleMask[i] = -1;
22396 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22399 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22402 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22404 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22405 TargetLowering::DAGCombinerInfo &DCI,
22406 const X86Subtarget *Subtarget) {
22408 SDValue Cond = N->getOperand(0);
22409 // Get the LHS/RHS of the select.
22410 SDValue LHS = N->getOperand(1);
22411 SDValue RHS = N->getOperand(2);
22412 EVT VT = LHS.getValueType();
22413 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22415 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22416 // instructions match the semantics of the common C idiom x<y?x:y but not
22417 // x<=y?x:y, because of how they handle negative zero (which can be
22418 // ignored in unsafe-math mode).
22419 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22420 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22421 (Subtarget->hasSSE2() ||
22422 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22423 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22425 unsigned Opcode = 0;
22426 // Check for x CC y ? x : y.
22427 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22428 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22432 // Converting this to a min would handle NaNs incorrectly, and swapping
22433 // the operands would cause it to handle comparisons between positive
22434 // and negative zero incorrectly.
22435 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22436 if (!DAG.getTarget().Options.UnsafeFPMath &&
22437 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22439 std::swap(LHS, RHS);
22441 Opcode = X86ISD::FMIN;
22444 // Converting this to a min would handle comparisons between positive
22445 // and negative zero incorrectly.
22446 if (!DAG.getTarget().Options.UnsafeFPMath &&
22447 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22449 Opcode = X86ISD::FMIN;
22452 // Converting this to a min would handle both negative zeros and NaNs
22453 // incorrectly, but we can swap the operands to fix both.
22454 std::swap(LHS, RHS);
22458 Opcode = X86ISD::FMIN;
22462 // Converting this to a max would handle comparisons between positive
22463 // and negative zero incorrectly.
22464 if (!DAG.getTarget().Options.UnsafeFPMath &&
22465 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22467 Opcode = X86ISD::FMAX;
22470 // Converting this to a max would handle NaNs incorrectly, and swapping
22471 // the operands would cause it to handle comparisons between positive
22472 // and negative zero incorrectly.
22473 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22474 if (!DAG.getTarget().Options.UnsafeFPMath &&
22475 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22477 std::swap(LHS, RHS);
22479 Opcode = X86ISD::FMAX;
22482 // Converting this to a max would handle both negative zeros and NaNs
22483 // incorrectly, but we can swap the operands to fix both.
22484 std::swap(LHS, RHS);
22488 Opcode = X86ISD::FMAX;
22491 // Check for x CC y ? y : x -- a min/max with reversed arms.
22492 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22493 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22497 // Converting this to a min would handle comparisons between positive
22498 // and negative zero incorrectly, and swapping the operands would
22499 // cause it to handle NaNs incorrectly.
22500 if (!DAG.getTarget().Options.UnsafeFPMath &&
22501 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22502 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22504 std::swap(LHS, RHS);
22506 Opcode = X86ISD::FMIN;
22509 // Converting this to a min would handle NaNs incorrectly.
22510 if (!DAG.getTarget().Options.UnsafeFPMath &&
22511 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22513 Opcode = X86ISD::FMIN;
22516 // Converting this to a min would handle both negative zeros and NaNs
22517 // incorrectly, but we can swap the operands to fix both.
22518 std::swap(LHS, RHS);
22522 Opcode = X86ISD::FMIN;
22526 // Converting this to a max would handle NaNs incorrectly.
22527 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22529 Opcode = X86ISD::FMAX;
22532 // Converting this to a max would handle comparisons between positive
22533 // and negative zero incorrectly, and swapping the operands would
22534 // cause it to handle NaNs incorrectly.
22535 if (!DAG.getTarget().Options.UnsafeFPMath &&
22536 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22537 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22539 std::swap(LHS, RHS);
22541 Opcode = X86ISD::FMAX;
22544 // Converting this to a max would handle both negative zeros and NaNs
22545 // incorrectly, but we can swap the operands to fix both.
22546 std::swap(LHS, RHS);
22550 Opcode = X86ISD::FMAX;
22556 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22559 EVT CondVT = Cond.getValueType();
22560 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22561 CondVT.getVectorElementType() == MVT::i1) {
22562 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22563 // lowering on KNL. In this case we convert it to
22564 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22565 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22566 // Since SKX these selects have a proper lowering.
22567 EVT OpVT = LHS.getValueType();
22568 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22569 (OpVT.getVectorElementType() == MVT::i8 ||
22570 OpVT.getVectorElementType() == MVT::i16) &&
22571 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22572 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22573 DCI.AddToWorklist(Cond.getNode());
22574 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22577 // If this is a select between two integer constants, try to do some
22579 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22580 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22581 // Don't do this for crazy integer types.
22582 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22583 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22584 // so that TrueC (the true value) is larger than FalseC.
22585 bool NeedsCondInvert = false;
22587 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22588 // Efficiently invertible.
22589 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22590 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22591 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22592 NeedsCondInvert = true;
22593 std::swap(TrueC, FalseC);
22596 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22597 if (FalseC->getAPIntValue() == 0 &&
22598 TrueC->getAPIntValue().isPowerOf2()) {
22599 if (NeedsCondInvert) // Invert the condition if needed.
22600 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22601 DAG.getConstant(1, Cond.getValueType()));
22603 // Zero extend the condition if needed.
22604 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22606 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22607 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22608 DAG.getConstant(ShAmt, MVT::i8));
22611 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22612 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22613 if (NeedsCondInvert) // Invert the condition if needed.
22614 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22615 DAG.getConstant(1, Cond.getValueType()));
22617 // Zero extend the condition if needed.
22618 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22619 FalseC->getValueType(0), Cond);
22620 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22621 SDValue(FalseC, 0));
22624 // Optimize cases that will turn into an LEA instruction. This requires
22625 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22626 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22627 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22628 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22630 bool isFastMultiplier = false;
22632 switch ((unsigned char)Diff) {
22634 case 1: // result = add base, cond
22635 case 2: // result = lea base( , cond*2)
22636 case 3: // result = lea base(cond, cond*2)
22637 case 4: // result = lea base( , cond*4)
22638 case 5: // result = lea base(cond, cond*4)
22639 case 8: // result = lea base( , cond*8)
22640 case 9: // result = lea base(cond, cond*8)
22641 isFastMultiplier = true;
22646 if (isFastMultiplier) {
22647 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22648 if (NeedsCondInvert) // Invert the condition if needed.
22649 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22650 DAG.getConstant(1, Cond.getValueType()));
22652 // Zero extend the condition if needed.
22653 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22655 // Scale the condition by the difference.
22657 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22658 DAG.getConstant(Diff, Cond.getValueType()));
22660 // Add the base if non-zero.
22661 if (FalseC->getAPIntValue() != 0)
22662 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22663 SDValue(FalseC, 0));
22670 // Canonicalize max and min:
22671 // (x > y) ? x : y -> (x >= y) ? x : y
22672 // (x < y) ? x : y -> (x <= y) ? x : y
22673 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22674 // the need for an extra compare
22675 // against zero. e.g.
22676 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22678 // testl %edi, %edi
22680 // cmovgl %edi, %eax
22684 // cmovsl %eax, %edi
22685 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22686 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22687 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22688 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22693 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22694 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22695 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22696 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22701 // Early exit check
22702 if (!TLI.isTypeLegal(VT))
22705 // Match VSELECTs into subs with unsigned saturation.
22706 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22707 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22708 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22709 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22710 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22712 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22713 // left side invert the predicate to simplify logic below.
22715 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22717 CC = ISD::getSetCCInverse(CC, true);
22718 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22722 if (Other.getNode() && Other->getNumOperands() == 2 &&
22723 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22724 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22725 SDValue CondRHS = Cond->getOperand(1);
22727 // Look for a general sub with unsigned saturation first.
22728 // x >= y ? x-y : 0 --> subus x, y
22729 // x > y ? x-y : 0 --> subus x, y
22730 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22731 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22732 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22734 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22735 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22736 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22737 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22738 // If the RHS is a constant we have to reverse the const
22739 // canonicalization.
22740 // x > C-1 ? x+-C : 0 --> subus x, C
22741 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22742 CondRHSConst->getAPIntValue() ==
22743 (-OpRHSConst->getAPIntValue() - 1))
22744 return DAG.getNode(
22745 X86ISD::SUBUS, DL, VT, OpLHS,
22746 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22748 // Another special case: If C was a sign bit, the sub has been
22749 // canonicalized into a xor.
22750 // FIXME: Would it be better to use computeKnownBits to determine
22751 // whether it's safe to decanonicalize the xor?
22752 // x s< 0 ? x^C : 0 --> subus x, C
22753 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22754 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22755 OpRHSConst->getAPIntValue().isSignBit())
22756 // Note that we have to rebuild the RHS constant here to ensure we
22757 // don't rely on particular values of undef lanes.
22758 return DAG.getNode(
22759 X86ISD::SUBUS, DL, VT, OpLHS,
22760 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22765 // Try to match a min/max vector operation.
22766 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22767 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22768 unsigned Opc = ret.first;
22769 bool NeedSplit = ret.second;
22771 if (Opc && NeedSplit) {
22772 unsigned NumElems = VT.getVectorNumElements();
22773 // Extract the LHS vectors
22774 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22775 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22777 // Extract the RHS vectors
22778 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22779 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22781 // Create min/max for each subvector
22782 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22783 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22785 // Merge the result
22786 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22788 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22791 // Simplify vector selection if condition value type matches vselect
22793 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22794 assert(Cond.getValueType().isVector() &&
22795 "vector select expects a vector selector!");
22797 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22798 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22800 // Try invert the condition if true value is not all 1s and false value
22802 if (!TValIsAllOnes && !FValIsAllZeros &&
22803 // Check if the selector will be produced by CMPP*/PCMP*
22804 Cond.getOpcode() == ISD::SETCC &&
22805 // Check if SETCC has already been promoted
22806 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22807 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22808 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22810 if (TValIsAllZeros || FValIsAllOnes) {
22811 SDValue CC = Cond.getOperand(2);
22812 ISD::CondCode NewCC =
22813 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22814 Cond.getOperand(0).getValueType().isInteger());
22815 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22816 std::swap(LHS, RHS);
22817 TValIsAllOnes = FValIsAllOnes;
22818 FValIsAllZeros = TValIsAllZeros;
22822 if (TValIsAllOnes || FValIsAllZeros) {
22825 if (TValIsAllOnes && FValIsAllZeros)
22827 else if (TValIsAllOnes)
22828 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22829 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22830 else if (FValIsAllZeros)
22831 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22832 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22834 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22838 // Try to fold this VSELECT into a MOVSS/MOVSD
22839 if (N->getOpcode() == ISD::VSELECT &&
22840 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22841 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22842 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22843 bool CanFold = false;
22844 unsigned NumElems = Cond.getNumOperands();
22848 if (isZero(Cond.getOperand(0))) {
22851 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22852 // fold (vselect <0,-1> -> (movsd A, B)
22853 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22854 CanFold = isAllOnes(Cond.getOperand(i));
22855 } else if (isAllOnes(Cond.getOperand(0))) {
22859 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22860 // fold (vselect <-1,0> -> (movsd B, A)
22861 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22862 CanFold = isZero(Cond.getOperand(i));
22866 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22867 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22868 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22871 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22872 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22873 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22874 // (v2i64 (bitcast B)))))
22876 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22877 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22878 // (v2f64 (bitcast B)))))
22880 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22881 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22882 // (v2i64 (bitcast A)))))
22884 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22885 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22886 // (v2f64 (bitcast A)))))
22888 CanFold = (isZero(Cond.getOperand(0)) &&
22889 isZero(Cond.getOperand(1)) &&
22890 isAllOnes(Cond.getOperand(2)) &&
22891 isAllOnes(Cond.getOperand(3)));
22893 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22894 isAllOnes(Cond.getOperand(1)) &&
22895 isZero(Cond.getOperand(2)) &&
22896 isZero(Cond.getOperand(3))) {
22898 std::swap(LHS, RHS);
22902 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22903 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22904 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22905 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22907 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22913 // If we know that this node is legal then we know that it is going to be
22914 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22915 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22916 // to simplify previous instructions.
22917 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22918 !DCI.isBeforeLegalize() &&
22919 // We explicitly check against v8i16 and v16i16 because, although
22920 // they're marked as Custom, they might only be legal when Cond is a
22921 // build_vector of constants. This will be taken care in a later
22923 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22924 VT != MVT::v8i16) &&
22925 // Don't optimize vector of constants. Those are handled by
22926 // the generic code and all the bits must be properly set for
22927 // the generic optimizer.
22928 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22929 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22931 // Don't optimize vector selects that map to mask-registers.
22935 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22936 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22938 APInt KnownZero, KnownOne;
22939 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22940 DCI.isBeforeLegalizeOps());
22941 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22942 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22944 // If we changed the computation somewhere in the DAG, this change
22945 // will affect all users of Cond.
22946 // Make sure it is fine and update all the nodes so that we do not
22947 // use the generic VSELECT anymore. Otherwise, we may perform
22948 // wrong optimizations as we messed up with the actual expectation
22949 // for the vector boolean values.
22950 if (Cond != TLO.Old) {
22951 // Check all uses of that condition operand to check whether it will be
22952 // consumed by non-BLEND instructions, which may depend on all bits are
22954 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22956 if (I->getOpcode() != ISD::VSELECT)
22957 // TODO: Add other opcodes eventually lowered into BLEND.
22960 // Update all the users of the condition, before committing the change,
22961 // so that the VSELECT optimizations that expect the correct vector
22962 // boolean value will not be triggered.
22963 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22965 DAG.ReplaceAllUsesOfValueWith(
22967 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22968 Cond, I->getOperand(1), I->getOperand(2)));
22969 DCI.CommitTargetLoweringOpt(TLO);
22972 // At this point, only Cond is changed. Change the condition
22973 // just for N to keep the opportunity to optimize all other
22974 // users their own way.
22975 DAG.ReplaceAllUsesOfValueWith(
22977 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22978 TLO.New, N->getOperand(1), N->getOperand(2)));
22983 // We should generate an X86ISD::BLENDI from a vselect if its argument
22984 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22985 // constants. This specific pattern gets generated when we split a
22986 // selector for a 512 bit vector in a machine without AVX512 (but with
22987 // 256-bit vectors), during legalization:
22989 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22991 // Iff we find this pattern and the build_vectors are built from
22992 // constants, we translate the vselect into a shuffle_vector that we
22993 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22994 if ((N->getOpcode() == ISD::VSELECT ||
22995 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22996 !DCI.isBeforeLegalize()) {
22997 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22998 if (Shuffle.getNode())
23005 // Check whether a boolean test is testing a boolean value generated by
23006 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23009 // Simplify the following patterns:
23010 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23011 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23012 // to (Op EFLAGS Cond)
23014 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23015 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23016 // to (Op EFLAGS !Cond)
23018 // where Op could be BRCOND or CMOV.
23020 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23021 // Quit if not CMP and SUB with its value result used.
23022 if (Cmp.getOpcode() != X86ISD::CMP &&
23023 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23026 // Quit if not used as a boolean value.
23027 if (CC != X86::COND_E && CC != X86::COND_NE)
23030 // Check CMP operands. One of them should be 0 or 1 and the other should be
23031 // an SetCC or extended from it.
23032 SDValue Op1 = Cmp.getOperand(0);
23033 SDValue Op2 = Cmp.getOperand(1);
23036 const ConstantSDNode* C = nullptr;
23037 bool needOppositeCond = (CC == X86::COND_E);
23038 bool checkAgainstTrue = false; // Is it a comparison against 1?
23040 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23042 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23044 else // Quit if all operands are not constants.
23047 if (C->getZExtValue() == 1) {
23048 needOppositeCond = !needOppositeCond;
23049 checkAgainstTrue = true;
23050 } else if (C->getZExtValue() != 0)
23051 // Quit if the constant is neither 0 or 1.
23054 bool truncatedToBoolWithAnd = false;
23055 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23056 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23057 SetCC.getOpcode() == ISD::TRUNCATE ||
23058 SetCC.getOpcode() == ISD::AND) {
23059 if (SetCC.getOpcode() == ISD::AND) {
23061 ConstantSDNode *CS;
23062 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23063 CS->getZExtValue() == 1)
23065 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23066 CS->getZExtValue() == 1)
23070 SetCC = SetCC.getOperand(OpIdx);
23071 truncatedToBoolWithAnd = true;
23073 SetCC = SetCC.getOperand(0);
23076 switch (SetCC.getOpcode()) {
23077 case X86ISD::SETCC_CARRY:
23078 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23079 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23080 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23081 // truncated to i1 using 'and'.
23082 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23084 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23085 "Invalid use of SETCC_CARRY!");
23087 case X86ISD::SETCC:
23088 // Set the condition code or opposite one if necessary.
23089 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23090 if (needOppositeCond)
23091 CC = X86::GetOppositeBranchCondition(CC);
23092 return SetCC.getOperand(1);
23093 case X86ISD::CMOV: {
23094 // Check whether false/true value has canonical one, i.e. 0 or 1.
23095 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23096 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23097 // Quit if true value is not a constant.
23100 // Quit if false value is not a constant.
23102 SDValue Op = SetCC.getOperand(0);
23103 // Skip 'zext' or 'trunc' node.
23104 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23105 Op.getOpcode() == ISD::TRUNCATE)
23106 Op = Op.getOperand(0);
23107 // A special case for rdrand/rdseed, where 0 is set if false cond is
23109 if ((Op.getOpcode() != X86ISD::RDRAND &&
23110 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23113 // Quit if false value is not the constant 0 or 1.
23114 bool FValIsFalse = true;
23115 if (FVal && FVal->getZExtValue() != 0) {
23116 if (FVal->getZExtValue() != 1)
23118 // If FVal is 1, opposite cond is needed.
23119 needOppositeCond = !needOppositeCond;
23120 FValIsFalse = false;
23122 // Quit if TVal is not the constant opposite of FVal.
23123 if (FValIsFalse && TVal->getZExtValue() != 1)
23125 if (!FValIsFalse && TVal->getZExtValue() != 0)
23127 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23128 if (needOppositeCond)
23129 CC = X86::GetOppositeBranchCondition(CC);
23130 return SetCC.getOperand(3);
23137 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23138 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23139 TargetLowering::DAGCombinerInfo &DCI,
23140 const X86Subtarget *Subtarget) {
23143 // If the flag operand isn't dead, don't touch this CMOV.
23144 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23147 SDValue FalseOp = N->getOperand(0);
23148 SDValue TrueOp = N->getOperand(1);
23149 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23150 SDValue Cond = N->getOperand(3);
23152 if (CC == X86::COND_E || CC == X86::COND_NE) {
23153 switch (Cond.getOpcode()) {
23157 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23158 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23159 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23165 Flags = checkBoolTestSetCCCombine(Cond, CC);
23166 if (Flags.getNode() &&
23167 // Extra check as FCMOV only supports a subset of X86 cond.
23168 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23169 SDValue Ops[] = { FalseOp, TrueOp,
23170 DAG.getConstant(CC, MVT::i8), Flags };
23171 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23174 // If this is a select between two integer constants, try to do some
23175 // optimizations. Note that the operands are ordered the opposite of SELECT
23177 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23178 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23179 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23180 // larger than FalseC (the false value).
23181 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23182 CC = X86::GetOppositeBranchCondition(CC);
23183 std::swap(TrueC, FalseC);
23184 std::swap(TrueOp, FalseOp);
23187 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23188 // This is efficient for any integer data type (including i8/i16) and
23190 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23191 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23192 DAG.getConstant(CC, MVT::i8), Cond);
23194 // Zero extend the condition if needed.
23195 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23197 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23198 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23199 DAG.getConstant(ShAmt, MVT::i8));
23200 if (N->getNumValues() == 2) // Dead flag value?
23201 return DCI.CombineTo(N, Cond, SDValue());
23205 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23206 // for any integer data type, including i8/i16.
23207 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23208 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23209 DAG.getConstant(CC, MVT::i8), Cond);
23211 // Zero extend the condition if needed.
23212 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23213 FalseC->getValueType(0), Cond);
23214 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23215 SDValue(FalseC, 0));
23217 if (N->getNumValues() == 2) // Dead flag value?
23218 return DCI.CombineTo(N, Cond, SDValue());
23222 // Optimize cases that will turn into an LEA instruction. This requires
23223 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23224 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23225 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23226 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23228 bool isFastMultiplier = false;
23230 switch ((unsigned char)Diff) {
23232 case 1: // result = add base, cond
23233 case 2: // result = lea base( , cond*2)
23234 case 3: // result = lea base(cond, cond*2)
23235 case 4: // result = lea base( , cond*4)
23236 case 5: // result = lea base(cond, cond*4)
23237 case 8: // result = lea base( , cond*8)
23238 case 9: // result = lea base(cond, cond*8)
23239 isFastMultiplier = true;
23244 if (isFastMultiplier) {
23245 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23246 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23247 DAG.getConstant(CC, MVT::i8), Cond);
23248 // Zero extend the condition if needed.
23249 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23251 // Scale the condition by the difference.
23253 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23254 DAG.getConstant(Diff, Cond.getValueType()));
23256 // Add the base if non-zero.
23257 if (FalseC->getAPIntValue() != 0)
23258 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23259 SDValue(FalseC, 0));
23260 if (N->getNumValues() == 2) // Dead flag value?
23261 return DCI.CombineTo(N, Cond, SDValue());
23268 // Handle these cases:
23269 // (select (x != c), e, c) -> select (x != c), e, x),
23270 // (select (x == c), c, e) -> select (x == c), x, e)
23271 // where the c is an integer constant, and the "select" is the combination
23272 // of CMOV and CMP.
23274 // The rationale for this change is that the conditional-move from a constant
23275 // needs two instructions, however, conditional-move from a register needs
23276 // only one instruction.
23278 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23279 // some instruction-combining opportunities. This opt needs to be
23280 // postponed as late as possible.
23282 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23283 // the DCI.xxxx conditions are provided to postpone the optimization as
23284 // late as possible.
23286 ConstantSDNode *CmpAgainst = nullptr;
23287 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23288 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23289 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23291 if (CC == X86::COND_NE &&
23292 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23293 CC = X86::GetOppositeBranchCondition(CC);
23294 std::swap(TrueOp, FalseOp);
23297 if (CC == X86::COND_E &&
23298 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23299 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23300 DAG.getConstant(CC, MVT::i8), Cond };
23301 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23309 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23310 const X86Subtarget *Subtarget) {
23311 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23313 default: return SDValue();
23314 // SSE/AVX/AVX2 blend intrinsics.
23315 case Intrinsic::x86_avx2_pblendvb:
23316 case Intrinsic::x86_avx2_pblendw:
23317 case Intrinsic::x86_avx2_pblendd_128:
23318 case Intrinsic::x86_avx2_pblendd_256:
23319 // Don't try to simplify this intrinsic if we don't have AVX2.
23320 if (!Subtarget->hasAVX2())
23323 case Intrinsic::x86_avx_blend_pd_256:
23324 case Intrinsic::x86_avx_blend_ps_256:
23325 case Intrinsic::x86_avx_blendv_pd_256:
23326 case Intrinsic::x86_avx_blendv_ps_256:
23327 // Don't try to simplify this intrinsic if we don't have AVX.
23328 if (!Subtarget->hasAVX())
23331 case Intrinsic::x86_sse41_pblendw:
23332 case Intrinsic::x86_sse41_blendpd:
23333 case Intrinsic::x86_sse41_blendps:
23334 case Intrinsic::x86_sse41_blendvps:
23335 case Intrinsic::x86_sse41_blendvpd:
23336 case Intrinsic::x86_sse41_pblendvb: {
23337 SDValue Op0 = N->getOperand(1);
23338 SDValue Op1 = N->getOperand(2);
23339 SDValue Mask = N->getOperand(3);
23341 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23342 if (!Subtarget->hasSSE41())
23345 // fold (blend A, A, Mask) -> A
23348 // fold (blend A, B, allZeros) -> A
23349 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23351 // fold (blend A, B, allOnes) -> B
23352 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23355 // Simplify the case where the mask is a constant i32 value.
23356 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23357 if (C->isNullValue())
23359 if (C->isAllOnesValue())
23366 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23367 case Intrinsic::x86_sse2_psrai_w:
23368 case Intrinsic::x86_sse2_psrai_d:
23369 case Intrinsic::x86_avx2_psrai_w:
23370 case Intrinsic::x86_avx2_psrai_d:
23371 case Intrinsic::x86_sse2_psra_w:
23372 case Intrinsic::x86_sse2_psra_d:
23373 case Intrinsic::x86_avx2_psra_w:
23374 case Intrinsic::x86_avx2_psra_d: {
23375 SDValue Op0 = N->getOperand(1);
23376 SDValue Op1 = N->getOperand(2);
23377 EVT VT = Op0.getValueType();
23378 assert(VT.isVector() && "Expected a vector type!");
23380 if (isa<BuildVectorSDNode>(Op1))
23381 Op1 = Op1.getOperand(0);
23383 if (!isa<ConstantSDNode>(Op1))
23386 EVT SVT = VT.getVectorElementType();
23387 unsigned SVTBits = SVT.getSizeInBits();
23389 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23390 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23391 uint64_t ShAmt = C.getZExtValue();
23393 // Don't try to convert this shift into a ISD::SRA if the shift
23394 // count is bigger than or equal to the element size.
23395 if (ShAmt >= SVTBits)
23398 // Trivial case: if the shift count is zero, then fold this
23399 // into the first operand.
23403 // Replace this packed shift intrinsic with a target independent
23405 SDValue Splat = DAG.getConstant(C, VT);
23406 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23411 /// PerformMulCombine - Optimize a single multiply with constant into two
23412 /// in order to implement it with two cheaper instructions, e.g.
23413 /// LEA + SHL, LEA + LEA.
23414 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23415 TargetLowering::DAGCombinerInfo &DCI) {
23416 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23419 EVT VT = N->getValueType(0);
23420 if (VT != MVT::i64)
23423 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23426 uint64_t MulAmt = C->getZExtValue();
23427 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23430 uint64_t MulAmt1 = 0;
23431 uint64_t MulAmt2 = 0;
23432 if ((MulAmt % 9) == 0) {
23434 MulAmt2 = MulAmt / 9;
23435 } else if ((MulAmt % 5) == 0) {
23437 MulAmt2 = MulAmt / 5;
23438 } else if ((MulAmt % 3) == 0) {
23440 MulAmt2 = MulAmt / 3;
23443 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23446 if (isPowerOf2_64(MulAmt2) &&
23447 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23448 // If second multiplifer is pow2, issue it first. We want the multiply by
23449 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23451 std::swap(MulAmt1, MulAmt2);
23454 if (isPowerOf2_64(MulAmt1))
23455 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23456 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23458 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23459 DAG.getConstant(MulAmt1, VT));
23461 if (isPowerOf2_64(MulAmt2))
23462 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23463 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23465 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23466 DAG.getConstant(MulAmt2, VT));
23468 // Do not add new nodes to DAG combiner worklist.
23469 DCI.CombineTo(N, NewMul, false);
23474 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23475 SDValue N0 = N->getOperand(0);
23476 SDValue N1 = N->getOperand(1);
23477 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23478 EVT VT = N0.getValueType();
23480 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23481 // since the result of setcc_c is all zero's or all ones.
23482 if (VT.isInteger() && !VT.isVector() &&
23483 N1C && N0.getOpcode() == ISD::AND &&
23484 N0.getOperand(1).getOpcode() == ISD::Constant) {
23485 SDValue N00 = N0.getOperand(0);
23486 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23487 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23488 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23489 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23490 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23491 APInt ShAmt = N1C->getAPIntValue();
23492 Mask = Mask.shl(ShAmt);
23494 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23495 N00, DAG.getConstant(Mask, VT));
23499 // Hardware support for vector shifts is sparse which makes us scalarize the
23500 // vector operations in many cases. Also, on sandybridge ADD is faster than
23502 // (shl V, 1) -> add V,V
23503 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23504 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23505 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23506 // We shift all of the values by one. In many cases we do not have
23507 // hardware support for this operation. This is better expressed as an ADD
23509 if (N1SplatC->getZExtValue() == 1)
23510 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23516 /// \brief Returns a vector of 0s if the node in input is a vector logical
23517 /// shift by a constant amount which is known to be bigger than or equal
23518 /// to the vector element size in bits.
23519 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23520 const X86Subtarget *Subtarget) {
23521 EVT VT = N->getValueType(0);
23523 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23524 (!Subtarget->hasInt256() ||
23525 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23528 SDValue Amt = N->getOperand(1);
23530 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23531 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23532 APInt ShiftAmt = AmtSplat->getAPIntValue();
23533 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23535 // SSE2/AVX2 logical shifts always return a vector of 0s
23536 // if the shift amount is bigger than or equal to
23537 // the element size. The constant shift amount will be
23538 // encoded as a 8-bit immediate.
23539 if (ShiftAmt.trunc(8).uge(MaxAmount))
23540 return getZeroVector(VT, Subtarget, DAG, DL);
23546 /// PerformShiftCombine - Combine shifts.
23547 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23548 TargetLowering::DAGCombinerInfo &DCI,
23549 const X86Subtarget *Subtarget) {
23550 if (N->getOpcode() == ISD::SHL) {
23551 SDValue V = PerformSHLCombine(N, DAG);
23552 if (V.getNode()) return V;
23555 if (N->getOpcode() != ISD::SRA) {
23556 // Try to fold this logical shift into a zero vector.
23557 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23558 if (V.getNode()) return V;
23564 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23565 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23566 // and friends. Likewise for OR -> CMPNEQSS.
23567 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23568 TargetLowering::DAGCombinerInfo &DCI,
23569 const X86Subtarget *Subtarget) {
23572 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23573 // we're requiring SSE2 for both.
23574 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23575 SDValue N0 = N->getOperand(0);
23576 SDValue N1 = N->getOperand(1);
23577 SDValue CMP0 = N0->getOperand(1);
23578 SDValue CMP1 = N1->getOperand(1);
23581 // The SETCCs should both refer to the same CMP.
23582 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23585 SDValue CMP00 = CMP0->getOperand(0);
23586 SDValue CMP01 = CMP0->getOperand(1);
23587 EVT VT = CMP00.getValueType();
23589 if (VT == MVT::f32 || VT == MVT::f64) {
23590 bool ExpectingFlags = false;
23591 // Check for any users that want flags:
23592 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23593 !ExpectingFlags && UI != UE; ++UI)
23594 switch (UI->getOpcode()) {
23599 ExpectingFlags = true;
23601 case ISD::CopyToReg:
23602 case ISD::SIGN_EXTEND:
23603 case ISD::ZERO_EXTEND:
23604 case ISD::ANY_EXTEND:
23608 if (!ExpectingFlags) {
23609 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23610 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23612 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23613 X86::CondCode tmp = cc0;
23618 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23619 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23620 // FIXME: need symbolic constants for these magic numbers.
23621 // See X86ATTInstPrinter.cpp:printSSECC().
23622 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23623 if (Subtarget->hasAVX512()) {
23624 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23625 CMP01, DAG.getConstant(x86cc, MVT::i8));
23626 if (N->getValueType(0) != MVT::i1)
23627 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23631 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23632 CMP00.getValueType(), CMP00, CMP01,
23633 DAG.getConstant(x86cc, MVT::i8));
23635 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23636 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23638 if (is64BitFP && !Subtarget->is64Bit()) {
23639 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23640 // 64-bit integer, since that's not a legal type. Since
23641 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23642 // bits, but can do this little dance to extract the lowest 32 bits
23643 // and work with those going forward.
23644 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23646 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23648 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23649 Vector32, DAG.getIntPtrConstant(0));
23653 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23654 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23655 DAG.getConstant(1, IntVT));
23656 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23657 return OneBitOfTruth;
23665 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23666 /// so it can be folded inside ANDNP.
23667 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23668 EVT VT = N->getValueType(0);
23670 // Match direct AllOnes for 128 and 256-bit vectors
23671 if (ISD::isBuildVectorAllOnes(N))
23674 // Look through a bit convert.
23675 if (N->getOpcode() == ISD::BITCAST)
23676 N = N->getOperand(0).getNode();
23678 // Sometimes the operand may come from a insert_subvector building a 256-bit
23680 if (VT.is256BitVector() &&
23681 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23682 SDValue V1 = N->getOperand(0);
23683 SDValue V2 = N->getOperand(1);
23685 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23686 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23687 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23688 ISD::isBuildVectorAllOnes(V2.getNode()))
23695 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23696 // register. In most cases we actually compare or select YMM-sized registers
23697 // and mixing the two types creates horrible code. This method optimizes
23698 // some of the transition sequences.
23699 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23700 TargetLowering::DAGCombinerInfo &DCI,
23701 const X86Subtarget *Subtarget) {
23702 EVT VT = N->getValueType(0);
23703 if (!VT.is256BitVector())
23706 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23707 N->getOpcode() == ISD::ZERO_EXTEND ||
23708 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23710 SDValue Narrow = N->getOperand(0);
23711 EVT NarrowVT = Narrow->getValueType(0);
23712 if (!NarrowVT.is128BitVector())
23715 if (Narrow->getOpcode() != ISD::XOR &&
23716 Narrow->getOpcode() != ISD::AND &&
23717 Narrow->getOpcode() != ISD::OR)
23720 SDValue N0 = Narrow->getOperand(0);
23721 SDValue N1 = Narrow->getOperand(1);
23724 // The Left side has to be a trunc.
23725 if (N0.getOpcode() != ISD::TRUNCATE)
23728 // The type of the truncated inputs.
23729 EVT WideVT = N0->getOperand(0)->getValueType(0);
23733 // The right side has to be a 'trunc' or a constant vector.
23734 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23735 ConstantSDNode *RHSConstSplat = nullptr;
23736 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23737 RHSConstSplat = RHSBV->getConstantSplatNode();
23738 if (!RHSTrunc && !RHSConstSplat)
23741 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23743 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23746 // Set N0 and N1 to hold the inputs to the new wide operation.
23747 N0 = N0->getOperand(0);
23748 if (RHSConstSplat) {
23749 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23750 SDValue(RHSConstSplat, 0));
23751 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23752 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23753 } else if (RHSTrunc) {
23754 N1 = N1->getOperand(0);
23757 // Generate the wide operation.
23758 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23759 unsigned Opcode = N->getOpcode();
23761 case ISD::ANY_EXTEND:
23763 case ISD::ZERO_EXTEND: {
23764 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23765 APInt Mask = APInt::getAllOnesValue(InBits);
23766 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23767 return DAG.getNode(ISD::AND, DL, VT,
23768 Op, DAG.getConstant(Mask, VT));
23770 case ISD::SIGN_EXTEND:
23771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23772 Op, DAG.getValueType(NarrowVT));
23774 llvm_unreachable("Unexpected opcode");
23778 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23779 TargetLowering::DAGCombinerInfo &DCI,
23780 const X86Subtarget *Subtarget) {
23781 EVT VT = N->getValueType(0);
23782 if (DCI.isBeforeLegalizeOps())
23785 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23789 // Create BEXTR instructions
23790 // BEXTR is ((X >> imm) & (2**size-1))
23791 if (VT == MVT::i32 || VT == MVT::i64) {
23792 SDValue N0 = N->getOperand(0);
23793 SDValue N1 = N->getOperand(1);
23796 // Check for BEXTR.
23797 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23798 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23799 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23800 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23801 if (MaskNode && ShiftNode) {
23802 uint64_t Mask = MaskNode->getZExtValue();
23803 uint64_t Shift = ShiftNode->getZExtValue();
23804 if (isMask_64(Mask)) {
23805 uint64_t MaskSize = CountPopulation_64(Mask);
23806 if (Shift + MaskSize <= VT.getSizeInBits())
23807 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23808 DAG.getConstant(Shift | (MaskSize << 8), VT));
23816 // Want to form ANDNP nodes:
23817 // 1) In the hopes of then easily combining them with OR and AND nodes
23818 // to form PBLEND/PSIGN.
23819 // 2) To match ANDN packed intrinsics
23820 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23823 SDValue N0 = N->getOperand(0);
23824 SDValue N1 = N->getOperand(1);
23827 // Check LHS for vnot
23828 if (N0.getOpcode() == ISD::XOR &&
23829 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23830 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23831 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23833 // Check RHS for vnot
23834 if (N1.getOpcode() == ISD::XOR &&
23835 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23836 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23837 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23842 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23843 TargetLowering::DAGCombinerInfo &DCI,
23844 const X86Subtarget *Subtarget) {
23845 if (DCI.isBeforeLegalizeOps())
23848 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23852 SDValue N0 = N->getOperand(0);
23853 SDValue N1 = N->getOperand(1);
23854 EVT VT = N->getValueType(0);
23856 // look for psign/blend
23857 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23858 if (!Subtarget->hasSSSE3() ||
23859 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23862 // Canonicalize pandn to RHS
23863 if (N0.getOpcode() == X86ISD::ANDNP)
23865 // or (and (m, y), (pandn m, x))
23866 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23867 SDValue Mask = N1.getOperand(0);
23868 SDValue X = N1.getOperand(1);
23870 if (N0.getOperand(0) == Mask)
23871 Y = N0.getOperand(1);
23872 if (N0.getOperand(1) == Mask)
23873 Y = N0.getOperand(0);
23875 // Check to see if the mask appeared in both the AND and ANDNP and
23879 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23880 // Look through mask bitcast.
23881 if (Mask.getOpcode() == ISD::BITCAST)
23882 Mask = Mask.getOperand(0);
23883 if (X.getOpcode() == ISD::BITCAST)
23884 X = X.getOperand(0);
23885 if (Y.getOpcode() == ISD::BITCAST)
23886 Y = Y.getOperand(0);
23888 EVT MaskVT = Mask.getValueType();
23890 // Validate that the Mask operand is a vector sra node.
23891 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23892 // there is no psrai.b
23893 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23894 unsigned SraAmt = ~0;
23895 if (Mask.getOpcode() == ISD::SRA) {
23896 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23897 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23898 SraAmt = AmtConst->getZExtValue();
23899 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23900 SDValue SraC = Mask.getOperand(1);
23901 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23903 if ((SraAmt + 1) != EltBits)
23908 // Now we know we at least have a plendvb with the mask val. See if
23909 // we can form a psignb/w/d.
23910 // psign = x.type == y.type == mask.type && y = sub(0, x);
23911 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23912 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23913 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23914 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23915 "Unsupported VT for PSIGN");
23916 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23917 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23919 // PBLENDVB only available on SSE 4.1
23920 if (!Subtarget->hasSSE41())
23923 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23925 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23926 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23927 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23928 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23929 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23933 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23936 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23937 MachineFunction &MF = DAG.getMachineFunction();
23938 bool OptForSize = MF.getFunction()->getAttributes().
23939 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23941 // SHLD/SHRD instructions have lower register pressure, but on some
23942 // platforms they have higher latency than the equivalent
23943 // series of shifts/or that would otherwise be generated.
23944 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23945 // have higher latencies and we are not optimizing for size.
23946 if (!OptForSize && Subtarget->isSHLDSlow())
23949 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23951 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23953 if (!N0.hasOneUse() || !N1.hasOneUse())
23956 SDValue ShAmt0 = N0.getOperand(1);
23957 if (ShAmt0.getValueType() != MVT::i8)
23959 SDValue ShAmt1 = N1.getOperand(1);
23960 if (ShAmt1.getValueType() != MVT::i8)
23962 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23963 ShAmt0 = ShAmt0.getOperand(0);
23964 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23965 ShAmt1 = ShAmt1.getOperand(0);
23968 unsigned Opc = X86ISD::SHLD;
23969 SDValue Op0 = N0.getOperand(0);
23970 SDValue Op1 = N1.getOperand(0);
23971 if (ShAmt0.getOpcode() == ISD::SUB) {
23972 Opc = X86ISD::SHRD;
23973 std::swap(Op0, Op1);
23974 std::swap(ShAmt0, ShAmt1);
23977 unsigned Bits = VT.getSizeInBits();
23978 if (ShAmt1.getOpcode() == ISD::SUB) {
23979 SDValue Sum = ShAmt1.getOperand(0);
23980 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23981 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23982 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23983 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23984 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23985 return DAG.getNode(Opc, DL, VT,
23987 DAG.getNode(ISD::TRUNCATE, DL,
23990 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23991 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23993 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23994 return DAG.getNode(Opc, DL, VT,
23995 N0.getOperand(0), N1.getOperand(0),
23996 DAG.getNode(ISD::TRUNCATE, DL,
24003 // Generate NEG and CMOV for integer abs.
24004 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24005 EVT VT = N->getValueType(0);
24007 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24008 // 8-bit integer abs to NEG and CMOV.
24009 if (VT.isInteger() && VT.getSizeInBits() == 8)
24012 SDValue N0 = N->getOperand(0);
24013 SDValue N1 = N->getOperand(1);
24016 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24017 // and change it to SUB and CMOV.
24018 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24019 N0.getOpcode() == ISD::ADD &&
24020 N0.getOperand(1) == N1 &&
24021 N1.getOpcode() == ISD::SRA &&
24022 N1.getOperand(0) == N0.getOperand(0))
24023 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24024 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24025 // Generate SUB & CMOV.
24026 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24027 DAG.getConstant(0, VT), N0.getOperand(0));
24029 SDValue Ops[] = { N0.getOperand(0), Neg,
24030 DAG.getConstant(X86::COND_GE, MVT::i8),
24031 SDValue(Neg.getNode(), 1) };
24032 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24037 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24038 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24039 TargetLowering::DAGCombinerInfo &DCI,
24040 const X86Subtarget *Subtarget) {
24041 if (DCI.isBeforeLegalizeOps())
24044 if (Subtarget->hasCMov()) {
24045 SDValue RV = performIntegerAbsCombine(N, DAG);
24053 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24054 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24055 TargetLowering::DAGCombinerInfo &DCI,
24056 const X86Subtarget *Subtarget) {
24057 LoadSDNode *Ld = cast<LoadSDNode>(N);
24058 EVT RegVT = Ld->getValueType(0);
24059 EVT MemVT = Ld->getMemoryVT();
24061 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24063 // On Sandybridge unaligned 256bit loads are inefficient.
24064 ISD::LoadExtType Ext = Ld->getExtensionType();
24065 unsigned Alignment = Ld->getAlignment();
24066 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24067 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
24068 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24069 unsigned NumElems = RegVT.getVectorNumElements();
24073 SDValue Ptr = Ld->getBasePtr();
24074 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24076 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24078 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24079 Ld->getPointerInfo(), Ld->isVolatile(),
24080 Ld->isNonTemporal(), Ld->isInvariant(),
24082 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24083 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24084 Ld->getPointerInfo(), Ld->isVolatile(),
24085 Ld->isNonTemporal(), Ld->isInvariant(),
24086 std::min(16U, Alignment));
24087 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24089 Load2.getValue(1));
24091 SDValue NewVec = DAG.getUNDEF(RegVT);
24092 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24093 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24094 return DCI.CombineTo(N, NewVec, TF, true);
24100 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24101 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24102 const X86Subtarget *Subtarget) {
24103 StoreSDNode *St = cast<StoreSDNode>(N);
24104 EVT VT = St->getValue().getValueType();
24105 EVT StVT = St->getMemoryVT();
24107 SDValue StoredVal = St->getOperand(1);
24108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24110 // If we are saving a concatenation of two XMM registers, perform two stores.
24111 // On Sandy Bridge, 256-bit memory operations are executed by two
24112 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
24113 // memory operation.
24114 unsigned Alignment = St->getAlignment();
24115 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24116 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
24117 StVT == VT && !IsAligned) {
24118 unsigned NumElems = VT.getVectorNumElements();
24122 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24123 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24125 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24126 SDValue Ptr0 = St->getBasePtr();
24127 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24129 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24130 St->getPointerInfo(), St->isVolatile(),
24131 St->isNonTemporal(), Alignment);
24132 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24133 St->getPointerInfo(), St->isVolatile(),
24134 St->isNonTemporal(),
24135 std::min(16U, Alignment));
24136 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24139 // Optimize trunc store (of multiple scalars) to shuffle and store.
24140 // First, pack all of the elements in one place. Next, store to memory
24141 // in fewer chunks.
24142 if (St->isTruncatingStore() && VT.isVector()) {
24143 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24144 unsigned NumElems = VT.getVectorNumElements();
24145 assert(StVT != VT && "Cannot truncate to the same type");
24146 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24147 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24149 // From, To sizes and ElemCount must be pow of two
24150 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24151 // We are going to use the original vector elt for storing.
24152 // Accumulated smaller vector elements must be a multiple of the store size.
24153 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24155 unsigned SizeRatio = FromSz / ToSz;
24157 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24159 // Create a type on which we perform the shuffle
24160 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24161 StVT.getScalarType(), NumElems*SizeRatio);
24163 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24165 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24166 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24167 for (unsigned i = 0; i != NumElems; ++i)
24168 ShuffleVec[i] = i * SizeRatio;
24170 // Can't shuffle using an illegal type.
24171 if (!TLI.isTypeLegal(WideVecVT))
24174 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24175 DAG.getUNDEF(WideVecVT),
24177 // At this point all of the data is stored at the bottom of the
24178 // register. We now need to save it to mem.
24180 // Find the largest store unit
24181 MVT StoreType = MVT::i8;
24182 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24183 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24184 MVT Tp = (MVT::SimpleValueType)tp;
24185 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24189 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24190 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24191 (64 <= NumElems * ToSz))
24192 StoreType = MVT::f64;
24194 // Bitcast the original vector into a vector of store-size units
24195 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24196 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24197 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24198 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24199 SmallVector<SDValue, 8> Chains;
24200 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24201 TLI.getPointerTy());
24202 SDValue Ptr = St->getBasePtr();
24204 // Perform one or more big stores into memory.
24205 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24206 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24207 StoreType, ShuffWide,
24208 DAG.getIntPtrConstant(i));
24209 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24210 St->getPointerInfo(), St->isVolatile(),
24211 St->isNonTemporal(), St->getAlignment());
24212 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24213 Chains.push_back(Ch);
24216 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24219 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24220 // the FP state in cases where an emms may be missing.
24221 // A preferable solution to the general problem is to figure out the right
24222 // places to insert EMMS. This qualifies as a quick hack.
24224 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24225 if (VT.getSizeInBits() != 64)
24228 const Function *F = DAG.getMachineFunction().getFunction();
24229 bool NoImplicitFloatOps = F->getAttributes().
24230 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24231 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24232 && Subtarget->hasSSE2();
24233 if ((VT.isVector() ||
24234 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24235 isa<LoadSDNode>(St->getValue()) &&
24236 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24237 St->getChain().hasOneUse() && !St->isVolatile()) {
24238 SDNode* LdVal = St->getValue().getNode();
24239 LoadSDNode *Ld = nullptr;
24240 int TokenFactorIndex = -1;
24241 SmallVector<SDValue, 8> Ops;
24242 SDNode* ChainVal = St->getChain().getNode();
24243 // Must be a store of a load. We currently handle two cases: the load
24244 // is a direct child, and it's under an intervening TokenFactor. It is
24245 // possible to dig deeper under nested TokenFactors.
24246 if (ChainVal == LdVal)
24247 Ld = cast<LoadSDNode>(St->getChain());
24248 else if (St->getValue().hasOneUse() &&
24249 ChainVal->getOpcode() == ISD::TokenFactor) {
24250 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24251 if (ChainVal->getOperand(i).getNode() == LdVal) {
24252 TokenFactorIndex = i;
24253 Ld = cast<LoadSDNode>(St->getValue());
24255 Ops.push_back(ChainVal->getOperand(i));
24259 if (!Ld || !ISD::isNormalLoad(Ld))
24262 // If this is not the MMX case, i.e. we are just turning i64 load/store
24263 // into f64 load/store, avoid the transformation if there are multiple
24264 // uses of the loaded value.
24265 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24270 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24271 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24273 if (Subtarget->is64Bit() || F64IsLegal) {
24274 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24275 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24276 Ld->getPointerInfo(), Ld->isVolatile(),
24277 Ld->isNonTemporal(), Ld->isInvariant(),
24278 Ld->getAlignment());
24279 SDValue NewChain = NewLd.getValue(1);
24280 if (TokenFactorIndex != -1) {
24281 Ops.push_back(NewChain);
24282 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24284 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24285 St->getPointerInfo(),
24286 St->isVolatile(), St->isNonTemporal(),
24287 St->getAlignment());
24290 // Otherwise, lower to two pairs of 32-bit loads / stores.
24291 SDValue LoAddr = Ld->getBasePtr();
24292 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24293 DAG.getConstant(4, MVT::i32));
24295 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24296 Ld->getPointerInfo(),
24297 Ld->isVolatile(), Ld->isNonTemporal(),
24298 Ld->isInvariant(), Ld->getAlignment());
24299 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24300 Ld->getPointerInfo().getWithOffset(4),
24301 Ld->isVolatile(), Ld->isNonTemporal(),
24303 MinAlign(Ld->getAlignment(), 4));
24305 SDValue NewChain = LoLd.getValue(1);
24306 if (TokenFactorIndex != -1) {
24307 Ops.push_back(LoLd);
24308 Ops.push_back(HiLd);
24309 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24312 LoAddr = St->getBasePtr();
24313 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24314 DAG.getConstant(4, MVT::i32));
24316 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24317 St->getPointerInfo(),
24318 St->isVolatile(), St->isNonTemporal(),
24319 St->getAlignment());
24320 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24321 St->getPointerInfo().getWithOffset(4),
24323 St->isNonTemporal(),
24324 MinAlign(St->getAlignment(), 4));
24325 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24330 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24331 /// and return the operands for the horizontal operation in LHS and RHS. A
24332 /// horizontal operation performs the binary operation on successive elements
24333 /// of its first operand, then on successive elements of its second operand,
24334 /// returning the resulting values in a vector. For example, if
24335 /// A = < float a0, float a1, float a2, float a3 >
24337 /// B = < float b0, float b1, float b2, float b3 >
24338 /// then the result of doing a horizontal operation on A and B is
24339 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24340 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24341 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24342 /// set to A, RHS to B, and the routine returns 'true'.
24343 /// Note that the binary operation should have the property that if one of the
24344 /// operands is UNDEF then the result is UNDEF.
24345 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24346 // Look for the following pattern: if
24347 // A = < float a0, float a1, float a2, float a3 >
24348 // B = < float b0, float b1, float b2, float b3 >
24350 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24351 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24352 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24353 // which is A horizontal-op B.
24355 // At least one of the operands should be a vector shuffle.
24356 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24357 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24360 MVT VT = LHS.getSimpleValueType();
24362 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24363 "Unsupported vector type for horizontal add/sub");
24365 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24366 // operate independently on 128-bit lanes.
24367 unsigned NumElts = VT.getVectorNumElements();
24368 unsigned NumLanes = VT.getSizeInBits()/128;
24369 unsigned NumLaneElts = NumElts / NumLanes;
24370 assert((NumLaneElts % 2 == 0) &&
24371 "Vector type should have an even number of elements in each lane");
24372 unsigned HalfLaneElts = NumLaneElts/2;
24374 // View LHS in the form
24375 // LHS = VECTOR_SHUFFLE A, B, LMask
24376 // If LHS is not a shuffle then pretend it is the shuffle
24377 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24378 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24381 SmallVector<int, 16> LMask(NumElts);
24382 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24383 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24384 A = LHS.getOperand(0);
24385 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24386 B = LHS.getOperand(1);
24387 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24388 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24390 if (LHS.getOpcode() != ISD::UNDEF)
24392 for (unsigned i = 0; i != NumElts; ++i)
24396 // Likewise, view RHS in the form
24397 // RHS = VECTOR_SHUFFLE C, D, RMask
24399 SmallVector<int, 16> RMask(NumElts);
24400 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24401 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24402 C = RHS.getOperand(0);
24403 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24404 D = RHS.getOperand(1);
24405 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24406 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24408 if (RHS.getOpcode() != ISD::UNDEF)
24410 for (unsigned i = 0; i != NumElts; ++i)
24414 // Check that the shuffles are both shuffling the same vectors.
24415 if (!(A == C && B == D) && !(A == D && B == C))
24418 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24419 if (!A.getNode() && !B.getNode())
24422 // If A and B occur in reverse order in RHS, then "swap" them (which means
24423 // rewriting the mask).
24425 CommuteVectorShuffleMask(RMask, NumElts);
24427 // At this point LHS and RHS are equivalent to
24428 // LHS = VECTOR_SHUFFLE A, B, LMask
24429 // RHS = VECTOR_SHUFFLE A, B, RMask
24430 // Check that the masks correspond to performing a horizontal operation.
24431 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24432 for (unsigned i = 0; i != NumLaneElts; ++i) {
24433 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24435 // Ignore any UNDEF components.
24436 if (LIdx < 0 || RIdx < 0 ||
24437 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24438 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24441 // Check that successive elements are being operated on. If not, this is
24442 // not a horizontal operation.
24443 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24444 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24445 if (!(LIdx == Index && RIdx == Index + 1) &&
24446 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24451 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24452 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24456 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24457 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24458 const X86Subtarget *Subtarget) {
24459 EVT VT = N->getValueType(0);
24460 SDValue LHS = N->getOperand(0);
24461 SDValue RHS = N->getOperand(1);
24463 // Try to synthesize horizontal adds from adds of shuffles.
24464 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24465 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24466 isHorizontalBinOp(LHS, RHS, true))
24467 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24471 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24472 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24473 const X86Subtarget *Subtarget) {
24474 EVT VT = N->getValueType(0);
24475 SDValue LHS = N->getOperand(0);
24476 SDValue RHS = N->getOperand(1);
24478 // Try to synthesize horizontal subs from subs of shuffles.
24479 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24480 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24481 isHorizontalBinOp(LHS, RHS, false))
24482 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24486 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24487 /// X86ISD::FXOR nodes.
24488 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24489 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24490 // F[X]OR(0.0, x) -> x
24491 // F[X]OR(x, 0.0) -> x
24492 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24493 if (C->getValueAPF().isPosZero())
24494 return N->getOperand(1);
24495 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24496 if (C->getValueAPF().isPosZero())
24497 return N->getOperand(0);
24501 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24502 /// X86ISD::FMAX nodes.
24503 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24504 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24506 // Only perform optimizations if UnsafeMath is used.
24507 if (!DAG.getTarget().Options.UnsafeFPMath)
24510 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24511 // into FMINC and FMAXC, which are Commutative operations.
24512 unsigned NewOp = 0;
24513 switch (N->getOpcode()) {
24514 default: llvm_unreachable("unknown opcode");
24515 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24516 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24519 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24520 N->getOperand(0), N->getOperand(1));
24523 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24524 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24525 // FAND(0.0, x) -> 0.0
24526 // FAND(x, 0.0) -> 0.0
24527 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24528 if (C->getValueAPF().isPosZero())
24529 return N->getOperand(0);
24530 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24531 if (C->getValueAPF().isPosZero())
24532 return N->getOperand(1);
24536 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24537 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24538 // FANDN(x, 0.0) -> 0.0
24539 // FANDN(0.0, x) -> x
24540 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24541 if (C->getValueAPF().isPosZero())
24542 return N->getOperand(1);
24543 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24544 if (C->getValueAPF().isPosZero())
24545 return N->getOperand(1);
24549 static SDValue PerformBTCombine(SDNode *N,
24551 TargetLowering::DAGCombinerInfo &DCI) {
24552 // BT ignores high bits in the bit index operand.
24553 SDValue Op1 = N->getOperand(1);
24554 if (Op1.hasOneUse()) {
24555 unsigned BitWidth = Op1.getValueSizeInBits();
24556 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24557 APInt KnownZero, KnownOne;
24558 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24559 !DCI.isBeforeLegalizeOps());
24560 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24561 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24562 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24563 DCI.CommitTargetLoweringOpt(TLO);
24568 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24569 SDValue Op = N->getOperand(0);
24570 if (Op.getOpcode() == ISD::BITCAST)
24571 Op = Op.getOperand(0);
24572 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24573 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24574 VT.getVectorElementType().getSizeInBits() ==
24575 OpVT.getVectorElementType().getSizeInBits()) {
24576 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24581 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24582 const X86Subtarget *Subtarget) {
24583 EVT VT = N->getValueType(0);
24584 if (!VT.isVector())
24587 SDValue N0 = N->getOperand(0);
24588 SDValue N1 = N->getOperand(1);
24589 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24592 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24593 // both SSE and AVX2 since there is no sign-extended shift right
24594 // operation on a vector with 64-bit elements.
24595 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24596 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24597 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24598 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24599 SDValue N00 = N0.getOperand(0);
24601 // EXTLOAD has a better solution on AVX2,
24602 // it may be replaced with X86ISD::VSEXT node.
24603 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24604 if (!ISD::isNormalLoad(N00.getNode()))
24607 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24608 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24610 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24616 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24617 TargetLowering::DAGCombinerInfo &DCI,
24618 const X86Subtarget *Subtarget) {
24619 SDValue N0 = N->getOperand(0);
24620 EVT VT = N->getValueType(0);
24622 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24623 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24624 // This exposes the sext to the sdivrem lowering, so that it directly extends
24625 // from AH (which we otherwise need to do contortions to access).
24626 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24627 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24629 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24630 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24631 N0.getOperand(0), N0.getOperand(1));
24632 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24633 return R.getValue(1);
24636 if (!DCI.isBeforeLegalizeOps())
24639 if (!Subtarget->hasFp256())
24642 if (VT.isVector() && VT.getSizeInBits() == 256) {
24643 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24651 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24652 const X86Subtarget* Subtarget) {
24654 EVT VT = N->getValueType(0);
24656 // Let legalize expand this if it isn't a legal type yet.
24657 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24660 EVT ScalarVT = VT.getScalarType();
24661 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24662 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24665 SDValue A = N->getOperand(0);
24666 SDValue B = N->getOperand(1);
24667 SDValue C = N->getOperand(2);
24669 bool NegA = (A.getOpcode() == ISD::FNEG);
24670 bool NegB = (B.getOpcode() == ISD::FNEG);
24671 bool NegC = (C.getOpcode() == ISD::FNEG);
24673 // Negative multiplication when NegA xor NegB
24674 bool NegMul = (NegA != NegB);
24676 A = A.getOperand(0);
24678 B = B.getOperand(0);
24680 C = C.getOperand(0);
24684 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24686 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24688 return DAG.getNode(Opcode, dl, VT, A, B, C);
24691 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24692 TargetLowering::DAGCombinerInfo &DCI,
24693 const X86Subtarget *Subtarget) {
24694 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24695 // (and (i32 x86isd::setcc_carry), 1)
24696 // This eliminates the zext. This transformation is necessary because
24697 // ISD::SETCC is always legalized to i8.
24699 SDValue N0 = N->getOperand(0);
24700 EVT VT = N->getValueType(0);
24702 if (N0.getOpcode() == ISD::AND &&
24704 N0.getOperand(0).hasOneUse()) {
24705 SDValue N00 = N0.getOperand(0);
24706 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24707 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24708 if (!C || C->getZExtValue() != 1)
24710 return DAG.getNode(ISD::AND, dl, VT,
24711 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24712 N00.getOperand(0), N00.getOperand(1)),
24713 DAG.getConstant(1, VT));
24717 if (N0.getOpcode() == ISD::TRUNCATE &&
24719 N0.getOperand(0).hasOneUse()) {
24720 SDValue N00 = N0.getOperand(0);
24721 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24722 return DAG.getNode(ISD::AND, dl, VT,
24723 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24724 N00.getOperand(0), N00.getOperand(1)),
24725 DAG.getConstant(1, VT));
24728 if (VT.is256BitVector()) {
24729 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24734 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24735 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24736 // This exposes the zext to the udivrem lowering, so that it directly extends
24737 // from AH (which we otherwise need to do contortions to access).
24738 if (N0.getOpcode() == ISD::UDIVREM &&
24739 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24740 (VT == MVT::i32 || VT == MVT::i64)) {
24741 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24742 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24743 N0.getOperand(0), N0.getOperand(1));
24744 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24745 return R.getValue(1);
24751 // Optimize x == -y --> x+y == 0
24752 // x != -y --> x+y != 0
24753 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24754 const X86Subtarget* Subtarget) {
24755 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24756 SDValue LHS = N->getOperand(0);
24757 SDValue RHS = N->getOperand(1);
24758 EVT VT = N->getValueType(0);
24761 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24762 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24763 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24764 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24765 LHS.getValueType(), RHS, LHS.getOperand(1));
24766 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24767 addV, DAG.getConstant(0, addV.getValueType()), CC);
24769 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24770 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24771 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24772 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24773 RHS.getValueType(), LHS, RHS.getOperand(1));
24774 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24775 addV, DAG.getConstant(0, addV.getValueType()), CC);
24778 if (VT.getScalarType() == MVT::i1) {
24779 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24780 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24781 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24782 if (!IsSEXT0 && !IsVZero0)
24784 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24785 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24786 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24788 if (!IsSEXT1 && !IsVZero1)
24791 if (IsSEXT0 && IsVZero1) {
24792 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24793 if (CC == ISD::SETEQ)
24794 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24795 return LHS.getOperand(0);
24797 if (IsSEXT1 && IsVZero0) {
24798 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24799 if (CC == ISD::SETEQ)
24800 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24801 return RHS.getOperand(0);
24808 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24809 const X86Subtarget *Subtarget) {
24811 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24812 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24813 "X86insertps is only defined for v4x32");
24815 SDValue Ld = N->getOperand(1);
24816 if (MayFoldLoad(Ld)) {
24817 // Extract the countS bits from the immediate so we can get the proper
24818 // address when narrowing the vector load to a specific element.
24819 // When the second source op is a memory address, interps doesn't use
24820 // countS and just gets an f32 from that address.
24821 unsigned DestIndex =
24822 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24823 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24827 // Create this as a scalar to vector to match the instruction pattern.
24828 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24829 // countS bits are ignored when loading from memory on insertps, which
24830 // means we don't need to explicitly set them to 0.
24831 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24832 LoadScalarToVector, N->getOperand(2));
24835 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24836 // as "sbb reg,reg", since it can be extended without zext and produces
24837 // an all-ones bit which is more useful than 0/1 in some cases.
24838 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24841 return DAG.getNode(ISD::AND, DL, VT,
24842 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24843 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24844 DAG.getConstant(1, VT));
24845 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24846 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24847 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24848 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24851 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24852 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24853 TargetLowering::DAGCombinerInfo &DCI,
24854 const X86Subtarget *Subtarget) {
24856 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24857 SDValue EFLAGS = N->getOperand(1);
24859 if (CC == X86::COND_A) {
24860 // Try to convert COND_A into COND_B in an attempt to facilitate
24861 // materializing "setb reg".
24863 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24864 // cannot take an immediate as its first operand.
24866 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24867 EFLAGS.getValueType().isInteger() &&
24868 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24869 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24870 EFLAGS.getNode()->getVTList(),
24871 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24872 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24873 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24877 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24878 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24880 if (CC == X86::COND_B)
24881 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24885 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24886 if (Flags.getNode()) {
24887 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24888 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24894 // Optimize branch condition evaluation.
24896 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24897 TargetLowering::DAGCombinerInfo &DCI,
24898 const X86Subtarget *Subtarget) {
24900 SDValue Chain = N->getOperand(0);
24901 SDValue Dest = N->getOperand(1);
24902 SDValue EFLAGS = N->getOperand(3);
24903 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24907 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24908 if (Flags.getNode()) {
24909 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24910 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24917 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24918 SelectionDAG &DAG) {
24919 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24920 // optimize away operation when it's from a constant.
24922 // The general transformation is:
24923 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24924 // AND(VECTOR_CMP(x,y), constant2)
24925 // constant2 = UNARYOP(constant)
24927 // Early exit if this isn't a vector operation, the operand of the
24928 // unary operation isn't a bitwise AND, or if the sizes of the operations
24929 // aren't the same.
24930 EVT VT = N->getValueType(0);
24931 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24932 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24933 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24936 // Now check that the other operand of the AND is a constant. We could
24937 // make the transformation for non-constant splats as well, but it's unclear
24938 // that would be a benefit as it would not eliminate any operations, just
24939 // perform one more step in scalar code before moving to the vector unit.
24940 if (BuildVectorSDNode *BV =
24941 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24942 // Bail out if the vector isn't a constant.
24943 if (!BV->isConstant())
24946 // Everything checks out. Build up the new and improved node.
24948 EVT IntVT = BV->getValueType(0);
24949 // Create a new constant of the appropriate type for the transformed
24951 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24952 // The AND node needs bitcasts to/from an integer vector type around it.
24953 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24954 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24955 N->getOperand(0)->getOperand(0), MaskConst);
24956 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24963 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24964 const X86TargetLowering *XTLI) {
24965 // First try to optimize away the conversion entirely when it's
24966 // conditionally from a constant. Vectors only.
24967 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24968 if (Res != SDValue())
24971 // Now move on to more general possibilities.
24972 SDValue Op0 = N->getOperand(0);
24973 EVT InVT = Op0->getValueType(0);
24975 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24976 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24978 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24979 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24980 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24983 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24984 // a 32-bit target where SSE doesn't support i64->FP operations.
24985 if (Op0.getOpcode() == ISD::LOAD) {
24986 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24987 EVT VT = Ld->getValueType(0);
24988 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24989 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24990 !XTLI->getSubtarget()->is64Bit() &&
24992 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24993 Ld->getChain(), Op0, DAG);
24994 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25001 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25002 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25003 X86TargetLowering::DAGCombinerInfo &DCI) {
25004 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25005 // the result is either zero or one (depending on the input carry bit).
25006 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25007 if (X86::isZeroNode(N->getOperand(0)) &&
25008 X86::isZeroNode(N->getOperand(1)) &&
25009 // We don't have a good way to replace an EFLAGS use, so only do this when
25011 SDValue(N, 1).use_empty()) {
25013 EVT VT = N->getValueType(0);
25014 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25015 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25016 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25017 DAG.getConstant(X86::COND_B,MVT::i8),
25019 DAG.getConstant(1, VT));
25020 return DCI.CombineTo(N, Res1, CarryOut);
25026 // fold (add Y, (sete X, 0)) -> adc 0, Y
25027 // (add Y, (setne X, 0)) -> sbb -1, Y
25028 // (sub (sete X, 0), Y) -> sbb 0, Y
25029 // (sub (setne X, 0), Y) -> adc -1, Y
25030 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25033 // Look through ZExts.
25034 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25035 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25038 SDValue SetCC = Ext.getOperand(0);
25039 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25042 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25043 if (CC != X86::COND_E && CC != X86::COND_NE)
25046 SDValue Cmp = SetCC.getOperand(1);
25047 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25048 !X86::isZeroNode(Cmp.getOperand(1)) ||
25049 !Cmp.getOperand(0).getValueType().isInteger())
25052 SDValue CmpOp0 = Cmp.getOperand(0);
25053 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25054 DAG.getConstant(1, CmpOp0.getValueType()));
25056 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25057 if (CC == X86::COND_NE)
25058 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25059 DL, OtherVal.getValueType(), OtherVal,
25060 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25061 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25062 DL, OtherVal.getValueType(), OtherVal,
25063 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25066 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25067 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25068 const X86Subtarget *Subtarget) {
25069 EVT VT = N->getValueType(0);
25070 SDValue Op0 = N->getOperand(0);
25071 SDValue Op1 = N->getOperand(1);
25073 // Try to synthesize horizontal adds from adds of shuffles.
25074 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25075 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25076 isHorizontalBinOp(Op0, Op1, true))
25077 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25079 return OptimizeConditionalInDecrement(N, DAG);
25082 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25083 const X86Subtarget *Subtarget) {
25084 SDValue Op0 = N->getOperand(0);
25085 SDValue Op1 = N->getOperand(1);
25087 // X86 can't encode an immediate LHS of a sub. See if we can push the
25088 // negation into a preceding instruction.
25089 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25090 // If the RHS of the sub is a XOR with one use and a constant, invert the
25091 // immediate. Then add one to the LHS of the sub so we can turn
25092 // X-Y -> X+~Y+1, saving one register.
25093 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25094 isa<ConstantSDNode>(Op1.getOperand(1))) {
25095 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25096 EVT VT = Op0.getValueType();
25097 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25099 DAG.getConstant(~XorC, VT));
25100 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25101 DAG.getConstant(C->getAPIntValue()+1, VT));
25105 // Try to synthesize horizontal adds from adds of shuffles.
25106 EVT VT = N->getValueType(0);
25107 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25108 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25109 isHorizontalBinOp(Op0, Op1, true))
25110 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25112 return OptimizeConditionalInDecrement(N, DAG);
25115 /// performVZEXTCombine - Performs build vector combines
25116 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25117 TargetLowering::DAGCombinerInfo &DCI,
25118 const X86Subtarget *Subtarget) {
25120 MVT VT = N->getSimpleValueType(0);
25121 SDValue Op = N->getOperand(0);
25122 MVT OpVT = Op.getSimpleValueType();
25123 MVT OpEltVT = OpVT.getVectorElementType();
25124 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25126 // (vzext (bitcast (vzext (x)) -> (vzext x)
25128 while (V.getOpcode() == ISD::BITCAST)
25129 V = V.getOperand(0);
25131 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25132 MVT InnerVT = V.getSimpleValueType();
25133 MVT InnerEltVT = InnerVT.getVectorElementType();
25135 // If the element sizes match exactly, we can just do one larger vzext. This
25136 // is always an exact type match as vzext operates on integer types.
25137 if (OpEltVT == InnerEltVT) {
25138 assert(OpVT == InnerVT && "Types must match for vzext!");
25139 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25142 // The only other way we can combine them is if only a single element of the
25143 // inner vzext is used in the input to the outer vzext.
25144 if (InnerEltVT.getSizeInBits() < InputBits)
25147 // In this case, the inner vzext is completely dead because we're going to
25148 // only look at bits inside of the low element. Just do the outer vzext on
25149 // a bitcast of the input to the inner.
25150 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25151 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25154 // Check if we can bypass extracting and re-inserting an element of an input
25155 // vector. Essentialy:
25156 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25157 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25158 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25159 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25160 SDValue ExtractedV = V.getOperand(0);
25161 SDValue OrigV = ExtractedV.getOperand(0);
25162 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25163 if (ExtractIdx->getZExtValue() == 0) {
25164 MVT OrigVT = OrigV.getSimpleValueType();
25165 // Extract a subvector if necessary...
25166 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25167 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25168 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25169 OrigVT.getVectorNumElements() / Ratio);
25170 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25171 DAG.getIntPtrConstant(0));
25173 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25174 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25181 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25182 DAGCombinerInfo &DCI) const {
25183 SelectionDAG &DAG = DCI.DAG;
25184 switch (N->getOpcode()) {
25186 case ISD::EXTRACT_VECTOR_ELT:
25187 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25190 case X86ISD::SHRUNKBLEND:
25191 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25192 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25193 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25194 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25195 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25196 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25199 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25200 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25201 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25202 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25203 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25204 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25205 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25206 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25207 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25209 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25211 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25212 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25213 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25214 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25215 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25216 case ISD::ANY_EXTEND:
25217 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25218 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25219 case ISD::SIGN_EXTEND_INREG:
25220 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25221 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25222 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25223 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25224 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25225 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25226 case X86ISD::SHUFP: // Handle all target specific shuffles
25227 case X86ISD::PALIGNR:
25228 case X86ISD::UNPCKH:
25229 case X86ISD::UNPCKL:
25230 case X86ISD::MOVHLPS:
25231 case X86ISD::MOVLHPS:
25232 case X86ISD::PSHUFB:
25233 case X86ISD::PSHUFD:
25234 case X86ISD::PSHUFHW:
25235 case X86ISD::PSHUFLW:
25236 case X86ISD::MOVSS:
25237 case X86ISD::MOVSD:
25238 case X86ISD::VPERMILPI:
25239 case X86ISD::VPERM2X128:
25240 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25241 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25242 case ISD::INTRINSIC_WO_CHAIN:
25243 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25244 case X86ISD::INSERTPS:
25245 return PerformINSERTPSCombine(N, DAG, Subtarget);
25246 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25252 /// isTypeDesirableForOp - Return true if the target has native support for
25253 /// the specified value type and it is 'desirable' to use the type for the
25254 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25255 /// instruction encodings are longer and some i16 instructions are slow.
25256 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25257 if (!isTypeLegal(VT))
25259 if (VT != MVT::i16)
25266 case ISD::SIGN_EXTEND:
25267 case ISD::ZERO_EXTEND:
25268 case ISD::ANY_EXTEND:
25281 /// IsDesirableToPromoteOp - This method query the target whether it is
25282 /// beneficial for dag combiner to promote the specified node. If true, it
25283 /// should return the desired promotion type by reference.
25284 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25285 EVT VT = Op.getValueType();
25286 if (VT != MVT::i16)
25289 bool Promote = false;
25290 bool Commute = false;
25291 switch (Op.getOpcode()) {
25294 LoadSDNode *LD = cast<LoadSDNode>(Op);
25295 // If the non-extending load has a single use and it's not live out, then it
25296 // might be folded.
25297 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25298 Op.hasOneUse()*/) {
25299 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25300 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25301 // The only case where we'd want to promote LOAD (rather then it being
25302 // promoted as an operand is when it's only use is liveout.
25303 if (UI->getOpcode() != ISD::CopyToReg)
25310 case ISD::SIGN_EXTEND:
25311 case ISD::ZERO_EXTEND:
25312 case ISD::ANY_EXTEND:
25317 SDValue N0 = Op.getOperand(0);
25318 // Look out for (store (shl (load), x)).
25319 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25332 SDValue N0 = Op.getOperand(0);
25333 SDValue N1 = Op.getOperand(1);
25334 if (!Commute && MayFoldLoad(N1))
25336 // Avoid disabling potential load folding opportunities.
25337 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25339 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25349 //===----------------------------------------------------------------------===//
25350 // X86 Inline Assembly Support
25351 //===----------------------------------------------------------------------===//
25354 // Helper to match a string separated by whitespace.
25355 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25356 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25358 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25359 StringRef piece(*args[i]);
25360 if (!s.startswith(piece)) // Check if the piece matches.
25363 s = s.substr(piece.size());
25364 StringRef::size_type pos = s.find_first_not_of(" \t");
25365 if (pos == 0) // We matched a prefix.
25373 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25376 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25378 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25379 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25380 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25381 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25383 if (AsmPieces.size() == 3)
25385 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25392 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25393 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25395 std::string AsmStr = IA->getAsmString();
25397 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25398 if (!Ty || Ty->getBitWidth() % 16 != 0)
25401 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25402 SmallVector<StringRef, 4> AsmPieces;
25403 SplitString(AsmStr, AsmPieces, ";\n");
25405 switch (AsmPieces.size()) {
25406 default: return false;
25408 // FIXME: this should verify that we are targeting a 486 or better. If not,
25409 // we will turn this bswap into something that will be lowered to logical
25410 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25411 // lower so don't worry about this.
25413 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25414 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25415 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25416 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25417 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25418 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25419 // No need to check constraints, nothing other than the equivalent of
25420 // "=r,0" would be valid here.
25421 return IntrinsicLowering::LowerToByteSwap(CI);
25424 // rorw $$8, ${0:w} --> llvm.bswap.i16
25425 if (CI->getType()->isIntegerTy(16) &&
25426 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25427 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25428 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25430 const std::string &ConstraintsStr = IA->getConstraintString();
25431 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25432 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25433 if (clobbersFlagRegisters(AsmPieces))
25434 return IntrinsicLowering::LowerToByteSwap(CI);
25438 if (CI->getType()->isIntegerTy(32) &&
25439 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25440 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25441 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25442 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25444 const std::string &ConstraintsStr = IA->getConstraintString();
25445 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25446 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25447 if (clobbersFlagRegisters(AsmPieces))
25448 return IntrinsicLowering::LowerToByteSwap(CI);
25451 if (CI->getType()->isIntegerTy(64)) {
25452 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25453 if (Constraints.size() >= 2 &&
25454 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25455 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25456 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25457 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25458 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25459 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25460 return IntrinsicLowering::LowerToByteSwap(CI);
25468 /// getConstraintType - Given a constraint letter, return the type of
25469 /// constraint it is for this target.
25470 X86TargetLowering::ConstraintType
25471 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25472 if (Constraint.size() == 1) {
25473 switch (Constraint[0]) {
25484 return C_RegisterClass;
25508 return TargetLowering::getConstraintType(Constraint);
25511 /// Examine constraint type and operand type and determine a weight value.
25512 /// This object must already have been set up with the operand type
25513 /// and the current alternative constraint selected.
25514 TargetLowering::ConstraintWeight
25515 X86TargetLowering::getSingleConstraintMatchWeight(
25516 AsmOperandInfo &info, const char *constraint) const {
25517 ConstraintWeight weight = CW_Invalid;
25518 Value *CallOperandVal = info.CallOperandVal;
25519 // If we don't have a value, we can't do a match,
25520 // but allow it at the lowest weight.
25521 if (!CallOperandVal)
25523 Type *type = CallOperandVal->getType();
25524 // Look at the constraint type.
25525 switch (*constraint) {
25527 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25538 if (CallOperandVal->getType()->isIntegerTy())
25539 weight = CW_SpecificReg;
25544 if (type->isFloatingPointTy())
25545 weight = CW_SpecificReg;
25548 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25549 weight = CW_SpecificReg;
25553 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25554 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25555 weight = CW_Register;
25558 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25559 if (C->getZExtValue() <= 31)
25560 weight = CW_Constant;
25564 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25565 if (C->getZExtValue() <= 63)
25566 weight = CW_Constant;
25570 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25571 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25572 weight = CW_Constant;
25576 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25577 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25578 weight = CW_Constant;
25582 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25583 if (C->getZExtValue() <= 3)
25584 weight = CW_Constant;
25588 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25589 if (C->getZExtValue() <= 0xff)
25590 weight = CW_Constant;
25595 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25596 weight = CW_Constant;
25600 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25601 if ((C->getSExtValue() >= -0x80000000LL) &&
25602 (C->getSExtValue() <= 0x7fffffffLL))
25603 weight = CW_Constant;
25607 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25608 if (C->getZExtValue() <= 0xffffffff)
25609 weight = CW_Constant;
25616 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25617 /// with another that has more specific requirements based on the type of the
25618 /// corresponding operand.
25619 const char *X86TargetLowering::
25620 LowerXConstraint(EVT ConstraintVT) const {
25621 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25622 // 'f' like normal targets.
25623 if (ConstraintVT.isFloatingPoint()) {
25624 if (Subtarget->hasSSE2())
25626 if (Subtarget->hasSSE1())
25630 return TargetLowering::LowerXConstraint(ConstraintVT);
25633 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25634 /// vector. If it is invalid, don't add anything to Ops.
25635 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25636 std::string &Constraint,
25637 std::vector<SDValue>&Ops,
25638 SelectionDAG &DAG) const {
25641 // Only support length 1 constraints for now.
25642 if (Constraint.length() > 1) return;
25644 char ConstraintLetter = Constraint[0];
25645 switch (ConstraintLetter) {
25648 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25649 if (C->getZExtValue() <= 31) {
25650 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25656 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25657 if (C->getZExtValue() <= 63) {
25658 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25664 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25665 if (isInt<8>(C->getSExtValue())) {
25666 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25672 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25673 if (C->getZExtValue() <= 255) {
25674 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25680 // 32-bit signed value
25681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25682 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25683 C->getSExtValue())) {
25684 // Widen to 64 bits here to get it sign extended.
25685 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25688 // FIXME gcc accepts some relocatable values here too, but only in certain
25689 // memory models; it's complicated.
25694 // 32-bit unsigned value
25695 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25696 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25697 C->getZExtValue())) {
25698 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25702 // FIXME gcc accepts some relocatable values here too, but only in certain
25703 // memory models; it's complicated.
25707 // Literal immediates are always ok.
25708 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25709 // Widen to 64 bits here to get it sign extended.
25710 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25714 // In any sort of PIC mode addresses need to be computed at runtime by
25715 // adding in a register or some sort of table lookup. These can't
25716 // be used as immediates.
25717 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25720 // If we are in non-pic codegen mode, we allow the address of a global (with
25721 // an optional displacement) to be used with 'i'.
25722 GlobalAddressSDNode *GA = nullptr;
25723 int64_t Offset = 0;
25725 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25727 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25728 Offset += GA->getOffset();
25730 } else if (Op.getOpcode() == ISD::ADD) {
25731 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25732 Offset += C->getZExtValue();
25733 Op = Op.getOperand(0);
25736 } else if (Op.getOpcode() == ISD::SUB) {
25737 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25738 Offset += -C->getZExtValue();
25739 Op = Op.getOperand(0);
25744 // Otherwise, this isn't something we can handle, reject it.
25748 const GlobalValue *GV = GA->getGlobal();
25749 // If we require an extra load to get this address, as in PIC mode, we
25750 // can't accept it.
25751 if (isGlobalStubReference(
25752 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25755 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25756 GA->getValueType(0), Offset);
25761 if (Result.getNode()) {
25762 Ops.push_back(Result);
25765 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25768 std::pair<unsigned, const TargetRegisterClass*>
25769 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25771 // First, see if this is a constraint that directly corresponds to an LLVM
25773 if (Constraint.size() == 1) {
25774 // GCC Constraint Letters
25775 switch (Constraint[0]) {
25777 // TODO: Slight differences here in allocation order and leaving
25778 // RIP in the class. Do they matter any more here than they do
25779 // in the normal allocation?
25780 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25781 if (Subtarget->is64Bit()) {
25782 if (VT == MVT::i32 || VT == MVT::f32)
25783 return std::make_pair(0U, &X86::GR32RegClass);
25784 if (VT == MVT::i16)
25785 return std::make_pair(0U, &X86::GR16RegClass);
25786 if (VT == MVT::i8 || VT == MVT::i1)
25787 return std::make_pair(0U, &X86::GR8RegClass);
25788 if (VT == MVT::i64 || VT == MVT::f64)
25789 return std::make_pair(0U, &X86::GR64RegClass);
25792 // 32-bit fallthrough
25793 case 'Q': // Q_REGS
25794 if (VT == MVT::i32 || VT == MVT::f32)
25795 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25796 if (VT == MVT::i16)
25797 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25798 if (VT == MVT::i8 || VT == MVT::i1)
25799 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25800 if (VT == MVT::i64)
25801 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25803 case 'r': // GENERAL_REGS
25804 case 'l': // INDEX_REGS
25805 if (VT == MVT::i8 || VT == MVT::i1)
25806 return std::make_pair(0U, &X86::GR8RegClass);
25807 if (VT == MVT::i16)
25808 return std::make_pair(0U, &X86::GR16RegClass);
25809 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25810 return std::make_pair(0U, &X86::GR32RegClass);
25811 return std::make_pair(0U, &X86::GR64RegClass);
25812 case 'R': // LEGACY_REGS
25813 if (VT == MVT::i8 || VT == MVT::i1)
25814 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25815 if (VT == MVT::i16)
25816 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25817 if (VT == MVT::i32 || !Subtarget->is64Bit())
25818 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25819 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25820 case 'f': // FP Stack registers.
25821 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25822 // value to the correct fpstack register class.
25823 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25824 return std::make_pair(0U, &X86::RFP32RegClass);
25825 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25826 return std::make_pair(0U, &X86::RFP64RegClass);
25827 return std::make_pair(0U, &X86::RFP80RegClass);
25828 case 'y': // MMX_REGS if MMX allowed.
25829 if (!Subtarget->hasMMX()) break;
25830 return std::make_pair(0U, &X86::VR64RegClass);
25831 case 'Y': // SSE_REGS if SSE2 allowed
25832 if (!Subtarget->hasSSE2()) break;
25834 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25835 if (!Subtarget->hasSSE1()) break;
25837 switch (VT.SimpleTy) {
25839 // Scalar SSE types.
25842 return std::make_pair(0U, &X86::FR32RegClass);
25845 return std::make_pair(0U, &X86::FR64RegClass);
25853 return std::make_pair(0U, &X86::VR128RegClass);
25861 return std::make_pair(0U, &X86::VR256RegClass);
25866 return std::make_pair(0U, &X86::VR512RegClass);
25872 // Use the default implementation in TargetLowering to convert the register
25873 // constraint into a member of a register class.
25874 std::pair<unsigned, const TargetRegisterClass*> Res;
25875 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25877 // Not found as a standard register?
25879 // Map st(0) -> st(7) -> ST0
25880 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25881 tolower(Constraint[1]) == 's' &&
25882 tolower(Constraint[2]) == 't' &&
25883 Constraint[3] == '(' &&
25884 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25885 Constraint[5] == ')' &&
25886 Constraint[6] == '}') {
25888 Res.first = X86::FP0+Constraint[4]-'0';
25889 Res.second = &X86::RFP80RegClass;
25893 // GCC allows "st(0)" to be called just plain "st".
25894 if (StringRef("{st}").equals_lower(Constraint)) {
25895 Res.first = X86::FP0;
25896 Res.second = &X86::RFP80RegClass;
25901 if (StringRef("{flags}").equals_lower(Constraint)) {
25902 Res.first = X86::EFLAGS;
25903 Res.second = &X86::CCRRegClass;
25907 // 'A' means EAX + EDX.
25908 if (Constraint == "A") {
25909 Res.first = X86::EAX;
25910 Res.second = &X86::GR32_ADRegClass;
25916 // Otherwise, check to see if this is a register class of the wrong value
25917 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25918 // turn into {ax},{dx}.
25919 if (Res.second->hasType(VT))
25920 return Res; // Correct type already, nothing to do.
25922 // All of the single-register GCC register classes map their values onto
25923 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25924 // really want an 8-bit or 32-bit register, map to the appropriate register
25925 // class and return the appropriate register.
25926 if (Res.second == &X86::GR16RegClass) {
25927 if (VT == MVT::i8 || VT == MVT::i1) {
25928 unsigned DestReg = 0;
25929 switch (Res.first) {
25931 case X86::AX: DestReg = X86::AL; break;
25932 case X86::DX: DestReg = X86::DL; break;
25933 case X86::CX: DestReg = X86::CL; break;
25934 case X86::BX: DestReg = X86::BL; break;
25937 Res.first = DestReg;
25938 Res.second = &X86::GR8RegClass;
25940 } else if (VT == MVT::i32 || VT == MVT::f32) {
25941 unsigned DestReg = 0;
25942 switch (Res.first) {
25944 case X86::AX: DestReg = X86::EAX; break;
25945 case X86::DX: DestReg = X86::EDX; break;
25946 case X86::CX: DestReg = X86::ECX; break;
25947 case X86::BX: DestReg = X86::EBX; break;
25948 case X86::SI: DestReg = X86::ESI; break;
25949 case X86::DI: DestReg = X86::EDI; break;
25950 case X86::BP: DestReg = X86::EBP; break;
25951 case X86::SP: DestReg = X86::ESP; break;
25954 Res.first = DestReg;
25955 Res.second = &X86::GR32RegClass;
25957 } else if (VT == MVT::i64 || VT == MVT::f64) {
25958 unsigned DestReg = 0;
25959 switch (Res.first) {
25961 case X86::AX: DestReg = X86::RAX; break;
25962 case X86::DX: DestReg = X86::RDX; break;
25963 case X86::CX: DestReg = X86::RCX; break;
25964 case X86::BX: DestReg = X86::RBX; break;
25965 case X86::SI: DestReg = X86::RSI; break;
25966 case X86::DI: DestReg = X86::RDI; break;
25967 case X86::BP: DestReg = X86::RBP; break;
25968 case X86::SP: DestReg = X86::RSP; break;
25971 Res.first = DestReg;
25972 Res.second = &X86::GR64RegClass;
25975 } else if (Res.second == &X86::FR32RegClass ||
25976 Res.second == &X86::FR64RegClass ||
25977 Res.second == &X86::VR128RegClass ||
25978 Res.second == &X86::VR256RegClass ||
25979 Res.second == &X86::FR32XRegClass ||
25980 Res.second == &X86::FR64XRegClass ||
25981 Res.second == &X86::VR128XRegClass ||
25982 Res.second == &X86::VR256XRegClass ||
25983 Res.second == &X86::VR512RegClass) {
25984 // Handle references to XMM physical registers that got mapped into the
25985 // wrong class. This can happen with constraints like {xmm0} where the
25986 // target independent register mapper will just pick the first match it can
25987 // find, ignoring the required type.
25989 if (VT == MVT::f32 || VT == MVT::i32)
25990 Res.second = &X86::FR32RegClass;
25991 else if (VT == MVT::f64 || VT == MVT::i64)
25992 Res.second = &X86::FR64RegClass;
25993 else if (X86::VR128RegClass.hasType(VT))
25994 Res.second = &X86::VR128RegClass;
25995 else if (X86::VR256RegClass.hasType(VT))
25996 Res.second = &X86::VR256RegClass;
25997 else if (X86::VR512RegClass.hasType(VT))
25998 Res.second = &X86::VR512RegClass;
26004 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26006 // Scaling factors are not free at all.
26007 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26008 // will take 2 allocations in the out of order engine instead of 1
26009 // for plain addressing mode, i.e. inst (reg1).
26011 // vaddps (%rsi,%drx), %ymm0, %ymm1
26012 // Requires two allocations (one for the load, one for the computation)
26014 // vaddps (%rsi), %ymm0, %ymm1
26015 // Requires just 1 allocation, i.e., freeing allocations for other operations
26016 // and having less micro operations to execute.
26018 // For some X86 architectures, this is even worse because for instance for
26019 // stores, the complex addressing mode forces the instruction to use the
26020 // "load" ports instead of the dedicated "store" port.
26021 // E.g., on Haswell:
26022 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26023 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26024 if (isLegalAddressingMode(AM, Ty))
26025 // Scale represents reg2 * scale, thus account for 1
26026 // as soon as we use a second register.
26027 return AM.Scale != 0;
26031 bool X86TargetLowering::isTargetFTOL() const {
26032 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();