1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 // Forward declarations.
71 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
74 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
75 const X86Subtarget &STI)
76 : TargetLowering(TM), Subtarget(&STI) {
77 X86ScalarSSEf64 = Subtarget->hasSSE2();
78 X86ScalarSSEf32 = Subtarget->hasSSE1();
81 // Set up the TargetLowering object.
82 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
84 // X86 is weird. It always uses i8 for shift amounts and setcc results.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // For 64-bit, since we have so many registers, use the ILP scheduler.
90 // For 32-bit, use the register pressure specific scheduling.
91 // For Atom, always use ILP scheduling.
92 if (Subtarget->isAtom())
93 setSchedulingPreference(Sched::ILP);
94 else if (Subtarget->is64Bit())
95 setSchedulingPreference(Sched::ILP);
97 setSchedulingPreference(Sched::RegPressure);
98 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
99 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
101 // Bypass expensive divides on Atom when compiling with O2.
102 if (TM.getOptLevel() >= CodeGenOpt::Default) {
103 if (Subtarget->hasSlowDivide32())
104 addBypassSlowDiv(32, 8);
105 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
106 addBypassSlowDiv(64, 16);
109 if (Subtarget->isTargetKnownWindowsMSVC()) {
110 // Setup Windows compiler runtime calls.
111 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
112 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
113 setLibcallName(RTLIB::SREM_I64, "_allrem");
114 setLibcallName(RTLIB::UREM_I64, "_aullrem");
115 setLibcallName(RTLIB::MUL_I64, "_allmul");
116 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
117 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
118 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
119 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
120 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
122 // The _ftol2 runtime function has an unusual calling conv, which
123 // is modeled by a special pseudo-instruction.
124 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
125 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
126 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
127 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
130 if (Subtarget->isTargetDarwin()) {
131 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
132 setUseUnderscoreSetJmp(false);
133 setUseUnderscoreLongJmp(false);
134 } else if (Subtarget->isTargetWindowsGNU()) {
135 // MS runtime is weird: it exports _setjmp, but longjmp!
136 setUseUnderscoreSetJmp(true);
137 setUseUnderscoreLongJmp(false);
139 setUseUnderscoreSetJmp(true);
140 setUseUnderscoreLongJmp(true);
143 // Set up the register classes.
144 addRegisterClass(MVT::i8, &X86::GR8RegClass);
145 addRegisterClass(MVT::i16, &X86::GR16RegClass);
146 addRegisterClass(MVT::i32, &X86::GR32RegClass);
147 if (Subtarget->is64Bit())
148 addRegisterClass(MVT::i64, &X86::GR64RegClass);
150 for (MVT VT : MVT::integer_valuetypes())
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
153 // We don't accept any truncstore of integer registers.
154 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
155 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
156 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
157 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
158 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
159 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
163 // SETOEQ and SETUNE require checking two conditions.
164 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
165 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
166 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
167 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
168 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
169 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
171 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
173 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
174 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
175 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
177 if (Subtarget->is64Bit()) {
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
179 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
180 } else if (!Subtarget->useSoftFloat()) {
181 // We have an algorithm for SSE2->double, and we turn this into a
182 // 64-bit FILD followed by conditional FADD for other targets.
183 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
184 // We have an algorithm for SSE2, and we turn this into a 64-bit
185 // FILD for other targets.
186 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
189 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
191 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
192 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
194 if (!Subtarget->useSoftFloat()) {
195 // SSE has no i16 to fp conversion, only i32
196 if (X86ScalarSSEf32) {
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
198 // f32 and f64 cases are Legal, f80 case is not
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
202 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
206 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
209 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
210 // are Legal, f80 is custom lowered.
211 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
214 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
216 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
219 if (X86ScalarSSEf32) {
220 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
221 // f32 and f64 cases are Legal, f80 case is not
222 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
225 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
228 // Handle FP_TO_UINT by promoting the destination to a larger signed
230 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
234 if (Subtarget->is64Bit()) {
235 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
237 } else if (!Subtarget->useSoftFloat()) {
238 // Since AVX is a superset of SSE3, only check for SSE here.
239 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
240 // Expand FP_TO_UINT into a select.
241 // FIXME: We would like to use a Custom expander here eventually to do
242 // the optimal thing for SSE vs. the default expansion in the legalizer.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
250 if (isTargetFTOL()) {
251 // Use the _ftol2 runtime function, which has a pseudo-instruction
252 // to handle its weird calling convention.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
256 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
257 if (!X86ScalarSSEf64) {
258 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
259 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
260 if (Subtarget->is64Bit()) {
261 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
262 // Without SSE, i64->f64 goes through memory.
263 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
267 // Scalar integer divide and remainder are lowered to use operations that
268 // produce two results, to match the available instructions. This exposes
269 // the two-result form to trivial CSE, which is able to combine x/y and x%y
270 // into a single instruction.
272 // Scalar integer multiply-high is also lowered to use two-result
273 // operations, to match the available instructions. However, plain multiply
274 // (low) operations are left as Legal, as there are single-result
275 // instructions for this in x86. Using the two-result multiply instructions
276 // when both high and low results are needed must be arranged by dagcombine.
277 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
279 setOperationAction(ISD::MULHS, VT, Expand);
280 setOperationAction(ISD::MULHU, VT, Expand);
281 setOperationAction(ISD::SDIV, VT, Expand);
282 setOperationAction(ISD::UDIV, VT, Expand);
283 setOperationAction(ISD::SREM, VT, Expand);
284 setOperationAction(ISD::UREM, VT, Expand);
286 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
287 setOperationAction(ISD::ADDC, VT, Custom);
288 setOperationAction(ISD::ADDE, VT, Custom);
289 setOperationAction(ISD::SUBC, VT, Custom);
290 setOperationAction(ISD::SUBE, VT, Custom);
293 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
294 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
295 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
296 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
298 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
309 if (Subtarget->is64Bit())
310 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
314 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
315 setOperationAction(ISD::FREM , MVT::f32 , Expand);
316 setOperationAction(ISD::FREM , MVT::f64 , Expand);
317 setOperationAction(ISD::FREM , MVT::f80 , Expand);
318 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
320 // Promote the i8 variants and force them on up to i32 which has a shorter
322 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
323 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
324 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
325 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
326 if (Subtarget->hasBMI()) {
327 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
328 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
329 if (Subtarget->is64Bit())
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
332 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
333 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
334 if (Subtarget->is64Bit())
335 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
338 if (Subtarget->hasLZCNT()) {
339 // When promoting the i8 variants, force them to i32 for a shorter
341 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
342 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
343 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
344 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
347 if (Subtarget->is64Bit())
348 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
350 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
351 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
352 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
353 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
355 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
356 if (Subtarget->is64Bit()) {
357 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
362 // Special handling for half-precision floating point conversions.
363 // If we don't have F16C support, then lower half float conversions
364 // into library calls.
365 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
366 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
367 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
370 // There's never any support for operations beyond MVT::f32.
371 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
372 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
374 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
376 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
377 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
378 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
379 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
380 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
381 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
383 if (Subtarget->hasPOPCNT()) {
384 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
386 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
387 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
388 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
393 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
395 if (!Subtarget->hasMOVBE())
396 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
398 // These should be promoted to a larger select which is supported.
399 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
400 // X86 wants to expand cmov itself.
401 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
402 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
403 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
404 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
405 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
406 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
407 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
408 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
409 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
410 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
411 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
412 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
413 if (Subtarget->is64Bit()) {
414 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
417 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
418 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
419 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
420 // support continuation, user-level threading, and etc.. As a result, no
421 // other SjLj exception interfaces are implemented and please don't build
422 // your own exception handling based on them.
423 // LLVM/Clang supports zero-cost DWARF exception handling.
424 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
425 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
428 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
429 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
430 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
431 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
434 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
435 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
436 if (Subtarget->is64Bit()) {
437 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
438 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
439 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
440 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
443 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
444 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
447 if (Subtarget->is64Bit()) {
448 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
453 if (Subtarget->hasSSE1())
454 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
456 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
458 // Expand certain atomics
459 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
461 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
462 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
463 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
466 if (Subtarget->hasCmpxchg16b()) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
470 // FIXME - use subtarget debug flags
471 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
472 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
473 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
476 if (Subtarget->is64Bit()) {
477 setExceptionPointerRegister(X86::RAX);
478 setExceptionSelectorRegister(X86::RDX);
480 setExceptionPointerRegister(X86::EAX);
481 setExceptionSelectorRegister(X86::EDX);
483 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
484 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
486 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
487 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
489 setOperationAction(ISD::TRAP, MVT::Other, Legal);
490 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
492 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
493 setOperationAction(ISD::VASTART , MVT::Other, Custom);
494 setOperationAction(ISD::VAEND , MVT::Other, Expand);
495 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
496 // TargetInfo::X86_64ABIBuiltinVaList
497 setOperationAction(ISD::VAARG , MVT::Other, Custom);
498 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
500 // TargetInfo::CharPtrBuiltinVaList
501 setOperationAction(ISD::VAARG , MVT::Other, Expand);
502 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
505 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
506 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
508 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
510 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
511 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
512 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
514 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
515 // f32 and f64 use SSE.
516 // Set up the FP register classes.
517 addRegisterClass(MVT::f32, &X86::FR32RegClass);
518 addRegisterClass(MVT::f64, &X86::FR64RegClass);
520 // Use ANDPD to simulate FABS.
521 setOperationAction(ISD::FABS , MVT::f64, Custom);
522 setOperationAction(ISD::FABS , MVT::f32, Custom);
524 // Use XORP to simulate FNEG.
525 setOperationAction(ISD::FNEG , MVT::f64, Custom);
526 setOperationAction(ISD::FNEG , MVT::f32, Custom);
528 // Use ANDPD and ORPD to simulate FCOPYSIGN.
529 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
530 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
532 // Lower this to FGETSIGNx86 plus an AND.
533 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
534 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
536 // We don't support sin/cos/fmod
537 setOperationAction(ISD::FSIN , MVT::f64, Expand);
538 setOperationAction(ISD::FCOS , MVT::f64, Expand);
539 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
540 setOperationAction(ISD::FSIN , MVT::f32, Expand);
541 setOperationAction(ISD::FCOS , MVT::f32, Expand);
542 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
544 // Expand FP immediates into loads from the stack, except for the special
546 addLegalFPImmediate(APFloat(+0.0)); // xorpd
547 addLegalFPImmediate(APFloat(+0.0f)); // xorps
548 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
549 // Use SSE for f32, x87 for f64.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, &X86::FR32RegClass);
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
554 // Use ANDPS to simulate FABS.
555 setOperationAction(ISD::FABS , MVT::f32, Custom);
557 // Use XORP to simulate FNEG.
558 setOperationAction(ISD::FNEG , MVT::f32, Custom);
560 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
562 // Use ANDPS and ORPS to simulate FCOPYSIGN.
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
566 // We don't support sin/cos/fmod
567 setOperationAction(ISD::FSIN , MVT::f32, Expand);
568 setOperationAction(ISD::FCOS , MVT::f32, Expand);
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
571 // Special cases we handle for FP constants.
572 addLegalFPImmediate(APFloat(+0.0f)); // xorps
573 addLegalFPImmediate(APFloat(+0.0)); // FLD0
574 addLegalFPImmediate(APFloat(+1.0)); // FLD1
575 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
576 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
578 if (!TM.Options.UnsafeFPMath) {
579 setOperationAction(ISD::FSIN , MVT::f64, Expand);
580 setOperationAction(ISD::FCOS , MVT::f64, Expand);
581 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
583 } else if (!Subtarget->useSoftFloat()) {
584 // f32 and f64 in x87.
585 // Set up the FP register classes.
586 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
587 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
589 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
590 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
591 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
592 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
594 if (!TM.Options.UnsafeFPMath) {
595 setOperationAction(ISD::FSIN , MVT::f64, Expand);
596 setOperationAction(ISD::FSIN , MVT::f32, Expand);
597 setOperationAction(ISD::FCOS , MVT::f64, Expand);
598 setOperationAction(ISD::FCOS , MVT::f32, Expand);
599 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
600 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
602 addLegalFPImmediate(APFloat(+0.0)); // FLD0
603 addLegalFPImmediate(APFloat(+1.0)); // FLD1
604 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
605 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
606 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
607 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
608 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
609 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
612 // We don't support FMA.
613 setOperationAction(ISD::FMA, MVT::f64, Expand);
614 setOperationAction(ISD::FMA, MVT::f32, Expand);
616 // Long double always uses X87.
617 if (!Subtarget->useSoftFloat()) {
618 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
619 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
620 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
622 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
623 addLegalFPImmediate(TmpFlt); // FLD0
625 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
628 APFloat TmpFlt2(+1.0);
629 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
631 addLegalFPImmediate(TmpFlt2); // FLD1
632 TmpFlt2.changeSign();
633 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
636 if (!TM.Options.UnsafeFPMath) {
637 setOperationAction(ISD::FSIN , MVT::f80, Expand);
638 setOperationAction(ISD::FCOS , MVT::f80, Expand);
639 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
642 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
643 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
644 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
645 setOperationAction(ISD::FRINT, MVT::f80, Expand);
646 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
647 setOperationAction(ISD::FMA, MVT::f80, Expand);
650 // Always use a library call for pow.
651 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
652 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
653 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
655 setOperationAction(ISD::FLOG, MVT::f80, Expand);
656 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
657 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
658 setOperationAction(ISD::FEXP, MVT::f80, Expand);
659 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
660 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
661 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
663 // First set operation action for all vector types to either promote
664 // (for widening) or expand (for scalarization). Then we will selectively
665 // turn on ones that can be effectively codegen'd.
666 for (MVT VT : MVT::vector_valuetypes()) {
667 setOperationAction(ISD::ADD , VT, Expand);
668 setOperationAction(ISD::SUB , VT, Expand);
669 setOperationAction(ISD::FADD, VT, Expand);
670 setOperationAction(ISD::FNEG, VT, Expand);
671 setOperationAction(ISD::FSUB, VT, Expand);
672 setOperationAction(ISD::MUL , VT, Expand);
673 setOperationAction(ISD::FMUL, VT, Expand);
674 setOperationAction(ISD::SDIV, VT, Expand);
675 setOperationAction(ISD::UDIV, VT, Expand);
676 setOperationAction(ISD::FDIV, VT, Expand);
677 setOperationAction(ISD::SREM, VT, Expand);
678 setOperationAction(ISD::UREM, VT, Expand);
679 setOperationAction(ISD::LOAD, VT, Expand);
680 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
682 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
683 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
684 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
685 setOperationAction(ISD::FABS, VT, Expand);
686 setOperationAction(ISD::FSIN, VT, Expand);
687 setOperationAction(ISD::FSINCOS, VT, Expand);
688 setOperationAction(ISD::FCOS, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FREM, VT, Expand);
691 setOperationAction(ISD::FMA, VT, Expand);
692 setOperationAction(ISD::FPOWI, VT, Expand);
693 setOperationAction(ISD::FSQRT, VT, Expand);
694 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
695 setOperationAction(ISD::FFLOOR, VT, Expand);
696 setOperationAction(ISD::FCEIL, VT, Expand);
697 setOperationAction(ISD::FTRUNC, VT, Expand);
698 setOperationAction(ISD::FRINT, VT, Expand);
699 setOperationAction(ISD::FNEARBYINT, VT, Expand);
700 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
701 setOperationAction(ISD::MULHS, VT, Expand);
702 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHU, VT, Expand);
704 setOperationAction(ISD::SDIVREM, VT, Expand);
705 setOperationAction(ISD::UDIVREM, VT, Expand);
706 setOperationAction(ISD::FPOW, VT, Expand);
707 setOperationAction(ISD::CTPOP, VT, Expand);
708 setOperationAction(ISD::CTTZ, VT, Expand);
709 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
710 setOperationAction(ISD::CTLZ, VT, Expand);
711 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::SHL, VT, Expand);
713 setOperationAction(ISD::SRA, VT, Expand);
714 setOperationAction(ISD::SRL, VT, Expand);
715 setOperationAction(ISD::ROTL, VT, Expand);
716 setOperationAction(ISD::ROTR, VT, Expand);
717 setOperationAction(ISD::BSWAP, VT, Expand);
718 setOperationAction(ISD::SETCC, VT, Expand);
719 setOperationAction(ISD::FLOG, VT, Expand);
720 setOperationAction(ISD::FLOG2, VT, Expand);
721 setOperationAction(ISD::FLOG10, VT, Expand);
722 setOperationAction(ISD::FEXP, VT, Expand);
723 setOperationAction(ISD::FEXP2, VT, Expand);
724 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
725 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
726 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
727 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
728 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
729 setOperationAction(ISD::TRUNCATE, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
731 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
732 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
733 setOperationAction(ISD::VSELECT, VT, Expand);
734 setOperationAction(ISD::SELECT_CC, VT, Expand);
735 for (MVT InnerVT : MVT::vector_valuetypes()) {
736 setTruncStoreAction(InnerVT, VT, Expand);
738 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
739 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
741 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
742 // types, we have to deal with them whether we ask for Expansion or not.
743 // Setting Expand causes its own optimisation problems though, so leave
745 if (VT.getVectorElementType() == MVT::i1)
746 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
748 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
749 // split/scalarized right now.
750 if (VT.getVectorElementType() == MVT::f16)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
755 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
756 // with -msoft-float, disable use of MMX as well.
757 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
758 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
759 // No operations on x86mmx supported, everything uses intrinsics.
762 // MMX-sized vectors (other than x86mmx) are expected to be expanded
763 // into smaller operations.
764 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
765 setOperationAction(ISD::MULHS, MMXTy, Expand);
766 setOperationAction(ISD::AND, MMXTy, Expand);
767 setOperationAction(ISD::OR, MMXTy, Expand);
768 setOperationAction(ISD::XOR, MMXTy, Expand);
769 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
770 setOperationAction(ISD::SELECT, MMXTy, Expand);
771 setOperationAction(ISD::BITCAST, MMXTy, Expand);
773 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
775 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
776 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
778 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
780 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
782 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
783 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
784 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
785 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
786 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
788 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
790 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
794 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
795 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
797 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
798 // registers cannot be used even for integer operations.
799 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
800 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
801 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
802 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
804 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
805 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
806 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
807 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
808 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
809 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
810 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
811 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
812 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
813 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
814 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
815 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
816 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
818 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
819 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
820 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
821 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
822 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
823 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
824 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
825 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
826 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
828 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
829 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
830 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
831 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
833 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
834 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
835 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
837 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
839 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
840 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
841 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
842 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
844 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
845 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
846 MVT VT = (MVT::SimpleValueType)i;
847 // Do not attempt to custom lower non-power-of-2 vectors
848 if (!isPowerOf2_32(VT.getVectorNumElements()))
850 // Do not attempt to custom lower non-128-bit vectors
851 if (!VT.is128BitVector())
853 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
854 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
855 setOperationAction(ISD::VSELECT, VT, Custom);
856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
859 // We support custom legalizing of sext and anyext loads for specific
860 // memory vector types which we can load as a scalar (or sequence of
861 // scalars) and extend in-register to a legal 128-bit vector type. For sext
862 // loads these must work with a single scalar load.
863 for (MVT VT : MVT::integer_vector_valuetypes()) {
864 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
865 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
866 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
867 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
868 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
869 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
870 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
871 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
872 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
875 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
876 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
877 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
878 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
879 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
880 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
881 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
882 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
884 if (Subtarget->is64Bit()) {
885 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
886 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
889 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
890 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
891 MVT VT = (MVT::SimpleValueType)i;
893 // Do not attempt to promote non-128-bit vectors
894 if (!VT.is128BitVector())
897 setOperationAction(ISD::AND, VT, Promote);
898 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
899 setOperationAction(ISD::OR, VT, Promote);
900 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
901 setOperationAction(ISD::XOR, VT, Promote);
902 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
903 setOperationAction(ISD::LOAD, VT, Promote);
904 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
905 setOperationAction(ISD::SELECT, VT, Promote);
906 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
909 // Custom lower v2i64 and v2f64 selects.
910 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
911 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
912 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
913 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
915 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
916 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
918 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
920 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
921 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
922 // As there is no 64-bit GPR available, we need build a special custom
923 // sequence to convert from v2i32 to v2f32.
924 if (!Subtarget->is64Bit())
925 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
927 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
928 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
930 for (MVT VT : MVT::fp_vector_valuetypes())
931 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
933 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
934 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
935 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
938 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
939 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
940 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
941 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
942 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
943 setOperationAction(ISD::FRINT, RoundedTy, Legal);
944 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
947 // FIXME: Do we need to handle scalar-to-vector here?
948 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
950 // We directly match byte blends in the backend as they match the VSELECT
952 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
954 // SSE41 brings specific instructions for doing vector sign extend even in
955 // cases where we don't have SRA.
956 for (MVT VT : MVT::integer_vector_valuetypes()) {
957 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
958 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
959 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
962 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
963 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
964 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
965 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
966 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
967 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
968 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
970 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
971 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
972 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
973 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
974 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
975 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
977 // i8 and i16 vectors are custom because the source register and source
978 // source memory operand types are not the same width. f32 vectors are
979 // custom since the immediate controlling the insert encodes additional
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
983 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
984 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
988 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
989 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
991 // FIXME: these should be Legal, but that's only for the case where
992 // the index is constant. For now custom expand to deal with that.
993 if (Subtarget->is64Bit()) {
994 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
995 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
999 if (Subtarget->hasSSE2()) {
1000 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1001 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1004 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1005 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1007 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1008 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1010 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1011 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1013 // In the customized shift lowering, the legal cases in AVX2 will be
1015 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1016 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1018 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1019 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1021 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1024 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1025 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1026 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1027 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1028 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1029 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1030 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1032 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1033 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1034 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1036 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1037 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1038 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1039 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1040 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1041 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1042 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1043 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1044 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1045 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1046 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1047 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1049 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1050 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1051 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1052 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1053 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1059 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1060 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1062 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1063 // even though v8i16 is a legal type.
1064 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1065 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1066 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1068 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1069 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1070 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1075 for (MVT VT : MVT::fp_vector_valuetypes())
1076 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1078 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1079 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1081 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1082 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1084 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1085 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1087 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1088 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1089 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1090 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1092 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1093 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1094 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1096 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1097 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1098 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1099 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1100 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1101 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1102 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1103 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1104 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1105 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1106 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1107 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1109 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1110 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1111 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1112 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1114 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1115 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1116 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1117 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1118 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1119 setOperationAction(ISD::FMA, MVT::f32, Legal);
1120 setOperationAction(ISD::FMA, MVT::f64, Legal);
1123 if (Subtarget->hasInt256()) {
1124 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1125 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1126 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1127 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1129 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1130 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1131 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1132 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1134 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1135 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1136 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1137 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1139 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1140 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1141 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1142 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1144 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1145 // when we have a 256bit-wide blend with immediate.
1146 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1148 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1149 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1150 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1151 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1152 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1153 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1154 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1156 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1157 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1158 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1159 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1160 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1161 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1163 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1164 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1165 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1166 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1168 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1169 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1170 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1171 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1173 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1174 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1175 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1176 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1179 // In the customized shift lowering, the legal cases in AVX2 will be
1181 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1182 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1184 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1187 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1189 // Custom lower several nodes for 256-bit types.
1190 for (MVT VT : MVT::vector_valuetypes()) {
1191 if (VT.getScalarSizeInBits() >= 32) {
1192 setOperationAction(ISD::MLOAD, VT, Legal);
1193 setOperationAction(ISD::MSTORE, VT, Legal);
1195 // Extract subvector is special because the value type
1196 // (result) is 128-bit but the source is 256-bit wide.
1197 if (VT.is128BitVector()) {
1198 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1200 // Do not attempt to custom lower other non-256-bit vectors
1201 if (!VT.is256BitVector())
1204 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1205 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1206 setOperationAction(ISD::VSELECT, VT, Custom);
1207 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1208 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1209 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1210 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1211 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1214 if (Subtarget->hasInt256())
1215 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1218 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1219 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1220 MVT VT = (MVT::SimpleValueType)i;
1222 // Do not attempt to promote non-256-bit vectors
1223 if (!VT.is256BitVector())
1226 setOperationAction(ISD::AND, VT, Promote);
1227 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1228 setOperationAction(ISD::OR, VT, Promote);
1229 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1230 setOperationAction(ISD::XOR, VT, Promote);
1231 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1232 setOperationAction(ISD::LOAD, VT, Promote);
1233 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1234 setOperationAction(ISD::SELECT, VT, Promote);
1235 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1239 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1240 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1241 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1242 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1243 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1245 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1246 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1247 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1249 for (MVT VT : MVT::fp_vector_valuetypes())
1250 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1252 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1253 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1254 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1255 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1256 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1257 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1258 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1259 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1260 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1261 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1262 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1263 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1265 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1266 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1267 setOperationAction(ISD::XOR, MVT::i1, Legal);
1268 setOperationAction(ISD::OR, MVT::i1, Legal);
1269 setOperationAction(ISD::AND, MVT::i1, Legal);
1270 setOperationAction(ISD::SUB, MVT::i1, Custom);
1271 setOperationAction(ISD::ADD, MVT::i1, Custom);
1272 setOperationAction(ISD::MUL, MVT::i1, Custom);
1273 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1274 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1275 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1276 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1277 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1279 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1280 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1281 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1282 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1283 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1284 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1286 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1287 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1288 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1289 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1290 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1291 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1292 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1293 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1295 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1296 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1297 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1298 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1299 if (Subtarget->is64Bit()) {
1300 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1301 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1302 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1303 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1305 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1306 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1307 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1308 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1309 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1310 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1311 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1312 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1313 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1314 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1315 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1316 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1317 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1318 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1319 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1320 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1322 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1323 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1324 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1325 if (Subtarget->hasDQI()) {
1326 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1327 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1329 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1330 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1331 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1332 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1333 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1334 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1335 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1336 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1337 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1338 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1339 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1340 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1341 if (Subtarget->hasDQI()) {
1342 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1343 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1345 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1350 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1354 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1362 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1363 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1365 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1367 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1368 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1369 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1370 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1371 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1372 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1373 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1374 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1375 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1376 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1377 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1379 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1380 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1382 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1383 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1385 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1387 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1388 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1390 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1391 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1393 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1396 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1397 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1398 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1399 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1400 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1401 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1403 if (Subtarget->hasCDI()) {
1404 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1405 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1407 if (Subtarget->hasDQI()) {
1408 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1409 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1410 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1412 // Custom lower several nodes.
1413 for (MVT VT : MVT::vector_valuetypes()) {
1414 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1416 setOperationAction(ISD::AND, VT, Legal);
1417 setOperationAction(ISD::OR, VT, Legal);
1418 setOperationAction(ISD::XOR, VT, Legal);
1420 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1421 setOperationAction(ISD::MGATHER, VT, Custom);
1422 setOperationAction(ISD::MSCATTER, VT, Custom);
1424 // Extract subvector is special because the value type
1425 // (result) is 256/128-bit but the source is 512-bit wide.
1426 if (VT.is128BitVector() || VT.is256BitVector()) {
1427 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1429 if (VT.getVectorElementType() == MVT::i1)
1430 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1432 // Do not attempt to custom lower other non-512-bit vectors
1433 if (!VT.is512BitVector())
1436 if (EltSize >= 32) {
1437 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1438 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1439 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1440 setOperationAction(ISD::VSELECT, VT, Legal);
1441 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1442 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1443 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1444 setOperationAction(ISD::MLOAD, VT, Legal);
1445 setOperationAction(ISD::MSTORE, VT, Legal);
1448 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1449 MVT VT = (MVT::SimpleValueType)i;
1451 // Do not attempt to promote non-512-bit vectors.
1452 if (!VT.is512BitVector())
1455 setOperationAction(ISD::SELECT, VT, Promote);
1456 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1460 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1461 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1462 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1464 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1465 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1467 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1468 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1469 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1470 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1471 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1472 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1473 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1474 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1475 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1476 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1477 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1478 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1479 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1480 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1481 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1482 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1483 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1484 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1485 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1486 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1487 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1488 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1489 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1490 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1491 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1492 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1493 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1495 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1496 const MVT VT = (MVT::SimpleValueType)i;
1498 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1500 // Do not attempt to promote non-512-bit vectors.
1501 if (!VT.is512BitVector())
1505 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1506 setOperationAction(ISD::VSELECT, VT, Legal);
1511 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1512 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1513 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1515 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1516 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1517 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1518 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1519 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1520 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1521 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1522 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1524 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1526 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1527 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1528 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1529 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1530 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1531 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1532 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1533 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1536 // We want to custom lower some of our intrinsics.
1537 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1538 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1539 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1540 if (!Subtarget->is64Bit())
1541 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1543 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1544 // handle type legalization for these operations here.
1546 // FIXME: We really should do custom legalization for addition and
1547 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1548 // than generic legalization for 64-bit multiplication-with-overflow, though.
1549 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1550 // Add/Sub/Mul with overflow operations are custom lowered.
1552 setOperationAction(ISD::SADDO, VT, Custom);
1553 setOperationAction(ISD::UADDO, VT, Custom);
1554 setOperationAction(ISD::SSUBO, VT, Custom);
1555 setOperationAction(ISD::USUBO, VT, Custom);
1556 setOperationAction(ISD::SMULO, VT, Custom);
1557 setOperationAction(ISD::UMULO, VT, Custom);
1561 if (!Subtarget->is64Bit()) {
1562 // These libcalls are not available in 32-bit.
1563 setLibcallName(RTLIB::SHL_I128, nullptr);
1564 setLibcallName(RTLIB::SRL_I128, nullptr);
1565 setLibcallName(RTLIB::SRA_I128, nullptr);
1568 // Combine sin / cos into one node or libcall if possible.
1569 if (Subtarget->hasSinCos()) {
1570 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1571 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1572 if (Subtarget->isTargetDarwin()) {
1573 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1574 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1575 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1576 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1580 if (Subtarget->isTargetWin64()) {
1581 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1582 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1583 setOperationAction(ISD::SREM, MVT::i128, Custom);
1584 setOperationAction(ISD::UREM, MVT::i128, Custom);
1585 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1586 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1589 // We have target-specific dag combine patterns for the following nodes:
1590 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1591 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1592 setTargetDAGCombine(ISD::BITCAST);
1593 setTargetDAGCombine(ISD::VSELECT);
1594 setTargetDAGCombine(ISD::SELECT);
1595 setTargetDAGCombine(ISD::SHL);
1596 setTargetDAGCombine(ISD::SRA);
1597 setTargetDAGCombine(ISD::SRL);
1598 setTargetDAGCombine(ISD::OR);
1599 setTargetDAGCombine(ISD::AND);
1600 setTargetDAGCombine(ISD::ADD);
1601 setTargetDAGCombine(ISD::FADD);
1602 setTargetDAGCombine(ISD::FSUB);
1603 setTargetDAGCombine(ISD::FMA);
1604 setTargetDAGCombine(ISD::SUB);
1605 setTargetDAGCombine(ISD::LOAD);
1606 setTargetDAGCombine(ISD::MLOAD);
1607 setTargetDAGCombine(ISD::STORE);
1608 setTargetDAGCombine(ISD::MSTORE);
1609 setTargetDAGCombine(ISD::ZERO_EXTEND);
1610 setTargetDAGCombine(ISD::ANY_EXTEND);
1611 setTargetDAGCombine(ISD::SIGN_EXTEND);
1612 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1613 setTargetDAGCombine(ISD::SINT_TO_FP);
1614 setTargetDAGCombine(ISD::UINT_TO_FP);
1615 setTargetDAGCombine(ISD::SETCC);
1616 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1617 setTargetDAGCombine(ISD::BUILD_VECTOR);
1618 setTargetDAGCombine(ISD::MUL);
1619 setTargetDAGCombine(ISD::XOR);
1621 computeRegisterProperties(Subtarget->getRegisterInfo());
1623 // On Darwin, -Os means optimize for size without hurting performance,
1624 // do not reduce the limit.
1625 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1626 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1627 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1628 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1629 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1630 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1631 setPrefLoopAlignment(4); // 2^4 bytes.
1633 // Predictable cmov don't hurt on atom because it's in-order.
1634 PredictableSelectIsExpensive = !Subtarget->isAtom();
1635 EnableExtLdPromotion = true;
1636 setPrefFunctionAlignment(4); // 2^4 bytes.
1638 verifyIntrinsicTables();
1641 // This has so far only been implemented for 64-bit MachO.
1642 bool X86TargetLowering::useLoadStackGuardNode() const {
1643 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1646 TargetLoweringBase::LegalizeTypeAction
1647 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1648 if (ExperimentalVectorWideningLegalization &&
1649 VT.getVectorNumElements() != 1 &&
1650 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1651 return TypeWidenVector;
1653 return TargetLoweringBase::getPreferredVectorAction(VT);
1656 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1658 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1660 const unsigned NumElts = VT.getVectorNumElements();
1661 const EVT EltVT = VT.getVectorElementType();
1662 if (VT.is512BitVector()) {
1663 if (Subtarget->hasAVX512())
1664 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1665 EltVT == MVT::f32 || EltVT == MVT::f64)
1667 case 8: return MVT::v8i1;
1668 case 16: return MVT::v16i1;
1670 if (Subtarget->hasBWI())
1671 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1673 case 32: return MVT::v32i1;
1674 case 64: return MVT::v64i1;
1678 if (VT.is256BitVector() || VT.is128BitVector()) {
1679 if (Subtarget->hasVLX())
1680 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1681 EltVT == MVT::f32 || EltVT == MVT::f64)
1683 case 2: return MVT::v2i1;
1684 case 4: return MVT::v4i1;
1685 case 8: return MVT::v8i1;
1687 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1688 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1690 case 8: return MVT::v8i1;
1691 case 16: return MVT::v16i1;
1692 case 32: return MVT::v32i1;
1696 return VT.changeVectorElementTypeToInteger();
1699 /// Helper for getByValTypeAlignment to determine
1700 /// the desired ByVal argument alignment.
1701 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1704 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1705 if (VTy->getBitWidth() == 128)
1707 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1708 unsigned EltAlign = 0;
1709 getMaxByValAlign(ATy->getElementType(), EltAlign);
1710 if (EltAlign > MaxAlign)
1711 MaxAlign = EltAlign;
1712 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1713 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1714 unsigned EltAlign = 0;
1715 getMaxByValAlign(STy->getElementType(i), EltAlign);
1716 if (EltAlign > MaxAlign)
1717 MaxAlign = EltAlign;
1724 /// Return the desired alignment for ByVal aggregate
1725 /// function arguments in the caller parameter area. For X86, aggregates
1726 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1727 /// are at 4-byte boundaries.
1728 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1729 if (Subtarget->is64Bit()) {
1730 // Max of 8 and alignment of type.
1731 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1738 if (Subtarget->hasSSE1())
1739 getMaxByValAlign(Ty, Align);
1743 /// Returns the target specific optimal type for load
1744 /// and store operations as a result of memset, memcpy, and memmove
1745 /// lowering. If DstAlign is zero that means it's safe to destination
1746 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1747 /// means there isn't a need to check it against alignment requirement,
1748 /// probably because the source does not need to be loaded. If 'IsMemset' is
1749 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1750 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1751 /// source is constant so it does not need to be loaded.
1752 /// It returns EVT::Other if the type should be determined using generic
1753 /// target-independent logic.
1755 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1756 unsigned DstAlign, unsigned SrcAlign,
1757 bool IsMemset, bool ZeroMemset,
1759 MachineFunction &MF) const {
1760 const Function *F = MF.getFunction();
1761 if ((!IsMemset || ZeroMemset) &&
1762 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1764 (Subtarget->isUnalignedMemAccessFast() ||
1765 ((DstAlign == 0 || DstAlign >= 16) &&
1766 (SrcAlign == 0 || SrcAlign >= 16)))) {
1768 if (Subtarget->hasInt256())
1770 if (Subtarget->hasFp256())
1773 if (Subtarget->hasSSE2())
1775 if (Subtarget->hasSSE1())
1777 } else if (!MemcpyStrSrc && Size >= 8 &&
1778 !Subtarget->is64Bit() &&
1779 Subtarget->hasSSE2()) {
1780 // Do not use f64 to lower memcpy if source is string constant. It's
1781 // better to use i32 to avoid the loads.
1785 if (Subtarget->is64Bit() && Size >= 8)
1790 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1792 return X86ScalarSSEf32;
1793 else if (VT == MVT::f64)
1794 return X86ScalarSSEf64;
1799 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1804 *Fast = Subtarget->isUnalignedMemAccessFast();
1808 /// Return the entry encoding for a jump table in the
1809 /// current function. The returned value is a member of the
1810 /// MachineJumpTableInfo::JTEntryKind enum.
1811 unsigned X86TargetLowering::getJumpTableEncoding() const {
1812 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1814 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1815 Subtarget->isPICStyleGOT())
1816 return MachineJumpTableInfo::EK_Custom32;
1818 // Otherwise, use the normal jump table encoding heuristics.
1819 return TargetLowering::getJumpTableEncoding();
1822 bool X86TargetLowering::useSoftFloat() const {
1823 return Subtarget->useSoftFloat();
1827 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1828 const MachineBasicBlock *MBB,
1829 unsigned uid,MCContext &Ctx) const{
1830 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1831 Subtarget->isPICStyleGOT());
1832 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1834 return MCSymbolRefExpr::create(MBB->getSymbol(),
1835 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1838 /// Returns relocation base for the given PIC jumptable.
1839 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1840 SelectionDAG &DAG) const {
1841 if (!Subtarget->is64Bit())
1842 // This doesn't have SDLoc associated with it, but is not really the
1843 // same as a Register.
1844 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1848 /// This returns the relocation base for the given PIC jumptable,
1849 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1850 const MCExpr *X86TargetLowering::
1851 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1852 MCContext &Ctx) const {
1853 // X86-64 uses RIP relative addressing based on the jump table label.
1854 if (Subtarget->isPICStyleRIPRel())
1855 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1857 // Otherwise, the reference is relative to the PIC base.
1858 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1861 std::pair<const TargetRegisterClass *, uint8_t>
1862 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1864 const TargetRegisterClass *RRC = nullptr;
1866 switch (VT.SimpleTy) {
1868 return TargetLowering::findRepresentativeClass(TRI, VT);
1869 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1870 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1873 RRC = &X86::VR64RegClass;
1875 case MVT::f32: case MVT::f64:
1876 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1877 case MVT::v4f32: case MVT::v2f64:
1878 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1880 RRC = &X86::VR128RegClass;
1883 return std::make_pair(RRC, Cost);
1886 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1887 unsigned &Offset) const {
1888 if (!Subtarget->isTargetLinux())
1891 if (Subtarget->is64Bit()) {
1892 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1894 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1906 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1907 unsigned DestAS) const {
1908 assert(SrcAS != DestAS && "Expected different address spaces!");
1910 return SrcAS < 256 && DestAS < 256;
1913 //===----------------------------------------------------------------------===//
1914 // Return Value Calling Convention Implementation
1915 //===----------------------------------------------------------------------===//
1917 #include "X86GenCallingConv.inc"
1920 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1921 MachineFunction &MF, bool isVarArg,
1922 const SmallVectorImpl<ISD::OutputArg> &Outs,
1923 LLVMContext &Context) const {
1924 SmallVector<CCValAssign, 16> RVLocs;
1925 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1926 return CCInfo.CheckReturn(Outs, RetCC_X86);
1929 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1930 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1935 X86TargetLowering::LowerReturn(SDValue Chain,
1936 CallingConv::ID CallConv, bool isVarArg,
1937 const SmallVectorImpl<ISD::OutputArg> &Outs,
1938 const SmallVectorImpl<SDValue> &OutVals,
1939 SDLoc dl, SelectionDAG &DAG) const {
1940 MachineFunction &MF = DAG.getMachineFunction();
1941 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1943 SmallVector<CCValAssign, 16> RVLocs;
1944 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1945 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1948 SmallVector<SDValue, 6> RetOps;
1949 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1950 // Operand #1 = Bytes To Pop
1951 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
1954 // Copy the result values into the output registers.
1955 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1956 CCValAssign &VA = RVLocs[i];
1957 assert(VA.isRegLoc() && "Can only return in registers!");
1958 SDValue ValToCopy = OutVals[i];
1959 EVT ValVT = ValToCopy.getValueType();
1961 // Promote values to the appropriate types.
1962 if (VA.getLocInfo() == CCValAssign::SExt)
1963 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1964 else if (VA.getLocInfo() == CCValAssign::ZExt)
1965 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1966 else if (VA.getLocInfo() == CCValAssign::AExt) {
1967 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
1968 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1970 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1972 else if (VA.getLocInfo() == CCValAssign::BCvt)
1973 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
1975 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1976 "Unexpected FP-extend for return value.");
1978 // If this is x86-64, and we disabled SSE, we can't return FP values,
1979 // or SSE or MMX vectors.
1980 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1981 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1982 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1983 report_fatal_error("SSE register return with SSE disabled");
1985 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1986 // llvm-gcc has never done it right and no one has noticed, so this
1987 // should be OK for now.
1988 if (ValVT == MVT::f64 &&
1989 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1990 report_fatal_error("SSE2 register return with SSE2 disabled");
1992 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1993 // the RET instruction and handled by the FP Stackifier.
1994 if (VA.getLocReg() == X86::FP0 ||
1995 VA.getLocReg() == X86::FP1) {
1996 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1997 // change the value to the FP stack register class.
1998 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1999 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2000 RetOps.push_back(ValToCopy);
2001 // Don't emit a copytoreg.
2005 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2006 // which is returned in RAX / RDX.
2007 if (Subtarget->is64Bit()) {
2008 if (ValVT == MVT::x86mmx) {
2009 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2010 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2011 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2013 // If we don't have SSE2 available, convert to v4f32 so the generated
2014 // register is legal.
2015 if (!Subtarget->hasSSE2())
2016 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2021 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2022 Flag = Chain.getValue(1);
2023 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2026 // All x86 ABIs require that for returning structs by value we copy
2027 // the sret argument into %rax/%eax (depending on ABI) for the return.
2028 // We saved the argument into a virtual register in the entry block,
2029 // so now we copy the value out and into %rax/%eax.
2031 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2032 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2033 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2034 // either case FuncInfo->setSRetReturnReg() will have been called.
2035 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2036 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2039 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2040 X86::RAX : X86::EAX;
2041 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2042 Flag = Chain.getValue(1);
2044 // RAX/EAX now acts like a return value.
2045 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2048 RetOps[0] = Chain; // Update chain.
2050 // Add the flag if we have it.
2052 RetOps.push_back(Flag);
2054 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2057 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2058 if (N->getNumValues() != 1)
2060 if (!N->hasNUsesOfValue(1, 0))
2063 SDValue TCChain = Chain;
2064 SDNode *Copy = *N->use_begin();
2065 if (Copy->getOpcode() == ISD::CopyToReg) {
2066 // If the copy has a glue operand, we conservatively assume it isn't safe to
2067 // perform a tail call.
2068 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2070 TCChain = Copy->getOperand(0);
2071 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2074 bool HasRet = false;
2075 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2077 if (UI->getOpcode() != X86ISD::RET_FLAG)
2079 // If we are returning more than one value, we can definitely
2080 // not make a tail call see PR19530
2081 if (UI->getNumOperands() > 4)
2083 if (UI->getNumOperands() == 4 &&
2084 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2097 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2098 ISD::NodeType ExtendKind) const {
2100 // TODO: Is this also valid on 32-bit?
2101 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2102 ReturnMVT = MVT::i8;
2104 ReturnMVT = MVT::i32;
2106 EVT MinVT = getRegisterType(Context, ReturnMVT);
2107 return VT.bitsLT(MinVT) ? MinVT : VT;
2110 /// Lower the result values of a call into the
2111 /// appropriate copies out of appropriate physical registers.
2114 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2115 CallingConv::ID CallConv, bool isVarArg,
2116 const SmallVectorImpl<ISD::InputArg> &Ins,
2117 SDLoc dl, SelectionDAG &DAG,
2118 SmallVectorImpl<SDValue> &InVals) const {
2120 // Assign locations to each value returned by this call.
2121 SmallVector<CCValAssign, 16> RVLocs;
2122 bool Is64Bit = Subtarget->is64Bit();
2123 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2125 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2127 // Copy all of the result registers out of their specified physreg.
2128 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2129 CCValAssign &VA = RVLocs[i];
2130 EVT CopyVT = VA.getLocVT();
2132 // If this is x86-64, and we disabled SSE, we can't return FP values
2133 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2134 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2135 report_fatal_error("SSE register return with SSE disabled");
2138 // If we prefer to use the value in xmm registers, copy it out as f80 and
2139 // use a truncate to move it from fp stack reg to xmm reg.
2140 bool RoundAfterCopy = false;
2141 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2142 isScalarFPTypeInSSEReg(VA.getValVT())) {
2144 RoundAfterCopy = (CopyVT != VA.getLocVT());
2147 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2148 CopyVT, InFlag).getValue(1);
2149 SDValue Val = Chain.getValue(0);
2152 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2153 // This truncation won't change the value.
2154 DAG.getIntPtrConstant(1, dl));
2156 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2157 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2159 InFlag = Chain.getValue(2);
2160 InVals.push_back(Val);
2166 //===----------------------------------------------------------------------===//
2167 // C & StdCall & Fast Calling Convention implementation
2168 //===----------------------------------------------------------------------===//
2169 // StdCall calling convention seems to be standard for many Windows' API
2170 // routines and around. It differs from C calling convention just a little:
2171 // callee should clean up the stack, not caller. Symbols should be also
2172 // decorated in some fancy way :) It doesn't support any vector arguments.
2173 // For info on fast calling convention see Fast Calling Convention (tail call)
2174 // implementation LowerX86_32FastCCCallTo.
2176 /// CallIsStructReturn - Determines whether a call uses struct return
2178 enum StructReturnType {
2183 static StructReturnType
2184 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2186 return NotStructReturn;
2188 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2189 if (!Flags.isSRet())
2190 return NotStructReturn;
2191 if (Flags.isInReg())
2192 return RegStructReturn;
2193 return StackStructReturn;
2196 /// Determines whether a function uses struct return semantics.
2197 static StructReturnType
2198 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2200 return NotStructReturn;
2202 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2203 if (!Flags.isSRet())
2204 return NotStructReturn;
2205 if (Flags.isInReg())
2206 return RegStructReturn;
2207 return StackStructReturn;
2210 /// Make a copy of an aggregate at address specified by "Src" to address
2211 /// "Dst" with size and alignment information specified by the specific
2212 /// parameter attribute. The copy will be passed as a byval function parameter.
2214 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2215 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2217 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2219 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2220 /*isVolatile*/false, /*AlwaysInline=*/true,
2221 /*isTailCall*/false,
2222 MachinePointerInfo(), MachinePointerInfo());
2225 /// Return true if the calling convention is one that
2226 /// supports tail call optimization.
2227 static bool IsTailCallConvention(CallingConv::ID CC) {
2228 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2229 CC == CallingConv::HiPE);
2232 /// \brief Return true if the calling convention is a C calling convention.
2233 static bool IsCCallConvention(CallingConv::ID CC) {
2234 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2235 CC == CallingConv::X86_64_SysV);
2238 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2240 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2241 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2245 CallingConv::ID CalleeCC = CS.getCallingConv();
2246 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2252 /// Return true if the function is being made into
2253 /// a tailcall target by changing its ABI.
2254 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2255 bool GuaranteedTailCallOpt) {
2256 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2260 X86TargetLowering::LowerMemArgument(SDValue Chain,
2261 CallingConv::ID CallConv,
2262 const SmallVectorImpl<ISD::InputArg> &Ins,
2263 SDLoc dl, SelectionDAG &DAG,
2264 const CCValAssign &VA,
2265 MachineFrameInfo *MFI,
2267 // Create the nodes corresponding to a load from this parameter slot.
2268 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2269 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2270 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2271 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2274 // If value is passed by pointer we have address passed instead of the value
2276 bool ExtendedInMem = VA.isExtInLoc() &&
2277 VA.getValVT().getScalarType() == MVT::i1;
2279 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2280 ValVT = VA.getLocVT();
2282 ValVT = VA.getValVT();
2284 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2285 // changed with more analysis.
2286 // In case of tail call optimization mark all arguments mutable. Since they
2287 // could be overwritten by lowering of arguments in case of a tail call.
2288 if (Flags.isByVal()) {
2289 unsigned Bytes = Flags.getByValSize();
2290 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2291 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2292 return DAG.getFrameIndex(FI, getPointerTy());
2294 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2295 VA.getLocMemOffset(), isImmutable);
2296 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2297 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2298 MachinePointerInfo::getFixedStack(FI),
2299 false, false, false, 0);
2300 return ExtendedInMem ?
2301 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2305 // FIXME: Get this from tablegen.
2306 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2307 const X86Subtarget *Subtarget) {
2308 assert(Subtarget->is64Bit());
2310 if (Subtarget->isCallingConvWin64(CallConv)) {
2311 static const MCPhysReg GPR64ArgRegsWin64[] = {
2312 X86::RCX, X86::RDX, X86::R8, X86::R9
2314 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2317 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2318 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2320 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2323 // FIXME: Get this from tablegen.
2324 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2325 CallingConv::ID CallConv,
2326 const X86Subtarget *Subtarget) {
2327 assert(Subtarget->is64Bit());
2328 if (Subtarget->isCallingConvWin64(CallConv)) {
2329 // The XMM registers which might contain var arg parameters are shadowed
2330 // in their paired GPR. So we only need to save the GPR to their home
2332 // TODO: __vectorcall will change this.
2336 const Function *Fn = MF.getFunction();
2337 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2338 bool isSoftFloat = Subtarget->useSoftFloat();
2339 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2340 "SSE register cannot be used when SSE is disabled!");
2341 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2342 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2346 static const MCPhysReg XMMArgRegs64Bit[] = {
2347 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2348 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2350 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2354 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2355 CallingConv::ID CallConv,
2357 const SmallVectorImpl<ISD::InputArg> &Ins,
2360 SmallVectorImpl<SDValue> &InVals)
2362 MachineFunction &MF = DAG.getMachineFunction();
2363 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2364 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2366 const Function* Fn = MF.getFunction();
2367 if (Fn->hasExternalLinkage() &&
2368 Subtarget->isTargetCygMing() &&
2369 Fn->getName() == "main")
2370 FuncInfo->setForceFramePointer(true);
2372 MachineFrameInfo *MFI = MF.getFrameInfo();
2373 bool Is64Bit = Subtarget->is64Bit();
2374 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2376 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2377 "Var args not supported with calling convention fastcc, ghc or hipe");
2379 // Assign locations to all of the incoming arguments.
2380 SmallVector<CCValAssign, 16> ArgLocs;
2381 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2383 // Allocate shadow area for Win64
2385 CCInfo.AllocateStack(32, 8);
2387 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2389 unsigned LastVal = ~0U;
2391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2392 CCValAssign &VA = ArgLocs[i];
2393 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2395 assert(VA.getValNo() != LastVal &&
2396 "Don't support value assigned to multiple locs yet");
2398 LastVal = VA.getValNo();
2400 if (VA.isRegLoc()) {
2401 EVT RegVT = VA.getLocVT();
2402 const TargetRegisterClass *RC;
2403 if (RegVT == MVT::i32)
2404 RC = &X86::GR32RegClass;
2405 else if (Is64Bit && RegVT == MVT::i64)
2406 RC = &X86::GR64RegClass;
2407 else if (RegVT == MVT::f32)
2408 RC = &X86::FR32RegClass;
2409 else if (RegVT == MVT::f64)
2410 RC = &X86::FR64RegClass;
2411 else if (RegVT.is512BitVector())
2412 RC = &X86::VR512RegClass;
2413 else if (RegVT.is256BitVector())
2414 RC = &X86::VR256RegClass;
2415 else if (RegVT.is128BitVector())
2416 RC = &X86::VR128RegClass;
2417 else if (RegVT == MVT::x86mmx)
2418 RC = &X86::VR64RegClass;
2419 else if (RegVT == MVT::i1)
2420 RC = &X86::VK1RegClass;
2421 else if (RegVT == MVT::v8i1)
2422 RC = &X86::VK8RegClass;
2423 else if (RegVT == MVT::v16i1)
2424 RC = &X86::VK16RegClass;
2425 else if (RegVT == MVT::v32i1)
2426 RC = &X86::VK32RegClass;
2427 else if (RegVT == MVT::v64i1)
2428 RC = &X86::VK64RegClass;
2430 llvm_unreachable("Unknown argument type!");
2432 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2433 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2435 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2436 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2438 if (VA.getLocInfo() == CCValAssign::SExt)
2439 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2440 DAG.getValueType(VA.getValVT()));
2441 else if (VA.getLocInfo() == CCValAssign::ZExt)
2442 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2443 DAG.getValueType(VA.getValVT()));
2444 else if (VA.getLocInfo() == CCValAssign::BCvt)
2445 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2447 if (VA.isExtInLoc()) {
2448 // Handle MMX values passed in XMM regs.
2449 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2450 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2452 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2455 assert(VA.isMemLoc());
2456 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2459 // If value is passed via pointer - do a load.
2460 if (VA.getLocInfo() == CCValAssign::Indirect)
2461 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2462 MachinePointerInfo(), false, false, false, 0);
2464 InVals.push_back(ArgValue);
2467 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2468 // All x86 ABIs require that for returning structs by value we copy the
2469 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2470 // the argument into a virtual register so that we can access it from the
2472 if (Ins[i].Flags.isSRet()) {
2473 unsigned Reg = FuncInfo->getSRetReturnReg();
2475 MVT PtrTy = getPointerTy();
2476 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2477 FuncInfo->setSRetReturnReg(Reg);
2479 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2480 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2485 unsigned StackSize = CCInfo.getNextStackOffset();
2486 // Align stack specially for tail calls.
2487 if (FuncIsMadeTailCallSafe(CallConv,
2488 MF.getTarget().Options.GuaranteedTailCallOpt))
2489 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2491 // If the function takes variable number of arguments, make a frame index for
2492 // the start of the first vararg value... for expansion of llvm.va_start. We
2493 // can skip this if there are no va_start calls.
2494 if (MFI->hasVAStart() &&
2495 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2496 CallConv != CallingConv::X86_ThisCall))) {
2497 FuncInfo->setVarArgsFrameIndex(
2498 MFI->CreateFixedObject(1, StackSize, true));
2501 MachineModuleInfo &MMI = MF.getMMI();
2502 const Function *WinEHParent = nullptr;
2503 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2504 WinEHParent = MMI.getWinEHParent(Fn);
2505 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2506 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2508 // Figure out if XMM registers are in use.
2509 assert(!(Subtarget->useSoftFloat() &&
2510 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2511 "SSE register cannot be used when SSE is disabled!");
2513 // 64-bit calling conventions support varargs and register parameters, so we
2514 // have to do extra work to spill them in the prologue.
2515 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2516 // Find the first unallocated argument registers.
2517 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2518 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2519 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2520 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2521 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2522 "SSE register cannot be used when SSE is disabled!");
2524 // Gather all the live in physical registers.
2525 SmallVector<SDValue, 6> LiveGPRs;
2526 SmallVector<SDValue, 8> LiveXMMRegs;
2528 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2529 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2531 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2533 if (!ArgXMMs.empty()) {
2534 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2535 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2536 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2537 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2538 LiveXMMRegs.push_back(
2539 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2544 // Get to the caller-allocated home save location. Add 8 to account
2545 // for the return address.
2546 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2547 FuncInfo->setRegSaveFrameIndex(
2548 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2549 // Fixup to set vararg frame on shadow area (4 x i64).
2551 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2553 // For X86-64, if there are vararg parameters that are passed via
2554 // registers, then we must store them to their spots on the stack so
2555 // they may be loaded by deferencing the result of va_next.
2556 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2557 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2558 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2559 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2562 // Store the integer parameter registers.
2563 SmallVector<SDValue, 8> MemOps;
2564 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2566 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2567 for (SDValue Val : LiveGPRs) {
2568 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2569 DAG.getIntPtrConstant(Offset, dl));
2571 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2572 MachinePointerInfo::getFixedStack(
2573 FuncInfo->getRegSaveFrameIndex(), Offset),
2575 MemOps.push_back(Store);
2579 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2580 // Now store the XMM (fp + vector) parameter registers.
2581 SmallVector<SDValue, 12> SaveXMMOps;
2582 SaveXMMOps.push_back(Chain);
2583 SaveXMMOps.push_back(ALVal);
2584 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2585 FuncInfo->getRegSaveFrameIndex(), dl));
2586 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2587 FuncInfo->getVarArgsFPOffset(), dl));
2588 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2590 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2591 MVT::Other, SaveXMMOps));
2594 if (!MemOps.empty())
2595 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2596 } else if (IsWinEHOutlined) {
2597 // Get to the caller-allocated home save location. Add 8 to account
2598 // for the return address.
2599 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2600 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2601 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2603 MMI.getWinEHFuncInfo(Fn)
2604 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2605 FuncInfo->getRegSaveFrameIndex();
2607 // Store the second integer parameter (rdx) into rsp+16 relative to the
2608 // stack pointer at the entry of the function.
2610 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2611 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2612 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2613 Chain = DAG.getStore(
2614 Val.getValue(1), dl, Val, RSFIN,
2615 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2616 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2619 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2620 // Find the largest legal vector type.
2621 MVT VecVT = MVT::Other;
2622 // FIXME: Only some x86_32 calling conventions support AVX512.
2623 if (Subtarget->hasAVX512() &&
2624 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2625 CallConv == CallingConv::Intel_OCL_BI)))
2626 VecVT = MVT::v16f32;
2627 else if (Subtarget->hasAVX())
2629 else if (Subtarget->hasSSE2())
2632 // We forward some GPRs and some vector types.
2633 SmallVector<MVT, 2> RegParmTypes;
2634 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2635 RegParmTypes.push_back(IntVT);
2636 if (VecVT != MVT::Other)
2637 RegParmTypes.push_back(VecVT);
2639 // Compute the set of forwarded registers. The rest are scratch.
2640 SmallVectorImpl<ForwardedRegister> &Forwards =
2641 FuncInfo->getForwardedMustTailRegParms();
2642 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2644 // Conservatively forward AL on x86_64, since it might be used for varargs.
2645 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2646 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2647 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2650 // Copy all forwards from physical to virtual registers.
2651 for (ForwardedRegister &F : Forwards) {
2652 // FIXME: Can we use a less constrained schedule?
2653 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2654 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2655 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2659 // Some CCs need callee pop.
2660 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2661 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2662 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2664 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2665 // If this is an sret function, the return should pop the hidden pointer.
2666 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2667 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2668 argsAreStructReturn(Ins) == StackStructReturn)
2669 FuncInfo->setBytesToPopOnReturn(4);
2673 // RegSaveFrameIndex is X86-64 only.
2674 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2675 if (CallConv == CallingConv::X86_FastCall ||
2676 CallConv == CallingConv::X86_ThisCall)
2677 // fastcc functions can't have varargs.
2678 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2681 FuncInfo->setArgumentStackSize(StackSize);
2683 if (IsWinEHParent) {
2684 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2685 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2686 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2687 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2688 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2689 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2690 /*isVolatile=*/true,
2691 /*isNonTemporal=*/false, /*Alignment=*/0);
2698 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2699 SDValue StackPtr, SDValue Arg,
2700 SDLoc dl, SelectionDAG &DAG,
2701 const CCValAssign &VA,
2702 ISD::ArgFlagsTy Flags) const {
2703 unsigned LocMemOffset = VA.getLocMemOffset();
2704 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2705 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2706 if (Flags.isByVal())
2707 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2709 return DAG.getStore(Chain, dl, Arg, PtrOff,
2710 MachinePointerInfo::getStack(LocMemOffset),
2714 /// Emit a load of return address if tail call
2715 /// optimization is performed and it is required.
2717 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2718 SDValue &OutRetAddr, SDValue Chain,
2719 bool IsTailCall, bool Is64Bit,
2720 int FPDiff, SDLoc dl) const {
2721 // Adjust the Return address stack slot.
2722 EVT VT = getPointerTy();
2723 OutRetAddr = getReturnAddressFrameIndex(DAG);
2725 // Load the "old" Return address.
2726 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2727 false, false, false, 0);
2728 return SDValue(OutRetAddr.getNode(), 1);
2731 /// Emit a store of the return address if tail call
2732 /// optimization is performed and it is required (FPDiff!=0).
2733 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2734 SDValue Chain, SDValue RetAddrFrIdx,
2735 EVT PtrVT, unsigned SlotSize,
2736 int FPDiff, SDLoc dl) {
2737 // Store the return address to the appropriate stack slot.
2738 if (!FPDiff) return Chain;
2739 // Calculate the new stack slot for the return address.
2740 int NewReturnAddrFI =
2741 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2743 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2744 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2745 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2751 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2752 SmallVectorImpl<SDValue> &InVals) const {
2753 SelectionDAG &DAG = CLI.DAG;
2755 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2756 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2757 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2758 SDValue Chain = CLI.Chain;
2759 SDValue Callee = CLI.Callee;
2760 CallingConv::ID CallConv = CLI.CallConv;
2761 bool &isTailCall = CLI.IsTailCall;
2762 bool isVarArg = CLI.IsVarArg;
2764 MachineFunction &MF = DAG.getMachineFunction();
2765 bool Is64Bit = Subtarget->is64Bit();
2766 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2767 StructReturnType SR = callIsStructReturn(Outs);
2768 bool IsSibcall = false;
2769 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2770 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2772 if (Attr.getValueAsString() == "true")
2775 if (Subtarget->isPICStyleGOT() &&
2776 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2777 // If we are using a GOT, disable tail calls to external symbols with
2778 // default visibility. Tail calling such a symbol requires using a GOT
2779 // relocation, which forces early binding of the symbol. This breaks code
2780 // that require lazy function symbol resolution. Using musttail or
2781 // GuaranteedTailCallOpt will override this.
2782 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2783 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2784 G->getGlobal()->hasDefaultVisibility()))
2788 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2790 // Force this to be a tail call. The verifier rules are enough to ensure
2791 // that we can lower this successfully without moving the return address
2794 } else if (isTailCall) {
2795 // Check if it's really possible to do a tail call.
2796 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2797 isVarArg, SR != NotStructReturn,
2798 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2799 Outs, OutVals, Ins, DAG);
2801 // Sibcalls are automatically detected tailcalls which do not require
2803 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2810 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2811 "Var args not supported with calling convention fastcc, ghc or hipe");
2813 // Analyze operands of the call, assigning locations to each operand.
2814 SmallVector<CCValAssign, 16> ArgLocs;
2815 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2817 // Allocate shadow area for Win64
2819 CCInfo.AllocateStack(32, 8);
2821 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2823 // Get a count of how many bytes are to be pushed on the stack.
2824 unsigned NumBytes = CCInfo.getNextStackOffset();
2826 // This is a sibcall. The memory operands are available in caller's
2827 // own caller's stack.
2829 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2830 IsTailCallConvention(CallConv))
2831 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2834 if (isTailCall && !IsSibcall && !IsMustTail) {
2835 // Lower arguments at fp - stackoffset + fpdiff.
2836 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2838 FPDiff = NumBytesCallerPushed - NumBytes;
2840 // Set the delta of movement of the returnaddr stackslot.
2841 // But only set if delta is greater than previous delta.
2842 if (FPDiff < X86Info->getTCReturnAddrDelta())
2843 X86Info->setTCReturnAddrDelta(FPDiff);
2846 unsigned NumBytesToPush = NumBytes;
2847 unsigned NumBytesToPop = NumBytes;
2849 // If we have an inalloca argument, all stack space has already been allocated
2850 // for us and be right at the top of the stack. We don't support multiple
2851 // arguments passed in memory when using inalloca.
2852 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2854 if (!ArgLocs.back().isMemLoc())
2855 report_fatal_error("cannot use inalloca attribute on a register "
2857 if (ArgLocs.back().getLocMemOffset() != 0)
2858 report_fatal_error("any parameter with the inalloca attribute must be "
2859 "the only memory argument");
2863 Chain = DAG.getCALLSEQ_START(
2864 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2866 SDValue RetAddrFrIdx;
2867 // Load return address for tail calls.
2868 if (isTailCall && FPDiff)
2869 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2870 Is64Bit, FPDiff, dl);
2872 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2873 SmallVector<SDValue, 8> MemOpChains;
2876 // Walk the register/memloc assignments, inserting copies/loads. In the case
2877 // of tail call optimization arguments are handle later.
2878 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2879 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2880 // Skip inalloca arguments, they have already been written.
2881 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2882 if (Flags.isInAlloca())
2885 CCValAssign &VA = ArgLocs[i];
2886 EVT RegVT = VA.getLocVT();
2887 SDValue Arg = OutVals[i];
2888 bool isByVal = Flags.isByVal();
2890 // Promote the value if needed.
2891 switch (VA.getLocInfo()) {
2892 default: llvm_unreachable("Unknown loc info!");
2893 case CCValAssign::Full: break;
2894 case CCValAssign::SExt:
2895 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2897 case CCValAssign::ZExt:
2898 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2900 case CCValAssign::AExt:
2901 if (Arg.getValueType().isVector() &&
2902 Arg.getValueType().getScalarType() == MVT::i1)
2903 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2904 else if (RegVT.is128BitVector()) {
2905 // Special case: passing MMX values in XMM registers.
2906 Arg = DAG.getBitcast(MVT::i64, Arg);
2907 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2908 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2910 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2912 case CCValAssign::BCvt:
2913 Arg = DAG.getBitcast(RegVT, Arg);
2915 case CCValAssign::Indirect: {
2916 // Store the argument.
2917 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2918 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2919 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2920 MachinePointerInfo::getFixedStack(FI),
2927 if (VA.isRegLoc()) {
2928 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2929 if (isVarArg && IsWin64) {
2930 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2931 // shadow reg if callee is a varargs function.
2932 unsigned ShadowReg = 0;
2933 switch (VA.getLocReg()) {
2934 case X86::XMM0: ShadowReg = X86::RCX; break;
2935 case X86::XMM1: ShadowReg = X86::RDX; break;
2936 case X86::XMM2: ShadowReg = X86::R8; break;
2937 case X86::XMM3: ShadowReg = X86::R9; break;
2940 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2942 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2943 assert(VA.isMemLoc());
2944 if (!StackPtr.getNode())
2945 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2947 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2948 dl, DAG, VA, Flags));
2952 if (!MemOpChains.empty())
2953 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2955 if (Subtarget->isPICStyleGOT()) {
2956 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2960 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2962 // If we are tail calling and generating PIC/GOT style code load the
2963 // address of the callee into ECX. The value in ecx is used as target of
2964 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2965 // for tail calls on PIC/GOT architectures. Normally we would just put the
2966 // address of GOT into ebx and then call target@PLT. But for tail calls
2967 // ebx would be restored (since ebx is callee saved) before jumping to the
2970 // Note: The actual moving to ECX is done further down.
2971 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2972 if (G && !G->getGlobal()->hasLocalLinkage() &&
2973 G->getGlobal()->hasDefaultVisibility())
2974 Callee = LowerGlobalAddress(Callee, DAG);
2975 else if (isa<ExternalSymbolSDNode>(Callee))
2976 Callee = LowerExternalSymbol(Callee, DAG);
2980 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2981 // From AMD64 ABI document:
2982 // For calls that may call functions that use varargs or stdargs
2983 // (prototype-less calls or calls to functions containing ellipsis (...) in
2984 // the declaration) %al is used as hidden argument to specify the number
2985 // of SSE registers used. The contents of %al do not need to match exactly
2986 // the number of registers, but must be an ubound on the number of SSE
2987 // registers used and is in the range 0 - 8 inclusive.
2989 // Count the number of XMM registers allocated.
2990 static const MCPhysReg XMMArgRegs[] = {
2991 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2992 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2994 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2995 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2996 && "SSE registers cannot be used when SSE is disabled");
2998 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2999 DAG.getConstant(NumXMMRegs, dl,
3003 if (isVarArg && IsMustTail) {
3004 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3005 for (const auto &F : Forwards) {
3006 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3007 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3011 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3012 // don't need this because the eligibility check rejects calls that require
3013 // shuffling arguments passed in memory.
3014 if (!IsSibcall && isTailCall) {
3015 // Force all the incoming stack arguments to be loaded from the stack
3016 // before any new outgoing arguments are stored to the stack, because the
3017 // outgoing stack slots may alias the incoming argument stack slots, and
3018 // the alias isn't otherwise explicit. This is slightly more conservative
3019 // than necessary, because it means that each store effectively depends
3020 // on every argument instead of just those arguments it would clobber.
3021 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3023 SmallVector<SDValue, 8> MemOpChains2;
3026 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3027 CCValAssign &VA = ArgLocs[i];
3030 assert(VA.isMemLoc());
3031 SDValue Arg = OutVals[i];
3032 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3033 // Skip inalloca arguments. They don't require any work.
3034 if (Flags.isInAlloca())
3036 // Create frame index.
3037 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3038 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3039 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3040 FIN = DAG.getFrameIndex(FI, getPointerTy());
3042 if (Flags.isByVal()) {
3043 // Copy relative to framepointer.
3044 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3045 if (!StackPtr.getNode())
3046 StackPtr = DAG.getCopyFromReg(Chain, dl,
3047 RegInfo->getStackRegister(),
3049 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3051 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3055 // Store relative to framepointer.
3056 MemOpChains2.push_back(
3057 DAG.getStore(ArgChain, dl, Arg, FIN,
3058 MachinePointerInfo::getFixedStack(FI),
3063 if (!MemOpChains2.empty())
3064 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3066 // Store the return address to the appropriate stack slot.
3067 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3068 getPointerTy(), RegInfo->getSlotSize(),
3072 // Build a sequence of copy-to-reg nodes chained together with token chain
3073 // and flag operands which copy the outgoing args into registers.
3075 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3076 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3077 RegsToPass[i].second, InFlag);
3078 InFlag = Chain.getValue(1);
3081 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3082 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3083 // In the 64-bit large code model, we have to make all calls
3084 // through a register, since the call instruction's 32-bit
3085 // pc-relative offset may not be large enough to hold the whole
3087 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3088 // If the callee is a GlobalAddress node (quite common, every direct call
3089 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3091 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3093 // We should use extra load for direct calls to dllimported functions in
3095 const GlobalValue *GV = G->getGlobal();
3096 if (!GV->hasDLLImportStorageClass()) {
3097 unsigned char OpFlags = 0;
3098 bool ExtraLoad = false;
3099 unsigned WrapperKind = ISD::DELETED_NODE;
3101 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3102 // external symbols most go through the PLT in PIC mode. If the symbol
3103 // has hidden or protected visibility, or if it is static or local, then
3104 // we don't need to use the PLT - we can directly call it.
3105 if (Subtarget->isTargetELF() &&
3106 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3107 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3108 OpFlags = X86II::MO_PLT;
3109 } else if (Subtarget->isPICStyleStubAny() &&
3110 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3111 (!Subtarget->getTargetTriple().isMacOSX() ||
3112 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3113 // PC-relative references to external symbols should go through $stub,
3114 // unless we're building with the leopard linker or later, which
3115 // automatically synthesizes these stubs.
3116 OpFlags = X86II::MO_DARWIN_STUB;
3117 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3118 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3119 // If the function is marked as non-lazy, generate an indirect call
3120 // which loads from the GOT directly. This avoids runtime overhead
3121 // at the cost of eager binding (and one extra byte of encoding).
3122 OpFlags = X86II::MO_GOTPCREL;
3123 WrapperKind = X86ISD::WrapperRIP;
3127 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3128 G->getOffset(), OpFlags);
3130 // Add a wrapper if needed.
3131 if (WrapperKind != ISD::DELETED_NODE)
3132 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3133 // Add extra indirection if needed.
3135 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3136 MachinePointerInfo::getGOT(),
3137 false, false, false, 0);
3139 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3140 unsigned char OpFlags = 0;
3142 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3143 // external symbols should go through the PLT.
3144 if (Subtarget->isTargetELF() &&
3145 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3146 OpFlags = X86II::MO_PLT;
3147 } else if (Subtarget->isPICStyleStubAny() &&
3148 (!Subtarget->getTargetTriple().isMacOSX() ||
3149 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3150 // PC-relative references to external symbols should go through $stub,
3151 // unless we're building with the leopard linker or later, which
3152 // automatically synthesizes these stubs.
3153 OpFlags = X86II::MO_DARWIN_STUB;
3156 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3158 } else if (Subtarget->isTarget64BitILP32() &&
3159 Callee->getValueType(0) == MVT::i32) {
3160 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3161 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3164 // Returns a chain & a flag for retval copy to use.
3165 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3166 SmallVector<SDValue, 8> Ops;
3168 if (!IsSibcall && isTailCall) {
3169 Chain = DAG.getCALLSEQ_END(Chain,
3170 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3171 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3172 InFlag = Chain.getValue(1);
3175 Ops.push_back(Chain);
3176 Ops.push_back(Callee);
3179 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3181 // Add argument registers to the end of the list so that they are known live
3183 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3184 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3185 RegsToPass[i].second.getValueType()));
3187 // Add a register mask operand representing the call-preserved registers.
3188 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3189 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3190 assert(Mask && "Missing call preserved mask for calling convention");
3191 Ops.push_back(DAG.getRegisterMask(Mask));
3193 if (InFlag.getNode())
3194 Ops.push_back(InFlag);
3198 //// If this is the first return lowered for this function, add the regs
3199 //// to the liveout set for the function.
3200 // This isn't right, although it's probably harmless on x86; liveouts
3201 // should be computed from returns not tail calls. Consider a void
3202 // function making a tail call to a function returning int.
3203 MF.getFrameInfo()->setHasTailCall();
3204 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3207 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3208 InFlag = Chain.getValue(1);
3210 // Create the CALLSEQ_END node.
3211 unsigned NumBytesForCalleeToPop;
3212 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3213 DAG.getTarget().Options.GuaranteedTailCallOpt))
3214 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3215 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3216 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3217 SR == StackStructReturn)
3218 // If this is a call to a struct-return function, the callee
3219 // pops the hidden struct pointer, so we have to push it back.
3220 // This is common for Darwin/X86, Linux & Mingw32 targets.
3221 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3222 NumBytesForCalleeToPop = 4;
3224 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3226 // Returns a flag for retval copy to use.
3228 Chain = DAG.getCALLSEQ_END(Chain,
3229 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3230 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3233 InFlag = Chain.getValue(1);
3236 // Handle result values, copying them out of physregs into vregs that we
3238 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3239 Ins, dl, DAG, InVals);
3242 //===----------------------------------------------------------------------===//
3243 // Fast Calling Convention (tail call) implementation
3244 //===----------------------------------------------------------------------===//
3246 // Like std call, callee cleans arguments, convention except that ECX is
3247 // reserved for storing the tail called function address. Only 2 registers are
3248 // free for argument passing (inreg). Tail call optimization is performed
3250 // * tailcallopt is enabled
3251 // * caller/callee are fastcc
3252 // On X86_64 architecture with GOT-style position independent code only local
3253 // (within module) calls are supported at the moment.
3254 // To keep the stack aligned according to platform abi the function
3255 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3256 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3257 // If a tail called function callee has more arguments than the caller the
3258 // caller needs to make sure that there is room to move the RETADDR to. This is
3259 // achieved by reserving an area the size of the argument delta right after the
3260 // original RETADDR, but before the saved framepointer or the spilled registers
3261 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3273 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3274 /// for a 16 byte align requirement.
3276 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3277 SelectionDAG& DAG) const {
3278 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3279 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3280 unsigned StackAlignment = TFI.getStackAlignment();
3281 uint64_t AlignMask = StackAlignment - 1;
3282 int64_t Offset = StackSize;
3283 unsigned SlotSize = RegInfo->getSlotSize();
3284 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3285 // Number smaller than 12 so just add the difference.
3286 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3288 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3289 Offset = ((~AlignMask) & Offset) + StackAlignment +
3290 (StackAlignment-SlotSize);
3295 /// MatchingStackOffset - Return true if the given stack call argument is
3296 /// already available in the same position (relatively) of the caller's
3297 /// incoming argument stack.
3299 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3300 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3301 const X86InstrInfo *TII) {
3302 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3304 if (Arg.getOpcode() == ISD::CopyFromReg) {
3305 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3306 if (!TargetRegisterInfo::isVirtualRegister(VR))
3308 MachineInstr *Def = MRI->getVRegDef(VR);
3311 if (!Flags.isByVal()) {
3312 if (!TII->isLoadFromStackSlot(Def, FI))
3315 unsigned Opcode = Def->getOpcode();
3316 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3317 Opcode == X86::LEA64_32r) &&
3318 Def->getOperand(1).isFI()) {
3319 FI = Def->getOperand(1).getIndex();
3320 Bytes = Flags.getByValSize();
3324 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3325 if (Flags.isByVal())
3326 // ByVal argument is passed in as a pointer but it's now being
3327 // dereferenced. e.g.
3328 // define @foo(%struct.X* %A) {
3329 // tail call @bar(%struct.X* byval %A)
3332 SDValue Ptr = Ld->getBasePtr();
3333 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3336 FI = FINode->getIndex();
3337 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3338 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3339 FI = FINode->getIndex();
3340 Bytes = Flags.getByValSize();
3344 assert(FI != INT_MAX);
3345 if (!MFI->isFixedObjectIndex(FI))
3347 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3350 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3351 /// for tail call optimization. Targets which want to do tail call
3352 /// optimization should implement this function.
3354 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3355 CallingConv::ID CalleeCC,
3357 bool isCalleeStructRet,
3358 bool isCallerStructRet,
3360 const SmallVectorImpl<ISD::OutputArg> &Outs,
3361 const SmallVectorImpl<SDValue> &OutVals,
3362 const SmallVectorImpl<ISD::InputArg> &Ins,
3363 SelectionDAG &DAG) const {
3364 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3367 // If -tailcallopt is specified, make fastcc functions tail-callable.
3368 const MachineFunction &MF = DAG.getMachineFunction();
3369 const Function *CallerF = MF.getFunction();
3371 // If the function return type is x86_fp80 and the callee return type is not,
3372 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3373 // perform a tailcall optimization here.
3374 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3377 CallingConv::ID CallerCC = CallerF->getCallingConv();
3378 bool CCMatch = CallerCC == CalleeCC;
3379 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3380 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3382 // Win64 functions have extra shadow space for argument homing. Don't do the
3383 // sibcall if the caller and callee have mismatched expectations for this
3385 if (IsCalleeWin64 != IsCallerWin64)
3388 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3389 if (IsTailCallConvention(CalleeCC) && CCMatch)
3394 // Look for obvious safe cases to perform tail call optimization that do not
3395 // require ABI changes. This is what gcc calls sibcall.
3397 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3398 // emit a special epilogue.
3399 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3400 if (RegInfo->needsStackRealignment(MF))
3403 // Also avoid sibcall optimization if either caller or callee uses struct
3404 // return semantics.
3405 if (isCalleeStructRet || isCallerStructRet)
3408 // An stdcall/thiscall caller is expected to clean up its arguments; the
3409 // callee isn't going to do that.
3410 // FIXME: this is more restrictive than needed. We could produce a tailcall
3411 // when the stack adjustment matches. For example, with a thiscall that takes
3412 // only one argument.
3413 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3414 CallerCC == CallingConv::X86_ThisCall))
3417 // Do not sibcall optimize vararg calls unless all arguments are passed via
3419 if (isVarArg && !Outs.empty()) {
3421 // Optimizing for varargs on Win64 is unlikely to be safe without
3422 // additional testing.
3423 if (IsCalleeWin64 || IsCallerWin64)
3426 SmallVector<CCValAssign, 16> ArgLocs;
3427 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3430 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3431 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3432 if (!ArgLocs[i].isRegLoc())
3436 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3437 // stack. Therefore, if it's not used by the call it is not safe to optimize
3438 // this into a sibcall.
3439 bool Unused = false;
3440 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3447 SmallVector<CCValAssign, 16> RVLocs;
3448 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3450 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3451 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3452 CCValAssign &VA = RVLocs[i];
3453 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3458 // If the calling conventions do not match, then we'd better make sure the
3459 // results are returned in the same way as what the caller expects.
3461 SmallVector<CCValAssign, 16> RVLocs1;
3462 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3464 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3466 SmallVector<CCValAssign, 16> RVLocs2;
3467 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3469 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3471 if (RVLocs1.size() != RVLocs2.size())
3473 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3474 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3476 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3478 if (RVLocs1[i].isRegLoc()) {
3479 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3482 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3488 // If the callee takes no arguments then go on to check the results of the
3490 if (!Outs.empty()) {
3491 // Check if stack adjustment is needed. For now, do not do this if any
3492 // argument is passed on the stack.
3493 SmallVector<CCValAssign, 16> ArgLocs;
3494 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3497 // Allocate shadow area for Win64
3499 CCInfo.AllocateStack(32, 8);
3501 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3502 if (CCInfo.getNextStackOffset()) {
3503 MachineFunction &MF = DAG.getMachineFunction();
3504 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3507 // Check if the arguments are already laid out in the right way as
3508 // the caller's fixed stack objects.
3509 MachineFrameInfo *MFI = MF.getFrameInfo();
3510 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3511 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3512 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3513 CCValAssign &VA = ArgLocs[i];
3514 SDValue Arg = OutVals[i];
3515 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3516 if (VA.getLocInfo() == CCValAssign::Indirect)
3518 if (!VA.isRegLoc()) {
3519 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3526 // If the tailcall address may be in a register, then make sure it's
3527 // possible to register allocate for it. In 32-bit, the call address can
3528 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3529 // callee-saved registers are restored. These happen to be the same
3530 // registers used to pass 'inreg' arguments so watch out for those.
3531 if (!Subtarget->is64Bit() &&
3532 ((!isa<GlobalAddressSDNode>(Callee) &&
3533 !isa<ExternalSymbolSDNode>(Callee)) ||
3534 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3535 unsigned NumInRegs = 0;
3536 // In PIC we need an extra register to formulate the address computation
3538 unsigned MaxInRegs =
3539 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3541 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3542 CCValAssign &VA = ArgLocs[i];
3545 unsigned Reg = VA.getLocReg();
3548 case X86::EAX: case X86::EDX: case X86::ECX:
3549 if (++NumInRegs == MaxInRegs)
3561 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3562 const TargetLibraryInfo *libInfo) const {
3563 return X86::createFastISel(funcInfo, libInfo);
3566 //===----------------------------------------------------------------------===//
3567 // Other Lowering Hooks
3568 //===----------------------------------------------------------------------===//
3570 static bool MayFoldLoad(SDValue Op) {
3571 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3574 static bool MayFoldIntoStore(SDValue Op) {
3575 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3578 static bool isTargetShuffle(unsigned Opcode) {
3580 default: return false;
3581 case X86ISD::BLENDI:
3582 case X86ISD::PSHUFB:
3583 case X86ISD::PSHUFD:
3584 case X86ISD::PSHUFHW:
3585 case X86ISD::PSHUFLW:
3587 case X86ISD::PALIGNR:
3588 case X86ISD::MOVLHPS:
3589 case X86ISD::MOVLHPD:
3590 case X86ISD::MOVHLPS:
3591 case X86ISD::MOVLPS:
3592 case X86ISD::MOVLPD:
3593 case X86ISD::MOVSHDUP:
3594 case X86ISD::MOVSLDUP:
3595 case X86ISD::MOVDDUP:
3598 case X86ISD::UNPCKL:
3599 case X86ISD::UNPCKH:
3600 case X86ISD::VPERMILPI:
3601 case X86ISD::VPERM2X128:
3602 case X86ISD::VPERMI:
3607 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3608 SDValue V1, unsigned TargetMask,
3609 SelectionDAG &DAG) {
3611 default: llvm_unreachable("Unknown x86 shuffle node");
3612 case X86ISD::PSHUFD:
3613 case X86ISD::PSHUFHW:
3614 case X86ISD::PSHUFLW:
3615 case X86ISD::VPERMILPI:
3616 case X86ISD::VPERMI:
3617 return DAG.getNode(Opc, dl, VT, V1,
3618 DAG.getConstant(TargetMask, dl, MVT::i8));
3622 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3623 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3625 default: llvm_unreachable("Unknown x86 shuffle node");
3626 case X86ISD::MOVLHPS:
3627 case X86ISD::MOVLHPD:
3628 case X86ISD::MOVHLPS:
3629 case X86ISD::MOVLPS:
3630 case X86ISD::MOVLPD:
3633 case X86ISD::UNPCKL:
3634 case X86ISD::UNPCKH:
3635 return DAG.getNode(Opc, dl, VT, V1, V2);
3639 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3640 MachineFunction &MF = DAG.getMachineFunction();
3641 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3642 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3643 int ReturnAddrIndex = FuncInfo->getRAIndex();
3645 if (ReturnAddrIndex == 0) {
3646 // Set up a frame object for the return address.
3647 unsigned SlotSize = RegInfo->getSlotSize();
3648 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3651 FuncInfo->setRAIndex(ReturnAddrIndex);
3654 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3657 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3658 bool hasSymbolicDisplacement) {
3659 // Offset should fit into 32 bit immediate field.
3660 if (!isInt<32>(Offset))
3663 // If we don't have a symbolic displacement - we don't have any extra
3665 if (!hasSymbolicDisplacement)
3668 // FIXME: Some tweaks might be needed for medium code model.
3669 if (M != CodeModel::Small && M != CodeModel::Kernel)
3672 // For small code model we assume that latest object is 16MB before end of 31
3673 // bits boundary. We may also accept pretty large negative constants knowing
3674 // that all objects are in the positive half of address space.
3675 if (M == CodeModel::Small && Offset < 16*1024*1024)
3678 // For kernel code model we know that all object resist in the negative half
3679 // of 32bits address space. We may not accept negative offsets, since they may
3680 // be just off and we may accept pretty large positive ones.
3681 if (M == CodeModel::Kernel && Offset >= 0)
3687 /// isCalleePop - Determines whether the callee is required to pop its
3688 /// own arguments. Callee pop is necessary to support tail calls.
3689 bool X86::isCalleePop(CallingConv::ID CallingConv,
3690 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3691 switch (CallingConv) {
3694 case CallingConv::X86_StdCall:
3695 case CallingConv::X86_FastCall:
3696 case CallingConv::X86_ThisCall:
3698 case CallingConv::Fast:
3699 case CallingConv::GHC:
3700 case CallingConv::HiPE:
3707 /// \brief Return true if the condition is an unsigned comparison operation.
3708 static bool isX86CCUnsigned(unsigned X86CC) {
3710 default: llvm_unreachable("Invalid integer condition!");
3711 case X86::COND_E: return true;
3712 case X86::COND_G: return false;
3713 case X86::COND_GE: return false;
3714 case X86::COND_L: return false;
3715 case X86::COND_LE: return false;
3716 case X86::COND_NE: return true;
3717 case X86::COND_B: return true;
3718 case X86::COND_A: return true;
3719 case X86::COND_BE: return true;
3720 case X86::COND_AE: return true;
3722 llvm_unreachable("covered switch fell through?!");
3725 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3726 /// specific condition code, returning the condition code and the LHS/RHS of the
3727 /// comparison to make.
3728 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3729 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3731 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3732 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3733 // X > -1 -> X == 0, jump !sign.
3734 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3735 return X86::COND_NS;
3737 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3738 // X < 0 -> X == 0, jump on sign.
3741 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3743 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3744 return X86::COND_LE;
3748 switch (SetCCOpcode) {
3749 default: llvm_unreachable("Invalid integer condition!");
3750 case ISD::SETEQ: return X86::COND_E;
3751 case ISD::SETGT: return X86::COND_G;
3752 case ISD::SETGE: return X86::COND_GE;
3753 case ISD::SETLT: return X86::COND_L;
3754 case ISD::SETLE: return X86::COND_LE;
3755 case ISD::SETNE: return X86::COND_NE;
3756 case ISD::SETULT: return X86::COND_B;
3757 case ISD::SETUGT: return X86::COND_A;
3758 case ISD::SETULE: return X86::COND_BE;
3759 case ISD::SETUGE: return X86::COND_AE;
3763 // First determine if it is required or is profitable to flip the operands.
3765 // If LHS is a foldable load, but RHS is not, flip the condition.
3766 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3767 !ISD::isNON_EXTLoad(RHS.getNode())) {
3768 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3769 std::swap(LHS, RHS);
3772 switch (SetCCOpcode) {
3778 std::swap(LHS, RHS);
3782 // On a floating point condition, the flags are set as follows:
3784 // 0 | 0 | 0 | X > Y
3785 // 0 | 0 | 1 | X < Y
3786 // 1 | 0 | 0 | X == Y
3787 // 1 | 1 | 1 | unordered
3788 switch (SetCCOpcode) {
3789 default: llvm_unreachable("Condcode should be pre-legalized away");
3791 case ISD::SETEQ: return X86::COND_E;
3792 case ISD::SETOLT: // flipped
3794 case ISD::SETGT: return X86::COND_A;
3795 case ISD::SETOLE: // flipped
3797 case ISD::SETGE: return X86::COND_AE;
3798 case ISD::SETUGT: // flipped
3800 case ISD::SETLT: return X86::COND_B;
3801 case ISD::SETUGE: // flipped
3803 case ISD::SETLE: return X86::COND_BE;
3805 case ISD::SETNE: return X86::COND_NE;
3806 case ISD::SETUO: return X86::COND_P;
3807 case ISD::SETO: return X86::COND_NP;
3809 case ISD::SETUNE: return X86::COND_INVALID;
3813 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3814 /// code. Current x86 isa includes the following FP cmov instructions:
3815 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3816 static bool hasFPCMov(unsigned X86CC) {
3832 /// isFPImmLegal - Returns true if the target can instruction select the
3833 /// specified FP immediate natively. If false, the legalizer will
3834 /// materialize the FP immediate as a load from a constant pool.
3835 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3836 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3837 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3843 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3844 ISD::LoadExtType ExtTy,
3846 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3847 // relocation target a movq or addq instruction: don't let the load shrink.
3848 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3849 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3850 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3851 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3855 /// \brief Returns true if it is beneficial to convert a load of a constant
3856 /// to just the constant itself.
3857 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3859 assert(Ty->isIntegerTy());
3861 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3862 if (BitSize == 0 || BitSize > 64)
3867 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3868 unsigned Index) const {
3869 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3872 return (Index == 0 || Index == ResVT.getVectorNumElements());
3875 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3876 // Speculate cttz only if we can directly use TZCNT.
3877 return Subtarget->hasBMI();
3880 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3881 // Speculate ctlz only if we can directly use LZCNT.
3882 return Subtarget->hasLZCNT();
3885 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3886 /// the specified range (L, H].
3887 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3888 return (Val < 0) || (Val >= Low && Val < Hi);
3891 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3892 /// specified value.
3893 static bool isUndefOrEqual(int Val, int CmpVal) {
3894 return (Val < 0 || Val == CmpVal);
3897 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3898 /// from position Pos and ending in Pos+Size, falls within the specified
3899 /// sequential range (Low, Low+Size]. or is undef.
3900 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3901 unsigned Pos, unsigned Size, int Low) {
3902 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3903 if (!isUndefOrEqual(Mask[i], Low))
3908 /// isVEXTRACTIndex - Return true if the specified
3909 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3910 /// suitable for instruction that extract 128 or 256 bit vectors
3911 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3912 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3913 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3916 // The index should be aligned on a vecWidth-bit boundary.
3918 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3920 MVT VT = N->getSimpleValueType(0);
3921 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3922 bool Result = (Index * ElSize) % vecWidth == 0;
3927 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3928 /// operand specifies a subvector insert that is suitable for input to
3929 /// insertion of 128 or 256-bit subvectors
3930 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3931 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3932 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3934 // The index should be aligned on a vecWidth-bit boundary.
3936 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3938 MVT VT = N->getSimpleValueType(0);
3939 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3940 bool Result = (Index * ElSize) % vecWidth == 0;
3945 bool X86::isVINSERT128Index(SDNode *N) {
3946 return isVINSERTIndex(N, 128);
3949 bool X86::isVINSERT256Index(SDNode *N) {
3950 return isVINSERTIndex(N, 256);
3953 bool X86::isVEXTRACT128Index(SDNode *N) {
3954 return isVEXTRACTIndex(N, 128);
3957 bool X86::isVEXTRACT256Index(SDNode *N) {
3958 return isVEXTRACTIndex(N, 256);
3961 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3962 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3963 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3964 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3967 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3969 MVT VecVT = N->getOperand(0).getSimpleValueType();
3970 MVT ElVT = VecVT.getVectorElementType();
3972 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3973 return Index / NumElemsPerChunk;
3976 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3977 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3978 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3979 llvm_unreachable("Illegal insert subvector for VINSERT");
3982 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3984 MVT VecVT = N->getSimpleValueType(0);
3985 MVT ElVT = VecVT.getVectorElementType();
3987 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3988 return Index / NumElemsPerChunk;
3991 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3992 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3993 /// and VINSERTI128 instructions.
3994 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3995 return getExtractVEXTRACTImmediate(N, 128);
3998 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3999 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4000 /// and VINSERTI64x4 instructions.
4001 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4002 return getExtractVEXTRACTImmediate(N, 256);
4005 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4006 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4007 /// and VINSERTI128 instructions.
4008 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4009 return getInsertVINSERTImmediate(N, 128);
4012 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4013 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4014 /// and VINSERTI64x4 instructions.
4015 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4016 return getInsertVINSERTImmediate(N, 256);
4019 /// isZero - Returns true if Elt is a constant integer zero
4020 static bool isZero(SDValue V) {
4021 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4022 return C && C->isNullValue();
4025 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4027 bool X86::isZeroNode(SDValue Elt) {
4030 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4031 return CFP->getValueAPF().isPosZero();
4035 /// getZeroVector - Returns a vector of specified type with all zero elements.
4037 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4038 SelectionDAG &DAG, SDLoc dl) {
4039 assert(VT.isVector() && "Expected a vector type");
4041 // Always build SSE zero vectors as <4 x i32> bitcasted
4042 // to their dest type. This ensures they get CSE'd.
4044 if (VT.is128BitVector()) { // SSE
4045 if (Subtarget->hasSSE2()) { // SSE2
4046 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4047 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4049 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4050 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4052 } else if (VT.is256BitVector()) { // AVX
4053 if (Subtarget->hasInt256()) { // AVX2
4054 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4055 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4056 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4058 // 256-bit logic and arithmetic instructions in AVX are all
4059 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4060 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4061 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4062 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4064 } else if (VT.is512BitVector()) { // AVX-512
4065 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4066 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4067 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4068 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4069 } else if (VT.getScalarType() == MVT::i1) {
4071 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4072 && "Unexpected vector type");
4073 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4074 && "Unexpected vector type");
4075 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4076 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4077 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4079 llvm_unreachable("Unexpected vector type");
4081 return DAG.getBitcast(VT, Vec);
4084 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4085 SelectionDAG &DAG, SDLoc dl,
4086 unsigned vectorWidth) {
4087 assert((vectorWidth == 128 || vectorWidth == 256) &&
4088 "Unsupported vector width");
4089 EVT VT = Vec.getValueType();
4090 EVT ElVT = VT.getVectorElementType();
4091 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4092 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4093 VT.getVectorNumElements()/Factor);
4095 // Extract from UNDEF is UNDEF.
4096 if (Vec.getOpcode() == ISD::UNDEF)
4097 return DAG.getUNDEF(ResultVT);
4099 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4102 // This is the index of the first element of the vectorWidth-bit chunk
4104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4107 // If the input is a buildvector just emit a smaller one.
4108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4120 /// instructions or a simple subregister reference. Idx is an index in the
4121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4122 /// lowering EXTRACT_VECTOR_ELT operations easier.
4123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4124 SelectionDAG &DAG, SDLoc dl) {
4125 assert((Vec.getValueType().is256BitVector() ||
4126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4132 SelectionDAG &DAG, SDLoc dl) {
4133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4138 unsigned IdxVal, SelectionDAG &DAG,
4139 SDLoc dl, unsigned vectorWidth) {
4140 assert((vectorWidth == 128 || vectorWidth == 256) &&
4141 "Unsupported vector width");
4142 // Inserting UNDEF is Result
4143 if (Vec.getOpcode() == ISD::UNDEF)
4145 EVT VT = Vec.getValueType();
4146 EVT ElVT = VT.getVectorElementType();
4147 EVT ResultVT = Result.getValueType();
4149 // Insert the relevant vectorWidth bits.
4150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4152 // This is the index of the first element of the vectorWidth-bit chunk
4154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4164 /// simple superregister reference. Idx is an index in the 128 bits
4165 /// we want. It need not be aligned to a 128-bit boundary. That makes
4166 /// lowering INSERT_VECTOR_ELT operations easier.
4167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4168 SelectionDAG &DAG, SDLoc dl) {
4169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4171 // For insertion into the zero index (low half) of a 256-bit vector, it is
4172 // more efficient to generate a blend with immediate instead of an insert*128.
4173 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4174 // extend the subvector to the size of the result vector. Make sure that
4175 // we are not recursing on that node by checking for undef here.
4176 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4177 Result.getOpcode() != ISD::UNDEF) {
4178 EVT ResultVT = Result.getValueType();
4179 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4180 SDValue Undef = DAG.getUNDEF(ResultVT);
4181 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4184 // The blend instruction, and therefore its mask, depend on the data type.
4185 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4186 if (ScalarType.isFloatingPoint()) {
4187 // Choose either vblendps (float) or vblendpd (double).
4188 unsigned ScalarSize = ScalarType.getSizeInBits();
4189 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4190 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4191 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4192 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4195 const X86Subtarget &Subtarget =
4196 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4198 // AVX2 is needed for 256-bit integer blend support.
4199 // Integers must be cast to 32-bit because there is only vpblendd;
4200 // vpblendw can't be used for this because it has a handicapped mask.
4202 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4203 // is still more efficient than using the wrong domain vinsertf128 that
4204 // will be created by InsertSubVector().
4205 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4207 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4208 Vec256 = DAG.getBitcast(CastVT, Vec256);
4209 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4210 return DAG.getBitcast(ResultVT, Vec256);
4213 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4216 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4217 SelectionDAG &DAG, SDLoc dl) {
4218 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4219 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4222 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4223 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4224 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4225 /// large BUILD_VECTORS.
4226 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4227 unsigned NumElems, SelectionDAG &DAG,
4229 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4230 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4233 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4234 unsigned NumElems, SelectionDAG &DAG,
4236 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4237 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4240 /// getOnesVector - Returns a vector of specified type with all bits set.
4241 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4242 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4243 /// Then bitcast to their original type, ensuring they get CSE'd.
4244 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4246 assert(VT.isVector() && "Expected a vector type");
4248 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4250 if (VT.is256BitVector()) {
4251 if (HasInt256) { // AVX2
4252 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4253 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4255 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4256 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4258 } else if (VT.is128BitVector()) {
4259 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4261 llvm_unreachable("Unexpected vector type");
4263 return DAG.getBitcast(VT, Vec);
4266 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4267 /// operation of specified width.
4268 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4270 unsigned NumElems = VT.getVectorNumElements();
4271 SmallVector<int, 8> Mask;
4272 Mask.push_back(NumElems);
4273 for (unsigned i = 1; i != NumElems; ++i)
4275 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4278 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4279 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4281 unsigned NumElems = VT.getVectorNumElements();
4282 SmallVector<int, 8> Mask;
4283 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4285 Mask.push_back(i + NumElems);
4287 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4290 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4291 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4293 unsigned NumElems = VT.getVectorNumElements();
4294 SmallVector<int, 8> Mask;
4295 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4296 Mask.push_back(i + Half);
4297 Mask.push_back(i + NumElems + Half);
4299 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4302 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4303 /// vector of zero or undef vector. This produces a shuffle where the low
4304 /// element of V2 is swizzled into the zero/undef vector, landing at element
4305 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4306 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4308 const X86Subtarget *Subtarget,
4309 SelectionDAG &DAG) {
4310 MVT VT = V2.getSimpleValueType();
4312 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4313 unsigned NumElems = VT.getVectorNumElements();
4314 SmallVector<int, 16> MaskVec;
4315 for (unsigned i = 0; i != NumElems; ++i)
4316 // If this is the insertion idx, put the low elt of V2 here.
4317 MaskVec.push_back(i == Idx ? NumElems : i);
4318 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4321 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4322 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4323 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4324 /// shuffles which use a single input multiple times, and in those cases it will
4325 /// adjust the mask to only have indices within that single input.
4326 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4327 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4328 unsigned NumElems = VT.getVectorNumElements();
4332 bool IsFakeUnary = false;
4333 switch(N->getOpcode()) {
4334 case X86ISD::BLENDI:
4335 ImmN = N->getOperand(N->getNumOperands()-1);
4336 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4339 ImmN = N->getOperand(N->getNumOperands()-1);
4340 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4341 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4343 case X86ISD::UNPCKH:
4344 DecodeUNPCKHMask(VT, Mask);
4345 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4347 case X86ISD::UNPCKL:
4348 DecodeUNPCKLMask(VT, Mask);
4349 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4351 case X86ISD::MOVHLPS:
4352 DecodeMOVHLPSMask(NumElems, Mask);
4353 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4355 case X86ISD::MOVLHPS:
4356 DecodeMOVLHPSMask(NumElems, Mask);
4357 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4359 case X86ISD::PALIGNR:
4360 ImmN = N->getOperand(N->getNumOperands()-1);
4361 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4363 case X86ISD::PSHUFD:
4364 case X86ISD::VPERMILPI:
4365 ImmN = N->getOperand(N->getNumOperands()-1);
4366 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4369 case X86ISD::PSHUFHW:
4370 ImmN = N->getOperand(N->getNumOperands()-1);
4371 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4374 case X86ISD::PSHUFLW:
4375 ImmN = N->getOperand(N->getNumOperands()-1);
4376 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4379 case X86ISD::PSHUFB: {
4381 SDValue MaskNode = N->getOperand(1);
4382 while (MaskNode->getOpcode() == ISD::BITCAST)
4383 MaskNode = MaskNode->getOperand(0);
4385 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4386 // If we have a build-vector, then things are easy.
4387 EVT VT = MaskNode.getValueType();
4388 assert(VT.isVector() &&
4389 "Can't produce a non-vector with a build_vector!");
4390 if (!VT.isInteger())
4393 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4395 SmallVector<uint64_t, 32> RawMask;
4396 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4397 SDValue Op = MaskNode->getOperand(i);
4398 if (Op->getOpcode() == ISD::UNDEF) {
4399 RawMask.push_back((uint64_t)SM_SentinelUndef);
4402 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4405 APInt MaskElement = CN->getAPIntValue();
4407 // We now have to decode the element which could be any integer size and
4408 // extract each byte of it.
4409 for (int j = 0; j < NumBytesPerElement; ++j) {
4410 // Note that this is x86 and so always little endian: the low byte is
4411 // the first byte of the mask.
4412 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4413 MaskElement = MaskElement.lshr(8);
4416 DecodePSHUFBMask(RawMask, Mask);
4420 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4424 SDValue Ptr = MaskLoad->getBasePtr();
4425 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4426 Ptr->getOpcode() == X86ISD::WrapperRIP)
4427 Ptr = Ptr->getOperand(0);
4429 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4430 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4433 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4434 DecodePSHUFBMask(C, Mask);
4442 case X86ISD::VPERMI:
4443 ImmN = N->getOperand(N->getNumOperands()-1);
4444 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4449 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4451 case X86ISD::VPERM2X128:
4452 ImmN = N->getOperand(N->getNumOperands()-1);
4453 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4454 if (Mask.empty()) return false;
4456 case X86ISD::MOVSLDUP:
4457 DecodeMOVSLDUPMask(VT, Mask);
4460 case X86ISD::MOVSHDUP:
4461 DecodeMOVSHDUPMask(VT, Mask);
4464 case X86ISD::MOVDDUP:
4465 DecodeMOVDDUPMask(VT, Mask);
4468 case X86ISD::MOVLHPD:
4469 case X86ISD::MOVLPD:
4470 case X86ISD::MOVLPS:
4471 // Not yet implemented
4473 default: llvm_unreachable("unknown target shuffle node");
4476 // If we have a fake unary shuffle, the shuffle mask is spread across two
4477 // inputs that are actually the same node. Re-map the mask to always point
4478 // into the first input.
4481 if (M >= (int)Mask.size())
4487 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4488 /// element of the result of the vector shuffle.
4489 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4492 return SDValue(); // Limit search depth.
4494 SDValue V = SDValue(N, 0);
4495 EVT VT = V.getValueType();
4496 unsigned Opcode = V.getOpcode();
4498 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4499 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4500 int Elt = SV->getMaskElt(Index);
4503 return DAG.getUNDEF(VT.getVectorElementType());
4505 unsigned NumElems = VT.getVectorNumElements();
4506 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4507 : SV->getOperand(1);
4508 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4511 // Recurse into target specific vector shuffles to find scalars.
4512 if (isTargetShuffle(Opcode)) {
4513 MVT ShufVT = V.getSimpleValueType();
4514 unsigned NumElems = ShufVT.getVectorNumElements();
4515 SmallVector<int, 16> ShuffleMask;
4518 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4521 int Elt = ShuffleMask[Index];
4523 return DAG.getUNDEF(ShufVT.getVectorElementType());
4525 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4527 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4531 // Actual nodes that may contain scalar elements
4532 if (Opcode == ISD::BITCAST) {
4533 V = V.getOperand(0);
4534 EVT SrcVT = V.getValueType();
4535 unsigned NumElems = VT.getVectorNumElements();
4537 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4541 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4542 return (Index == 0) ? V.getOperand(0)
4543 : DAG.getUNDEF(VT.getVectorElementType());
4545 if (V.getOpcode() == ISD::BUILD_VECTOR)
4546 return V.getOperand(Index);
4551 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4553 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4554 unsigned NumNonZero, unsigned NumZero,
4556 const X86Subtarget* Subtarget,
4557 const TargetLowering &TLI) {
4565 // SSE4.1 - use PINSRB to insert each byte directly.
4566 if (Subtarget->hasSSE41()) {
4567 for (unsigned i = 0; i < 16; ++i) {
4568 bool isNonZero = (NonZeros & (1 << i)) != 0;
4572 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4574 V = DAG.getUNDEF(MVT::v16i8);
4577 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4578 MVT::v16i8, V, Op.getOperand(i),
4579 DAG.getIntPtrConstant(i, dl));
4586 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4587 for (unsigned i = 0; i < 16; ++i) {
4588 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4589 if (ThisIsNonZero && First) {
4591 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4593 V = DAG.getUNDEF(MVT::v8i16);
4598 SDValue ThisElt, LastElt;
4599 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4600 if (LastIsNonZero) {
4601 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4602 MVT::i16, Op.getOperand(i-1));
4604 if (ThisIsNonZero) {
4605 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4606 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4607 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4609 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4613 if (ThisElt.getNode())
4614 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4615 DAG.getIntPtrConstant(i/2, dl));
4619 return DAG.getBitcast(MVT::v16i8, V);
4622 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4624 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4625 unsigned NumNonZero, unsigned NumZero,
4627 const X86Subtarget* Subtarget,
4628 const TargetLowering &TLI) {
4635 for (unsigned i = 0; i < 8; ++i) {
4636 bool isNonZero = (NonZeros & (1 << i)) != 0;
4640 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4642 V = DAG.getUNDEF(MVT::v8i16);
4645 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4646 MVT::v8i16, V, Op.getOperand(i),
4647 DAG.getIntPtrConstant(i, dl));
4654 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4655 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4656 const X86Subtarget *Subtarget,
4657 const TargetLowering &TLI) {
4658 // Find all zeroable elements.
4659 std::bitset<4> Zeroable;
4660 for (int i=0; i < 4; ++i) {
4661 SDValue Elt = Op->getOperand(i);
4662 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4664 assert(Zeroable.size() - Zeroable.count() > 1 &&
4665 "We expect at least two non-zero elements!");
4667 // We only know how to deal with build_vector nodes where elements are either
4668 // zeroable or extract_vector_elt with constant index.
4669 SDValue FirstNonZero;
4670 unsigned FirstNonZeroIdx;
4671 for (unsigned i=0; i < 4; ++i) {
4674 SDValue Elt = Op->getOperand(i);
4675 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4676 !isa<ConstantSDNode>(Elt.getOperand(1)))
4678 // Make sure that this node is extracting from a 128-bit vector.
4679 MVT VT = Elt.getOperand(0).getSimpleValueType();
4680 if (!VT.is128BitVector())
4682 if (!FirstNonZero.getNode()) {
4684 FirstNonZeroIdx = i;
4688 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4689 SDValue V1 = FirstNonZero.getOperand(0);
4690 MVT VT = V1.getSimpleValueType();
4692 // See if this build_vector can be lowered as a blend with zero.
4694 unsigned EltMaskIdx, EltIdx;
4696 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4697 if (Zeroable[EltIdx]) {
4698 // The zero vector will be on the right hand side.
4699 Mask[EltIdx] = EltIdx+4;
4703 Elt = Op->getOperand(EltIdx);
4704 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4705 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4706 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4708 Mask[EltIdx] = EltIdx;
4712 // Let the shuffle legalizer deal with blend operations.
4713 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4714 if (V1.getSimpleValueType() != VT)
4715 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4716 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4719 // See if we can lower this build_vector to a INSERTPS.
4720 if (!Subtarget->hasSSE41())
4723 SDValue V2 = Elt.getOperand(0);
4724 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4727 bool CanFold = true;
4728 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4732 SDValue Current = Op->getOperand(i);
4733 SDValue SrcVector = Current->getOperand(0);
4736 CanFold = SrcVector == V1 &&
4737 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4743 assert(V1.getNode() && "Expected at least two non-zero elements!");
4744 if (V1.getSimpleValueType() != MVT::v4f32)
4745 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4746 if (V2.getSimpleValueType() != MVT::v4f32)
4747 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4749 // Ok, we can emit an INSERTPS instruction.
4750 unsigned ZMask = Zeroable.to_ulong();
4752 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4753 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4755 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4756 DAG.getIntPtrConstant(InsertPSMask, DL));
4757 return DAG.getBitcast(VT, Result);
4760 /// Return a vector logical shift node.
4761 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4762 unsigned NumBits, SelectionDAG &DAG,
4763 const TargetLowering &TLI, SDLoc dl) {
4764 assert(VT.is128BitVector() && "Unknown type for VShift");
4765 MVT ShVT = MVT::v2i64;
4766 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4767 SrcOp = DAG.getBitcast(ShVT, SrcOp);
4768 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4769 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4770 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4771 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4775 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4777 // Check if the scalar load can be widened into a vector load. And if
4778 // the address is "base + cst" see if the cst can be "absorbed" into
4779 // the shuffle mask.
4780 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4781 SDValue Ptr = LD->getBasePtr();
4782 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4784 EVT PVT = LD->getValueType(0);
4785 if (PVT != MVT::i32 && PVT != MVT::f32)
4790 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4791 FI = FINode->getIndex();
4793 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4794 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4795 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4796 Offset = Ptr.getConstantOperandVal(1);
4797 Ptr = Ptr.getOperand(0);
4802 // FIXME: 256-bit vector instructions don't require a strict alignment,
4803 // improve this code to support it better.
4804 unsigned RequiredAlign = VT.getSizeInBits()/8;
4805 SDValue Chain = LD->getChain();
4806 // Make sure the stack object alignment is at least 16 or 32.
4807 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4808 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4809 if (MFI->isFixedObjectIndex(FI)) {
4810 // Can't change the alignment. FIXME: It's possible to compute
4811 // the exact stack offset and reference FI + adjust offset instead.
4812 // If someone *really* cares about this. That's the way to implement it.
4815 MFI->setObjectAlignment(FI, RequiredAlign);
4819 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4820 // Ptr + (Offset & ~15).
4823 if ((Offset % RequiredAlign) & 3)
4825 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4828 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4829 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4832 int EltNo = (Offset - StartOffset) >> 2;
4833 unsigned NumElems = VT.getVectorNumElements();
4835 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4836 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4837 LD->getPointerInfo().getWithOffset(StartOffset),
4838 false, false, false, 0);
4840 SmallVector<int, 8> Mask(NumElems, EltNo);
4842 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4848 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4849 /// elements can be replaced by a single large load which has the same value as
4850 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4852 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4854 /// FIXME: we'd also like to handle the case where the last elements are zero
4855 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4856 /// There's even a handy isZeroNode for that purpose.
4857 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4858 SDLoc &DL, SelectionDAG &DAG,
4859 bool isAfterLegalize) {
4860 unsigned NumElems = Elts.size();
4862 LoadSDNode *LDBase = nullptr;
4863 unsigned LastLoadedElt = -1U;
4865 // For each element in the initializer, see if we've found a load or an undef.
4866 // If we don't find an initial load element, or later load elements are
4867 // non-consecutive, bail out.
4868 for (unsigned i = 0; i < NumElems; ++i) {
4869 SDValue Elt = Elts[i];
4870 // Look through a bitcast.
4871 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4872 Elt = Elt.getOperand(0);
4873 if (!Elt.getNode() ||
4874 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4877 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4879 LDBase = cast<LoadSDNode>(Elt.getNode());
4883 if (Elt.getOpcode() == ISD::UNDEF)
4886 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4887 EVT LdVT = Elt.getValueType();
4888 // Each loaded element must be the correct fractional portion of the
4889 // requested vector load.
4890 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4892 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4897 // If we have found an entire vector of loads and undefs, then return a large
4898 // load of the entire vector width starting at the base pointer. If we found
4899 // consecutive loads for the low half, generate a vzext_load node.
4900 if (LastLoadedElt == NumElems - 1) {
4901 assert(LDBase && "Did not find base load for merging consecutive loads");
4902 EVT EltVT = LDBase->getValueType(0);
4903 // Ensure that the input vector size for the merged loads matches the
4904 // cumulative size of the input elements.
4905 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4908 if (isAfterLegalize &&
4909 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4912 SDValue NewLd = SDValue();
4914 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4915 LDBase->getPointerInfo(), LDBase->isVolatile(),
4916 LDBase->isNonTemporal(), LDBase->isInvariant(),
4917 LDBase->getAlignment());
4919 if (LDBase->hasAnyUseOfValue(1)) {
4920 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4922 SDValue(NewLd.getNode(), 1));
4923 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4924 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4925 SDValue(NewLd.getNode(), 1));
4931 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4932 //of a v4i32 / v4f32. It's probably worth generalizing.
4933 EVT EltVT = VT.getVectorElementType();
4934 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4935 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4936 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4937 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4939 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4940 LDBase->getPointerInfo(),
4941 LDBase->getAlignment(),
4942 false/*isVolatile*/, true/*ReadMem*/,
4945 // Make sure the newly-created LOAD is in the same position as LDBase in
4946 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4947 // update uses of LDBase's output chain to use the TokenFactor.
4948 if (LDBase->hasAnyUseOfValue(1)) {
4949 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4950 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4951 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4952 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4953 SDValue(ResNode.getNode(), 1));
4956 return DAG.getBitcast(VT, ResNode);
4961 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4962 /// to generate a splat value for the following cases:
4963 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4964 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4965 /// a scalar load, or a constant.
4966 /// The VBROADCAST node is returned when a pattern is found,
4967 /// or SDValue() otherwise.
4968 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4969 SelectionDAG &DAG) {
4970 // VBROADCAST requires AVX.
4971 // TODO: Splats could be generated for non-AVX CPUs using SSE
4972 // instructions, but there's less potential gain for only 128-bit vectors.
4973 if (!Subtarget->hasAVX())
4976 MVT VT = Op.getSimpleValueType();
4979 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4980 "Unsupported vector type for broadcast.");
4985 switch (Op.getOpcode()) {
4987 // Unknown pattern found.
4990 case ISD::BUILD_VECTOR: {
4991 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4992 BitVector UndefElements;
4993 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4995 // We need a splat of a single value to use broadcast, and it doesn't
4996 // make any sense if the value is only in one element of the vector.
4997 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5001 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5002 Ld.getOpcode() == ISD::ConstantFP);
5004 // Make sure that all of the users of a non-constant load are from the
5005 // BUILD_VECTOR node.
5006 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5011 case ISD::VECTOR_SHUFFLE: {
5012 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5014 // Shuffles must have a splat mask where the first element is
5016 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5019 SDValue Sc = Op.getOperand(0);
5020 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5021 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5023 if (!Subtarget->hasInt256())
5026 // Use the register form of the broadcast instruction available on AVX2.
5027 if (VT.getSizeInBits() >= 256)
5028 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5029 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5032 Ld = Sc.getOperand(0);
5033 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5034 Ld.getOpcode() == ISD::ConstantFP);
5036 // The scalar_to_vector node and the suspected
5037 // load node must have exactly one user.
5038 // Constants may have multiple users.
5040 // AVX-512 has register version of the broadcast
5041 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5042 Ld.getValueType().getSizeInBits() >= 32;
5043 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5050 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5051 bool IsGE256 = (VT.getSizeInBits() >= 256);
5053 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5054 // instruction to save 8 or more bytes of constant pool data.
5055 // TODO: If multiple splats are generated to load the same constant,
5056 // it may be detrimental to overall size. There needs to be a way to detect
5057 // that condition to know if this is truly a size win.
5058 const Function *F = DAG.getMachineFunction().getFunction();
5059 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5061 // Handle broadcasting a single constant scalar from the constant pool
5063 // On Sandybridge (no AVX2), it is still better to load a constant vector
5064 // from the constant pool and not to broadcast it from a scalar.
5065 // But override that restriction when optimizing for size.
5066 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5067 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5068 EVT CVT = Ld.getValueType();
5069 assert(!CVT.isVector() && "Must not broadcast a vector type");
5071 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5072 // For size optimization, also splat v2f64 and v2i64, and for size opt
5073 // with AVX2, also splat i8 and i16.
5074 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5075 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5076 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5077 const Constant *C = nullptr;
5078 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5079 C = CI->getConstantIntValue();
5080 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5081 C = CF->getConstantFPValue();
5083 assert(C && "Invalid constant type");
5085 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5086 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5087 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5088 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5089 MachinePointerInfo::getConstantPool(),
5090 false, false, false, Alignment);
5092 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5096 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5098 // Handle AVX2 in-register broadcasts.
5099 if (!IsLoad && Subtarget->hasInt256() &&
5100 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5101 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5103 // The scalar source must be a normal load.
5107 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5108 (Subtarget->hasVLX() && ScalarSize == 64))
5109 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5111 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5112 // double since there is no vbroadcastsd xmm
5113 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5114 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5115 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5118 // Unsupported broadcast.
5122 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5123 /// underlying vector and index.
5125 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5127 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5129 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5130 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5133 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5135 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5137 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5138 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5141 // In this case the vector is the extract_subvector expression and the index
5142 // is 2, as specified by the shuffle.
5143 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5144 SDValue ShuffleVec = SVOp->getOperand(0);
5145 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5146 assert(ShuffleVecVT.getVectorElementType() ==
5147 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5149 int ShuffleIdx = SVOp->getMaskElt(Idx);
5150 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5151 ExtractedFromVec = ShuffleVec;
5157 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5158 MVT VT = Op.getSimpleValueType();
5160 // Skip if insert_vec_elt is not supported.
5161 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5162 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5166 unsigned NumElems = Op.getNumOperands();
5170 SmallVector<unsigned, 4> InsertIndices;
5171 SmallVector<int, 8> Mask(NumElems, -1);
5173 for (unsigned i = 0; i != NumElems; ++i) {
5174 unsigned Opc = Op.getOperand(i).getOpcode();
5176 if (Opc == ISD::UNDEF)
5179 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5180 // Quit if more than 1 elements need inserting.
5181 if (InsertIndices.size() > 1)
5184 InsertIndices.push_back(i);
5188 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5189 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5190 // Quit if non-constant index.
5191 if (!isa<ConstantSDNode>(ExtIdx))
5193 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5195 // Quit if extracted from vector of different type.
5196 if (ExtractedFromVec.getValueType() != VT)
5199 if (!VecIn1.getNode())
5200 VecIn1 = ExtractedFromVec;
5201 else if (VecIn1 != ExtractedFromVec) {
5202 if (!VecIn2.getNode())
5203 VecIn2 = ExtractedFromVec;
5204 else if (VecIn2 != ExtractedFromVec)
5205 // Quit if more than 2 vectors to shuffle
5209 if (ExtractedFromVec == VecIn1)
5211 else if (ExtractedFromVec == VecIn2)
5212 Mask[i] = Idx + NumElems;
5215 if (!VecIn1.getNode())
5218 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5219 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5220 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5221 unsigned Idx = InsertIndices[i];
5222 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5223 DAG.getIntPtrConstant(Idx, DL));
5229 static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
5230 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5231 Op.getScalarValueSizeInBits() == 1 &&
5232 "Can not convert non-constant vector");
5233 uint64_t Immediate = 0;
5234 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5235 SDValue In = Op.getOperand(idx);
5236 if (In.getOpcode() != ISD::UNDEF)
5237 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5241 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5242 return DAG.getConstant(Immediate, dl, VT);
5244 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5246 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5248 MVT VT = Op.getSimpleValueType();
5249 assert((VT.getVectorElementType() == MVT::i1) &&
5250 "Unexpected type in LowerBUILD_VECTORvXi1!");
5253 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5254 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5255 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5256 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5259 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5260 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5261 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5262 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5265 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5266 SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
5267 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5268 return DAG.getBitcast(VT, Imm);
5269 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5270 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5271 DAG.getIntPtrConstant(0, dl));
5274 // Vector has one or more non-const elements
5275 uint64_t Immediate = 0;
5276 SmallVector<unsigned, 16> NonConstIdx;
5277 bool IsSplat = true;
5278 bool HasConstElts = false;
5280 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5281 SDValue In = Op.getOperand(idx);
5282 if (In.getOpcode() == ISD::UNDEF)
5284 if (!isa<ConstantSDNode>(In))
5285 NonConstIdx.push_back(idx);
5287 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5288 HasConstElts = true;
5292 else if (In != Op.getOperand(SplatIdx))
5296 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5298 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5299 DAG.getConstant(1, dl, VT),
5300 DAG.getConstant(0, dl, VT));
5302 // insert elements one by one
5306 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5307 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5309 else if (HasConstElts)
5310 Imm = DAG.getConstant(0, dl, VT);
5312 Imm = DAG.getUNDEF(VT);
5313 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5314 DstVec = DAG.getBitcast(VT, Imm);
5316 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5317 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5318 DAG.getIntPtrConstant(0, dl));
5321 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5322 unsigned InsertIdx = NonConstIdx[i];
5323 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5324 Op.getOperand(InsertIdx),
5325 DAG.getIntPtrConstant(InsertIdx, dl));
5330 /// \brief Return true if \p N implements a horizontal binop and return the
5331 /// operands for the horizontal binop into V0 and V1.
5333 /// This is a helper function of LowerToHorizontalOp().
5334 /// This function checks that the build_vector \p N in input implements a
5335 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5336 /// operation to match.
5337 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5338 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5339 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5342 /// This function only analyzes elements of \p N whose indices are
5343 /// in range [BaseIdx, LastIdx).
5344 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5346 unsigned BaseIdx, unsigned LastIdx,
5347 SDValue &V0, SDValue &V1) {
5348 EVT VT = N->getValueType(0);
5350 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5351 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5352 "Invalid Vector in input!");
5354 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5355 bool CanFold = true;
5356 unsigned ExpectedVExtractIdx = BaseIdx;
5357 unsigned NumElts = LastIdx - BaseIdx;
5358 V0 = DAG.getUNDEF(VT);
5359 V1 = DAG.getUNDEF(VT);
5361 // Check if N implements a horizontal binop.
5362 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5363 SDValue Op = N->getOperand(i + BaseIdx);
5366 if (Op->getOpcode() == ISD::UNDEF) {
5367 // Update the expected vector extract index.
5368 if (i * 2 == NumElts)
5369 ExpectedVExtractIdx = BaseIdx;
5370 ExpectedVExtractIdx += 2;
5374 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5379 SDValue Op0 = Op.getOperand(0);
5380 SDValue Op1 = Op.getOperand(1);
5382 // Try to match the following pattern:
5383 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5384 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5385 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5386 Op0.getOperand(0) == Op1.getOperand(0) &&
5387 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5388 isa<ConstantSDNode>(Op1.getOperand(1)));
5392 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5393 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5395 if (i * 2 < NumElts) {
5396 if (V0.getOpcode() == ISD::UNDEF) {
5397 V0 = Op0.getOperand(0);
5398 if (V0.getValueType() != VT)
5402 if (V1.getOpcode() == ISD::UNDEF) {
5403 V1 = Op0.getOperand(0);
5404 if (V1.getValueType() != VT)
5407 if (i * 2 == NumElts)
5408 ExpectedVExtractIdx = BaseIdx;
5411 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5412 if (I0 == ExpectedVExtractIdx)
5413 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5414 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5415 // Try to match the following dag sequence:
5416 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5417 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5421 ExpectedVExtractIdx += 2;
5427 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5428 /// a concat_vector.
5430 /// This is a helper function of LowerToHorizontalOp().
5431 /// This function expects two 256-bit vectors called V0 and V1.
5432 /// At first, each vector is split into two separate 128-bit vectors.
5433 /// Then, the resulting 128-bit vectors are used to implement two
5434 /// horizontal binary operations.
5436 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5438 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5439 /// the two new horizontal binop.
5440 /// When Mode is set, the first horizontal binop dag node would take as input
5441 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5442 /// horizontal binop dag node would take as input the lower 128-bit of V1
5443 /// and the upper 128-bit of V1.
5445 /// HADD V0_LO, V0_HI
5446 /// HADD V1_LO, V1_HI
5448 /// Otherwise, the first horizontal binop dag node takes as input the lower
5449 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5450 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5452 /// HADD V0_LO, V1_LO
5453 /// HADD V0_HI, V1_HI
5455 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5456 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5457 /// the upper 128-bits of the result.
5458 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5459 SDLoc DL, SelectionDAG &DAG,
5460 unsigned X86Opcode, bool Mode,
5461 bool isUndefLO, bool isUndefHI) {
5462 EVT VT = V0.getValueType();
5463 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5464 "Invalid nodes in input!");
5466 unsigned NumElts = VT.getVectorNumElements();
5467 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5468 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5469 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5470 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5471 EVT NewVT = V0_LO.getValueType();
5473 SDValue LO = DAG.getUNDEF(NewVT);
5474 SDValue HI = DAG.getUNDEF(NewVT);
5477 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5478 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5479 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5480 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5481 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5483 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5484 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5485 V1_LO->getOpcode() != ISD::UNDEF))
5486 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5488 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5489 V1_HI->getOpcode() != ISD::UNDEF))
5490 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5493 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5496 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5498 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5499 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5500 EVT VT = BV->getValueType(0);
5501 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5502 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5506 unsigned NumElts = VT.getVectorNumElements();
5507 SDValue InVec0 = DAG.getUNDEF(VT);
5508 SDValue InVec1 = DAG.getUNDEF(VT);
5510 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5511 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5513 // Odd-numbered elements in the input build vector are obtained from
5514 // adding two integer/float elements.
5515 // Even-numbered elements in the input build vector are obtained from
5516 // subtracting two integer/float elements.
5517 unsigned ExpectedOpcode = ISD::FSUB;
5518 unsigned NextExpectedOpcode = ISD::FADD;
5519 bool AddFound = false;
5520 bool SubFound = false;
5522 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5523 SDValue Op = BV->getOperand(i);
5525 // Skip 'undef' values.
5526 unsigned Opcode = Op.getOpcode();
5527 if (Opcode == ISD::UNDEF) {
5528 std::swap(ExpectedOpcode, NextExpectedOpcode);
5532 // Early exit if we found an unexpected opcode.
5533 if (Opcode != ExpectedOpcode)
5536 SDValue Op0 = Op.getOperand(0);
5537 SDValue Op1 = Op.getOperand(1);
5539 // Try to match the following pattern:
5540 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5541 // Early exit if we cannot match that sequence.
5542 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5543 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5544 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5545 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5546 Op0.getOperand(1) != Op1.getOperand(1))
5549 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5553 // We found a valid add/sub node. Update the information accordingly.
5559 // Update InVec0 and InVec1.
5560 if (InVec0.getOpcode() == ISD::UNDEF) {
5561 InVec0 = Op0.getOperand(0);
5562 if (InVec0.getValueType() != VT)
5565 if (InVec1.getOpcode() == ISD::UNDEF) {
5566 InVec1 = Op1.getOperand(0);
5567 if (InVec1.getValueType() != VT)
5571 // Make sure that operands in input to each add/sub node always
5572 // come from a same pair of vectors.
5573 if (InVec0 != Op0.getOperand(0)) {
5574 if (ExpectedOpcode == ISD::FSUB)
5577 // FADD is commutable. Try to commute the operands
5578 // and then test again.
5579 std::swap(Op0, Op1);
5580 if (InVec0 != Op0.getOperand(0))
5584 if (InVec1 != Op1.getOperand(0))
5587 // Update the pair of expected opcodes.
5588 std::swap(ExpectedOpcode, NextExpectedOpcode);
5591 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5592 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5593 InVec1.getOpcode() != ISD::UNDEF)
5594 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5599 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5600 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5601 const X86Subtarget *Subtarget,
5602 SelectionDAG &DAG) {
5603 EVT VT = BV->getValueType(0);
5604 unsigned NumElts = VT.getVectorNumElements();
5605 unsigned NumUndefsLO = 0;
5606 unsigned NumUndefsHI = 0;
5607 unsigned Half = NumElts/2;
5609 // Count the number of UNDEF operands in the build_vector in input.
5610 for (unsigned i = 0, e = Half; i != e; ++i)
5611 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5614 for (unsigned i = Half, e = NumElts; i != e; ++i)
5615 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5618 // Early exit if this is either a build_vector of all UNDEFs or all the
5619 // operands but one are UNDEF.
5620 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5624 SDValue InVec0, InVec1;
5625 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5626 // Try to match an SSE3 float HADD/HSUB.
5627 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5628 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5630 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5631 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5632 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5633 // Try to match an SSSE3 integer HADD/HSUB.
5634 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5635 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5637 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5638 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5641 if (!Subtarget->hasAVX())
5644 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5645 // Try to match an AVX horizontal add/sub of packed single/double
5646 // precision floating point values from 256-bit vectors.
5647 SDValue InVec2, InVec3;
5648 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5649 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5650 ((InVec0.getOpcode() == ISD::UNDEF ||
5651 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5652 ((InVec1.getOpcode() == ISD::UNDEF ||
5653 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5654 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5656 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5657 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5658 ((InVec0.getOpcode() == ISD::UNDEF ||
5659 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5660 ((InVec1.getOpcode() == ISD::UNDEF ||
5661 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5662 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5663 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5664 // Try to match an AVX2 horizontal add/sub of signed integers.
5665 SDValue InVec2, InVec3;
5667 bool CanFold = true;
5669 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5670 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5671 ((InVec0.getOpcode() == ISD::UNDEF ||
5672 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5673 ((InVec1.getOpcode() == ISD::UNDEF ||
5674 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5675 X86Opcode = X86ISD::HADD;
5676 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5677 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5678 ((InVec0.getOpcode() == ISD::UNDEF ||
5679 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5680 ((InVec1.getOpcode() == ISD::UNDEF ||
5681 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5682 X86Opcode = X86ISD::HSUB;
5687 // Fold this build_vector into a single horizontal add/sub.
5688 // Do this only if the target has AVX2.
5689 if (Subtarget->hasAVX2())
5690 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5692 // Do not try to expand this build_vector into a pair of horizontal
5693 // add/sub if we can emit a pair of scalar add/sub.
5694 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5697 // Convert this build_vector into a pair of horizontal binop followed by
5699 bool isUndefLO = NumUndefsLO == Half;
5700 bool isUndefHI = NumUndefsHI == Half;
5701 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5702 isUndefLO, isUndefHI);
5706 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5707 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5709 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5710 X86Opcode = X86ISD::HADD;
5711 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5712 X86Opcode = X86ISD::HSUB;
5713 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5714 X86Opcode = X86ISD::FHADD;
5715 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5716 X86Opcode = X86ISD::FHSUB;
5720 // Don't try to expand this build_vector into a pair of horizontal add/sub
5721 // if we can simply emit a pair of scalar add/sub.
5722 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5725 // Convert this build_vector into two horizontal add/sub followed by
5727 bool isUndefLO = NumUndefsLO == Half;
5728 bool isUndefHI = NumUndefsHI == Half;
5729 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5730 isUndefLO, isUndefHI);
5737 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5740 MVT VT = Op.getSimpleValueType();
5741 MVT ExtVT = VT.getVectorElementType();
5742 unsigned NumElems = Op.getNumOperands();
5744 // Generate vectors for predicate vectors.
5745 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5746 return LowerBUILD_VECTORvXi1(Op, DAG);
5748 // Vectors containing all zeros can be matched by pxor and xorps later
5749 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5750 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5751 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5752 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5755 return getZeroVector(VT, Subtarget, DAG, dl);
5758 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5759 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5760 // vpcmpeqd on 256-bit vectors.
5761 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5762 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5765 if (!VT.is512BitVector())
5766 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5769 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5770 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5772 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5773 return HorizontalOp;
5774 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5777 unsigned EVTBits = ExtVT.getSizeInBits();
5779 unsigned NumZero = 0;
5780 unsigned NumNonZero = 0;
5781 unsigned NonZeros = 0;
5782 bool IsAllConstants = true;
5783 SmallSet<SDValue, 8> Values;
5784 for (unsigned i = 0; i < NumElems; ++i) {
5785 SDValue Elt = Op.getOperand(i);
5786 if (Elt.getOpcode() == ISD::UNDEF)
5789 if (Elt.getOpcode() != ISD::Constant &&
5790 Elt.getOpcode() != ISD::ConstantFP)
5791 IsAllConstants = false;
5792 if (X86::isZeroNode(Elt))
5795 NonZeros |= (1 << i);
5800 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5801 if (NumNonZero == 0)
5802 return DAG.getUNDEF(VT);
5804 // Special case for single non-zero, non-undef, element.
5805 if (NumNonZero == 1) {
5806 unsigned Idx = countTrailingZeros(NonZeros);
5807 SDValue Item = Op.getOperand(Idx);
5809 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5810 // the value are obviously zero, truncate the value to i32 and do the
5811 // insertion that way. Only do this if the value is non-constant or if the
5812 // value is a constant being inserted into element 0. It is cheaper to do
5813 // a constant pool load than it is to do a movd + shuffle.
5814 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5815 (!IsAllConstants || Idx == 0)) {
5816 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5818 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5819 EVT VecVT = MVT::v4i32;
5821 // Truncate the value (which may itself be a constant) to i32, and
5822 // convert it to a vector with movd (S2V+shuffle to zero extend).
5823 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5824 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5825 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
5826 Item, Idx * 2, true, Subtarget, DAG));
5830 // If we have a constant or non-constant insertion into the low element of
5831 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5832 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5833 // depending on what the source datatype is.
5836 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5838 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5839 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5840 if (VT.is512BitVector()) {
5841 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5842 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5843 Item, DAG.getIntPtrConstant(0, dl));
5845 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5846 "Expected an SSE value type!");
5847 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5848 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5849 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5852 // We can't directly insert an i8 or i16 into a vector, so zero extend
5854 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5855 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5856 if (VT.is256BitVector()) {
5857 if (Subtarget->hasAVX()) {
5858 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5859 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5861 // Without AVX, we need to extend to a 128-bit vector and then
5862 // insert into the 256-bit vector.
5863 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5864 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5865 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5868 assert(VT.is128BitVector() && "Expected an SSE value type!");
5869 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5870 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5872 return DAG.getBitcast(VT, Item);
5876 // Is it a vector logical left shift?
5877 if (NumElems == 2 && Idx == 1 &&
5878 X86::isZeroNode(Op.getOperand(0)) &&
5879 !X86::isZeroNode(Op.getOperand(1))) {
5880 unsigned NumBits = VT.getSizeInBits();
5881 return getVShift(true, VT,
5882 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5883 VT, Op.getOperand(1)),
5884 NumBits/2, DAG, *this, dl);
5887 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5890 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5891 // is a non-constant being inserted into an element other than the low one,
5892 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5893 // movd/movss) to move this into the low element, then shuffle it into
5895 if (EVTBits == 32) {
5896 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5897 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5901 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5902 if (Values.size() == 1) {
5903 if (EVTBits == 32) {
5904 // Instead of a shuffle like this:
5905 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5906 // Check if it's possible to issue this instead.
5907 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5908 unsigned Idx = countTrailingZeros(NonZeros);
5909 SDValue Item = Op.getOperand(Idx);
5910 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5911 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5916 // A vector full of immediates; various special cases are already
5917 // handled, so this is best done with a single constant-pool load.
5921 // For AVX-length vectors, see if we can use a vector load to get all of the
5922 // elements, otherwise build the individual 128-bit pieces and use
5923 // shuffles to put them in place.
5924 if (VT.is256BitVector() || VT.is512BitVector()) {
5925 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5927 // Check for a build vector of consecutive loads.
5928 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5931 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5933 // Build both the lower and upper subvector.
5934 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5935 makeArrayRef(&V[0], NumElems/2));
5936 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5937 makeArrayRef(&V[NumElems / 2], NumElems/2));
5939 // Recreate the wider vector with the lower and upper part.
5940 if (VT.is256BitVector())
5941 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5942 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5945 // Let legalizer expand 2-wide build_vectors.
5946 if (EVTBits == 64) {
5947 if (NumNonZero == 1) {
5948 // One half is zero or undef.
5949 unsigned Idx = countTrailingZeros(NonZeros);
5950 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5951 Op.getOperand(Idx));
5952 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5957 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5958 if (EVTBits == 8 && NumElems == 16)
5959 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5963 if (EVTBits == 16 && NumElems == 8)
5964 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5968 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5969 if (EVTBits == 32 && NumElems == 4)
5970 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5973 // If element VT is == 32 bits, turn it into a number of shuffles.
5974 SmallVector<SDValue, 8> V(NumElems);
5975 if (NumElems == 4 && NumZero > 0) {
5976 for (unsigned i = 0; i < 4; ++i) {
5977 bool isZero = !(NonZeros & (1 << i));
5979 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5981 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5984 for (unsigned i = 0; i < 2; ++i) {
5985 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5988 V[i] = V[i*2]; // Must be a zero vector.
5991 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5994 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5997 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6002 bool Reverse1 = (NonZeros & 0x3) == 2;
6003 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6007 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6008 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6010 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6013 if (Values.size() > 1 && VT.is128BitVector()) {
6014 // Check for a build vector of consecutive loads.
6015 for (unsigned i = 0; i < NumElems; ++i)
6016 V[i] = Op.getOperand(i);
6018 // Check for elements which are consecutive loads.
6019 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6022 // Check for a build vector from mostly shuffle plus few inserting.
6023 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6026 // For SSE 4.1, use insertps to put the high elements into the low element.
6027 if (Subtarget->hasSSE41()) {
6029 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6030 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6032 Result = DAG.getUNDEF(VT);
6034 for (unsigned i = 1; i < NumElems; ++i) {
6035 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6036 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6037 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6042 // Otherwise, expand into a number of unpckl*, start by extending each of
6043 // our (non-undef) elements to the full vector width with the element in the
6044 // bottom slot of the vector (which generates no code for SSE).
6045 for (unsigned i = 0; i < NumElems; ++i) {
6046 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6047 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6049 V[i] = DAG.getUNDEF(VT);
6052 // Next, we iteratively mix elements, e.g. for v4f32:
6053 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6054 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6055 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6056 unsigned EltStride = NumElems >> 1;
6057 while (EltStride != 0) {
6058 for (unsigned i = 0; i < EltStride; ++i) {
6059 // If V[i+EltStride] is undef and this is the first round of mixing,
6060 // then it is safe to just drop this shuffle: V[i] is already in the
6061 // right place, the one element (since it's the first round) being
6062 // inserted as undef can be dropped. This isn't safe for successive
6063 // rounds because they will permute elements within both vectors.
6064 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6065 EltStride == NumElems/2)
6068 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6077 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6078 // to create 256-bit vectors from two other 128-bit ones.
6079 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6081 MVT ResVT = Op.getSimpleValueType();
6083 assert((ResVT.is256BitVector() ||
6084 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6086 SDValue V1 = Op.getOperand(0);
6087 SDValue V2 = Op.getOperand(1);
6088 unsigned NumElems = ResVT.getVectorNumElements();
6089 if (ResVT.is256BitVector())
6090 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6092 if (Op.getNumOperands() == 4) {
6093 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6094 ResVT.getVectorNumElements()/2);
6095 SDValue V3 = Op.getOperand(2);
6096 SDValue V4 = Op.getOperand(3);
6097 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6098 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6100 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6103 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6104 const X86Subtarget *Subtarget,
6105 SelectionDAG & DAG) {
6107 MVT ResVT = Op.getSimpleValueType();
6108 unsigned NumOfOperands = Op.getNumOperands();
6110 assert(isPowerOf2_32(NumOfOperands) &&
6111 "Unexpected number of operands in CONCAT_VECTORS");
6113 if (NumOfOperands > 2) {
6114 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6115 ResVT.getVectorNumElements()/2);
6116 SmallVector<SDValue, 2> Ops;
6117 for (unsigned i = 0; i < NumOfOperands/2; i++)
6118 Ops.push_back(Op.getOperand(i));
6119 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6121 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6122 Ops.push_back(Op.getOperand(i));
6123 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6124 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6127 SDValue V1 = Op.getOperand(0);
6128 SDValue V2 = Op.getOperand(1);
6129 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6130 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6132 if (IsZeroV1 && IsZeroV2)
6133 return getZeroVector(ResVT, Subtarget, DAG, dl);
6135 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6136 SDValue Undef = DAG.getUNDEF(ResVT);
6137 unsigned NumElems = ResVT.getVectorNumElements();
6138 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6140 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6141 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6145 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6146 // Zero the upper bits of V1
6147 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6148 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6151 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6154 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6155 const X86Subtarget *Subtarget,
6156 SelectionDAG &DAG) {
6157 MVT VT = Op.getSimpleValueType();
6158 if (VT.getVectorElementType() == MVT::i1)
6159 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6161 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6162 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6163 Op.getNumOperands() == 4)));
6165 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6166 // from two other 128-bit ones.
6168 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6169 return LowerAVXCONCAT_VECTORS(Op, DAG);
6173 //===----------------------------------------------------------------------===//
6174 // Vector shuffle lowering
6176 // This is an experimental code path for lowering vector shuffles on x86. It is
6177 // designed to handle arbitrary vector shuffles and blends, gracefully
6178 // degrading performance as necessary. It works hard to recognize idiomatic
6179 // shuffles and lower them to optimal instruction patterns without leaving
6180 // a framework that allows reasonably efficient handling of all vector shuffle
6182 //===----------------------------------------------------------------------===//
6184 /// \brief Tiny helper function to identify a no-op mask.
6186 /// This is a somewhat boring predicate function. It checks whether the mask
6187 /// array input, which is assumed to be a single-input shuffle mask of the kind
6188 /// used by the X86 shuffle instructions (not a fully general
6189 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6190 /// in-place shuffle are 'no-op's.
6191 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6192 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6193 if (Mask[i] != -1 && Mask[i] != i)
6198 /// \brief Helper function to classify a mask as a single-input mask.
6200 /// This isn't a generic single-input test because in the vector shuffle
6201 /// lowering we canonicalize single inputs to be the first input operand. This
6202 /// means we can more quickly test for a single input by only checking whether
6203 /// an input from the second operand exists. We also assume that the size of
6204 /// mask corresponds to the size of the input vectors which isn't true in the
6205 /// fully general case.
6206 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6208 if (M >= (int)Mask.size())
6213 /// \brief Test whether there are elements crossing 128-bit lanes in this
6216 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6217 /// and we routinely test for these.
6218 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6219 int LaneSize = 128 / VT.getScalarSizeInBits();
6220 int Size = Mask.size();
6221 for (int i = 0; i < Size; ++i)
6222 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6227 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6229 /// This checks a shuffle mask to see if it is performing the same
6230 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6231 /// that it is also not lane-crossing. It may however involve a blend from the
6232 /// same lane of a second vector.
6234 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6235 /// non-trivial to compute in the face of undef lanes. The representation is
6236 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6237 /// entries from both V1 and V2 inputs to the wider mask.
6239 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6240 SmallVectorImpl<int> &RepeatedMask) {
6241 int LaneSize = 128 / VT.getScalarSizeInBits();
6242 RepeatedMask.resize(LaneSize, -1);
6243 int Size = Mask.size();
6244 for (int i = 0; i < Size; ++i) {
6247 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6248 // This entry crosses lanes, so there is no way to model this shuffle.
6251 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6252 if (RepeatedMask[i % LaneSize] == -1)
6253 // This is the first non-undef entry in this slot of a 128-bit lane.
6254 RepeatedMask[i % LaneSize] =
6255 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6256 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6257 // Found a mismatch with the repeated mask.
6263 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6266 /// This is a fast way to test a shuffle mask against a fixed pattern:
6268 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6270 /// It returns true if the mask is exactly as wide as the argument list, and
6271 /// each element of the mask is either -1 (signifying undef) or the value given
6272 /// in the argument.
6273 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6274 ArrayRef<int> ExpectedMask) {
6275 if (Mask.size() != ExpectedMask.size())
6278 int Size = Mask.size();
6280 // If the values are build vectors, we can look through them to find
6281 // equivalent inputs that make the shuffles equivalent.
6282 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6283 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6285 for (int i = 0; i < Size; ++i)
6286 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6287 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6288 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6289 if (!MaskBV || !ExpectedBV ||
6290 MaskBV->getOperand(Mask[i] % Size) !=
6291 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6298 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6300 /// This helper function produces an 8-bit shuffle immediate corresponding to
6301 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6302 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6305 /// NB: We rely heavily on "undef" masks preserving the input lane.
6306 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6307 SelectionDAG &DAG) {
6308 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6309 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6310 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6311 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6312 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6315 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6316 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6317 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6318 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6319 return DAG.getConstant(Imm, DL, MVT::i8);
6322 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6324 /// This is used as a fallback approach when first class blend instructions are
6325 /// unavailable. Currently it is only suitable for integer vectors, but could
6326 /// be generalized for floating point vectors if desirable.
6327 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6328 SDValue V2, ArrayRef<int> Mask,
6329 SelectionDAG &DAG) {
6330 assert(VT.isInteger() && "Only supports integer vector types!");
6331 MVT EltVT = VT.getScalarType();
6332 int NumEltBits = EltVT.getSizeInBits();
6333 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6334 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6336 SmallVector<SDValue, 16> MaskOps;
6337 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6338 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6339 return SDValue(); // Shuffled input!
6340 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6343 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6344 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6345 // We have to cast V2 around.
6346 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6347 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6348 DAG.getBitcast(MaskVT, V1Mask),
6349 DAG.getBitcast(MaskVT, V2)));
6350 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6353 /// \brief Try to emit a blend instruction for a shuffle.
6355 /// This doesn't do any checks for the availability of instructions for blending
6356 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6357 /// be matched in the backend with the type given. What it does check for is
6358 /// that the shuffle mask is in fact a blend.
6359 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6360 SDValue V2, ArrayRef<int> Mask,
6361 const X86Subtarget *Subtarget,
6362 SelectionDAG &DAG) {
6363 unsigned BlendMask = 0;
6364 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6365 if (Mask[i] >= Size) {
6366 if (Mask[i] != i + Size)
6367 return SDValue(); // Shuffled V2 input!
6368 BlendMask |= 1u << i;
6371 if (Mask[i] >= 0 && Mask[i] != i)
6372 return SDValue(); // Shuffled V1 input!
6374 switch (VT.SimpleTy) {
6379 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6380 DAG.getConstant(BlendMask, DL, MVT::i8));
6384 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6388 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6389 // that instruction.
6390 if (Subtarget->hasAVX2()) {
6391 // Scale the blend by the number of 32-bit dwords per element.
6392 int Scale = VT.getScalarSizeInBits() / 32;
6394 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6395 if (Mask[i] >= Size)
6396 for (int j = 0; j < Scale; ++j)
6397 BlendMask |= 1u << (i * Scale + j);
6399 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6400 V1 = DAG.getBitcast(BlendVT, V1);
6401 V2 = DAG.getBitcast(BlendVT, V2);
6402 return DAG.getBitcast(
6403 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6404 DAG.getConstant(BlendMask, DL, MVT::i8)));
6408 // For integer shuffles we need to expand the mask and cast the inputs to
6409 // v8i16s prior to blending.
6410 int Scale = 8 / VT.getVectorNumElements();
6412 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6413 if (Mask[i] >= Size)
6414 for (int j = 0; j < Scale; ++j)
6415 BlendMask |= 1u << (i * Scale + j);
6417 V1 = DAG.getBitcast(MVT::v8i16, V1);
6418 V2 = DAG.getBitcast(MVT::v8i16, V2);
6419 return DAG.getBitcast(VT,
6420 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6421 DAG.getConstant(BlendMask, DL, MVT::i8)));
6425 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6426 SmallVector<int, 8> RepeatedMask;
6427 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6428 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6429 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6431 for (int i = 0; i < 8; ++i)
6432 if (RepeatedMask[i] >= 16)
6433 BlendMask |= 1u << i;
6434 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6435 DAG.getConstant(BlendMask, DL, MVT::i8));
6441 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6442 "256-bit byte-blends require AVX2 support!");
6444 // Scale the blend by the number of bytes per element.
6445 int Scale = VT.getScalarSizeInBits() / 8;
6447 // This form of blend is always done on bytes. Compute the byte vector
6449 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6451 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6452 // mix of LLVM's code generator and the x86 backend. We tell the code
6453 // generator that boolean values in the elements of an x86 vector register
6454 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6455 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6456 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6457 // of the element (the remaining are ignored) and 0 in that high bit would
6458 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6459 // the LLVM model for boolean values in vector elements gets the relevant
6460 // bit set, it is set backwards and over constrained relative to x86's
6462 SmallVector<SDValue, 32> VSELECTMask;
6463 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6464 for (int j = 0; j < Scale; ++j)
6465 VSELECTMask.push_back(
6466 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6467 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6470 V1 = DAG.getBitcast(BlendVT, V1);
6471 V2 = DAG.getBitcast(BlendVT, V2);
6472 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6473 DAG.getNode(ISD::BUILD_VECTOR, DL,
6474 BlendVT, VSELECTMask),
6479 llvm_unreachable("Not a supported integer vector type!");
6483 /// \brief Try to lower as a blend of elements from two inputs followed by
6484 /// a single-input permutation.
6486 /// This matches the pattern where we can blend elements from two inputs and
6487 /// then reduce the shuffle to a single-input permutation.
6488 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6491 SelectionDAG &DAG) {
6492 // We build up the blend mask while checking whether a blend is a viable way
6493 // to reduce the shuffle.
6494 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6495 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6497 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6501 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6503 if (BlendMask[Mask[i] % Size] == -1)
6504 BlendMask[Mask[i] % Size] = Mask[i];
6505 else if (BlendMask[Mask[i] % Size] != Mask[i])
6506 return SDValue(); // Can't blend in the needed input!
6508 PermuteMask[i] = Mask[i] % Size;
6511 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6512 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6515 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6516 /// blends and permutes.
6518 /// This matches the extremely common pattern for handling combined
6519 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6520 /// operations. It will try to pick the best arrangement of shuffles and
6522 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6526 SelectionDAG &DAG) {
6527 // Shuffle the input elements into the desired positions in V1 and V2 and
6528 // blend them together.
6529 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6530 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6531 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6532 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6533 if (Mask[i] >= 0 && Mask[i] < Size) {
6534 V1Mask[i] = Mask[i];
6536 } else if (Mask[i] >= Size) {
6537 V2Mask[i] = Mask[i] - Size;
6538 BlendMask[i] = i + Size;
6541 // Try to lower with the simpler initial blend strategy unless one of the
6542 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6543 // shuffle may be able to fold with a load or other benefit. However, when
6544 // we'll have to do 2x as many shuffles in order to achieve this, blending
6545 // first is a better strategy.
6546 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6547 if (SDValue BlendPerm =
6548 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6551 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6552 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6553 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6556 /// \brief Try to lower a vector shuffle as a byte rotation.
6558 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6559 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6560 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6561 /// try to generically lower a vector shuffle through such an pattern. It
6562 /// does not check for the profitability of lowering either as PALIGNR or
6563 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6564 /// This matches shuffle vectors that look like:
6566 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6568 /// Essentially it concatenates V1 and V2, shifts right by some number of
6569 /// elements, and takes the low elements as the result. Note that while this is
6570 /// specified as a *right shift* because x86 is little-endian, it is a *left
6571 /// rotate* of the vector lanes.
6572 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6575 const X86Subtarget *Subtarget,
6576 SelectionDAG &DAG) {
6577 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6579 int NumElts = Mask.size();
6580 int NumLanes = VT.getSizeInBits() / 128;
6581 int NumLaneElts = NumElts / NumLanes;
6583 // We need to detect various ways of spelling a rotation:
6584 // [11, 12, 13, 14, 15, 0, 1, 2]
6585 // [-1, 12, 13, 14, -1, -1, 1, -1]
6586 // [-1, -1, -1, -1, -1, -1, 1, 2]
6587 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6588 // [-1, 4, 5, 6, -1, -1, 9, -1]
6589 // [-1, 4, 5, 6, -1, -1, -1, -1]
6592 for (int l = 0; l < NumElts; l += NumLaneElts) {
6593 for (int i = 0; i < NumLaneElts; ++i) {
6594 if (Mask[l + i] == -1)
6596 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6598 // Get the mod-Size index and lane correct it.
6599 int LaneIdx = (Mask[l + i] % NumElts) - l;
6600 // Make sure it was in this lane.
6601 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6604 // Determine where a rotated vector would have started.
6605 int StartIdx = i - LaneIdx;
6607 // The identity rotation isn't interesting, stop.
6610 // If we found the tail of a vector the rotation must be the missing
6611 // front. If we found the head of a vector, it must be how much of the
6613 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6616 Rotation = CandidateRotation;
6617 else if (Rotation != CandidateRotation)
6618 // The rotations don't match, so we can't match this mask.
6621 // Compute which value this mask is pointing at.
6622 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6624 // Compute which of the two target values this index should be assigned
6625 // to. This reflects whether the high elements are remaining or the low
6626 // elements are remaining.
6627 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6629 // Either set up this value if we've not encountered it before, or check
6630 // that it remains consistent.
6633 else if (TargetV != MaskV)
6634 // This may be a rotation, but it pulls from the inputs in some
6635 // unsupported interleaving.
6640 // Check that we successfully analyzed the mask, and normalize the results.
6641 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6642 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6648 // The actual rotate instruction rotates bytes, so we need to scale the
6649 // rotation based on how many bytes are in the vector lane.
6650 int Scale = 16 / NumLaneElts;
6652 // SSSE3 targets can use the palignr instruction.
6653 if (Subtarget->hasSSSE3()) {
6654 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6655 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6656 Lo = DAG.getBitcast(AlignVT, Lo);
6657 Hi = DAG.getBitcast(AlignVT, Hi);
6659 return DAG.getBitcast(
6660 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6661 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
6664 assert(VT.getSizeInBits() == 128 &&
6665 "Rotate-based lowering only supports 128-bit lowering!");
6666 assert(Mask.size() <= 16 &&
6667 "Can shuffle at most 16 bytes in a 128-bit vector!");
6669 // Default SSE2 implementation
6670 int LoByteShift = 16 - Rotation * Scale;
6671 int HiByteShift = Rotation * Scale;
6673 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6674 Lo = DAG.getBitcast(MVT::v2i64, Lo);
6675 Hi = DAG.getBitcast(MVT::v2i64, Hi);
6677 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6678 DAG.getConstant(LoByteShift, DL, MVT::i8));
6679 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6680 DAG.getConstant(HiByteShift, DL, MVT::i8));
6681 return DAG.getBitcast(VT,
6682 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6685 /// \brief Compute whether each element of a shuffle is zeroable.
6687 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6688 /// Either it is an undef element in the shuffle mask, the element of the input
6689 /// referenced is undef, or the element of the input referenced is known to be
6690 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6691 /// as many lanes with this technique as possible to simplify the remaining
6693 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6694 SDValue V1, SDValue V2) {
6695 SmallBitVector Zeroable(Mask.size(), false);
6697 while (V1.getOpcode() == ISD::BITCAST)
6698 V1 = V1->getOperand(0);
6699 while (V2.getOpcode() == ISD::BITCAST)
6700 V2 = V2->getOperand(0);
6702 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6703 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6705 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6707 // Handle the easy cases.
6708 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6713 // If this is an index into a build_vector node (which has the same number
6714 // of elements), dig out the input value and use it.
6715 SDValue V = M < Size ? V1 : V2;
6716 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6719 SDValue Input = V.getOperand(M % Size);
6720 // The UNDEF opcode check really should be dead code here, but not quite
6721 // worth asserting on (it isn't invalid, just unexpected).
6722 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6729 /// \brief Try to emit a bitmask instruction for a shuffle.
6731 /// This handles cases where we can model a blend exactly as a bitmask due to
6732 /// one of the inputs being zeroable.
6733 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6734 SDValue V2, ArrayRef<int> Mask,
6735 SelectionDAG &DAG) {
6736 MVT EltVT = VT.getScalarType();
6737 int NumEltBits = EltVT.getSizeInBits();
6738 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6739 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6740 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6742 if (EltVT.isFloatingPoint()) {
6743 Zero = DAG.getBitcast(EltVT, Zero);
6744 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6746 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6747 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6749 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6752 if (Mask[i] % Size != i)
6753 return SDValue(); // Not a blend.
6755 V = Mask[i] < Size ? V1 : V2;
6756 else if (V != (Mask[i] < Size ? V1 : V2))
6757 return SDValue(); // Can only let one input through the mask.
6759 VMaskOps[i] = AllOnes;
6762 return SDValue(); // No non-zeroable elements!
6764 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6765 V = DAG.getNode(VT.isFloatingPoint()
6766 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6771 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6773 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6774 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6775 /// matches elements from one of the input vectors shuffled to the left or
6776 /// right with zeroable elements 'shifted in'. It handles both the strictly
6777 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6780 /// PSHL : (little-endian) left bit shift.
6781 /// [ zz, 0, zz, 2 ]
6782 /// [ -1, 4, zz, -1 ]
6783 /// PSRL : (little-endian) right bit shift.
6785 /// [ -1, -1, 7, zz]
6786 /// PSLLDQ : (little-endian) left byte shift
6787 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6788 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6789 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6790 /// PSRLDQ : (little-endian) right byte shift
6791 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6792 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6793 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6794 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6795 SDValue V2, ArrayRef<int> Mask,
6796 SelectionDAG &DAG) {
6797 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6799 int Size = Mask.size();
6800 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6802 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6803 for (int i = 0; i < Size; i += Scale)
6804 for (int j = 0; j < Shift; ++j)
6805 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6811 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6812 for (int i = 0; i != Size; i += Scale) {
6813 unsigned Pos = Left ? i + Shift : i;
6814 unsigned Low = Left ? i : i + Shift;
6815 unsigned Len = Scale - Shift;
6816 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6817 Low + (V == V1 ? 0 : Size)))
6821 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6822 bool ByteShift = ShiftEltBits > 64;
6823 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6824 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6825 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6827 // Normalize the scale for byte shifts to still produce an i64 element
6829 Scale = ByteShift ? Scale / 2 : Scale;
6831 // We need to round trip through the appropriate type for the shift.
6832 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6833 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6834 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6835 "Illegal integer vector type");
6836 V = DAG.getBitcast(ShiftVT, V);
6838 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6839 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6840 return DAG.getBitcast(VT, V);
6843 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6844 // keep doubling the size of the integer elements up to that. We can
6845 // then shift the elements of the integer vector by whole multiples of
6846 // their width within the elements of the larger integer vector. Test each
6847 // multiple to see if we can find a match with the moved element indices
6848 // and that the shifted in elements are all zeroable.
6849 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6850 for (int Shift = 1; Shift != Scale; ++Shift)
6851 for (bool Left : {true, false})
6852 if (CheckZeros(Shift, Scale, Left))
6853 for (SDValue V : {V1, V2})
6854 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6861 /// \brief Lower a vector shuffle as a zero or any extension.
6863 /// Given a specific number of elements, element bit width, and extension
6864 /// stride, produce either a zero or any extension based on the available
6865 /// features of the subtarget.
6866 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6867 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6868 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6869 assert(Scale > 1 && "Need a scale to extend.");
6870 int NumElements = VT.getVectorNumElements();
6871 int EltBits = VT.getScalarSizeInBits();
6872 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6873 "Only 8, 16, and 32 bit elements can be extended.");
6874 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6876 // Found a valid zext mask! Try various lowering strategies based on the
6877 // input type and available ISA extensions.
6878 if (Subtarget->hasSSE41()) {
6879 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6880 NumElements / Scale);
6881 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6884 // For any extends we can cheat for larger element sizes and use shuffle
6885 // instructions that can fold with a load and/or copy.
6886 if (AnyExt && EltBits == 32) {
6887 int PSHUFDMask[4] = {0, -1, 1, -1};
6888 return DAG.getBitcast(
6889 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6890 DAG.getBitcast(MVT::v4i32, InputV),
6891 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
6893 if (AnyExt && EltBits == 16 && Scale > 2) {
6894 int PSHUFDMask[4] = {0, -1, 0, -1};
6895 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6896 DAG.getBitcast(MVT::v4i32, InputV),
6897 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
6898 int PSHUFHWMask[4] = {1, -1, -1, -1};
6899 return DAG.getBitcast(
6900 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6901 DAG.getBitcast(MVT::v8i16, InputV),
6902 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
6905 // If this would require more than 2 unpack instructions to expand, use
6906 // pshufb when available. We can only use more than 2 unpack instructions
6907 // when zero extending i8 elements which also makes it easier to use pshufb.
6908 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6909 assert(NumElements == 16 && "Unexpected byte vector width!");
6910 SDValue PSHUFBMask[16];
6911 for (int i = 0; i < 16; ++i)
6913 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
6914 InputV = DAG.getBitcast(MVT::v16i8, InputV);
6915 return DAG.getBitcast(VT,
6916 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6917 DAG.getNode(ISD::BUILD_VECTOR, DL,
6918 MVT::v16i8, PSHUFBMask)));
6921 // Otherwise emit a sequence of unpacks.
6923 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6924 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6925 : getZeroVector(InputVT, Subtarget, DAG, DL);
6926 InputV = DAG.getBitcast(InputVT, InputV);
6927 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6931 } while (Scale > 1);
6932 return DAG.getBitcast(VT, InputV);
6935 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6937 /// This routine will try to do everything in its power to cleverly lower
6938 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6939 /// check for the profitability of this lowering, it tries to aggressively
6940 /// match this pattern. It will use all of the micro-architectural details it
6941 /// can to emit an efficient lowering. It handles both blends with all-zero
6942 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6943 /// masking out later).
6945 /// The reason we have dedicated lowering for zext-style shuffles is that they
6946 /// are both incredibly common and often quite performance sensitive.
6947 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6948 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6949 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6950 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6952 int Bits = VT.getSizeInBits();
6953 int NumElements = VT.getVectorNumElements();
6954 assert(VT.getScalarSizeInBits() <= 32 &&
6955 "Exceeds 32-bit integer zero extension limit");
6956 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6958 // Define a helper function to check a particular ext-scale and lower to it if
6960 auto Lower = [&](int Scale) -> SDValue {
6963 for (int i = 0; i < NumElements; ++i) {
6965 continue; // Valid anywhere but doesn't tell us anything.
6966 if (i % Scale != 0) {
6967 // Each of the extended elements need to be zeroable.
6971 // We no longer are in the anyext case.
6976 // Each of the base elements needs to be consecutive indices into the
6977 // same input vector.
6978 SDValue V = Mask[i] < NumElements ? V1 : V2;
6981 else if (InputV != V)
6982 return SDValue(); // Flip-flopping inputs.
6984 if (Mask[i] % NumElements != i / Scale)
6985 return SDValue(); // Non-consecutive strided elements.
6988 // If we fail to find an input, we have a zero-shuffle which should always
6989 // have already been handled.
6990 // FIXME: Maybe handle this here in case during blending we end up with one?
6994 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6995 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
6998 // The widest scale possible for extending is to a 64-bit integer.
6999 assert(Bits % 64 == 0 &&
7000 "The number of bits in a vector must be divisible by 64 on x86!");
7001 int NumExtElements = Bits / 64;
7003 // Each iteration, try extending the elements half as much, but into twice as
7005 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7006 assert(NumElements % NumExtElements == 0 &&
7007 "The input vector size must be divisible by the extended size.");
7008 if (SDValue V = Lower(NumElements / NumExtElements))
7012 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7016 // Returns one of the source operands if the shuffle can be reduced to a
7017 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7018 auto CanZExtLowHalf = [&]() {
7019 for (int i = NumElements / 2; i != NumElements; ++i)
7022 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7024 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7029 if (SDValue V = CanZExtLowHalf()) {
7030 V = DAG.getBitcast(MVT::v2i64, V);
7031 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7032 return DAG.getBitcast(VT, V);
7035 // No viable ext lowering found.
7039 /// \brief Try to get a scalar value for a specific element of a vector.
7041 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7042 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7043 SelectionDAG &DAG) {
7044 MVT VT = V.getSimpleValueType();
7045 MVT EltVT = VT.getVectorElementType();
7046 while (V.getOpcode() == ISD::BITCAST)
7047 V = V.getOperand(0);
7048 // If the bitcasts shift the element size, we can't extract an equivalent
7050 MVT NewVT = V.getSimpleValueType();
7051 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7054 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7055 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7056 // Ensure the scalar operand is the same size as the destination.
7057 // FIXME: Add support for scalar truncation where possible.
7058 SDValue S = V.getOperand(Idx);
7059 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7060 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7066 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7068 /// This is particularly important because the set of instructions varies
7069 /// significantly based on whether the operand is a load or not.
7070 static bool isShuffleFoldableLoad(SDValue V) {
7071 while (V.getOpcode() == ISD::BITCAST)
7072 V = V.getOperand(0);
7074 return ISD::isNON_EXTLoad(V.getNode());
7077 /// \brief Try to lower insertion of a single element into a zero vector.
7079 /// This is a common pattern that we have especially efficient patterns to lower
7080 /// across all subtarget feature sets.
7081 static SDValue lowerVectorShuffleAsElementInsertion(
7082 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7083 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7084 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7086 MVT EltVT = VT.getVectorElementType();
7088 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7089 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7091 bool IsV1Zeroable = true;
7092 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7093 if (i != V2Index && !Zeroable[i]) {
7094 IsV1Zeroable = false;
7098 // Check for a single input from a SCALAR_TO_VECTOR node.
7099 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7100 // all the smarts here sunk into that routine. However, the current
7101 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7102 // vector shuffle lowering is dead.
7103 if (SDValue V2S = getScalarValueForVectorElement(
7104 V2, Mask[V2Index] - Mask.size(), DAG)) {
7105 // We need to zext the scalar if it is smaller than an i32.
7106 V2S = DAG.getBitcast(EltVT, V2S);
7107 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7108 // Using zext to expand a narrow element won't work for non-zero
7113 // Zero-extend directly to i32.
7115 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7117 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7118 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7119 EltVT == MVT::i16) {
7120 // Either not inserting from the low element of the input or the input
7121 // element size is too small to use VZEXT_MOVL to clear the high bits.
7125 if (!IsV1Zeroable) {
7126 // If V1 can't be treated as a zero vector we have fewer options to lower
7127 // this. We can't support integer vectors or non-zero targets cheaply, and
7128 // the V1 elements can't be permuted in any way.
7129 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7130 if (!VT.isFloatingPoint() || V2Index != 0)
7132 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7133 V1Mask[V2Index] = -1;
7134 if (!isNoopShuffleMask(V1Mask))
7136 // This is essentially a special case blend operation, but if we have
7137 // general purpose blend operations, they are always faster. Bail and let
7138 // the rest of the lowering handle these as blends.
7139 if (Subtarget->hasSSE41())
7142 // Otherwise, use MOVSD or MOVSS.
7143 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7144 "Only two types of floating point element types to handle!");
7145 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7149 // This lowering only works for the low element with floating point vectors.
7150 if (VT.isFloatingPoint() && V2Index != 0)
7153 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7155 V2 = DAG.getBitcast(VT, V2);
7158 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7159 // the desired position. Otherwise it is more efficient to do a vector
7160 // shift left. We know that we can do a vector shift left because all
7161 // the inputs are zero.
7162 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7163 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7164 V2Shuffle[V2Index] = 0;
7165 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7167 V2 = DAG.getBitcast(MVT::v2i64, V2);
7169 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7171 V2Index * EltVT.getSizeInBits()/8, DL,
7172 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7173 V2 = DAG.getBitcast(VT, V2);
7179 /// \brief Try to lower broadcast of a single element.
7181 /// For convenience, this code also bundles all of the subtarget feature set
7182 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7183 /// a convenient way to factor it out.
7184 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7186 const X86Subtarget *Subtarget,
7187 SelectionDAG &DAG) {
7188 if (!Subtarget->hasAVX())
7190 if (VT.isInteger() && !Subtarget->hasAVX2())
7193 // Check that the mask is a broadcast.
7194 int BroadcastIdx = -1;
7196 if (M >= 0 && BroadcastIdx == -1)
7198 else if (M >= 0 && M != BroadcastIdx)
7201 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7202 "a sorted mask where the broadcast "
7205 // Go up the chain of (vector) values to find a scalar load that we can
7206 // combine with the broadcast.
7208 switch (V.getOpcode()) {
7209 case ISD::CONCAT_VECTORS: {
7210 int OperandSize = Mask.size() / V.getNumOperands();
7211 V = V.getOperand(BroadcastIdx / OperandSize);
7212 BroadcastIdx %= OperandSize;
7216 case ISD::INSERT_SUBVECTOR: {
7217 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7218 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7222 int BeginIdx = (int)ConstantIdx->getZExtValue();
7224 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7225 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7226 BroadcastIdx -= BeginIdx;
7237 // Check if this is a broadcast of a scalar. We special case lowering
7238 // for scalars so that we can more effectively fold with loads.
7239 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7240 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7241 V = V.getOperand(BroadcastIdx);
7243 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7244 // Only AVX2 has register broadcasts.
7245 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7247 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7248 // We can't broadcast from a vector register without AVX2, and we can only
7249 // broadcast from the zero-element of a vector register.
7253 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7256 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7257 // INSERTPS when the V1 elements are already in the correct locations
7258 // because otherwise we can just always use two SHUFPS instructions which
7259 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7260 // perform INSERTPS if a single V1 element is out of place and all V2
7261 // elements are zeroable.
7262 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7264 SelectionDAG &DAG) {
7265 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7266 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7267 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7268 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7270 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7273 int V1DstIndex = -1;
7274 int V2DstIndex = -1;
7275 bool V1UsedInPlace = false;
7277 for (int i = 0; i < 4; ++i) {
7278 // Synthesize a zero mask from the zeroable elements (includes undefs).
7284 // Flag if we use any V1 inputs in place.
7286 V1UsedInPlace = true;
7290 // We can only insert a single non-zeroable element.
7291 if (V1DstIndex != -1 || V2DstIndex != -1)
7295 // V1 input out of place for insertion.
7298 // V2 input for insertion.
7303 // Don't bother if we have no (non-zeroable) element for insertion.
7304 if (V1DstIndex == -1 && V2DstIndex == -1)
7307 // Determine element insertion src/dst indices. The src index is from the
7308 // start of the inserted vector, not the start of the concatenated vector.
7309 unsigned V2SrcIndex = 0;
7310 if (V1DstIndex != -1) {
7311 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7312 // and don't use the original V2 at all.
7313 V2SrcIndex = Mask[V1DstIndex];
7314 V2DstIndex = V1DstIndex;
7317 V2SrcIndex = Mask[V2DstIndex] - 4;
7320 // If no V1 inputs are used in place, then the result is created only from
7321 // the zero mask and the V2 insertion - so remove V1 dependency.
7323 V1 = DAG.getUNDEF(MVT::v4f32);
7325 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7326 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7328 // Insert the V2 element into the desired position.
7330 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7331 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7334 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7335 /// UNPCK instruction.
7337 /// This specifically targets cases where we end up with alternating between
7338 /// the two inputs, and so can permute them into something that feeds a single
7339 /// UNPCK instruction. Note that this routine only targets integer vectors
7340 /// because for floating point vectors we have a generalized SHUFPS lowering
7341 /// strategy that handles everything that doesn't *exactly* match an unpack,
7342 /// making this clever lowering unnecessary.
7343 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7344 SDValue V2, ArrayRef<int> Mask,
7345 SelectionDAG &DAG) {
7346 assert(!VT.isFloatingPoint() &&
7347 "This routine only supports integer vectors.");
7348 assert(!isSingleInputShuffleMask(Mask) &&
7349 "This routine should only be used when blending two inputs.");
7350 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7352 int Size = Mask.size();
7354 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7355 return M >= 0 && M % Size < Size / 2;
7357 int NumHiInputs = std::count_if(
7358 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7360 bool UnpackLo = NumLoInputs >= NumHiInputs;
7362 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7363 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7364 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7366 for (int i = 0; i < Size; ++i) {
7370 // Each element of the unpack contains Scale elements from this mask.
7371 int UnpackIdx = i / Scale;
7373 // We only handle the case where V1 feeds the first slots of the unpack.
7374 // We rely on canonicalization to ensure this is the case.
7375 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7378 // Setup the mask for this input. The indexing is tricky as we have to
7379 // handle the unpack stride.
7380 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7381 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7385 // If we will have to shuffle both inputs to use the unpack, check whether
7386 // we can just unpack first and shuffle the result. If so, skip this unpack.
7387 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7388 !isNoopShuffleMask(V2Mask))
7391 // Shuffle the inputs into place.
7392 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7393 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7395 // Cast the inputs to the type we will use to unpack them.
7396 V1 = DAG.getBitcast(UnpackVT, V1);
7397 V2 = DAG.getBitcast(UnpackVT, V2);
7399 // Unpack the inputs and cast the result back to the desired type.
7400 return DAG.getBitcast(
7401 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7405 // We try each unpack from the largest to the smallest to try and find one
7406 // that fits this mask.
7407 int OrigNumElements = VT.getVectorNumElements();
7408 int OrigScalarSize = VT.getScalarSizeInBits();
7409 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7410 int Scale = ScalarSize / OrigScalarSize;
7411 int NumElements = OrigNumElements / Scale;
7412 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7413 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7417 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7419 if (NumLoInputs == 0 || NumHiInputs == 0) {
7420 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7421 "We have to have *some* inputs!");
7422 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7424 // FIXME: We could consider the total complexity of the permute of each
7425 // possible unpacking. Or at the least we should consider how many
7426 // half-crossings are created.
7427 // FIXME: We could consider commuting the unpacks.
7429 SmallVector<int, 32> PermMask;
7430 PermMask.assign(Size, -1);
7431 for (int i = 0; i < Size; ++i) {
7435 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7438 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7440 return DAG.getVectorShuffle(
7441 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7443 DAG.getUNDEF(VT), PermMask);
7449 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7451 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7452 /// support for floating point shuffles but not integer shuffles. These
7453 /// instructions will incur a domain crossing penalty on some chips though so
7454 /// it is better to avoid lowering through this for integer vectors where
7456 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7457 const X86Subtarget *Subtarget,
7458 SelectionDAG &DAG) {
7460 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7461 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7462 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7463 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7464 ArrayRef<int> Mask = SVOp->getMask();
7465 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7467 if (isSingleInputShuffleMask(Mask)) {
7468 // Use low duplicate instructions for masks that match their pattern.
7469 if (Subtarget->hasSSE3())
7470 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7471 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7473 // Straight shuffle of a single input vector. Simulate this by using the
7474 // single input as both of the "inputs" to this instruction..
7475 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7477 if (Subtarget->hasAVX()) {
7478 // If we have AVX, we can use VPERMILPS which will allow folding a load
7479 // into the shuffle.
7480 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7481 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7484 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7485 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7487 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7488 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7490 // If we have a single input, insert that into V1 if we can do so cheaply.
7491 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7492 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7493 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7495 // Try inverting the insertion since for v2 masks it is easy to do and we
7496 // can't reliably sort the mask one way or the other.
7497 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7498 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7499 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7500 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7504 // Try to use one of the special instruction patterns to handle two common
7505 // blend patterns if a zero-blend above didn't work.
7506 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7507 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7508 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7509 // We can either use a special instruction to load over the low double or
7510 // to move just the low double.
7512 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7514 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7516 if (Subtarget->hasSSE41())
7517 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7521 // Use dedicated unpack instructions for masks that match their pattern.
7522 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7523 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7524 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7525 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7527 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7528 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7529 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7532 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7534 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7535 /// the integer unit to minimize domain crossing penalties. However, for blends
7536 /// it falls back to the floating point shuffle operation with appropriate bit
7538 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7539 const X86Subtarget *Subtarget,
7540 SelectionDAG &DAG) {
7542 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7543 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7544 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7545 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7546 ArrayRef<int> Mask = SVOp->getMask();
7547 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7549 if (isSingleInputShuffleMask(Mask)) {
7550 // Check for being able to broadcast a single element.
7551 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7552 Mask, Subtarget, DAG))
7555 // Straight shuffle of a single input vector. For everything from SSE2
7556 // onward this has a single fast instruction with no scary immediates.
7557 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7558 V1 = DAG.getBitcast(MVT::v4i32, V1);
7559 int WidenedMask[4] = {
7560 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7561 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7562 return DAG.getBitcast(
7564 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7565 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7567 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7568 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7569 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7570 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7572 // If we have a blend of two PACKUS operations an the blend aligns with the
7573 // low and half halves, we can just merge the PACKUS operations. This is
7574 // particularly important as it lets us merge shuffles that this routine itself
7576 auto GetPackNode = [](SDValue V) {
7577 while (V.getOpcode() == ISD::BITCAST)
7578 V = V.getOperand(0);
7580 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7582 if (SDValue V1Pack = GetPackNode(V1))
7583 if (SDValue V2Pack = GetPackNode(V2))
7584 return DAG.getBitcast(MVT::v2i64,
7585 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7586 Mask[0] == 0 ? V1Pack.getOperand(0)
7587 : V1Pack.getOperand(1),
7588 Mask[1] == 2 ? V2Pack.getOperand(0)
7589 : V2Pack.getOperand(1)));
7591 // Try to use shift instructions.
7593 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7596 // When loading a scalar and then shuffling it into a vector we can often do
7597 // the insertion cheaply.
7598 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7599 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7601 // Try inverting the insertion since for v2 masks it is easy to do and we
7602 // can't reliably sort the mask one way or the other.
7603 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7604 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7605 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7608 // We have different paths for blend lowering, but they all must use the
7609 // *exact* same predicate.
7610 bool IsBlendSupported = Subtarget->hasSSE41();
7611 if (IsBlendSupported)
7612 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7616 // Use dedicated unpack instructions for masks that match their pattern.
7617 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7618 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7619 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7620 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7622 // Try to use byte rotation instructions.
7623 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7624 if (Subtarget->hasSSSE3())
7625 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7626 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7629 // If we have direct support for blends, we should lower by decomposing into
7630 // a permute. That will be faster than the domain cross.
7631 if (IsBlendSupported)
7632 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7635 // We implement this with SHUFPD which is pretty lame because it will likely
7636 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7637 // However, all the alternatives are still more cycles and newer chips don't
7638 // have this problem. It would be really nice if x86 had better shuffles here.
7639 V1 = DAG.getBitcast(MVT::v2f64, V1);
7640 V2 = DAG.getBitcast(MVT::v2f64, V2);
7641 return DAG.getBitcast(MVT::v2i64,
7642 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7645 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7647 /// This is used to disable more specialized lowerings when the shufps lowering
7648 /// will happen to be efficient.
7649 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7650 // This routine only handles 128-bit shufps.
7651 assert(Mask.size() == 4 && "Unsupported mask size!");
7653 // To lower with a single SHUFPS we need to have the low half and high half
7654 // each requiring a single input.
7655 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7657 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7663 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7665 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7666 /// It makes no assumptions about whether this is the *best* lowering, it simply
7668 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7669 ArrayRef<int> Mask, SDValue V1,
7670 SDValue V2, SelectionDAG &DAG) {
7671 SDValue LowV = V1, HighV = V2;
7672 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7675 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7677 if (NumV2Elements == 1) {
7679 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7682 // Compute the index adjacent to V2Index and in the same half by toggling
7684 int V2AdjIndex = V2Index ^ 1;
7686 if (Mask[V2AdjIndex] == -1) {
7687 // Handles all the cases where we have a single V2 element and an undef.
7688 // This will only ever happen in the high lanes because we commute the
7689 // vector otherwise.
7691 std::swap(LowV, HighV);
7692 NewMask[V2Index] -= 4;
7694 // Handle the case where the V2 element ends up adjacent to a V1 element.
7695 // To make this work, blend them together as the first step.
7696 int V1Index = V2AdjIndex;
7697 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7698 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7699 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7701 // Now proceed to reconstruct the final blend as we have the necessary
7702 // high or low half formed.
7709 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7710 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7712 } else if (NumV2Elements == 2) {
7713 if (Mask[0] < 4 && Mask[1] < 4) {
7714 // Handle the easy case where we have V1 in the low lanes and V2 in the
7718 } else if (Mask[2] < 4 && Mask[3] < 4) {
7719 // We also handle the reversed case because this utility may get called
7720 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7721 // arrange things in the right direction.
7727 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7728 // trying to place elements directly, just blend them and set up the final
7729 // shuffle to place them.
7731 // The first two blend mask elements are for V1, the second two are for
7733 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7734 Mask[2] < 4 ? Mask[2] : Mask[3],
7735 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7736 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7737 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7738 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7740 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7743 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7744 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7745 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7746 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7749 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7750 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7753 /// \brief Lower 4-lane 32-bit floating point shuffles.
7755 /// Uses instructions exclusively from the floating point unit to minimize
7756 /// domain crossing penalties, as these are sufficient to implement all v4f32
7758 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7759 const X86Subtarget *Subtarget,
7760 SelectionDAG &DAG) {
7762 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7763 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7764 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7765 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7766 ArrayRef<int> Mask = SVOp->getMask();
7767 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7770 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7772 if (NumV2Elements == 0) {
7773 // Check for being able to broadcast a single element.
7774 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7775 Mask, Subtarget, DAG))
7778 // Use even/odd duplicate instructions for masks that match their pattern.
7779 if (Subtarget->hasSSE3()) {
7780 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7781 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7782 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7783 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7786 if (Subtarget->hasAVX()) {
7787 // If we have AVX, we can use VPERMILPS which will allow folding a load
7788 // into the shuffle.
7789 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7790 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7793 // Otherwise, use a straight shuffle of a single input vector. We pass the
7794 // input vector to both operands to simulate this with a SHUFPS.
7795 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7796 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7799 // There are special ways we can lower some single-element blends. However, we
7800 // have custom ways we can lower more complex single-element blends below that
7801 // we defer to if both this and BLENDPS fail to match, so restrict this to
7802 // when the V2 input is targeting element 0 of the mask -- that is the fast
7804 if (NumV2Elements == 1 && Mask[0] >= 4)
7805 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7806 Mask, Subtarget, DAG))
7809 if (Subtarget->hasSSE41()) {
7810 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7814 // Use INSERTPS if we can complete the shuffle efficiently.
7815 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7818 if (!isSingleSHUFPSMask(Mask))
7819 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7820 DL, MVT::v4f32, V1, V2, Mask, DAG))
7824 // Use dedicated unpack instructions for masks that match their pattern.
7825 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7826 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7827 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7828 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7829 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7830 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7831 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7832 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7834 // Otherwise fall back to a SHUFPS lowering strategy.
7835 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7838 /// \brief Lower 4-lane i32 vector shuffles.
7840 /// We try to handle these with integer-domain shuffles where we can, but for
7841 /// blends we use the floating point domain blend instructions.
7842 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7843 const X86Subtarget *Subtarget,
7844 SelectionDAG &DAG) {
7846 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7847 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7848 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7849 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7850 ArrayRef<int> Mask = SVOp->getMask();
7851 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7853 // Whenever we can lower this as a zext, that instruction is strictly faster
7854 // than any alternative. It also allows us to fold memory operands into the
7855 // shuffle in many cases.
7856 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7857 Mask, Subtarget, DAG))
7861 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7863 if (NumV2Elements == 0) {
7864 // Check for being able to broadcast a single element.
7865 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7866 Mask, Subtarget, DAG))
7869 // Straight shuffle of a single input vector. For everything from SSE2
7870 // onward this has a single fast instruction with no scary immediates.
7871 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7872 // but we aren't actually going to use the UNPCK instruction because doing
7873 // so prevents folding a load into this instruction or making a copy.
7874 const int UnpackLoMask[] = {0, 0, 1, 1};
7875 const int UnpackHiMask[] = {2, 2, 3, 3};
7876 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7877 Mask = UnpackLoMask;
7878 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7879 Mask = UnpackHiMask;
7881 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7882 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7885 // Try to use shift instructions.
7887 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7890 // There are special ways we can lower some single-element blends.
7891 if (NumV2Elements == 1)
7892 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7893 Mask, Subtarget, DAG))
7896 // We have different paths for blend lowering, but they all must use the
7897 // *exact* same predicate.
7898 bool IsBlendSupported = Subtarget->hasSSE41();
7899 if (IsBlendSupported)
7900 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7904 if (SDValue Masked =
7905 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7908 // Use dedicated unpack instructions for masks that match their pattern.
7909 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7910 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7911 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7912 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7913 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7914 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7915 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7916 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7918 // Try to use byte rotation instructions.
7919 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7920 if (Subtarget->hasSSSE3())
7921 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7922 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7925 // If we have direct support for blends, we should lower by decomposing into
7926 // a permute. That will be faster than the domain cross.
7927 if (IsBlendSupported)
7928 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7931 // Try to lower by permuting the inputs into an unpack instruction.
7932 if (SDValue Unpack =
7933 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7936 // We implement this with SHUFPS because it can blend from two vectors.
7937 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7938 // up the inputs, bypassing domain shift penalties that we would encur if we
7939 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7941 return DAG.getBitcast(
7943 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
7944 DAG.getBitcast(MVT::v4f32, V2), Mask));
7947 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7948 /// shuffle lowering, and the most complex part.
7950 /// The lowering strategy is to try to form pairs of input lanes which are
7951 /// targeted at the same half of the final vector, and then use a dword shuffle
7952 /// to place them onto the right half, and finally unpack the paired lanes into
7953 /// their final position.
7955 /// The exact breakdown of how to form these dword pairs and align them on the
7956 /// correct sides is really tricky. See the comments within the function for
7957 /// more of the details.
7959 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7960 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7961 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7962 /// vector, form the analogous 128-bit 8-element Mask.
7963 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7964 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7965 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7966 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7967 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7969 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7970 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7971 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7973 SmallVector<int, 4> LoInputs;
7974 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7975 [](int M) { return M >= 0; });
7976 std::sort(LoInputs.begin(), LoInputs.end());
7977 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7978 SmallVector<int, 4> HiInputs;
7979 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7980 [](int M) { return M >= 0; });
7981 std::sort(HiInputs.begin(), HiInputs.end());
7982 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7984 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7985 int NumHToL = LoInputs.size() - NumLToL;
7987 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7988 int NumHToH = HiInputs.size() - NumLToH;
7989 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7990 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7991 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7992 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7994 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7995 // such inputs we can swap two of the dwords across the half mark and end up
7996 // with <=2 inputs to each half in each half. Once there, we can fall through
7997 // to the generic code below. For example:
7999 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8000 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8002 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8003 // and an existing 2-into-2 on the other half. In this case we may have to
8004 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8005 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8006 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8007 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8008 // half than the one we target for fixing) will be fixed when we re-enter this
8009 // path. We will also combine away any sequence of PSHUFD instructions that
8010 // result into a single instruction. Here is an example of the tricky case:
8012 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8013 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8015 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8017 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8018 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8020 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8021 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8023 // The result is fine to be handled by the generic logic.
8024 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8025 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8026 int AOffset, int BOffset) {
8027 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8028 "Must call this with A having 3 or 1 inputs from the A half.");
8029 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8030 "Must call this with B having 1 or 3 inputs from the B half.");
8031 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8032 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8034 // Compute the index of dword with only one word among the three inputs in
8035 // a half by taking the sum of the half with three inputs and subtracting
8036 // the sum of the actual three inputs. The difference is the remaining
8039 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8040 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8041 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8042 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8043 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8044 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8045 int TripleNonInputIdx =
8046 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8047 TripleDWord = TripleNonInputIdx / 2;
8049 // We use xor with one to compute the adjacent DWord to whichever one the
8051 OneInputDWord = (OneInput / 2) ^ 1;
8053 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8054 // and BToA inputs. If there is also such a problem with the BToB and AToB
8055 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8056 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8057 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8058 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8059 // Compute how many inputs will be flipped by swapping these DWords. We
8061 // to balance this to ensure we don't form a 3-1 shuffle in the other
8063 int NumFlippedAToBInputs =
8064 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8065 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8066 int NumFlippedBToBInputs =
8067 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8068 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8069 if ((NumFlippedAToBInputs == 1 &&
8070 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8071 (NumFlippedBToBInputs == 1 &&
8072 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8073 // We choose whether to fix the A half or B half based on whether that
8074 // half has zero flipped inputs. At zero, we may not be able to fix it
8075 // with that half. We also bias towards fixing the B half because that
8076 // will more commonly be the high half, and we have to bias one way.
8077 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8078 ArrayRef<int> Inputs) {
8079 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8080 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8081 PinnedIdx ^ 1) != Inputs.end();
8082 // Determine whether the free index is in the flipped dword or the
8083 // unflipped dword based on where the pinned index is. We use this bit
8084 // in an xor to conditionally select the adjacent dword.
8085 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8086 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8087 FixFreeIdx) != Inputs.end();
8088 if (IsFixIdxInput == IsFixFreeIdxInput)
8090 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8091 FixFreeIdx) != Inputs.end();
8092 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8093 "We need to be changing the number of flipped inputs!");
8094 int PSHUFHalfMask[] = {0, 1, 2, 3};
8095 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8096 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8098 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8101 if (M != -1 && M == FixIdx)
8103 else if (M != -1 && M == FixFreeIdx)
8106 if (NumFlippedBToBInputs != 0) {
8108 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8109 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8111 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8113 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8114 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8119 int PSHUFDMask[] = {0, 1, 2, 3};
8120 PSHUFDMask[ADWord] = BDWord;
8121 PSHUFDMask[BDWord] = ADWord;
8124 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8125 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8127 // Adjust the mask to match the new locations of A and B.
8129 if (M != -1 && M/2 == ADWord)
8130 M = 2 * BDWord + M % 2;
8131 else if (M != -1 && M/2 == BDWord)
8132 M = 2 * ADWord + M % 2;
8134 // Recurse back into this routine to re-compute state now that this isn't
8135 // a 3 and 1 problem.
8136 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8139 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8140 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8141 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8142 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8144 // At this point there are at most two inputs to the low and high halves from
8145 // each half. That means the inputs can always be grouped into dwords and
8146 // those dwords can then be moved to the correct half with a dword shuffle.
8147 // We use at most one low and one high word shuffle to collect these paired
8148 // inputs into dwords, and finally a dword shuffle to place them.
8149 int PSHUFLMask[4] = {-1, -1, -1, -1};
8150 int PSHUFHMask[4] = {-1, -1, -1, -1};
8151 int PSHUFDMask[4] = {-1, -1, -1, -1};
8153 // First fix the masks for all the inputs that are staying in their
8154 // original halves. This will then dictate the targets of the cross-half
8156 auto fixInPlaceInputs =
8157 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8158 MutableArrayRef<int> SourceHalfMask,
8159 MutableArrayRef<int> HalfMask, int HalfOffset) {
8160 if (InPlaceInputs.empty())
8162 if (InPlaceInputs.size() == 1) {
8163 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8164 InPlaceInputs[0] - HalfOffset;
8165 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8168 if (IncomingInputs.empty()) {
8169 // Just fix all of the in place inputs.
8170 for (int Input : InPlaceInputs) {
8171 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8172 PSHUFDMask[Input / 2] = Input / 2;
8177 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8178 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8179 InPlaceInputs[0] - HalfOffset;
8180 // Put the second input next to the first so that they are packed into
8181 // a dword. We find the adjacent index by toggling the low bit.
8182 int AdjIndex = InPlaceInputs[0] ^ 1;
8183 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8184 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8185 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8187 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8188 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8190 // Now gather the cross-half inputs and place them into a free dword of
8191 // their target half.
8192 // FIXME: This operation could almost certainly be simplified dramatically to
8193 // look more like the 3-1 fixing operation.
8194 auto moveInputsToRightHalf = [&PSHUFDMask](
8195 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8196 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8197 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8199 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8200 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8202 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8204 int LowWord = Word & ~1;
8205 int HighWord = Word | 1;
8206 return isWordClobbered(SourceHalfMask, LowWord) ||
8207 isWordClobbered(SourceHalfMask, HighWord);
8210 if (IncomingInputs.empty())
8213 if (ExistingInputs.empty()) {
8214 // Map any dwords with inputs from them into the right half.
8215 for (int Input : IncomingInputs) {
8216 // If the source half mask maps over the inputs, turn those into
8217 // swaps and use the swapped lane.
8218 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8219 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8220 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8221 Input - SourceOffset;
8222 // We have to swap the uses in our half mask in one sweep.
8223 for (int &M : HalfMask)
8224 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8226 else if (M == Input)
8227 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8229 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8230 Input - SourceOffset &&
8231 "Previous placement doesn't match!");
8233 // Note that this correctly re-maps both when we do a swap and when
8234 // we observe the other side of the swap above. We rely on that to
8235 // avoid swapping the members of the input list directly.
8236 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8239 // Map the input's dword into the correct half.
8240 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8241 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8243 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8245 "Previous placement doesn't match!");
8248 // And just directly shift any other-half mask elements to be same-half
8249 // as we will have mirrored the dword containing the element into the
8250 // same position within that half.
8251 for (int &M : HalfMask)
8252 if (M >= SourceOffset && M < SourceOffset + 4) {
8253 M = M - SourceOffset + DestOffset;
8254 assert(M >= 0 && "This should never wrap below zero!");
8259 // Ensure we have the input in a viable dword of its current half. This
8260 // is particularly tricky because the original position may be clobbered
8261 // by inputs being moved and *staying* in that half.
8262 if (IncomingInputs.size() == 1) {
8263 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8264 int InputFixed = std::find(std::begin(SourceHalfMask),
8265 std::end(SourceHalfMask), -1) -
8266 std::begin(SourceHalfMask) + SourceOffset;
8267 SourceHalfMask[InputFixed - SourceOffset] =
8268 IncomingInputs[0] - SourceOffset;
8269 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8271 IncomingInputs[0] = InputFixed;
8273 } else if (IncomingInputs.size() == 2) {
8274 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8275 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8276 // We have two non-adjacent or clobbered inputs we need to extract from
8277 // the source half. To do this, we need to map them into some adjacent
8278 // dword slot in the source mask.
8279 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8280 IncomingInputs[1] - SourceOffset};
8282 // If there is a free slot in the source half mask adjacent to one of
8283 // the inputs, place the other input in it. We use (Index XOR 1) to
8284 // compute an adjacent index.
8285 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8286 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8287 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8288 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8289 InputsFixed[1] = InputsFixed[0] ^ 1;
8290 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8291 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8292 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8293 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8294 InputsFixed[0] = InputsFixed[1] ^ 1;
8295 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8296 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8297 // The two inputs are in the same DWord but it is clobbered and the
8298 // adjacent DWord isn't used at all. Move both inputs to the free
8300 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8301 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8302 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8303 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8305 // The only way we hit this point is if there is no clobbering
8306 // (because there are no off-half inputs to this half) and there is no
8307 // free slot adjacent to one of the inputs. In this case, we have to
8308 // swap an input with a non-input.
8309 for (int i = 0; i < 4; ++i)
8310 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8311 "We can't handle any clobbers here!");
8312 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8313 "Cannot have adjacent inputs here!");
8315 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8316 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8318 // We also have to update the final source mask in this case because
8319 // it may need to undo the above swap.
8320 for (int &M : FinalSourceHalfMask)
8321 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8322 M = InputsFixed[1] + SourceOffset;
8323 else if (M == InputsFixed[1] + SourceOffset)
8324 M = (InputsFixed[0] ^ 1) + SourceOffset;
8326 InputsFixed[1] = InputsFixed[0] ^ 1;
8329 // Point everything at the fixed inputs.
8330 for (int &M : HalfMask)
8331 if (M == IncomingInputs[0])
8332 M = InputsFixed[0] + SourceOffset;
8333 else if (M == IncomingInputs[1])
8334 M = InputsFixed[1] + SourceOffset;
8336 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8337 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8340 llvm_unreachable("Unhandled input size!");
8343 // Now hoist the DWord down to the right half.
8344 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8345 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8346 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8347 for (int &M : HalfMask)
8348 for (int Input : IncomingInputs)
8350 M = FreeDWord * 2 + Input % 2;
8352 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8353 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8354 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8355 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8357 // Now enact all the shuffles we've computed to move the inputs into their
8359 if (!isNoopShuffleMask(PSHUFLMask))
8360 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8361 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8362 if (!isNoopShuffleMask(PSHUFHMask))
8363 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8364 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8365 if (!isNoopShuffleMask(PSHUFDMask))
8368 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8369 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8371 // At this point, each half should contain all its inputs, and we can then
8372 // just shuffle them into their final position.
8373 assert(std::count_if(LoMask.begin(), LoMask.end(),
8374 [](int M) { return M >= 4; }) == 0 &&
8375 "Failed to lift all the high half inputs to the low mask!");
8376 assert(std::count_if(HiMask.begin(), HiMask.end(),
8377 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8378 "Failed to lift all the low half inputs to the high mask!");
8380 // Do a half shuffle for the low mask.
8381 if (!isNoopShuffleMask(LoMask))
8382 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8383 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8385 // Do a half shuffle with the high mask after shifting its values down.
8386 for (int &M : HiMask)
8389 if (!isNoopShuffleMask(HiMask))
8390 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8391 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8396 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8397 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8398 SDValue V2, ArrayRef<int> Mask,
8399 SelectionDAG &DAG, bool &V1InUse,
8401 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8407 int Size = Mask.size();
8408 int Scale = 16 / Size;
8409 for (int i = 0; i < 16; ++i) {
8410 if (Mask[i / Scale] == -1) {
8411 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8413 const int ZeroMask = 0x80;
8414 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8416 int V2Idx = Mask[i / Scale] < Size
8418 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8419 if (Zeroable[i / Scale])
8420 V1Idx = V2Idx = ZeroMask;
8421 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8422 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8423 V1InUse |= (ZeroMask != V1Idx);
8424 V2InUse |= (ZeroMask != V2Idx);
8429 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8430 DAG.getBitcast(MVT::v16i8, V1),
8431 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8433 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8434 DAG.getBitcast(MVT::v16i8, V2),
8435 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8437 // If we need shuffled inputs from both, blend the two.
8439 if (V1InUse && V2InUse)
8440 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8442 V = V1InUse ? V1 : V2;
8444 // Cast the result back to the correct type.
8445 return DAG.getBitcast(VT, V);
8448 /// \brief Generic lowering of 8-lane i16 shuffles.
8450 /// This handles both single-input shuffles and combined shuffle/blends with
8451 /// two inputs. The single input shuffles are immediately delegated to
8452 /// a dedicated lowering routine.
8454 /// The blends are lowered in one of three fundamental ways. If there are few
8455 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8456 /// of the input is significantly cheaper when lowered as an interleaving of
8457 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8458 /// halves of the inputs separately (making them have relatively few inputs)
8459 /// and then concatenate them.
8460 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8461 const X86Subtarget *Subtarget,
8462 SelectionDAG &DAG) {
8464 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8465 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8466 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8467 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8468 ArrayRef<int> OrigMask = SVOp->getMask();
8469 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8470 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8471 MutableArrayRef<int> Mask(MaskStorage);
8473 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8475 // Whenever we can lower this as a zext, that instruction is strictly faster
8476 // than any alternative.
8477 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8478 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8481 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8483 auto isV2 = [](int M) { return M >= 8; };
8485 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8487 if (NumV2Inputs == 0) {
8488 // Check for being able to broadcast a single element.
8489 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8490 Mask, Subtarget, DAG))
8493 // Try to use shift instructions.
8495 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8498 // Use dedicated unpack instructions for masks that match their pattern.
8499 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8500 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8501 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8502 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8504 // Try to use byte rotation instructions.
8505 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8506 Mask, Subtarget, DAG))
8509 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8513 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8514 "All single-input shuffles should be canonicalized to be V1-input "
8517 // Try to use shift instructions.
8519 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8522 // There are special ways we can lower some single-element blends.
8523 if (NumV2Inputs == 1)
8524 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8525 Mask, Subtarget, DAG))
8528 // We have different paths for blend lowering, but they all must use the
8529 // *exact* same predicate.
8530 bool IsBlendSupported = Subtarget->hasSSE41();
8531 if (IsBlendSupported)
8532 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8536 if (SDValue Masked =
8537 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8540 // Use dedicated unpack instructions for masks that match their pattern.
8541 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8542 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8543 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8544 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8546 // Try to use byte rotation instructions.
8547 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8548 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8551 if (SDValue BitBlend =
8552 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8555 if (SDValue Unpack =
8556 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8559 // If we can't directly blend but can use PSHUFB, that will be better as it
8560 // can both shuffle and set up the inefficient blend.
8561 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8562 bool V1InUse, V2InUse;
8563 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8567 // We can always bit-blend if we have to so the fallback strategy is to
8568 // decompose into single-input permutes and blends.
8569 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8573 /// \brief Check whether a compaction lowering can be done by dropping even
8574 /// elements and compute how many times even elements must be dropped.
8576 /// This handles shuffles which take every Nth element where N is a power of
8577 /// two. Example shuffle masks:
8579 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8580 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8581 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8582 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8583 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8584 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8586 /// Any of these lanes can of course be undef.
8588 /// This routine only supports N <= 3.
8589 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8592 /// \returns N above, or the number of times even elements must be dropped if
8593 /// there is such a number. Otherwise returns zero.
8594 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8595 // Figure out whether we're looping over two inputs or just one.
8596 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8598 // The modulus for the shuffle vector entries is based on whether this is
8599 // a single input or not.
8600 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8601 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8602 "We should only be called with masks with a power-of-2 size!");
8604 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8606 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8607 // and 2^3 simultaneously. This is because we may have ambiguity with
8608 // partially undef inputs.
8609 bool ViableForN[3] = {true, true, true};
8611 for (int i = 0, e = Mask.size(); i < e; ++i) {
8612 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8617 bool IsAnyViable = false;
8618 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8619 if (ViableForN[j]) {
8622 // The shuffle mask must be equal to (i * 2^N) % M.
8623 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8626 ViableForN[j] = false;
8628 // Early exit if we exhaust the possible powers of two.
8633 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8637 // Return 0 as there is no viable power of two.
8641 /// \brief Generic lowering of v16i8 shuffles.
8643 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8644 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8645 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8646 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8648 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8649 const X86Subtarget *Subtarget,
8650 SelectionDAG &DAG) {
8652 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8653 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8654 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8655 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8656 ArrayRef<int> Mask = SVOp->getMask();
8657 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8659 // Try to use shift instructions.
8661 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8664 // Try to use byte rotation instructions.
8665 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8666 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8669 // Try to use a zext lowering.
8670 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8671 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8675 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8677 // For single-input shuffles, there are some nicer lowering tricks we can use.
8678 if (NumV2Elements == 0) {
8679 // Check for being able to broadcast a single element.
8680 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8681 Mask, Subtarget, DAG))
8684 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8685 // Notably, this handles splat and partial-splat shuffles more efficiently.
8686 // However, it only makes sense if the pre-duplication shuffle simplifies
8687 // things significantly. Currently, this means we need to be able to
8688 // express the pre-duplication shuffle as an i16 shuffle.
8690 // FIXME: We should check for other patterns which can be widened into an
8691 // i16 shuffle as well.
8692 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8693 for (int i = 0; i < 16; i += 2)
8694 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8699 auto tryToWidenViaDuplication = [&]() -> SDValue {
8700 if (!canWidenViaDuplication(Mask))
8702 SmallVector<int, 4> LoInputs;
8703 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8704 [](int M) { return M >= 0 && M < 8; });
8705 std::sort(LoInputs.begin(), LoInputs.end());
8706 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8708 SmallVector<int, 4> HiInputs;
8709 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8710 [](int M) { return M >= 8; });
8711 std::sort(HiInputs.begin(), HiInputs.end());
8712 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8715 bool TargetLo = LoInputs.size() >= HiInputs.size();
8716 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8717 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8719 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8720 SmallDenseMap<int, int, 8> LaneMap;
8721 for (int I : InPlaceInputs) {
8722 PreDupI16Shuffle[I/2] = I/2;
8725 int j = TargetLo ? 0 : 4, je = j + 4;
8726 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8727 // Check if j is already a shuffle of this input. This happens when
8728 // there are two adjacent bytes after we move the low one.
8729 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8730 // If we haven't yet mapped the input, search for a slot into which
8732 while (j < je && PreDupI16Shuffle[j] != -1)
8736 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8739 // Map this input with the i16 shuffle.
8740 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8743 // Update the lane map based on the mapping we ended up with.
8744 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8746 V1 = DAG.getBitcast(
8748 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8749 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8751 // Unpack the bytes to form the i16s that will be shuffled into place.
8752 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8753 MVT::v16i8, V1, V1);
8755 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8756 for (int i = 0; i < 16; ++i)
8757 if (Mask[i] != -1) {
8758 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8759 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8760 if (PostDupI16Shuffle[i / 2] == -1)
8761 PostDupI16Shuffle[i / 2] = MappedMask;
8763 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8764 "Conflicting entrties in the original shuffle!");
8766 return DAG.getBitcast(
8768 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8769 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8771 if (SDValue V = tryToWidenViaDuplication())
8775 // Use dedicated unpack instructions for masks that match their pattern.
8776 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8777 0, 16, 1, 17, 2, 18, 3, 19,
8779 4, 20, 5, 21, 6, 22, 7, 23}))
8780 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8781 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8782 8, 24, 9, 25, 10, 26, 11, 27,
8784 12, 28, 13, 29, 14, 30, 15, 31}))
8785 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8787 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8788 // with PSHUFB. It is important to do this before we attempt to generate any
8789 // blends but after all of the single-input lowerings. If the single input
8790 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8791 // want to preserve that and we can DAG combine any longer sequences into
8792 // a PSHUFB in the end. But once we start blending from multiple inputs,
8793 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8794 // and there are *very* few patterns that would actually be faster than the
8795 // PSHUFB approach because of its ability to zero lanes.
8797 // FIXME: The only exceptions to the above are blends which are exact
8798 // interleavings with direct instructions supporting them. We currently don't
8799 // handle those well here.
8800 if (Subtarget->hasSSSE3()) {
8801 bool V1InUse = false;
8802 bool V2InUse = false;
8804 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8805 DAG, V1InUse, V2InUse);
8807 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8808 // do so. This avoids using them to handle blends-with-zero which is
8809 // important as a single pshufb is significantly faster for that.
8810 if (V1InUse && V2InUse) {
8811 if (Subtarget->hasSSE41())
8812 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8813 Mask, Subtarget, DAG))
8816 // We can use an unpack to do the blending rather than an or in some
8817 // cases. Even though the or may be (very minorly) more efficient, we
8818 // preference this lowering because there are common cases where part of
8819 // the complexity of the shuffles goes away when we do the final blend as
8821 // FIXME: It might be worth trying to detect if the unpack-feeding
8822 // shuffles will both be pshufb, in which case we shouldn't bother with
8824 if (SDValue Unpack =
8825 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8832 // There are special ways we can lower some single-element blends.
8833 if (NumV2Elements == 1)
8834 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8835 Mask, Subtarget, DAG))
8838 if (SDValue BitBlend =
8839 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8842 // Check whether a compaction lowering can be done. This handles shuffles
8843 // which take every Nth element for some even N. See the helper function for
8846 // We special case these as they can be particularly efficiently handled with
8847 // the PACKUSB instruction on x86 and they show up in common patterns of
8848 // rearranging bytes to truncate wide elements.
8849 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8850 // NumEvenDrops is the power of two stride of the elements. Another way of
8851 // thinking about it is that we need to drop the even elements this many
8852 // times to get the original input.
8853 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8855 // First we need to zero all the dropped bytes.
8856 assert(NumEvenDrops <= 3 &&
8857 "No support for dropping even elements more than 3 times.");
8858 // We use the mask type to pick which bytes are preserved based on how many
8859 // elements are dropped.
8860 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8861 SDValue ByteClearMask = DAG.getBitcast(
8862 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
8863 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8865 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8867 // Now pack things back together.
8868 V1 = DAG.getBitcast(MVT::v8i16, V1);
8869 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
8870 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8871 for (int i = 1; i < NumEvenDrops; ++i) {
8872 Result = DAG.getBitcast(MVT::v8i16, Result);
8873 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8879 // Handle multi-input cases by blending single-input shuffles.
8880 if (NumV2Elements > 0)
8881 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8884 // The fallback path for single-input shuffles widens this into two v8i16
8885 // vectors with unpacks, shuffles those, and then pulls them back together
8889 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8890 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8891 for (int i = 0; i < 16; ++i)
8893 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8895 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8897 SDValue VLoHalf, VHiHalf;
8898 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8899 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8901 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8902 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8903 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8904 [](int M) { return M >= 0 && M % 2 == 1; })) {
8905 // Use a mask to drop the high bytes.
8906 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
8907 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8908 DAG.getConstant(0x00FF, DL, MVT::v8i16));
8910 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8911 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8913 // Squash the masks to point directly into VLoHalf.
8914 for (int &M : LoBlendMask)
8917 for (int &M : HiBlendMask)
8921 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8922 // VHiHalf so that we can blend them as i16s.
8923 VLoHalf = DAG.getBitcast(
8924 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8925 VHiHalf = DAG.getBitcast(
8926 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8929 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8930 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8932 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8935 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8937 /// This routine breaks down the specific type of 128-bit shuffle and
8938 /// dispatches to the lowering routines accordingly.
8939 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8940 MVT VT, const X86Subtarget *Subtarget,
8941 SelectionDAG &DAG) {
8942 switch (VT.SimpleTy) {
8944 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8946 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8948 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8950 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8952 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8954 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8957 llvm_unreachable("Unimplemented!");
8961 /// \brief Helper function to test whether a shuffle mask could be
8962 /// simplified by widening the elements being shuffled.
8964 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8965 /// leaves it in an unspecified state.
8967 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8968 /// shuffle masks. The latter have the special property of a '-2' representing
8969 /// a zero-ed lane of a vector.
8970 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8971 SmallVectorImpl<int> &WidenedMask) {
8972 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8973 // If both elements are undef, its trivial.
8974 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8975 WidenedMask.push_back(SM_SentinelUndef);
8979 // Check for an undef mask and a mask value properly aligned to fit with
8980 // a pair of values. If we find such a case, use the non-undef mask's value.
8981 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
8982 WidenedMask.push_back(Mask[i + 1] / 2);
8985 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
8986 WidenedMask.push_back(Mask[i] / 2);
8990 // When zeroing, we need to spread the zeroing across both lanes to widen.
8991 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
8992 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
8993 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
8994 WidenedMask.push_back(SM_SentinelZero);
9000 // Finally check if the two mask values are adjacent and aligned with
9002 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9003 WidenedMask.push_back(Mask[i] / 2);
9007 // Otherwise we can't safely widen the elements used in this shuffle.
9010 assert(WidenedMask.size() == Mask.size() / 2 &&
9011 "Incorrect size of mask after widening the elements!");
9016 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9018 /// This routine just extracts two subvectors, shuffles them independently, and
9019 /// then concatenates them back together. This should work effectively with all
9020 /// AVX vector shuffle types.
9021 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9022 SDValue V2, ArrayRef<int> Mask,
9023 SelectionDAG &DAG) {
9024 assert(VT.getSizeInBits() >= 256 &&
9025 "Only for 256-bit or wider vector shuffles!");
9026 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9027 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9029 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9030 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9032 int NumElements = VT.getVectorNumElements();
9033 int SplitNumElements = NumElements / 2;
9034 MVT ScalarVT = VT.getScalarType();
9035 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9037 // Rather than splitting build-vectors, just build two narrower build
9038 // vectors. This helps shuffling with splats and zeros.
9039 auto SplitVector = [&](SDValue V) {
9040 while (V.getOpcode() == ISD::BITCAST)
9041 V = V->getOperand(0);
9043 MVT OrigVT = V.getSimpleValueType();
9044 int OrigNumElements = OrigVT.getVectorNumElements();
9045 int OrigSplitNumElements = OrigNumElements / 2;
9046 MVT OrigScalarVT = OrigVT.getScalarType();
9047 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9051 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9053 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9054 DAG.getIntPtrConstant(0, DL));
9055 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9056 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9059 SmallVector<SDValue, 16> LoOps, HiOps;
9060 for (int i = 0; i < OrigSplitNumElements; ++i) {
9061 LoOps.push_back(BV->getOperand(i));
9062 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9064 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9065 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9067 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9068 DAG.getBitcast(SplitVT, HiV));
9071 SDValue LoV1, HiV1, LoV2, HiV2;
9072 std::tie(LoV1, HiV1) = SplitVector(V1);
9073 std::tie(LoV2, HiV2) = SplitVector(V2);
9075 // Now create two 4-way blends of these half-width vectors.
9076 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9077 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9078 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9079 for (int i = 0; i < SplitNumElements; ++i) {
9080 int M = HalfMask[i];
9081 if (M >= NumElements) {
9082 if (M >= NumElements + SplitNumElements)
9086 V2BlendMask.push_back(M - NumElements);
9087 V1BlendMask.push_back(-1);
9088 BlendMask.push_back(SplitNumElements + i);
9089 } else if (M >= 0) {
9090 if (M >= SplitNumElements)
9094 V2BlendMask.push_back(-1);
9095 V1BlendMask.push_back(M);
9096 BlendMask.push_back(i);
9098 V2BlendMask.push_back(-1);
9099 V1BlendMask.push_back(-1);
9100 BlendMask.push_back(-1);
9104 // Because the lowering happens after all combining takes place, we need to
9105 // manually combine these blend masks as much as possible so that we create
9106 // a minimal number of high-level vector shuffle nodes.
9108 // First try just blending the halves of V1 or V2.
9109 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9110 return DAG.getUNDEF(SplitVT);
9111 if (!UseLoV2 && !UseHiV2)
9112 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9113 if (!UseLoV1 && !UseHiV1)
9114 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9116 SDValue V1Blend, V2Blend;
9117 if (UseLoV1 && UseHiV1) {
9119 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9121 // We only use half of V1 so map the usage down into the final blend mask.
9122 V1Blend = UseLoV1 ? LoV1 : HiV1;
9123 for (int i = 0; i < SplitNumElements; ++i)
9124 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9125 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9127 if (UseLoV2 && UseHiV2) {
9129 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9131 // We only use half of V2 so map the usage down into the final blend mask.
9132 V2Blend = UseLoV2 ? LoV2 : HiV2;
9133 for (int i = 0; i < SplitNumElements; ++i)
9134 if (BlendMask[i] >= SplitNumElements)
9135 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9137 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9139 SDValue Lo = HalfBlend(LoMask);
9140 SDValue Hi = HalfBlend(HiMask);
9141 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9144 /// \brief Either split a vector in halves or decompose the shuffles and the
9147 /// This is provided as a good fallback for many lowerings of non-single-input
9148 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9149 /// between splitting the shuffle into 128-bit components and stitching those
9150 /// back together vs. extracting the single-input shuffles and blending those
9152 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9153 SDValue V2, ArrayRef<int> Mask,
9154 SelectionDAG &DAG) {
9155 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9156 "lower single-input shuffles as it "
9157 "could then recurse on itself.");
9158 int Size = Mask.size();
9160 // If this can be modeled as a broadcast of two elements followed by a blend,
9161 // prefer that lowering. This is especially important because broadcasts can
9162 // often fold with memory operands.
9163 auto DoBothBroadcast = [&] {
9164 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9167 if (V2BroadcastIdx == -1)
9168 V2BroadcastIdx = M - Size;
9169 else if (M - Size != V2BroadcastIdx)
9171 } else if (M >= 0) {
9172 if (V1BroadcastIdx == -1)
9174 else if (M != V1BroadcastIdx)
9179 if (DoBothBroadcast())
9180 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9183 // If the inputs all stem from a single 128-bit lane of each input, then we
9184 // split them rather than blending because the split will decompose to
9185 // unusually few instructions.
9186 int LaneCount = VT.getSizeInBits() / 128;
9187 int LaneSize = Size / LaneCount;
9188 SmallBitVector LaneInputs[2];
9189 LaneInputs[0].resize(LaneCount, false);
9190 LaneInputs[1].resize(LaneCount, false);
9191 for (int i = 0; i < Size; ++i)
9193 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9194 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9195 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9197 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9198 // that the decomposed single-input shuffles don't end up here.
9199 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9202 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9203 /// a permutation and blend of those lanes.
9205 /// This essentially blends the out-of-lane inputs to each lane into the lane
9206 /// from a permuted copy of the vector. This lowering strategy results in four
9207 /// instructions in the worst case for a single-input cross lane shuffle which
9208 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9209 /// of. Special cases for each particular shuffle pattern should be handled
9210 /// prior to trying this lowering.
9211 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9212 SDValue V1, SDValue V2,
9214 SelectionDAG &DAG) {
9215 // FIXME: This should probably be generalized for 512-bit vectors as well.
9216 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9217 int LaneSize = Mask.size() / 2;
9219 // If there are only inputs from one 128-bit lane, splitting will in fact be
9220 // less expensive. The flags track whether the given lane contains an element
9221 // that crosses to another lane.
9222 bool LaneCrossing[2] = {false, false};
9223 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9224 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9225 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9226 if (!LaneCrossing[0] || !LaneCrossing[1])
9227 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9229 if (isSingleInputShuffleMask(Mask)) {
9230 SmallVector<int, 32> FlippedBlendMask;
9231 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9232 FlippedBlendMask.push_back(
9233 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9235 : Mask[i] % LaneSize +
9236 (i / LaneSize) * LaneSize + Size));
9238 // Flip the vector, and blend the results which should now be in-lane. The
9239 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9240 // 5 for the high source. The value 3 selects the high half of source 2 and
9241 // the value 2 selects the low half of source 2. We only use source 2 to
9242 // allow folding it into a memory operand.
9243 unsigned PERMMask = 3 | 2 << 4;
9244 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9245 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9246 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9249 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9250 // will be handled by the above logic and a blend of the results, much like
9251 // other patterns in AVX.
9252 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9255 /// \brief Handle lowering 2-lane 128-bit shuffles.
9256 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9257 SDValue V2, ArrayRef<int> Mask,
9258 const X86Subtarget *Subtarget,
9259 SelectionDAG &DAG) {
9260 // TODO: If minimizing size and one of the inputs is a zero vector and the
9261 // the zero vector has only one use, we could use a VPERM2X128 to save the
9262 // instruction bytes needed to explicitly generate the zero vector.
9264 // Blends are faster and handle all the non-lane-crossing cases.
9265 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9269 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9270 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9272 // If either input operand is a zero vector, use VPERM2X128 because its mask
9273 // allows us to replace the zero input with an implicit zero.
9274 if (!IsV1Zero && !IsV2Zero) {
9275 // Check for patterns which can be matched with a single insert of a 128-bit
9277 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9278 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9279 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9280 VT.getVectorNumElements() / 2);
9281 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9282 DAG.getIntPtrConstant(0, DL));
9283 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9284 OnlyUsesV1 ? V1 : V2,
9285 DAG.getIntPtrConstant(0, DL));
9286 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9290 // Otherwise form a 128-bit permutation. After accounting for undefs,
9291 // convert the 64-bit shuffle mask selection values into 128-bit
9292 // selection bits by dividing the indexes by 2 and shifting into positions
9293 // defined by a vperm2*128 instruction's immediate control byte.
9295 // The immediate permute control byte looks like this:
9296 // [1:0] - select 128 bits from sources for low half of destination
9298 // [3] - zero low half of destination
9299 // [5:4] - select 128 bits from sources for high half of destination
9301 // [7] - zero high half of destination
9303 int MaskLO = Mask[0];
9304 if (MaskLO == SM_SentinelUndef)
9305 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9307 int MaskHI = Mask[2];
9308 if (MaskHI == SM_SentinelUndef)
9309 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9311 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9313 // If either input is a zero vector, replace it with an undef input.
9314 // Shuffle mask values < 4 are selecting elements of V1.
9315 // Shuffle mask values >= 4 are selecting elements of V2.
9316 // Adjust each half of the permute mask by clearing the half that was
9317 // selecting the zero vector and setting the zero mask bit.
9319 V1 = DAG.getUNDEF(VT);
9321 PermMask = (PermMask & 0xf0) | 0x08;
9323 PermMask = (PermMask & 0x0f) | 0x80;
9326 V2 = DAG.getUNDEF(VT);
9328 PermMask = (PermMask & 0xf0) | 0x08;
9330 PermMask = (PermMask & 0x0f) | 0x80;
9333 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9334 DAG.getConstant(PermMask, DL, MVT::i8));
9337 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9338 /// shuffling each lane.
9340 /// This will only succeed when the result of fixing the 128-bit lanes results
9341 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9342 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9343 /// the lane crosses early and then use simpler shuffles within each lane.
9345 /// FIXME: It might be worthwhile at some point to support this without
9346 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9347 /// in x86 only floating point has interesting non-repeating shuffles, and even
9348 /// those are still *marginally* more expensive.
9349 static SDValue lowerVectorShuffleByMerging128BitLanes(
9350 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9351 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9352 assert(!isSingleInputShuffleMask(Mask) &&
9353 "This is only useful with multiple inputs.");
9355 int Size = Mask.size();
9356 int LaneSize = 128 / VT.getScalarSizeInBits();
9357 int NumLanes = Size / LaneSize;
9358 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9360 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9361 // check whether the in-128-bit lane shuffles share a repeating pattern.
9362 SmallVector<int, 4> Lanes;
9363 Lanes.resize(NumLanes, -1);
9364 SmallVector<int, 4> InLaneMask;
9365 InLaneMask.resize(LaneSize, -1);
9366 for (int i = 0; i < Size; ++i) {
9370 int j = i / LaneSize;
9373 // First entry we've seen for this lane.
9374 Lanes[j] = Mask[i] / LaneSize;
9375 } else if (Lanes[j] != Mask[i] / LaneSize) {
9376 // This doesn't match the lane selected previously!
9380 // Check that within each lane we have a consistent shuffle mask.
9381 int k = i % LaneSize;
9382 if (InLaneMask[k] < 0) {
9383 InLaneMask[k] = Mask[i] % LaneSize;
9384 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9385 // This doesn't fit a repeating in-lane mask.
9390 // First shuffle the lanes into place.
9391 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9392 VT.getSizeInBits() / 64);
9393 SmallVector<int, 8> LaneMask;
9394 LaneMask.resize(NumLanes * 2, -1);
9395 for (int i = 0; i < NumLanes; ++i)
9396 if (Lanes[i] >= 0) {
9397 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9398 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9401 V1 = DAG.getBitcast(LaneVT, V1);
9402 V2 = DAG.getBitcast(LaneVT, V2);
9403 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9405 // Cast it back to the type we actually want.
9406 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9408 // Now do a simple shuffle that isn't lane crossing.
9409 SmallVector<int, 8> NewMask;
9410 NewMask.resize(Size, -1);
9411 for (int i = 0; i < Size; ++i)
9413 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9414 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9415 "Must not introduce lane crosses at this point!");
9417 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9420 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9423 /// This returns true if the elements from a particular input are already in the
9424 /// slot required by the given mask and require no permutation.
9425 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9426 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9427 int Size = Mask.size();
9428 for (int i = 0; i < Size; ++i)
9429 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9435 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9436 ArrayRef<int> Mask, SDValue V1,
9437 SDValue V2, SelectionDAG &DAG) {
9439 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9440 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9441 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9442 int NumElts = VT.getVectorNumElements();
9443 bool ShufpdMask = true;
9444 bool CommutableMask = true;
9445 unsigned Immediate = 0;
9446 for (int i = 0; i < NumElts; ++i) {
9449 int Val = (i & 6) + NumElts * (i & 1);
9450 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9451 if (Mask[i] < Val || Mask[i] > Val + 1)
9453 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9454 CommutableMask = false;
9455 Immediate |= (Mask[i] % 2) << i;
9458 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
9459 DAG.getConstant(Immediate, DL, MVT::i8));
9461 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
9462 DAG.getConstant(Immediate, DL, MVT::i8));
9466 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9468 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9469 /// isn't available.
9470 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9471 const X86Subtarget *Subtarget,
9472 SelectionDAG &DAG) {
9474 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9475 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9476 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9477 ArrayRef<int> Mask = SVOp->getMask();
9478 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9480 SmallVector<int, 4> WidenedMask;
9481 if (canWidenShuffleElements(Mask, WidenedMask))
9482 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9485 if (isSingleInputShuffleMask(Mask)) {
9486 // Check for being able to broadcast a single element.
9487 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9488 Mask, Subtarget, DAG))
9491 // Use low duplicate instructions for masks that match their pattern.
9492 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9493 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9495 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9496 // Non-half-crossing single input shuffles can be lowerid with an
9497 // interleaved permutation.
9498 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9499 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9500 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9501 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9504 // With AVX2 we have direct support for this permutation.
9505 if (Subtarget->hasAVX2())
9506 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9507 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9509 // Otherwise, fall back.
9510 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9514 // X86 has dedicated unpack instructions that can handle specific blend
9515 // operations: UNPCKH and UNPCKL.
9516 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9517 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9518 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9519 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9520 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9521 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9522 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9523 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9525 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9529 // Check if the blend happens to exactly fit that of SHUFPD.
9531 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
9534 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9535 // shuffle. However, if we have AVX2 and either inputs are already in place,
9536 // we will be able to shuffle even across lanes the other input in a single
9537 // instruction so skip this pattern.
9538 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9539 isShuffleMaskInputInPlace(1, Mask))))
9540 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9541 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9544 // If we have AVX2 then we always want to lower with a blend because an v4 we
9545 // can fully permute the elements.
9546 if (Subtarget->hasAVX2())
9547 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9550 // Otherwise fall back on generic lowering.
9551 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9554 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9556 /// This routine is only called when we have AVX2 and thus a reasonable
9557 /// instruction set for v4i64 shuffling..
9558 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9559 const X86Subtarget *Subtarget,
9560 SelectionDAG &DAG) {
9562 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9563 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9564 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9565 ArrayRef<int> Mask = SVOp->getMask();
9566 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9567 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9569 SmallVector<int, 4> WidenedMask;
9570 if (canWidenShuffleElements(Mask, WidenedMask))
9571 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9574 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9578 // Check for being able to broadcast a single element.
9579 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9580 Mask, Subtarget, DAG))
9583 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9584 // use lower latency instructions that will operate on both 128-bit lanes.
9585 SmallVector<int, 2> RepeatedMask;
9586 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9587 if (isSingleInputShuffleMask(Mask)) {
9588 int PSHUFDMask[] = {-1, -1, -1, -1};
9589 for (int i = 0; i < 2; ++i)
9590 if (RepeatedMask[i] >= 0) {
9591 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9592 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9594 return DAG.getBitcast(
9596 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9597 DAG.getBitcast(MVT::v8i32, V1),
9598 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9602 // AVX2 provides a direct instruction for permuting a single input across
9604 if (isSingleInputShuffleMask(Mask))
9605 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9606 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9608 // Try to use shift instructions.
9610 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9613 // Use dedicated unpack instructions for masks that match their pattern.
9614 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9615 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9616 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9617 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9618 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9619 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9620 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9621 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9623 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9624 // shuffle. However, if we have AVX2 and either inputs are already in place,
9625 // we will be able to shuffle even across lanes the other input in a single
9626 // instruction so skip this pattern.
9627 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9628 isShuffleMaskInputInPlace(1, Mask))))
9629 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9630 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9633 // Otherwise fall back on generic blend lowering.
9634 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9638 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9640 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9641 /// isn't available.
9642 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9643 const X86Subtarget *Subtarget,
9644 SelectionDAG &DAG) {
9646 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9647 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9648 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9649 ArrayRef<int> Mask = SVOp->getMask();
9650 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9652 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9656 // Check for being able to broadcast a single element.
9657 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9658 Mask, Subtarget, DAG))
9661 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9662 // options to efficiently lower the shuffle.
9663 SmallVector<int, 4> RepeatedMask;
9664 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9665 assert(RepeatedMask.size() == 4 &&
9666 "Repeated masks must be half the mask width!");
9668 // Use even/odd duplicate instructions for masks that match their pattern.
9669 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9670 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9671 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9672 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9674 if (isSingleInputShuffleMask(Mask))
9675 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9676 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9678 // Use dedicated unpack instructions for masks that match their pattern.
9679 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9680 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9681 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9682 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9683 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9684 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9685 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9686 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9688 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9689 // have already handled any direct blends. We also need to squash the
9690 // repeated mask into a simulated v4f32 mask.
9691 for (int i = 0; i < 4; ++i)
9692 if (RepeatedMask[i] >= 8)
9693 RepeatedMask[i] -= 4;
9694 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9697 // If we have a single input shuffle with different shuffle patterns in the
9698 // two 128-bit lanes use the variable mask to VPERMILPS.
9699 if (isSingleInputShuffleMask(Mask)) {
9700 SDValue VPermMask[8];
9701 for (int i = 0; i < 8; ++i)
9702 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9703 : DAG.getConstant(Mask[i], DL, MVT::i32);
9704 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9706 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9707 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9709 if (Subtarget->hasAVX2())
9711 X86ISD::VPERMV, DL, MVT::v8f32,
9712 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
9713 MVT::v8i32, VPermMask)),
9716 // Otherwise, fall back.
9717 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9721 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9723 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9724 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9727 // If we have AVX2 then we always want to lower with a blend because at v8 we
9728 // can fully permute the elements.
9729 if (Subtarget->hasAVX2())
9730 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9733 // Otherwise fall back on generic lowering.
9734 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9737 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9739 /// This routine is only called when we have AVX2 and thus a reasonable
9740 /// instruction set for v8i32 shuffling..
9741 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9742 const X86Subtarget *Subtarget,
9743 SelectionDAG &DAG) {
9745 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9746 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9747 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9748 ArrayRef<int> Mask = SVOp->getMask();
9749 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9750 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9752 // Whenever we can lower this as a zext, that instruction is strictly faster
9753 // than any alternative. It also allows us to fold memory operands into the
9754 // shuffle in many cases.
9755 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9756 Mask, Subtarget, DAG))
9759 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9763 // Check for being able to broadcast a single element.
9764 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9765 Mask, Subtarget, DAG))
9768 // If the shuffle mask is repeated in each 128-bit lane we can use more
9769 // efficient instructions that mirror the shuffles across the two 128-bit
9771 SmallVector<int, 4> RepeatedMask;
9772 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9773 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9774 if (isSingleInputShuffleMask(Mask))
9775 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9776 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9778 // Use dedicated unpack instructions for masks that match their pattern.
9779 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9780 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9781 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9782 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9783 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9784 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9785 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9786 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9789 // Try to use shift instructions.
9791 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9794 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9795 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9798 // If the shuffle patterns aren't repeated but it is a single input, directly
9799 // generate a cross-lane VPERMD instruction.
9800 if (isSingleInputShuffleMask(Mask)) {
9801 SDValue VPermMask[8];
9802 for (int i = 0; i < 8; ++i)
9803 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9804 : DAG.getConstant(Mask[i], DL, MVT::i32);
9806 X86ISD::VPERMV, DL, MVT::v8i32,
9807 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9810 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9812 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9813 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9816 // Otherwise fall back on generic blend lowering.
9817 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9821 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9823 /// This routine is only called when we have AVX2 and thus a reasonable
9824 /// instruction set for v16i16 shuffling..
9825 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9826 const X86Subtarget *Subtarget,
9827 SelectionDAG &DAG) {
9829 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9830 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9831 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9832 ArrayRef<int> Mask = SVOp->getMask();
9833 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9834 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9836 // Whenever we can lower this as a zext, that instruction is strictly faster
9837 // than any alternative. It also allows us to fold memory operands into the
9838 // shuffle in many cases.
9839 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9840 Mask, Subtarget, DAG))
9843 // Check for being able to broadcast a single element.
9844 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9845 Mask, Subtarget, DAG))
9848 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9852 // Use dedicated unpack instructions for masks that match their pattern.
9853 if (isShuffleEquivalent(V1, V2, Mask,
9854 {// First 128-bit lane:
9855 0, 16, 1, 17, 2, 18, 3, 19,
9856 // Second 128-bit lane:
9857 8, 24, 9, 25, 10, 26, 11, 27}))
9858 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9859 if (isShuffleEquivalent(V1, V2, Mask,
9860 {// First 128-bit lane:
9861 4, 20, 5, 21, 6, 22, 7, 23,
9862 // Second 128-bit lane:
9863 12, 28, 13, 29, 14, 30, 15, 31}))
9864 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9866 // Try to use shift instructions.
9868 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9871 // Try to use byte rotation instructions.
9872 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9873 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9876 if (isSingleInputShuffleMask(Mask)) {
9877 // There are no generalized cross-lane shuffle operations available on i16
9879 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9880 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9883 SmallVector<int, 8> RepeatedMask;
9884 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9885 // As this is a single-input shuffle, the repeated mask should be
9886 // a strictly valid v8i16 mask that we can pass through to the v8i16
9887 // lowering to handle even the v16 case.
9888 return lowerV8I16GeneralSingleInputVectorShuffle(
9889 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9892 SDValue PSHUFBMask[32];
9893 for (int i = 0; i < 16; ++i) {
9894 if (Mask[i] == -1) {
9895 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9899 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9900 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9901 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
9902 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
9904 return DAG.getBitcast(MVT::v16i16,
9905 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
9906 DAG.getBitcast(MVT::v32i8, V1),
9907 DAG.getNode(ISD::BUILD_VECTOR, DL,
9908 MVT::v32i8, PSHUFBMask)));
9911 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9913 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9914 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9917 // Otherwise fall back on generic lowering.
9918 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9921 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9923 /// This routine is only called when we have AVX2 and thus a reasonable
9924 /// instruction set for v32i8 shuffling..
9925 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9926 const X86Subtarget *Subtarget,
9927 SelectionDAG &DAG) {
9929 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9930 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9931 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9932 ArrayRef<int> Mask = SVOp->getMask();
9933 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9934 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9936 // Whenever we can lower this as a zext, that instruction is strictly faster
9937 // than any alternative. It also allows us to fold memory operands into the
9938 // shuffle in many cases.
9939 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9940 Mask, Subtarget, DAG))
9943 // Check for being able to broadcast a single element.
9944 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9945 Mask, Subtarget, DAG))
9948 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9952 // Use dedicated unpack instructions for masks that match their pattern.
9953 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9955 if (isShuffleEquivalent(
9957 {// First 128-bit lane:
9958 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9959 // Second 128-bit lane:
9960 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9961 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9962 if (isShuffleEquivalent(
9964 {// First 128-bit lane:
9965 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9966 // Second 128-bit lane:
9967 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9968 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9970 // Try to use shift instructions.
9972 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9975 // Try to use byte rotation instructions.
9976 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9977 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9980 if (isSingleInputShuffleMask(Mask)) {
9981 // There are no generalized cross-lane shuffle operations available on i8
9983 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9984 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9987 SDValue PSHUFBMask[32];
9988 for (int i = 0; i < 32; ++i)
9991 ? DAG.getUNDEF(MVT::i8)
9992 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
9996 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9997 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10000 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10002 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10003 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10006 // Otherwise fall back on generic lowering.
10007 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10010 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10012 /// This routine either breaks down the specific type of a 256-bit x86 vector
10013 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10014 /// together based on the available instructions.
10015 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10016 MVT VT, const X86Subtarget *Subtarget,
10017 SelectionDAG &DAG) {
10019 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10020 ArrayRef<int> Mask = SVOp->getMask();
10022 // If we have a single input to the zero element, insert that into V1 if we
10023 // can do so cheaply.
10024 int NumElts = VT.getVectorNumElements();
10025 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10026 return M >= NumElts;
10029 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10030 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10031 DL, VT, V1, V2, Mask, Subtarget, DAG))
10034 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10035 // check for those subtargets here and avoid much of the subtarget querying in
10036 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10037 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10038 // floating point types there eventually, just immediately cast everything to
10039 // a float and operate entirely in that domain.
10040 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10041 int ElementBits = VT.getScalarSizeInBits();
10042 if (ElementBits < 32)
10043 // No floating point type available, decompose into 128-bit vectors.
10044 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10046 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10047 VT.getVectorNumElements());
10048 V1 = DAG.getBitcast(FpVT, V1);
10049 V2 = DAG.getBitcast(FpVT, V2);
10050 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10053 switch (VT.SimpleTy) {
10055 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10057 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10059 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10061 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10063 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10065 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10068 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10072 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10073 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10074 const X86Subtarget *Subtarget,
10075 SelectionDAG &DAG) {
10077 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10078 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10079 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10080 ArrayRef<int> Mask = SVOp->getMask();
10081 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10083 // X86 has dedicated unpack instructions that can handle specific blend
10084 // operations: UNPCKH and UNPCKL.
10085 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10086 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10087 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10088 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10090 // FIXME: Implement direct support for this type!
10091 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10094 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10095 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10096 const X86Subtarget *Subtarget,
10097 SelectionDAG &DAG) {
10099 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10100 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10101 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10102 ArrayRef<int> Mask = SVOp->getMask();
10103 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10105 // Use dedicated unpack instructions for masks that match their pattern.
10106 if (isShuffleEquivalent(V1, V2, Mask,
10107 {// First 128-bit lane.
10108 0, 16, 1, 17, 4, 20, 5, 21,
10109 // Second 128-bit lane.
10110 8, 24, 9, 25, 12, 28, 13, 29}))
10111 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10112 if (isShuffleEquivalent(V1, V2, Mask,
10113 {// First 128-bit lane.
10114 2, 18, 3, 19, 6, 22, 7, 23,
10115 // Second 128-bit lane.
10116 10, 26, 11, 27, 14, 30, 15, 31}))
10117 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10119 // FIXME: Implement direct support for this type!
10120 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10123 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10124 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10125 const X86Subtarget *Subtarget,
10126 SelectionDAG &DAG) {
10128 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10129 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10130 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10131 ArrayRef<int> Mask = SVOp->getMask();
10132 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10134 // X86 has dedicated unpack instructions that can handle specific blend
10135 // operations: UNPCKH and UNPCKL.
10136 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10137 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10138 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10139 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10141 // FIXME: Implement direct support for this type!
10142 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10145 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10146 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10147 const X86Subtarget *Subtarget,
10148 SelectionDAG &DAG) {
10150 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10151 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10152 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10153 ArrayRef<int> Mask = SVOp->getMask();
10154 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10156 // Use dedicated unpack instructions for masks that match their pattern.
10157 if (isShuffleEquivalent(V1, V2, Mask,
10158 {// First 128-bit lane.
10159 0, 16, 1, 17, 4, 20, 5, 21,
10160 // Second 128-bit lane.
10161 8, 24, 9, 25, 12, 28, 13, 29}))
10162 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10163 if (isShuffleEquivalent(V1, V2, Mask,
10164 {// First 128-bit lane.
10165 2, 18, 3, 19, 6, 22, 7, 23,
10166 // Second 128-bit lane.
10167 10, 26, 11, 27, 14, 30, 15, 31}))
10168 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10170 // FIXME: Implement direct support for this type!
10171 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10174 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10175 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10176 const X86Subtarget *Subtarget,
10177 SelectionDAG &DAG) {
10179 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10180 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10181 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10182 ArrayRef<int> Mask = SVOp->getMask();
10183 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10184 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10186 // FIXME: Implement direct support for this type!
10187 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10190 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10191 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10192 const X86Subtarget *Subtarget,
10193 SelectionDAG &DAG) {
10195 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10196 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10197 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10198 ArrayRef<int> Mask = SVOp->getMask();
10199 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10200 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10202 // FIXME: Implement direct support for this type!
10203 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10206 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10208 /// This routine either breaks down the specific type of a 512-bit x86 vector
10209 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10210 /// together based on the available instructions.
10211 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10212 MVT VT, const X86Subtarget *Subtarget,
10213 SelectionDAG &DAG) {
10215 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10216 ArrayRef<int> Mask = SVOp->getMask();
10217 assert(Subtarget->hasAVX512() &&
10218 "Cannot lower 512-bit vectors w/ basic ISA!");
10220 // Check for being able to broadcast a single element.
10221 if (SDValue Broadcast =
10222 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10225 // Dispatch to each element type for lowering. If we don't have supprot for
10226 // specific element type shuffles at 512 bits, immediately split them and
10227 // lower them. Each lowering routine of a given type is allowed to assume that
10228 // the requisite ISA extensions for that element type are available.
10229 switch (VT.SimpleTy) {
10231 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10233 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10235 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10237 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10239 if (Subtarget->hasBWI())
10240 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10243 if (Subtarget->hasBWI())
10244 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10248 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10251 // Otherwise fall back on splitting.
10252 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10255 /// \brief Top-level lowering for x86 vector shuffles.
10257 /// This handles decomposition, canonicalization, and lowering of all x86
10258 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10259 /// above in helper routines. The canonicalization attempts to widen shuffles
10260 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10261 /// s.t. only one of the two inputs needs to be tested, etc.
10262 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10263 SelectionDAG &DAG) {
10264 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10265 ArrayRef<int> Mask = SVOp->getMask();
10266 SDValue V1 = Op.getOperand(0);
10267 SDValue V2 = Op.getOperand(1);
10268 MVT VT = Op.getSimpleValueType();
10269 int NumElements = VT.getVectorNumElements();
10272 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10274 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10275 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10276 if (V1IsUndef && V2IsUndef)
10277 return DAG.getUNDEF(VT);
10279 // When we create a shuffle node we put the UNDEF node to second operand,
10280 // but in some cases the first operand may be transformed to UNDEF.
10281 // In this case we should just commute the node.
10283 return DAG.getCommutedVectorShuffle(*SVOp);
10285 // Check for non-undef masks pointing at an undef vector and make the masks
10286 // undef as well. This makes it easier to match the shuffle based solely on
10290 if (M >= NumElements) {
10291 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10292 for (int &M : NewMask)
10293 if (M >= NumElements)
10295 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10298 // We actually see shuffles that are entirely re-arrangements of a set of
10299 // zero inputs. This mostly happens while decomposing complex shuffles into
10300 // simple ones. Directly lower these as a buildvector of zeros.
10301 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10302 if (Zeroable.all())
10303 return getZeroVector(VT, Subtarget, DAG, dl);
10305 // Try to collapse shuffles into using a vector type with fewer elements but
10306 // wider element types. We cap this to not form integers or floating point
10307 // elements wider than 64 bits, but it might be interesting to form i128
10308 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10309 SmallVector<int, 16> WidenedMask;
10310 if (VT.getScalarSizeInBits() < 64 &&
10311 canWidenShuffleElements(Mask, WidenedMask)) {
10312 MVT NewEltVT = VT.isFloatingPoint()
10313 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10314 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10315 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10316 // Make sure that the new vector type is legal. For example, v2f64 isn't
10318 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10319 V1 = DAG.getBitcast(NewVT, V1);
10320 V2 = DAG.getBitcast(NewVT, V2);
10321 return DAG.getBitcast(
10322 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10326 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10327 for (int M : SVOp->getMask())
10329 ++NumUndefElements;
10330 else if (M < NumElements)
10335 // Commute the shuffle as needed such that more elements come from V1 than
10336 // V2. This allows us to match the shuffle pattern strictly on how many
10337 // elements come from V1 without handling the symmetric cases.
10338 if (NumV2Elements > NumV1Elements)
10339 return DAG.getCommutedVectorShuffle(*SVOp);
10341 // When the number of V1 and V2 elements are the same, try to minimize the
10342 // number of uses of V2 in the low half of the vector. When that is tied,
10343 // ensure that the sum of indices for V1 is equal to or lower than the sum
10344 // indices for V2. When those are equal, try to ensure that the number of odd
10345 // indices for V1 is lower than the number of odd indices for V2.
10346 if (NumV1Elements == NumV2Elements) {
10347 int LowV1Elements = 0, LowV2Elements = 0;
10348 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10349 if (M >= NumElements)
10353 if (LowV2Elements > LowV1Elements) {
10354 return DAG.getCommutedVectorShuffle(*SVOp);
10355 } else if (LowV2Elements == LowV1Elements) {
10356 int SumV1Indices = 0, SumV2Indices = 0;
10357 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10358 if (SVOp->getMask()[i] >= NumElements)
10360 else if (SVOp->getMask()[i] >= 0)
10362 if (SumV2Indices < SumV1Indices) {
10363 return DAG.getCommutedVectorShuffle(*SVOp);
10364 } else if (SumV2Indices == SumV1Indices) {
10365 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10366 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10367 if (SVOp->getMask()[i] >= NumElements)
10368 NumV2OddIndices += i % 2;
10369 else if (SVOp->getMask()[i] >= 0)
10370 NumV1OddIndices += i % 2;
10371 if (NumV2OddIndices < NumV1OddIndices)
10372 return DAG.getCommutedVectorShuffle(*SVOp);
10377 // For each vector width, delegate to a specialized lowering routine.
10378 if (VT.getSizeInBits() == 128)
10379 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10381 if (VT.getSizeInBits() == 256)
10382 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10384 // Force AVX-512 vectors to be scalarized for now.
10385 // FIXME: Implement AVX-512 support!
10386 if (VT.getSizeInBits() == 512)
10387 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10389 llvm_unreachable("Unimplemented!");
10392 // This function assumes its argument is a BUILD_VECTOR of constants or
10393 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10395 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10396 unsigned &MaskValue) {
10398 unsigned NumElems = BuildVector->getNumOperands();
10399 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10400 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10401 unsigned NumElemsInLane = NumElems / NumLanes;
10403 // Blend for v16i16 should be symetric for the both lanes.
10404 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10405 SDValue EltCond = BuildVector->getOperand(i);
10406 SDValue SndLaneEltCond =
10407 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10409 int Lane1Cond = -1, Lane2Cond = -1;
10410 if (isa<ConstantSDNode>(EltCond))
10411 Lane1Cond = !isZero(EltCond);
10412 if (isa<ConstantSDNode>(SndLaneEltCond))
10413 Lane2Cond = !isZero(SndLaneEltCond);
10415 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10416 // Lane1Cond != 0, means we want the first argument.
10417 // Lane1Cond == 0, means we want the second argument.
10418 // The encoding of this argument is 0 for the first argument, 1
10419 // for the second. Therefore, invert the condition.
10420 MaskValue |= !Lane1Cond << i;
10421 else if (Lane1Cond < 0)
10422 MaskValue |= !Lane2Cond << i;
10429 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10430 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10431 const X86Subtarget *Subtarget,
10432 SelectionDAG &DAG) {
10433 SDValue Cond = Op.getOperand(0);
10434 SDValue LHS = Op.getOperand(1);
10435 SDValue RHS = Op.getOperand(2);
10437 MVT VT = Op.getSimpleValueType();
10439 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10441 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10443 // Only non-legal VSELECTs reach this lowering, convert those into generic
10444 // shuffles and re-use the shuffle lowering path for blends.
10445 SmallVector<int, 32> Mask;
10446 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10447 SDValue CondElt = CondBV->getOperand(i);
10449 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10451 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10454 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10455 // A vselect where all conditions and data are constants can be optimized into
10456 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10457 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10458 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10459 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10462 // Try to lower this to a blend-style vector shuffle. This can handle all
10463 // constant condition cases.
10464 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10467 // Variable blends are only legal from SSE4.1 onward.
10468 if (!Subtarget->hasSSE41())
10471 // Only some types will be legal on some subtargets. If we can emit a legal
10472 // VSELECT-matching blend, return Op, and but if we need to expand, return
10474 switch (Op.getSimpleValueType().SimpleTy) {
10476 // Most of the vector types have blends past SSE4.1.
10480 // The byte blends for AVX vectors were introduced only in AVX2.
10481 if (Subtarget->hasAVX2())
10488 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10489 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10492 // FIXME: We should custom lower this by fixing the condition and using i8
10498 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10499 MVT VT = Op.getSimpleValueType();
10502 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10505 if (VT.getSizeInBits() == 8) {
10506 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10507 Op.getOperand(0), Op.getOperand(1));
10508 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10509 DAG.getValueType(VT));
10510 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10513 if (VT.getSizeInBits() == 16) {
10514 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10515 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10517 return DAG.getNode(
10518 ISD::TRUNCATE, dl, MVT::i16,
10519 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10520 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10521 Op.getOperand(1)));
10522 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10523 Op.getOperand(0), Op.getOperand(1));
10524 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10525 DAG.getValueType(VT));
10526 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10529 if (VT == MVT::f32) {
10530 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10531 // the result back to FR32 register. It's only worth matching if the
10532 // result has a single use which is a store or a bitcast to i32. And in
10533 // the case of a store, it's not worth it if the index is a constant 0,
10534 // because a MOVSSmr can be used instead, which is smaller and faster.
10535 if (!Op.hasOneUse())
10537 SDNode *User = *Op.getNode()->use_begin();
10538 if ((User->getOpcode() != ISD::STORE ||
10539 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10540 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10541 (User->getOpcode() != ISD::BITCAST ||
10542 User->getValueType(0) != MVT::i32))
10544 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10545 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10547 return DAG.getBitcast(MVT::f32, Extract);
10550 if (VT == MVT::i32 || VT == MVT::i64) {
10551 // ExtractPS/pextrq works with constant index.
10552 if (isa<ConstantSDNode>(Op.getOperand(1)))
10558 /// Extract one bit from mask vector, like v16i1 or v8i1.
10559 /// AVX-512 feature.
10561 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10562 SDValue Vec = Op.getOperand(0);
10564 MVT VecVT = Vec.getSimpleValueType();
10565 SDValue Idx = Op.getOperand(1);
10566 MVT EltVT = Op.getSimpleValueType();
10568 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10569 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10570 "Unexpected vector type in ExtractBitFromMaskVector");
10572 // variable index can't be handled in mask registers,
10573 // extend vector to VR512
10574 if (!isa<ConstantSDNode>(Idx)) {
10575 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10576 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10577 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10578 ExtVT.getVectorElementType(), Ext, Idx);
10579 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10582 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10583 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10584 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10585 rc = getRegClassFor(MVT::v16i1);
10586 unsigned MaxSift = rc->getSize()*8 - 1;
10587 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10588 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10589 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10590 DAG.getConstant(MaxSift, dl, MVT::i8));
10591 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10592 DAG.getIntPtrConstant(0, dl));
10596 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10597 SelectionDAG &DAG) const {
10599 SDValue Vec = Op.getOperand(0);
10600 MVT VecVT = Vec.getSimpleValueType();
10601 SDValue Idx = Op.getOperand(1);
10603 if (Op.getSimpleValueType() == MVT::i1)
10604 return ExtractBitFromMaskVector(Op, DAG);
10606 if (!isa<ConstantSDNode>(Idx)) {
10607 if (VecVT.is512BitVector() ||
10608 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10609 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10612 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10613 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10614 MaskEltVT.getSizeInBits());
10616 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10617 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10618 getZeroVector(MaskVT, Subtarget, DAG, dl),
10619 Idx, DAG.getConstant(0, dl, getPointerTy()));
10620 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10621 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10622 Perm, DAG.getConstant(0, dl, getPointerTy()));
10627 // If this is a 256-bit vector result, first extract the 128-bit vector and
10628 // then extract the element from the 128-bit vector.
10629 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10631 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10632 // Get the 128-bit vector.
10633 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10634 MVT EltVT = VecVT.getVectorElementType();
10636 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10638 //if (IdxVal >= NumElems/2)
10639 // IdxVal -= NumElems/2;
10640 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10641 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10642 DAG.getConstant(IdxVal, dl, MVT::i32));
10645 assert(VecVT.is128BitVector() && "Unexpected vector length");
10647 if (Subtarget->hasSSE41())
10648 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
10651 MVT VT = Op.getSimpleValueType();
10652 // TODO: handle v16i8.
10653 if (VT.getSizeInBits() == 16) {
10654 SDValue Vec = Op.getOperand(0);
10655 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10657 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10658 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10659 DAG.getBitcast(MVT::v4i32, Vec),
10660 Op.getOperand(1)));
10661 // Transform it so it match pextrw which produces a 32-bit result.
10662 MVT EltVT = MVT::i32;
10663 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10664 Op.getOperand(0), Op.getOperand(1));
10665 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10666 DAG.getValueType(VT));
10667 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10670 if (VT.getSizeInBits() == 32) {
10671 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10675 // SHUFPS the element to the lowest double word, then movss.
10676 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10677 MVT VVT = Op.getOperand(0).getSimpleValueType();
10678 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10679 DAG.getUNDEF(VVT), Mask);
10680 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10681 DAG.getIntPtrConstant(0, dl));
10684 if (VT.getSizeInBits() == 64) {
10685 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10686 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10687 // to match extract_elt for f64.
10688 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10692 // UNPCKHPD the element to the lowest double word, then movsd.
10693 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10694 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10695 int Mask[2] = { 1, -1 };
10696 MVT VVT = Op.getOperand(0).getSimpleValueType();
10697 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10698 DAG.getUNDEF(VVT), Mask);
10699 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10700 DAG.getIntPtrConstant(0, dl));
10706 /// Insert one bit to mask vector, like v16i1 or v8i1.
10707 /// AVX-512 feature.
10709 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10711 SDValue Vec = Op.getOperand(0);
10712 SDValue Elt = Op.getOperand(1);
10713 SDValue Idx = Op.getOperand(2);
10714 MVT VecVT = Vec.getSimpleValueType();
10716 if (!isa<ConstantSDNode>(Idx)) {
10717 // Non constant index. Extend source and destination,
10718 // insert element and then truncate the result.
10719 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10720 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10721 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10722 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10723 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10724 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10727 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10728 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10730 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10731 DAG.getConstant(IdxVal, dl, MVT::i8));
10732 if (Vec.getOpcode() == ISD::UNDEF)
10734 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10737 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10738 SelectionDAG &DAG) const {
10739 MVT VT = Op.getSimpleValueType();
10740 MVT EltVT = VT.getVectorElementType();
10742 if (EltVT == MVT::i1)
10743 return InsertBitToMaskVector(Op, DAG);
10746 SDValue N0 = Op.getOperand(0);
10747 SDValue N1 = Op.getOperand(1);
10748 SDValue N2 = Op.getOperand(2);
10749 if (!isa<ConstantSDNode>(N2))
10751 auto *N2C = cast<ConstantSDNode>(N2);
10752 unsigned IdxVal = N2C->getZExtValue();
10754 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10755 // into that, and then insert the subvector back into the result.
10756 if (VT.is256BitVector() || VT.is512BitVector()) {
10757 // With a 256-bit vector, we can insert into the zero element efficiently
10758 // using a blend if we have AVX or AVX2 and the right data type.
10759 if (VT.is256BitVector() && IdxVal == 0) {
10760 // TODO: It is worthwhile to cast integer to floating point and back
10761 // and incur a domain crossing penalty if that's what we'll end up
10762 // doing anyway after extracting to a 128-bit vector.
10763 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10764 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10765 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10766 N2 = DAG.getIntPtrConstant(1, dl);
10767 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10771 // Get the desired 128-bit vector chunk.
10772 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10774 // Insert the element into the desired chunk.
10775 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10776 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10778 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10779 DAG.getConstant(IdxIn128, dl, MVT::i32));
10781 // Insert the changed part back into the bigger vector
10782 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10784 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10786 if (Subtarget->hasSSE41()) {
10787 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10789 if (VT == MVT::v8i16) {
10790 Opc = X86ISD::PINSRW;
10792 assert(VT == MVT::v16i8);
10793 Opc = X86ISD::PINSRB;
10796 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10798 if (N1.getValueType() != MVT::i32)
10799 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10800 if (N2.getValueType() != MVT::i32)
10801 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10802 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10805 if (EltVT == MVT::f32) {
10806 // Bits [7:6] of the constant are the source select. This will always be
10807 // zero here. The DAG Combiner may combine an extract_elt index into
10808 // these bits. For example (insert (extract, 3), 2) could be matched by
10809 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10810 // Bits [5:4] of the constant are the destination select. This is the
10811 // value of the incoming immediate.
10812 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10813 // combine either bitwise AND or insert of float 0.0 to set these bits.
10815 const Function *F = DAG.getMachineFunction().getFunction();
10816 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10817 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10818 // If this is an insertion of 32-bits into the low 32-bits of
10819 // a vector, we prefer to generate a blend with immediate rather
10820 // than an insertps. Blends are simpler operations in hardware and so
10821 // will always have equal or better performance than insertps.
10822 // But if optimizing for size and there's a load folding opportunity,
10823 // generate insertps because blendps does not have a 32-bit memory
10825 N2 = DAG.getIntPtrConstant(1, dl);
10826 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10827 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10829 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
10830 // Create this as a scalar to vector..
10831 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10832 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10835 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10836 // PINSR* works with constant index.
10841 if (EltVT == MVT::i8)
10844 if (EltVT.getSizeInBits() == 16) {
10845 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10846 // as its second argument.
10847 if (N1.getValueType() != MVT::i32)
10848 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10849 if (N2.getValueType() != MVT::i32)
10850 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10851 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10856 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10858 MVT OpVT = Op.getSimpleValueType();
10860 // If this is a 256-bit vector result, first insert into a 128-bit
10861 // vector and then insert into the 256-bit vector.
10862 if (!OpVT.is128BitVector()) {
10863 // Insert into a 128-bit vector.
10864 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10865 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10866 OpVT.getVectorNumElements() / SizeFactor);
10868 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10870 // Insert the 128-bit vector.
10871 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10874 if (OpVT == MVT::v1i64 &&
10875 Op.getOperand(0).getValueType() == MVT::i64)
10876 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10878 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10879 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10880 return DAG.getBitcast(
10881 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
10884 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10885 // a simple subregister reference or explicit instructions to grab
10886 // upper bits of a vector.
10887 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10888 SelectionDAG &DAG) {
10890 SDValue In = Op.getOperand(0);
10891 SDValue Idx = Op.getOperand(1);
10892 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10893 MVT ResVT = Op.getSimpleValueType();
10894 MVT InVT = In.getSimpleValueType();
10896 if (Subtarget->hasFp256()) {
10897 if (ResVT.is128BitVector() &&
10898 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10899 isa<ConstantSDNode>(Idx)) {
10900 return Extract128BitVector(In, IdxVal, DAG, dl);
10902 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10903 isa<ConstantSDNode>(Idx)) {
10904 return Extract256BitVector(In, IdxVal, DAG, dl);
10910 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10911 // simple superregister reference or explicit instructions to insert
10912 // the upper bits of a vector.
10913 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10914 SelectionDAG &DAG) {
10915 if (!Subtarget->hasAVX())
10919 SDValue Vec = Op.getOperand(0);
10920 SDValue SubVec = Op.getOperand(1);
10921 SDValue Idx = Op.getOperand(2);
10923 if (!isa<ConstantSDNode>(Idx))
10926 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10927 MVT OpVT = Op.getSimpleValueType();
10928 MVT SubVecVT = SubVec.getSimpleValueType();
10930 // Fold two 16-byte subvector loads into one 32-byte load:
10931 // (insert_subvector (insert_subvector undef, (load addr), 0),
10932 // (load addr + 16), Elts/2)
10934 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10935 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10936 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10937 !Subtarget->isUnalignedMem32Slow()) {
10938 SDValue SubVec2 = Vec.getOperand(1);
10939 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10940 if (Idx2->getZExtValue() == 0) {
10941 SDValue Ops[] = { SubVec2, SubVec };
10942 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
10948 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10949 SubVecVT.is128BitVector())
10950 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10952 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10953 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10955 if (OpVT.getVectorElementType() == MVT::i1) {
10956 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
10958 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
10959 SDValue Undef = DAG.getUNDEF(OpVT);
10960 unsigned NumElems = OpVT.getVectorNumElements();
10961 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
10963 if (IdxVal == OpVT.getVectorNumElements() / 2) {
10964 // Zero upper bits of the Vec
10965 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10966 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10968 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10970 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10971 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10974 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10976 // Zero upper bits of the Vec2
10977 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10978 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
10979 // Zero lower bits of the Vec
10980 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10981 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10982 // Merge them together
10983 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10989 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10990 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10991 // one of the above mentioned nodes. It has to be wrapped because otherwise
10992 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10993 // be used to form addressing mode. These wrapped nodes will be selected
10996 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10997 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10999 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11000 // global base reg.
11001 unsigned char OpFlag = 0;
11002 unsigned WrapperKind = X86ISD::Wrapper;
11003 CodeModel::Model M = DAG.getTarget().getCodeModel();
11005 if (Subtarget->isPICStyleRIPRel() &&
11006 (M == CodeModel::Small || M == CodeModel::Kernel))
11007 WrapperKind = X86ISD::WrapperRIP;
11008 else if (Subtarget->isPICStyleGOT())
11009 OpFlag = X86II::MO_GOTOFF;
11010 else if (Subtarget->isPICStyleStubPIC())
11011 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11013 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11014 CP->getAlignment(),
11015 CP->getOffset(), OpFlag);
11017 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11018 // With PIC, the address is actually $g + Offset.
11020 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11021 DAG.getNode(X86ISD::GlobalBaseReg,
11022 SDLoc(), getPointerTy()),
11029 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11030 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11032 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11033 // global base reg.
11034 unsigned char OpFlag = 0;
11035 unsigned WrapperKind = X86ISD::Wrapper;
11036 CodeModel::Model M = DAG.getTarget().getCodeModel();
11038 if (Subtarget->isPICStyleRIPRel() &&
11039 (M == CodeModel::Small || M == CodeModel::Kernel))
11040 WrapperKind = X86ISD::WrapperRIP;
11041 else if (Subtarget->isPICStyleGOT())
11042 OpFlag = X86II::MO_GOTOFF;
11043 else if (Subtarget->isPICStyleStubPIC())
11044 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11046 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11049 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11051 // With PIC, the address is actually $g + Offset.
11053 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11054 DAG.getNode(X86ISD::GlobalBaseReg,
11055 SDLoc(), getPointerTy()),
11062 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11063 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11065 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11066 // global base reg.
11067 unsigned char OpFlag = 0;
11068 unsigned WrapperKind = X86ISD::Wrapper;
11069 CodeModel::Model M = DAG.getTarget().getCodeModel();
11071 if (Subtarget->isPICStyleRIPRel() &&
11072 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11073 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11074 OpFlag = X86II::MO_GOTPCREL;
11075 WrapperKind = X86ISD::WrapperRIP;
11076 } else if (Subtarget->isPICStyleGOT()) {
11077 OpFlag = X86II::MO_GOT;
11078 } else if (Subtarget->isPICStyleStubPIC()) {
11079 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11080 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11081 OpFlag = X86II::MO_DARWIN_NONLAZY;
11084 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11087 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11089 // With PIC, the address is actually $g + Offset.
11090 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11091 !Subtarget->is64Bit()) {
11092 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11093 DAG.getNode(X86ISD::GlobalBaseReg,
11094 SDLoc(), getPointerTy()),
11098 // For symbols that require a load from a stub to get the address, emit the
11100 if (isGlobalStubReference(OpFlag))
11101 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11102 MachinePointerInfo::getGOT(), false, false, false, 0);
11108 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11109 // Create the TargetBlockAddressAddress node.
11110 unsigned char OpFlags =
11111 Subtarget->ClassifyBlockAddressReference();
11112 CodeModel::Model M = DAG.getTarget().getCodeModel();
11113 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11114 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11116 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11119 if (Subtarget->isPICStyleRIPRel() &&
11120 (M == CodeModel::Small || M == CodeModel::Kernel))
11121 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11123 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11125 // With PIC, the address is actually $g + Offset.
11126 if (isGlobalRelativeToPICBase(OpFlags)) {
11127 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11128 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11136 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11137 int64_t Offset, SelectionDAG &DAG) const {
11138 // Create the TargetGlobalAddress node, folding in the constant
11139 // offset if it is legal.
11140 unsigned char OpFlags =
11141 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11142 CodeModel::Model M = DAG.getTarget().getCodeModel();
11144 if (OpFlags == X86II::MO_NO_FLAG &&
11145 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11146 // A direct static reference to a global.
11147 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11150 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11153 if (Subtarget->isPICStyleRIPRel() &&
11154 (M == CodeModel::Small || M == CodeModel::Kernel))
11155 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11157 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11159 // With PIC, the address is actually $g + Offset.
11160 if (isGlobalRelativeToPICBase(OpFlags)) {
11161 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11162 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11166 // For globals that require a load from a stub to get the address, emit the
11168 if (isGlobalStubReference(OpFlags))
11169 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11170 MachinePointerInfo::getGOT(), false, false, false, 0);
11172 // If there was a non-zero offset that we didn't fold, create an explicit
11173 // addition for it.
11175 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11176 DAG.getConstant(Offset, dl, getPointerTy()));
11182 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11183 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11184 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11185 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11189 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11190 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11191 unsigned char OperandFlags, bool LocalDynamic = false) {
11192 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11193 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11195 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11196 GA->getValueType(0),
11200 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11204 SDValue Ops[] = { Chain, TGA, *InFlag };
11205 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11207 SDValue Ops[] = { Chain, TGA };
11208 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11211 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11212 MFI->setAdjustsStack(true);
11213 MFI->setHasCalls(true);
11215 SDValue Flag = Chain.getValue(1);
11216 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11219 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11221 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11224 SDLoc dl(GA); // ? function entry point might be better
11225 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11226 DAG.getNode(X86ISD::GlobalBaseReg,
11227 SDLoc(), PtrVT), InFlag);
11228 InFlag = Chain.getValue(1);
11230 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11233 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11235 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11237 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11238 X86::RAX, X86II::MO_TLSGD);
11241 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11247 // Get the start address of the TLS block for this module.
11248 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11249 .getInfo<X86MachineFunctionInfo>();
11250 MFI->incNumLocalDynamicTLSAccesses();
11254 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11255 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11258 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11259 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11260 InFlag = Chain.getValue(1);
11261 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11262 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11265 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11269 unsigned char OperandFlags = X86II::MO_DTPOFF;
11270 unsigned WrapperKind = X86ISD::Wrapper;
11271 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11272 GA->getValueType(0),
11273 GA->getOffset(), OperandFlags);
11274 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11276 // Add x@dtpoff with the base.
11277 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11280 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11281 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11282 const EVT PtrVT, TLSModel::Model model,
11283 bool is64Bit, bool isPIC) {
11286 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11287 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11288 is64Bit ? 257 : 256));
11290 SDValue ThreadPointer =
11291 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11292 MachinePointerInfo(Ptr), false, false, false, 0);
11294 unsigned char OperandFlags = 0;
11295 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11297 unsigned WrapperKind = X86ISD::Wrapper;
11298 if (model == TLSModel::LocalExec) {
11299 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11300 } else if (model == TLSModel::InitialExec) {
11302 OperandFlags = X86II::MO_GOTTPOFF;
11303 WrapperKind = X86ISD::WrapperRIP;
11305 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11308 llvm_unreachable("Unexpected model");
11311 // emit "addl x@ntpoff,%eax" (local exec)
11312 // or "addl x@indntpoff,%eax" (initial exec)
11313 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11315 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11316 GA->getOffset(), OperandFlags);
11317 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11319 if (model == TLSModel::InitialExec) {
11320 if (isPIC && !is64Bit) {
11321 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11322 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11326 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11327 MachinePointerInfo::getGOT(), false, false, false, 0);
11330 // The address of the thread local variable is the add of the thread
11331 // pointer with the offset of the variable.
11332 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11336 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11338 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11339 const GlobalValue *GV = GA->getGlobal();
11341 if (Subtarget->isTargetELF()) {
11342 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11344 case TLSModel::GeneralDynamic:
11345 if (Subtarget->is64Bit())
11346 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11347 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11348 case TLSModel::LocalDynamic:
11349 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11350 Subtarget->is64Bit());
11351 case TLSModel::InitialExec:
11352 case TLSModel::LocalExec:
11353 return LowerToTLSExecModel(
11354 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11355 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11357 llvm_unreachable("Unknown TLS model.");
11360 if (Subtarget->isTargetDarwin()) {
11361 // Darwin only has one model of TLS. Lower to that.
11362 unsigned char OpFlag = 0;
11363 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11364 X86ISD::WrapperRIP : X86ISD::Wrapper;
11366 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11367 // global base reg.
11368 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11369 !Subtarget->is64Bit();
11371 OpFlag = X86II::MO_TLVP_PIC_BASE;
11373 OpFlag = X86II::MO_TLVP;
11375 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11376 GA->getValueType(0),
11377 GA->getOffset(), OpFlag);
11378 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11380 // With PIC32, the address is actually $g + Offset.
11382 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11383 DAG.getNode(X86ISD::GlobalBaseReg,
11384 SDLoc(), getPointerTy()),
11387 // Lowering the machine isd will make sure everything is in the right
11389 SDValue Chain = DAG.getEntryNode();
11390 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11391 SDValue Args[] = { Chain, Offset };
11392 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11394 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11395 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11396 MFI->setAdjustsStack(true);
11398 // And our return value (tls address) is in the standard call return value
11400 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11401 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11402 Chain.getValue(1));
11405 if (Subtarget->isTargetKnownWindowsMSVC() ||
11406 Subtarget->isTargetWindowsGNU()) {
11407 // Just use the implicit TLS architecture
11408 // Need to generate someting similar to:
11409 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11411 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11412 // mov rcx, qword [rdx+rcx*8]
11413 // mov eax, .tls$:tlsvar
11414 // [rax+rcx] contains the address
11415 // Windows 64bit: gs:0x58
11416 // Windows 32bit: fs:__tls_array
11419 SDValue Chain = DAG.getEntryNode();
11421 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11422 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11423 // use its literal value of 0x2C.
11424 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11425 ? Type::getInt8PtrTy(*DAG.getContext(),
11427 : Type::getInt32PtrTy(*DAG.getContext(),
11431 Subtarget->is64Bit()
11432 ? DAG.getIntPtrConstant(0x58, dl)
11433 : (Subtarget->isTargetWindowsGNU()
11434 ? DAG.getIntPtrConstant(0x2C, dl)
11435 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11437 SDValue ThreadPointer =
11438 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11439 MachinePointerInfo(Ptr), false, false, false, 0);
11442 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11443 res = ThreadPointer;
11445 // Load the _tls_index variable
11446 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11447 if (Subtarget->is64Bit())
11448 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, IDX,
11449 MachinePointerInfo(), MVT::i32, false, false,
11452 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11453 false, false, false, 0);
11455 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11457 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11459 res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11462 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11463 false, false, false, 0);
11465 // Get the offset of start of .tls section
11466 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11467 GA->getValueType(0),
11468 GA->getOffset(), X86II::MO_SECREL);
11469 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11471 // The address of the thread local variable is the add of the thread
11472 // pointer with the offset of the variable.
11473 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11476 llvm_unreachable("TLS not implemented for this target.");
11479 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11480 /// and take a 2 x i32 value to shift plus a shift amount.
11481 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11482 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11483 MVT VT = Op.getSimpleValueType();
11484 unsigned VTBits = VT.getSizeInBits();
11486 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11487 SDValue ShOpLo = Op.getOperand(0);
11488 SDValue ShOpHi = Op.getOperand(1);
11489 SDValue ShAmt = Op.getOperand(2);
11490 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11491 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11493 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11494 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11495 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11496 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11497 : DAG.getConstant(0, dl, VT);
11499 SDValue Tmp2, Tmp3;
11500 if (Op.getOpcode() == ISD::SHL_PARTS) {
11501 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11502 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11504 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11505 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11508 // If the shift amount is larger or equal than the width of a part we can't
11509 // rely on the results of shld/shrd. Insert a test and select the appropriate
11510 // values for large shift amounts.
11511 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11512 DAG.getConstant(VTBits, dl, MVT::i8));
11513 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11514 AndNode, DAG.getConstant(0, dl, MVT::i8));
11517 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11518 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11519 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11521 if (Op.getOpcode() == ISD::SHL_PARTS) {
11522 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11523 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11525 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11526 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11529 SDValue Ops[2] = { Lo, Hi };
11530 return DAG.getMergeValues(Ops, dl);
11533 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11534 SelectionDAG &DAG) const {
11535 SDValue Src = Op.getOperand(0);
11536 MVT SrcVT = Src.getSimpleValueType();
11537 MVT VT = Op.getSimpleValueType();
11540 if (SrcVT.isVector()) {
11541 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
11542 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
11543 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
11544 DAG.getUNDEF(SrcVT)));
11546 if (SrcVT.getVectorElementType() == MVT::i1) {
11547 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11548 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11549 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
11554 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11555 "Unknown SINT_TO_FP to lower!");
11557 // These are really Legal; return the operand so the caller accepts it as
11559 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11561 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11562 Subtarget->is64Bit()) {
11566 unsigned Size = SrcVT.getSizeInBits()/8;
11567 MachineFunction &MF = DAG.getMachineFunction();
11568 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11569 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11570 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11572 MachinePointerInfo::getFixedStack(SSFI),
11574 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11577 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11579 SelectionDAG &DAG) const {
11583 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11585 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11587 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11589 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11591 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11592 MachineMemOperand *MMO;
11594 int SSFI = FI->getIndex();
11596 DAG.getMachineFunction()
11597 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11598 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11600 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11601 StackSlot = StackSlot.getOperand(1);
11603 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11604 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11606 Tys, Ops, SrcVT, MMO);
11609 Chain = Result.getValue(1);
11610 SDValue InFlag = Result.getValue(2);
11612 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11613 // shouldn't be necessary except that RFP cannot be live across
11614 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11615 MachineFunction &MF = DAG.getMachineFunction();
11616 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11617 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11618 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11619 Tys = DAG.getVTList(MVT::Other);
11621 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11623 MachineMemOperand *MMO =
11624 DAG.getMachineFunction()
11625 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11626 MachineMemOperand::MOStore, SSFISize, SSFISize);
11628 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11629 Ops, Op.getValueType(), MMO);
11630 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11631 MachinePointerInfo::getFixedStack(SSFI),
11632 false, false, false, 0);
11638 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11639 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11640 SelectionDAG &DAG) const {
11641 // This algorithm is not obvious. Here it is what we're trying to output:
11644 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11645 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11647 haddpd %xmm0, %xmm0
11649 pshufd $0x4e, %xmm0, %xmm1
11655 LLVMContext *Context = DAG.getContext();
11657 // Build some magic constants.
11658 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11659 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11660 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11662 SmallVector<Constant*,2> CV1;
11664 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11665 APInt(64, 0x4330000000000000ULL))));
11667 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11668 APInt(64, 0x4530000000000000ULL))));
11669 Constant *C1 = ConstantVector::get(CV1);
11670 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11672 // Load the 64-bit value into an XMM register.
11673 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11675 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11676 MachinePointerInfo::getConstantPool(),
11677 false, false, false, 16);
11679 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
11681 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11682 MachinePointerInfo::getConstantPool(),
11683 false, false, false, 16);
11684 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
11685 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11688 if (Subtarget->hasSSE3()) {
11689 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11690 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11692 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
11693 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11695 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11696 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
11699 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11700 DAG.getIntPtrConstant(0, dl));
11703 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11704 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11705 SelectionDAG &DAG) const {
11707 // FP constant to bias correct the final result.
11708 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11711 // Load the 32-bit value into an XMM register.
11712 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11715 // Zero out the upper parts of the register.
11716 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11718 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11719 DAG.getBitcast(MVT::v2f64, Load),
11720 DAG.getIntPtrConstant(0, dl));
11722 // Or the load with the bias.
11723 SDValue Or = DAG.getNode(
11724 ISD::OR, dl, MVT::v2i64,
11725 DAG.getBitcast(MVT::v2i64,
11726 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
11727 DAG.getBitcast(MVT::v2i64,
11728 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
11730 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11731 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
11733 // Subtract the bias.
11734 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11736 // Handle final rounding.
11737 EVT DestVT = Op.getValueType();
11739 if (DestVT.bitsLT(MVT::f64))
11740 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11741 DAG.getIntPtrConstant(0, dl));
11742 if (DestVT.bitsGT(MVT::f64))
11743 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11745 // Handle final rounding.
11749 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11750 const X86Subtarget &Subtarget) {
11751 // The algorithm is the following:
11752 // #ifdef __SSE4_1__
11753 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11754 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11755 // (uint4) 0x53000000, 0xaa);
11757 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11758 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11760 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11761 // return (float4) lo + fhi;
11764 SDValue V = Op->getOperand(0);
11765 EVT VecIntVT = V.getValueType();
11766 bool Is128 = VecIntVT == MVT::v4i32;
11767 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11768 // If we convert to something else than the supported type, e.g., to v4f64,
11770 if (VecFloatVT != Op->getValueType(0))
11773 unsigned NumElts = VecIntVT.getVectorNumElements();
11774 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11775 "Unsupported custom type");
11776 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11778 // In the #idef/#else code, we have in common:
11779 // - The vector of constants:
11785 // Create the splat vector for 0x4b000000.
11786 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
11787 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11788 CstLow, CstLow, CstLow, CstLow};
11789 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11790 makeArrayRef(&CstLowArray[0], NumElts));
11791 // Create the splat vector for 0x53000000.
11792 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
11793 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11794 CstHigh, CstHigh, CstHigh, CstHigh};
11795 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11796 makeArrayRef(&CstHighArray[0], NumElts));
11798 // Create the right shift.
11799 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
11800 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11801 CstShift, CstShift, CstShift, CstShift};
11802 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11803 makeArrayRef(&CstShiftArray[0], NumElts));
11804 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11807 if (Subtarget.hasSSE41()) {
11808 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11809 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11810 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
11811 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
11812 // Low will be bitcasted right away, so do not bother bitcasting back to its
11814 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11815 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11816 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11817 // (uint4) 0x53000000, 0xaa);
11818 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
11819 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
11820 // High will be bitcasted right away, so do not bother bitcasting back to
11821 // its original type.
11822 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11823 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11825 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
11826 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11827 CstMask, CstMask, CstMask);
11828 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11829 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11830 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11832 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11833 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11836 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11837 SDValue CstFAdd = DAG.getConstantFP(
11838 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
11839 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11840 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11841 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11842 makeArrayRef(&CstFAddArray[0], NumElts));
11844 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11845 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
11847 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11848 // return (float4) lo + fhi;
11849 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
11850 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11853 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11854 SelectionDAG &DAG) const {
11855 SDValue N0 = Op.getOperand(0);
11856 MVT SVT = N0.getSimpleValueType();
11859 switch (SVT.SimpleTy) {
11861 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11866 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11867 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11868 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11872 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11875 if (Subtarget->hasAVX512())
11876 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
11877 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
11879 llvm_unreachable(nullptr);
11882 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11883 SelectionDAG &DAG) const {
11884 SDValue N0 = Op.getOperand(0);
11887 if (Op.getValueType().isVector())
11888 return lowerUINT_TO_FP_vec(Op, DAG);
11890 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11891 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11892 // the optimization here.
11893 if (DAG.SignBitIsZero(N0))
11894 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11896 MVT SrcVT = N0.getSimpleValueType();
11897 MVT DstVT = Op.getSimpleValueType();
11898 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11899 return LowerUINT_TO_FP_i64(Op, DAG);
11900 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11901 return LowerUINT_TO_FP_i32(Op, DAG);
11902 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11905 // Make a 64-bit buffer, and use it to build an FILD.
11906 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11907 if (SrcVT == MVT::i32) {
11908 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
11909 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11910 getPointerTy(), StackSlot, WordOff);
11911 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11912 StackSlot, MachinePointerInfo(),
11914 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
11915 OffsetSlot, MachinePointerInfo(),
11917 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11921 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11922 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11923 StackSlot, MachinePointerInfo(),
11925 // For i64 source, we need to add the appropriate power of 2 if the input
11926 // was negative. This is the same as the optimization in
11927 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11928 // we must be careful to do the computation in x87 extended precision, not
11929 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11930 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11931 MachineMemOperand *MMO =
11932 DAG.getMachineFunction()
11933 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11934 MachineMemOperand::MOLoad, 8, 8);
11936 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11937 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11938 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11941 APInt FF(32, 0x5F800000ULL);
11943 // Check whether the sign bit is set.
11944 SDValue SignSet = DAG.getSetCC(dl,
11945 getSetCCResultType(*DAG.getContext(), MVT::i64),
11947 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
11949 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11950 SDValue FudgePtr = DAG.getConstantPool(
11951 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11954 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11955 SDValue Zero = DAG.getIntPtrConstant(0, dl);
11956 SDValue Four = DAG.getIntPtrConstant(4, dl);
11957 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11959 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11961 // Load the value out, extending it from f32 to f80.
11962 // FIXME: Avoid the extend by constructing the right constant pool?
11963 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11964 FudgePtr, MachinePointerInfo::getConstantPool(),
11965 MVT::f32, false, false, false, 4);
11966 // Extend everything to 80 bits to force it to be done on x87.
11967 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11968 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
11969 DAG.getIntPtrConstant(0, dl));
11972 std::pair<SDValue,SDValue>
11973 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11974 bool IsSigned, bool IsReplace) const {
11977 EVT DstTy = Op.getValueType();
11979 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11980 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11984 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11985 DstTy.getSimpleVT() >= MVT::i16 &&
11986 "Unknown FP_TO_INT to lower!");
11988 // These are really Legal.
11989 if (DstTy == MVT::i32 &&
11990 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11991 return std::make_pair(SDValue(), SDValue());
11992 if (Subtarget->is64Bit() &&
11993 DstTy == MVT::i64 &&
11994 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11995 return std::make_pair(SDValue(), SDValue());
11997 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11998 // stack slot, or into the FTOL runtime function.
11999 MachineFunction &MF = DAG.getMachineFunction();
12000 unsigned MemSize = DstTy.getSizeInBits()/8;
12001 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12002 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12005 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12006 Opc = X86ISD::WIN_FTOL;
12008 switch (DstTy.getSimpleVT().SimpleTy) {
12009 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12010 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12011 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12012 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12015 SDValue Chain = DAG.getEntryNode();
12016 SDValue Value = Op.getOperand(0);
12017 EVT TheVT = Op.getOperand(0).getValueType();
12018 // FIXME This causes a redundant load/store if the SSE-class value is already
12019 // in memory, such as if it is on the callstack.
12020 if (isScalarFPTypeInSSEReg(TheVT)) {
12021 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12022 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12023 MachinePointerInfo::getFixedStack(SSFI),
12025 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12027 Chain, StackSlot, DAG.getValueType(TheVT)
12030 MachineMemOperand *MMO =
12031 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12032 MachineMemOperand::MOLoad, MemSize, MemSize);
12033 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12034 Chain = Value.getValue(1);
12035 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12036 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12039 MachineMemOperand *MMO =
12040 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12041 MachineMemOperand::MOStore, MemSize, MemSize);
12043 if (Opc != X86ISD::WIN_FTOL) {
12044 // Build the FP_TO_INT*_IN_MEM
12045 SDValue Ops[] = { Chain, Value, StackSlot };
12046 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12048 return std::make_pair(FIST, StackSlot);
12050 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12051 DAG.getVTList(MVT::Other, MVT::Glue),
12053 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12054 MVT::i32, ftol.getValue(1));
12055 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12056 MVT::i32, eax.getValue(2));
12057 SDValue Ops[] = { eax, edx };
12058 SDValue pair = IsReplace
12059 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12060 : DAG.getMergeValues(Ops, DL);
12061 return std::make_pair(pair, SDValue());
12065 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12066 const X86Subtarget *Subtarget) {
12067 MVT VT = Op->getSimpleValueType(0);
12068 SDValue In = Op->getOperand(0);
12069 MVT InVT = In.getSimpleValueType();
12072 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12073 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12075 // Optimize vectors in AVX mode:
12078 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12079 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12080 // Concat upper and lower parts.
12083 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12084 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12085 // Concat upper and lower parts.
12088 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12089 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12090 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12093 if (Subtarget->hasInt256())
12094 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12096 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12097 SDValue Undef = DAG.getUNDEF(InVT);
12098 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12099 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12100 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12102 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12103 VT.getVectorNumElements()/2);
12105 OpLo = DAG.getBitcast(HVT, OpLo);
12106 OpHi = DAG.getBitcast(HVT, OpHi);
12108 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12111 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12112 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12113 MVT VT = Op->getSimpleValueType(0);
12114 SDValue In = Op->getOperand(0);
12115 MVT InVT = In.getSimpleValueType();
12117 unsigned int NumElts = VT.getVectorNumElements();
12118 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12121 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12122 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12124 assert(InVT.getVectorElementType() == MVT::i1);
12125 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12127 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12129 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12131 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12132 if (VT.is512BitVector())
12134 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12137 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12138 SelectionDAG &DAG) {
12139 if (Subtarget->hasFp256())
12140 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12146 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12147 SelectionDAG &DAG) {
12149 MVT VT = Op.getSimpleValueType();
12150 SDValue In = Op.getOperand(0);
12151 MVT SVT = In.getSimpleValueType();
12153 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12154 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12156 if (Subtarget->hasFp256())
12157 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12160 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12161 VT.getVectorNumElements() != SVT.getVectorNumElements());
12165 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12167 MVT VT = Op.getSimpleValueType();
12168 SDValue In = Op.getOperand(0);
12169 MVT InVT = In.getSimpleValueType();
12171 if (VT == MVT::i1) {
12172 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12173 "Invalid scalar TRUNCATE operation");
12174 if (InVT.getSizeInBits() >= 32)
12176 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12177 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12179 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12180 "Invalid TRUNCATE operation");
12182 // move vector to mask - truncate solution for SKX
12183 if (VT.getVectorElementType() == MVT::i1) {
12184 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12185 Subtarget->hasBWI())
12186 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12187 if ((InVT.is256BitVector() || InVT.is128BitVector())
12188 && InVT.getScalarSizeInBits() <= 16 &&
12189 Subtarget->hasBWI() && Subtarget->hasVLX())
12190 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12191 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12192 Subtarget->hasDQI())
12193 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12194 if ((InVT.is256BitVector() || InVT.is128BitVector())
12195 && InVT.getScalarSizeInBits() >= 32 &&
12196 Subtarget->hasDQI() && Subtarget->hasVLX())
12197 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12199 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12200 if (VT.getVectorElementType().getSizeInBits() >=8)
12201 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12203 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12204 unsigned NumElts = InVT.getVectorNumElements();
12205 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12206 if (InVT.getSizeInBits() < 512) {
12207 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12208 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12213 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12214 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12215 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12218 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12219 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12220 if (Subtarget->hasInt256()) {
12221 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12222 In = DAG.getBitcast(MVT::v8i32, In);
12223 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12225 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12226 DAG.getIntPtrConstant(0, DL));
12229 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12230 DAG.getIntPtrConstant(0, DL));
12231 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12232 DAG.getIntPtrConstant(2, DL));
12233 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12234 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12235 static const int ShufMask[] = {0, 2, 4, 6};
12236 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12239 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12240 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12241 if (Subtarget->hasInt256()) {
12242 In = DAG.getBitcast(MVT::v32i8, In);
12244 SmallVector<SDValue,32> pshufbMask;
12245 for (unsigned i = 0; i < 2; ++i) {
12246 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12247 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12248 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12249 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12250 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12251 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12252 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12253 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12254 for (unsigned j = 0; j < 8; ++j)
12255 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12257 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12258 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12259 In = DAG.getBitcast(MVT::v4i64, In);
12261 static const int ShufMask[] = {0, 2, -1, -1};
12262 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12264 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12265 DAG.getIntPtrConstant(0, DL));
12266 return DAG.getBitcast(VT, In);
12269 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12270 DAG.getIntPtrConstant(0, DL));
12272 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12273 DAG.getIntPtrConstant(4, DL));
12275 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12276 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12278 // The PSHUFB mask:
12279 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12280 -1, -1, -1, -1, -1, -1, -1, -1};
12282 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12283 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12284 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12286 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12287 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12289 // The MOVLHPS Mask:
12290 static const int ShufMask2[] = {0, 1, 4, 5};
12291 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12292 return DAG.getBitcast(MVT::v8i16, res);
12295 // Handle truncation of V256 to V128 using shuffles.
12296 if (!VT.is128BitVector() || !InVT.is256BitVector())
12299 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12301 unsigned NumElems = VT.getVectorNumElements();
12302 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12304 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12305 // Prepare truncation shuffle mask
12306 for (unsigned i = 0; i != NumElems; ++i)
12307 MaskVec[i] = i * 2;
12308 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
12309 DAG.getUNDEF(NVT), &MaskVec[0]);
12310 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12311 DAG.getIntPtrConstant(0, DL));
12314 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12315 SelectionDAG &DAG) const {
12316 assert(!Op.getSimpleValueType().isVector());
12318 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12319 /*IsSigned=*/ true, /*IsReplace=*/ false);
12320 SDValue FIST = Vals.first, StackSlot = Vals.second;
12321 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12322 if (!FIST.getNode()) return Op;
12324 if (StackSlot.getNode())
12325 // Load the result.
12326 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12327 FIST, StackSlot, MachinePointerInfo(),
12328 false, false, false, 0);
12330 // The node is the result.
12334 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12335 SelectionDAG &DAG) const {
12336 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12337 /*IsSigned=*/ false, /*IsReplace=*/ false);
12338 SDValue FIST = Vals.first, StackSlot = Vals.second;
12339 assert(FIST.getNode() && "Unexpected failure");
12341 if (StackSlot.getNode())
12342 // Load the result.
12343 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12344 FIST, StackSlot, MachinePointerInfo(),
12345 false, false, false, 0);
12347 // The node is the result.
12351 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12353 MVT VT = Op.getSimpleValueType();
12354 SDValue In = Op.getOperand(0);
12355 MVT SVT = In.getSimpleValueType();
12357 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12359 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12360 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12361 In, DAG.getUNDEF(SVT)));
12364 /// The only differences between FABS and FNEG are the mask and the logic op.
12365 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12366 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12367 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12368 "Wrong opcode for lowering FABS or FNEG.");
12370 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12372 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12373 // into an FNABS. We'll lower the FABS after that if it is still in use.
12375 for (SDNode *User : Op->uses())
12376 if (User->getOpcode() == ISD::FNEG)
12379 SDValue Op0 = Op.getOperand(0);
12380 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12383 MVT VT = Op.getSimpleValueType();
12384 // Assume scalar op for initialization; update for vector if needed.
12385 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12386 // generate a 16-byte vector constant and logic op even for the scalar case.
12387 // Using a 16-byte mask allows folding the load of the mask with
12388 // the logic op, so it can save (~4 bytes) on code size.
12390 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12391 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12392 // decide if we should generate a 16-byte constant mask when we only need 4 or
12393 // 8 bytes for the scalar case.
12394 if (VT.isVector()) {
12395 EltVT = VT.getVectorElementType();
12396 NumElts = VT.getVectorNumElements();
12399 unsigned EltBits = EltVT.getSizeInBits();
12400 LLVMContext *Context = DAG.getContext();
12401 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12403 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12404 Constant *C = ConstantInt::get(*Context, MaskElt);
12405 C = ConstantVector::getSplat(NumElts, C);
12406 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12407 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12408 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12409 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12410 MachinePointerInfo::getConstantPool(),
12411 false, false, false, Alignment);
12413 if (VT.isVector()) {
12414 // For a vector, cast operands to a vector type, perform the logic op,
12415 // and cast the result back to the original value type.
12416 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12417 SDValue MaskCasted = DAG.getBitcast(VecVT, Mask);
12418 SDValue Operand = IsFNABS ? DAG.getBitcast(VecVT, Op0.getOperand(0))
12419 : DAG.getBitcast(VecVT, Op0);
12420 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12421 return DAG.getBitcast(VT,
12422 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12425 // If not vector, then scalar.
12426 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12427 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12428 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12431 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12432 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12433 LLVMContext *Context = DAG.getContext();
12434 SDValue Op0 = Op.getOperand(0);
12435 SDValue Op1 = Op.getOperand(1);
12437 MVT VT = Op.getSimpleValueType();
12438 MVT SrcVT = Op1.getSimpleValueType();
12440 // If second operand is smaller, extend it first.
12441 if (SrcVT.bitsLT(VT)) {
12442 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12445 // And if it is bigger, shrink it first.
12446 if (SrcVT.bitsGT(VT)) {
12447 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12451 // At this point the operands and the result should have the same
12452 // type, and that won't be f80 since that is not custom lowered.
12454 const fltSemantics &Sem =
12455 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12456 const unsigned SizeInBits = VT.getSizeInBits();
12458 SmallVector<Constant *, 4> CV(
12459 VT == MVT::f64 ? 2 : 4,
12460 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12462 // First, clear all bits but the sign bit from the second operand (sign).
12463 CV[0] = ConstantFP::get(*Context,
12464 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12465 Constant *C = ConstantVector::get(CV);
12466 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12467 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12468 MachinePointerInfo::getConstantPool(),
12469 false, false, false, 16);
12470 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12472 // Next, clear the sign bit from the first operand (magnitude).
12473 // If it's a constant, we can clear it here.
12474 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12475 APFloat APF = Op0CN->getValueAPF();
12476 // If the magnitude is a positive zero, the sign bit alone is enough.
12477 if (APF.isPosZero())
12480 CV[0] = ConstantFP::get(*Context, APF);
12482 CV[0] = ConstantFP::get(
12484 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12486 C = ConstantVector::get(CV);
12487 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12488 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12489 MachinePointerInfo::getConstantPool(),
12490 false, false, false, 16);
12491 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12492 if (!isa<ConstantFPSDNode>(Op0))
12493 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12495 // OR the magnitude value with the sign bit.
12496 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12499 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12500 SDValue N0 = Op.getOperand(0);
12502 MVT VT = Op.getSimpleValueType();
12504 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12505 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12506 DAG.getConstant(1, dl, VT));
12507 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12510 // Check whether an OR'd tree is PTEST-able.
12511 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12512 SelectionDAG &DAG) {
12513 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12515 if (!Subtarget->hasSSE41())
12518 if (!Op->hasOneUse())
12521 SDNode *N = Op.getNode();
12524 SmallVector<SDValue, 8> Opnds;
12525 DenseMap<SDValue, unsigned> VecInMap;
12526 SmallVector<SDValue, 8> VecIns;
12527 EVT VT = MVT::Other;
12529 // Recognize a special case where a vector is casted into wide integer to
12531 Opnds.push_back(N->getOperand(0));
12532 Opnds.push_back(N->getOperand(1));
12534 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12535 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12536 // BFS traverse all OR'd operands.
12537 if (I->getOpcode() == ISD::OR) {
12538 Opnds.push_back(I->getOperand(0));
12539 Opnds.push_back(I->getOperand(1));
12540 // Re-evaluate the number of nodes to be traversed.
12541 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12545 // Quit if a non-EXTRACT_VECTOR_ELT
12546 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12549 // Quit if without a constant index.
12550 SDValue Idx = I->getOperand(1);
12551 if (!isa<ConstantSDNode>(Idx))
12554 SDValue ExtractedFromVec = I->getOperand(0);
12555 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12556 if (M == VecInMap.end()) {
12557 VT = ExtractedFromVec.getValueType();
12558 // Quit if not 128/256-bit vector.
12559 if (!VT.is128BitVector() && !VT.is256BitVector())
12561 // Quit if not the same type.
12562 if (VecInMap.begin() != VecInMap.end() &&
12563 VT != VecInMap.begin()->first.getValueType())
12565 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12566 VecIns.push_back(ExtractedFromVec);
12568 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12571 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12572 "Not extracted from 128-/256-bit vector.");
12574 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12576 for (DenseMap<SDValue, unsigned>::const_iterator
12577 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12578 // Quit if not all elements are used.
12579 if (I->second != FullMask)
12583 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12585 // Cast all vectors into TestVT for PTEST.
12586 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12587 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
12589 // If more than one full vectors are evaluated, OR them first before PTEST.
12590 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12591 // Each iteration will OR 2 nodes and append the result until there is only
12592 // 1 node left, i.e. the final OR'd value of all vectors.
12593 SDValue LHS = VecIns[Slot];
12594 SDValue RHS = VecIns[Slot + 1];
12595 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12598 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12599 VecIns.back(), VecIns.back());
12602 /// \brief return true if \c Op has a use that doesn't just read flags.
12603 static bool hasNonFlagsUse(SDValue Op) {
12604 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12606 SDNode *User = *UI;
12607 unsigned UOpNo = UI.getOperandNo();
12608 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12609 // Look pass truncate.
12610 UOpNo = User->use_begin().getOperandNo();
12611 User = *User->use_begin();
12614 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12615 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12621 /// Emit nodes that will be selected as "test Op0,Op0", or something
12623 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12624 SelectionDAG &DAG) const {
12625 if (Op.getValueType() == MVT::i1) {
12626 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12627 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12628 DAG.getConstant(0, dl, MVT::i8));
12630 // CF and OF aren't always set the way we want. Determine which
12631 // of these we need.
12632 bool NeedCF = false;
12633 bool NeedOF = false;
12636 case X86::COND_A: case X86::COND_AE:
12637 case X86::COND_B: case X86::COND_BE:
12640 case X86::COND_G: case X86::COND_GE:
12641 case X86::COND_L: case X86::COND_LE:
12642 case X86::COND_O: case X86::COND_NO: {
12643 // Check if we really need to set the
12644 // Overflow flag. If NoSignedWrap is present
12645 // that is not actually needed.
12646 switch (Op->getOpcode()) {
12651 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12652 if (BinNode->Flags.hasNoSignedWrap())
12662 // See if we can use the EFLAGS value from the operand instead of
12663 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12664 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12665 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12666 // Emit a CMP with 0, which is the TEST pattern.
12667 //if (Op.getValueType() == MVT::i1)
12668 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12669 // DAG.getConstant(0, MVT::i1));
12670 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12671 DAG.getConstant(0, dl, Op.getValueType()));
12673 unsigned Opcode = 0;
12674 unsigned NumOperands = 0;
12676 // Truncate operations may prevent the merge of the SETCC instruction
12677 // and the arithmetic instruction before it. Attempt to truncate the operands
12678 // of the arithmetic instruction and use a reduced bit-width instruction.
12679 bool NeedTruncation = false;
12680 SDValue ArithOp = Op;
12681 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12682 SDValue Arith = Op->getOperand(0);
12683 // Both the trunc and the arithmetic op need to have one user each.
12684 if (Arith->hasOneUse())
12685 switch (Arith.getOpcode()) {
12692 NeedTruncation = true;
12698 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12699 // which may be the result of a CAST. We use the variable 'Op', which is the
12700 // non-casted variable when we check for possible users.
12701 switch (ArithOp.getOpcode()) {
12703 // Due to an isel shortcoming, be conservative if this add is likely to be
12704 // selected as part of a load-modify-store instruction. When the root node
12705 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12706 // uses of other nodes in the match, such as the ADD in this case. This
12707 // leads to the ADD being left around and reselected, with the result being
12708 // two adds in the output. Alas, even if none our users are stores, that
12709 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12710 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12711 // climbing the DAG back to the root, and it doesn't seem to be worth the
12713 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12714 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12715 if (UI->getOpcode() != ISD::CopyToReg &&
12716 UI->getOpcode() != ISD::SETCC &&
12717 UI->getOpcode() != ISD::STORE)
12720 if (ConstantSDNode *C =
12721 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12722 // An add of one will be selected as an INC.
12723 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12724 Opcode = X86ISD::INC;
12729 // An add of negative one (subtract of one) will be selected as a DEC.
12730 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12731 Opcode = X86ISD::DEC;
12737 // Otherwise use a regular EFLAGS-setting add.
12738 Opcode = X86ISD::ADD;
12743 // If we have a constant logical shift that's only used in a comparison
12744 // against zero turn it into an equivalent AND. This allows turning it into
12745 // a TEST instruction later.
12746 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12747 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12748 EVT VT = Op.getValueType();
12749 unsigned BitWidth = VT.getSizeInBits();
12750 unsigned ShAmt = Op->getConstantOperandVal(1);
12751 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12753 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12754 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12755 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12756 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12758 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12759 DAG.getConstant(Mask, dl, VT));
12760 DAG.ReplaceAllUsesWith(Op, New);
12766 // If the primary and result isn't used, don't bother using X86ISD::AND,
12767 // because a TEST instruction will be better.
12768 if (!hasNonFlagsUse(Op))
12774 // Due to the ISEL shortcoming noted above, be conservative if this op is
12775 // likely to be selected as part of a load-modify-store instruction.
12776 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12777 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12778 if (UI->getOpcode() == ISD::STORE)
12781 // Otherwise use a regular EFLAGS-setting instruction.
12782 switch (ArithOp.getOpcode()) {
12783 default: llvm_unreachable("unexpected operator!");
12784 case ISD::SUB: Opcode = X86ISD::SUB; break;
12785 case ISD::XOR: Opcode = X86ISD::XOR; break;
12786 case ISD::AND: Opcode = X86ISD::AND; break;
12788 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12789 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12790 if (EFLAGS.getNode())
12793 Opcode = X86ISD::OR;
12807 return SDValue(Op.getNode(), 1);
12813 // If we found that truncation is beneficial, perform the truncation and
12815 if (NeedTruncation) {
12816 EVT VT = Op.getValueType();
12817 SDValue WideVal = Op->getOperand(0);
12818 EVT WideVT = WideVal.getValueType();
12819 unsigned ConvertedOp = 0;
12820 // Use a target machine opcode to prevent further DAGCombine
12821 // optimizations that may separate the arithmetic operations
12822 // from the setcc node.
12823 switch (WideVal.getOpcode()) {
12825 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12826 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12827 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12828 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12829 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12833 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12834 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12835 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12836 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12837 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12843 // Emit a CMP with 0, which is the TEST pattern.
12844 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12845 DAG.getConstant(0, dl, Op.getValueType()));
12847 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12848 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12850 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12851 DAG.ReplaceAllUsesWith(Op, New);
12852 return SDValue(New.getNode(), 1);
12855 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12857 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12858 SDLoc dl, SelectionDAG &DAG) const {
12859 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12860 if (C->getAPIntValue() == 0)
12861 return EmitTest(Op0, X86CC, dl, DAG);
12863 if (Op0.getValueType() == MVT::i1)
12864 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12867 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12868 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12869 // Do the comparison at i32 if it's smaller, besides the Atom case.
12870 // This avoids subregister aliasing issues. Keep the smaller reference
12871 // if we're optimizing for size, however, as that'll allow better folding
12872 // of memory operations.
12873 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12874 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12875 Attribute::MinSize) &&
12876 !Subtarget->isAtom()) {
12877 unsigned ExtendOp =
12878 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12879 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12880 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12882 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12883 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12884 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12886 return SDValue(Sub.getNode(), 1);
12888 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12891 /// Convert a comparison if required by the subtarget.
12892 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12893 SelectionDAG &DAG) const {
12894 // If the subtarget does not support the FUCOMI instruction, floating-point
12895 // comparisons have to be converted.
12896 if (Subtarget->hasCMov() ||
12897 Cmp.getOpcode() != X86ISD::CMP ||
12898 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12899 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12902 // The instruction selector will select an FUCOM instruction instead of
12903 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12904 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12905 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12907 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12908 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12909 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12910 DAG.getConstant(8, dl, MVT::i8));
12911 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12912 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12915 /// The minimum architected relative accuracy is 2^-12. We need one
12916 /// Newton-Raphson step to have a good float result (24 bits of precision).
12917 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12918 DAGCombinerInfo &DCI,
12919 unsigned &RefinementSteps,
12920 bool &UseOneConstNR) const {
12921 EVT VT = Op.getValueType();
12922 const char *RecipOp;
12924 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
12925 // TODO: Add support for AVX512 (v16f32).
12926 // It is likely not profitable to do this for f64 because a double-precision
12927 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12928 // instructions: convert to single, rsqrtss, convert back to double, refine
12929 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12930 // along with FMA, this could be a throughput win.
12931 if (VT == MVT::f32 && Subtarget->hasSSE1())
12933 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
12934 (VT == MVT::v8f32 && Subtarget->hasAVX()))
12935 RecipOp = "vec-sqrtf";
12939 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
12940 if (!Recips.isEnabled(RecipOp))
12943 RefinementSteps = Recips.getRefinementSteps(RecipOp);
12944 UseOneConstNR = false;
12945 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12948 /// The minimum architected relative accuracy is 2^-12. We need one
12949 /// Newton-Raphson step to have a good float result (24 bits of precision).
12950 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12951 DAGCombinerInfo &DCI,
12952 unsigned &RefinementSteps) const {
12953 EVT VT = Op.getValueType();
12954 const char *RecipOp;
12956 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12957 // TODO: Add support for AVX512 (v16f32).
12958 // It is likely not profitable to do this for f64 because a double-precision
12959 // reciprocal estimate with refinement on x86 prior to FMA requires
12960 // 15 instructions: convert to single, rcpss, convert back to double, refine
12961 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12962 // along with FMA, this could be a throughput win.
12963 if (VT == MVT::f32 && Subtarget->hasSSE1())
12965 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
12966 (VT == MVT::v8f32 && Subtarget->hasAVX()))
12967 RecipOp = "vec-divf";
12971 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
12972 if (!Recips.isEnabled(RecipOp))
12975 RefinementSteps = Recips.getRefinementSteps(RecipOp);
12976 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12979 /// If we have at least two divisions that use the same divisor, convert to
12980 /// multplication by a reciprocal. This may need to be adjusted for a given
12981 /// CPU if a division's cost is not at least twice the cost of a multiplication.
12982 /// This is because we still need one division to calculate the reciprocal and
12983 /// then we need two multiplies by that reciprocal as replacements for the
12984 /// original divisions.
12985 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
12986 return NumUsers > 1;
12989 static bool isAllOnes(SDValue V) {
12990 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12991 return C && C->isAllOnesValue();
12994 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12995 /// if it's possible.
12996 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12997 SDLoc dl, SelectionDAG &DAG) const {
12998 SDValue Op0 = And.getOperand(0);
12999 SDValue Op1 = And.getOperand(1);
13000 if (Op0.getOpcode() == ISD::TRUNCATE)
13001 Op0 = Op0.getOperand(0);
13002 if (Op1.getOpcode() == ISD::TRUNCATE)
13003 Op1 = Op1.getOperand(0);
13006 if (Op1.getOpcode() == ISD::SHL)
13007 std::swap(Op0, Op1);
13008 if (Op0.getOpcode() == ISD::SHL) {
13009 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13010 if (And00C->getZExtValue() == 1) {
13011 // If we looked past a truncate, check that it's only truncating away
13013 unsigned BitWidth = Op0.getValueSizeInBits();
13014 unsigned AndBitWidth = And.getValueSizeInBits();
13015 if (BitWidth > AndBitWidth) {
13017 DAG.computeKnownBits(Op0, Zeros, Ones);
13018 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13022 RHS = Op0.getOperand(1);
13024 } else if (Op1.getOpcode() == ISD::Constant) {
13025 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13026 uint64_t AndRHSVal = AndRHS->getZExtValue();
13027 SDValue AndLHS = Op0;
13029 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13030 LHS = AndLHS.getOperand(0);
13031 RHS = AndLHS.getOperand(1);
13034 // Use BT if the immediate can't be encoded in a TEST instruction.
13035 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13037 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13041 if (LHS.getNode()) {
13042 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13043 // instruction. Since the shift amount is in-range-or-undefined, we know
13044 // that doing a bittest on the i32 value is ok. We extend to i32 because
13045 // the encoding for the i16 version is larger than the i32 version.
13046 // Also promote i16 to i32 for performance / code size reason.
13047 if (LHS.getValueType() == MVT::i8 ||
13048 LHS.getValueType() == MVT::i16)
13049 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13051 // If the operand types disagree, extend the shift amount to match. Since
13052 // BT ignores high bits (like shifts) we can use anyextend.
13053 if (LHS.getValueType() != RHS.getValueType())
13054 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13056 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13057 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13058 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13059 DAG.getConstant(Cond, dl, MVT::i8), BT);
13065 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13067 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13072 // SSE Condition code mapping:
13081 switch (SetCCOpcode) {
13082 default: llvm_unreachable("Unexpected SETCC condition");
13084 case ISD::SETEQ: SSECC = 0; break;
13086 case ISD::SETGT: Swap = true; // Fallthrough
13088 case ISD::SETOLT: SSECC = 1; break;
13090 case ISD::SETGE: Swap = true; // Fallthrough
13092 case ISD::SETOLE: SSECC = 2; break;
13093 case ISD::SETUO: SSECC = 3; break;
13095 case ISD::SETNE: SSECC = 4; break;
13096 case ISD::SETULE: Swap = true; // Fallthrough
13097 case ISD::SETUGE: SSECC = 5; break;
13098 case ISD::SETULT: Swap = true; // Fallthrough
13099 case ISD::SETUGT: SSECC = 6; break;
13100 case ISD::SETO: SSECC = 7; break;
13102 case ISD::SETONE: SSECC = 8; break;
13105 std::swap(Op0, Op1);
13110 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13111 // ones, and then concatenate the result back.
13112 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13113 MVT VT = Op.getSimpleValueType();
13115 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13116 "Unsupported value type for operation");
13118 unsigned NumElems = VT.getVectorNumElements();
13120 SDValue CC = Op.getOperand(2);
13122 // Extract the LHS vectors
13123 SDValue LHS = Op.getOperand(0);
13124 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13125 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13127 // Extract the RHS vectors
13128 SDValue RHS = Op.getOperand(1);
13129 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13130 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13132 // Issue the operation on the smaller types and concatenate the result back
13133 MVT EltVT = VT.getVectorElementType();
13134 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13135 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13136 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13137 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13140 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13141 SDValue Op0 = Op.getOperand(0);
13142 SDValue Op1 = Op.getOperand(1);
13143 SDValue CC = Op.getOperand(2);
13144 MVT VT = Op.getSimpleValueType();
13147 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13148 "Unexpected type for boolean compare operation");
13149 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13150 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13151 DAG.getConstant(-1, dl, VT));
13152 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13153 DAG.getConstant(-1, dl, VT));
13154 switch (SetCCOpcode) {
13155 default: llvm_unreachable("Unexpected SETCC condition");
13157 // (x == y) -> ~(x ^ y)
13158 return DAG.getNode(ISD::XOR, dl, VT,
13159 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13160 DAG.getConstant(-1, dl, VT));
13162 // (x != y) -> (x ^ y)
13163 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13166 // (x > y) -> (x & ~y)
13167 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13170 // (x < y) -> (~x & y)
13171 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13174 // (x <= y) -> (~x | y)
13175 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13178 // (x >=y) -> (x | ~y)
13179 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13183 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13184 const X86Subtarget *Subtarget) {
13185 SDValue Op0 = Op.getOperand(0);
13186 SDValue Op1 = Op.getOperand(1);
13187 SDValue CC = Op.getOperand(2);
13188 MVT VT = Op.getSimpleValueType();
13191 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13192 Op.getValueType().getScalarType() == MVT::i1 &&
13193 "Cannot set masked compare for this operation");
13195 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13197 bool Unsigned = false;
13200 switch (SetCCOpcode) {
13201 default: llvm_unreachable("Unexpected SETCC condition");
13202 case ISD::SETNE: SSECC = 4; break;
13203 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13204 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13205 case ISD::SETLT: Swap = true; //fall-through
13206 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13207 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13208 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13209 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13210 case ISD::SETULE: Unsigned = true; //fall-through
13211 case ISD::SETLE: SSECC = 2; break;
13215 std::swap(Op0, Op1);
13217 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13218 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13219 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13220 DAG.getConstant(SSECC, dl, MVT::i8));
13223 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13224 /// operand \p Op1. If non-trivial (for example because it's not constant)
13225 /// return an empty value.
13226 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13228 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13232 MVT VT = Op1.getSimpleValueType();
13233 MVT EVT = VT.getVectorElementType();
13234 unsigned n = VT.getVectorNumElements();
13235 SmallVector<SDValue, 8> ULTOp1;
13237 for (unsigned i = 0; i < n; ++i) {
13238 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13239 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13242 // Avoid underflow.
13243 APInt Val = Elt->getAPIntValue();
13247 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13250 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13253 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13254 SelectionDAG &DAG) {
13255 SDValue Op0 = Op.getOperand(0);
13256 SDValue Op1 = Op.getOperand(1);
13257 SDValue CC = Op.getOperand(2);
13258 MVT VT = Op.getSimpleValueType();
13259 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13260 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13265 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13266 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13269 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13270 unsigned Opc = X86ISD::CMPP;
13271 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13272 assert(VT.getVectorNumElements() <= 16);
13273 Opc = X86ISD::CMPM;
13275 // In the two special cases we can't handle, emit two comparisons.
13278 unsigned CombineOpc;
13279 if (SetCCOpcode == ISD::SETUEQ) {
13280 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13282 assert(SetCCOpcode == ISD::SETONE);
13283 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13286 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13287 DAG.getConstant(CC0, dl, MVT::i8));
13288 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13289 DAG.getConstant(CC1, dl, MVT::i8));
13290 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13292 // Handle all other FP comparisons here.
13293 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13294 DAG.getConstant(SSECC, dl, MVT::i8));
13297 // Break 256-bit integer vector compare into smaller ones.
13298 if (VT.is256BitVector() && !Subtarget->hasInt256())
13299 return Lower256IntVSETCC(Op, DAG);
13301 EVT OpVT = Op1.getValueType();
13302 if (OpVT.getVectorElementType() == MVT::i1)
13303 return LowerBoolVSETCC_AVX512(Op, DAG);
13305 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13306 if (Subtarget->hasAVX512()) {
13307 if (Op1.getValueType().is512BitVector() ||
13308 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13309 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13310 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13312 // In AVX-512 architecture setcc returns mask with i1 elements,
13313 // But there is no compare instruction for i8 and i16 elements in KNL.
13314 // We are not talking about 512-bit operands in this case, these
13315 // types are illegal.
13317 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13318 OpVT.getVectorElementType().getSizeInBits() >= 8))
13319 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13320 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13323 // We are handling one of the integer comparisons here. Since SSE only has
13324 // GT and EQ comparisons for integer, swapping operands and multiple
13325 // operations may be required for some comparisons.
13327 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13328 bool Subus = false;
13330 switch (SetCCOpcode) {
13331 default: llvm_unreachable("Unexpected SETCC condition");
13332 case ISD::SETNE: Invert = true;
13333 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13334 case ISD::SETLT: Swap = true;
13335 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13336 case ISD::SETGE: Swap = true;
13337 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13338 Invert = true; break;
13339 case ISD::SETULT: Swap = true;
13340 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13341 FlipSigns = true; break;
13342 case ISD::SETUGE: Swap = true;
13343 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13344 FlipSigns = true; Invert = true; break;
13347 // Special case: Use min/max operations for SETULE/SETUGE
13348 MVT VET = VT.getVectorElementType();
13350 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13351 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13354 switch (SetCCOpcode) {
13356 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13357 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13360 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13363 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13364 if (!MinMax && hasSubus) {
13365 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13367 // t = psubus Op0, Op1
13368 // pcmpeq t, <0..0>
13369 switch (SetCCOpcode) {
13371 case ISD::SETULT: {
13372 // If the comparison is against a constant we can turn this into a
13373 // setule. With psubus, setule does not require a swap. This is
13374 // beneficial because the constant in the register is no longer
13375 // destructed as the destination so it can be hoisted out of a loop.
13376 // Only do this pre-AVX since vpcmp* is no longer destructive.
13377 if (Subtarget->hasAVX())
13379 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13380 if (ULEOp1.getNode()) {
13382 Subus = true; Invert = false; Swap = false;
13386 // Psubus is better than flip-sign because it requires no inversion.
13387 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13388 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13392 Opc = X86ISD::SUBUS;
13398 std::swap(Op0, Op1);
13400 // Check that the operation in question is available (most are plain SSE2,
13401 // but PCMPGTQ and PCMPEQQ have different requirements).
13402 if (VT == MVT::v2i64) {
13403 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13404 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13406 // First cast everything to the right type.
13407 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13408 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13410 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13411 // bits of the inputs before performing those operations. The lower
13412 // compare is always unsigned.
13415 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13417 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13418 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13419 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13420 Sign, Zero, Sign, Zero);
13422 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13423 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13425 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13426 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13427 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13429 // Create masks for only the low parts/high parts of the 64 bit integers.
13430 static const int MaskHi[] = { 1, 1, 3, 3 };
13431 static const int MaskLo[] = { 0, 0, 2, 2 };
13432 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13433 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13434 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13436 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13437 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13440 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13442 return DAG.getBitcast(VT, Result);
13445 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13446 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13447 // pcmpeqd + pshufd + pand.
13448 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13450 // First cast everything to the right type.
13451 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13452 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13455 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13457 // Make sure the lower and upper halves are both all-ones.
13458 static const int Mask[] = { 1, 0, 3, 2 };
13459 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13460 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13463 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13465 return DAG.getBitcast(VT, Result);
13469 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13470 // bits of the inputs before performing those operations.
13472 EVT EltVT = VT.getVectorElementType();
13473 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13475 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13476 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13479 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13481 // If the logical-not of the result is required, perform that now.
13483 Result = DAG.getNOT(dl, Result, VT);
13486 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13489 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13490 getZeroVector(VT, Subtarget, DAG, dl));
13495 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13497 MVT VT = Op.getSimpleValueType();
13499 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13501 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13502 && "SetCC type must be 8-bit or 1-bit integer");
13503 SDValue Op0 = Op.getOperand(0);
13504 SDValue Op1 = Op.getOperand(1);
13506 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13508 // Optimize to BT if possible.
13509 // Lower (X & (1 << N)) == 0 to BT(X, N).
13510 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13511 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13512 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13513 Op1.getOpcode() == ISD::Constant &&
13514 cast<ConstantSDNode>(Op1)->isNullValue() &&
13515 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13516 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13517 if (NewSetCC.getNode()) {
13519 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13524 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13526 if (Op1.getOpcode() == ISD::Constant &&
13527 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13528 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13529 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13531 // If the input is a setcc, then reuse the input setcc or use a new one with
13532 // the inverted condition.
13533 if (Op0.getOpcode() == X86ISD::SETCC) {
13534 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13535 bool Invert = (CC == ISD::SETNE) ^
13536 cast<ConstantSDNode>(Op1)->isNullValue();
13540 CCode = X86::GetOppositeBranchCondition(CCode);
13541 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13542 DAG.getConstant(CCode, dl, MVT::i8),
13543 Op0.getOperand(1));
13545 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13549 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13550 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13551 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13553 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13554 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13557 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13558 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13559 if (X86CC == X86::COND_INVALID)
13562 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13563 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13564 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13565 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13567 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13571 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13572 static bool isX86LogicalCmp(SDValue Op) {
13573 unsigned Opc = Op.getNode()->getOpcode();
13574 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13575 Opc == X86ISD::SAHF)
13577 if (Op.getResNo() == 1 &&
13578 (Opc == X86ISD::ADD ||
13579 Opc == X86ISD::SUB ||
13580 Opc == X86ISD::ADC ||
13581 Opc == X86ISD::SBB ||
13582 Opc == X86ISD::SMUL ||
13583 Opc == X86ISD::UMUL ||
13584 Opc == X86ISD::INC ||
13585 Opc == X86ISD::DEC ||
13586 Opc == X86ISD::OR ||
13587 Opc == X86ISD::XOR ||
13588 Opc == X86ISD::AND))
13591 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13597 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13598 if (V.getOpcode() != ISD::TRUNCATE)
13601 SDValue VOp0 = V.getOperand(0);
13602 unsigned InBits = VOp0.getValueSizeInBits();
13603 unsigned Bits = V.getValueSizeInBits();
13604 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13607 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13608 bool addTest = true;
13609 SDValue Cond = Op.getOperand(0);
13610 SDValue Op1 = Op.getOperand(1);
13611 SDValue Op2 = Op.getOperand(2);
13613 EVT VT = Op1.getValueType();
13616 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13617 // are available or VBLENDV if AVX is available.
13618 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13619 if (Cond.getOpcode() == ISD::SETCC &&
13620 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13621 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13622 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13623 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13624 int SSECC = translateX86FSETCC(
13625 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13628 if (Subtarget->hasAVX512()) {
13629 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13630 DAG.getConstant(SSECC, DL, MVT::i8));
13631 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13634 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13635 DAG.getConstant(SSECC, DL, MVT::i8));
13637 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13638 // of 3 logic instructions for size savings and potentially speed.
13639 // Unfortunately, there is no scalar form of VBLENDV.
13641 // If either operand is a constant, don't try this. We can expect to
13642 // optimize away at least one of the logic instructions later in that
13643 // case, so that sequence would be faster than a variable blend.
13645 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13646 // uses XMM0 as the selection register. That may need just as many
13647 // instructions as the AND/ANDN/OR sequence due to register moves, so
13650 if (Subtarget->hasAVX() &&
13651 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13653 // Convert to vectors, do a VSELECT, and convert back to scalar.
13654 // All of the conversions should be optimized away.
13656 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13657 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13658 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13659 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13661 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13662 VCmp = DAG.getBitcast(VCmpVT, VCmp);
13664 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13666 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13667 VSel, DAG.getIntPtrConstant(0, DL));
13669 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13670 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13671 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13675 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
13677 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
13678 Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
13679 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
13680 Op1Scalar = Op1.getOperand(0);
13682 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
13683 Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
13684 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
13685 Op2Scalar = Op2.getOperand(0);
13686 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
13687 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
13688 Op1Scalar.getValueType(),
13689 Cond, Op1Scalar, Op2Scalar);
13690 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
13691 return DAG.getBitcast(VT, newSelect);
13692 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
13693 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
13694 DAG.getIntPtrConstant(0, DL));
13698 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13699 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13700 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13701 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13702 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13703 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13704 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13706 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13709 if (Cond.getOpcode() == ISD::SETCC) {
13710 SDValue NewCond = LowerSETCC(Cond, DAG);
13711 if (NewCond.getNode())
13715 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13716 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13717 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13718 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13719 if (Cond.getOpcode() == X86ISD::SETCC &&
13720 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13721 isZero(Cond.getOperand(1).getOperand(1))) {
13722 SDValue Cmp = Cond.getOperand(1);
13724 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13726 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13727 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13728 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13730 SDValue CmpOp0 = Cmp.getOperand(0);
13731 // Apply further optimizations for special cases
13732 // (select (x != 0), -1, 0) -> neg & sbb
13733 // (select (x == 0), 0, -1) -> neg & sbb
13734 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13735 if (YC->isNullValue() &&
13736 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13737 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13738 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13739 DAG.getConstant(0, DL,
13740 CmpOp0.getValueType()),
13742 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13743 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13744 SDValue(Neg.getNode(), 1));
13748 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13749 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13750 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13752 SDValue Res = // Res = 0 or -1.
13753 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13754 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13756 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13757 Res = DAG.getNOT(DL, Res, Res.getValueType());
13759 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13760 if (!N2C || !N2C->isNullValue())
13761 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13766 // Look past (and (setcc_carry (cmp ...)), 1).
13767 if (Cond.getOpcode() == ISD::AND &&
13768 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13769 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13770 if (C && C->getAPIntValue() == 1)
13771 Cond = Cond.getOperand(0);
13774 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13775 // setting operand in place of the X86ISD::SETCC.
13776 unsigned CondOpcode = Cond.getOpcode();
13777 if (CondOpcode == X86ISD::SETCC ||
13778 CondOpcode == X86ISD::SETCC_CARRY) {
13779 CC = Cond.getOperand(0);
13781 SDValue Cmp = Cond.getOperand(1);
13782 unsigned Opc = Cmp.getOpcode();
13783 MVT VT = Op.getSimpleValueType();
13785 bool IllegalFPCMov = false;
13786 if (VT.isFloatingPoint() && !VT.isVector() &&
13787 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13788 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13790 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13791 Opc == X86ISD::BT) { // FIXME
13795 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13796 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13797 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13798 Cond.getOperand(0).getValueType() != MVT::i8)) {
13799 SDValue LHS = Cond.getOperand(0);
13800 SDValue RHS = Cond.getOperand(1);
13801 unsigned X86Opcode;
13804 switch (CondOpcode) {
13805 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13806 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13807 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13808 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13809 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13810 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13811 default: llvm_unreachable("unexpected overflowing operator");
13813 if (CondOpcode == ISD::UMULO)
13814 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13817 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13819 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13821 if (CondOpcode == ISD::UMULO)
13822 Cond = X86Op.getValue(2);
13824 Cond = X86Op.getValue(1);
13826 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
13831 // Look pass the truncate if the high bits are known zero.
13832 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13833 Cond = Cond.getOperand(0);
13835 // We know the result of AND is compared against zero. Try to match
13837 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13838 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13839 if (NewSetCC.getNode()) {
13840 CC = NewSetCC.getOperand(0);
13841 Cond = NewSetCC.getOperand(1);
13848 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
13849 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13852 // a < b ? -1 : 0 -> RES = ~setcc_carry
13853 // a < b ? 0 : -1 -> RES = setcc_carry
13854 // a >= b ? -1 : 0 -> RES = setcc_carry
13855 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13856 if (Cond.getOpcode() == X86ISD::SUB) {
13857 Cond = ConvertCmpIfNecessary(Cond, DAG);
13858 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13860 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13861 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13862 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13863 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13865 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13866 return DAG.getNOT(DL, Res, Res.getValueType());
13871 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13872 // widen the cmov and push the truncate through. This avoids introducing a new
13873 // branch during isel and doesn't add any extensions.
13874 if (Op.getValueType() == MVT::i8 &&
13875 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13876 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13877 if (T1.getValueType() == T2.getValueType() &&
13878 // Blacklist CopyFromReg to avoid partial register stalls.
13879 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13880 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13881 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13882 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13886 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13887 // condition is true.
13888 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13889 SDValue Ops[] = { Op2, Op1, CC, Cond };
13890 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13893 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
13894 const X86Subtarget *Subtarget,
13895 SelectionDAG &DAG) {
13896 MVT VT = Op->getSimpleValueType(0);
13897 SDValue In = Op->getOperand(0);
13898 MVT InVT = In.getSimpleValueType();
13899 MVT VTElt = VT.getVectorElementType();
13900 MVT InVTElt = InVT.getVectorElementType();
13904 if ((InVTElt == MVT::i1) &&
13905 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13906 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13908 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13909 VTElt.getSizeInBits() <= 16)) ||
13911 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13912 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13914 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13915 VTElt.getSizeInBits() >= 32))))
13916 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13918 unsigned int NumElts = VT.getVectorNumElements();
13920 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13923 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13924 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13925 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13926 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13929 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13930 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13932 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
13935 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
13937 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
13938 if (VT.is512BitVector())
13940 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
13943 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
13944 const X86Subtarget *Subtarget,
13945 SelectionDAG &DAG) {
13946 SDValue In = Op->getOperand(0);
13947 MVT VT = Op->getSimpleValueType(0);
13948 MVT InVT = In.getSimpleValueType();
13949 assert(VT.getSizeInBits() == InVT.getSizeInBits());
13951 MVT InSVT = InVT.getScalarType();
13952 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
13954 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
13956 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
13961 // SSE41 targets can use the pmovsx* instructions directly.
13962 if (Subtarget->hasSSE41())
13963 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13965 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
13969 // As SRAI is only available on i16/i32 types, we expand only up to i32
13970 // and handle i64 separately.
13971 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
13972 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
13973 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
13974 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
13975 Curr = DAG.getBitcast(CurrVT, Curr);
13978 SDValue SignExt = Curr;
13979 if (CurrVT != InVT) {
13980 unsigned SignExtShift =
13981 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
13982 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
13983 DAG.getConstant(SignExtShift, dl, MVT::i8));
13989 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
13990 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
13991 DAG.getConstant(31, dl, MVT::i8));
13992 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
13993 return DAG.getBitcast(VT, Ext);
13999 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14000 SelectionDAG &DAG) {
14001 MVT VT = Op->getSimpleValueType(0);
14002 SDValue In = Op->getOperand(0);
14003 MVT InVT = In.getSimpleValueType();
14006 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14007 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14009 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14010 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14011 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14014 if (Subtarget->hasInt256())
14015 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14017 // Optimize vectors in AVX mode
14018 // Sign extend v8i16 to v8i32 and
14021 // Divide input vector into two parts
14022 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14023 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14024 // concat the vectors to original VT
14026 unsigned NumElems = InVT.getVectorNumElements();
14027 SDValue Undef = DAG.getUNDEF(InVT);
14029 SmallVector<int,8> ShufMask1(NumElems, -1);
14030 for (unsigned i = 0; i != NumElems/2; ++i)
14033 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14035 SmallVector<int,8> ShufMask2(NumElems, -1);
14036 for (unsigned i = 0; i != NumElems/2; ++i)
14037 ShufMask2[i] = i + NumElems/2;
14039 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14041 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14042 VT.getVectorNumElements()/2);
14044 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14045 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14047 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14050 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14051 // may emit an illegal shuffle but the expansion is still better than scalar
14052 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14053 // we'll emit a shuffle and a arithmetic shift.
14054 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14055 // TODO: It is possible to support ZExt by zeroing the undef values during
14056 // the shuffle phase or after the shuffle.
14057 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14058 SelectionDAG &DAG) {
14059 MVT RegVT = Op.getSimpleValueType();
14060 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14061 assert(RegVT.isInteger() &&
14062 "We only custom lower integer vector sext loads.");
14064 // Nothing useful we can do without SSE2 shuffles.
14065 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14067 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14069 EVT MemVT = Ld->getMemoryVT();
14070 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14071 unsigned RegSz = RegVT.getSizeInBits();
14073 ISD::LoadExtType Ext = Ld->getExtensionType();
14075 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14076 && "Only anyext and sext are currently implemented.");
14077 assert(MemVT != RegVT && "Cannot extend to the same type");
14078 assert(MemVT.isVector() && "Must load a vector from memory");
14080 unsigned NumElems = RegVT.getVectorNumElements();
14081 unsigned MemSz = MemVT.getSizeInBits();
14082 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14084 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14085 // The only way in which we have a legal 256-bit vector result but not the
14086 // integer 256-bit operations needed to directly lower a sextload is if we
14087 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14088 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14089 // correctly legalized. We do this late to allow the canonical form of
14090 // sextload to persist throughout the rest of the DAG combiner -- it wants
14091 // to fold together any extensions it can, and so will fuse a sign_extend
14092 // of an sextload into a sextload targeting a wider value.
14094 if (MemSz == 128) {
14095 // Just switch this to a normal load.
14096 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14097 "it must be a legal 128-bit vector "
14099 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14100 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14101 Ld->isInvariant(), Ld->getAlignment());
14103 assert(MemSz < 128 &&
14104 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14105 // Do an sext load to a 128-bit vector type. We want to use the same
14106 // number of elements, but elements half as wide. This will end up being
14107 // recursively lowered by this routine, but will succeed as we definitely
14108 // have all the necessary features if we're using AVX1.
14110 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14111 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14113 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14114 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14115 Ld->isNonTemporal(), Ld->isInvariant(),
14116 Ld->getAlignment());
14119 // Replace chain users with the new chain.
14120 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14121 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14123 // Finally, do a normal sign-extend to the desired register.
14124 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14127 // All sizes must be a power of two.
14128 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14129 "Non-power-of-two elements are not custom lowered!");
14131 // Attempt to load the original value using scalar loads.
14132 // Find the largest scalar type that divides the total loaded size.
14133 MVT SclrLoadTy = MVT::i8;
14134 for (MVT Tp : MVT::integer_valuetypes()) {
14135 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14140 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14141 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14143 SclrLoadTy = MVT::f64;
14145 // Calculate the number of scalar loads that we need to perform
14146 // in order to load our vector from memory.
14147 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14149 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14150 "Can only lower sext loads with a single scalar load!");
14152 unsigned loadRegZize = RegSz;
14153 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14156 // Represent our vector as a sequence of elements which are the
14157 // largest scalar that we can load.
14158 EVT LoadUnitVecVT = EVT::getVectorVT(
14159 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14161 // Represent the data using the same element type that is stored in
14162 // memory. In practice, we ''widen'' MemVT.
14164 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14165 loadRegZize / MemVT.getScalarType().getSizeInBits());
14167 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14168 "Invalid vector type");
14170 // We can't shuffle using an illegal type.
14171 assert(TLI.isTypeLegal(WideVecVT) &&
14172 "We only lower types that form legal widened vector types");
14174 SmallVector<SDValue, 8> Chains;
14175 SDValue Ptr = Ld->getBasePtr();
14176 SDValue Increment =
14177 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14178 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14180 for (unsigned i = 0; i < NumLoads; ++i) {
14181 // Perform a single load.
14182 SDValue ScalarLoad =
14183 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14184 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14185 Ld->getAlignment());
14186 Chains.push_back(ScalarLoad.getValue(1));
14187 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14188 // another round of DAGCombining.
14190 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14192 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14193 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14195 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14198 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14200 // Bitcast the loaded value to a vector of the original element type, in
14201 // the size of the target vector type.
14202 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14203 unsigned SizeRatio = RegSz / MemSz;
14205 if (Ext == ISD::SEXTLOAD) {
14206 // If we have SSE4.1, we can directly emit a VSEXT node.
14207 if (Subtarget->hasSSE41()) {
14208 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14209 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14213 // Otherwise we'll shuffle the small elements in the high bits of the
14214 // larger type and perform an arithmetic shift. If the shift is not legal
14215 // it's better to scalarize.
14216 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14217 "We can't implement a sext load without an arithmetic right shift!");
14219 // Redistribute the loaded elements into the different locations.
14220 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14221 for (unsigned i = 0; i != NumElems; ++i)
14222 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14224 SDValue Shuff = DAG.getVectorShuffle(
14225 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14227 Shuff = DAG.getBitcast(RegVT, Shuff);
14229 // Build the arithmetic shift.
14230 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14231 MemVT.getVectorElementType().getSizeInBits();
14233 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14234 DAG.getConstant(Amt, dl, RegVT));
14236 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14240 // Redistribute the loaded elements into the different locations.
14241 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14242 for (unsigned i = 0; i != NumElems; ++i)
14243 ShuffleVec[i * SizeRatio] = i;
14245 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14246 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14248 // Bitcast to the requested type.
14249 Shuff = DAG.getBitcast(RegVT, Shuff);
14250 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14254 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14255 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14256 // from the AND / OR.
14257 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14258 Opc = Op.getOpcode();
14259 if (Opc != ISD::OR && Opc != ISD::AND)
14261 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14262 Op.getOperand(0).hasOneUse() &&
14263 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14264 Op.getOperand(1).hasOneUse());
14267 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14268 // 1 and that the SETCC node has a single use.
14269 static bool isXor1OfSetCC(SDValue Op) {
14270 if (Op.getOpcode() != ISD::XOR)
14272 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14273 if (N1C && N1C->getAPIntValue() == 1) {
14274 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14275 Op.getOperand(0).hasOneUse();
14280 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14281 bool addTest = true;
14282 SDValue Chain = Op.getOperand(0);
14283 SDValue Cond = Op.getOperand(1);
14284 SDValue Dest = Op.getOperand(2);
14287 bool Inverted = false;
14289 if (Cond.getOpcode() == ISD::SETCC) {
14290 // Check for setcc([su]{add,sub,mul}o == 0).
14291 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14292 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14293 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14294 Cond.getOperand(0).getResNo() == 1 &&
14295 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14296 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14297 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14298 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14299 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14300 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14302 Cond = Cond.getOperand(0);
14304 SDValue NewCond = LowerSETCC(Cond, DAG);
14305 if (NewCond.getNode())
14310 // FIXME: LowerXALUO doesn't handle these!!
14311 else if (Cond.getOpcode() == X86ISD::ADD ||
14312 Cond.getOpcode() == X86ISD::SUB ||
14313 Cond.getOpcode() == X86ISD::SMUL ||
14314 Cond.getOpcode() == X86ISD::UMUL)
14315 Cond = LowerXALUO(Cond, DAG);
14318 // Look pass (and (setcc_carry (cmp ...)), 1).
14319 if (Cond.getOpcode() == ISD::AND &&
14320 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14321 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14322 if (C && C->getAPIntValue() == 1)
14323 Cond = Cond.getOperand(0);
14326 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14327 // setting operand in place of the X86ISD::SETCC.
14328 unsigned CondOpcode = Cond.getOpcode();
14329 if (CondOpcode == X86ISD::SETCC ||
14330 CondOpcode == X86ISD::SETCC_CARRY) {
14331 CC = Cond.getOperand(0);
14333 SDValue Cmp = Cond.getOperand(1);
14334 unsigned Opc = Cmp.getOpcode();
14335 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14336 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14340 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14344 // These can only come from an arithmetic instruction with overflow,
14345 // e.g. SADDO, UADDO.
14346 Cond = Cond.getNode()->getOperand(1);
14352 CondOpcode = Cond.getOpcode();
14353 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14354 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14355 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14356 Cond.getOperand(0).getValueType() != MVT::i8)) {
14357 SDValue LHS = Cond.getOperand(0);
14358 SDValue RHS = Cond.getOperand(1);
14359 unsigned X86Opcode;
14362 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14363 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14365 switch (CondOpcode) {
14366 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14368 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14370 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14373 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14374 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14376 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14378 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14381 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14382 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14383 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14384 default: llvm_unreachable("unexpected overflowing operator");
14387 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14388 if (CondOpcode == ISD::UMULO)
14389 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14392 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14394 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14396 if (CondOpcode == ISD::UMULO)
14397 Cond = X86Op.getValue(2);
14399 Cond = X86Op.getValue(1);
14401 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14405 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14406 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14407 if (CondOpc == ISD::OR) {
14408 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14409 // two branches instead of an explicit OR instruction with a
14411 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14412 isX86LogicalCmp(Cmp)) {
14413 CC = Cond.getOperand(0).getOperand(0);
14414 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14415 Chain, Dest, CC, Cmp);
14416 CC = Cond.getOperand(1).getOperand(0);
14420 } else { // ISD::AND
14421 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14422 // two branches instead of an explicit AND instruction with a
14423 // separate test. However, we only do this if this block doesn't
14424 // have a fall-through edge, because this requires an explicit
14425 // jmp when the condition is false.
14426 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14427 isX86LogicalCmp(Cmp) &&
14428 Op.getNode()->hasOneUse()) {
14429 X86::CondCode CCode =
14430 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14431 CCode = X86::GetOppositeBranchCondition(CCode);
14432 CC = DAG.getConstant(CCode, dl, MVT::i8);
14433 SDNode *User = *Op.getNode()->use_begin();
14434 // Look for an unconditional branch following this conditional branch.
14435 // We need this because we need to reverse the successors in order
14436 // to implement FCMP_OEQ.
14437 if (User->getOpcode() == ISD::BR) {
14438 SDValue FalseBB = User->getOperand(1);
14440 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14441 assert(NewBR == User);
14445 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14446 Chain, Dest, CC, Cmp);
14447 X86::CondCode CCode =
14448 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14449 CCode = X86::GetOppositeBranchCondition(CCode);
14450 CC = DAG.getConstant(CCode, dl, MVT::i8);
14456 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14457 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14458 // It should be transformed during dag combiner except when the condition
14459 // is set by a arithmetics with overflow node.
14460 X86::CondCode CCode =
14461 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14462 CCode = X86::GetOppositeBranchCondition(CCode);
14463 CC = DAG.getConstant(CCode, dl, MVT::i8);
14464 Cond = Cond.getOperand(0).getOperand(1);
14466 } else if (Cond.getOpcode() == ISD::SETCC &&
14467 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14468 // For FCMP_OEQ, we can emit
14469 // two branches instead of an explicit AND instruction with a
14470 // separate test. However, we only do this if this block doesn't
14471 // have a fall-through edge, because this requires an explicit
14472 // jmp when the condition is false.
14473 if (Op.getNode()->hasOneUse()) {
14474 SDNode *User = *Op.getNode()->use_begin();
14475 // Look for an unconditional branch following this conditional branch.
14476 // We need this because we need to reverse the successors in order
14477 // to implement FCMP_OEQ.
14478 if (User->getOpcode() == ISD::BR) {
14479 SDValue FalseBB = User->getOperand(1);
14481 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14482 assert(NewBR == User);
14486 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14487 Cond.getOperand(0), Cond.getOperand(1));
14488 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14489 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14490 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14491 Chain, Dest, CC, Cmp);
14492 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14497 } else if (Cond.getOpcode() == ISD::SETCC &&
14498 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14499 // For FCMP_UNE, we can emit
14500 // two branches instead of an explicit AND instruction with a
14501 // separate test. However, we only do this if this block doesn't
14502 // have a fall-through edge, because this requires an explicit
14503 // jmp when the condition is false.
14504 if (Op.getNode()->hasOneUse()) {
14505 SDNode *User = *Op.getNode()->use_begin();
14506 // Look for an unconditional branch following this conditional branch.
14507 // We need this because we need to reverse the successors in order
14508 // to implement FCMP_UNE.
14509 if (User->getOpcode() == ISD::BR) {
14510 SDValue FalseBB = User->getOperand(1);
14512 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14513 assert(NewBR == User);
14516 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14517 Cond.getOperand(0), Cond.getOperand(1));
14518 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14519 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14520 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14521 Chain, Dest, CC, Cmp);
14522 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14532 // Look pass the truncate if the high bits are known zero.
14533 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14534 Cond = Cond.getOperand(0);
14536 // We know the result of AND is compared against zero. Try to match
14538 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14539 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14540 if (NewSetCC.getNode()) {
14541 CC = NewSetCC.getOperand(0);
14542 Cond = NewSetCC.getOperand(1);
14549 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14550 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14551 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14553 Cond = ConvertCmpIfNecessary(Cond, DAG);
14554 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14555 Chain, Dest, CC, Cond);
14558 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14559 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14560 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14561 // that the guard pages used by the OS virtual memory manager are allocated in
14562 // correct sequence.
14564 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14565 SelectionDAG &DAG) const {
14566 MachineFunction &MF = DAG.getMachineFunction();
14567 bool SplitStack = MF.shouldSplitStack();
14568 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14573 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14574 SDNode* Node = Op.getNode();
14576 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14577 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14578 " not tell us which reg is the stack pointer!");
14579 EVT VT = Node->getValueType(0);
14580 SDValue Tmp1 = SDValue(Node, 0);
14581 SDValue Tmp2 = SDValue(Node, 1);
14582 SDValue Tmp3 = Node->getOperand(2);
14583 SDValue Chain = Tmp1.getOperand(0);
14585 // Chain the dynamic stack allocation so that it doesn't modify the stack
14586 // pointer when other instructions are using the stack.
14587 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14590 SDValue Size = Tmp2.getOperand(1);
14591 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14592 Chain = SP.getValue(1);
14593 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14594 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14595 unsigned StackAlign = TFI.getStackAlignment();
14596 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14597 if (Align > StackAlign)
14598 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14599 DAG.getConstant(-(uint64_t)Align, dl, VT));
14600 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14602 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14603 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14606 SDValue Ops[2] = { Tmp1, Tmp2 };
14607 return DAG.getMergeValues(Ops, dl);
14611 SDValue Chain = Op.getOperand(0);
14612 SDValue Size = Op.getOperand(1);
14613 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14614 EVT VT = Op.getNode()->getValueType(0);
14616 bool Is64Bit = Subtarget->is64Bit();
14617 EVT SPTy = getPointerTy();
14620 MachineRegisterInfo &MRI = MF.getRegInfo();
14623 // The 64 bit implementation of segmented stacks needs to clobber both r10
14624 // r11. This makes it impossible to use it along with nested parameters.
14625 const Function *F = MF.getFunction();
14627 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14629 if (I->hasNestAttr())
14630 report_fatal_error("Cannot use segmented stacks with functions that "
14631 "have nested arguments.");
14634 const TargetRegisterClass *AddrRegClass =
14635 getRegClassFor(getPointerTy());
14636 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14637 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14638 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14639 DAG.getRegister(Vreg, SPTy));
14640 SDValue Ops1[2] = { Value, Chain };
14641 return DAG.getMergeValues(Ops1, dl);
14644 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14646 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14647 Flag = Chain.getValue(1);
14648 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14650 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14652 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14653 unsigned SPReg = RegInfo->getStackRegister();
14654 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14655 Chain = SP.getValue(1);
14658 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14659 DAG.getConstant(-(uint64_t)Align, dl, VT));
14660 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14663 SDValue Ops1[2] = { SP, Chain };
14664 return DAG.getMergeValues(Ops1, dl);
14668 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14669 MachineFunction &MF = DAG.getMachineFunction();
14670 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14672 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14675 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14676 // vastart just stores the address of the VarArgsFrameIndex slot into the
14677 // memory location argument.
14678 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14680 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14681 MachinePointerInfo(SV), false, false, 0);
14685 // gp_offset (0 - 6 * 8)
14686 // fp_offset (48 - 48 + 8 * 16)
14687 // overflow_arg_area (point to parameters coming in memory).
14689 SmallVector<SDValue, 8> MemOps;
14690 SDValue FIN = Op.getOperand(1);
14692 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14693 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14695 FIN, MachinePointerInfo(SV), false, false, 0);
14696 MemOps.push_back(Store);
14699 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14700 FIN, DAG.getIntPtrConstant(4, DL));
14701 Store = DAG.getStore(Op.getOperand(0), DL,
14702 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14704 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14705 MemOps.push_back(Store);
14707 // Store ptr to overflow_arg_area
14708 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14709 FIN, DAG.getIntPtrConstant(4, DL));
14710 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14712 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14713 MachinePointerInfo(SV, 8),
14715 MemOps.push_back(Store);
14717 // Store ptr to reg_save_area.
14718 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14719 FIN, DAG.getIntPtrConstant(8, DL));
14720 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14722 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14723 MachinePointerInfo(SV, 16), false, false, 0);
14724 MemOps.push_back(Store);
14725 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14728 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14729 assert(Subtarget->is64Bit() &&
14730 "LowerVAARG only handles 64-bit va_arg!");
14731 assert((Subtarget->isTargetLinux() ||
14732 Subtarget->isTargetDarwin()) &&
14733 "Unhandled target in LowerVAARG");
14734 assert(Op.getNode()->getNumOperands() == 4);
14735 SDValue Chain = Op.getOperand(0);
14736 SDValue SrcPtr = Op.getOperand(1);
14737 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14738 unsigned Align = Op.getConstantOperandVal(3);
14741 EVT ArgVT = Op.getNode()->getValueType(0);
14742 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14743 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14746 // Decide which area this value should be read from.
14747 // TODO: Implement the AMD64 ABI in its entirety. This simple
14748 // selection mechanism works only for the basic types.
14749 if (ArgVT == MVT::f80) {
14750 llvm_unreachable("va_arg for f80 not yet implemented");
14751 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14752 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14753 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14754 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14756 llvm_unreachable("Unhandled argument type in LowerVAARG");
14759 if (ArgMode == 2) {
14760 // Sanity Check: Make sure using fp_offset makes sense.
14761 assert(!Subtarget->useSoftFloat() &&
14762 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14763 Attribute::NoImplicitFloat)) &&
14764 Subtarget->hasSSE1());
14767 // Insert VAARG_64 node into the DAG
14768 // VAARG_64 returns two values: Variable Argument Address, Chain
14769 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14770 DAG.getConstant(ArgMode, dl, MVT::i8),
14771 DAG.getConstant(Align, dl, MVT::i32)};
14772 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14773 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14774 VTs, InstOps, MVT::i64,
14775 MachinePointerInfo(SV),
14777 /*Volatile=*/false,
14779 /*WriteMem=*/true);
14780 Chain = VAARG.getValue(1);
14782 // Load the next argument and return it
14783 return DAG.getLoad(ArgVT, dl,
14786 MachinePointerInfo(),
14787 false, false, false, 0);
14790 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14791 SelectionDAG &DAG) {
14792 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14793 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14794 SDValue Chain = Op.getOperand(0);
14795 SDValue DstPtr = Op.getOperand(1);
14796 SDValue SrcPtr = Op.getOperand(2);
14797 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14798 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14801 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14802 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
14804 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14807 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14808 // amount is a constant. Takes immediate version of shift as input.
14809 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14810 SDValue SrcOp, uint64_t ShiftAmt,
14811 SelectionDAG &DAG) {
14812 MVT ElementType = VT.getVectorElementType();
14814 // Fold this packed shift into its first operand if ShiftAmt is 0.
14818 // Check for ShiftAmt >= element width
14819 if (ShiftAmt >= ElementType.getSizeInBits()) {
14820 if (Opc == X86ISD::VSRAI)
14821 ShiftAmt = ElementType.getSizeInBits() - 1;
14823 return DAG.getConstant(0, dl, VT);
14826 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14827 && "Unknown target vector shift-by-constant node");
14829 // Fold this packed vector shift into a build vector if SrcOp is a
14830 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14831 if (VT == SrcOp.getSimpleValueType() &&
14832 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14833 SmallVector<SDValue, 8> Elts;
14834 unsigned NumElts = SrcOp->getNumOperands();
14835 ConstantSDNode *ND;
14838 default: llvm_unreachable(nullptr);
14839 case X86ISD::VSHLI:
14840 for (unsigned i=0; i!=NumElts; ++i) {
14841 SDValue CurrentOp = SrcOp->getOperand(i);
14842 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14843 Elts.push_back(CurrentOp);
14846 ND = cast<ConstantSDNode>(CurrentOp);
14847 const APInt &C = ND->getAPIntValue();
14848 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
14851 case X86ISD::VSRLI:
14852 for (unsigned i=0; i!=NumElts; ++i) {
14853 SDValue CurrentOp = SrcOp->getOperand(i);
14854 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14855 Elts.push_back(CurrentOp);
14858 ND = cast<ConstantSDNode>(CurrentOp);
14859 const APInt &C = ND->getAPIntValue();
14860 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
14863 case X86ISD::VSRAI:
14864 for (unsigned i=0; i!=NumElts; ++i) {
14865 SDValue CurrentOp = SrcOp->getOperand(i);
14866 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14867 Elts.push_back(CurrentOp);
14870 ND = cast<ConstantSDNode>(CurrentOp);
14871 const APInt &C = ND->getAPIntValue();
14872 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
14877 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14880 return DAG.getNode(Opc, dl, VT, SrcOp,
14881 DAG.getConstant(ShiftAmt, dl, MVT::i8));
14884 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14885 // may or may not be a constant. Takes immediate version of shift as input.
14886 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14887 SDValue SrcOp, SDValue ShAmt,
14888 SelectionDAG &DAG) {
14889 MVT SVT = ShAmt.getSimpleValueType();
14890 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14892 // Catch shift-by-constant.
14893 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14894 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14895 CShAmt->getZExtValue(), DAG);
14897 // Change opcode to non-immediate version
14899 default: llvm_unreachable("Unknown target vector shift node");
14900 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14901 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14902 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14905 const X86Subtarget &Subtarget =
14906 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14907 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14908 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14909 // Let the shuffle legalizer expand this shift amount node.
14910 SDValue Op0 = ShAmt.getOperand(0);
14911 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14912 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14914 // Need to build a vector containing shift amount.
14915 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14916 SmallVector<SDValue, 4> ShOps;
14917 ShOps.push_back(ShAmt);
14918 if (SVT == MVT::i32) {
14919 ShOps.push_back(DAG.getConstant(0, dl, SVT));
14920 ShOps.push_back(DAG.getUNDEF(SVT));
14922 ShOps.push_back(DAG.getUNDEF(SVT));
14924 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14925 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14928 // The return type has to be a 128-bit type with the same element
14929 // type as the input type.
14930 MVT EltVT = VT.getVectorElementType();
14931 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14933 ShAmt = DAG.getBitcast(ShVT, ShAmt);
14934 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14937 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14938 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14939 /// necessary casting for \p Mask when lowering masking intrinsics.
14940 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14941 SDValue PreservedSrc,
14942 const X86Subtarget *Subtarget,
14943 SelectionDAG &DAG) {
14944 EVT VT = Op.getValueType();
14945 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14946 MVT::i1, VT.getVectorNumElements());
14947 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14948 Mask.getValueType().getSizeInBits());
14951 assert(MaskVT.isSimple() && "invalid mask type");
14953 if (isAllOnes(Mask))
14956 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14957 // are extracted by EXTRACT_SUBVECTOR.
14958 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14959 DAG.getBitcast(BitcastVT, Mask),
14960 DAG.getIntPtrConstant(0, dl));
14962 switch (Op.getOpcode()) {
14964 case X86ISD::PCMPEQM:
14965 case X86ISD::PCMPGTM:
14967 case X86ISD::CMPMU:
14968 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14970 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14971 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14972 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14975 /// \brief Creates an SDNode for a predicated scalar operation.
14976 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14977 /// The mask is comming as MVT::i8 and it should be truncated
14978 /// to MVT::i1 while lowering masking intrinsics.
14979 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14980 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14981 /// a scalar instruction.
14982 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14983 SDValue PreservedSrc,
14984 const X86Subtarget *Subtarget,
14985 SelectionDAG &DAG) {
14986 if (isAllOnes(Mask))
14989 EVT VT = Op.getValueType();
14991 // The mask should be of type MVT::i1
14992 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
14994 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14995 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14996 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
14999 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15000 /// function or when returning to a parent frame after catching an exception, we
15001 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15002 /// Here's the math:
15003 /// RegNodeBase = EntryEBP - RegNodeSize
15004 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15005 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15006 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15007 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15008 SDValue EntryEBP) {
15009 MachineFunction &MF = DAG.getMachineFunction();
15012 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15013 MVT PtrVT = TLI.getPointerTy();
15015 // It's possible that the parent function no longer has a personality function
15016 // if the exceptional code was optimized away, in which case we just return
15017 // the incoming EBP.
15018 if (!Fn->hasPersonalityFn())
15021 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15022 // WinEHStatePass for the full struct definition.
15024 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15026 report_fatal_error("can only recover FP for MSVC EH personality functions");
15027 case EHPersonality::MSVC_X86SEH: RegNodeSize = 24; break;
15028 case EHPersonality::MSVC_CXX: RegNodeSize = 16; break;
15031 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15033 MCSymbol *OffsetSym =
15034 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15035 GlobalValue::getRealLinkageName(Fn->getName()));
15036 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15037 SDValue RegNodeFrameOffset =
15038 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, dl, PtrVT, OffsetSymVal);
15040 // RegNodeBase = EntryEBP - RegNodeSize
15041 // ParentFP = RegNodeBase - RegNodeFrameOffset
15042 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15043 DAG.getConstant(RegNodeSize, dl, PtrVT));
15044 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15047 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15048 SelectionDAG &DAG) {
15050 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15051 EVT VT = Op.getValueType();
15052 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15054 switch(IntrData->Type) {
15055 case INTR_TYPE_1OP:
15056 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15057 case INTR_TYPE_2OP:
15058 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15060 case INTR_TYPE_3OP:
15061 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15062 Op.getOperand(2), Op.getOperand(3));
15063 case INTR_TYPE_1OP_MASK_RM: {
15064 SDValue Src = Op.getOperand(1);
15065 SDValue PassThru = Op.getOperand(2);
15066 SDValue Mask = Op.getOperand(3);
15067 SDValue RoundingMode;
15068 if (Op.getNumOperands() == 4)
15069 RoundingMode = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15071 RoundingMode = Op.getOperand(4);
15072 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15073 if (IntrWithRoundingModeOpcode != 0) {
15074 unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue();
15075 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
15076 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15077 dl, Op.getValueType(), Src, RoundingMode),
15078 Mask, PassThru, Subtarget, DAG);
15080 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15082 Mask, PassThru, Subtarget, DAG);
15084 case INTR_TYPE_1OP_MASK: {
15085 SDValue Src = Op.getOperand(1);
15086 SDValue Passthru = Op.getOperand(2);
15087 SDValue Mask = Op.getOperand(3);
15088 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15089 Mask, Passthru, Subtarget, DAG);
15091 case INTR_TYPE_SCALAR_MASK_RM: {
15092 SDValue Src1 = Op.getOperand(1);
15093 SDValue Src2 = Op.getOperand(2);
15094 SDValue Src0 = Op.getOperand(3);
15095 SDValue Mask = Op.getOperand(4);
15096 // There are 2 kinds of intrinsics in this group:
15097 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
15098 // (2) With rounding mode and sae - 7 operands.
15099 if (Op.getNumOperands() == 6) {
15100 SDValue Sae = Op.getOperand(5);
15101 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15102 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15104 Mask, Src0, Subtarget, DAG);
15106 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15107 SDValue RoundingMode = Op.getOperand(5);
15108 SDValue Sae = Op.getOperand(6);
15109 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15110 RoundingMode, Sae),
15111 Mask, Src0, Subtarget, DAG);
15113 case INTR_TYPE_2OP_MASK: {
15114 SDValue Src1 = Op.getOperand(1);
15115 SDValue Src2 = Op.getOperand(2);
15116 SDValue PassThru = Op.getOperand(3);
15117 SDValue Mask = Op.getOperand(4);
15118 // We specify 2 possible opcodes for intrinsics with rounding modes.
15119 // First, we check if the intrinsic may have non-default rounding mode,
15120 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15121 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15122 if (IntrWithRoundingModeOpcode != 0) {
15123 SDValue Rnd = Op.getOperand(5);
15124 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15125 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15126 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15127 dl, Op.getValueType(),
15129 Mask, PassThru, Subtarget, DAG);
15132 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15134 Mask, PassThru, Subtarget, DAG);
15136 case INTR_TYPE_2OP_MASK_RM: {
15137 SDValue Src1 = Op.getOperand(1);
15138 SDValue Src2 = Op.getOperand(2);
15139 SDValue PassThru = Op.getOperand(3);
15140 SDValue Mask = Op.getOperand(4);
15141 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15142 // First, we check if the intrinsic have rounding mode (6 operands),
15143 // if not, we set rounding mode to "current".
15145 if (Op.getNumOperands() == 6)
15146 Rnd = Op.getOperand(5);
15148 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15149 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15151 Mask, PassThru, Subtarget, DAG);
15153 case INTR_TYPE_3OP_MASK: {
15154 SDValue Src1 = Op.getOperand(1);
15155 SDValue Src2 = Op.getOperand(2);
15156 SDValue Src3 = Op.getOperand(3);
15157 SDValue PassThru = Op.getOperand(4);
15158 SDValue Mask = Op.getOperand(5);
15159 // We specify 2 possible opcodes for intrinsics with rounding modes.
15160 // First, we check if the intrinsic may have non-default rounding mode,
15161 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15162 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15163 if (IntrWithRoundingModeOpcode != 0) {
15164 SDValue Rnd = Op.getOperand(6);
15165 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15166 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15167 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15168 dl, Op.getValueType(),
15169 Src1, Src2, Src3, Rnd),
15170 Mask, PassThru, Subtarget, DAG);
15173 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15175 Mask, PassThru, Subtarget, DAG);
15177 case VPERM_3OP_MASKZ:
15178 case VPERM_3OP_MASK:
15181 case FMA_OP_MASK: {
15182 SDValue Src1 = Op.getOperand(1);
15183 SDValue Src2 = Op.getOperand(2);
15184 SDValue Src3 = Op.getOperand(3);
15185 SDValue Mask = Op.getOperand(4);
15186 EVT VT = Op.getValueType();
15187 SDValue PassThru = SDValue();
15189 // set PassThru element
15190 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
15191 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
15192 else if (IntrData->Type == FMA_OP_MASK3)
15197 // We specify 2 possible opcodes for intrinsics with rounding modes.
15198 // First, we check if the intrinsic may have non-default rounding mode,
15199 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15200 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15201 if (IntrWithRoundingModeOpcode != 0) {
15202 SDValue Rnd = Op.getOperand(5);
15203 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15204 X86::STATIC_ROUNDING::CUR_DIRECTION)
15205 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15206 dl, Op.getValueType(),
15207 Src1, Src2, Src3, Rnd),
15208 Mask, PassThru, Subtarget, DAG);
15210 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15211 dl, Op.getValueType(),
15213 Mask, PassThru, Subtarget, DAG);
15216 case CMP_MASK_CC: {
15217 // Comparison intrinsics with masks.
15218 // Example of transformation:
15219 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15220 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15222 // (v8i1 (insert_subvector undef,
15223 // (v2i1 (and (PCMPEQM %a, %b),
15224 // (extract_subvector
15225 // (v8i1 (bitcast %mask)), 0))), 0))))
15226 EVT VT = Op.getOperand(1).getValueType();
15227 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15228 VT.getVectorNumElements());
15229 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15230 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15231 Mask.getValueType().getSizeInBits());
15233 if (IntrData->Type == CMP_MASK_CC) {
15234 SDValue CC = Op.getOperand(3);
15235 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15236 // We specify 2 possible opcodes for intrinsics with rounding modes.
15237 // First, we check if the intrinsic may have non-default rounding mode,
15238 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15239 if (IntrData->Opc1 != 0) {
15240 SDValue Rnd = Op.getOperand(5);
15241 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15242 X86::STATIC_ROUNDING::CUR_DIRECTION)
15243 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15244 Op.getOperand(2), CC, Rnd);
15246 //default rounding mode
15248 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15249 Op.getOperand(2), CC);
15252 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15253 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15256 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15257 DAG.getTargetConstant(0, dl,
15260 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15261 DAG.getUNDEF(BitcastVT), CmpMask,
15262 DAG.getIntPtrConstant(0, dl));
15263 return DAG.getBitcast(Op.getValueType(), Res);
15265 case COMI: { // Comparison intrinsics
15266 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15267 SDValue LHS = Op.getOperand(1);
15268 SDValue RHS = Op.getOperand(2);
15269 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15270 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15271 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15272 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15273 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15274 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15277 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15278 Op.getOperand(1), Op.getOperand(2), DAG);
15280 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15281 Op.getSimpleValueType(),
15283 Op.getOperand(2), DAG),
15284 Op.getOperand(4), Op.getOperand(3), Subtarget,
15286 case COMPRESS_EXPAND_IN_REG: {
15287 SDValue Mask = Op.getOperand(3);
15288 SDValue DataToCompress = Op.getOperand(1);
15289 SDValue PassThru = Op.getOperand(2);
15290 if (isAllOnes(Mask)) // return data as is
15291 return Op.getOperand(1);
15293 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15295 Mask, PassThru, Subtarget, DAG);
15298 SDValue Mask = Op.getOperand(3);
15299 EVT VT = Op.getValueType();
15300 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15301 VT.getVectorNumElements());
15302 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15303 Mask.getValueType().getSizeInBits());
15305 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15306 DAG.getBitcast(BitcastVT, Mask),
15307 DAG.getIntPtrConstant(0, dl));
15308 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15317 default: return SDValue(); // Don't custom lower most intrinsics.
15319 case Intrinsic::x86_avx2_permd:
15320 case Intrinsic::x86_avx2_permps:
15321 // Operands intentionally swapped. Mask is last operand to intrinsic,
15322 // but second operand for node/instruction.
15323 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15324 Op.getOperand(2), Op.getOperand(1));
15326 // ptest and testp intrinsics. The intrinsic these come from are designed to
15327 // return an integer value, not just an instruction so lower it to the ptest
15328 // or testp pattern and a setcc for the result.
15329 case Intrinsic::x86_sse41_ptestz:
15330 case Intrinsic::x86_sse41_ptestc:
15331 case Intrinsic::x86_sse41_ptestnzc:
15332 case Intrinsic::x86_avx_ptestz_256:
15333 case Intrinsic::x86_avx_ptestc_256:
15334 case Intrinsic::x86_avx_ptestnzc_256:
15335 case Intrinsic::x86_avx_vtestz_ps:
15336 case Intrinsic::x86_avx_vtestc_ps:
15337 case Intrinsic::x86_avx_vtestnzc_ps:
15338 case Intrinsic::x86_avx_vtestz_pd:
15339 case Intrinsic::x86_avx_vtestc_pd:
15340 case Intrinsic::x86_avx_vtestnzc_pd:
15341 case Intrinsic::x86_avx_vtestz_ps_256:
15342 case Intrinsic::x86_avx_vtestc_ps_256:
15343 case Intrinsic::x86_avx_vtestnzc_ps_256:
15344 case Intrinsic::x86_avx_vtestz_pd_256:
15345 case Intrinsic::x86_avx_vtestc_pd_256:
15346 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15347 bool IsTestPacked = false;
15350 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15351 case Intrinsic::x86_avx_vtestz_ps:
15352 case Intrinsic::x86_avx_vtestz_pd:
15353 case Intrinsic::x86_avx_vtestz_ps_256:
15354 case Intrinsic::x86_avx_vtestz_pd_256:
15355 IsTestPacked = true; // Fallthrough
15356 case Intrinsic::x86_sse41_ptestz:
15357 case Intrinsic::x86_avx_ptestz_256:
15359 X86CC = X86::COND_E;
15361 case Intrinsic::x86_avx_vtestc_ps:
15362 case Intrinsic::x86_avx_vtestc_pd:
15363 case Intrinsic::x86_avx_vtestc_ps_256:
15364 case Intrinsic::x86_avx_vtestc_pd_256:
15365 IsTestPacked = true; // Fallthrough
15366 case Intrinsic::x86_sse41_ptestc:
15367 case Intrinsic::x86_avx_ptestc_256:
15369 X86CC = X86::COND_B;
15371 case Intrinsic::x86_avx_vtestnzc_ps:
15372 case Intrinsic::x86_avx_vtestnzc_pd:
15373 case Intrinsic::x86_avx_vtestnzc_ps_256:
15374 case Intrinsic::x86_avx_vtestnzc_pd_256:
15375 IsTestPacked = true; // Fallthrough
15376 case Intrinsic::x86_sse41_ptestnzc:
15377 case Intrinsic::x86_avx_ptestnzc_256:
15379 X86CC = X86::COND_A;
15383 SDValue LHS = Op.getOperand(1);
15384 SDValue RHS = Op.getOperand(2);
15385 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15386 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15387 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15388 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15389 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15391 case Intrinsic::x86_avx512_kortestz_w:
15392 case Intrinsic::x86_avx512_kortestc_w: {
15393 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15394 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
15395 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
15396 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15397 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15398 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15399 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15402 case Intrinsic::x86_sse42_pcmpistria128:
15403 case Intrinsic::x86_sse42_pcmpestria128:
15404 case Intrinsic::x86_sse42_pcmpistric128:
15405 case Intrinsic::x86_sse42_pcmpestric128:
15406 case Intrinsic::x86_sse42_pcmpistrio128:
15407 case Intrinsic::x86_sse42_pcmpestrio128:
15408 case Intrinsic::x86_sse42_pcmpistris128:
15409 case Intrinsic::x86_sse42_pcmpestris128:
15410 case Intrinsic::x86_sse42_pcmpistriz128:
15411 case Intrinsic::x86_sse42_pcmpestriz128: {
15415 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15416 case Intrinsic::x86_sse42_pcmpistria128:
15417 Opcode = X86ISD::PCMPISTRI;
15418 X86CC = X86::COND_A;
15420 case Intrinsic::x86_sse42_pcmpestria128:
15421 Opcode = X86ISD::PCMPESTRI;
15422 X86CC = X86::COND_A;
15424 case Intrinsic::x86_sse42_pcmpistric128:
15425 Opcode = X86ISD::PCMPISTRI;
15426 X86CC = X86::COND_B;
15428 case Intrinsic::x86_sse42_pcmpestric128:
15429 Opcode = X86ISD::PCMPESTRI;
15430 X86CC = X86::COND_B;
15432 case Intrinsic::x86_sse42_pcmpistrio128:
15433 Opcode = X86ISD::PCMPISTRI;
15434 X86CC = X86::COND_O;
15436 case Intrinsic::x86_sse42_pcmpestrio128:
15437 Opcode = X86ISD::PCMPESTRI;
15438 X86CC = X86::COND_O;
15440 case Intrinsic::x86_sse42_pcmpistris128:
15441 Opcode = X86ISD::PCMPISTRI;
15442 X86CC = X86::COND_S;
15444 case Intrinsic::x86_sse42_pcmpestris128:
15445 Opcode = X86ISD::PCMPESTRI;
15446 X86CC = X86::COND_S;
15448 case Intrinsic::x86_sse42_pcmpistriz128:
15449 Opcode = X86ISD::PCMPISTRI;
15450 X86CC = X86::COND_E;
15452 case Intrinsic::x86_sse42_pcmpestriz128:
15453 Opcode = X86ISD::PCMPESTRI;
15454 X86CC = X86::COND_E;
15457 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15458 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15459 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15460 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15461 DAG.getConstant(X86CC, dl, MVT::i8),
15462 SDValue(PCMP.getNode(), 1));
15463 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15466 case Intrinsic::x86_sse42_pcmpistri128:
15467 case Intrinsic::x86_sse42_pcmpestri128: {
15469 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15470 Opcode = X86ISD::PCMPISTRI;
15472 Opcode = X86ISD::PCMPESTRI;
15474 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15475 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15476 return DAG.getNode(Opcode, dl, VTs, NewOps);
15479 case Intrinsic::x86_seh_lsda: {
15480 // Compute the symbol for the LSDA. We know it'll get emitted later.
15481 MachineFunction &MF = DAG.getMachineFunction();
15482 SDValue Op1 = Op.getOperand(1);
15483 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15484 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15485 GlobalValue::getRealLinkageName(Fn->getName()));
15487 // Generate a simple absolute symbol reference. This intrinsic is only
15488 // supported on 32-bit Windows, which isn't PIC.
15489 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
15490 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15493 case Intrinsic::x86_seh_recoverfp: {
15494 SDValue FnOp = Op.getOperand(1);
15495 SDValue IncomingFPOp = Op.getOperand(2);
15496 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
15497 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
15499 report_fatal_error(
15500 "llvm.x86.seh.recoverfp must take a function as the first argument");
15501 return recoverFramePointer(DAG, Fn, IncomingFPOp);
15506 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15507 SDValue Src, SDValue Mask, SDValue Base,
15508 SDValue Index, SDValue ScaleOp, SDValue Chain,
15509 const X86Subtarget * Subtarget) {
15511 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15513 llvm_unreachable("Invalid scale type");
15514 unsigned ScaleVal = C->getZExtValue();
15515 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
15516 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
15518 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15519 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15520 Index.getSimpleValueType().getVectorNumElements());
15522 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15524 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15526 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15527 Mask.getValueType().getSizeInBits());
15529 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15530 // are extracted by EXTRACT_SUBVECTOR.
15531 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15532 DAG.getBitcast(BitcastVT, Mask),
15533 DAG.getIntPtrConstant(0, dl));
15535 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15536 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15537 SDValue Segment = DAG.getRegister(0, MVT::i32);
15538 if (Src.getOpcode() == ISD::UNDEF)
15539 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15540 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15541 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15542 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15543 return DAG.getMergeValues(RetOps, dl);
15546 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15547 SDValue Src, SDValue Mask, SDValue Base,
15548 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15550 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15552 llvm_unreachable("Invalid scale type");
15553 unsigned ScaleVal = C->getZExtValue();
15554 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
15555 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
15557 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15558 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15559 SDValue Segment = DAG.getRegister(0, MVT::i32);
15560 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15561 Index.getSimpleValueType().getVectorNumElements());
15563 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15565 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15567 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15568 Mask.getValueType().getSizeInBits());
15570 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15571 // are extracted by EXTRACT_SUBVECTOR.
15572 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15573 DAG.getBitcast(BitcastVT, Mask),
15574 DAG.getIntPtrConstant(0, dl));
15576 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15577 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15578 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15579 return SDValue(Res, 1);
15582 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15583 SDValue Mask, SDValue Base, SDValue Index,
15584 SDValue ScaleOp, SDValue Chain) {
15586 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15587 assert(C && "Invalid scale type");
15588 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15589 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15590 SDValue Segment = DAG.getRegister(0, MVT::i32);
15592 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15594 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15596 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15598 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15599 //SDVTList VTs = DAG.getVTList(MVT::Other);
15600 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15601 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15602 return SDValue(Res, 0);
15605 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15606 // read performance monitor counters (x86_rdpmc).
15607 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15608 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15609 SmallVectorImpl<SDValue> &Results) {
15610 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15611 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15614 // The ECX register is used to select the index of the performance counter
15616 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15618 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15620 // Reads the content of a 64-bit performance counter and returns it in the
15621 // registers EDX:EAX.
15622 if (Subtarget->is64Bit()) {
15623 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15624 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15627 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15628 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15631 Chain = HI.getValue(1);
15633 if (Subtarget->is64Bit()) {
15634 // The EAX register is loaded with the low-order 32 bits. The EDX register
15635 // is loaded with the supported high-order bits of the counter.
15636 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15637 DAG.getConstant(32, DL, MVT::i8));
15638 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15639 Results.push_back(Chain);
15643 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15644 SDValue Ops[] = { LO, HI };
15645 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15646 Results.push_back(Pair);
15647 Results.push_back(Chain);
15650 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15651 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15652 // also used to custom lower READCYCLECOUNTER nodes.
15653 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15654 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15655 SmallVectorImpl<SDValue> &Results) {
15656 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15657 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15660 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15661 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15662 // and the EAX register is loaded with the low-order 32 bits.
15663 if (Subtarget->is64Bit()) {
15664 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15665 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15668 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15669 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15672 SDValue Chain = HI.getValue(1);
15674 if (Opcode == X86ISD::RDTSCP_DAG) {
15675 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15677 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15678 // the ECX register. Add 'ecx' explicitly to the chain.
15679 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15681 // Explicitly store the content of ECX at the location passed in input
15682 // to the 'rdtscp' intrinsic.
15683 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15684 MachinePointerInfo(), false, false, 0);
15687 if (Subtarget->is64Bit()) {
15688 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15689 // the EAX register is loaded with the low-order 32 bits.
15690 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15691 DAG.getConstant(32, DL, MVT::i8));
15692 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15693 Results.push_back(Chain);
15697 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15698 SDValue Ops[] = { LO, HI };
15699 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15700 Results.push_back(Pair);
15701 Results.push_back(Chain);
15704 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15705 SelectionDAG &DAG) {
15706 SmallVector<SDValue, 2> Results;
15708 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15710 return DAG.getMergeValues(Results, DL);
15713 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
15714 SelectionDAG &DAG) {
15715 MachineFunction &MF = DAG.getMachineFunction();
15717 SDValue Chain = Op.getOperand(0);
15719 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15720 MVT VT = TLI.getPointerTy();
15722 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15723 unsigned FrameReg =
15724 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15725 unsigned SPReg = RegInfo->getStackRegister();
15727 // Get incoming EBP.
15728 SDValue IncomingEBP =
15729 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
15731 // Load [EBP-24] into SP.
15733 DAG.getNode(ISD::ADD, dl, VT, IncomingEBP, DAG.getConstant(-24, dl, VT));
15735 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
15736 false, VT.getScalarSizeInBits() / 8);
15737 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
15739 // FIXME: Restore the base pointer in case of stack realignment!
15741 // Adjust EBP to point back to the original frame position.
15742 SDValue NewFP = recoverFramePointer(DAG, MF.getFunction(), IncomingEBP);
15743 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
15747 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15748 SelectionDAG &DAG) {
15749 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15751 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15753 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
15754 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
15759 switch(IntrData->Type) {
15761 llvm_unreachable("Unknown Intrinsic Type");
15765 // Emit the node with the right value type.
15766 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15767 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15769 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15770 // Otherwise return the value from Rand, which is always 0, casted to i32.
15771 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15772 DAG.getConstant(1, dl, Op->getValueType(1)),
15773 DAG.getConstant(X86::COND_B, dl, MVT::i32),
15774 SDValue(Result.getNode(), 1) };
15775 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15776 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15779 // Return { result, isValid, chain }.
15780 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15781 SDValue(Result.getNode(), 2));
15784 //gather(v1, mask, index, base, scale);
15785 SDValue Chain = Op.getOperand(0);
15786 SDValue Src = Op.getOperand(2);
15787 SDValue Base = Op.getOperand(3);
15788 SDValue Index = Op.getOperand(4);
15789 SDValue Mask = Op.getOperand(5);
15790 SDValue Scale = Op.getOperand(6);
15791 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
15795 //scatter(base, mask, index, v1, scale);
15796 SDValue Chain = Op.getOperand(0);
15797 SDValue Base = Op.getOperand(2);
15798 SDValue Mask = Op.getOperand(3);
15799 SDValue Index = Op.getOperand(4);
15800 SDValue Src = Op.getOperand(5);
15801 SDValue Scale = Op.getOperand(6);
15802 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
15806 SDValue Hint = Op.getOperand(6);
15807 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15808 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15809 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15810 SDValue Chain = Op.getOperand(0);
15811 SDValue Mask = Op.getOperand(2);
15812 SDValue Index = Op.getOperand(3);
15813 SDValue Base = Op.getOperand(4);
15814 SDValue Scale = Op.getOperand(5);
15815 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15817 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15819 SmallVector<SDValue, 2> Results;
15820 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
15822 return DAG.getMergeValues(Results, dl);
15824 // Read Performance Monitoring Counters.
15826 SmallVector<SDValue, 2> Results;
15827 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15828 return DAG.getMergeValues(Results, dl);
15830 // XTEST intrinsics.
15832 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15833 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15834 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15835 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
15837 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15838 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15839 Ret, SDValue(InTrans.getNode(), 1));
15843 SmallVector<SDValue, 2> Results;
15844 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15845 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15846 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15847 DAG.getConstant(-1, dl, MVT::i8));
15848 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15849 Op.getOperand(4), GenCF.getValue(1));
15850 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15851 Op.getOperand(5), MachinePointerInfo(),
15853 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15854 DAG.getConstant(X86::COND_B, dl, MVT::i8),
15856 Results.push_back(SetCC);
15857 Results.push_back(Store);
15858 return DAG.getMergeValues(Results, dl);
15860 case COMPRESS_TO_MEM: {
15862 SDValue Mask = Op.getOperand(4);
15863 SDValue DataToCompress = Op.getOperand(3);
15864 SDValue Addr = Op.getOperand(2);
15865 SDValue Chain = Op.getOperand(0);
15867 EVT VT = DataToCompress.getValueType();
15868 if (isAllOnes(Mask)) // return just a store
15869 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15870 MachinePointerInfo(), false, false,
15871 VT.getScalarSizeInBits()/8);
15873 SDValue Compressed =
15874 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
15875 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
15876 return DAG.getStore(Chain, dl, Compressed, Addr,
15877 MachinePointerInfo(), false, false,
15878 VT.getScalarSizeInBits()/8);
15880 case EXPAND_FROM_MEM: {
15882 SDValue Mask = Op.getOperand(4);
15883 SDValue PassThru = Op.getOperand(3);
15884 SDValue Addr = Op.getOperand(2);
15885 SDValue Chain = Op.getOperand(0);
15886 EVT VT = Op.getValueType();
15888 if (isAllOnes(Mask)) // return just a load
15889 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15890 false, VT.getScalarSizeInBits()/8);
15892 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15893 false, false, false,
15894 VT.getScalarSizeInBits()/8);
15896 SDValue Results[] = {
15897 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
15898 Mask, PassThru, Subtarget, DAG), Chain};
15899 return DAG.getMergeValues(Results, dl);
15904 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15905 SelectionDAG &DAG) const {
15906 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15907 MFI->setReturnAddressIsTaken(true);
15909 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15912 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15914 EVT PtrVT = getPointerTy();
15917 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15918 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15919 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
15920 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15921 DAG.getNode(ISD::ADD, dl, PtrVT,
15922 FrameAddr, Offset),
15923 MachinePointerInfo(), false, false, false, 0);
15926 // Just load the return address.
15927 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15928 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15929 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15932 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15933 MachineFunction &MF = DAG.getMachineFunction();
15934 MachineFrameInfo *MFI = MF.getFrameInfo();
15935 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15936 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15937 EVT VT = Op.getValueType();
15939 MFI->setFrameAddressIsTaken(true);
15941 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15942 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15943 // is not possible to crawl up the stack without looking at the unwind codes
15945 int FrameAddrIndex = FuncInfo->getFAIndex();
15946 if (!FrameAddrIndex) {
15947 // Set up a frame object for the return address.
15948 unsigned SlotSize = RegInfo->getSlotSize();
15949 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15950 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
15951 FuncInfo->setFAIndex(FrameAddrIndex);
15953 return DAG.getFrameIndex(FrameAddrIndex, VT);
15956 unsigned FrameReg =
15957 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15958 SDLoc dl(Op); // FIXME probably not meaningful
15959 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15960 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15961 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15962 "Invalid Frame Register!");
15963 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15965 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15966 MachinePointerInfo(),
15967 false, false, false, 0);
15971 // FIXME? Maybe this could be a TableGen attribute on some registers and
15972 // this table could be generated automatically from RegInfo.
15973 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15975 unsigned Reg = StringSwitch<unsigned>(RegName)
15976 .Case("esp", X86::ESP)
15977 .Case("rsp", X86::RSP)
15981 report_fatal_error("Invalid register name global variable");
15984 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15985 SelectionDAG &DAG) const {
15986 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15987 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
15990 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15991 SDValue Chain = Op.getOperand(0);
15992 SDValue Offset = Op.getOperand(1);
15993 SDValue Handler = Op.getOperand(2);
15996 EVT PtrVT = getPointerTy();
15997 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15998 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15999 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16000 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16001 "Invalid Frame Register!");
16002 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16003 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16005 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16006 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
16008 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16009 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16011 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16013 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16014 DAG.getRegister(StoreAddrReg, PtrVT));
16017 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16018 SelectionDAG &DAG) const {
16020 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16021 DAG.getVTList(MVT::i32, MVT::Other),
16022 Op.getOperand(0), Op.getOperand(1));
16025 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16026 SelectionDAG &DAG) const {
16028 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16029 Op.getOperand(0), Op.getOperand(1));
16032 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16033 return Op.getOperand(0);
16036 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16037 SelectionDAG &DAG) const {
16038 SDValue Root = Op.getOperand(0);
16039 SDValue Trmp = Op.getOperand(1); // trampoline
16040 SDValue FPtr = Op.getOperand(2); // nested function
16041 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16044 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16045 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
16047 if (Subtarget->is64Bit()) {
16048 SDValue OutChains[6];
16050 // Large code-model.
16051 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16052 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16054 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16055 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16057 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16059 // Load the pointer to the nested function into R11.
16060 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16061 SDValue Addr = Trmp;
16062 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16063 Addr, MachinePointerInfo(TrmpAddr),
16066 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16067 DAG.getConstant(2, dl, MVT::i64));
16068 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16069 MachinePointerInfo(TrmpAddr, 2),
16072 // Load the 'nest' parameter value into R10.
16073 // R10 is specified in X86CallingConv.td
16074 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16075 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16076 DAG.getConstant(10, dl, MVT::i64));
16077 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16078 Addr, MachinePointerInfo(TrmpAddr, 10),
16081 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16082 DAG.getConstant(12, dl, MVT::i64));
16083 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16084 MachinePointerInfo(TrmpAddr, 12),
16087 // Jump to the nested function.
16088 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16089 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16090 DAG.getConstant(20, dl, MVT::i64));
16091 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16092 Addr, MachinePointerInfo(TrmpAddr, 20),
16095 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16096 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16097 DAG.getConstant(22, dl, MVT::i64));
16098 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
16099 Addr, MachinePointerInfo(TrmpAddr, 22),
16102 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16104 const Function *Func =
16105 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16106 CallingConv::ID CC = Func->getCallingConv();
16111 llvm_unreachable("Unsupported calling convention");
16112 case CallingConv::C:
16113 case CallingConv::X86_StdCall: {
16114 // Pass 'nest' parameter in ECX.
16115 // Must be kept in sync with X86CallingConv.td
16116 NestReg = X86::ECX;
16118 // Check that ECX wasn't needed by an 'inreg' parameter.
16119 FunctionType *FTy = Func->getFunctionType();
16120 const AttributeSet &Attrs = Func->getAttributes();
16122 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16123 unsigned InRegCount = 0;
16126 for (FunctionType::param_iterator I = FTy->param_begin(),
16127 E = FTy->param_end(); I != E; ++I, ++Idx)
16128 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16129 // FIXME: should only count parameters that are lowered to integers.
16130 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16132 if (InRegCount > 2) {
16133 report_fatal_error("Nest register in use - reduce number of inreg"
16139 case CallingConv::X86_FastCall:
16140 case CallingConv::X86_ThisCall:
16141 case CallingConv::Fast:
16142 // Pass 'nest' parameter in EAX.
16143 // Must be kept in sync with X86CallingConv.td
16144 NestReg = X86::EAX;
16148 SDValue OutChains[4];
16149 SDValue Addr, Disp;
16151 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16152 DAG.getConstant(10, dl, MVT::i32));
16153 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16155 // This is storing the opcode for MOV32ri.
16156 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16157 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16158 OutChains[0] = DAG.getStore(Root, dl,
16159 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16160 Trmp, MachinePointerInfo(TrmpAddr),
16163 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16164 DAG.getConstant(1, dl, MVT::i32));
16165 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16166 MachinePointerInfo(TrmpAddr, 1),
16169 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16170 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16171 DAG.getConstant(5, dl, MVT::i32));
16172 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16173 Addr, MachinePointerInfo(TrmpAddr, 5),
16176 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16177 DAG.getConstant(6, dl, MVT::i32));
16178 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16179 MachinePointerInfo(TrmpAddr, 6),
16182 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16186 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16187 SelectionDAG &DAG) const {
16189 The rounding mode is in bits 11:10 of FPSR, and has the following
16191 00 Round to nearest
16196 FLT_ROUNDS, on the other hand, expects the following:
16203 To perform the conversion, we do:
16204 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16207 MachineFunction &MF = DAG.getMachineFunction();
16208 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16209 unsigned StackAlignment = TFI.getStackAlignment();
16210 MVT VT = Op.getSimpleValueType();
16213 // Save FP Control Word to stack slot
16214 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16215 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16217 MachineMemOperand *MMO =
16218 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16219 MachineMemOperand::MOStore, 2, 2);
16221 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16222 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16223 DAG.getVTList(MVT::Other),
16224 Ops, MVT::i16, MMO);
16226 // Load FP Control Word from stack slot
16227 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16228 MachinePointerInfo(), false, false, false, 0);
16230 // Transform as necessary
16232 DAG.getNode(ISD::SRL, DL, MVT::i16,
16233 DAG.getNode(ISD::AND, DL, MVT::i16,
16234 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16235 DAG.getConstant(11, DL, MVT::i8));
16237 DAG.getNode(ISD::SRL, DL, MVT::i16,
16238 DAG.getNode(ISD::AND, DL, MVT::i16,
16239 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16240 DAG.getConstant(9, DL, MVT::i8));
16243 DAG.getNode(ISD::AND, DL, MVT::i16,
16244 DAG.getNode(ISD::ADD, DL, MVT::i16,
16245 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16246 DAG.getConstant(1, DL, MVT::i16)),
16247 DAG.getConstant(3, DL, MVT::i16));
16249 return DAG.getNode((VT.getSizeInBits() < 16 ?
16250 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16253 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16254 MVT VT = Op.getSimpleValueType();
16256 unsigned NumBits = VT.getSizeInBits();
16259 Op = Op.getOperand(0);
16260 if (VT == MVT::i8) {
16261 // Zero extend to i32 since there is not an i8 bsr.
16263 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16266 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16267 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16268 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16270 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16273 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16274 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16277 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16279 // Finally xor with NumBits-1.
16280 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16281 DAG.getConstant(NumBits - 1, dl, OpVT));
16284 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16288 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16289 MVT VT = Op.getSimpleValueType();
16291 unsigned NumBits = VT.getSizeInBits();
16294 Op = Op.getOperand(0);
16295 if (VT == MVT::i8) {
16296 // Zero extend to i32 since there is not an i8 bsr.
16298 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16301 // Issue a bsr (scan bits in reverse).
16302 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16303 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16305 // And xor with NumBits-1.
16306 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16307 DAG.getConstant(NumBits - 1, dl, OpVT));
16310 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16314 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16315 MVT VT = Op.getSimpleValueType();
16316 unsigned NumBits = VT.getSizeInBits();
16318 Op = Op.getOperand(0);
16320 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16321 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16322 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16324 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16327 DAG.getConstant(NumBits, dl, VT),
16328 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16331 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16334 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16335 // ones, and then concatenate the result back.
16336 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16337 MVT VT = Op.getSimpleValueType();
16339 assert(VT.is256BitVector() && VT.isInteger() &&
16340 "Unsupported value type for operation");
16342 unsigned NumElems = VT.getVectorNumElements();
16345 // Extract the LHS vectors
16346 SDValue LHS = Op.getOperand(0);
16347 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16348 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16350 // Extract the RHS vectors
16351 SDValue RHS = Op.getOperand(1);
16352 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16353 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16355 MVT EltVT = VT.getVectorElementType();
16356 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16358 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16359 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16360 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16363 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16364 if (Op.getValueType() == MVT::i1)
16365 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16366 Op.getOperand(0), Op.getOperand(1));
16367 assert(Op.getSimpleValueType().is256BitVector() &&
16368 Op.getSimpleValueType().isInteger() &&
16369 "Only handle AVX 256-bit vector integer operation");
16370 return Lower256IntArith(Op, DAG);
16373 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16374 if (Op.getValueType() == MVT::i1)
16375 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16376 Op.getOperand(0), Op.getOperand(1));
16377 assert(Op.getSimpleValueType().is256BitVector() &&
16378 Op.getSimpleValueType().isInteger() &&
16379 "Only handle AVX 256-bit vector integer operation");
16380 return Lower256IntArith(Op, DAG);
16383 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16384 SelectionDAG &DAG) {
16386 MVT VT = Op.getSimpleValueType();
16389 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16391 // Decompose 256-bit ops into smaller 128-bit ops.
16392 if (VT.is256BitVector() && !Subtarget->hasInt256())
16393 return Lower256IntArith(Op, DAG);
16395 SDValue A = Op.getOperand(0);
16396 SDValue B = Op.getOperand(1);
16398 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16399 // pairs, multiply and truncate.
16400 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16401 if (Subtarget->hasInt256()) {
16402 if (VT == MVT::v32i8) {
16403 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16404 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16405 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16406 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16407 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16408 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16409 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16410 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16411 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16412 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16415 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16416 return DAG.getNode(
16417 ISD::TRUNCATE, dl, VT,
16418 DAG.getNode(ISD::MUL, dl, ExVT,
16419 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16420 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16423 assert(VT == MVT::v16i8 &&
16424 "Pre-AVX2 support only supports v16i8 multiplication");
16425 MVT ExVT = MVT::v8i16;
16427 // Extract the lo parts and sign extend to i16
16429 if (Subtarget->hasSSE41()) {
16430 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16431 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16433 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16434 -1, 4, -1, 5, -1, 6, -1, 7};
16435 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16436 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16437 ALo = DAG.getBitcast(ExVT, ALo);
16438 BLo = DAG.getBitcast(ExVT, BLo);
16439 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16440 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16443 // Extract the hi parts and sign extend to i16
16445 if (Subtarget->hasSSE41()) {
16446 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16447 -1, -1, -1, -1, -1, -1, -1, -1};
16448 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16449 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16450 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16451 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16453 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16454 -1, 12, -1, 13, -1, 14, -1, 15};
16455 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16456 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16457 AHi = DAG.getBitcast(ExVT, AHi);
16458 BHi = DAG.getBitcast(ExVT, BHi);
16459 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16460 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16463 // Multiply, mask the lower 8bits of the lo/hi results and pack
16464 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16465 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16466 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16467 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16468 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16471 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16472 if (VT == MVT::v4i32) {
16473 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16474 "Should not custom lower when pmuldq is available!");
16476 // Extract the odd parts.
16477 static const int UnpackMask[] = { 1, -1, 3, -1 };
16478 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16479 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16481 // Multiply the even parts.
16482 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16483 // Now multiply odd parts.
16484 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16486 Evens = DAG.getBitcast(VT, Evens);
16487 Odds = DAG.getBitcast(VT, Odds);
16489 // Merge the two vectors back together with a shuffle. This expands into 2
16491 static const int ShufMask[] = { 0, 4, 2, 6 };
16492 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16495 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16496 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16498 // Ahi = psrlqi(a, 32);
16499 // Bhi = psrlqi(b, 32);
16501 // AloBlo = pmuludq(a, b);
16502 // AloBhi = pmuludq(a, Bhi);
16503 // AhiBlo = pmuludq(Ahi, b);
16505 // AloBhi = psllqi(AloBhi, 32);
16506 // AhiBlo = psllqi(AhiBlo, 32);
16507 // return AloBlo + AloBhi + AhiBlo;
16509 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16510 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16512 SDValue AhiBlo = Ahi;
16513 SDValue AloBhi = Bhi;
16514 // Bit cast to 32-bit vectors for MULUDQ
16515 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16516 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16517 A = DAG.getBitcast(MulVT, A);
16518 B = DAG.getBitcast(MulVT, B);
16519 Ahi = DAG.getBitcast(MulVT, Ahi);
16520 Bhi = DAG.getBitcast(MulVT, Bhi);
16522 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16523 // After shifting right const values the result may be all-zero.
16524 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
16525 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16526 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16528 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
16529 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16530 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16533 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16534 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16537 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16538 assert(Subtarget->isTargetWin64() && "Unexpected target");
16539 EVT VT = Op.getValueType();
16540 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16541 "Unexpected return type for lowering");
16545 switch (Op->getOpcode()) {
16546 default: llvm_unreachable("Unexpected request for libcall!");
16547 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16548 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16549 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16550 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16551 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16552 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16556 SDValue InChain = DAG.getEntryNode();
16558 TargetLowering::ArgListTy Args;
16559 TargetLowering::ArgListEntry Entry;
16560 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16561 EVT ArgVT = Op->getOperand(i).getValueType();
16562 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16563 "Unexpected argument type for lowering");
16564 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16565 Entry.Node = StackPtr;
16566 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16568 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16569 Entry.Ty = PointerType::get(ArgTy,0);
16570 Entry.isSExt = false;
16571 Entry.isZExt = false;
16572 Args.push_back(Entry);
16575 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16578 TargetLowering::CallLoweringInfo CLI(DAG);
16579 CLI.setDebugLoc(dl).setChain(InChain)
16580 .setCallee(getLibcallCallingConv(LC),
16581 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16582 Callee, std::move(Args), 0)
16583 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16585 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16586 return DAG.getBitcast(VT, CallInfo.first);
16589 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16590 SelectionDAG &DAG) {
16591 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16592 EVT VT = Op0.getValueType();
16595 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16596 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16598 // PMULxD operations multiply each even value (starting at 0) of LHS with
16599 // the related value of RHS and produce a widen result.
16600 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16601 // => <2 x i64> <ae|cg>
16603 // In other word, to have all the results, we need to perform two PMULxD:
16604 // 1. one with the even values.
16605 // 2. one with the odd values.
16606 // To achieve #2, with need to place the odd values at an even position.
16608 // Place the odd value at an even position (basically, shift all values 1
16609 // step to the left):
16610 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16611 // <a|b|c|d> => <b|undef|d|undef>
16612 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16613 // <e|f|g|h> => <f|undef|h|undef>
16614 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16616 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16618 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16619 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16621 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16622 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16623 // => <2 x i64> <ae|cg>
16624 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16625 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16626 // => <2 x i64> <bf|dh>
16627 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16629 // Shuffle it back into the right order.
16630 SDValue Highs, Lows;
16631 if (VT == MVT::v8i32) {
16632 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16633 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16634 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16635 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16637 const int HighMask[] = {1, 5, 3, 7};
16638 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16639 const int LowMask[] = {0, 4, 2, 6};
16640 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16643 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16644 // unsigned multiply.
16645 if (IsSigned && !Subtarget->hasSSE41()) {
16647 DAG.getConstant(31, dl,
16648 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16649 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16650 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16651 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16652 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16654 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16655 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16658 // The first result of MUL_LOHI is actually the low value, followed by the
16660 SDValue Ops[] = {Lows, Highs};
16661 return DAG.getMergeValues(Ops, dl);
16664 // Return true if the requred (according to Opcode) shift-imm form is natively
16665 // supported by the Subtarget
16666 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16668 if (VT.getScalarSizeInBits() < 16)
16671 if (VT.is512BitVector() &&
16672 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16675 bool LShift = VT.is128BitVector() ||
16676 (VT.is256BitVector() && Subtarget->hasInt256());
16678 bool AShift = LShift && (Subtarget->hasVLX() ||
16679 (VT != MVT::v2i64 && VT != MVT::v4i64));
16680 return (Opcode == ISD::SRA) ? AShift : LShift;
16683 // The shift amount is a variable, but it is the same for all vector lanes.
16684 // These instrcutions are defined together with shift-immediate.
16686 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16688 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16691 // Return true if the requred (according to Opcode) variable-shift form is
16692 // natively supported by the Subtarget
16693 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16696 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16699 // vXi16 supported only on AVX-512, BWI
16700 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16703 if (VT.is512BitVector() || Subtarget->hasVLX())
16706 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16707 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16708 return (Opcode == ISD::SRA) ? AShift : LShift;
16711 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16712 const X86Subtarget *Subtarget) {
16713 MVT VT = Op.getSimpleValueType();
16715 SDValue R = Op.getOperand(0);
16716 SDValue Amt = Op.getOperand(1);
16718 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16719 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16721 // Optimize shl/srl/sra with constant shift amount.
16722 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16723 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16724 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16726 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
16727 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16729 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16730 unsigned NumElts = VT.getVectorNumElements();
16731 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16733 if (Op.getOpcode() == ISD::SHL) {
16734 // Simple i8 add case
16736 return DAG.getNode(ISD::ADD, dl, VT, R, R);
16738 // Make a large shift.
16739 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16741 SHL = DAG.getBitcast(VT, SHL);
16742 // Zero out the rightmost bits.
16743 SmallVector<SDValue, 32> V(
16744 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16745 return DAG.getNode(ISD::AND, dl, VT, SHL,
16746 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16748 if (Op.getOpcode() == ISD::SRL) {
16749 // Make a large shift.
16750 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16752 SRL = DAG.getBitcast(VT, SRL);
16753 // Zero out the leftmost bits.
16754 SmallVector<SDValue, 32> V(
16755 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16756 return DAG.getNode(ISD::AND, dl, VT, SRL,
16757 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16759 if (Op.getOpcode() == ISD::SRA) {
16760 if (ShiftAmt == 7) {
16761 // R s>> 7 === R s< 0
16762 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16763 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16766 // R s>> a === ((R u>> a) ^ m) - m
16767 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16768 SmallVector<SDValue, 32> V(NumElts,
16769 DAG.getConstant(128 >> ShiftAmt, dl,
16771 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16772 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16773 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16776 llvm_unreachable("Unknown shift opcode.");
16781 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16782 if (!Subtarget->is64Bit() &&
16783 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16784 Amt.getOpcode() == ISD::BITCAST &&
16785 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16786 Amt = Amt.getOperand(0);
16787 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16788 VT.getVectorNumElements();
16789 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16790 uint64_t ShiftAmt = 0;
16791 for (unsigned i = 0; i != Ratio; ++i) {
16792 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16796 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16798 // Check remaining shift amounts.
16799 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16800 uint64_t ShAmt = 0;
16801 for (unsigned j = 0; j != Ratio; ++j) {
16802 ConstantSDNode *C =
16803 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16807 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16809 if (ShAmt != ShiftAmt)
16812 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16818 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16819 const X86Subtarget* Subtarget) {
16820 MVT VT = Op.getSimpleValueType();
16822 SDValue R = Op.getOperand(0);
16823 SDValue Amt = Op.getOperand(1);
16825 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16826 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16828 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
16829 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
16831 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
16833 EVT EltVT = VT.getVectorElementType();
16835 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16836 // Check if this build_vector node is doing a splat.
16837 // If so, then set BaseShAmt equal to the splat value.
16838 BaseShAmt = BV->getSplatValue();
16839 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16840 BaseShAmt = SDValue();
16842 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16843 Amt = Amt.getOperand(0);
16845 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16846 if (SVN && SVN->isSplat()) {
16847 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16848 SDValue InVec = Amt.getOperand(0);
16849 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16850 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16851 "Unexpected shuffle index found!");
16852 BaseShAmt = InVec.getOperand(SplatIdx);
16853 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16854 if (ConstantSDNode *C =
16855 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16856 if (C->getZExtValue() == SplatIdx)
16857 BaseShAmt = InVec.getOperand(1);
16862 // Avoid introducing an extract element from a shuffle.
16863 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16864 DAG.getIntPtrConstant(SplatIdx, dl));
16868 if (BaseShAmt.getNode()) {
16869 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16870 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16871 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16872 else if (EltVT.bitsLT(MVT::i32))
16873 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16875 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
16879 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16880 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
16881 Amt.getOpcode() == ISD::BITCAST &&
16882 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16883 Amt = Amt.getOperand(0);
16884 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16885 VT.getVectorNumElements();
16886 std::vector<SDValue> Vals(Ratio);
16887 for (unsigned i = 0; i != Ratio; ++i)
16888 Vals[i] = Amt.getOperand(i);
16889 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16890 for (unsigned j = 0; j != Ratio; ++j)
16891 if (Vals[j] != Amt.getOperand(i + j))
16894 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
16899 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16900 SelectionDAG &DAG) {
16901 MVT VT = Op.getSimpleValueType();
16903 SDValue R = Op.getOperand(0);
16904 SDValue Amt = Op.getOperand(1);
16906 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16907 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16909 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16912 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16915 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
16918 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16919 // shifts per-lane and then shuffle the partial results back together.
16920 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16921 // Splat the shift amounts so the scalar shifts above will catch it.
16922 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16923 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16924 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16925 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16926 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16929 // If possible, lower this packed shift into a vector multiply instead of
16930 // expanding it into a sequence of scalar shifts.
16931 // Do this only if the vector shift count is a constant build_vector.
16932 if (Op.getOpcode() == ISD::SHL &&
16933 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16934 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16935 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16936 SmallVector<SDValue, 8> Elts;
16937 EVT SVT = VT.getScalarType();
16938 unsigned SVTBits = SVT.getSizeInBits();
16939 const APInt &One = APInt(SVTBits, 1);
16940 unsigned NumElems = VT.getVectorNumElements();
16942 for (unsigned i=0; i !=NumElems; ++i) {
16943 SDValue Op = Amt->getOperand(i);
16944 if (Op->getOpcode() == ISD::UNDEF) {
16945 Elts.push_back(Op);
16949 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16950 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16951 uint64_t ShAmt = C.getZExtValue();
16952 if (ShAmt >= SVTBits) {
16953 Elts.push_back(DAG.getUNDEF(SVT));
16956 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
16958 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16959 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16962 // Lower SHL with variable shift amount.
16963 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16964 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
16966 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
16967 DAG.getConstant(0x3f800000U, dl, VT));
16968 Op = DAG.getBitcast(MVT::v4f32, Op);
16969 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16970 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16973 // If possible, lower this shift as a sequence of two shifts by
16974 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16976 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16978 // Could be rewritten as:
16979 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16981 // The advantage is that the two shifts from the example would be
16982 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16983 // the vector shift into four scalar shifts plus four pairs of vector
16985 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16986 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16987 unsigned TargetOpcode = X86ISD::MOVSS;
16988 bool CanBeSimplified;
16989 // The splat value for the first packed shift (the 'X' from the example).
16990 SDValue Amt1 = Amt->getOperand(0);
16991 // The splat value for the second packed shift (the 'Y' from the example).
16992 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16993 Amt->getOperand(2);
16995 // See if it is possible to replace this node with a sequence of
16996 // two shifts followed by a MOVSS/MOVSD
16997 if (VT == MVT::v4i32) {
16998 // Check if it is legal to use a MOVSS.
16999 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17000 Amt2 == Amt->getOperand(3);
17001 if (!CanBeSimplified) {
17002 // Otherwise, check if we can still simplify this node using a MOVSD.
17003 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17004 Amt->getOperand(2) == Amt->getOperand(3);
17005 TargetOpcode = X86ISD::MOVSD;
17006 Amt2 = Amt->getOperand(2);
17009 // Do similar checks for the case where the machine value type
17011 CanBeSimplified = Amt1 == Amt->getOperand(1);
17012 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17013 CanBeSimplified = Amt2 == Amt->getOperand(i);
17015 if (!CanBeSimplified) {
17016 TargetOpcode = X86ISD::MOVSD;
17017 CanBeSimplified = true;
17018 Amt2 = Amt->getOperand(4);
17019 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17020 CanBeSimplified = Amt1 == Amt->getOperand(i);
17021 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17022 CanBeSimplified = Amt2 == Amt->getOperand(j);
17026 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17027 isa<ConstantSDNode>(Amt2)) {
17028 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17029 EVT CastVT = MVT::v4i32;
17031 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
17032 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17034 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
17035 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17036 if (TargetOpcode == X86ISD::MOVSD)
17037 CastVT = MVT::v2i64;
17038 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
17039 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
17040 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17042 return DAG.getBitcast(VT, Result);
17046 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
17047 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
17048 unsigned ShiftOpcode = Op->getOpcode();
17050 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
17051 // On SSE41 targets we make use of the fact that VSELECT lowers
17052 // to PBLENDVB which selects bytes based just on the sign bit.
17053 if (Subtarget->hasSSE41()) {
17054 V0 = DAG.getBitcast(VT, V0);
17055 V1 = DAG.getBitcast(VT, V1);
17056 Sel = DAG.getBitcast(VT, Sel);
17057 return DAG.getBitcast(SelVT,
17058 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
17060 // On pre-SSE41 targets we test for the sign bit by comparing to
17061 // zero - a negative value will set all bits of the lanes to true
17062 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
17063 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
17064 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
17065 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
17068 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
17069 // We can safely do this using i16 shifts as we're only interested in
17070 // the 3 lower bits of each byte.
17071 Amt = DAG.getBitcast(ExtVT, Amt);
17072 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
17073 Amt = DAG.getBitcast(VT, Amt);
17075 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
17076 // r = VSELECT(r, shift(r, 4), a);
17078 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17079 R = SignBitSelect(VT, Amt, M, R);
17082 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17084 // r = VSELECT(r, shift(r, 2), a);
17085 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17086 R = SignBitSelect(VT, Amt, M, R);
17089 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17091 // return VSELECT(r, shift(r, 1), a);
17092 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17093 R = SignBitSelect(VT, Amt, M, R);
17097 if (Op->getOpcode() == ISD::SRA) {
17098 // For SRA we need to unpack each byte to the higher byte of a i16 vector
17099 // so we can correctly sign extend. We don't care what happens to the
17101 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
17102 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
17103 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
17104 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
17105 ALo = DAG.getBitcast(ExtVT, ALo);
17106 AHi = DAG.getBitcast(ExtVT, AHi);
17107 RLo = DAG.getBitcast(ExtVT, RLo);
17108 RHi = DAG.getBitcast(ExtVT, RHi);
17110 // r = VSELECT(r, shift(r, 4), a);
17111 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17112 DAG.getConstant(4, dl, ExtVT));
17113 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17114 DAG.getConstant(4, dl, ExtVT));
17115 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17116 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17119 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17120 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17122 // r = VSELECT(r, shift(r, 2), a);
17123 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17124 DAG.getConstant(2, dl, ExtVT));
17125 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17126 DAG.getConstant(2, dl, ExtVT));
17127 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17128 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17131 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17132 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17134 // r = VSELECT(r, shift(r, 1), a);
17135 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17136 DAG.getConstant(1, dl, ExtVT));
17137 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17138 DAG.getConstant(1, dl, ExtVT));
17139 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17140 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17142 // Logical shift the result back to the lower byte, leaving a zero upper
17144 // meaning that we can safely pack with PACKUSWB.
17146 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
17148 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
17149 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17153 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17154 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17155 // solution better.
17156 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17157 MVT ExtVT = MVT::v8i32;
17159 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17160 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
17161 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
17162 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17163 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
17166 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
17167 MVT ExtVT = MVT::v8i32;
17168 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
17169 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
17170 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
17171 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
17172 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
17173 ALo = DAG.getBitcast(ExtVT, ALo);
17174 AHi = DAG.getBitcast(ExtVT, AHi);
17175 RLo = DAG.getBitcast(ExtVT, RLo);
17176 RHi = DAG.getBitcast(ExtVT, RHi);
17177 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
17178 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
17179 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
17180 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
17181 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
17184 if (VT == MVT::v8i16) {
17185 unsigned ShiftOpcode = Op->getOpcode();
17187 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
17188 // On SSE41 targets we make use of the fact that VSELECT lowers
17189 // to PBLENDVB which selects bytes based just on the sign bit.
17190 if (Subtarget->hasSSE41()) {
17191 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
17192 V0 = DAG.getBitcast(ExtVT, V0);
17193 V1 = DAG.getBitcast(ExtVT, V1);
17194 Sel = DAG.getBitcast(ExtVT, Sel);
17195 return DAG.getBitcast(
17196 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
17198 // On pre-SSE41 targets we splat the sign bit - a negative value will
17199 // set all bits of the lanes to true and VSELECT uses that in
17200 // its OR(AND(V0,C),AND(V1,~C)) lowering.
17202 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
17203 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
17206 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
17207 if (Subtarget->hasSSE41()) {
17208 // On SSE41 targets we need to replicate the shift mask in both
17209 // bytes for PBLENDVB.
17212 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
17213 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
17215 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
17218 // r = VSELECT(r, shift(r, 8), a);
17219 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
17220 R = SignBitSelect(Amt, M, R);
17223 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17225 // r = VSELECT(r, shift(r, 4), a);
17226 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17227 R = SignBitSelect(Amt, M, R);
17230 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17232 // r = VSELECT(r, shift(r, 2), a);
17233 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17234 R = SignBitSelect(Amt, M, R);
17237 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17239 // return VSELECT(r, shift(r, 1), a);
17240 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17241 R = SignBitSelect(Amt, M, R);
17245 // Decompose 256-bit shifts into smaller 128-bit shifts.
17246 if (VT.is256BitVector()) {
17247 unsigned NumElems = VT.getVectorNumElements();
17248 MVT EltVT = VT.getVectorElementType();
17249 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17251 // Extract the two vectors
17252 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17253 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17255 // Recreate the shift amount vectors
17256 SDValue Amt1, Amt2;
17257 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17258 // Constant shift amount
17259 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
17260 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
17261 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
17263 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17264 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17266 // Variable shift amount
17267 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17268 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17271 // Issue new vector shifts for the smaller types
17272 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17273 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17275 // Concatenate the result back
17276 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17282 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17283 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17284 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17285 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17286 // has only one use.
17287 SDNode *N = Op.getNode();
17288 SDValue LHS = N->getOperand(0);
17289 SDValue RHS = N->getOperand(1);
17290 unsigned BaseOp = 0;
17293 switch (Op.getOpcode()) {
17294 default: llvm_unreachable("Unknown ovf instruction!");
17296 // A subtract of one will be selected as a INC. Note that INC doesn't
17297 // set CF, so we can't do this for UADDO.
17298 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17300 BaseOp = X86ISD::INC;
17301 Cond = X86::COND_O;
17304 BaseOp = X86ISD::ADD;
17305 Cond = X86::COND_O;
17308 BaseOp = X86ISD::ADD;
17309 Cond = X86::COND_B;
17312 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17313 // set CF, so we can't do this for USUBO.
17314 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17316 BaseOp = X86ISD::DEC;
17317 Cond = X86::COND_O;
17320 BaseOp = X86ISD::SUB;
17321 Cond = X86::COND_O;
17324 BaseOp = X86ISD::SUB;
17325 Cond = X86::COND_B;
17328 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
17329 Cond = X86::COND_O;
17331 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17332 if (N->getValueType(0) == MVT::i8) {
17333 BaseOp = X86ISD::UMUL8;
17334 Cond = X86::COND_O;
17337 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17339 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17342 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17343 DAG.getConstant(X86::COND_O, DL, MVT::i32),
17344 SDValue(Sum.getNode(), 2));
17346 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17350 // Also sets EFLAGS.
17351 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17352 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17355 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17356 DAG.getConstant(Cond, DL, MVT::i32),
17357 SDValue(Sum.getNode(), 1));
17359 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17362 /// Returns true if the operand type is exactly twice the native width, and
17363 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17364 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17365 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17366 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17367 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17370 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17371 else if (OpWidth == 128)
17372 return Subtarget->hasCmpxchg16b();
17377 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17378 return needsCmpXchgNb(SI->getValueOperand()->getType());
17381 // Note: this turns large loads into lock cmpxchg8b/16b.
17382 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17383 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17384 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17385 return needsCmpXchgNb(PTy->getElementType());
17388 TargetLoweringBase::AtomicRMWExpansionKind
17389 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17390 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17391 const Type *MemType = AI->getType();
17393 // If the operand is too big, we must see if cmpxchg8/16b is available
17394 // and default to library calls otherwise.
17395 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
17396 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
17397 : AtomicRMWExpansionKind::None;
17400 AtomicRMWInst::BinOp Op = AI->getOperation();
17403 llvm_unreachable("Unknown atomic operation");
17404 case AtomicRMWInst::Xchg:
17405 case AtomicRMWInst::Add:
17406 case AtomicRMWInst::Sub:
17407 // It's better to use xadd, xsub or xchg for these in all cases.
17408 return AtomicRMWExpansionKind::None;
17409 case AtomicRMWInst::Or:
17410 case AtomicRMWInst::And:
17411 case AtomicRMWInst::Xor:
17412 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17413 // prefix to a normal instruction for these operations.
17414 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
17415 : AtomicRMWExpansionKind::None;
17416 case AtomicRMWInst::Nand:
17417 case AtomicRMWInst::Max:
17418 case AtomicRMWInst::Min:
17419 case AtomicRMWInst::UMax:
17420 case AtomicRMWInst::UMin:
17421 // These always require a non-trivial set of data operations on x86. We must
17422 // use a cmpxchg loop.
17423 return AtomicRMWExpansionKind::CmpXChg;
17427 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17428 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17429 // no-sse2). There isn't any reason to disable it if the target processor
17431 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17435 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17436 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17437 const Type *MemType = AI->getType();
17438 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17439 // there is no benefit in turning such RMWs into loads, and it is actually
17440 // harmful as it introduces a mfence.
17441 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17444 auto Builder = IRBuilder<>(AI);
17445 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17446 auto SynchScope = AI->getSynchScope();
17447 // We must restrict the ordering to avoid generating loads with Release or
17448 // ReleaseAcquire orderings.
17449 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17450 auto Ptr = AI->getPointerOperand();
17452 // Before the load we need a fence. Here is an example lifted from
17453 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17456 // x.store(1, relaxed);
17457 // r1 = y.fetch_add(0, release);
17459 // y.fetch_add(42, acquire);
17460 // r2 = x.load(relaxed);
17461 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17462 // lowered to just a load without a fence. A mfence flushes the store buffer,
17463 // making the optimization clearly correct.
17464 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17465 // otherwise, we might be able to be more agressive on relaxed idempotent
17466 // rmw. In practice, they do not look useful, so we don't try to be
17467 // especially clever.
17468 if (SynchScope == SingleThread)
17469 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17470 // the IR level, so we must wrap it in an intrinsic.
17473 if (!hasMFENCE(*Subtarget))
17474 // FIXME: it might make sense to use a locked operation here but on a
17475 // different cache-line to prevent cache-line bouncing. In practice it
17476 // is probably a small win, and x86 processors without mfence are rare
17477 // enough that we do not bother.
17481 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
17482 Builder.CreateCall(MFence, {});
17484 // Finally we can emit the atomic load.
17485 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17486 AI->getType()->getPrimitiveSizeInBits());
17487 Loaded->setAtomic(Order, SynchScope);
17488 AI->replaceAllUsesWith(Loaded);
17489 AI->eraseFromParent();
17493 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17494 SelectionDAG &DAG) {
17496 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17497 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17498 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17499 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17501 // The only fence that needs an instruction is a sequentially-consistent
17502 // cross-thread fence.
17503 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17504 if (hasMFENCE(*Subtarget))
17505 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17507 SDValue Chain = Op.getOperand(0);
17508 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17510 DAG.getRegister(X86::ESP, MVT::i32), // Base
17511 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17512 DAG.getRegister(0, MVT::i32), // Index
17513 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17514 DAG.getRegister(0, MVT::i32), // Segment.
17518 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17519 return SDValue(Res, 0);
17522 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17523 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17526 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17527 SelectionDAG &DAG) {
17528 MVT T = Op.getSimpleValueType();
17532 switch(T.SimpleTy) {
17533 default: llvm_unreachable("Invalid value type!");
17534 case MVT::i8: Reg = X86::AL; size = 1; break;
17535 case MVT::i16: Reg = X86::AX; size = 2; break;
17536 case MVT::i32: Reg = X86::EAX; size = 4; break;
17538 assert(Subtarget->is64Bit() && "Node not type legal!");
17539 Reg = X86::RAX; size = 8;
17542 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17543 Op.getOperand(2), SDValue());
17544 SDValue Ops[] = { cpIn.getValue(0),
17547 DAG.getTargetConstant(size, DL, MVT::i8),
17548 cpIn.getValue(1) };
17549 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17550 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17551 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17555 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17556 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17557 MVT::i32, cpOut.getValue(2));
17558 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17559 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17562 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17563 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17564 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17568 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17569 SelectionDAG &DAG) {
17570 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17571 MVT DstVT = Op.getSimpleValueType();
17573 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17574 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17575 if (DstVT != MVT::f64)
17576 // This conversion needs to be expanded.
17579 SDValue InVec = Op->getOperand(0);
17581 unsigned NumElts = SrcVT.getVectorNumElements();
17582 EVT SVT = SrcVT.getVectorElementType();
17584 // Widen the vector in input in the case of MVT::v2i32.
17585 // Example: from MVT::v2i32 to MVT::v4i32.
17586 SmallVector<SDValue, 16> Elts;
17587 for (unsigned i = 0, e = NumElts; i != e; ++i)
17588 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17589 DAG.getIntPtrConstant(i, dl)));
17591 // Explicitly mark the extra elements as Undef.
17592 Elts.append(NumElts, DAG.getUNDEF(SVT));
17594 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17595 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17596 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
17597 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17598 DAG.getIntPtrConstant(0, dl));
17601 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17602 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17603 assert((DstVT == MVT::i64 ||
17604 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17605 "Unexpected custom BITCAST");
17606 // i64 <=> MMX conversions are Legal.
17607 if (SrcVT==MVT::i64 && DstVT.isVector())
17609 if (DstVT==MVT::i64 && SrcVT.isVector())
17611 // MMX <=> MMX conversions are Legal.
17612 if (SrcVT.isVector() && DstVT.isVector())
17614 // All other conversions need to be expanded.
17618 /// Compute the horizontal sum of bytes in V for the elements of VT.
17620 /// Requires V to be a byte vector and VT to be an integer vector type with
17621 /// wider elements than V's type. The width of the elements of VT determines
17622 /// how many bytes of V are summed horizontally to produce each element of the
17624 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
17625 const X86Subtarget *Subtarget,
17626 SelectionDAG &DAG) {
17628 MVT ByteVecVT = V.getSimpleValueType();
17629 MVT EltVT = VT.getVectorElementType();
17630 int NumElts = VT.getVectorNumElements();
17631 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
17632 "Expected value to have byte element type.");
17633 assert(EltVT != MVT::i8 &&
17634 "Horizontal byte sum only makes sense for wider elements!");
17635 unsigned VecSize = VT.getSizeInBits();
17636 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
17638 // PSADBW instruction horizontally add all bytes and leave the result in i64
17639 // chunks, thus directly computes the pop count for v2i64 and v4i64.
17640 if (EltVT == MVT::i64) {
17641 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17642 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
17643 return DAG.getBitcast(VT, V);
17646 if (EltVT == MVT::i32) {
17647 // We unpack the low half and high half into i32s interleaved with zeros so
17648 // that we can use PSADBW to horizontally sum them. The most useful part of
17649 // this is that it lines up the results of two PSADBW instructions to be
17650 // two v2i64 vectors which concatenated are the 4 population counts. We can
17651 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
17652 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
17653 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
17654 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
17656 // Do the horizontal sums into two v2i64s.
17657 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17658 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17659 DAG.getBitcast(ByteVecVT, Low), Zeros);
17660 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17661 DAG.getBitcast(ByteVecVT, High), Zeros);
17663 // Merge them together.
17664 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
17665 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
17666 DAG.getBitcast(ShortVecVT, Low),
17667 DAG.getBitcast(ShortVecVT, High));
17669 return DAG.getBitcast(VT, V);
17672 // The only element type left is i16.
17673 assert(EltVT == MVT::i16 && "Unknown how to handle type");
17675 // To obtain pop count for each i16 element starting from the pop count for
17676 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
17677 // right by 8. It is important to shift as i16s as i8 vector shift isn't
17678 // directly supported.
17679 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
17680 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
17681 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17682 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
17683 DAG.getBitcast(ByteVecVT, V));
17684 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17687 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
17688 const X86Subtarget *Subtarget,
17689 SelectionDAG &DAG) {
17690 MVT VT = Op.getSimpleValueType();
17691 MVT EltVT = VT.getVectorElementType();
17692 unsigned VecSize = VT.getSizeInBits();
17694 // Implement a lookup table in register by using an algorithm based on:
17695 // http://wm.ite.pl/articles/sse-popcount.html
17697 // The general idea is that every lower byte nibble in the input vector is an
17698 // index into a in-register pre-computed pop count table. We then split up the
17699 // input vector in two new ones: (1) a vector with only the shifted-right
17700 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
17701 // masked out higher ones) for each byte. PSHUB is used separately with both
17702 // to index the in-register table. Next, both are added and the result is a
17703 // i8 vector where each element contains the pop count for input byte.
17705 // To obtain the pop count for elements != i8, we follow up with the same
17706 // approach and use additional tricks as described below.
17708 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
17709 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
17710 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
17711 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
17713 int NumByteElts = VecSize / 8;
17714 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
17715 SDValue In = DAG.getBitcast(ByteVecVT, Op);
17716 SmallVector<SDValue, 16> LUTVec;
17717 for (int i = 0; i < NumByteElts; ++i)
17718 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
17719 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
17720 SmallVector<SDValue, 16> Mask0F(NumByteElts,
17721 DAG.getConstant(0x0F, DL, MVT::i8));
17722 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
17725 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
17726 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
17727 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
17730 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
17732 // The input vector is used as the shuffle mask that index elements into the
17733 // LUT. After counting low and high nibbles, add the vector to obtain the
17734 // final pop count per i8 element.
17735 SDValue HighPopCnt =
17736 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
17737 SDValue LowPopCnt =
17738 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
17739 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
17741 if (EltVT == MVT::i8)
17744 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
17747 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
17748 const X86Subtarget *Subtarget,
17749 SelectionDAG &DAG) {
17750 MVT VT = Op.getSimpleValueType();
17751 assert(VT.is128BitVector() &&
17752 "Only 128-bit vector bitmath lowering supported.");
17754 int VecSize = VT.getSizeInBits();
17755 MVT EltVT = VT.getVectorElementType();
17756 int Len = EltVT.getSizeInBits();
17758 // This is the vectorized version of the "best" algorithm from
17759 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17760 // with a minor tweak to use a series of adds + shifts instead of vector
17761 // multiplications. Implemented for all integer vector types. We only use
17762 // this when we don't have SSSE3 which allows a LUT-based lowering that is
17763 // much faster, even faster than using native popcnt instructions.
17765 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
17766 MVT VT = V.getSimpleValueType();
17767 SmallVector<SDValue, 32> Shifters(
17768 VT.getVectorNumElements(),
17769 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
17770 return DAG.getNode(OpCode, DL, VT, V,
17771 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
17773 auto GetMask = [&](SDValue V, APInt Mask) {
17774 MVT VT = V.getSimpleValueType();
17775 SmallVector<SDValue, 32> Masks(
17776 VT.getVectorNumElements(),
17777 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
17778 return DAG.getNode(ISD::AND, DL, VT, V,
17779 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
17782 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
17783 // x86, so set the SRL type to have elements at least i16 wide. This is
17784 // correct because all of our SRLs are followed immediately by a mask anyways
17785 // that handles any bits that sneak into the high bits of the byte elements.
17786 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
17790 // v = v - ((v >> 1) & 0x55555555...)
17792 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
17793 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
17794 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
17796 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17797 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
17798 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
17799 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
17800 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
17802 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17803 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
17804 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
17805 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
17807 // At this point, V contains the byte-wise population count, and we are
17808 // merely doing a horizontal sum if necessary to get the wider element
17810 if (EltVT == MVT::i8)
17813 return LowerHorizontalByteSum(
17814 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
17818 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17819 SelectionDAG &DAG) {
17820 MVT VT = Op.getSimpleValueType();
17821 // FIXME: Need to add AVX-512 support here!
17822 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17823 "Unknown CTPOP type to handle");
17824 SDLoc DL(Op.getNode());
17825 SDValue Op0 = Op.getOperand(0);
17827 if (!Subtarget->hasSSSE3()) {
17828 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
17829 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
17830 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
17833 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
17834 unsigned NumElems = VT.getVectorNumElements();
17836 // Extract each 128-bit vector, compute pop count and concat the result.
17837 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
17838 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
17840 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
17841 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
17842 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
17845 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
17848 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17849 SelectionDAG &DAG) {
17850 assert(Op.getValueType().isVector() &&
17851 "We only do custom lowering for vector population count.");
17852 return LowerVectorCTPOP(Op, Subtarget, DAG);
17855 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17856 SDNode *Node = Op.getNode();
17858 EVT T = Node->getValueType(0);
17859 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17860 DAG.getConstant(0, dl, T), Node->getOperand(2));
17861 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17862 cast<AtomicSDNode>(Node)->getMemoryVT(),
17863 Node->getOperand(0),
17864 Node->getOperand(1), negOp,
17865 cast<AtomicSDNode>(Node)->getMemOperand(),
17866 cast<AtomicSDNode>(Node)->getOrdering(),
17867 cast<AtomicSDNode>(Node)->getSynchScope());
17870 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17871 SDNode *Node = Op.getNode();
17873 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17875 // Convert seq_cst store -> xchg
17876 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17877 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17878 // (The only way to get a 16-byte store is cmpxchg16b)
17879 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17880 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17881 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17882 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17883 cast<AtomicSDNode>(Node)->getMemoryVT(),
17884 Node->getOperand(0),
17885 Node->getOperand(1), Node->getOperand(2),
17886 cast<AtomicSDNode>(Node)->getMemOperand(),
17887 cast<AtomicSDNode>(Node)->getOrdering(),
17888 cast<AtomicSDNode>(Node)->getSynchScope());
17889 return Swap.getValue(1);
17891 // Other atomic stores have a simple pattern.
17895 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17896 EVT VT = Op.getNode()->getSimpleValueType(0);
17898 // Let legalize expand this if it isn't a legal type yet.
17899 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17902 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17905 bool ExtraOp = false;
17906 switch (Op.getOpcode()) {
17907 default: llvm_unreachable("Invalid code");
17908 case ISD::ADDC: Opc = X86ISD::ADD; break;
17909 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17910 case ISD::SUBC: Opc = X86ISD::SUB; break;
17911 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17915 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17917 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17918 Op.getOperand(1), Op.getOperand(2));
17921 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17922 SelectionDAG &DAG) {
17923 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17925 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17926 // which returns the values as { float, float } (in XMM0) or
17927 // { double, double } (which is returned in XMM0, XMM1).
17929 SDValue Arg = Op.getOperand(0);
17930 EVT ArgVT = Arg.getValueType();
17931 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17933 TargetLowering::ArgListTy Args;
17934 TargetLowering::ArgListEntry Entry;
17938 Entry.isSExt = false;
17939 Entry.isZExt = false;
17940 Args.push_back(Entry);
17942 bool isF64 = ArgVT == MVT::f64;
17943 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17944 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17945 // the results are returned via SRet in memory.
17946 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17947 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17948 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17950 Type *RetTy = isF64
17951 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17952 : (Type*)VectorType::get(ArgTy, 4);
17954 TargetLowering::CallLoweringInfo CLI(DAG);
17955 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17956 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17958 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17961 // Returned in xmm0 and xmm1.
17962 return CallResult.first;
17964 // Returned in bits 0:31 and 32:64 xmm0.
17965 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17966 CallResult.first, DAG.getIntPtrConstant(0, dl));
17967 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17968 CallResult.first, DAG.getIntPtrConstant(1, dl));
17969 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17970 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17973 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
17974 SelectionDAG &DAG) {
17975 assert(Subtarget->hasAVX512() &&
17976 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17978 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
17979 EVT VT = N->getValue().getValueType();
17980 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
17983 // X86 scatter kills mask register, so its type should be added to
17984 // the list of return values
17985 if (N->getNumValues() == 1) {
17986 SDValue Index = N->getIndex();
17987 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17988 !Index.getValueType().is512BitVector())
17989 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17991 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
17992 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17993 N->getOperand(3), Index };
17995 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
17996 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
17997 return SDValue(NewScatter.getNode(), 0);
18002 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
18003 SelectionDAG &DAG) {
18004 assert(Subtarget->hasAVX512() &&
18005 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18007 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
18008 EVT VT = Op.getValueType();
18009 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
18012 SDValue Index = N->getIndex();
18013 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18014 !Index.getValueType().is512BitVector()) {
18015 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18016 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18017 N->getOperand(3), Index };
18018 DAG.UpdateNodeOperands(N, Ops);
18023 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
18024 SelectionDAG &DAG) const {
18025 // TODO: Eventually, the lowering of these nodes should be informed by or
18026 // deferred to the GC strategy for the function in which they appear. For
18027 // now, however, they must be lowered to something. Since they are logically
18028 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18029 // require special handling for these nodes), lower them as literal NOOPs for
18031 SmallVector<SDValue, 2> Ops;
18033 Ops.push_back(Op.getOperand(0));
18034 if (Op->getGluedNode())
18035 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18038 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18039 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18044 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
18045 SelectionDAG &DAG) const {
18046 // TODO: Eventually, the lowering of these nodes should be informed by or
18047 // deferred to the GC strategy for the function in which they appear. For
18048 // now, however, they must be lowered to something. Since they are logically
18049 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18050 // require special handling for these nodes), lower them as literal NOOPs for
18052 SmallVector<SDValue, 2> Ops;
18054 Ops.push_back(Op.getOperand(0));
18055 if (Op->getGluedNode())
18056 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18059 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18060 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18065 /// LowerOperation - Provide custom lowering hooks for some operations.
18067 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18068 switch (Op.getOpcode()) {
18069 default: llvm_unreachable("Should not custom lower this!");
18070 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18071 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18072 return LowerCMP_SWAP(Op, Subtarget, DAG);
18073 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
18074 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18075 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18076 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18077 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
18078 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
18079 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18080 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18081 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18082 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18083 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18084 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18085 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18086 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18087 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18088 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18089 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18090 case ISD::SHL_PARTS:
18091 case ISD::SRA_PARTS:
18092 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18093 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18094 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18095 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18096 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18097 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18098 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18099 case ISD::SIGN_EXTEND_VECTOR_INREG:
18100 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
18101 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18102 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18103 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18104 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18106 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18107 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18108 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18109 case ISD::SETCC: return LowerSETCC(Op, DAG);
18110 case ISD::SELECT: return LowerSELECT(Op, DAG);
18111 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18112 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18113 case ISD::VASTART: return LowerVASTART(Op, DAG);
18114 case ISD::VAARG: return LowerVAARG(Op, DAG);
18115 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18116 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
18117 case ISD::INTRINSIC_VOID:
18118 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18119 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18120 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18121 case ISD::FRAME_TO_ARGS_OFFSET:
18122 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18123 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18124 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18125 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18126 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18127 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18128 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18129 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18130 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18131 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18132 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18133 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18134 case ISD::UMUL_LOHI:
18135 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18138 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18144 case ISD::UMULO: return LowerXALUO(Op, DAG);
18145 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18146 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18150 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18151 case ISD::ADD: return LowerADD(Op, DAG);
18152 case ISD::SUB: return LowerSUB(Op, DAG);
18153 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18154 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
18155 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
18156 case ISD::GC_TRANSITION_START:
18157 return LowerGC_TRANSITION_START(Op, DAG);
18158 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
18162 /// ReplaceNodeResults - Replace a node with an illegal result type
18163 /// with a new node built out of custom code.
18164 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18165 SmallVectorImpl<SDValue>&Results,
18166 SelectionDAG &DAG) const {
18168 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18169 switch (N->getOpcode()) {
18171 llvm_unreachable("Do not know how to custom type legalize this operation!");
18172 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
18173 case X86ISD::FMINC:
18175 case X86ISD::FMAXC:
18176 case X86ISD::FMAX: {
18177 EVT VT = N->getValueType(0);
18178 if (VT != MVT::v2f32)
18179 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
18180 SDValue UNDEF = DAG.getUNDEF(VT);
18181 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18182 N->getOperand(0), UNDEF);
18183 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18184 N->getOperand(1), UNDEF);
18185 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
18188 case ISD::SIGN_EXTEND_INREG:
18193 // We don't want to expand or promote these.
18200 case ISD::UDIVREM: {
18201 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18202 Results.push_back(V);
18205 case ISD::FP_TO_SINT:
18206 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
18207 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
18208 if (N->getOperand(0).getValueType() == MVT::f16)
18211 case ISD::FP_TO_UINT: {
18212 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18214 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18217 std::pair<SDValue,SDValue> Vals =
18218 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18219 SDValue FIST = Vals.first, StackSlot = Vals.second;
18220 if (FIST.getNode()) {
18221 EVT VT = N->getValueType(0);
18222 // Return a load from the stack slot.
18223 if (StackSlot.getNode())
18224 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18225 MachinePointerInfo(),
18226 false, false, false, 0));
18228 Results.push_back(FIST);
18232 case ISD::UINT_TO_FP: {
18233 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18234 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18235 N->getValueType(0) != MVT::v2f32)
18237 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18239 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
18241 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18242 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18243 DAG.getBitcast(MVT::v2i64, VBias));
18244 Or = DAG.getBitcast(MVT::v2f64, Or);
18245 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18246 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18249 case ISD::FP_ROUND: {
18250 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18252 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18253 Results.push_back(V);
18256 case ISD::FP_EXTEND: {
18257 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
18258 // No other ValueType for FP_EXTEND should reach this point.
18259 assert(N->getValueType(0) == MVT::v2f32 &&
18260 "Do not know how to legalize this Node");
18263 case ISD::INTRINSIC_W_CHAIN: {
18264 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18266 default : llvm_unreachable("Do not know how to custom type "
18267 "legalize this intrinsic operation!");
18268 case Intrinsic::x86_rdtsc:
18269 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18271 case Intrinsic::x86_rdtscp:
18272 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18274 case Intrinsic::x86_rdpmc:
18275 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18278 case ISD::READCYCLECOUNTER: {
18279 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18282 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18283 EVT T = N->getValueType(0);
18284 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18285 bool Regs64bit = T == MVT::i128;
18286 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18287 SDValue cpInL, cpInH;
18288 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18289 DAG.getConstant(0, dl, HalfT));
18290 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18291 DAG.getConstant(1, dl, HalfT));
18292 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18293 Regs64bit ? X86::RAX : X86::EAX,
18295 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18296 Regs64bit ? X86::RDX : X86::EDX,
18297 cpInH, cpInL.getValue(1));
18298 SDValue swapInL, swapInH;
18299 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18300 DAG.getConstant(0, dl, HalfT));
18301 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18302 DAG.getConstant(1, dl, HalfT));
18303 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18304 Regs64bit ? X86::RBX : X86::EBX,
18305 swapInL, cpInH.getValue(1));
18306 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18307 Regs64bit ? X86::RCX : X86::ECX,
18308 swapInH, swapInL.getValue(1));
18309 SDValue Ops[] = { swapInH.getValue(0),
18311 swapInH.getValue(1) };
18312 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18313 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18314 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18315 X86ISD::LCMPXCHG8_DAG;
18316 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18317 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18318 Regs64bit ? X86::RAX : X86::EAX,
18319 HalfT, Result.getValue(1));
18320 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18321 Regs64bit ? X86::RDX : X86::EDX,
18322 HalfT, cpOutL.getValue(2));
18323 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18325 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18326 MVT::i32, cpOutH.getValue(2));
18328 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18329 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
18330 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18332 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18333 Results.push_back(Success);
18334 Results.push_back(EFLAGS.getValue(1));
18337 case ISD::ATOMIC_SWAP:
18338 case ISD::ATOMIC_LOAD_ADD:
18339 case ISD::ATOMIC_LOAD_SUB:
18340 case ISD::ATOMIC_LOAD_AND:
18341 case ISD::ATOMIC_LOAD_OR:
18342 case ISD::ATOMIC_LOAD_XOR:
18343 case ISD::ATOMIC_LOAD_NAND:
18344 case ISD::ATOMIC_LOAD_MIN:
18345 case ISD::ATOMIC_LOAD_MAX:
18346 case ISD::ATOMIC_LOAD_UMIN:
18347 case ISD::ATOMIC_LOAD_UMAX:
18348 case ISD::ATOMIC_LOAD: {
18349 // Delegate to generic TypeLegalization. Situations we can really handle
18350 // should have already been dealt with by AtomicExpandPass.cpp.
18353 case ISD::BITCAST: {
18354 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18355 EVT DstVT = N->getValueType(0);
18356 EVT SrcVT = N->getOperand(0)->getValueType(0);
18358 if (SrcVT != MVT::f64 ||
18359 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18362 unsigned NumElts = DstVT.getVectorNumElements();
18363 EVT SVT = DstVT.getVectorElementType();
18364 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18365 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18366 MVT::v2f64, N->getOperand(0));
18367 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
18369 if (ExperimentalVectorWideningLegalization) {
18370 // If we are legalizing vectors by widening, we already have the desired
18371 // legal vector type, just return it.
18372 Results.push_back(ToVecInt);
18376 SmallVector<SDValue, 8> Elts;
18377 for (unsigned i = 0, e = NumElts; i != e; ++i)
18378 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18379 ToVecInt, DAG.getIntPtrConstant(i, dl)));
18381 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18386 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18387 switch ((X86ISD::NodeType)Opcode) {
18388 case X86ISD::FIRST_NUMBER: break;
18389 case X86ISD::BSF: return "X86ISD::BSF";
18390 case X86ISD::BSR: return "X86ISD::BSR";
18391 case X86ISD::SHLD: return "X86ISD::SHLD";
18392 case X86ISD::SHRD: return "X86ISD::SHRD";
18393 case X86ISD::FAND: return "X86ISD::FAND";
18394 case X86ISD::FANDN: return "X86ISD::FANDN";
18395 case X86ISD::FOR: return "X86ISD::FOR";
18396 case X86ISD::FXOR: return "X86ISD::FXOR";
18397 case X86ISD::FILD: return "X86ISD::FILD";
18398 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18399 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18400 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18401 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18402 case X86ISD::FLD: return "X86ISD::FLD";
18403 case X86ISD::FST: return "X86ISD::FST";
18404 case X86ISD::CALL: return "X86ISD::CALL";
18405 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18406 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18407 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18408 case X86ISD::BT: return "X86ISD::BT";
18409 case X86ISD::CMP: return "X86ISD::CMP";
18410 case X86ISD::COMI: return "X86ISD::COMI";
18411 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18412 case X86ISD::CMPM: return "X86ISD::CMPM";
18413 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18414 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
18415 case X86ISD::SETCC: return "X86ISD::SETCC";
18416 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18417 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18418 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
18419 case X86ISD::CMOV: return "X86ISD::CMOV";
18420 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18421 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18422 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18423 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18424 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18425 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18426 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18427 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
18428 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
18429 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
18430 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18431 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18432 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18433 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18434 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18435 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
18436 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18437 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18438 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18439 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18440 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
18441 case X86ISD::ADDUS: return "X86ISD::ADDUS";
18442 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18443 case X86ISD::HADD: return "X86ISD::HADD";
18444 case X86ISD::HSUB: return "X86ISD::HSUB";
18445 case X86ISD::FHADD: return "X86ISD::FHADD";
18446 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18447 case X86ISD::UMAX: return "X86ISD::UMAX";
18448 case X86ISD::UMIN: return "X86ISD::UMIN";
18449 case X86ISD::SMAX: return "X86ISD::SMAX";
18450 case X86ISD::SMIN: return "X86ISD::SMIN";
18451 case X86ISD::ABS: return "X86ISD::ABS";
18452 case X86ISD::FMAX: return "X86ISD::FMAX";
18453 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
18454 case X86ISD::FMIN: return "X86ISD::FMIN";
18455 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
18456 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18457 case X86ISD::FMINC: return "X86ISD::FMINC";
18458 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18459 case X86ISD::FRCP: return "X86ISD::FRCP";
18460 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18461 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18462 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18463 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18464 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18465 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18466 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18467 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18468 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18469 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18470 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18471 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18472 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18473 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18474 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18475 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18476 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18477 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18478 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18479 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18480 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18481 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
18482 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18483 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18484 case X86ISD::VSHL: return "X86ISD::VSHL";
18485 case X86ISD::VSRL: return "X86ISD::VSRL";
18486 case X86ISD::VSRA: return "X86ISD::VSRA";
18487 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18488 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18489 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18490 case X86ISD::CMPP: return "X86ISD::CMPP";
18491 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18492 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18493 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18494 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18495 case X86ISD::ADD: return "X86ISD::ADD";
18496 case X86ISD::SUB: return "X86ISD::SUB";
18497 case X86ISD::ADC: return "X86ISD::ADC";
18498 case X86ISD::SBB: return "X86ISD::SBB";
18499 case X86ISD::SMUL: return "X86ISD::SMUL";
18500 case X86ISD::UMUL: return "X86ISD::UMUL";
18501 case X86ISD::SMUL8: return "X86ISD::SMUL8";
18502 case X86ISD::UMUL8: return "X86ISD::UMUL8";
18503 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
18504 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
18505 case X86ISD::INC: return "X86ISD::INC";
18506 case X86ISD::DEC: return "X86ISD::DEC";
18507 case X86ISD::OR: return "X86ISD::OR";
18508 case X86ISD::XOR: return "X86ISD::XOR";
18509 case X86ISD::AND: return "X86ISD::AND";
18510 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18511 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18512 case X86ISD::PTEST: return "X86ISD::PTEST";
18513 case X86ISD::TESTP: return "X86ISD::TESTP";
18514 case X86ISD::TESTM: return "X86ISD::TESTM";
18515 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18516 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18517 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18518 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18519 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18520 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18521 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18522 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18523 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18524 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18525 case X86ISD::SHUF128: return "X86ISD::SHUF128";
18526 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18527 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18528 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18529 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18530 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18531 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18532 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18533 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18534 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18535 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18536 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18537 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18538 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18539 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
18540 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18541 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
18542 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18543 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18544 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18545 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18546 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18547 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18548 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
18549 case X86ISD::VRANGE: return "X86ISD::VRANGE";
18550 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18551 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18552 case X86ISD::PSADBW: return "X86ISD::PSADBW";
18553 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18554 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18555 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18556 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18557 case X86ISD::MFENCE: return "X86ISD::MFENCE";
18558 case X86ISD::SFENCE: return "X86ISD::SFENCE";
18559 case X86ISD::LFENCE: return "X86ISD::LFENCE";
18560 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18561 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18562 case X86ISD::SAHF: return "X86ISD::SAHF";
18563 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18564 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18565 case X86ISD::FMADD: return "X86ISD::FMADD";
18566 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18567 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18568 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18569 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18570 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18571 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
18572 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
18573 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
18574 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
18575 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
18576 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
18577 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
18578 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18579 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18580 case X86ISD::XTEST: return "X86ISD::XTEST";
18581 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
18582 case X86ISD::EXPAND: return "X86ISD::EXPAND";
18583 case X86ISD::SELECT: return "X86ISD::SELECT";
18584 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
18585 case X86ISD::RCP28: return "X86ISD::RCP28";
18586 case X86ISD::EXP2: return "X86ISD::EXP2";
18587 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
18588 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
18589 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
18590 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
18591 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
18592 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
18593 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
18594 case X86ISD::SCALEF: return "X86ISD::SCALEF";
18595 case X86ISD::ADDS: return "X86ISD::ADDS";
18596 case X86ISD::SUBS: return "X86ISD::SUBS";
18597 case X86ISD::AVG: return "X86ISD::AVG";
18598 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
18599 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
18604 // isLegalAddressingMode - Return true if the addressing mode represented
18605 // by AM is legal for this target, for a load/store of the specified type.
18606 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18608 unsigned AS) const {
18609 // X86 supports extremely general addressing modes.
18610 CodeModel::Model M = getTargetMachine().getCodeModel();
18611 Reloc::Model R = getTargetMachine().getRelocationModel();
18613 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18614 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18619 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18621 // If a reference to this global requires an extra load, we can't fold it.
18622 if (isGlobalStubReference(GVFlags))
18625 // If BaseGV requires a register for the PIC base, we cannot also have a
18626 // BaseReg specified.
18627 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18630 // If lower 4G is not available, then we must use rip-relative addressing.
18631 if ((M != CodeModel::Small || R != Reloc::Static) &&
18632 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18636 switch (AM.Scale) {
18642 // These scales always work.
18647 // These scales are formed with basereg+scalereg. Only accept if there is
18652 default: // Other stuff never works.
18659 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18660 unsigned Bits = Ty->getScalarSizeInBits();
18662 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18663 // particularly cheaper than those without.
18667 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18668 // variable shifts just as cheap as scalar ones.
18669 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18672 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18673 // fully general vector.
18677 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18678 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18680 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18681 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18682 return NumBits1 > NumBits2;
18685 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18686 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18689 if (!isTypeLegal(EVT::getEVT(Ty1)))
18692 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18694 // Assuming the caller doesn't have a zeroext or signext return parameter,
18695 // truncation all the way down to i1 is valid.
18699 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18700 return isInt<32>(Imm);
18703 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18704 // Can also use sub to handle negated immediates.
18705 return isInt<32>(Imm);
18708 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18709 if (!VT1.isInteger() || !VT2.isInteger())
18711 unsigned NumBits1 = VT1.getSizeInBits();
18712 unsigned NumBits2 = VT2.getSizeInBits();
18713 return NumBits1 > NumBits2;
18716 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18717 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18718 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18721 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18722 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18723 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18726 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18727 EVT VT1 = Val.getValueType();
18728 if (isZExtFree(VT1, VT2))
18731 if (Val.getOpcode() != ISD::LOAD)
18734 if (!VT1.isSimple() || !VT1.isInteger() ||
18735 !VT2.isSimple() || !VT2.isInteger())
18738 switch (VT1.getSimpleVT().SimpleTy) {
18743 // X86 has 8, 16, and 32-bit zero-extending loads.
18750 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18753 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18754 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
18757 VT = VT.getScalarType();
18759 if (!VT.isSimple())
18762 switch (VT.getSimpleVT().SimpleTy) {
18773 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18774 // i16 instructions are longer (0x66 prefix) and potentially slower.
18775 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18778 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18779 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18780 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18781 /// are assumed to be legal.
18783 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18785 if (!VT.isSimple())
18788 // Not for i1 vectors
18789 if (VT.getScalarType() == MVT::i1)
18792 // Very little shuffling can be done for 64-bit vectors right now.
18793 if (VT.getSizeInBits() == 64)
18796 // We only care that the types being shuffled are legal. The lowering can
18797 // handle any possible shuffle mask that results.
18798 return isTypeLegal(VT.getSimpleVT());
18802 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18804 // Just delegate to the generic legality, clear masks aren't special.
18805 return isShuffleMaskLegal(Mask, VT);
18808 //===----------------------------------------------------------------------===//
18809 // X86 Scheduler Hooks
18810 //===----------------------------------------------------------------------===//
18812 /// Utility function to emit xbegin specifying the start of an RTM region.
18813 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18814 const TargetInstrInfo *TII) {
18815 DebugLoc DL = MI->getDebugLoc();
18817 const BasicBlock *BB = MBB->getBasicBlock();
18818 MachineFunction::iterator I = MBB;
18821 // For the v = xbegin(), we generate
18832 MachineBasicBlock *thisMBB = MBB;
18833 MachineFunction *MF = MBB->getParent();
18834 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18835 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18836 MF->insert(I, mainMBB);
18837 MF->insert(I, sinkMBB);
18839 // Transfer the remainder of BB and its successor edges to sinkMBB.
18840 sinkMBB->splice(sinkMBB->begin(), MBB,
18841 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18842 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18846 // # fallthrough to mainMBB
18847 // # abortion to sinkMBB
18848 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18849 thisMBB->addSuccessor(mainMBB);
18850 thisMBB->addSuccessor(sinkMBB);
18854 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18855 mainMBB->addSuccessor(sinkMBB);
18858 // EAX is live into the sinkMBB
18859 sinkMBB->addLiveIn(X86::EAX);
18860 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18861 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18864 MI->eraseFromParent();
18868 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18869 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18870 // in the .td file.
18871 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18872 const TargetInstrInfo *TII) {
18874 switch (MI->getOpcode()) {
18875 default: llvm_unreachable("illegal opcode!");
18876 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18877 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18878 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18879 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18880 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18881 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18882 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18883 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18886 DebugLoc dl = MI->getDebugLoc();
18887 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18889 unsigned NumArgs = MI->getNumOperands();
18890 for (unsigned i = 1; i < NumArgs; ++i) {
18891 MachineOperand &Op = MI->getOperand(i);
18892 if (!(Op.isReg() && Op.isImplicit()))
18893 MIB.addOperand(Op);
18895 if (MI->hasOneMemOperand())
18896 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18898 BuildMI(*BB, MI, dl,
18899 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18900 .addReg(X86::XMM0);
18902 MI->eraseFromParent();
18906 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18907 // defs in an instruction pattern
18908 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18909 const TargetInstrInfo *TII) {
18911 switch (MI->getOpcode()) {
18912 default: llvm_unreachable("illegal opcode!");
18913 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18914 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18915 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18916 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18917 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18918 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18919 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18920 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18923 DebugLoc dl = MI->getDebugLoc();
18924 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18926 unsigned NumArgs = MI->getNumOperands(); // remove the results
18927 for (unsigned i = 1; i < NumArgs; ++i) {
18928 MachineOperand &Op = MI->getOperand(i);
18929 if (!(Op.isReg() && Op.isImplicit()))
18930 MIB.addOperand(Op);
18932 if (MI->hasOneMemOperand())
18933 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18935 BuildMI(*BB, MI, dl,
18936 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18939 MI->eraseFromParent();
18943 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18944 const X86Subtarget *Subtarget) {
18945 DebugLoc dl = MI->getDebugLoc();
18946 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18947 // Address into RAX/EAX, other two args into ECX, EDX.
18948 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18949 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18950 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18951 for (int i = 0; i < X86::AddrNumOperands; ++i)
18952 MIB.addOperand(MI->getOperand(i));
18954 unsigned ValOps = X86::AddrNumOperands;
18955 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18956 .addReg(MI->getOperand(ValOps).getReg());
18957 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18958 .addReg(MI->getOperand(ValOps+1).getReg());
18960 // The instruction doesn't actually take any operands though.
18961 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18963 MI->eraseFromParent(); // The pseudo is gone now.
18967 MachineBasicBlock *
18968 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18969 MachineBasicBlock *MBB) const {
18970 // Emit va_arg instruction on X86-64.
18972 // Operands to this pseudo-instruction:
18973 // 0 ) Output : destination address (reg)
18974 // 1-5) Input : va_list address (addr, i64mem)
18975 // 6 ) ArgSize : Size (in bytes) of vararg type
18976 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18977 // 8 ) Align : Alignment of type
18978 // 9 ) EFLAGS (implicit-def)
18980 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18981 static_assert(X86::AddrNumOperands == 5,
18982 "VAARG_64 assumes 5 address operands");
18984 unsigned DestReg = MI->getOperand(0).getReg();
18985 MachineOperand &Base = MI->getOperand(1);
18986 MachineOperand &Scale = MI->getOperand(2);
18987 MachineOperand &Index = MI->getOperand(3);
18988 MachineOperand &Disp = MI->getOperand(4);
18989 MachineOperand &Segment = MI->getOperand(5);
18990 unsigned ArgSize = MI->getOperand(6).getImm();
18991 unsigned ArgMode = MI->getOperand(7).getImm();
18992 unsigned Align = MI->getOperand(8).getImm();
18994 // Memory Reference
18995 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18996 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18997 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18999 // Machine Information
19000 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19001 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19002 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19003 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19004 DebugLoc DL = MI->getDebugLoc();
19006 // struct va_list {
19009 // i64 overflow_area (address)
19010 // i64 reg_save_area (address)
19012 // sizeof(va_list) = 24
19013 // alignment(va_list) = 8
19015 unsigned TotalNumIntRegs = 6;
19016 unsigned TotalNumXMMRegs = 8;
19017 bool UseGPOffset = (ArgMode == 1);
19018 bool UseFPOffset = (ArgMode == 2);
19019 unsigned MaxOffset = TotalNumIntRegs * 8 +
19020 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19022 /* Align ArgSize to a multiple of 8 */
19023 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19024 bool NeedsAlign = (Align > 8);
19026 MachineBasicBlock *thisMBB = MBB;
19027 MachineBasicBlock *overflowMBB;
19028 MachineBasicBlock *offsetMBB;
19029 MachineBasicBlock *endMBB;
19031 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19032 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19033 unsigned OffsetReg = 0;
19035 if (!UseGPOffset && !UseFPOffset) {
19036 // If we only pull from the overflow region, we don't create a branch.
19037 // We don't need to alter control flow.
19038 OffsetDestReg = 0; // unused
19039 OverflowDestReg = DestReg;
19041 offsetMBB = nullptr;
19042 overflowMBB = thisMBB;
19045 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19046 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19047 // If not, pull from overflow_area. (branch to overflowMBB)
19052 // offsetMBB overflowMBB
19057 // Registers for the PHI in endMBB
19058 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19059 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19061 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19062 MachineFunction *MF = MBB->getParent();
19063 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19064 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19065 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19067 MachineFunction::iterator MBBIter = MBB;
19070 // Insert the new basic blocks
19071 MF->insert(MBBIter, offsetMBB);
19072 MF->insert(MBBIter, overflowMBB);
19073 MF->insert(MBBIter, endMBB);
19075 // Transfer the remainder of MBB and its successor edges to endMBB.
19076 endMBB->splice(endMBB->begin(), thisMBB,
19077 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19078 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19080 // Make offsetMBB and overflowMBB successors of thisMBB
19081 thisMBB->addSuccessor(offsetMBB);
19082 thisMBB->addSuccessor(overflowMBB);
19084 // endMBB is a successor of both offsetMBB and overflowMBB
19085 offsetMBB->addSuccessor(endMBB);
19086 overflowMBB->addSuccessor(endMBB);
19088 // Load the offset value into a register
19089 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19090 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19094 .addDisp(Disp, UseFPOffset ? 4 : 0)
19095 .addOperand(Segment)
19096 .setMemRefs(MMOBegin, MMOEnd);
19098 // Check if there is enough room left to pull this argument.
19099 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19101 .addImm(MaxOffset + 8 - ArgSizeA8);
19103 // Branch to "overflowMBB" if offset >= max
19104 // Fall through to "offsetMBB" otherwise
19105 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19106 .addMBB(overflowMBB);
19109 // In offsetMBB, emit code to use the reg_save_area.
19111 assert(OffsetReg != 0);
19113 // Read the reg_save_area address.
19114 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19115 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19120 .addOperand(Segment)
19121 .setMemRefs(MMOBegin, MMOEnd);
19123 // Zero-extend the offset
19124 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19125 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19128 .addImm(X86::sub_32bit);
19130 // Add the offset to the reg_save_area to get the final address.
19131 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19132 .addReg(OffsetReg64)
19133 .addReg(RegSaveReg);
19135 // Compute the offset for the next argument
19136 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19137 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19139 .addImm(UseFPOffset ? 16 : 8);
19141 // Store it back into the va_list.
19142 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19146 .addDisp(Disp, UseFPOffset ? 4 : 0)
19147 .addOperand(Segment)
19148 .addReg(NextOffsetReg)
19149 .setMemRefs(MMOBegin, MMOEnd);
19152 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
19157 // Emit code to use overflow area
19160 // Load the overflow_area address into a register.
19161 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19162 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19167 .addOperand(Segment)
19168 .setMemRefs(MMOBegin, MMOEnd);
19170 // If we need to align it, do so. Otherwise, just copy the address
19171 // to OverflowDestReg.
19173 // Align the overflow address
19174 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19175 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19177 // aligned_addr = (addr + (align-1)) & ~(align-1)
19178 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19179 .addReg(OverflowAddrReg)
19182 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19184 .addImm(~(uint64_t)(Align-1));
19186 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19187 .addReg(OverflowAddrReg);
19190 // Compute the next overflow address after this argument.
19191 // (the overflow address should be kept 8-byte aligned)
19192 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19193 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19194 .addReg(OverflowDestReg)
19195 .addImm(ArgSizeA8);
19197 // Store the new overflow address.
19198 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19203 .addOperand(Segment)
19204 .addReg(NextAddrReg)
19205 .setMemRefs(MMOBegin, MMOEnd);
19207 // If we branched, emit the PHI to the front of endMBB.
19209 BuildMI(*endMBB, endMBB->begin(), DL,
19210 TII->get(X86::PHI), DestReg)
19211 .addReg(OffsetDestReg).addMBB(offsetMBB)
19212 .addReg(OverflowDestReg).addMBB(overflowMBB);
19215 // Erase the pseudo instruction
19216 MI->eraseFromParent();
19221 MachineBasicBlock *
19222 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19224 MachineBasicBlock *MBB) const {
19225 // Emit code to save XMM registers to the stack. The ABI says that the
19226 // number of registers to save is given in %al, so it's theoretically
19227 // possible to do an indirect jump trick to avoid saving all of them,
19228 // however this code takes a simpler approach and just executes all
19229 // of the stores if %al is non-zero. It's less code, and it's probably
19230 // easier on the hardware branch predictor, and stores aren't all that
19231 // expensive anyway.
19233 // Create the new basic blocks. One block contains all the XMM stores,
19234 // and one block is the final destination regardless of whether any
19235 // stores were performed.
19236 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19237 MachineFunction *F = MBB->getParent();
19238 MachineFunction::iterator MBBIter = MBB;
19240 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19241 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19242 F->insert(MBBIter, XMMSaveMBB);
19243 F->insert(MBBIter, EndMBB);
19245 // Transfer the remainder of MBB and its successor edges to EndMBB.
19246 EndMBB->splice(EndMBB->begin(), MBB,
19247 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19248 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19250 // The original block will now fall through to the XMM save block.
19251 MBB->addSuccessor(XMMSaveMBB);
19252 // The XMMSaveMBB will fall through to the end block.
19253 XMMSaveMBB->addSuccessor(EndMBB);
19255 // Now add the instructions.
19256 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19257 DebugLoc DL = MI->getDebugLoc();
19259 unsigned CountReg = MI->getOperand(0).getReg();
19260 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19261 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19263 if (!Subtarget->isTargetWin64()) {
19264 // If %al is 0, branch around the XMM save block.
19265 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19266 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
19267 MBB->addSuccessor(EndMBB);
19270 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19271 // that was just emitted, but clearly shouldn't be "saved".
19272 assert((MI->getNumOperands() <= 3 ||
19273 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19274 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19275 && "Expected last argument to be EFLAGS");
19276 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19277 // In the XMM save block, save all the XMM argument registers.
19278 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19279 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19280 MachineMemOperand *MMO =
19281 F->getMachineMemOperand(
19282 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19283 MachineMemOperand::MOStore,
19284 /*Size=*/16, /*Align=*/16);
19285 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19286 .addFrameIndex(RegSaveFrameIndex)
19287 .addImm(/*Scale=*/1)
19288 .addReg(/*IndexReg=*/0)
19289 .addImm(/*Disp=*/Offset)
19290 .addReg(/*Segment=*/0)
19291 .addReg(MI->getOperand(i).getReg())
19292 .addMemOperand(MMO);
19295 MI->eraseFromParent(); // The pseudo instruction is gone now.
19300 // The EFLAGS operand of SelectItr might be missing a kill marker
19301 // because there were multiple uses of EFLAGS, and ISel didn't know
19302 // which to mark. Figure out whether SelectItr should have had a
19303 // kill marker, and set it if it should. Returns the correct kill
19305 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19306 MachineBasicBlock* BB,
19307 const TargetRegisterInfo* TRI) {
19308 // Scan forward through BB for a use/def of EFLAGS.
19309 MachineBasicBlock::iterator miI(std::next(SelectItr));
19310 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19311 const MachineInstr& mi = *miI;
19312 if (mi.readsRegister(X86::EFLAGS))
19314 if (mi.definesRegister(X86::EFLAGS))
19315 break; // Should have kill-flag - update below.
19318 // If we hit the end of the block, check whether EFLAGS is live into a
19320 if (miI == BB->end()) {
19321 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19322 sEnd = BB->succ_end();
19323 sItr != sEnd; ++sItr) {
19324 MachineBasicBlock* succ = *sItr;
19325 if (succ->isLiveIn(X86::EFLAGS))
19330 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19331 // out. SelectMI should have a kill flag on EFLAGS.
19332 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19336 MachineBasicBlock *
19337 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19338 MachineBasicBlock *BB) const {
19339 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19340 DebugLoc DL = MI->getDebugLoc();
19342 // To "insert" a SELECT_CC instruction, we actually have to insert the
19343 // diamond control-flow pattern. The incoming instruction knows the
19344 // destination vreg to set, the condition code register to branch on, the
19345 // true/false values to select between, and a branch opcode to use.
19346 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19347 MachineFunction::iterator It = BB;
19353 // cmpTY ccX, r1, r2
19355 // fallthrough --> copy0MBB
19356 MachineBasicBlock *thisMBB = BB;
19357 MachineFunction *F = BB->getParent();
19359 // We also lower double CMOVs:
19360 // (CMOV (CMOV F, T, cc1), T, cc2)
19361 // to two successives branches. For that, we look for another CMOV as the
19362 // following instruction.
19364 // Without this, we would add a PHI between the two jumps, which ends up
19365 // creating a few copies all around. For instance, for
19367 // (sitofp (zext (fcmp une)))
19369 // we would generate:
19371 // ucomiss %xmm1, %xmm0
19372 // movss <1.0f>, %xmm0
19373 // movaps %xmm0, %xmm1
19375 // xorps %xmm1, %xmm1
19378 // movaps %xmm1, %xmm0
19382 // because this custom-inserter would have generated:
19394 // A: X = ...; Y = ...
19396 // C: Z = PHI [X, A], [Y, B]
19398 // E: PHI [X, C], [Z, D]
19400 // If we lower both CMOVs in a single step, we can instead generate:
19412 // A: X = ...; Y = ...
19414 // E: PHI [X, A], [X, C], [Y, D]
19416 // Which, in our sitofp/fcmp example, gives us something like:
19418 // ucomiss %xmm1, %xmm0
19419 // movss <1.0f>, %xmm0
19422 // xorps %xmm0, %xmm0
19426 MachineInstr *NextCMOV = nullptr;
19427 MachineBasicBlock::iterator NextMIIt =
19428 std::next(MachineBasicBlock::iterator(MI));
19429 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
19430 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
19431 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
19432 NextCMOV = &*NextMIIt;
19434 MachineBasicBlock *jcc1MBB = nullptr;
19436 // If we have a double CMOV, we lower it to two successive branches to
19437 // the same block. EFLAGS is used by both, so mark it as live in the second.
19439 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
19440 F->insert(It, jcc1MBB);
19441 jcc1MBB->addLiveIn(X86::EFLAGS);
19444 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19445 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19446 F->insert(It, copy0MBB);
19447 F->insert(It, sinkMBB);
19449 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19450 // live into the sink and copy blocks.
19451 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
19453 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
19454 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
19455 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
19456 copy0MBB->addLiveIn(X86::EFLAGS);
19457 sinkMBB->addLiveIn(X86::EFLAGS);
19460 // Transfer the remainder of BB and its successor edges to sinkMBB.
19461 sinkMBB->splice(sinkMBB->begin(), BB,
19462 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19463 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19465 // Add the true and fallthrough blocks as its successors.
19467 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
19468 BB->addSuccessor(jcc1MBB);
19470 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
19471 // jump to the sinkMBB.
19472 jcc1MBB->addSuccessor(copy0MBB);
19473 jcc1MBB->addSuccessor(sinkMBB);
19475 BB->addSuccessor(copy0MBB);
19478 // The true block target of the first (or only) branch is always sinkMBB.
19479 BB->addSuccessor(sinkMBB);
19481 // Create the conditional branch instruction.
19483 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19484 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19487 unsigned Opc2 = X86::GetCondBranchFromCond(
19488 (X86::CondCode)NextCMOV->getOperand(3).getImm());
19489 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
19493 // %FalseValue = ...
19494 // # fallthrough to sinkMBB
19495 copy0MBB->addSuccessor(sinkMBB);
19498 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19500 MachineInstrBuilder MIB =
19501 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
19502 MI->getOperand(0).getReg())
19503 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19504 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19506 // If we have a double CMOV, the second Jcc provides the same incoming
19507 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
19509 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
19510 // Copy the PHI result to the register defined by the second CMOV.
19511 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
19512 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
19513 .addReg(MI->getOperand(0).getReg());
19514 NextCMOV->eraseFromParent();
19517 MI->eraseFromParent(); // The pseudo instruction is gone now.
19521 MachineBasicBlock *
19522 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19523 MachineBasicBlock *BB) const {
19524 MachineFunction *MF = BB->getParent();
19525 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19526 DebugLoc DL = MI->getDebugLoc();
19527 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19529 assert(MF->shouldSplitStack());
19531 const bool Is64Bit = Subtarget->is64Bit();
19532 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19534 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19535 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19538 // ... [Till the alloca]
19539 // If stacklet is not large enough, jump to mallocMBB
19542 // Allocate by subtracting from RSP
19543 // Jump to continueMBB
19546 // Allocate by call to runtime
19550 // [rest of original BB]
19553 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19554 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19555 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19557 MachineRegisterInfo &MRI = MF->getRegInfo();
19558 const TargetRegisterClass *AddrRegClass =
19559 getRegClassFor(getPointerTy());
19561 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19562 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19563 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19564 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19565 sizeVReg = MI->getOperand(1).getReg(),
19566 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19568 MachineFunction::iterator MBBIter = BB;
19571 MF->insert(MBBIter, bumpMBB);
19572 MF->insert(MBBIter, mallocMBB);
19573 MF->insert(MBBIter, continueMBB);
19575 continueMBB->splice(continueMBB->begin(), BB,
19576 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19577 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19579 // Add code to the main basic block to check if the stack limit has been hit,
19580 // and if so, jump to mallocMBB otherwise to bumpMBB.
19581 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19582 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19583 .addReg(tmpSPVReg).addReg(sizeVReg);
19584 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19585 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19586 .addReg(SPLimitVReg);
19587 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
19589 // bumpMBB simply decreases the stack pointer, since we know the current
19590 // stacklet has enough space.
19591 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19592 .addReg(SPLimitVReg);
19593 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19594 .addReg(SPLimitVReg);
19595 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19597 // Calls into a routine in libgcc to allocate more space from the heap.
19598 const uint32_t *RegMask =
19599 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19601 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19603 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19604 .addExternalSymbol("__morestack_allocate_stack_space")
19605 .addRegMask(RegMask)
19606 .addReg(X86::RDI, RegState::Implicit)
19607 .addReg(X86::RAX, RegState::ImplicitDefine);
19608 } else if (Is64Bit) {
19609 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19611 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19612 .addExternalSymbol("__morestack_allocate_stack_space")
19613 .addRegMask(RegMask)
19614 .addReg(X86::EDI, RegState::Implicit)
19615 .addReg(X86::EAX, RegState::ImplicitDefine);
19617 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19619 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19620 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19621 .addExternalSymbol("__morestack_allocate_stack_space")
19622 .addRegMask(RegMask)
19623 .addReg(X86::EAX, RegState::ImplicitDefine);
19627 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19630 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19631 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19632 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19634 // Set up the CFG correctly.
19635 BB->addSuccessor(bumpMBB);
19636 BB->addSuccessor(mallocMBB);
19637 mallocMBB->addSuccessor(continueMBB);
19638 bumpMBB->addSuccessor(continueMBB);
19640 // Take care of the PHI nodes.
19641 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19642 MI->getOperand(0).getReg())
19643 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19644 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19646 // Delete the original pseudo instruction.
19647 MI->eraseFromParent();
19650 return continueMBB;
19653 MachineBasicBlock *
19654 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19655 MachineBasicBlock *BB) const {
19656 DebugLoc DL = MI->getDebugLoc();
19658 assert(!Subtarget->isTargetMachO());
19660 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
19663 MI->eraseFromParent(); // The pseudo instruction is gone now.
19667 MachineBasicBlock *
19668 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19669 MachineBasicBlock *BB) const {
19670 // This is pretty easy. We're taking the value that we received from
19671 // our load from the relocation, sticking it in either RDI (x86-64)
19672 // or EAX and doing an indirect call. The return value will then
19673 // be in the normal return register.
19674 MachineFunction *F = BB->getParent();
19675 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19676 DebugLoc DL = MI->getDebugLoc();
19678 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19679 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19681 // Get a register mask for the lowered call.
19682 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19683 // proper register mask.
19684 const uint32_t *RegMask =
19685 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19686 if (Subtarget->is64Bit()) {
19687 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19688 TII->get(X86::MOV64rm), X86::RDI)
19690 .addImm(0).addReg(0)
19691 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19692 MI->getOperand(3).getTargetFlags())
19694 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19695 addDirectMem(MIB, X86::RDI);
19696 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19697 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19698 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19699 TII->get(X86::MOV32rm), X86::EAX)
19701 .addImm(0).addReg(0)
19702 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19703 MI->getOperand(3).getTargetFlags())
19705 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19706 addDirectMem(MIB, X86::EAX);
19707 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19709 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19710 TII->get(X86::MOV32rm), X86::EAX)
19711 .addReg(TII->getGlobalBaseReg(F))
19712 .addImm(0).addReg(0)
19713 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19714 MI->getOperand(3).getTargetFlags())
19716 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19717 addDirectMem(MIB, X86::EAX);
19718 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19721 MI->eraseFromParent(); // The pseudo instruction is gone now.
19725 MachineBasicBlock *
19726 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19727 MachineBasicBlock *MBB) const {
19728 DebugLoc DL = MI->getDebugLoc();
19729 MachineFunction *MF = MBB->getParent();
19730 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19731 MachineRegisterInfo &MRI = MF->getRegInfo();
19733 const BasicBlock *BB = MBB->getBasicBlock();
19734 MachineFunction::iterator I = MBB;
19737 // Memory Reference
19738 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19739 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19742 unsigned MemOpndSlot = 0;
19744 unsigned CurOp = 0;
19746 DstReg = MI->getOperand(CurOp++).getReg();
19747 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19748 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19749 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19750 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19752 MemOpndSlot = CurOp;
19754 MVT PVT = getPointerTy();
19755 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19756 "Invalid Pointer Size!");
19758 // For v = setjmp(buf), we generate
19761 // buf[LabelOffset] = restoreMBB
19762 // SjLjSetup restoreMBB
19768 // v = phi(main, restore)
19771 // if base pointer being used, load it from frame
19774 MachineBasicBlock *thisMBB = MBB;
19775 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19776 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19777 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19778 MF->insert(I, mainMBB);
19779 MF->insert(I, sinkMBB);
19780 MF->push_back(restoreMBB);
19782 MachineInstrBuilder MIB;
19784 // Transfer the remainder of BB and its successor edges to sinkMBB.
19785 sinkMBB->splice(sinkMBB->begin(), MBB,
19786 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19787 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19790 unsigned PtrStoreOpc = 0;
19791 unsigned LabelReg = 0;
19792 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19793 Reloc::Model RM = MF->getTarget().getRelocationModel();
19794 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19795 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19797 // Prepare IP either in reg or imm.
19798 if (!UseImmLabel) {
19799 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19800 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19801 LabelReg = MRI.createVirtualRegister(PtrRC);
19802 if (Subtarget->is64Bit()) {
19803 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19807 .addMBB(restoreMBB)
19810 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19811 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19812 .addReg(XII->getGlobalBaseReg(MF))
19815 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19819 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19821 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19822 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19823 if (i == X86::AddrDisp)
19824 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19826 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19829 MIB.addReg(LabelReg);
19831 MIB.addMBB(restoreMBB);
19832 MIB.setMemRefs(MMOBegin, MMOEnd);
19834 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19835 .addMBB(restoreMBB);
19837 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19838 MIB.addRegMask(RegInfo->getNoPreservedMask());
19839 thisMBB->addSuccessor(mainMBB);
19840 thisMBB->addSuccessor(restoreMBB);
19844 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19845 mainMBB->addSuccessor(sinkMBB);
19848 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19849 TII->get(X86::PHI), DstReg)
19850 .addReg(mainDstReg).addMBB(mainMBB)
19851 .addReg(restoreDstReg).addMBB(restoreMBB);
19854 if (RegInfo->hasBasePointer(*MF)) {
19855 const bool Uses64BitFramePtr =
19856 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
19857 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
19858 X86FI->setRestoreBasePointer(MF);
19859 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
19860 unsigned BasePtr = RegInfo->getBaseRegister();
19861 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
19862 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
19863 FramePtr, true, X86FI->getRestoreBasePointerOffset())
19864 .setMIFlag(MachineInstr::FrameSetup);
19866 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19867 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
19868 restoreMBB->addSuccessor(sinkMBB);
19870 MI->eraseFromParent();
19874 MachineBasicBlock *
19875 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19876 MachineBasicBlock *MBB) const {
19877 DebugLoc DL = MI->getDebugLoc();
19878 MachineFunction *MF = MBB->getParent();
19879 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19880 MachineRegisterInfo &MRI = MF->getRegInfo();
19882 // Memory Reference
19883 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19884 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19886 MVT PVT = getPointerTy();
19887 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19888 "Invalid Pointer Size!");
19890 const TargetRegisterClass *RC =
19891 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19892 unsigned Tmp = MRI.createVirtualRegister(RC);
19893 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19894 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19895 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19896 unsigned SP = RegInfo->getStackRegister();
19898 MachineInstrBuilder MIB;
19900 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19901 const int64_t SPOffset = 2 * PVT.getStoreSize();
19903 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19904 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19907 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19908 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19909 MIB.addOperand(MI->getOperand(i));
19910 MIB.setMemRefs(MMOBegin, MMOEnd);
19912 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19913 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19914 if (i == X86::AddrDisp)
19915 MIB.addDisp(MI->getOperand(i), LabelOffset);
19917 MIB.addOperand(MI->getOperand(i));
19919 MIB.setMemRefs(MMOBegin, MMOEnd);
19921 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19922 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19923 if (i == X86::AddrDisp)
19924 MIB.addDisp(MI->getOperand(i), SPOffset);
19926 MIB.addOperand(MI->getOperand(i));
19928 MIB.setMemRefs(MMOBegin, MMOEnd);
19930 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19932 MI->eraseFromParent();
19936 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19937 // accumulator loops. Writing back to the accumulator allows the coalescer
19938 // to remove extra copies in the loop.
19939 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
19940 MachineBasicBlock *
19941 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19942 MachineBasicBlock *MBB) const {
19943 MachineOperand &AddendOp = MI->getOperand(3);
19945 // Bail out early if the addend isn't a register - we can't switch these.
19946 if (!AddendOp.isReg())
19949 MachineFunction &MF = *MBB->getParent();
19950 MachineRegisterInfo &MRI = MF.getRegInfo();
19952 // Check whether the addend is defined by a PHI:
19953 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19954 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19955 if (!AddendDef.isPHI())
19958 // Look for the following pattern:
19960 // %addend = phi [%entry, 0], [%loop, %result]
19962 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19966 // %addend = phi [%entry, 0], [%loop, %result]
19968 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19970 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19971 assert(AddendDef.getOperand(i).isReg());
19972 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19973 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19974 if (&PHISrcInst == MI) {
19975 // Found a matching instruction.
19976 unsigned NewFMAOpc = 0;
19977 switch (MI->getOpcode()) {
19978 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19979 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19980 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19981 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19982 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19983 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19984 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19985 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19986 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19987 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19988 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19989 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19990 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19991 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19992 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19993 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19994 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19995 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19996 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19997 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19999 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20000 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20001 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20002 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20003 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20004 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20005 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20006 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20007 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20008 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20009 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20010 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20011 default: llvm_unreachable("Unrecognized FMA variant.");
20014 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
20015 MachineInstrBuilder MIB =
20016 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20017 .addOperand(MI->getOperand(0))
20018 .addOperand(MI->getOperand(3))
20019 .addOperand(MI->getOperand(2))
20020 .addOperand(MI->getOperand(1));
20021 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20022 MI->eraseFromParent();
20029 MachineBasicBlock *
20030 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20031 MachineBasicBlock *BB) const {
20032 switch (MI->getOpcode()) {
20033 default: llvm_unreachable("Unexpected instr type to insert");
20034 case X86::TAILJMPd64:
20035 case X86::TAILJMPr64:
20036 case X86::TAILJMPm64:
20037 case X86::TAILJMPd64_REX:
20038 case X86::TAILJMPr64_REX:
20039 case X86::TAILJMPm64_REX:
20040 llvm_unreachable("TAILJMP64 would not be touched here.");
20041 case X86::TCRETURNdi64:
20042 case X86::TCRETURNri64:
20043 case X86::TCRETURNmi64:
20045 case X86::WIN_ALLOCA:
20046 return EmitLoweredWinAlloca(MI, BB);
20047 case X86::SEG_ALLOCA_32:
20048 case X86::SEG_ALLOCA_64:
20049 return EmitLoweredSegAlloca(MI, BB);
20050 case X86::TLSCall_32:
20051 case X86::TLSCall_64:
20052 return EmitLoweredTLSCall(MI, BB);
20053 case X86::CMOV_GR8:
20054 case X86::CMOV_FR32:
20055 case X86::CMOV_FR64:
20056 case X86::CMOV_V4F32:
20057 case X86::CMOV_V2F64:
20058 case X86::CMOV_V2I64:
20059 case X86::CMOV_V8F32:
20060 case X86::CMOV_V4F64:
20061 case X86::CMOV_V4I64:
20062 case X86::CMOV_V16F32:
20063 case X86::CMOV_V8F64:
20064 case X86::CMOV_V8I64:
20065 case X86::CMOV_GR16:
20066 case X86::CMOV_GR32:
20067 case X86::CMOV_RFP32:
20068 case X86::CMOV_RFP64:
20069 case X86::CMOV_RFP80:
20070 case X86::CMOV_V8I1:
20071 case X86::CMOV_V16I1:
20072 case X86::CMOV_V32I1:
20073 case X86::CMOV_V64I1:
20074 return EmitLoweredSelect(MI, BB);
20076 case X86::FP32_TO_INT16_IN_MEM:
20077 case X86::FP32_TO_INT32_IN_MEM:
20078 case X86::FP32_TO_INT64_IN_MEM:
20079 case X86::FP64_TO_INT16_IN_MEM:
20080 case X86::FP64_TO_INT32_IN_MEM:
20081 case X86::FP64_TO_INT64_IN_MEM:
20082 case X86::FP80_TO_INT16_IN_MEM:
20083 case X86::FP80_TO_INT32_IN_MEM:
20084 case X86::FP80_TO_INT64_IN_MEM: {
20085 MachineFunction *F = BB->getParent();
20086 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20087 DebugLoc DL = MI->getDebugLoc();
20089 // Change the floating point control register to use "round towards zero"
20090 // mode when truncating to an integer value.
20091 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20092 addFrameReference(BuildMI(*BB, MI, DL,
20093 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20095 // Load the old value of the high byte of the control word...
20097 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20098 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20101 // Set the high part to be round to zero...
20102 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20105 // Reload the modified control word now...
20106 addFrameReference(BuildMI(*BB, MI, DL,
20107 TII->get(X86::FLDCW16m)), CWFrameIdx);
20109 // Restore the memory image of control word to original value
20110 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20113 // Get the X86 opcode to use.
20115 switch (MI->getOpcode()) {
20116 default: llvm_unreachable("illegal opcode!");
20117 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20118 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20119 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20120 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20121 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20122 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20123 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20124 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20125 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20129 MachineOperand &Op = MI->getOperand(0);
20131 AM.BaseType = X86AddressMode::RegBase;
20132 AM.Base.Reg = Op.getReg();
20134 AM.BaseType = X86AddressMode::FrameIndexBase;
20135 AM.Base.FrameIndex = Op.getIndex();
20137 Op = MI->getOperand(1);
20139 AM.Scale = Op.getImm();
20140 Op = MI->getOperand(2);
20142 AM.IndexReg = Op.getImm();
20143 Op = MI->getOperand(3);
20144 if (Op.isGlobal()) {
20145 AM.GV = Op.getGlobal();
20147 AM.Disp = Op.getImm();
20149 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20150 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20152 // Reload the original control word now.
20153 addFrameReference(BuildMI(*BB, MI, DL,
20154 TII->get(X86::FLDCW16m)), CWFrameIdx);
20156 MI->eraseFromParent(); // The pseudo instruction is gone now.
20159 // String/text processing lowering.
20160 case X86::PCMPISTRM128REG:
20161 case X86::VPCMPISTRM128REG:
20162 case X86::PCMPISTRM128MEM:
20163 case X86::VPCMPISTRM128MEM:
20164 case X86::PCMPESTRM128REG:
20165 case X86::VPCMPESTRM128REG:
20166 case X86::PCMPESTRM128MEM:
20167 case X86::VPCMPESTRM128MEM:
20168 assert(Subtarget->hasSSE42() &&
20169 "Target must have SSE4.2 or AVX features enabled");
20170 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
20172 // String/text processing lowering.
20173 case X86::PCMPISTRIREG:
20174 case X86::VPCMPISTRIREG:
20175 case X86::PCMPISTRIMEM:
20176 case X86::VPCMPISTRIMEM:
20177 case X86::PCMPESTRIREG:
20178 case X86::VPCMPESTRIREG:
20179 case X86::PCMPESTRIMEM:
20180 case X86::VPCMPESTRIMEM:
20181 assert(Subtarget->hasSSE42() &&
20182 "Target must have SSE4.2 or AVX features enabled");
20183 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
20185 // Thread synchronization.
20187 return EmitMonitor(MI, BB, Subtarget);
20191 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
20193 case X86::VASTART_SAVE_XMM_REGS:
20194 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20196 case X86::VAARG_64:
20197 return EmitVAARG64WithCustomInserter(MI, BB);
20199 case X86::EH_SjLj_SetJmp32:
20200 case X86::EH_SjLj_SetJmp64:
20201 return emitEHSjLjSetJmp(MI, BB);
20203 case X86::EH_SjLj_LongJmp32:
20204 case X86::EH_SjLj_LongJmp64:
20205 return emitEHSjLjLongJmp(MI, BB);
20207 case TargetOpcode::STATEPOINT:
20208 // As an implementation detail, STATEPOINT shares the STACKMAP format at
20209 // this point in the process. We diverge later.
20210 return emitPatchPoint(MI, BB);
20212 case TargetOpcode::STACKMAP:
20213 case TargetOpcode::PATCHPOINT:
20214 return emitPatchPoint(MI, BB);
20216 case X86::VFMADDPDr213r:
20217 case X86::VFMADDPSr213r:
20218 case X86::VFMADDSDr213r:
20219 case X86::VFMADDSSr213r:
20220 case X86::VFMSUBPDr213r:
20221 case X86::VFMSUBPSr213r:
20222 case X86::VFMSUBSDr213r:
20223 case X86::VFMSUBSSr213r:
20224 case X86::VFNMADDPDr213r:
20225 case X86::VFNMADDPSr213r:
20226 case X86::VFNMADDSDr213r:
20227 case X86::VFNMADDSSr213r:
20228 case X86::VFNMSUBPDr213r:
20229 case X86::VFNMSUBPSr213r:
20230 case X86::VFNMSUBSDr213r:
20231 case X86::VFNMSUBSSr213r:
20232 case X86::VFMADDSUBPDr213r:
20233 case X86::VFMADDSUBPSr213r:
20234 case X86::VFMSUBADDPDr213r:
20235 case X86::VFMSUBADDPSr213r:
20236 case X86::VFMADDPDr213rY:
20237 case X86::VFMADDPSr213rY:
20238 case X86::VFMSUBPDr213rY:
20239 case X86::VFMSUBPSr213rY:
20240 case X86::VFNMADDPDr213rY:
20241 case X86::VFNMADDPSr213rY:
20242 case X86::VFNMSUBPDr213rY:
20243 case X86::VFNMSUBPSr213rY:
20244 case X86::VFMADDSUBPDr213rY:
20245 case X86::VFMADDSUBPSr213rY:
20246 case X86::VFMSUBADDPDr213rY:
20247 case X86::VFMSUBADDPSr213rY:
20248 return emitFMA3Instr(MI, BB);
20252 //===----------------------------------------------------------------------===//
20253 // X86 Optimization Hooks
20254 //===----------------------------------------------------------------------===//
20256 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20259 const SelectionDAG &DAG,
20260 unsigned Depth) const {
20261 unsigned BitWidth = KnownZero.getBitWidth();
20262 unsigned Opc = Op.getOpcode();
20263 assert((Opc >= ISD::BUILTIN_OP_END ||
20264 Opc == ISD::INTRINSIC_WO_CHAIN ||
20265 Opc == ISD::INTRINSIC_W_CHAIN ||
20266 Opc == ISD::INTRINSIC_VOID) &&
20267 "Should use MaskedValueIsZero if you don't know whether Op"
20268 " is a target node!");
20270 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20284 // These nodes' second result is a boolean.
20285 if (Op.getResNo() == 0)
20288 case X86ISD::SETCC:
20289 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20291 case ISD::INTRINSIC_WO_CHAIN: {
20292 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20293 unsigned NumLoBits = 0;
20296 case Intrinsic::x86_sse_movmsk_ps:
20297 case Intrinsic::x86_avx_movmsk_ps_256:
20298 case Intrinsic::x86_sse2_movmsk_pd:
20299 case Intrinsic::x86_avx_movmsk_pd_256:
20300 case Intrinsic::x86_mmx_pmovmskb:
20301 case Intrinsic::x86_sse2_pmovmskb_128:
20302 case Intrinsic::x86_avx2_pmovmskb: {
20303 // High bits of movmskp{s|d}, pmovmskb are known zero.
20305 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20306 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20307 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20308 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20309 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20310 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20311 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20312 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20314 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20323 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20325 const SelectionDAG &,
20326 unsigned Depth) const {
20327 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20328 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20329 return Op.getValueType().getScalarType().getSizeInBits();
20335 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20336 /// node is a GlobalAddress + offset.
20337 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20338 const GlobalValue* &GA,
20339 int64_t &Offset) const {
20340 if (N->getOpcode() == X86ISD::Wrapper) {
20341 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20342 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20343 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20347 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20350 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20351 /// same as extracting the high 128-bit part of 256-bit vector and then
20352 /// inserting the result into the low part of a new 256-bit vector
20353 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20354 EVT VT = SVOp->getValueType(0);
20355 unsigned NumElems = VT.getVectorNumElements();
20357 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20358 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20359 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20360 SVOp->getMaskElt(j) >= 0)
20366 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20367 /// same as extracting the low 128-bit part of 256-bit vector and then
20368 /// inserting the result into the high part of a new 256-bit vector
20369 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20370 EVT VT = SVOp->getValueType(0);
20371 unsigned NumElems = VT.getVectorNumElements();
20373 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20374 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20375 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20376 SVOp->getMaskElt(j) >= 0)
20382 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20383 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20384 TargetLowering::DAGCombinerInfo &DCI,
20385 const X86Subtarget* Subtarget) {
20387 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20388 SDValue V1 = SVOp->getOperand(0);
20389 SDValue V2 = SVOp->getOperand(1);
20390 EVT VT = SVOp->getValueType(0);
20391 unsigned NumElems = VT.getVectorNumElements();
20393 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20394 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20398 // V UNDEF BUILD_VECTOR UNDEF
20400 // CONCAT_VECTOR CONCAT_VECTOR
20403 // RESULT: V + zero extended
20405 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20406 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20407 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20410 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20413 // To match the shuffle mask, the first half of the mask should
20414 // be exactly the first vector, and all the rest a splat with the
20415 // first element of the second one.
20416 for (unsigned i = 0; i != NumElems/2; ++i)
20417 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20418 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20421 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20422 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20423 if (Ld->hasNUsesOfValue(1, 0)) {
20424 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20425 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20427 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20429 Ld->getPointerInfo(),
20430 Ld->getAlignment(),
20431 false/*isVolatile*/, true/*ReadMem*/,
20432 false/*WriteMem*/);
20434 // Make sure the newly-created LOAD is in the same position as Ld in
20435 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20436 // and update uses of Ld's output chain to use the TokenFactor.
20437 if (Ld->hasAnyUseOfValue(1)) {
20438 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20439 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20440 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20441 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20442 SDValue(ResNode.getNode(), 1));
20445 return DAG.getBitcast(VT, ResNode);
20449 // Emit a zeroed vector and insert the desired subvector on its
20451 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20452 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20453 return DCI.CombineTo(N, InsV);
20456 //===--------------------------------------------------------------------===//
20457 // Combine some shuffles into subvector extracts and inserts:
20460 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20461 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20462 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20463 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20464 return DCI.CombineTo(N, InsV);
20467 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20468 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20469 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20470 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20471 return DCI.CombineTo(N, InsV);
20477 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20480 /// This is the leaf of the recursive combinine below. When we have found some
20481 /// chain of single-use x86 shuffle instructions and accumulated the combined
20482 /// shuffle mask represented by them, this will try to pattern match that mask
20483 /// into either a single instruction if there is a special purpose instruction
20484 /// for this operation, or into a PSHUFB instruction which is a fully general
20485 /// instruction but should only be used to replace chains over a certain depth.
20486 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20487 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20488 TargetLowering::DAGCombinerInfo &DCI,
20489 const X86Subtarget *Subtarget) {
20490 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20492 // Find the operand that enters the chain. Note that multiple uses are OK
20493 // here, we're not going to remove the operand we find.
20494 SDValue Input = Op.getOperand(0);
20495 while (Input.getOpcode() == ISD::BITCAST)
20496 Input = Input.getOperand(0);
20498 MVT VT = Input.getSimpleValueType();
20499 MVT RootVT = Root.getSimpleValueType();
20502 // Just remove no-op shuffle masks.
20503 if (Mask.size() == 1) {
20504 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
20509 // Use the float domain if the operand type is a floating point type.
20510 bool FloatDomain = VT.isFloatingPoint();
20512 // For floating point shuffles, we don't have free copies in the shuffle
20513 // instructions or the ability to load as part of the instruction, so
20514 // canonicalize their shuffles to UNPCK or MOV variants.
20516 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20517 // vectors because it can have a load folded into it that UNPCK cannot. This
20518 // doesn't preclude something switching to the shorter encoding post-RA.
20520 // FIXME: Should teach these routines about AVX vector widths.
20521 if (FloatDomain && VT.getSizeInBits() == 128) {
20522 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
20523 bool Lo = Mask.equals({0, 0});
20526 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20527 // is no slower than UNPCKLPD but has the option to fold the input operand
20528 // into even an unaligned memory load.
20529 if (Lo && Subtarget->hasSSE3()) {
20530 Shuffle = X86ISD::MOVDDUP;
20531 ShuffleVT = MVT::v2f64;
20533 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20534 // than the UNPCK variants.
20535 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20536 ShuffleVT = MVT::v4f32;
20538 if (Depth == 1 && Root->getOpcode() == Shuffle)
20539 return false; // Nothing to do!
20540 Op = DAG.getBitcast(ShuffleVT, Input);
20541 DCI.AddToWorklist(Op.getNode());
20542 if (Shuffle == X86ISD::MOVDDUP)
20543 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20545 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20546 DCI.AddToWorklist(Op.getNode());
20547 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20551 if (Subtarget->hasSSE3() &&
20552 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
20553 bool Lo = Mask.equals({0, 0, 2, 2});
20554 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20555 MVT ShuffleVT = MVT::v4f32;
20556 if (Depth == 1 && Root->getOpcode() == Shuffle)
20557 return false; // Nothing to do!
20558 Op = DAG.getBitcast(ShuffleVT, Input);
20559 DCI.AddToWorklist(Op.getNode());
20560 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20561 DCI.AddToWorklist(Op.getNode());
20562 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20566 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
20567 bool Lo = Mask.equals({0, 0, 1, 1});
20568 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20569 MVT ShuffleVT = MVT::v4f32;
20570 if (Depth == 1 && Root->getOpcode() == Shuffle)
20571 return false; // Nothing to do!
20572 Op = DAG.getBitcast(ShuffleVT, Input);
20573 DCI.AddToWorklist(Op.getNode());
20574 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20575 DCI.AddToWorklist(Op.getNode());
20576 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20582 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20583 // variants as none of these have single-instruction variants that are
20584 // superior to the UNPCK formulation.
20585 if (!FloatDomain && VT.getSizeInBits() == 128 &&
20586 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20587 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
20588 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
20590 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
20591 bool Lo = Mask[0] == 0;
20592 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20593 if (Depth == 1 && Root->getOpcode() == Shuffle)
20594 return false; // Nothing to do!
20596 switch (Mask.size()) {
20598 ShuffleVT = MVT::v8i16;
20601 ShuffleVT = MVT::v16i8;
20604 llvm_unreachable("Impossible mask size!");
20606 Op = DAG.getBitcast(ShuffleVT, Input);
20607 DCI.AddToWorklist(Op.getNode());
20608 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20609 DCI.AddToWorklist(Op.getNode());
20610 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20615 // Don't try to re-form single instruction chains under any circumstances now
20616 // that we've done encoding canonicalization for them.
20620 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20621 // can replace them with a single PSHUFB instruction profitably. Intel's
20622 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20623 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20624 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20625 SmallVector<SDValue, 16> PSHUFBMask;
20626 int NumBytes = VT.getSizeInBits() / 8;
20627 int Ratio = NumBytes / Mask.size();
20628 for (int i = 0; i < NumBytes; ++i) {
20629 if (Mask[i / Ratio] == SM_SentinelUndef) {
20630 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20633 int M = Mask[i / Ratio] != SM_SentinelZero
20634 ? Ratio * Mask[i / Ratio] + i % Ratio
20636 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20638 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20639 Op = DAG.getBitcast(ByteVT, Input);
20640 DCI.AddToWorklist(Op.getNode());
20641 SDValue PSHUFBMaskOp =
20642 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20643 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20644 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20645 DCI.AddToWorklist(Op.getNode());
20646 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20651 // Failed to find any combines.
20655 /// \brief Fully generic combining of x86 shuffle instructions.
20657 /// This should be the last combine run over the x86 shuffle instructions. Once
20658 /// they have been fully optimized, this will recursively consider all chains
20659 /// of single-use shuffle instructions, build a generic model of the cumulative
20660 /// shuffle operation, and check for simpler instructions which implement this
20661 /// operation. We use this primarily for two purposes:
20663 /// 1) Collapse generic shuffles to specialized single instructions when
20664 /// equivalent. In most cases, this is just an encoding size win, but
20665 /// sometimes we will collapse multiple generic shuffles into a single
20666 /// special-purpose shuffle.
20667 /// 2) Look for sequences of shuffle instructions with 3 or more total
20668 /// instructions, and replace them with the slightly more expensive SSSE3
20669 /// PSHUFB instruction if available. We do this as the last combining step
20670 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20671 /// a suitable short sequence of other instructions. The PHUFB will either
20672 /// use a register or have to read from memory and so is slightly (but only
20673 /// slightly) more expensive than the other shuffle instructions.
20675 /// Because this is inherently a quadratic operation (for each shuffle in
20676 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20677 /// This should never be an issue in practice as the shuffle lowering doesn't
20678 /// produce sequences of more than 8 instructions.
20680 /// FIXME: We will currently miss some cases where the redundant shuffling
20681 /// would simplify under the threshold for PSHUFB formation because of
20682 /// combine-ordering. To fix this, we should do the redundant instruction
20683 /// combining in this recursive walk.
20684 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20685 ArrayRef<int> RootMask,
20686 int Depth, bool HasPSHUFB,
20688 TargetLowering::DAGCombinerInfo &DCI,
20689 const X86Subtarget *Subtarget) {
20690 // Bound the depth of our recursive combine because this is ultimately
20691 // quadratic in nature.
20695 // Directly rip through bitcasts to find the underlying operand.
20696 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20697 Op = Op.getOperand(0);
20699 MVT VT = Op.getSimpleValueType();
20700 if (!VT.isVector())
20701 return false; // Bail if we hit a non-vector.
20703 assert(Root.getSimpleValueType().isVector() &&
20704 "Shuffles operate on vector types!");
20705 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20706 "Can only combine shuffles of the same vector register size.");
20708 if (!isTargetShuffle(Op.getOpcode()))
20710 SmallVector<int, 16> OpMask;
20712 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20713 // We only can combine unary shuffles which we can decode the mask for.
20714 if (!HaveMask || !IsUnary)
20717 assert(VT.getVectorNumElements() == OpMask.size() &&
20718 "Different mask size from vector size!");
20719 assert(((RootMask.size() > OpMask.size() &&
20720 RootMask.size() % OpMask.size() == 0) ||
20721 (OpMask.size() > RootMask.size() &&
20722 OpMask.size() % RootMask.size() == 0) ||
20723 OpMask.size() == RootMask.size()) &&
20724 "The smaller number of elements must divide the larger.");
20725 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20726 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20727 assert(((RootRatio == 1 && OpRatio == 1) ||
20728 (RootRatio == 1) != (OpRatio == 1)) &&
20729 "Must not have a ratio for both incoming and op masks!");
20731 SmallVector<int, 16> Mask;
20732 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20734 // Merge this shuffle operation's mask into our accumulated mask. Note that
20735 // this shuffle's mask will be the first applied to the input, followed by the
20736 // root mask to get us all the way to the root value arrangement. The reason
20737 // for this order is that we are recursing up the operation chain.
20738 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20739 int RootIdx = i / RootRatio;
20740 if (RootMask[RootIdx] < 0) {
20741 // This is a zero or undef lane, we're done.
20742 Mask.push_back(RootMask[RootIdx]);
20746 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20747 int OpIdx = RootMaskedIdx / OpRatio;
20748 if (OpMask[OpIdx] < 0) {
20749 // The incoming lanes are zero or undef, it doesn't matter which ones we
20751 Mask.push_back(OpMask[OpIdx]);
20755 // Ok, we have non-zero lanes, map them through.
20756 Mask.push_back(OpMask[OpIdx] * OpRatio +
20757 RootMaskedIdx % OpRatio);
20760 // See if we can recurse into the operand to combine more things.
20761 switch (Op.getOpcode()) {
20762 case X86ISD::PSHUFB:
20764 case X86ISD::PSHUFD:
20765 case X86ISD::PSHUFHW:
20766 case X86ISD::PSHUFLW:
20767 if (Op.getOperand(0).hasOneUse() &&
20768 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20769 HasPSHUFB, DAG, DCI, Subtarget))
20773 case X86ISD::UNPCKL:
20774 case X86ISD::UNPCKH:
20775 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20776 // We can't check for single use, we have to check that this shuffle is the only user.
20777 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20778 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20779 HasPSHUFB, DAG, DCI, Subtarget))
20784 // Minor canonicalization of the accumulated shuffle mask to make it easier
20785 // to match below. All this does is detect masks with squential pairs of
20786 // elements, and shrink them to the half-width mask. It does this in a loop
20787 // so it will reduce the size of the mask to the minimal width mask which
20788 // performs an equivalent shuffle.
20789 SmallVector<int, 16> WidenedMask;
20790 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20791 Mask = std::move(WidenedMask);
20792 WidenedMask.clear();
20795 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20799 /// \brief Get the PSHUF-style mask from PSHUF node.
20801 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20802 /// PSHUF-style masks that can be reused with such instructions.
20803 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20804 MVT VT = N.getSimpleValueType();
20805 SmallVector<int, 4> Mask;
20807 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
20811 // If we have more than 128-bits, only the low 128-bits of shuffle mask
20812 // matter. Check that the upper masks are repeats and remove them.
20813 if (VT.getSizeInBits() > 128) {
20814 int LaneElts = 128 / VT.getScalarSizeInBits();
20816 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
20817 for (int j = 0; j < LaneElts; ++j)
20818 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
20819 "Mask doesn't repeat in high 128-bit lanes!");
20821 Mask.resize(LaneElts);
20824 switch (N.getOpcode()) {
20825 case X86ISD::PSHUFD:
20827 case X86ISD::PSHUFLW:
20830 case X86ISD::PSHUFHW:
20831 Mask.erase(Mask.begin(), Mask.begin() + 4);
20832 for (int &M : Mask)
20836 llvm_unreachable("No valid shuffle instruction found!");
20840 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20842 /// We walk up the chain and look for a combinable shuffle, skipping over
20843 /// shuffles that we could hoist this shuffle's transformation past without
20844 /// altering anything.
20846 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20848 TargetLowering::DAGCombinerInfo &DCI) {
20849 assert(N.getOpcode() == X86ISD::PSHUFD &&
20850 "Called with something other than an x86 128-bit half shuffle!");
20853 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20854 // of the shuffles in the chain so that we can form a fresh chain to replace
20856 SmallVector<SDValue, 8> Chain;
20857 SDValue V = N.getOperand(0);
20858 for (; V.hasOneUse(); V = V.getOperand(0)) {
20859 switch (V.getOpcode()) {
20861 return SDValue(); // Nothing combined!
20864 // Skip bitcasts as we always know the type for the target specific
20868 case X86ISD::PSHUFD:
20869 // Found another dword shuffle.
20872 case X86ISD::PSHUFLW:
20873 // Check that the low words (being shuffled) are the identity in the
20874 // dword shuffle, and the high words are self-contained.
20875 if (Mask[0] != 0 || Mask[1] != 1 ||
20876 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20879 Chain.push_back(V);
20882 case X86ISD::PSHUFHW:
20883 // Check that the high words (being shuffled) are the identity in the
20884 // dword shuffle, and the low words are self-contained.
20885 if (Mask[2] != 2 || Mask[3] != 3 ||
20886 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20889 Chain.push_back(V);
20892 case X86ISD::UNPCKL:
20893 case X86ISD::UNPCKH:
20894 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20895 // shuffle into a preceding word shuffle.
20896 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
20897 V.getSimpleValueType().getScalarType() != MVT::i16)
20900 // Search for a half-shuffle which we can combine with.
20901 unsigned CombineOp =
20902 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20903 if (V.getOperand(0) != V.getOperand(1) ||
20904 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20906 Chain.push_back(V);
20907 V = V.getOperand(0);
20909 switch (V.getOpcode()) {
20911 return SDValue(); // Nothing to combine.
20913 case X86ISD::PSHUFLW:
20914 case X86ISD::PSHUFHW:
20915 if (V.getOpcode() == CombineOp)
20918 Chain.push_back(V);
20922 V = V.getOperand(0);
20926 } while (V.hasOneUse());
20929 // Break out of the loop if we break out of the switch.
20933 if (!V.hasOneUse())
20934 // We fell out of the loop without finding a viable combining instruction.
20937 // Merge this node's mask and our incoming mask.
20938 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20939 for (int &M : Mask)
20941 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20942 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20944 // Rebuild the chain around this new shuffle.
20945 while (!Chain.empty()) {
20946 SDValue W = Chain.pop_back_val();
20948 if (V.getValueType() != W.getOperand(0).getValueType())
20949 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
20951 switch (W.getOpcode()) {
20953 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20955 case X86ISD::UNPCKL:
20956 case X86ISD::UNPCKH:
20957 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20960 case X86ISD::PSHUFD:
20961 case X86ISD::PSHUFLW:
20962 case X86ISD::PSHUFHW:
20963 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20967 if (V.getValueType() != N.getValueType())
20968 V = DAG.getBitcast(N.getValueType(), V);
20970 // Return the new chain to replace N.
20974 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20976 /// We walk up the chain, skipping shuffles of the other half and looking
20977 /// through shuffles which switch halves trying to find a shuffle of the same
20978 /// pair of dwords.
20979 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20981 TargetLowering::DAGCombinerInfo &DCI) {
20983 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20984 "Called with something other than an x86 128-bit half shuffle!");
20986 unsigned CombineOpcode = N.getOpcode();
20988 // Walk up a single-use chain looking for a combinable shuffle.
20989 SDValue V = N.getOperand(0);
20990 for (; V.hasOneUse(); V = V.getOperand(0)) {
20991 switch (V.getOpcode()) {
20993 return false; // Nothing combined!
20996 // Skip bitcasts as we always know the type for the target specific
21000 case X86ISD::PSHUFLW:
21001 case X86ISD::PSHUFHW:
21002 if (V.getOpcode() == CombineOpcode)
21005 // Other-half shuffles are no-ops.
21008 // Break out of the loop if we break out of the switch.
21012 if (!V.hasOneUse())
21013 // We fell out of the loop without finding a viable combining instruction.
21016 // Combine away the bottom node as its shuffle will be accumulated into
21017 // a preceding shuffle.
21018 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21020 // Record the old value.
21023 // Merge this node's mask and our incoming mask (adjusted to account for all
21024 // the pshufd instructions encountered).
21025 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21026 for (int &M : Mask)
21028 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21029 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21031 // Check that the shuffles didn't cancel each other out. If not, we need to
21032 // combine to the new one.
21034 // Replace the combinable shuffle with the combined one, updating all users
21035 // so that we re-evaluate the chain here.
21036 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21041 /// \brief Try to combine x86 target specific shuffles.
21042 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21043 TargetLowering::DAGCombinerInfo &DCI,
21044 const X86Subtarget *Subtarget) {
21046 MVT VT = N.getSimpleValueType();
21047 SmallVector<int, 4> Mask;
21049 switch (N.getOpcode()) {
21050 case X86ISD::PSHUFD:
21051 case X86ISD::PSHUFLW:
21052 case X86ISD::PSHUFHW:
21053 Mask = getPSHUFShuffleMask(N);
21054 assert(Mask.size() == 4);
21060 // Nuke no-op shuffles that show up after combining.
21061 if (isNoopShuffleMask(Mask))
21062 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21064 // Look for simplifications involving one or two shuffle instructions.
21065 SDValue V = N.getOperand(0);
21066 switch (N.getOpcode()) {
21069 case X86ISD::PSHUFLW:
21070 case X86ISD::PSHUFHW:
21071 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
21073 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21074 return SDValue(); // We combined away this shuffle, so we're done.
21076 // See if this reduces to a PSHUFD which is no more expensive and can
21077 // combine with more operations. Note that it has to at least flip the
21078 // dwords as otherwise it would have been removed as a no-op.
21079 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
21080 int DMask[] = {0, 1, 2, 3};
21081 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21082 DMask[DOffset + 0] = DOffset + 1;
21083 DMask[DOffset + 1] = DOffset + 0;
21084 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
21085 V = DAG.getBitcast(DVT, V);
21086 DCI.AddToWorklist(V.getNode());
21087 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
21088 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
21089 DCI.AddToWorklist(V.getNode());
21090 return DAG.getBitcast(VT, V);
21093 // Look for shuffle patterns which can be implemented as a single unpack.
21094 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21095 // only works when we have a PSHUFD followed by two half-shuffles.
21096 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21097 (V.getOpcode() == X86ISD::PSHUFLW ||
21098 V.getOpcode() == X86ISD::PSHUFHW) &&
21099 V.getOpcode() != N.getOpcode() &&
21101 SDValue D = V.getOperand(0);
21102 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21103 D = D.getOperand(0);
21104 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21105 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21106 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21107 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21108 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21110 for (int i = 0; i < 4; ++i) {
21111 WordMask[i + NOffset] = Mask[i] + NOffset;
21112 WordMask[i + VOffset] = VMask[i] + VOffset;
21114 // Map the word mask through the DWord mask.
21116 for (int i = 0; i < 8; ++i)
21117 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21118 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21119 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
21120 // We can replace all three shuffles with an unpack.
21121 V = DAG.getBitcast(VT, D.getOperand(0));
21122 DCI.AddToWorklist(V.getNode());
21123 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21132 case X86ISD::PSHUFD:
21133 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21142 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21144 /// We combine this directly on the abstract vector shuffle nodes so it is
21145 /// easier to generically match. We also insert dummy vector shuffle nodes for
21146 /// the operands which explicitly discard the lanes which are unused by this
21147 /// operation to try to flow through the rest of the combiner the fact that
21148 /// they're unused.
21149 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21151 EVT VT = N->getValueType(0);
21153 // We only handle target-independent shuffles.
21154 // FIXME: It would be easy and harmless to use the target shuffle mask
21155 // extraction tool to support more.
21156 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21159 auto *SVN = cast<ShuffleVectorSDNode>(N);
21160 ArrayRef<int> Mask = SVN->getMask();
21161 SDValue V1 = N->getOperand(0);
21162 SDValue V2 = N->getOperand(1);
21164 // We require the first shuffle operand to be the SUB node, and the second to
21165 // be the ADD node.
21166 // FIXME: We should support the commuted patterns.
21167 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21170 // If there are other uses of these operations we can't fold them.
21171 if (!V1->hasOneUse() || !V2->hasOneUse())
21174 // Ensure that both operations have the same operands. Note that we can
21175 // commute the FADD operands.
21176 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21177 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21178 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21181 // We're looking for blends between FADD and FSUB nodes. We insist on these
21182 // nodes being lined up in a specific expected pattern.
21183 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
21184 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
21185 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
21188 // Only specific types are legal at this point, assert so we notice if and
21189 // when these change.
21190 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21191 VT == MVT::v4f64) &&
21192 "Unknown vector type encountered!");
21194 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21197 /// PerformShuffleCombine - Performs several different shuffle combines.
21198 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21199 TargetLowering::DAGCombinerInfo &DCI,
21200 const X86Subtarget *Subtarget) {
21202 SDValue N0 = N->getOperand(0);
21203 SDValue N1 = N->getOperand(1);
21204 EVT VT = N->getValueType(0);
21206 // Don't create instructions with illegal types after legalize types has run.
21207 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21208 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21211 // If we have legalized the vector types, look for blends of FADD and FSUB
21212 // nodes that we can fuse into an ADDSUB node.
21213 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21214 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21217 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21218 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21219 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21220 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21222 // During Type Legalization, when promoting illegal vector types,
21223 // the backend might introduce new shuffle dag nodes and bitcasts.
21225 // This code performs the following transformation:
21226 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21227 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21229 // We do this only if both the bitcast and the BINOP dag nodes have
21230 // one use. Also, perform this transformation only if the new binary
21231 // operation is legal. This is to avoid introducing dag nodes that
21232 // potentially need to be further expanded (or custom lowered) into a
21233 // less optimal sequence of dag nodes.
21234 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21235 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21236 N0.getOpcode() == ISD::BITCAST) {
21237 SDValue BC0 = N0.getOperand(0);
21238 EVT SVT = BC0.getValueType();
21239 unsigned Opcode = BC0.getOpcode();
21240 unsigned NumElts = VT.getVectorNumElements();
21242 if (BC0.hasOneUse() && SVT.isVector() &&
21243 SVT.getVectorNumElements() * 2 == NumElts &&
21244 TLI.isOperationLegal(Opcode, VT)) {
21245 bool CanFold = false;
21257 unsigned SVTNumElts = SVT.getVectorNumElements();
21258 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21259 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21260 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21261 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21262 CanFold = SVOp->getMaskElt(i) < 0;
21265 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
21266 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
21267 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21268 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21273 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21274 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21275 // consecutive, non-overlapping, and in the right order.
21276 SmallVector<SDValue, 16> Elts;
21277 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21278 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21280 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
21283 if (isTargetShuffle(N->getOpcode())) {
21285 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21286 if (Shuffle.getNode())
21289 // Try recursively combining arbitrary sequences of x86 shuffle
21290 // instructions into higher-order shuffles. We do this after combining
21291 // specific PSHUF instruction sequences into their minimal form so that we
21292 // can evaluate how many specialized shuffle instructions are involved in
21293 // a particular chain.
21294 SmallVector<int, 1> NonceMask; // Just a placeholder.
21295 NonceMask.push_back(0);
21296 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21297 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21299 return SDValue(); // This routine will use CombineTo to replace N.
21305 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21306 /// specific shuffle of a load can be folded into a single element load.
21307 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21308 /// shuffles have been custom lowered so we need to handle those here.
21309 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21310 TargetLowering::DAGCombinerInfo &DCI) {
21311 if (DCI.isBeforeLegalizeOps())
21314 SDValue InVec = N->getOperand(0);
21315 SDValue EltNo = N->getOperand(1);
21317 if (!isa<ConstantSDNode>(EltNo))
21320 EVT OriginalVT = InVec.getValueType();
21322 if (InVec.getOpcode() == ISD::BITCAST) {
21323 // Don't duplicate a load with other uses.
21324 if (!InVec.hasOneUse())
21326 EVT BCVT = InVec.getOperand(0).getValueType();
21327 if (!BCVT.isVector() ||
21328 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
21330 InVec = InVec.getOperand(0);
21333 EVT CurrentVT = InVec.getValueType();
21335 if (!isTargetShuffle(InVec.getOpcode()))
21338 // Don't duplicate a load with other uses.
21339 if (!InVec.hasOneUse())
21342 SmallVector<int, 16> ShuffleMask;
21344 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
21345 ShuffleMask, UnaryShuffle))
21348 // Select the input vector, guarding against out of range extract vector.
21349 unsigned NumElems = CurrentVT.getVectorNumElements();
21350 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21351 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21352 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21353 : InVec.getOperand(1);
21355 // If inputs to shuffle are the same for both ops, then allow 2 uses
21356 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
21357 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21359 if (LdNode.getOpcode() == ISD::BITCAST) {
21360 // Don't duplicate a load with other uses.
21361 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21364 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21365 LdNode = LdNode.getOperand(0);
21368 if (!ISD::isNormalLoad(LdNode.getNode()))
21371 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21373 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21376 EVT EltVT = N->getValueType(0);
21377 // If there's a bitcast before the shuffle, check if the load type and
21378 // alignment is valid.
21379 unsigned Align = LN0->getAlignment();
21380 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21381 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21382 EltVT.getTypeForEVT(*DAG.getContext()));
21384 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21387 // All checks match so transform back to vector_shuffle so that DAG combiner
21388 // can finish the job
21391 // Create shuffle node taking into account the case that its a unary shuffle
21392 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
21393 : InVec.getOperand(1);
21394 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
21395 InVec.getOperand(0), Shuffle,
21397 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
21398 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21402 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
21403 /// special and don't usually play with other vector types, it's better to
21404 /// handle them early to be sure we emit efficient code by avoiding
21405 /// store-load conversions.
21406 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
21407 if (N->getValueType(0) != MVT::x86mmx ||
21408 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
21409 N->getOperand(0)->getValueType(0) != MVT::v2i32)
21412 SDValue V = N->getOperand(0);
21413 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
21414 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
21415 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
21416 N->getValueType(0), V.getOperand(0));
21421 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21422 /// generation and convert it from being a bunch of shuffles and extracts
21423 /// into a somewhat faster sequence. For i686, the best sequence is apparently
21424 /// storing the value and loading scalars back, while for x64 we should
21425 /// use 64-bit extracts and shifts.
21426 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21427 TargetLowering::DAGCombinerInfo &DCI) {
21428 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
21431 SDValue InputVector = N->getOperand(0);
21432 SDLoc dl(InputVector);
21433 // Detect mmx to i32 conversion through a v2i32 elt extract.
21434 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
21435 N->getValueType(0) == MVT::i32 &&
21436 InputVector.getValueType() == MVT::v2i32) {
21438 // The bitcast source is a direct mmx result.
21439 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
21440 if (MMXSrc.getValueType() == MVT::x86mmx)
21441 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21442 N->getValueType(0),
21443 InputVector.getNode()->getOperand(0));
21445 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
21446 SDValue MMXSrcOp = MMXSrc.getOperand(0);
21447 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
21448 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
21449 MMXSrcOp.getOpcode() == ISD::BITCAST &&
21450 MMXSrcOp.getValueType() == MVT::v1i64 &&
21451 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
21452 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21453 N->getValueType(0),
21454 MMXSrcOp.getOperand(0));
21457 EVT VT = N->getValueType(0);
21459 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
21460 InputVector.getOpcode() == ISD::BITCAST &&
21461 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
21462 uint64_t ExtractedElt =
21463 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
21464 uint64_t InputValue =
21465 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
21466 uint64_t Res = (InputValue >> ExtractedElt) & 1;
21467 return DAG.getConstant(Res, dl, MVT::i1);
21469 // Only operate on vectors of 4 elements, where the alternative shuffling
21470 // gets to be more expensive.
21471 if (InputVector.getValueType() != MVT::v4i32)
21474 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21475 // single use which is a sign-extend or zero-extend, and all elements are
21477 SmallVector<SDNode *, 4> Uses;
21478 unsigned ExtractedElements = 0;
21479 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21480 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21481 if (UI.getUse().getResNo() != InputVector.getResNo())
21484 SDNode *Extract = *UI;
21485 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21488 if (Extract->getValueType(0) != MVT::i32)
21490 if (!Extract->hasOneUse())
21492 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21493 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21495 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21498 // Record which element was extracted.
21499 ExtractedElements |=
21500 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21502 Uses.push_back(Extract);
21505 // If not all the elements were used, this may not be worthwhile.
21506 if (ExtractedElements != 15)
21509 // Ok, we've now decided to do the transformation.
21510 // If 64-bit shifts are legal, use the extract-shift sequence,
21511 // otherwise bounce the vector off the cache.
21512 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21515 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
21516 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
21517 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
21518 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21519 DAG.getConstant(0, dl, VecIdxTy));
21520 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21521 DAG.getConstant(1, dl, VecIdxTy));
21523 SDValue ShAmt = DAG.getConstant(32, dl,
21524 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
21525 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
21526 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21527 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
21528 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
21529 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21530 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
21532 // Store the value to a temporary stack slot.
21533 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21534 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21535 MachinePointerInfo(), false, false, 0);
21537 EVT ElementType = InputVector.getValueType().getVectorElementType();
21538 unsigned EltSize = ElementType.getSizeInBits() / 8;
21540 // Replace each use (extract) with a load of the appropriate element.
21541 for (unsigned i = 0; i < 4; ++i) {
21542 uint64_t Offset = EltSize * i;
21543 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
21545 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21546 StackPtr, OffsetVal);
21548 // Load the scalar.
21549 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
21550 ScalarAddr, MachinePointerInfo(),
21551 false, false, false, 0);
21556 // Replace the extracts
21557 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21558 UE = Uses.end(); UI != UE; ++UI) {
21559 SDNode *Extract = *UI;
21561 SDValue Idx = Extract->getOperand(1);
21562 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
21563 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21566 // The replacement was made in place; don't return anything.
21570 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21571 static std::pair<unsigned, bool>
21572 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21573 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21574 if (!VT.isVector())
21575 return std::make_pair(0, false);
21577 bool NeedSplit = false;
21578 switch (VT.getSimpleVT().SimpleTy) {
21579 default: return std::make_pair(0, false);
21582 if (!Subtarget->hasVLX())
21583 return std::make_pair(0, false);
21587 if (!Subtarget->hasBWI())
21588 return std::make_pair(0, false);
21592 if (!Subtarget->hasAVX512())
21593 return std::make_pair(0, false);
21598 if (!Subtarget->hasAVX2())
21600 if (!Subtarget->hasAVX())
21601 return std::make_pair(0, false);
21606 if (!Subtarget->hasSSE2())
21607 return std::make_pair(0, false);
21610 // SSE2 has only a small subset of the operations.
21611 bool hasUnsigned = Subtarget->hasSSE41() ||
21612 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21613 bool hasSigned = Subtarget->hasSSE41() ||
21614 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21616 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21619 // Check for x CC y ? x : y.
21620 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21621 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21626 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21629 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21632 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21635 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21637 // Check for x CC y ? y : x -- a min/max with reversed arms.
21638 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21639 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21644 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21647 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21650 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21653 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21657 return std::make_pair(Opc, NeedSplit);
21661 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21662 const X86Subtarget *Subtarget) {
21664 SDValue Cond = N->getOperand(0);
21665 SDValue LHS = N->getOperand(1);
21666 SDValue RHS = N->getOperand(2);
21668 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21669 SDValue CondSrc = Cond->getOperand(0);
21670 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21671 Cond = CondSrc->getOperand(0);
21674 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21677 // A vselect where all conditions and data are constants can be optimized into
21678 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21679 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21680 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21683 unsigned MaskValue = 0;
21684 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21687 MVT VT = N->getSimpleValueType(0);
21688 unsigned NumElems = VT.getVectorNumElements();
21689 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21690 for (unsigned i = 0; i < NumElems; ++i) {
21691 // Be sure we emit undef where we can.
21692 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21693 ShuffleMask[i] = -1;
21695 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21698 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21699 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21701 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21704 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21706 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21707 TargetLowering::DAGCombinerInfo &DCI,
21708 const X86Subtarget *Subtarget) {
21710 SDValue Cond = N->getOperand(0);
21711 // Get the LHS/RHS of the select.
21712 SDValue LHS = N->getOperand(1);
21713 SDValue RHS = N->getOperand(2);
21714 EVT VT = LHS.getValueType();
21715 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21717 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21718 // instructions match the semantics of the common C idiom x<y?x:y but not
21719 // x<=y?x:y, because of how they handle negative zero (which can be
21720 // ignored in unsafe-math mode).
21721 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
21722 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21723 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
21724 (Subtarget->hasSSE2() ||
21725 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21726 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21728 unsigned Opcode = 0;
21729 // Check for x CC y ? x : y.
21730 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21731 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21735 // Converting this to a min would handle NaNs incorrectly, and swapping
21736 // the operands would cause it to handle comparisons between positive
21737 // and negative zero incorrectly.
21738 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21739 if (!DAG.getTarget().Options.UnsafeFPMath &&
21740 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21742 std::swap(LHS, RHS);
21744 Opcode = X86ISD::FMIN;
21747 // Converting this to a min would handle comparisons between positive
21748 // and negative zero incorrectly.
21749 if (!DAG.getTarget().Options.UnsafeFPMath &&
21750 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21752 Opcode = X86ISD::FMIN;
21755 // Converting this to a min would handle both negative zeros and NaNs
21756 // incorrectly, but we can swap the operands to fix both.
21757 std::swap(LHS, RHS);
21761 Opcode = X86ISD::FMIN;
21765 // Converting this to a max would handle comparisons between positive
21766 // and negative zero incorrectly.
21767 if (!DAG.getTarget().Options.UnsafeFPMath &&
21768 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21770 Opcode = X86ISD::FMAX;
21773 // Converting this to a max would handle NaNs incorrectly, and swapping
21774 // the operands would cause it to handle comparisons between positive
21775 // and negative zero incorrectly.
21776 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21777 if (!DAG.getTarget().Options.UnsafeFPMath &&
21778 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21780 std::swap(LHS, RHS);
21782 Opcode = X86ISD::FMAX;
21785 // Converting this to a max would handle both negative zeros and NaNs
21786 // incorrectly, but we can swap the operands to fix both.
21787 std::swap(LHS, RHS);
21791 Opcode = X86ISD::FMAX;
21794 // Check for x CC y ? y : x -- a min/max with reversed arms.
21795 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21796 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21800 // Converting this to a min would handle comparisons between positive
21801 // and negative zero incorrectly, and swapping the operands would
21802 // cause it to handle NaNs incorrectly.
21803 if (!DAG.getTarget().Options.UnsafeFPMath &&
21804 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21805 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21807 std::swap(LHS, RHS);
21809 Opcode = X86ISD::FMIN;
21812 // Converting this to a min would handle NaNs incorrectly.
21813 if (!DAG.getTarget().Options.UnsafeFPMath &&
21814 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21816 Opcode = X86ISD::FMIN;
21819 // Converting this to a min would handle both negative zeros and NaNs
21820 // incorrectly, but we can swap the operands to fix both.
21821 std::swap(LHS, RHS);
21825 Opcode = X86ISD::FMIN;
21829 // Converting this to a max would handle NaNs incorrectly.
21830 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21832 Opcode = X86ISD::FMAX;
21835 // Converting this to a max would handle comparisons between positive
21836 // and negative zero incorrectly, and swapping the operands would
21837 // cause it to handle NaNs incorrectly.
21838 if (!DAG.getTarget().Options.UnsafeFPMath &&
21839 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21840 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21842 std::swap(LHS, RHS);
21844 Opcode = X86ISD::FMAX;
21847 // Converting this to a max would handle both negative zeros and NaNs
21848 // incorrectly, but we can swap the operands to fix both.
21849 std::swap(LHS, RHS);
21853 Opcode = X86ISD::FMAX;
21859 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21862 EVT CondVT = Cond.getValueType();
21863 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21864 CondVT.getVectorElementType() == MVT::i1) {
21865 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21866 // lowering on KNL. In this case we convert it to
21867 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21868 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21869 // Since SKX these selects have a proper lowering.
21870 EVT OpVT = LHS.getValueType();
21871 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21872 (OpVT.getVectorElementType() == MVT::i8 ||
21873 OpVT.getVectorElementType() == MVT::i16) &&
21874 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21875 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21876 DCI.AddToWorklist(Cond.getNode());
21877 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21880 // If this is a select between two integer constants, try to do some
21882 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21883 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21884 // Don't do this for crazy integer types.
21885 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21886 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21887 // so that TrueC (the true value) is larger than FalseC.
21888 bool NeedsCondInvert = false;
21890 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21891 // Efficiently invertible.
21892 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21893 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21894 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21895 NeedsCondInvert = true;
21896 std::swap(TrueC, FalseC);
21899 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21900 if (FalseC->getAPIntValue() == 0 &&
21901 TrueC->getAPIntValue().isPowerOf2()) {
21902 if (NeedsCondInvert) // Invert the condition if needed.
21903 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21904 DAG.getConstant(1, DL, Cond.getValueType()));
21906 // Zero extend the condition if needed.
21907 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21909 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21910 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21911 DAG.getConstant(ShAmt, DL, MVT::i8));
21914 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21915 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21916 if (NeedsCondInvert) // Invert the condition if needed.
21917 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21918 DAG.getConstant(1, DL, Cond.getValueType()));
21920 // Zero extend the condition if needed.
21921 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21922 FalseC->getValueType(0), Cond);
21923 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21924 SDValue(FalseC, 0));
21927 // Optimize cases that will turn into an LEA instruction. This requires
21928 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21929 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21930 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21931 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21933 bool isFastMultiplier = false;
21935 switch ((unsigned char)Diff) {
21937 case 1: // result = add base, cond
21938 case 2: // result = lea base( , cond*2)
21939 case 3: // result = lea base(cond, cond*2)
21940 case 4: // result = lea base( , cond*4)
21941 case 5: // result = lea base(cond, cond*4)
21942 case 8: // result = lea base( , cond*8)
21943 case 9: // result = lea base(cond, cond*8)
21944 isFastMultiplier = true;
21949 if (isFastMultiplier) {
21950 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21951 if (NeedsCondInvert) // Invert the condition if needed.
21952 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21953 DAG.getConstant(1, DL, Cond.getValueType()));
21955 // Zero extend the condition if needed.
21956 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21958 // Scale the condition by the difference.
21960 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21961 DAG.getConstant(Diff, DL,
21962 Cond.getValueType()));
21964 // Add the base if non-zero.
21965 if (FalseC->getAPIntValue() != 0)
21966 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21967 SDValue(FalseC, 0));
21974 // Canonicalize max and min:
21975 // (x > y) ? x : y -> (x >= y) ? x : y
21976 // (x < y) ? x : y -> (x <= y) ? x : y
21977 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21978 // the need for an extra compare
21979 // against zero. e.g.
21980 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21982 // testl %edi, %edi
21984 // cmovgl %edi, %eax
21988 // cmovsl %eax, %edi
21989 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21990 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21991 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21992 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21997 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21998 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21999 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22000 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22005 // Early exit check
22006 if (!TLI.isTypeLegal(VT))
22009 // Match VSELECTs into subs with unsigned saturation.
22010 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22011 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22012 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22013 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22014 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22016 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22017 // left side invert the predicate to simplify logic below.
22019 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22021 CC = ISD::getSetCCInverse(CC, true);
22022 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22026 if (Other.getNode() && Other->getNumOperands() == 2 &&
22027 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22028 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22029 SDValue CondRHS = Cond->getOperand(1);
22031 // Look for a general sub with unsigned saturation first.
22032 // x >= y ? x-y : 0 --> subus x, y
22033 // x > y ? x-y : 0 --> subus x, y
22034 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22035 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22036 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22038 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22039 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22040 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22041 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22042 // If the RHS is a constant we have to reverse the const
22043 // canonicalization.
22044 // x > C-1 ? x+-C : 0 --> subus x, C
22045 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22046 CondRHSConst->getAPIntValue() ==
22047 (-OpRHSConst->getAPIntValue() - 1))
22048 return DAG.getNode(
22049 X86ISD::SUBUS, DL, VT, OpLHS,
22050 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
22052 // Another special case: If C was a sign bit, the sub has been
22053 // canonicalized into a xor.
22054 // FIXME: Would it be better to use computeKnownBits to determine
22055 // whether it's safe to decanonicalize the xor?
22056 // x s< 0 ? x^C : 0 --> subus x, C
22057 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22058 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22059 OpRHSConst->getAPIntValue().isSignBit())
22060 // Note that we have to rebuild the RHS constant here to ensure we
22061 // don't rely on particular values of undef lanes.
22062 return DAG.getNode(
22063 X86ISD::SUBUS, DL, VT, OpLHS,
22064 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
22069 // Try to match a min/max vector operation.
22070 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22071 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22072 unsigned Opc = ret.first;
22073 bool NeedSplit = ret.second;
22075 if (Opc && NeedSplit) {
22076 unsigned NumElems = VT.getVectorNumElements();
22077 // Extract the LHS vectors
22078 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22079 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22081 // Extract the RHS vectors
22082 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22083 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22085 // Create min/max for each subvector
22086 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22087 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22089 // Merge the result
22090 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22092 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22095 // Simplify vector selection if condition value type matches vselect
22097 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22098 assert(Cond.getValueType().isVector() &&
22099 "vector select expects a vector selector!");
22101 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22102 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22104 // Try invert the condition if true value is not all 1s and false value
22106 if (!TValIsAllOnes && !FValIsAllZeros &&
22107 // Check if the selector will be produced by CMPP*/PCMP*
22108 Cond.getOpcode() == ISD::SETCC &&
22109 // Check if SETCC has already been promoted
22110 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22111 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22112 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22114 if (TValIsAllZeros || FValIsAllOnes) {
22115 SDValue CC = Cond.getOperand(2);
22116 ISD::CondCode NewCC =
22117 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22118 Cond.getOperand(0).getValueType().isInteger());
22119 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22120 std::swap(LHS, RHS);
22121 TValIsAllOnes = FValIsAllOnes;
22122 FValIsAllZeros = TValIsAllZeros;
22126 if (TValIsAllOnes || FValIsAllZeros) {
22129 if (TValIsAllOnes && FValIsAllZeros)
22131 else if (TValIsAllOnes)
22133 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
22134 else if (FValIsAllZeros)
22135 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22136 DAG.getBitcast(CondVT, LHS));
22138 return DAG.getBitcast(VT, Ret);
22142 // We should generate an X86ISD::BLENDI from a vselect if its argument
22143 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22144 // constants. This specific pattern gets generated when we split a
22145 // selector for a 512 bit vector in a machine without AVX512 (but with
22146 // 256-bit vectors), during legalization:
22148 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22150 // Iff we find this pattern and the build_vectors are built from
22151 // constants, we translate the vselect into a shuffle_vector that we
22152 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22153 if ((N->getOpcode() == ISD::VSELECT ||
22154 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22155 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
22156 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22157 if (Shuffle.getNode())
22161 // If this is a *dynamic* select (non-constant condition) and we can match
22162 // this node with one of the variable blend instructions, restructure the
22163 // condition so that the blends can use the high bit of each element and use
22164 // SimplifyDemandedBits to simplify the condition operand.
22165 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22166 !DCI.isBeforeLegalize() &&
22167 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22168 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22170 // Don't optimize vector selects that map to mask-registers.
22174 // We can only handle the cases where VSELECT is directly legal on the
22175 // subtarget. We custom lower VSELECT nodes with constant conditions and
22176 // this makes it hard to see whether a dynamic VSELECT will correctly
22177 // lower, so we both check the operation's status and explicitly handle the
22178 // cases where a *dynamic* blend will fail even though a constant-condition
22179 // blend could be custom lowered.
22180 // FIXME: We should find a better way to handle this class of problems.
22181 // Potentially, we should combine constant-condition vselect nodes
22182 // pre-legalization into shuffles and not mark as many types as custom
22184 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
22186 // FIXME: We don't support i16-element blends currently. We could and
22187 // should support them by making *all* the bits in the condition be set
22188 // rather than just the high bit and using an i8-element blend.
22189 if (VT.getScalarType() == MVT::i16)
22191 // Dynamic blending was only available from SSE4.1 onward.
22192 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
22194 // Byte blends are only available in AVX2
22195 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
22196 !Subtarget->hasAVX2())
22199 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22200 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22202 APInt KnownZero, KnownOne;
22203 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22204 DCI.isBeforeLegalizeOps());
22205 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22206 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22208 // If we changed the computation somewhere in the DAG, this change
22209 // will affect all users of Cond.
22210 // Make sure it is fine and update all the nodes so that we do not
22211 // use the generic VSELECT anymore. Otherwise, we may perform
22212 // wrong optimizations as we messed up with the actual expectation
22213 // for the vector boolean values.
22214 if (Cond != TLO.Old) {
22215 // Check all uses of that condition operand to check whether it will be
22216 // consumed by non-BLEND instructions, which may depend on all bits are
22218 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22220 if (I->getOpcode() != ISD::VSELECT)
22221 // TODO: Add other opcodes eventually lowered into BLEND.
22224 // Update all the users of the condition, before committing the change,
22225 // so that the VSELECT optimizations that expect the correct vector
22226 // boolean value will not be triggered.
22227 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22229 DAG.ReplaceAllUsesOfValueWith(
22231 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22232 Cond, I->getOperand(1), I->getOperand(2)));
22233 DCI.CommitTargetLoweringOpt(TLO);
22236 // At this point, only Cond is changed. Change the condition
22237 // just for N to keep the opportunity to optimize all other
22238 // users their own way.
22239 DAG.ReplaceAllUsesOfValueWith(
22241 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22242 TLO.New, N->getOperand(1), N->getOperand(2)));
22250 // Check whether a boolean test is testing a boolean value generated by
22251 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22254 // Simplify the following patterns:
22255 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22256 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22257 // to (Op EFLAGS Cond)
22259 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22260 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22261 // to (Op EFLAGS !Cond)
22263 // where Op could be BRCOND or CMOV.
22265 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22266 // Quit if not CMP and SUB with its value result used.
22267 if (Cmp.getOpcode() != X86ISD::CMP &&
22268 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22271 // Quit if not used as a boolean value.
22272 if (CC != X86::COND_E && CC != X86::COND_NE)
22275 // Check CMP operands. One of them should be 0 or 1 and the other should be
22276 // an SetCC or extended from it.
22277 SDValue Op1 = Cmp.getOperand(0);
22278 SDValue Op2 = Cmp.getOperand(1);
22281 const ConstantSDNode* C = nullptr;
22282 bool needOppositeCond = (CC == X86::COND_E);
22283 bool checkAgainstTrue = false; // Is it a comparison against 1?
22285 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22287 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22289 else // Quit if all operands are not constants.
22292 if (C->getZExtValue() == 1) {
22293 needOppositeCond = !needOppositeCond;
22294 checkAgainstTrue = true;
22295 } else if (C->getZExtValue() != 0)
22296 // Quit if the constant is neither 0 or 1.
22299 bool truncatedToBoolWithAnd = false;
22300 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22301 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22302 SetCC.getOpcode() == ISD::TRUNCATE ||
22303 SetCC.getOpcode() == ISD::AND) {
22304 if (SetCC.getOpcode() == ISD::AND) {
22306 ConstantSDNode *CS;
22307 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22308 CS->getZExtValue() == 1)
22310 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22311 CS->getZExtValue() == 1)
22315 SetCC = SetCC.getOperand(OpIdx);
22316 truncatedToBoolWithAnd = true;
22318 SetCC = SetCC.getOperand(0);
22321 switch (SetCC.getOpcode()) {
22322 case X86ISD::SETCC_CARRY:
22323 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22324 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22325 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22326 // truncated to i1 using 'and'.
22327 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22329 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22330 "Invalid use of SETCC_CARRY!");
22332 case X86ISD::SETCC:
22333 // Set the condition code or opposite one if necessary.
22334 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22335 if (needOppositeCond)
22336 CC = X86::GetOppositeBranchCondition(CC);
22337 return SetCC.getOperand(1);
22338 case X86ISD::CMOV: {
22339 // Check whether false/true value has canonical one, i.e. 0 or 1.
22340 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22341 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22342 // Quit if true value is not a constant.
22345 // Quit if false value is not a constant.
22347 SDValue Op = SetCC.getOperand(0);
22348 // Skip 'zext' or 'trunc' node.
22349 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22350 Op.getOpcode() == ISD::TRUNCATE)
22351 Op = Op.getOperand(0);
22352 // A special case for rdrand/rdseed, where 0 is set if false cond is
22354 if ((Op.getOpcode() != X86ISD::RDRAND &&
22355 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22358 // Quit if false value is not the constant 0 or 1.
22359 bool FValIsFalse = true;
22360 if (FVal && FVal->getZExtValue() != 0) {
22361 if (FVal->getZExtValue() != 1)
22363 // If FVal is 1, opposite cond is needed.
22364 needOppositeCond = !needOppositeCond;
22365 FValIsFalse = false;
22367 // Quit if TVal is not the constant opposite of FVal.
22368 if (FValIsFalse && TVal->getZExtValue() != 1)
22370 if (!FValIsFalse && TVal->getZExtValue() != 0)
22372 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22373 if (needOppositeCond)
22374 CC = X86::GetOppositeBranchCondition(CC);
22375 return SetCC.getOperand(3);
22382 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
22384 /// (X86or (X86setcc) (X86setcc))
22385 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
22386 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
22387 X86::CondCode &CC1, SDValue &Flags,
22389 if (Cond->getOpcode() == X86ISD::CMP) {
22390 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
22391 if (!CondOp1C || !CondOp1C->isNullValue())
22394 Cond = Cond->getOperand(0);
22399 SDValue SetCC0, SetCC1;
22400 switch (Cond->getOpcode()) {
22401 default: return false;
22408 SetCC0 = Cond->getOperand(0);
22409 SetCC1 = Cond->getOperand(1);
22413 // Make sure we have SETCC nodes, using the same flags value.
22414 if (SetCC0.getOpcode() != X86ISD::SETCC ||
22415 SetCC1.getOpcode() != X86ISD::SETCC ||
22416 SetCC0->getOperand(1) != SetCC1->getOperand(1))
22419 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
22420 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
22421 Flags = SetCC0->getOperand(1);
22425 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22426 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22427 TargetLowering::DAGCombinerInfo &DCI,
22428 const X86Subtarget *Subtarget) {
22431 // If the flag operand isn't dead, don't touch this CMOV.
22432 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22435 SDValue FalseOp = N->getOperand(0);
22436 SDValue TrueOp = N->getOperand(1);
22437 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22438 SDValue Cond = N->getOperand(3);
22440 if (CC == X86::COND_E || CC == X86::COND_NE) {
22441 switch (Cond.getOpcode()) {
22445 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22446 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22447 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22453 Flags = checkBoolTestSetCCCombine(Cond, CC);
22454 if (Flags.getNode() &&
22455 // Extra check as FCMOV only supports a subset of X86 cond.
22456 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22457 SDValue Ops[] = { FalseOp, TrueOp,
22458 DAG.getConstant(CC, DL, MVT::i8), Flags };
22459 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22462 // If this is a select between two integer constants, try to do some
22463 // optimizations. Note that the operands are ordered the opposite of SELECT
22465 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22466 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22467 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22468 // larger than FalseC (the false value).
22469 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22470 CC = X86::GetOppositeBranchCondition(CC);
22471 std::swap(TrueC, FalseC);
22472 std::swap(TrueOp, FalseOp);
22475 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22476 // This is efficient for any integer data type (including i8/i16) and
22478 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22479 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22480 DAG.getConstant(CC, DL, MVT::i8), Cond);
22482 // Zero extend the condition if needed.
22483 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22485 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22486 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22487 DAG.getConstant(ShAmt, DL, MVT::i8));
22488 if (N->getNumValues() == 2) // Dead flag value?
22489 return DCI.CombineTo(N, Cond, SDValue());
22493 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22494 // for any integer data type, including i8/i16.
22495 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22496 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22497 DAG.getConstant(CC, DL, MVT::i8), Cond);
22499 // Zero extend the condition if needed.
22500 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22501 FalseC->getValueType(0), Cond);
22502 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22503 SDValue(FalseC, 0));
22505 if (N->getNumValues() == 2) // Dead flag value?
22506 return DCI.CombineTo(N, Cond, SDValue());
22510 // Optimize cases that will turn into an LEA instruction. This requires
22511 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22512 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22513 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22514 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22516 bool isFastMultiplier = false;
22518 switch ((unsigned char)Diff) {
22520 case 1: // result = add base, cond
22521 case 2: // result = lea base( , cond*2)
22522 case 3: // result = lea base(cond, cond*2)
22523 case 4: // result = lea base( , cond*4)
22524 case 5: // result = lea base(cond, cond*4)
22525 case 8: // result = lea base( , cond*8)
22526 case 9: // result = lea base(cond, cond*8)
22527 isFastMultiplier = true;
22532 if (isFastMultiplier) {
22533 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22534 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22535 DAG.getConstant(CC, DL, MVT::i8), Cond);
22536 // Zero extend the condition if needed.
22537 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22539 // Scale the condition by the difference.
22541 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22542 DAG.getConstant(Diff, DL, Cond.getValueType()));
22544 // Add the base if non-zero.
22545 if (FalseC->getAPIntValue() != 0)
22546 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22547 SDValue(FalseC, 0));
22548 if (N->getNumValues() == 2) // Dead flag value?
22549 return DCI.CombineTo(N, Cond, SDValue());
22556 // Handle these cases:
22557 // (select (x != c), e, c) -> select (x != c), e, x),
22558 // (select (x == c), c, e) -> select (x == c), x, e)
22559 // where the c is an integer constant, and the "select" is the combination
22560 // of CMOV and CMP.
22562 // The rationale for this change is that the conditional-move from a constant
22563 // needs two instructions, however, conditional-move from a register needs
22564 // only one instruction.
22566 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22567 // some instruction-combining opportunities. This opt needs to be
22568 // postponed as late as possible.
22570 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22571 // the DCI.xxxx conditions are provided to postpone the optimization as
22572 // late as possible.
22574 ConstantSDNode *CmpAgainst = nullptr;
22575 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22576 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22577 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22579 if (CC == X86::COND_NE &&
22580 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22581 CC = X86::GetOppositeBranchCondition(CC);
22582 std::swap(TrueOp, FalseOp);
22585 if (CC == X86::COND_E &&
22586 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22587 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22588 DAG.getConstant(CC, DL, MVT::i8), Cond };
22589 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22594 // Fold and/or of setcc's to double CMOV:
22595 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
22596 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
22598 // This combine lets us generate:
22599 // cmovcc1 (jcc1 if we don't have CMOV)
22605 // cmovne (jne if we don't have CMOV)
22606 // When we can't use the CMOV instruction, it might increase branch
22608 // When we can use CMOV, or when there is no mispredict, this improves
22609 // throughput and reduces register pressure.
22611 if (CC == X86::COND_NE) {
22613 X86::CondCode CC0, CC1;
22615 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22617 std::swap(FalseOp, TrueOp);
22618 CC0 = X86::GetOppositeBranchCondition(CC0);
22619 CC1 = X86::GetOppositeBranchCondition(CC1);
22622 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22624 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22625 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22626 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22627 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22635 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22636 const X86Subtarget *Subtarget) {
22637 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22639 default: return SDValue();
22640 // SSE/AVX/AVX2 blend intrinsics.
22641 case Intrinsic::x86_avx2_pblendvb:
22642 // Don't try to simplify this intrinsic if we don't have AVX2.
22643 if (!Subtarget->hasAVX2())
22646 case Intrinsic::x86_avx_blendv_pd_256:
22647 case Intrinsic::x86_avx_blendv_ps_256:
22648 // Don't try to simplify this intrinsic if we don't have AVX.
22649 if (!Subtarget->hasAVX())
22652 case Intrinsic::x86_sse41_blendvps:
22653 case Intrinsic::x86_sse41_blendvpd:
22654 case Intrinsic::x86_sse41_pblendvb: {
22655 SDValue Op0 = N->getOperand(1);
22656 SDValue Op1 = N->getOperand(2);
22657 SDValue Mask = N->getOperand(3);
22659 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22660 if (!Subtarget->hasSSE41())
22663 // fold (blend A, A, Mask) -> A
22666 // fold (blend A, B, allZeros) -> A
22667 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22669 // fold (blend A, B, allOnes) -> B
22670 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22673 // Simplify the case where the mask is a constant i32 value.
22674 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22675 if (C->isNullValue())
22677 if (C->isAllOnesValue())
22684 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22685 case Intrinsic::x86_sse2_psrai_w:
22686 case Intrinsic::x86_sse2_psrai_d:
22687 case Intrinsic::x86_avx2_psrai_w:
22688 case Intrinsic::x86_avx2_psrai_d:
22689 case Intrinsic::x86_sse2_psra_w:
22690 case Intrinsic::x86_sse2_psra_d:
22691 case Intrinsic::x86_avx2_psra_w:
22692 case Intrinsic::x86_avx2_psra_d: {
22693 SDValue Op0 = N->getOperand(1);
22694 SDValue Op1 = N->getOperand(2);
22695 EVT VT = Op0.getValueType();
22696 assert(VT.isVector() && "Expected a vector type!");
22698 if (isa<BuildVectorSDNode>(Op1))
22699 Op1 = Op1.getOperand(0);
22701 if (!isa<ConstantSDNode>(Op1))
22704 EVT SVT = VT.getVectorElementType();
22705 unsigned SVTBits = SVT.getSizeInBits();
22707 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22708 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22709 uint64_t ShAmt = C.getZExtValue();
22711 // Don't try to convert this shift into a ISD::SRA if the shift
22712 // count is bigger than or equal to the element size.
22713 if (ShAmt >= SVTBits)
22716 // Trivial case: if the shift count is zero, then fold this
22717 // into the first operand.
22721 // Replace this packed shift intrinsic with a target independent
22724 SDValue Splat = DAG.getConstant(C, DL, VT);
22725 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
22730 /// PerformMulCombine - Optimize a single multiply with constant into two
22731 /// in order to implement it with two cheaper instructions, e.g.
22732 /// LEA + SHL, LEA + LEA.
22733 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22734 TargetLowering::DAGCombinerInfo &DCI) {
22735 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22738 EVT VT = N->getValueType(0);
22739 if (VT != MVT::i64 && VT != MVT::i32)
22742 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22745 uint64_t MulAmt = C->getZExtValue();
22746 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22749 uint64_t MulAmt1 = 0;
22750 uint64_t MulAmt2 = 0;
22751 if ((MulAmt % 9) == 0) {
22753 MulAmt2 = MulAmt / 9;
22754 } else if ((MulAmt % 5) == 0) {
22756 MulAmt2 = MulAmt / 5;
22757 } else if ((MulAmt % 3) == 0) {
22759 MulAmt2 = MulAmt / 3;
22762 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22765 if (isPowerOf2_64(MulAmt2) &&
22766 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22767 // If second multiplifer is pow2, issue it first. We want the multiply by
22768 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22770 std::swap(MulAmt1, MulAmt2);
22773 if (isPowerOf2_64(MulAmt1))
22774 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22775 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
22777 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22778 DAG.getConstant(MulAmt1, DL, VT));
22780 if (isPowerOf2_64(MulAmt2))
22781 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22782 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
22784 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22785 DAG.getConstant(MulAmt2, DL, VT));
22787 // Do not add new nodes to DAG combiner worklist.
22788 DCI.CombineTo(N, NewMul, false);
22793 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22794 SDValue N0 = N->getOperand(0);
22795 SDValue N1 = N->getOperand(1);
22796 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22797 EVT VT = N0.getValueType();
22799 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22800 // since the result of setcc_c is all zero's or all ones.
22801 if (VT.isInteger() && !VT.isVector() &&
22802 N1C && N0.getOpcode() == ISD::AND &&
22803 N0.getOperand(1).getOpcode() == ISD::Constant) {
22804 SDValue N00 = N0.getOperand(0);
22805 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22806 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22807 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22808 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22809 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22810 APInt ShAmt = N1C->getAPIntValue();
22811 Mask = Mask.shl(ShAmt);
22814 return DAG.getNode(ISD::AND, DL, VT,
22815 N00, DAG.getConstant(Mask, DL, VT));
22820 // Hardware support for vector shifts is sparse which makes us scalarize the
22821 // vector operations in many cases. Also, on sandybridge ADD is faster than
22823 // (shl V, 1) -> add V,V
22824 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22825 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22826 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22827 // We shift all of the values by one. In many cases we do not have
22828 // hardware support for this operation. This is better expressed as an ADD
22830 if (N1SplatC->getZExtValue() == 1)
22831 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22837 /// \brief Returns a vector of 0s if the node in input is a vector logical
22838 /// shift by a constant amount which is known to be bigger than or equal
22839 /// to the vector element size in bits.
22840 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22841 const X86Subtarget *Subtarget) {
22842 EVT VT = N->getValueType(0);
22844 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22845 (!Subtarget->hasInt256() ||
22846 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22849 SDValue Amt = N->getOperand(1);
22851 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22852 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22853 APInt ShiftAmt = AmtSplat->getAPIntValue();
22854 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22856 // SSE2/AVX2 logical shifts always return a vector of 0s
22857 // if the shift amount is bigger than or equal to
22858 // the element size. The constant shift amount will be
22859 // encoded as a 8-bit immediate.
22860 if (ShiftAmt.trunc(8).uge(MaxAmount))
22861 return getZeroVector(VT, Subtarget, DAG, DL);
22867 /// PerformShiftCombine - Combine shifts.
22868 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22869 TargetLowering::DAGCombinerInfo &DCI,
22870 const X86Subtarget *Subtarget) {
22871 if (N->getOpcode() == ISD::SHL)
22872 if (SDValue V = PerformSHLCombine(N, DAG))
22875 // Try to fold this logical shift into a zero vector.
22876 if (N->getOpcode() != ISD::SRA)
22877 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
22883 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22884 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22885 // and friends. Likewise for OR -> CMPNEQSS.
22886 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22887 TargetLowering::DAGCombinerInfo &DCI,
22888 const X86Subtarget *Subtarget) {
22891 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22892 // we're requiring SSE2 for both.
22893 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22894 SDValue N0 = N->getOperand(0);
22895 SDValue N1 = N->getOperand(1);
22896 SDValue CMP0 = N0->getOperand(1);
22897 SDValue CMP1 = N1->getOperand(1);
22900 // The SETCCs should both refer to the same CMP.
22901 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22904 SDValue CMP00 = CMP0->getOperand(0);
22905 SDValue CMP01 = CMP0->getOperand(1);
22906 EVT VT = CMP00.getValueType();
22908 if (VT == MVT::f32 || VT == MVT::f64) {
22909 bool ExpectingFlags = false;
22910 // Check for any users that want flags:
22911 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22912 !ExpectingFlags && UI != UE; ++UI)
22913 switch (UI->getOpcode()) {
22918 ExpectingFlags = true;
22920 case ISD::CopyToReg:
22921 case ISD::SIGN_EXTEND:
22922 case ISD::ZERO_EXTEND:
22923 case ISD::ANY_EXTEND:
22927 if (!ExpectingFlags) {
22928 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22929 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22931 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22932 X86::CondCode tmp = cc0;
22937 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22938 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22939 // FIXME: need symbolic constants for these magic numbers.
22940 // See X86ATTInstPrinter.cpp:printSSECC().
22941 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22942 if (Subtarget->hasAVX512()) {
22943 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22945 DAG.getConstant(x86cc, DL, MVT::i8));
22946 if (N->getValueType(0) != MVT::i1)
22947 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22951 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22952 CMP00.getValueType(), CMP00, CMP01,
22953 DAG.getConstant(x86cc, DL,
22956 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22957 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22959 if (is64BitFP && !Subtarget->is64Bit()) {
22960 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22961 // 64-bit integer, since that's not a legal type. Since
22962 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22963 // bits, but can do this little dance to extract the lowest 32 bits
22964 // and work with those going forward.
22965 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22967 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
22968 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22969 Vector32, DAG.getIntPtrConstant(0, DL));
22973 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
22974 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22975 DAG.getConstant(1, DL, IntVT));
22976 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
22978 return OneBitOfTruth;
22986 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22987 /// so it can be folded inside ANDNP.
22988 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22989 EVT VT = N->getValueType(0);
22991 // Match direct AllOnes for 128 and 256-bit vectors
22992 if (ISD::isBuildVectorAllOnes(N))
22995 // Look through a bit convert.
22996 if (N->getOpcode() == ISD::BITCAST)
22997 N = N->getOperand(0).getNode();
22999 // Sometimes the operand may come from a insert_subvector building a 256-bit
23001 if (VT.is256BitVector() &&
23002 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23003 SDValue V1 = N->getOperand(0);
23004 SDValue V2 = N->getOperand(1);
23006 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23007 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23008 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23009 ISD::isBuildVectorAllOnes(V2.getNode()))
23016 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23017 // register. In most cases we actually compare or select YMM-sized registers
23018 // and mixing the two types creates horrible code. This method optimizes
23019 // some of the transition sequences.
23020 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23021 TargetLowering::DAGCombinerInfo &DCI,
23022 const X86Subtarget *Subtarget) {
23023 EVT VT = N->getValueType(0);
23024 if (!VT.is256BitVector())
23027 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23028 N->getOpcode() == ISD::ZERO_EXTEND ||
23029 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23031 SDValue Narrow = N->getOperand(0);
23032 EVT NarrowVT = Narrow->getValueType(0);
23033 if (!NarrowVT.is128BitVector())
23036 if (Narrow->getOpcode() != ISD::XOR &&
23037 Narrow->getOpcode() != ISD::AND &&
23038 Narrow->getOpcode() != ISD::OR)
23041 SDValue N0 = Narrow->getOperand(0);
23042 SDValue N1 = Narrow->getOperand(1);
23045 // The Left side has to be a trunc.
23046 if (N0.getOpcode() != ISD::TRUNCATE)
23049 // The type of the truncated inputs.
23050 EVT WideVT = N0->getOperand(0)->getValueType(0);
23054 // The right side has to be a 'trunc' or a constant vector.
23055 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23056 ConstantSDNode *RHSConstSplat = nullptr;
23057 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23058 RHSConstSplat = RHSBV->getConstantSplatNode();
23059 if (!RHSTrunc && !RHSConstSplat)
23062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23064 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23067 // Set N0 and N1 to hold the inputs to the new wide operation.
23068 N0 = N0->getOperand(0);
23069 if (RHSConstSplat) {
23070 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23071 SDValue(RHSConstSplat, 0));
23072 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23073 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23074 } else if (RHSTrunc) {
23075 N1 = N1->getOperand(0);
23078 // Generate the wide operation.
23079 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23080 unsigned Opcode = N->getOpcode();
23082 case ISD::ANY_EXTEND:
23084 case ISD::ZERO_EXTEND: {
23085 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23086 APInt Mask = APInt::getAllOnesValue(InBits);
23087 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23088 return DAG.getNode(ISD::AND, DL, VT,
23089 Op, DAG.getConstant(Mask, DL, VT));
23091 case ISD::SIGN_EXTEND:
23092 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23093 Op, DAG.getValueType(NarrowVT));
23095 llvm_unreachable("Unexpected opcode");
23099 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
23100 TargetLowering::DAGCombinerInfo &DCI,
23101 const X86Subtarget *Subtarget) {
23102 SDValue N0 = N->getOperand(0);
23103 SDValue N1 = N->getOperand(1);
23106 // A vector zext_in_reg may be represented as a shuffle,
23107 // feeding into a bitcast (this represents anyext) feeding into
23108 // an and with a mask.
23109 // We'd like to try to combine that into a shuffle with zero
23110 // plus a bitcast, removing the and.
23111 if (N0.getOpcode() != ISD::BITCAST ||
23112 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
23115 // The other side of the AND should be a splat of 2^C, where C
23116 // is the number of bits in the source type.
23117 if (N1.getOpcode() == ISD::BITCAST)
23118 N1 = N1.getOperand(0);
23119 if (N1.getOpcode() != ISD::BUILD_VECTOR)
23121 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
23123 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
23124 EVT SrcType = Shuffle->getValueType(0);
23126 // We expect a single-source shuffle
23127 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
23130 unsigned SrcSize = SrcType.getScalarSizeInBits();
23132 APInt SplatValue, SplatUndef;
23133 unsigned SplatBitSize;
23135 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
23136 SplatBitSize, HasAnyUndefs))
23139 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
23140 // Make sure the splat matches the mask we expect
23141 if (SplatBitSize > ResSize ||
23142 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
23145 // Make sure the input and output size make sense
23146 if (SrcSize >= ResSize || ResSize % SrcSize)
23149 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
23150 // The number of u's between each two values depends on the ratio between
23151 // the source and dest type.
23152 unsigned ZextRatio = ResSize / SrcSize;
23153 bool IsZext = true;
23154 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
23155 if (i % ZextRatio) {
23156 if (Shuffle->getMaskElt(i) > 0) {
23162 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
23163 // Expected element number
23173 // Ok, perform the transformation - replace the shuffle with
23174 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
23175 // (instead of undef) where the k elements come from the zero vector.
23176 SmallVector<int, 8> Mask;
23177 unsigned NumElems = SrcType.getVectorNumElements();
23178 for (unsigned i = 0; i < NumElems; ++i)
23180 Mask.push_back(NumElems);
23182 Mask.push_back(i / ZextRatio);
23184 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
23185 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
23186 return DAG.getBitcast(N0.getValueType(), NewShuffle);
23189 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23190 TargetLowering::DAGCombinerInfo &DCI,
23191 const X86Subtarget *Subtarget) {
23192 if (DCI.isBeforeLegalizeOps())
23195 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
23198 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23201 EVT VT = N->getValueType(0);
23202 SDValue N0 = N->getOperand(0);
23203 SDValue N1 = N->getOperand(1);
23206 // Create BEXTR instructions
23207 // BEXTR is ((X >> imm) & (2**size-1))
23208 if (VT == MVT::i32 || VT == MVT::i64) {
23209 // Check for BEXTR.
23210 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23211 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23212 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23213 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23214 if (MaskNode && ShiftNode) {
23215 uint64_t Mask = MaskNode->getZExtValue();
23216 uint64_t Shift = ShiftNode->getZExtValue();
23217 if (isMask_64(Mask)) {
23218 uint64_t MaskSize = countPopulation(Mask);
23219 if (Shift + MaskSize <= VT.getSizeInBits())
23220 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23221 DAG.getConstant(Shift | (MaskSize << 8), DL,
23230 // Want to form ANDNP nodes:
23231 // 1) In the hopes of then easily combining them with OR and AND nodes
23232 // to form PBLEND/PSIGN.
23233 // 2) To match ANDN packed intrinsics
23234 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23237 // Check LHS for vnot
23238 if (N0.getOpcode() == ISD::XOR &&
23239 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23240 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23241 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23243 // Check RHS for vnot
23244 if (N1.getOpcode() == ISD::XOR &&
23245 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23246 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23247 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23252 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23253 TargetLowering::DAGCombinerInfo &DCI,
23254 const X86Subtarget *Subtarget) {
23255 if (DCI.isBeforeLegalizeOps())
23258 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23261 SDValue N0 = N->getOperand(0);
23262 SDValue N1 = N->getOperand(1);
23263 EVT VT = N->getValueType(0);
23265 // look for psign/blend
23266 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23267 if (!Subtarget->hasSSSE3() ||
23268 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23271 // Canonicalize pandn to RHS
23272 if (N0.getOpcode() == X86ISD::ANDNP)
23274 // or (and (m, y), (pandn m, x))
23275 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23276 SDValue Mask = N1.getOperand(0);
23277 SDValue X = N1.getOperand(1);
23279 if (N0.getOperand(0) == Mask)
23280 Y = N0.getOperand(1);
23281 if (N0.getOperand(1) == Mask)
23282 Y = N0.getOperand(0);
23284 // Check to see if the mask appeared in both the AND and ANDNP and
23288 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23289 // Look through mask bitcast.
23290 if (Mask.getOpcode() == ISD::BITCAST)
23291 Mask = Mask.getOperand(0);
23292 if (X.getOpcode() == ISD::BITCAST)
23293 X = X.getOperand(0);
23294 if (Y.getOpcode() == ISD::BITCAST)
23295 Y = Y.getOperand(0);
23297 EVT MaskVT = Mask.getValueType();
23299 // Validate that the Mask operand is a vector sra node.
23300 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23301 // there is no psrai.b
23302 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23303 unsigned SraAmt = ~0;
23304 if (Mask.getOpcode() == ISD::SRA) {
23305 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23306 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23307 SraAmt = AmtConst->getZExtValue();
23308 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23309 SDValue SraC = Mask.getOperand(1);
23310 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23312 if ((SraAmt + 1) != EltBits)
23317 // Now we know we at least have a plendvb with the mask val. See if
23318 // we can form a psignb/w/d.
23319 // psign = x.type == y.type == mask.type && y = sub(0, x);
23320 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23321 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23322 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23323 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23324 "Unsupported VT for PSIGN");
23325 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23326 return DAG.getBitcast(VT, Mask);
23328 // PBLENDVB only available on SSE 4.1
23329 if (!Subtarget->hasSSE41())
23332 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23334 X = DAG.getBitcast(BlendVT, X);
23335 Y = DAG.getBitcast(BlendVT, Y);
23336 Mask = DAG.getBitcast(BlendVT, Mask);
23337 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23338 return DAG.getBitcast(VT, Mask);
23342 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23345 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23346 MachineFunction &MF = DAG.getMachineFunction();
23348 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
23350 // SHLD/SHRD instructions have lower register pressure, but on some
23351 // platforms they have higher latency than the equivalent
23352 // series of shifts/or that would otherwise be generated.
23353 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23354 // have higher latencies and we are not optimizing for size.
23355 if (!OptForSize && Subtarget->isSHLDSlow())
23358 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23360 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23362 if (!N0.hasOneUse() || !N1.hasOneUse())
23365 SDValue ShAmt0 = N0.getOperand(1);
23366 if (ShAmt0.getValueType() != MVT::i8)
23368 SDValue ShAmt1 = N1.getOperand(1);
23369 if (ShAmt1.getValueType() != MVT::i8)
23371 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23372 ShAmt0 = ShAmt0.getOperand(0);
23373 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23374 ShAmt1 = ShAmt1.getOperand(0);
23377 unsigned Opc = X86ISD::SHLD;
23378 SDValue Op0 = N0.getOperand(0);
23379 SDValue Op1 = N1.getOperand(0);
23380 if (ShAmt0.getOpcode() == ISD::SUB) {
23381 Opc = X86ISD::SHRD;
23382 std::swap(Op0, Op1);
23383 std::swap(ShAmt0, ShAmt1);
23386 unsigned Bits = VT.getSizeInBits();
23387 if (ShAmt1.getOpcode() == ISD::SUB) {
23388 SDValue Sum = ShAmt1.getOperand(0);
23389 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23390 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23391 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23392 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23393 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23394 return DAG.getNode(Opc, DL, VT,
23396 DAG.getNode(ISD::TRUNCATE, DL,
23399 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23400 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23402 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23403 return DAG.getNode(Opc, DL, VT,
23404 N0.getOperand(0), N1.getOperand(0),
23405 DAG.getNode(ISD::TRUNCATE, DL,
23412 // Generate NEG and CMOV for integer abs.
23413 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23414 EVT VT = N->getValueType(0);
23416 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23417 // 8-bit integer abs to NEG and CMOV.
23418 if (VT.isInteger() && VT.getSizeInBits() == 8)
23421 SDValue N0 = N->getOperand(0);
23422 SDValue N1 = N->getOperand(1);
23425 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23426 // and change it to SUB and CMOV.
23427 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23428 N0.getOpcode() == ISD::ADD &&
23429 N0.getOperand(1) == N1 &&
23430 N1.getOpcode() == ISD::SRA &&
23431 N1.getOperand(0) == N0.getOperand(0))
23432 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23433 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23434 // Generate SUB & CMOV.
23435 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23436 DAG.getConstant(0, DL, VT), N0.getOperand(0));
23438 SDValue Ops[] = { N0.getOperand(0), Neg,
23439 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
23440 SDValue(Neg.getNode(), 1) };
23441 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23446 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23447 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23448 TargetLowering::DAGCombinerInfo &DCI,
23449 const X86Subtarget *Subtarget) {
23450 if (DCI.isBeforeLegalizeOps())
23453 if (Subtarget->hasCMov())
23454 if (SDValue RV = performIntegerAbsCombine(N, DAG))
23460 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23461 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23462 TargetLowering::DAGCombinerInfo &DCI,
23463 const X86Subtarget *Subtarget) {
23464 LoadSDNode *Ld = cast<LoadSDNode>(N);
23465 EVT RegVT = Ld->getValueType(0);
23466 EVT MemVT = Ld->getMemoryVT();
23468 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23470 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
23471 // into two 16-byte operations.
23472 ISD::LoadExtType Ext = Ld->getExtensionType();
23473 unsigned Alignment = Ld->getAlignment();
23474 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23475 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23476 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23477 unsigned NumElems = RegVT.getVectorNumElements();
23481 SDValue Ptr = Ld->getBasePtr();
23482 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
23484 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23486 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23487 Ld->getPointerInfo(), Ld->isVolatile(),
23488 Ld->isNonTemporal(), Ld->isInvariant(),
23490 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23491 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23492 Ld->getPointerInfo(), Ld->isVolatile(),
23493 Ld->isNonTemporal(), Ld->isInvariant(),
23494 std::min(16U, Alignment));
23495 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23497 Load2.getValue(1));
23499 SDValue NewVec = DAG.getUNDEF(RegVT);
23500 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23501 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23502 return DCI.CombineTo(N, NewVec, TF, true);
23508 /// PerformMLOADCombine - Resolve extending loads
23509 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
23510 TargetLowering::DAGCombinerInfo &DCI,
23511 const X86Subtarget *Subtarget) {
23512 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
23513 if (Mld->getExtensionType() != ISD::SEXTLOAD)
23516 EVT VT = Mld->getValueType(0);
23517 unsigned NumElems = VT.getVectorNumElements();
23518 EVT LdVT = Mld->getMemoryVT();
23521 assert(LdVT != VT && "Cannot extend to the same type");
23522 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
23523 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
23524 // From, To sizes and ElemCount must be pow of two
23525 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23526 "Unexpected size for extending masked load");
23528 unsigned SizeRatio = ToSz / FromSz;
23529 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
23531 // Create a type on which we perform the shuffle
23532 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23533 LdVT.getScalarType(), NumElems*SizeRatio);
23534 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23536 // Convert Src0 value
23537 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
23538 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
23539 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23540 for (unsigned i = 0; i != NumElems; ++i)
23541 ShuffleVec[i] = i * SizeRatio;
23543 // Can't shuffle using an illegal type.
23544 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23545 && "WideVecVT should be legal");
23546 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
23547 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
23549 // Prepare the new mask
23551 SDValue Mask = Mld->getMask();
23552 if (Mask.getValueType() == VT) {
23553 // Mask and original value have the same type
23554 NewMask = DAG.getBitcast(WideVecVT, Mask);
23555 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23556 for (unsigned i = 0; i != NumElems; ++i)
23557 ShuffleVec[i] = i * SizeRatio;
23558 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23559 ShuffleVec[i] = NumElems*SizeRatio;
23560 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23561 DAG.getConstant(0, dl, WideVecVT),
23565 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23566 unsigned WidenNumElts = NumElems*SizeRatio;
23567 unsigned MaskNumElts = VT.getVectorNumElements();
23568 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23571 unsigned NumConcat = WidenNumElts / MaskNumElts;
23572 SmallVector<SDValue, 16> Ops(NumConcat);
23573 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23575 for (unsigned i = 1; i != NumConcat; ++i)
23578 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23581 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
23582 Mld->getBasePtr(), NewMask, WideSrc0,
23583 Mld->getMemoryVT(), Mld->getMemOperand(),
23585 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
23586 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
23589 /// PerformMSTORECombine - Resolve truncating stores
23590 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
23591 const X86Subtarget *Subtarget) {
23592 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
23593 if (!Mst->isTruncatingStore())
23596 EVT VT = Mst->getValue().getValueType();
23597 unsigned NumElems = VT.getVectorNumElements();
23598 EVT StVT = Mst->getMemoryVT();
23601 assert(StVT != VT && "Cannot truncate to the same type");
23602 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23603 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23605 // From, To sizes and ElemCount must be pow of two
23606 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23607 "Unexpected size for truncating masked store");
23608 // We are going to use the original vector elt for storing.
23609 // Accumulated smaller vector elements must be a multiple of the store size.
23610 assert (((NumElems * FromSz) % ToSz) == 0 &&
23611 "Unexpected ratio for truncating masked store");
23613 unsigned SizeRatio = FromSz / ToSz;
23614 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23616 // Create a type on which we perform the shuffle
23617 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23618 StVT.getScalarType(), NumElems*SizeRatio);
23620 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23622 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
23623 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23624 for (unsigned i = 0; i != NumElems; ++i)
23625 ShuffleVec[i] = i * SizeRatio;
23627 // Can't shuffle using an illegal type.
23628 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23629 && "WideVecVT should be legal");
23631 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23632 DAG.getUNDEF(WideVecVT),
23636 SDValue Mask = Mst->getMask();
23637 if (Mask.getValueType() == VT) {
23638 // Mask and original value have the same type
23639 NewMask = DAG.getBitcast(WideVecVT, Mask);
23640 for (unsigned i = 0; i != NumElems; ++i)
23641 ShuffleVec[i] = i * SizeRatio;
23642 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23643 ShuffleVec[i] = NumElems*SizeRatio;
23644 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23645 DAG.getConstant(0, dl, WideVecVT),
23649 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23650 unsigned WidenNumElts = NumElems*SizeRatio;
23651 unsigned MaskNumElts = VT.getVectorNumElements();
23652 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23655 unsigned NumConcat = WidenNumElts / MaskNumElts;
23656 SmallVector<SDValue, 16> Ops(NumConcat);
23657 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23659 for (unsigned i = 1; i != NumConcat; ++i)
23662 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23665 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23666 NewMask, StVT, Mst->getMemOperand(), false);
23668 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23669 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23670 const X86Subtarget *Subtarget) {
23671 StoreSDNode *St = cast<StoreSDNode>(N);
23672 EVT VT = St->getValue().getValueType();
23673 EVT StVT = St->getMemoryVT();
23675 SDValue StoredVal = St->getOperand(1);
23676 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23678 // If we are saving a concatenation of two XMM registers and 32-byte stores
23679 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23680 unsigned Alignment = St->getAlignment();
23681 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23682 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23683 StVT == VT && !IsAligned) {
23684 unsigned NumElems = VT.getVectorNumElements();
23688 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23689 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23691 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23692 SDValue Ptr0 = St->getBasePtr();
23693 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23695 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23696 St->getPointerInfo(), St->isVolatile(),
23697 St->isNonTemporal(), Alignment);
23698 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23699 St->getPointerInfo(), St->isVolatile(),
23700 St->isNonTemporal(),
23701 std::min(16U, Alignment));
23702 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23705 // Optimize trunc store (of multiple scalars) to shuffle and store.
23706 // First, pack all of the elements in one place. Next, store to memory
23707 // in fewer chunks.
23708 if (St->isTruncatingStore() && VT.isVector()) {
23709 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23710 unsigned NumElems = VT.getVectorNumElements();
23711 assert(StVT != VT && "Cannot truncate to the same type");
23712 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23713 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23715 // From, To sizes and ElemCount must be pow of two
23716 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23717 // We are going to use the original vector elt for storing.
23718 // Accumulated smaller vector elements must be a multiple of the store size.
23719 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23721 unsigned SizeRatio = FromSz / ToSz;
23723 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23725 // Create a type on which we perform the shuffle
23726 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23727 StVT.getScalarType(), NumElems*SizeRatio);
23729 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23731 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
23732 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23733 for (unsigned i = 0; i != NumElems; ++i)
23734 ShuffleVec[i] = i * SizeRatio;
23736 // Can't shuffle using an illegal type.
23737 if (!TLI.isTypeLegal(WideVecVT))
23740 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23741 DAG.getUNDEF(WideVecVT),
23743 // At this point all of the data is stored at the bottom of the
23744 // register. We now need to save it to mem.
23746 // Find the largest store unit
23747 MVT StoreType = MVT::i8;
23748 for (MVT Tp : MVT::integer_valuetypes()) {
23749 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23753 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23754 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23755 (64 <= NumElems * ToSz))
23756 StoreType = MVT::f64;
23758 // Bitcast the original vector into a vector of store-size units
23759 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23760 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23761 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23762 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
23763 SmallVector<SDValue, 8> Chains;
23764 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23765 TLI.getPointerTy());
23766 SDValue Ptr = St->getBasePtr();
23768 // Perform one or more big stores into memory.
23769 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23770 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23771 StoreType, ShuffWide,
23772 DAG.getIntPtrConstant(i, dl));
23773 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23774 St->getPointerInfo(), St->isVolatile(),
23775 St->isNonTemporal(), St->getAlignment());
23776 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23777 Chains.push_back(Ch);
23780 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23783 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23784 // the FP state in cases where an emms may be missing.
23785 // A preferable solution to the general problem is to figure out the right
23786 // places to insert EMMS. This qualifies as a quick hack.
23788 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23789 if (VT.getSizeInBits() != 64)
23792 const Function *F = DAG.getMachineFunction().getFunction();
23793 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
23795 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
23796 if ((VT.isVector() ||
23797 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23798 isa<LoadSDNode>(St->getValue()) &&
23799 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23800 St->getChain().hasOneUse() && !St->isVolatile()) {
23801 SDNode* LdVal = St->getValue().getNode();
23802 LoadSDNode *Ld = nullptr;
23803 int TokenFactorIndex = -1;
23804 SmallVector<SDValue, 8> Ops;
23805 SDNode* ChainVal = St->getChain().getNode();
23806 // Must be a store of a load. We currently handle two cases: the load
23807 // is a direct child, and it's under an intervening TokenFactor. It is
23808 // possible to dig deeper under nested TokenFactors.
23809 if (ChainVal == LdVal)
23810 Ld = cast<LoadSDNode>(St->getChain());
23811 else if (St->getValue().hasOneUse() &&
23812 ChainVal->getOpcode() == ISD::TokenFactor) {
23813 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23814 if (ChainVal->getOperand(i).getNode() == LdVal) {
23815 TokenFactorIndex = i;
23816 Ld = cast<LoadSDNode>(St->getValue());
23818 Ops.push_back(ChainVal->getOperand(i));
23822 if (!Ld || !ISD::isNormalLoad(Ld))
23825 // If this is not the MMX case, i.e. we are just turning i64 load/store
23826 // into f64 load/store, avoid the transformation if there are multiple
23827 // uses of the loaded value.
23828 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23833 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23834 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23836 if (Subtarget->is64Bit() || F64IsLegal) {
23837 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23838 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23839 Ld->getPointerInfo(), Ld->isVolatile(),
23840 Ld->isNonTemporal(), Ld->isInvariant(),
23841 Ld->getAlignment());
23842 SDValue NewChain = NewLd.getValue(1);
23843 if (TokenFactorIndex != -1) {
23844 Ops.push_back(NewChain);
23845 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23847 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23848 St->getPointerInfo(),
23849 St->isVolatile(), St->isNonTemporal(),
23850 St->getAlignment());
23853 // Otherwise, lower to two pairs of 32-bit loads / stores.
23854 SDValue LoAddr = Ld->getBasePtr();
23855 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23856 DAG.getConstant(4, LdDL, MVT::i32));
23858 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23859 Ld->getPointerInfo(),
23860 Ld->isVolatile(), Ld->isNonTemporal(),
23861 Ld->isInvariant(), Ld->getAlignment());
23862 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23863 Ld->getPointerInfo().getWithOffset(4),
23864 Ld->isVolatile(), Ld->isNonTemporal(),
23866 MinAlign(Ld->getAlignment(), 4));
23868 SDValue NewChain = LoLd.getValue(1);
23869 if (TokenFactorIndex != -1) {
23870 Ops.push_back(LoLd);
23871 Ops.push_back(HiLd);
23872 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23875 LoAddr = St->getBasePtr();
23876 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23877 DAG.getConstant(4, StDL, MVT::i32));
23879 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23880 St->getPointerInfo(),
23881 St->isVolatile(), St->isNonTemporal(),
23882 St->getAlignment());
23883 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23884 St->getPointerInfo().getWithOffset(4),
23886 St->isNonTemporal(),
23887 MinAlign(St->getAlignment(), 4));
23888 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23891 // This is similar to the above case, but here we handle a scalar 64-bit
23892 // integer store that is extracted from a vector on a 32-bit target.
23893 // If we have SSE2, then we can treat it like a floating-point double
23894 // to get past legalization. The execution dependencies fixup pass will
23895 // choose the optimal machine instruction for the store if this really is
23896 // an integer or v2f32 rather than an f64.
23897 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
23898 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
23899 SDValue OldExtract = St->getOperand(1);
23900 SDValue ExtOp0 = OldExtract.getOperand(0);
23901 unsigned VecSize = ExtOp0.getValueSizeInBits();
23902 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
23903 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
23904 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
23905 BitCast, OldExtract.getOperand(1));
23906 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
23907 St->getPointerInfo(), St->isVolatile(),
23908 St->isNonTemporal(), St->getAlignment());
23914 /// Return 'true' if this vector operation is "horizontal"
23915 /// and return the operands for the horizontal operation in LHS and RHS. A
23916 /// horizontal operation performs the binary operation on successive elements
23917 /// of its first operand, then on successive elements of its second operand,
23918 /// returning the resulting values in a vector. For example, if
23919 /// A = < float a0, float a1, float a2, float a3 >
23921 /// B = < float b0, float b1, float b2, float b3 >
23922 /// then the result of doing a horizontal operation on A and B is
23923 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23924 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23925 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23926 /// set to A, RHS to B, and the routine returns 'true'.
23927 /// Note that the binary operation should have the property that if one of the
23928 /// operands is UNDEF then the result is UNDEF.
23929 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23930 // Look for the following pattern: if
23931 // A = < float a0, float a1, float a2, float a3 >
23932 // B = < float b0, float b1, float b2, float b3 >
23934 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23935 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23936 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23937 // which is A horizontal-op B.
23939 // At least one of the operands should be a vector shuffle.
23940 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23941 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23944 MVT VT = LHS.getSimpleValueType();
23946 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23947 "Unsupported vector type for horizontal add/sub");
23949 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23950 // operate independently on 128-bit lanes.
23951 unsigned NumElts = VT.getVectorNumElements();
23952 unsigned NumLanes = VT.getSizeInBits()/128;
23953 unsigned NumLaneElts = NumElts / NumLanes;
23954 assert((NumLaneElts % 2 == 0) &&
23955 "Vector type should have an even number of elements in each lane");
23956 unsigned HalfLaneElts = NumLaneElts/2;
23958 // View LHS in the form
23959 // LHS = VECTOR_SHUFFLE A, B, LMask
23960 // If LHS is not a shuffle then pretend it is the shuffle
23961 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23962 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23965 SmallVector<int, 16> LMask(NumElts);
23966 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23967 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23968 A = LHS.getOperand(0);
23969 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23970 B = LHS.getOperand(1);
23971 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23972 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23974 if (LHS.getOpcode() != ISD::UNDEF)
23976 for (unsigned i = 0; i != NumElts; ++i)
23980 // Likewise, view RHS in the form
23981 // RHS = VECTOR_SHUFFLE C, D, RMask
23983 SmallVector<int, 16> RMask(NumElts);
23984 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23985 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23986 C = RHS.getOperand(0);
23987 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23988 D = RHS.getOperand(1);
23989 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23990 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23992 if (RHS.getOpcode() != ISD::UNDEF)
23994 for (unsigned i = 0; i != NumElts; ++i)
23998 // Check that the shuffles are both shuffling the same vectors.
23999 if (!(A == C && B == D) && !(A == D && B == C))
24002 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24003 if (!A.getNode() && !B.getNode())
24006 // If A and B occur in reverse order in RHS, then "swap" them (which means
24007 // rewriting the mask).
24009 ShuffleVectorSDNode::commuteMask(RMask);
24011 // At this point LHS and RHS are equivalent to
24012 // LHS = VECTOR_SHUFFLE A, B, LMask
24013 // RHS = VECTOR_SHUFFLE A, B, RMask
24014 // Check that the masks correspond to performing a horizontal operation.
24015 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24016 for (unsigned i = 0; i != NumLaneElts; ++i) {
24017 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24019 // Ignore any UNDEF components.
24020 if (LIdx < 0 || RIdx < 0 ||
24021 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24022 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24025 // Check that successive elements are being operated on. If not, this is
24026 // not a horizontal operation.
24027 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24028 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24029 if (!(LIdx == Index && RIdx == Index + 1) &&
24030 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24035 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24036 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24040 /// Do target-specific dag combines on floating point adds.
24041 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24042 const X86Subtarget *Subtarget) {
24043 EVT VT = N->getValueType(0);
24044 SDValue LHS = N->getOperand(0);
24045 SDValue RHS = N->getOperand(1);
24047 // Try to synthesize horizontal adds from adds of shuffles.
24048 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24049 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24050 isHorizontalBinOp(LHS, RHS, true))
24051 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24055 /// Do target-specific dag combines on floating point subs.
24056 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24057 const X86Subtarget *Subtarget) {
24058 EVT VT = N->getValueType(0);
24059 SDValue LHS = N->getOperand(0);
24060 SDValue RHS = N->getOperand(1);
24062 // Try to synthesize horizontal subs from subs of shuffles.
24063 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24064 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24065 isHorizontalBinOp(LHS, RHS, false))
24066 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24070 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24071 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24072 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24074 // F[X]OR(0.0, x) -> x
24075 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24076 if (C->getValueAPF().isPosZero())
24077 return N->getOperand(1);
24079 // F[X]OR(x, 0.0) -> x
24080 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24081 if (C->getValueAPF().isPosZero())
24082 return N->getOperand(0);
24086 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24087 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24088 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24090 // Only perform optimizations if UnsafeMath is used.
24091 if (!DAG.getTarget().Options.UnsafeFPMath)
24094 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24095 // into FMINC and FMAXC, which are Commutative operations.
24096 unsigned NewOp = 0;
24097 switch (N->getOpcode()) {
24098 default: llvm_unreachable("unknown opcode");
24099 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24100 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24103 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24104 N->getOperand(0), N->getOperand(1));
24107 /// Do target-specific dag combines on X86ISD::FAND nodes.
24108 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24109 // FAND(0.0, x) -> 0.0
24110 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24111 if (C->getValueAPF().isPosZero())
24112 return N->getOperand(0);
24114 // FAND(x, 0.0) -> 0.0
24115 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24116 if (C->getValueAPF().isPosZero())
24117 return N->getOperand(1);
24122 /// Do target-specific dag combines on X86ISD::FANDN nodes
24123 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24124 // FANDN(0.0, x) -> x
24125 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24126 if (C->getValueAPF().isPosZero())
24127 return N->getOperand(1);
24129 // FANDN(x, 0.0) -> 0.0
24130 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24131 if (C->getValueAPF().isPosZero())
24132 return N->getOperand(1);
24137 static SDValue PerformBTCombine(SDNode *N,
24139 TargetLowering::DAGCombinerInfo &DCI) {
24140 // BT ignores high bits in the bit index operand.
24141 SDValue Op1 = N->getOperand(1);
24142 if (Op1.hasOneUse()) {
24143 unsigned BitWidth = Op1.getValueSizeInBits();
24144 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24145 APInt KnownZero, KnownOne;
24146 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24147 !DCI.isBeforeLegalizeOps());
24148 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24149 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24150 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24151 DCI.CommitTargetLoweringOpt(TLO);
24156 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24157 SDValue Op = N->getOperand(0);
24158 if (Op.getOpcode() == ISD::BITCAST)
24159 Op = Op.getOperand(0);
24160 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24161 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24162 VT.getVectorElementType().getSizeInBits() ==
24163 OpVT.getVectorElementType().getSizeInBits()) {
24164 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24169 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24170 const X86Subtarget *Subtarget) {
24171 EVT VT = N->getValueType(0);
24172 if (!VT.isVector())
24175 SDValue N0 = N->getOperand(0);
24176 SDValue N1 = N->getOperand(1);
24177 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24180 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24181 // both SSE and AVX2 since there is no sign-extended shift right
24182 // operation on a vector with 64-bit elements.
24183 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24184 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24185 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24186 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24187 SDValue N00 = N0.getOperand(0);
24189 // EXTLOAD has a better solution on AVX2,
24190 // it may be replaced with X86ISD::VSEXT node.
24191 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24192 if (!ISD::isNormalLoad(N00.getNode()))
24195 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24196 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24198 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24204 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24205 TargetLowering::DAGCombinerInfo &DCI,
24206 const X86Subtarget *Subtarget) {
24207 SDValue N0 = N->getOperand(0);
24208 EVT VT = N->getValueType(0);
24209 EVT SVT = VT.getScalarType();
24210 EVT InVT = N0.getValueType();
24211 EVT InSVT = InVT.getScalarType();
24214 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24215 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24216 // This exposes the sext to the sdivrem lowering, so that it directly extends
24217 // from AH (which we otherwise need to do contortions to access).
24218 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24219 InVT == MVT::i8 && VT == MVT::i32) {
24220 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24221 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
24222 N0.getOperand(0), N0.getOperand(1));
24223 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24224 return R.getValue(1);
24227 if (!DCI.isBeforeLegalizeOps()) {
24228 if (InVT == MVT::i1) {
24229 SDValue Zero = DAG.getConstant(0, DL, VT);
24231 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
24232 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
24237 if (VT.isVector() && Subtarget->hasSSE2()) {
24238 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
24239 EVT InVT = N.getValueType();
24240 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
24241 Size / InVT.getScalarSizeInBits());
24242 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
24243 DAG.getUNDEF(InVT));
24245 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
24248 // If target-size is less than 128-bits, extend to a type that would extend
24249 // to 128 bits, extend that and extract the original target vector.
24250 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
24251 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24252 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24253 unsigned Scale = 128 / VT.getSizeInBits();
24255 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
24256 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
24257 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
24258 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
24259 DAG.getIntPtrConstant(0, DL));
24262 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
24263 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
24264 if (VT.getSizeInBits() == 128 &&
24265 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24266 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24267 SDValue ExOp = ExtendVecSize(DL, N0, 128);
24268 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
24271 // On pre-AVX2 targets, split into 128-bit nodes of
24272 // ISD::SIGN_EXTEND_VECTOR_INREG.
24273 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
24274 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24275 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24276 unsigned NumVecs = VT.getSizeInBits() / 128;
24277 unsigned NumSubElts = 128 / SVT.getSizeInBits();
24278 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
24279 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
24281 SmallVector<SDValue, 8> Opnds;
24282 for (unsigned i = 0, Offset = 0; i != NumVecs;
24283 ++i, Offset += NumSubElts) {
24284 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
24285 DAG.getIntPtrConstant(Offset, DL));
24286 SrcVec = ExtendVecSize(DL, SrcVec, 128);
24287 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
24288 Opnds.push_back(SrcVec);
24290 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
24294 if (!Subtarget->hasFp256())
24297 if (VT.isVector() && VT.getSizeInBits() == 256)
24298 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
24304 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24305 const X86Subtarget* Subtarget) {
24307 EVT VT = N->getValueType(0);
24309 // Let legalize expand this if it isn't a legal type yet.
24310 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24313 EVT ScalarVT = VT.getScalarType();
24314 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24315 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
24316 !Subtarget->hasAVX512()))
24319 SDValue A = N->getOperand(0);
24320 SDValue B = N->getOperand(1);
24321 SDValue C = N->getOperand(2);
24323 bool NegA = (A.getOpcode() == ISD::FNEG);
24324 bool NegB = (B.getOpcode() == ISD::FNEG);
24325 bool NegC = (C.getOpcode() == ISD::FNEG);
24327 // Negative multiplication when NegA xor NegB
24328 bool NegMul = (NegA != NegB);
24330 A = A.getOperand(0);
24332 B = B.getOperand(0);
24334 C = C.getOperand(0);
24338 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24340 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24342 return DAG.getNode(Opcode, dl, VT, A, B, C);
24345 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24346 TargetLowering::DAGCombinerInfo &DCI,
24347 const X86Subtarget *Subtarget) {
24348 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24349 // (and (i32 x86isd::setcc_carry), 1)
24350 // This eliminates the zext. This transformation is necessary because
24351 // ISD::SETCC is always legalized to i8.
24353 SDValue N0 = N->getOperand(0);
24354 EVT VT = N->getValueType(0);
24356 if (N0.getOpcode() == ISD::AND &&
24358 N0.getOperand(0).hasOneUse()) {
24359 SDValue N00 = N0.getOperand(0);
24360 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24361 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24362 if (!C || C->getZExtValue() != 1)
24364 return DAG.getNode(ISD::AND, dl, VT,
24365 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24366 N00.getOperand(0), N00.getOperand(1)),
24367 DAG.getConstant(1, dl, VT));
24371 if (N0.getOpcode() == ISD::TRUNCATE &&
24373 N0.getOperand(0).hasOneUse()) {
24374 SDValue N00 = N0.getOperand(0);
24375 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24376 return DAG.getNode(ISD::AND, dl, VT,
24377 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24378 N00.getOperand(0), N00.getOperand(1)),
24379 DAG.getConstant(1, dl, VT));
24383 if (VT.is256BitVector())
24384 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
24387 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24388 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24389 // This exposes the zext to the udivrem lowering, so that it directly extends
24390 // from AH (which we otherwise need to do contortions to access).
24391 if (N0.getOpcode() == ISD::UDIVREM &&
24392 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24393 (VT == MVT::i32 || VT == MVT::i64)) {
24394 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24395 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24396 N0.getOperand(0), N0.getOperand(1));
24397 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24398 return R.getValue(1);
24404 // Optimize x == -y --> x+y == 0
24405 // x != -y --> x+y != 0
24406 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24407 const X86Subtarget* Subtarget) {
24408 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24409 SDValue LHS = N->getOperand(0);
24410 SDValue RHS = N->getOperand(1);
24411 EVT VT = N->getValueType(0);
24414 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24415 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24416 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24417 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
24418 LHS.getOperand(1));
24419 return DAG.getSetCC(DL, N->getValueType(0), addV,
24420 DAG.getConstant(0, DL, addV.getValueType()), CC);
24422 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24423 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24424 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24425 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
24426 RHS.getOperand(1));
24427 return DAG.getSetCC(DL, N->getValueType(0), addV,
24428 DAG.getConstant(0, DL, addV.getValueType()), CC);
24431 if (VT.getScalarType() == MVT::i1 &&
24432 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
24434 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24435 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24436 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24438 if (!IsSEXT0 || !IsVZero1) {
24439 // Swap the operands and update the condition code.
24440 std::swap(LHS, RHS);
24441 CC = ISD::getSetCCSwappedOperands(CC);
24443 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24444 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24445 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24448 if (IsSEXT0 && IsVZero1) {
24449 assert(VT == LHS.getOperand(0).getValueType() &&
24450 "Uexpected operand type");
24451 if (CC == ISD::SETGT)
24452 return DAG.getConstant(0, DL, VT);
24453 if (CC == ISD::SETLE)
24454 return DAG.getConstant(1, DL, VT);
24455 if (CC == ISD::SETEQ || CC == ISD::SETGE)
24456 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24458 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
24459 "Unexpected condition code!");
24460 return LHS.getOperand(0);
24467 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
24468 SelectionDAG &DAG) {
24470 MVT VT = Load->getSimpleValueType(0);
24471 MVT EVT = VT.getVectorElementType();
24472 SDValue Addr = Load->getOperand(1);
24473 SDValue NewAddr = DAG.getNode(
24474 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
24475 DAG.getConstant(Index * EVT.getStoreSize(), dl,
24476 Addr.getSimpleValueType()));
24479 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
24480 DAG.getMachineFunction().getMachineMemOperand(
24481 Load->getMemOperand(), 0, EVT.getStoreSize()));
24485 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24486 const X86Subtarget *Subtarget) {
24488 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24489 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24490 "X86insertps is only defined for v4x32");
24492 SDValue Ld = N->getOperand(1);
24493 if (MayFoldLoad(Ld)) {
24494 // Extract the countS bits from the immediate so we can get the proper
24495 // address when narrowing the vector load to a specific element.
24496 // When the second source op is a memory address, insertps doesn't use
24497 // countS and just gets an f32 from that address.
24498 unsigned DestIndex =
24499 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24501 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24503 // Create this as a scalar to vector to match the instruction pattern.
24504 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24505 // countS bits are ignored when loading from memory on insertps, which
24506 // means we don't need to explicitly set them to 0.
24507 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24508 LoadScalarToVector, N->getOperand(2));
24513 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
24514 SDValue V0 = N->getOperand(0);
24515 SDValue V1 = N->getOperand(1);
24517 EVT VT = N->getValueType(0);
24519 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
24520 // operands and changing the mask to 1. This saves us a bunch of
24521 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
24522 // x86InstrInfo knows how to commute this back after instruction selection
24523 // if it would help register allocation.
24525 // TODO: If optimizing for size or a processor that doesn't suffer from
24526 // partial register update stalls, this should be transformed into a MOVSD
24527 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
24529 if (VT == MVT::v2f64)
24530 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
24531 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
24532 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
24533 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
24539 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24540 // as "sbb reg,reg", since it can be extended without zext and produces
24541 // an all-ones bit which is more useful than 0/1 in some cases.
24542 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24545 return DAG.getNode(ISD::AND, DL, VT,
24546 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24547 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24549 DAG.getConstant(1, DL, VT));
24550 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24551 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24552 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24553 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24557 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24558 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24559 TargetLowering::DAGCombinerInfo &DCI,
24560 const X86Subtarget *Subtarget) {
24562 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24563 SDValue EFLAGS = N->getOperand(1);
24565 if (CC == X86::COND_A) {
24566 // Try to convert COND_A into COND_B in an attempt to facilitate
24567 // materializing "setb reg".
24569 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24570 // cannot take an immediate as its first operand.
24572 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24573 EFLAGS.getValueType().isInteger() &&
24574 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24575 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24576 EFLAGS.getNode()->getVTList(),
24577 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24578 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24579 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24583 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24584 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24586 if (CC == X86::COND_B)
24587 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24589 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
24590 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24591 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24597 // Optimize branch condition evaluation.
24599 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24600 TargetLowering::DAGCombinerInfo &DCI,
24601 const X86Subtarget *Subtarget) {
24603 SDValue Chain = N->getOperand(0);
24604 SDValue Dest = N->getOperand(1);
24605 SDValue EFLAGS = N->getOperand(3);
24606 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24608 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
24609 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24610 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24617 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24618 SelectionDAG &DAG) {
24619 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24620 // optimize away operation when it's from a constant.
24622 // The general transformation is:
24623 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24624 // AND(VECTOR_CMP(x,y), constant2)
24625 // constant2 = UNARYOP(constant)
24627 // Early exit if this isn't a vector operation, the operand of the
24628 // unary operation isn't a bitwise AND, or if the sizes of the operations
24629 // aren't the same.
24630 EVT VT = N->getValueType(0);
24631 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24632 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24633 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24636 // Now check that the other operand of the AND is a constant. We could
24637 // make the transformation for non-constant splats as well, but it's unclear
24638 // that would be a benefit as it would not eliminate any operations, just
24639 // perform one more step in scalar code before moving to the vector unit.
24640 if (BuildVectorSDNode *BV =
24641 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24642 // Bail out if the vector isn't a constant.
24643 if (!BV->isConstant())
24646 // Everything checks out. Build up the new and improved node.
24648 EVT IntVT = BV->getValueType(0);
24649 // Create a new constant of the appropriate type for the transformed
24651 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24652 // The AND node needs bitcasts to/from an integer vector type around it.
24653 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
24654 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24655 N->getOperand(0)->getOperand(0), MaskConst);
24656 SDValue Res = DAG.getBitcast(VT, NewAnd);
24663 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24664 const X86Subtarget *Subtarget) {
24665 SDValue Op0 = N->getOperand(0);
24666 EVT VT = N->getValueType(0);
24667 EVT InVT = Op0.getValueType();
24668 EVT InSVT = InVT.getScalarType();
24669 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24671 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
24672 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
24673 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
24675 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
24676 InVT.getVectorNumElements());
24677 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
24679 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
24680 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
24682 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
24688 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24689 const X86Subtarget *Subtarget) {
24690 // First try to optimize away the conversion entirely when it's
24691 // conditionally from a constant. Vectors only.
24692 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
24695 // Now move on to more general possibilities.
24696 SDValue Op0 = N->getOperand(0);
24697 EVT VT = N->getValueType(0);
24698 EVT InVT = Op0.getValueType();
24699 EVT InSVT = InVT.getScalarType();
24701 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
24702 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
24703 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
24705 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
24706 InVT.getVectorNumElements());
24707 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24708 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
24711 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24712 // a 32-bit target where SSE doesn't support i64->FP operations.
24713 if (Op0.getOpcode() == ISD::LOAD) {
24714 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24715 EVT LdVT = Ld->getValueType(0);
24717 // This transformation is not supported if the result type is f16
24718 if (VT == MVT::f16)
24721 if (!Ld->isVolatile() && !VT.isVector() &&
24722 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24723 !Subtarget->is64Bit() && LdVT == MVT::i64) {
24724 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
24725 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
24726 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24733 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24734 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24735 X86TargetLowering::DAGCombinerInfo &DCI) {
24736 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24737 // the result is either zero or one (depending on the input carry bit).
24738 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24739 if (X86::isZeroNode(N->getOperand(0)) &&
24740 X86::isZeroNode(N->getOperand(1)) &&
24741 // We don't have a good way to replace an EFLAGS use, so only do this when
24743 SDValue(N, 1).use_empty()) {
24745 EVT VT = N->getValueType(0);
24746 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
24747 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24748 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24749 DAG.getConstant(X86::COND_B, DL,
24752 DAG.getConstant(1, DL, VT));
24753 return DCI.CombineTo(N, Res1, CarryOut);
24759 // fold (add Y, (sete X, 0)) -> adc 0, Y
24760 // (add Y, (setne X, 0)) -> sbb -1, Y
24761 // (sub (sete X, 0), Y) -> sbb 0, Y
24762 // (sub (setne X, 0), Y) -> adc -1, Y
24763 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24766 // Look through ZExts.
24767 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24768 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24771 SDValue SetCC = Ext.getOperand(0);
24772 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24775 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24776 if (CC != X86::COND_E && CC != X86::COND_NE)
24779 SDValue Cmp = SetCC.getOperand(1);
24780 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24781 !X86::isZeroNode(Cmp.getOperand(1)) ||
24782 !Cmp.getOperand(0).getValueType().isInteger())
24785 SDValue CmpOp0 = Cmp.getOperand(0);
24786 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24787 DAG.getConstant(1, DL, CmpOp0.getValueType()));
24789 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24790 if (CC == X86::COND_NE)
24791 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24792 DL, OtherVal.getValueType(), OtherVal,
24793 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
24795 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24796 DL, OtherVal.getValueType(), OtherVal,
24797 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
24800 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24801 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24802 const X86Subtarget *Subtarget) {
24803 EVT VT = N->getValueType(0);
24804 SDValue Op0 = N->getOperand(0);
24805 SDValue Op1 = N->getOperand(1);
24807 // Try to synthesize horizontal adds from adds of shuffles.
24808 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24809 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24810 isHorizontalBinOp(Op0, Op1, true))
24811 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24813 return OptimizeConditionalInDecrement(N, DAG);
24816 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24817 const X86Subtarget *Subtarget) {
24818 SDValue Op0 = N->getOperand(0);
24819 SDValue Op1 = N->getOperand(1);
24821 // X86 can't encode an immediate LHS of a sub. See if we can push the
24822 // negation into a preceding instruction.
24823 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24824 // If the RHS of the sub is a XOR with one use and a constant, invert the
24825 // immediate. Then add one to the LHS of the sub so we can turn
24826 // X-Y -> X+~Y+1, saving one register.
24827 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24828 isa<ConstantSDNode>(Op1.getOperand(1))) {
24829 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24830 EVT VT = Op0.getValueType();
24831 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24833 DAG.getConstant(~XorC, SDLoc(Op1), VT));
24834 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24835 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
24839 // Try to synthesize horizontal adds from adds of shuffles.
24840 EVT VT = N->getValueType(0);
24841 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24842 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24843 isHorizontalBinOp(Op0, Op1, true))
24844 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24846 return OptimizeConditionalInDecrement(N, DAG);
24849 /// performVZEXTCombine - Performs build vector combines
24850 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24851 TargetLowering::DAGCombinerInfo &DCI,
24852 const X86Subtarget *Subtarget) {
24854 MVT VT = N->getSimpleValueType(0);
24855 SDValue Op = N->getOperand(0);
24856 MVT OpVT = Op.getSimpleValueType();
24857 MVT OpEltVT = OpVT.getVectorElementType();
24858 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24860 // (vzext (bitcast (vzext (x)) -> (vzext x)
24862 while (V.getOpcode() == ISD::BITCAST)
24863 V = V.getOperand(0);
24865 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24866 MVT InnerVT = V.getSimpleValueType();
24867 MVT InnerEltVT = InnerVT.getVectorElementType();
24869 // If the element sizes match exactly, we can just do one larger vzext. This
24870 // is always an exact type match as vzext operates on integer types.
24871 if (OpEltVT == InnerEltVT) {
24872 assert(OpVT == InnerVT && "Types must match for vzext!");
24873 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24876 // The only other way we can combine them is if only a single element of the
24877 // inner vzext is used in the input to the outer vzext.
24878 if (InnerEltVT.getSizeInBits() < InputBits)
24881 // In this case, the inner vzext is completely dead because we're going to
24882 // only look at bits inside of the low element. Just do the outer vzext on
24883 // a bitcast of the input to the inner.
24884 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
24887 // Check if we can bypass extracting and re-inserting an element of an input
24888 // vector. Essentialy:
24889 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24890 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24891 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24892 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24893 SDValue ExtractedV = V.getOperand(0);
24894 SDValue OrigV = ExtractedV.getOperand(0);
24895 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24896 if (ExtractIdx->getZExtValue() == 0) {
24897 MVT OrigVT = OrigV.getSimpleValueType();
24898 // Extract a subvector if necessary...
24899 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24900 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24901 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24902 OrigVT.getVectorNumElements() / Ratio);
24903 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24904 DAG.getIntPtrConstant(0, DL));
24906 Op = DAG.getBitcast(OpVT, OrigV);
24907 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24914 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24915 DAGCombinerInfo &DCI) const {
24916 SelectionDAG &DAG = DCI.DAG;
24917 switch (N->getOpcode()) {
24919 case ISD::EXTRACT_VECTOR_ELT:
24920 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24923 case X86ISD::SHRUNKBLEND:
24924 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24925 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
24926 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24927 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24928 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24929 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24930 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24933 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24934 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24935 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24936 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24937 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24938 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
24939 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24940 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
24941 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
24942 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
24943 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24944 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24946 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24948 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24949 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24950 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24951 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24952 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24953 case ISD::ANY_EXTEND:
24954 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24955 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24956 case ISD::SIGN_EXTEND_INREG:
24957 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24958 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24959 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24960 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24961 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24962 case X86ISD::SHUFP: // Handle all target specific shuffles
24963 case X86ISD::PALIGNR:
24964 case X86ISD::UNPCKH:
24965 case X86ISD::UNPCKL:
24966 case X86ISD::MOVHLPS:
24967 case X86ISD::MOVLHPS:
24968 case X86ISD::PSHUFB:
24969 case X86ISD::PSHUFD:
24970 case X86ISD::PSHUFHW:
24971 case X86ISD::PSHUFLW:
24972 case X86ISD::MOVSS:
24973 case X86ISD::MOVSD:
24974 case X86ISD::VPERMILPI:
24975 case X86ISD::VPERM2X128:
24976 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24977 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24978 case ISD::INTRINSIC_WO_CHAIN:
24979 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24980 case X86ISD::INSERTPS: {
24981 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
24982 return PerformINSERTPSCombine(N, DAG, Subtarget);
24985 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
24991 /// isTypeDesirableForOp - Return true if the target has native support for
24992 /// the specified value type and it is 'desirable' to use the type for the
24993 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24994 /// instruction encodings are longer and some i16 instructions are slow.
24995 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24996 if (!isTypeLegal(VT))
24998 if (VT != MVT::i16)
25005 case ISD::SIGN_EXTEND:
25006 case ISD::ZERO_EXTEND:
25007 case ISD::ANY_EXTEND:
25020 /// IsDesirableToPromoteOp - This method query the target whether it is
25021 /// beneficial for dag combiner to promote the specified node. If true, it
25022 /// should return the desired promotion type by reference.
25023 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25024 EVT VT = Op.getValueType();
25025 if (VT != MVT::i16)
25028 bool Promote = false;
25029 bool Commute = false;
25030 switch (Op.getOpcode()) {
25033 LoadSDNode *LD = cast<LoadSDNode>(Op);
25034 // If the non-extending load has a single use and it's not live out, then it
25035 // might be folded.
25036 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25037 Op.hasOneUse()*/) {
25038 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25039 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25040 // The only case where we'd want to promote LOAD (rather then it being
25041 // promoted as an operand is when it's only use is liveout.
25042 if (UI->getOpcode() != ISD::CopyToReg)
25049 case ISD::SIGN_EXTEND:
25050 case ISD::ZERO_EXTEND:
25051 case ISD::ANY_EXTEND:
25056 SDValue N0 = Op.getOperand(0);
25057 // Look out for (store (shl (load), x)).
25058 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25071 SDValue N0 = Op.getOperand(0);
25072 SDValue N1 = Op.getOperand(1);
25073 if (!Commute && MayFoldLoad(N1))
25075 // Avoid disabling potential load folding opportunities.
25076 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25078 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25088 //===----------------------------------------------------------------------===//
25089 // X86 Inline Assembly Support
25090 //===----------------------------------------------------------------------===//
25092 // Helper to match a string separated by whitespace.
25093 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
25094 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
25096 for (StringRef Piece : Pieces) {
25097 if (!S.startswith(Piece)) // Check if the piece matches.
25100 S = S.substr(Piece.size());
25101 StringRef::size_type Pos = S.find_first_not_of(" \t");
25102 if (Pos == 0) // We matched a prefix.
25111 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25113 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25114 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25115 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25116 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25118 if (AsmPieces.size() == 3)
25120 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25127 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25128 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25130 std::string AsmStr = IA->getAsmString();
25132 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25133 if (!Ty || Ty->getBitWidth() % 16 != 0)
25136 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25137 SmallVector<StringRef, 4> AsmPieces;
25138 SplitString(AsmStr, AsmPieces, ";\n");
25140 switch (AsmPieces.size()) {
25141 default: return false;
25143 // FIXME: this should verify that we are targeting a 486 or better. If not,
25144 // we will turn this bswap into something that will be lowered to logical
25145 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25146 // lower so don't worry about this.
25148 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
25149 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
25150 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
25151 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
25152 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
25153 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
25154 // No need to check constraints, nothing other than the equivalent of
25155 // "=r,0" would be valid here.
25156 return IntrinsicLowering::LowerToByteSwap(CI);
25159 // rorw $$8, ${0:w} --> llvm.bswap.i16
25160 if (CI->getType()->isIntegerTy(16) &&
25161 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25162 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
25163 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
25165 const std::string &ConstraintsStr = IA->getConstraintString();
25166 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25167 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25168 if (clobbersFlagRegisters(AsmPieces))
25169 return IntrinsicLowering::LowerToByteSwap(CI);
25173 if (CI->getType()->isIntegerTy(32) &&
25174 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25175 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
25176 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
25177 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
25179 const std::string &ConstraintsStr = IA->getConstraintString();
25180 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25181 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25182 if (clobbersFlagRegisters(AsmPieces))
25183 return IntrinsicLowering::LowerToByteSwap(CI);
25186 if (CI->getType()->isIntegerTy(64)) {
25187 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25188 if (Constraints.size() >= 2 &&
25189 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25190 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25191 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25192 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
25193 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
25194 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
25195 return IntrinsicLowering::LowerToByteSwap(CI);
25203 /// getConstraintType - Given a constraint letter, return the type of
25204 /// constraint it is for this target.
25205 X86TargetLowering::ConstraintType
25206 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25207 if (Constraint.size() == 1) {
25208 switch (Constraint[0]) {
25219 return C_RegisterClass;
25243 return TargetLowering::getConstraintType(Constraint);
25246 /// Examine constraint type and operand type and determine a weight value.
25247 /// This object must already have been set up with the operand type
25248 /// and the current alternative constraint selected.
25249 TargetLowering::ConstraintWeight
25250 X86TargetLowering::getSingleConstraintMatchWeight(
25251 AsmOperandInfo &info, const char *constraint) const {
25252 ConstraintWeight weight = CW_Invalid;
25253 Value *CallOperandVal = info.CallOperandVal;
25254 // If we don't have a value, we can't do a match,
25255 // but allow it at the lowest weight.
25256 if (!CallOperandVal)
25258 Type *type = CallOperandVal->getType();
25259 // Look at the constraint type.
25260 switch (*constraint) {
25262 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25273 if (CallOperandVal->getType()->isIntegerTy())
25274 weight = CW_SpecificReg;
25279 if (type->isFloatingPointTy())
25280 weight = CW_SpecificReg;
25283 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25284 weight = CW_SpecificReg;
25288 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25289 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25290 weight = CW_Register;
25293 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25294 if (C->getZExtValue() <= 31)
25295 weight = CW_Constant;
25299 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25300 if (C->getZExtValue() <= 63)
25301 weight = CW_Constant;
25305 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25306 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25307 weight = CW_Constant;
25311 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25312 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25313 weight = CW_Constant;
25317 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25318 if (C->getZExtValue() <= 3)
25319 weight = CW_Constant;
25323 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25324 if (C->getZExtValue() <= 0xff)
25325 weight = CW_Constant;
25330 if (isa<ConstantFP>(CallOperandVal)) {
25331 weight = CW_Constant;
25335 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25336 if ((C->getSExtValue() >= -0x80000000LL) &&
25337 (C->getSExtValue() <= 0x7fffffffLL))
25338 weight = CW_Constant;
25342 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25343 if (C->getZExtValue() <= 0xffffffff)
25344 weight = CW_Constant;
25351 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25352 /// with another that has more specific requirements based on the type of the
25353 /// corresponding operand.
25354 const char *X86TargetLowering::
25355 LowerXConstraint(EVT ConstraintVT) const {
25356 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25357 // 'f' like normal targets.
25358 if (ConstraintVT.isFloatingPoint()) {
25359 if (Subtarget->hasSSE2())
25361 if (Subtarget->hasSSE1())
25365 return TargetLowering::LowerXConstraint(ConstraintVT);
25368 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25369 /// vector. If it is invalid, don't add anything to Ops.
25370 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25371 std::string &Constraint,
25372 std::vector<SDValue>&Ops,
25373 SelectionDAG &DAG) const {
25376 // Only support length 1 constraints for now.
25377 if (Constraint.length() > 1) return;
25379 char ConstraintLetter = Constraint[0];
25380 switch (ConstraintLetter) {
25383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25384 if (C->getZExtValue() <= 31) {
25385 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25386 Op.getValueType());
25392 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25393 if (C->getZExtValue() <= 63) {
25394 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25395 Op.getValueType());
25401 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25402 if (isInt<8>(C->getSExtValue())) {
25403 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25404 Op.getValueType());
25410 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25411 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
25412 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
25413 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
25414 Op.getValueType());
25420 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25421 if (C->getZExtValue() <= 3) {
25422 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25423 Op.getValueType());
25429 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25430 if (C->getZExtValue() <= 255) {
25431 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25432 Op.getValueType());
25438 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25439 if (C->getZExtValue() <= 127) {
25440 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25441 Op.getValueType());
25447 // 32-bit signed value
25448 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25449 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25450 C->getSExtValue())) {
25451 // Widen to 64 bits here to get it sign extended.
25452 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
25455 // FIXME gcc accepts some relocatable values here too, but only in certain
25456 // memory models; it's complicated.
25461 // 32-bit unsigned value
25462 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25463 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25464 C->getZExtValue())) {
25465 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25466 Op.getValueType());
25470 // FIXME gcc accepts some relocatable values here too, but only in certain
25471 // memory models; it's complicated.
25475 // Literal immediates are always ok.
25476 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25477 // Widen to 64 bits here to get it sign extended.
25478 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
25482 // In any sort of PIC mode addresses need to be computed at runtime by
25483 // adding in a register or some sort of table lookup. These can't
25484 // be used as immediates.
25485 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25488 // If we are in non-pic codegen mode, we allow the address of a global (with
25489 // an optional displacement) to be used with 'i'.
25490 GlobalAddressSDNode *GA = nullptr;
25491 int64_t Offset = 0;
25493 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25495 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25496 Offset += GA->getOffset();
25498 } else if (Op.getOpcode() == ISD::ADD) {
25499 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25500 Offset += C->getZExtValue();
25501 Op = Op.getOperand(0);
25504 } else if (Op.getOpcode() == ISD::SUB) {
25505 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25506 Offset += -C->getZExtValue();
25507 Op = Op.getOperand(0);
25512 // Otherwise, this isn't something we can handle, reject it.
25516 const GlobalValue *GV = GA->getGlobal();
25517 // If we require an extra load to get this address, as in PIC mode, we
25518 // can't accept it.
25519 if (isGlobalStubReference(
25520 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25523 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25524 GA->getValueType(0), Offset);
25529 if (Result.getNode()) {
25530 Ops.push_back(Result);
25533 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25536 std::pair<unsigned, const TargetRegisterClass *>
25537 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
25538 const std::string &Constraint,
25540 // First, see if this is a constraint that directly corresponds to an LLVM
25542 if (Constraint.size() == 1) {
25543 // GCC Constraint Letters
25544 switch (Constraint[0]) {
25546 // TODO: Slight differences here in allocation order and leaving
25547 // RIP in the class. Do they matter any more here than they do
25548 // in the normal allocation?
25549 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25550 if (Subtarget->is64Bit()) {
25551 if (VT == MVT::i32 || VT == MVT::f32)
25552 return std::make_pair(0U, &X86::GR32RegClass);
25553 if (VT == MVT::i16)
25554 return std::make_pair(0U, &X86::GR16RegClass);
25555 if (VT == MVT::i8 || VT == MVT::i1)
25556 return std::make_pair(0U, &X86::GR8RegClass);
25557 if (VT == MVT::i64 || VT == MVT::f64)
25558 return std::make_pair(0U, &X86::GR64RegClass);
25561 // 32-bit fallthrough
25562 case 'Q': // Q_REGS
25563 if (VT == MVT::i32 || VT == MVT::f32)
25564 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25565 if (VT == MVT::i16)
25566 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25567 if (VT == MVT::i8 || VT == MVT::i1)
25568 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25569 if (VT == MVT::i64)
25570 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25572 case 'r': // GENERAL_REGS
25573 case 'l': // INDEX_REGS
25574 if (VT == MVT::i8 || VT == MVT::i1)
25575 return std::make_pair(0U, &X86::GR8RegClass);
25576 if (VT == MVT::i16)
25577 return std::make_pair(0U, &X86::GR16RegClass);
25578 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25579 return std::make_pair(0U, &X86::GR32RegClass);
25580 return std::make_pair(0U, &X86::GR64RegClass);
25581 case 'R': // LEGACY_REGS
25582 if (VT == MVT::i8 || VT == MVT::i1)
25583 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25584 if (VT == MVT::i16)
25585 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25586 if (VT == MVT::i32 || !Subtarget->is64Bit())
25587 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25588 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25589 case 'f': // FP Stack registers.
25590 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25591 // value to the correct fpstack register class.
25592 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25593 return std::make_pair(0U, &X86::RFP32RegClass);
25594 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25595 return std::make_pair(0U, &X86::RFP64RegClass);
25596 return std::make_pair(0U, &X86::RFP80RegClass);
25597 case 'y': // MMX_REGS if MMX allowed.
25598 if (!Subtarget->hasMMX()) break;
25599 return std::make_pair(0U, &X86::VR64RegClass);
25600 case 'Y': // SSE_REGS if SSE2 allowed
25601 if (!Subtarget->hasSSE2()) break;
25603 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25604 if (!Subtarget->hasSSE1()) break;
25606 switch (VT.SimpleTy) {
25608 // Scalar SSE types.
25611 return std::make_pair(0U, &X86::FR32RegClass);
25614 return std::make_pair(0U, &X86::FR64RegClass);
25622 return std::make_pair(0U, &X86::VR128RegClass);
25630 return std::make_pair(0U, &X86::VR256RegClass);
25635 return std::make_pair(0U, &X86::VR512RegClass);
25641 // Use the default implementation in TargetLowering to convert the register
25642 // constraint into a member of a register class.
25643 std::pair<unsigned, const TargetRegisterClass*> Res;
25644 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
25646 // Not found as a standard register?
25648 // Map st(0) -> st(7) -> ST0
25649 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25650 tolower(Constraint[1]) == 's' &&
25651 tolower(Constraint[2]) == 't' &&
25652 Constraint[3] == '(' &&
25653 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25654 Constraint[5] == ')' &&
25655 Constraint[6] == '}') {
25657 Res.first = X86::FP0+Constraint[4]-'0';
25658 Res.second = &X86::RFP80RegClass;
25662 // GCC allows "st(0)" to be called just plain "st".
25663 if (StringRef("{st}").equals_lower(Constraint)) {
25664 Res.first = X86::FP0;
25665 Res.second = &X86::RFP80RegClass;
25670 if (StringRef("{flags}").equals_lower(Constraint)) {
25671 Res.first = X86::EFLAGS;
25672 Res.second = &X86::CCRRegClass;
25676 // 'A' means EAX + EDX.
25677 if (Constraint == "A") {
25678 Res.first = X86::EAX;
25679 Res.second = &X86::GR32_ADRegClass;
25685 // Otherwise, check to see if this is a register class of the wrong value
25686 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25687 // turn into {ax},{dx}.
25688 // MVT::Other is used to specify clobber names.
25689 if (Res.second->hasType(VT) || VT == MVT::Other)
25690 return Res; // Correct type already, nothing to do.
25692 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
25693 // return "eax". This should even work for things like getting 64bit integer
25694 // registers when given an f64 type.
25695 const TargetRegisterClass *Class = Res.second;
25696 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
25697 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
25698 unsigned Size = VT.getSizeInBits();
25699 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
25700 : Size == 16 ? MVT::i16
25701 : Size == 32 ? MVT::i32
25702 : Size == 64 ? MVT::i64
25704 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
25706 Res.first = DestReg;
25707 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
25708 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
25709 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
25710 : &X86::GR64RegClass;
25711 assert(Res.second->contains(Res.first) && "Register in register class");
25713 // No register found/type mismatch.
25715 Res.second = nullptr;
25717 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
25718 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
25719 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
25720 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
25721 Class == &X86::VR512RegClass) {
25722 // Handle references to XMM physical registers that got mapped into the
25723 // wrong class. This can happen with constraints like {xmm0} where the
25724 // target independent register mapper will just pick the first match it can
25725 // find, ignoring the required type.
25727 if (VT == MVT::f32 || VT == MVT::i32)
25728 Res.second = &X86::FR32RegClass;
25729 else if (VT == MVT::f64 || VT == MVT::i64)
25730 Res.second = &X86::FR64RegClass;
25731 else if (X86::VR128RegClass.hasType(VT))
25732 Res.second = &X86::VR128RegClass;
25733 else if (X86::VR256RegClass.hasType(VT))
25734 Res.second = &X86::VR256RegClass;
25735 else if (X86::VR512RegClass.hasType(VT))
25736 Res.second = &X86::VR512RegClass;
25738 // Type mismatch and not a clobber: Return an error;
25740 Res.second = nullptr;
25747 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25749 unsigned AS) const {
25750 // Scaling factors are not free at all.
25751 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25752 // will take 2 allocations in the out of order engine instead of 1
25753 // for plain addressing mode, i.e. inst (reg1).
25755 // vaddps (%rsi,%drx), %ymm0, %ymm1
25756 // Requires two allocations (one for the load, one for the computation)
25758 // vaddps (%rsi), %ymm0, %ymm1
25759 // Requires just 1 allocation, i.e., freeing allocations for other operations
25760 // and having less micro operations to execute.
25762 // For some X86 architectures, this is even worse because for instance for
25763 // stores, the complex addressing mode forces the instruction to use the
25764 // "load" ports instead of the dedicated "store" port.
25765 // E.g., on Haswell:
25766 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25767 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25768 if (isLegalAddressingMode(AM, Ty, AS))
25769 // Scale represents reg2 * scale, thus account for 1
25770 // as soon as we use a second register.
25771 return AM.Scale != 0;
25775 bool X86TargetLowering::isTargetFTOL() const {
25776 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();