1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::BLENDI:
3543 case X86ISD::PSHUFB:
3544 case X86ISD::PSHUFD:
3545 case X86ISD::PSHUFHW:
3546 case X86ISD::PSHUFLW:
3548 case X86ISD::PALIGNR:
3549 case X86ISD::MOVLHPS:
3550 case X86ISD::MOVLHPD:
3551 case X86ISD::MOVHLPS:
3552 case X86ISD::MOVLPS:
3553 case X86ISD::MOVLPD:
3554 case X86ISD::MOVSHDUP:
3555 case X86ISD::MOVSLDUP:
3556 case X86ISD::MOVDDUP:
3559 case X86ISD::UNPCKL:
3560 case X86ISD::UNPCKH:
3561 case X86ISD::VPERMILPI:
3562 case X86ISD::VPERM2X128:
3563 case X86ISD::VPERMI:
3568 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3569 SDValue V1, SelectionDAG &DAG) {
3571 default: llvm_unreachable("Unknown x86 shuffle node");
3572 case X86ISD::MOVSHDUP:
3573 case X86ISD::MOVSLDUP:
3574 case X86ISD::MOVDDUP:
3575 return DAG.getNode(Opc, dl, VT, V1);
3579 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3580 SDValue V1, unsigned TargetMask,
3581 SelectionDAG &DAG) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::PSHUFD:
3585 case X86ISD::PSHUFHW:
3586 case X86ISD::PSHUFLW:
3587 case X86ISD::VPERMILPI:
3588 case X86ISD::VPERMI:
3589 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3593 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3594 SDValue V1, SDValue V2, unsigned TargetMask,
3595 SelectionDAG &DAG) {
3597 default: llvm_unreachable("Unknown x86 shuffle node");
3598 case X86ISD::PALIGNR:
3599 case X86ISD::VALIGN:
3601 case X86ISD::VPERM2X128:
3602 return DAG.getNode(Opc, dl, VT, V1, V2,
3603 DAG.getConstant(TargetMask, MVT::i8));
3607 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3608 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3610 default: llvm_unreachable("Unknown x86 shuffle node");
3611 case X86ISD::MOVLHPS:
3612 case X86ISD::MOVLHPD:
3613 case X86ISD::MOVHLPS:
3614 case X86ISD::MOVLPS:
3615 case X86ISD::MOVLPD:
3618 case X86ISD::UNPCKL:
3619 case X86ISD::UNPCKH:
3620 return DAG.getNode(Opc, dl, VT, V1, V2);
3624 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3625 MachineFunction &MF = DAG.getMachineFunction();
3626 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3627 DAG.getSubtarget().getRegisterInfo());
3628 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3629 int ReturnAddrIndex = FuncInfo->getRAIndex();
3631 if (ReturnAddrIndex == 0) {
3632 // Set up a frame object for the return address.
3633 unsigned SlotSize = RegInfo->getSlotSize();
3634 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3637 FuncInfo->setRAIndex(ReturnAddrIndex);
3640 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3643 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3644 bool hasSymbolicDisplacement) {
3645 // Offset should fit into 32 bit immediate field.
3646 if (!isInt<32>(Offset))
3649 // If we don't have a symbolic displacement - we don't have any extra
3651 if (!hasSymbolicDisplacement)
3654 // FIXME: Some tweaks might be needed for medium code model.
3655 if (M != CodeModel::Small && M != CodeModel::Kernel)
3658 // For small code model we assume that latest object is 16MB before end of 31
3659 // bits boundary. We may also accept pretty large negative constants knowing
3660 // that all objects are in the positive half of address space.
3661 if (M == CodeModel::Small && Offset < 16*1024*1024)
3664 // For kernel code model we know that all object resist in the negative half
3665 // of 32bits address space. We may not accept negative offsets, since they may
3666 // be just off and we may accept pretty large positive ones.
3667 if (M == CodeModel::Kernel && Offset > 0)
3673 /// isCalleePop - Determines whether the callee is required to pop its
3674 /// own arguments. Callee pop is necessary to support tail calls.
3675 bool X86::isCalleePop(CallingConv::ID CallingConv,
3676 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3677 switch (CallingConv) {
3680 case CallingConv::X86_StdCall:
3681 case CallingConv::X86_FastCall:
3682 case CallingConv::X86_ThisCall:
3684 case CallingConv::Fast:
3685 case CallingConv::GHC:
3686 case CallingConv::HiPE:
3693 /// \brief Return true if the condition is an unsigned comparison operation.
3694 static bool isX86CCUnsigned(unsigned X86CC) {
3696 default: llvm_unreachable("Invalid integer condition!");
3697 case X86::COND_E: return true;
3698 case X86::COND_G: return false;
3699 case X86::COND_GE: return false;
3700 case X86::COND_L: return false;
3701 case X86::COND_LE: return false;
3702 case X86::COND_NE: return true;
3703 case X86::COND_B: return true;
3704 case X86::COND_A: return true;
3705 case X86::COND_BE: return true;
3706 case X86::COND_AE: return true;
3708 llvm_unreachable("covered switch fell through?!");
3711 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3712 /// specific condition code, returning the condition code and the LHS/RHS of the
3713 /// comparison to make.
3714 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3715 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3718 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3719 // X > -1 -> X == 0, jump !sign.
3720 RHS = DAG.getConstant(0, RHS.getValueType());
3721 return X86::COND_NS;
3723 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3724 // X < 0 -> X == 0, jump on sign.
3727 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3729 RHS = DAG.getConstant(0, RHS.getValueType());
3730 return X86::COND_LE;
3734 switch (SetCCOpcode) {
3735 default: llvm_unreachable("Invalid integer condition!");
3736 case ISD::SETEQ: return X86::COND_E;
3737 case ISD::SETGT: return X86::COND_G;
3738 case ISD::SETGE: return X86::COND_GE;
3739 case ISD::SETLT: return X86::COND_L;
3740 case ISD::SETLE: return X86::COND_LE;
3741 case ISD::SETNE: return X86::COND_NE;
3742 case ISD::SETULT: return X86::COND_B;
3743 case ISD::SETUGT: return X86::COND_A;
3744 case ISD::SETULE: return X86::COND_BE;
3745 case ISD::SETUGE: return X86::COND_AE;
3749 // First determine if it is required or is profitable to flip the operands.
3751 // If LHS is a foldable load, but RHS is not, flip the condition.
3752 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3753 !ISD::isNON_EXTLoad(RHS.getNode())) {
3754 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3755 std::swap(LHS, RHS);
3758 switch (SetCCOpcode) {
3764 std::swap(LHS, RHS);
3768 // On a floating point condition, the flags are set as follows:
3770 // 0 | 0 | 0 | X > Y
3771 // 0 | 0 | 1 | X < Y
3772 // 1 | 0 | 0 | X == Y
3773 // 1 | 1 | 1 | unordered
3774 switch (SetCCOpcode) {
3775 default: llvm_unreachable("Condcode should be pre-legalized away");
3777 case ISD::SETEQ: return X86::COND_E;
3778 case ISD::SETOLT: // flipped
3780 case ISD::SETGT: return X86::COND_A;
3781 case ISD::SETOLE: // flipped
3783 case ISD::SETGE: return X86::COND_AE;
3784 case ISD::SETUGT: // flipped
3786 case ISD::SETLT: return X86::COND_B;
3787 case ISD::SETUGE: // flipped
3789 case ISD::SETLE: return X86::COND_BE;
3791 case ISD::SETNE: return X86::COND_NE;
3792 case ISD::SETUO: return X86::COND_P;
3793 case ISD::SETO: return X86::COND_NP;
3795 case ISD::SETUNE: return X86::COND_INVALID;
3799 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3800 /// code. Current x86 isa includes the following FP cmov instructions:
3801 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3802 static bool hasFPCMov(unsigned X86CC) {
3818 /// isFPImmLegal - Returns true if the target can instruction select the
3819 /// specified FP immediate natively. If false, the legalizer will
3820 /// materialize the FP immediate as a load from a constant pool.
3821 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3822 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3823 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3829 /// \brief Returns true if it is beneficial to convert a load of a constant
3830 /// to just the constant itself.
3831 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3833 assert(Ty->isIntegerTy());
3835 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3836 if (BitSize == 0 || BitSize > 64)
3841 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3842 /// the specified range (L, H].
3843 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3844 return (Val < 0) || (Val >= Low && Val < Hi);
3847 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3848 /// specified value.
3849 static bool isUndefOrEqual(int Val, int CmpVal) {
3850 return (Val < 0 || Val == CmpVal);
3853 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3854 /// from position Pos and ending in Pos+Size, falls within the specified
3855 /// sequential range (L, L+Pos]. or is undef.
3856 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3857 unsigned Pos, unsigned Size, int Low) {
3858 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3859 if (!isUndefOrEqual(Mask[i], Low))
3864 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3865 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3866 /// the second operand.
3867 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3868 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3869 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3870 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3871 return (Mask[0] < 2 && Mask[1] < 2);
3875 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3876 /// is suitable for input to PSHUFHW.
3877 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3878 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3881 // Lower quadword copied in order or undef.
3882 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3885 // Upper quadword shuffled.
3886 for (unsigned i = 4; i != 8; ++i)
3887 if (!isUndefOrInRange(Mask[i], 4, 8))
3890 if (VT == MVT::v16i16) {
3891 // Lower quadword copied in order or undef.
3892 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3895 // Upper quadword shuffled.
3896 for (unsigned i = 12; i != 16; ++i)
3897 if (!isUndefOrInRange(Mask[i], 12, 16))
3904 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3905 /// is suitable for input to PSHUFLW.
3906 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3907 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3910 // Upper quadword copied in order.
3911 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3914 // Lower quadword shuffled.
3915 for (unsigned i = 0; i != 4; ++i)
3916 if (!isUndefOrInRange(Mask[i], 0, 4))
3919 if (VT == MVT::v16i16) {
3920 // Upper quadword copied in order.
3921 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3924 // Lower quadword shuffled.
3925 for (unsigned i = 8; i != 12; ++i)
3926 if (!isUndefOrInRange(Mask[i], 8, 12))
3933 /// \brief Return true if the mask specifies a shuffle of elements that is
3934 /// suitable for input to intralane (palignr) or interlane (valign) vector
3936 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3937 unsigned NumElts = VT.getVectorNumElements();
3938 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3939 unsigned NumLaneElts = NumElts/NumLanes;
3941 // Do not handle 64-bit element shuffles with palignr.
3942 if (NumLaneElts == 2)
3945 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3947 for (i = 0; i != NumLaneElts; ++i) {
3952 // Lane is all undef, go to next lane
3953 if (i == NumLaneElts)
3956 int Start = Mask[i+l];
3958 // Make sure its in this lane in one of the sources
3959 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3960 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3963 // If not lane 0, then we must match lane 0
3964 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3967 // Correct second source to be contiguous with first source
3968 if (Start >= (int)NumElts)
3969 Start -= NumElts - NumLaneElts;
3971 // Make sure we're shifting in the right direction.
3972 if (Start <= (int)(i+l))
3977 // Check the rest of the elements to see if they are consecutive.
3978 for (++i; i != NumLaneElts; ++i) {
3979 int Idx = Mask[i+l];
3981 // Make sure its in this lane
3982 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3983 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3986 // If not lane 0, then we must match lane 0
3987 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3990 if (Idx >= (int)NumElts)
3991 Idx -= NumElts - NumLaneElts;
3993 if (!isUndefOrEqual(Idx, Start+i))
4002 /// \brief Return true if the node specifies a shuffle of elements that is
4003 /// suitable for input to PALIGNR.
4004 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4005 const X86Subtarget *Subtarget) {
4006 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4007 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4008 VT.is512BitVector())
4009 // FIXME: Add AVX512BW.
4012 return isAlignrMask(Mask, VT, false);
4015 /// \brief Return true if the node specifies a shuffle of elements that is
4016 /// suitable for input to VALIGN.
4017 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4018 const X86Subtarget *Subtarget) {
4019 // FIXME: Add AVX512VL.
4020 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4022 return isAlignrMask(Mask, VT, true);
4025 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4026 /// the two vector operands have swapped position.
4027 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4028 unsigned NumElems) {
4029 for (unsigned i = 0; i != NumElems; ++i) {
4033 else if (idx < (int)NumElems)
4034 Mask[i] = idx + NumElems;
4036 Mask[i] = idx - NumElems;
4040 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4041 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4042 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4043 /// reverse of what x86 shuffles want.
4044 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4046 unsigned NumElems = VT.getVectorNumElements();
4047 unsigned NumLanes = VT.getSizeInBits()/128;
4048 unsigned NumLaneElems = NumElems/NumLanes;
4050 if (NumLaneElems != 2 && NumLaneElems != 4)
4053 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4054 bool symetricMaskRequired =
4055 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4057 // VSHUFPSY divides the resulting vector into 4 chunks.
4058 // The sources are also splitted into 4 chunks, and each destination
4059 // chunk must come from a different source chunk.
4061 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4062 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4064 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4065 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4067 // VSHUFPDY divides the resulting vector into 4 chunks.
4068 // The sources are also splitted into 4 chunks, and each destination
4069 // chunk must come from a different source chunk.
4071 // SRC1 => X3 X2 X1 X0
4072 // SRC2 => Y3 Y2 Y1 Y0
4074 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4076 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4077 unsigned HalfLaneElems = NumLaneElems/2;
4078 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4079 for (unsigned i = 0; i != NumLaneElems; ++i) {
4080 int Idx = Mask[i+l];
4081 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4082 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4084 // For VSHUFPSY, the mask of the second half must be the same as the
4085 // first but with the appropriate offsets. This works in the same way as
4086 // VPERMILPS works with masks.
4087 if (!symetricMaskRequired || Idx < 0)
4089 if (MaskVal[i] < 0) {
4090 MaskVal[i] = Idx - l;
4093 if ((signed)(Idx - l) != MaskVal[i])
4101 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4102 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4103 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4104 if (!VT.is128BitVector())
4107 unsigned NumElems = VT.getVectorNumElements();
4112 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4113 return isUndefOrEqual(Mask[0], 6) &&
4114 isUndefOrEqual(Mask[1], 7) &&
4115 isUndefOrEqual(Mask[2], 2) &&
4116 isUndefOrEqual(Mask[3], 3);
4119 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4120 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4122 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4123 if (!VT.is128BitVector())
4126 unsigned NumElems = VT.getVectorNumElements();
4131 return isUndefOrEqual(Mask[0], 2) &&
4132 isUndefOrEqual(Mask[1], 3) &&
4133 isUndefOrEqual(Mask[2], 2) &&
4134 isUndefOrEqual(Mask[3], 3);
4137 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4138 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4139 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4140 if (!VT.is128BitVector())
4143 unsigned NumElems = VT.getVectorNumElements();
4145 if (NumElems != 2 && NumElems != 4)
4148 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4149 if (!isUndefOrEqual(Mask[i], i + NumElems))
4152 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4153 if (!isUndefOrEqual(Mask[i], i))
4159 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4160 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4161 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4162 if (!VT.is128BitVector())
4165 unsigned NumElems = VT.getVectorNumElements();
4167 if (NumElems != 2 && NumElems != 4)
4170 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i))
4174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4181 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4182 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4183 /// i. e: If all but one element come from the same vector.
4184 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4185 // TODO: Deal with AVX's VINSERTPS
4186 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4189 unsigned CorrectPosV1 = 0;
4190 unsigned CorrectPosV2 = 0;
4191 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4192 if (Mask[i] == -1) {
4200 else if (Mask[i] == i + 4)
4204 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4205 // We have 3 elements (undefs count as elements from any vector) from one
4206 // vector, and one from another.
4213 // Some special combinations that can be optimized.
4216 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4217 SelectionDAG &DAG) {
4218 MVT VT = SVOp->getSimpleValueType(0);
4221 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4224 ArrayRef<int> Mask = SVOp->getMask();
4226 // These are the special masks that may be optimized.
4227 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4228 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4229 bool MatchEvenMask = true;
4230 bool MatchOddMask = true;
4231 for (int i=0; i<8; ++i) {
4232 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4233 MatchEvenMask = false;
4234 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4235 MatchOddMask = false;
4238 if (!MatchEvenMask && !MatchOddMask)
4241 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4243 SDValue Op0 = SVOp->getOperand(0);
4244 SDValue Op1 = SVOp->getOperand(1);
4246 if (MatchEvenMask) {
4247 // Shift the second operand right to 32 bits.
4248 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4249 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4251 // Shift the first operand left to 32 bits.
4252 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4253 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4255 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4256 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4259 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4260 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4261 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4262 bool HasInt256, bool V2IsSplat = false) {
4264 assert(VT.getSizeInBits() >= 128 &&
4265 "Unsupported vector type for unpckl");
4267 unsigned NumElts = VT.getVectorNumElements();
4268 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4269 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4272 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4273 "Unsupported vector type for unpckh");
4275 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned NumLaneElts = NumElts/NumLanes;
4279 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4280 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4281 int BitI = Mask[l+i];
4282 int BitI1 = Mask[l+i+1];
4283 if (!isUndefOrEqual(BitI, j))
4286 if (!isUndefOrEqual(BitI1, NumElts))
4289 if (!isUndefOrEqual(BitI1, j + NumElts))
4298 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4299 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4300 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4301 bool HasInt256, bool V2IsSplat = false) {
4302 assert(VT.getSizeInBits() >= 128 &&
4303 "Unsupported vector type for unpckh");
4305 unsigned NumElts = VT.getVectorNumElements();
4306 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4307 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4310 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4311 "Unsupported vector type for unpckh");
4313 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4314 unsigned NumLanes = VT.getSizeInBits()/128;
4315 unsigned NumLaneElts = NumElts/NumLanes;
4317 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4318 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4319 int BitI = Mask[l+i];
4320 int BitI1 = Mask[l+i+1];
4321 if (!isUndefOrEqual(BitI, j))
4324 if (isUndefOrEqual(BitI1, NumElts))
4327 if (!isUndefOrEqual(BitI1, j+NumElts))
4335 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4336 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4338 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4339 unsigned NumElts = VT.getVectorNumElements();
4340 bool Is256BitVec = VT.is256BitVector();
4342 if (VT.is512BitVector())
4344 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4345 "Unsupported vector type for unpckh");
4347 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4348 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4351 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4352 // FIXME: Need a better way to get rid of this, there's no latency difference
4353 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4354 // the former later. We should also remove the "_undef" special mask.
4355 if (NumElts == 4 && Is256BitVec)
4358 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4359 // independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4368 if (!isUndefOrEqual(BitI, j))
4370 if (!isUndefOrEqual(BitI1, j))
4378 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4379 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4381 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4382 unsigned NumElts = VT.getVectorNumElements();
4384 if (VT.is512BitVector())
4387 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4388 "Unsupported vector type for unpckh");
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4394 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4395 // independently on 128-bit lanes.
4396 unsigned NumLanes = VT.getSizeInBits()/128;
4397 unsigned NumLaneElts = NumElts/NumLanes;
4399 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4400 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4401 int BitI = Mask[l+i];
4402 int BitI1 = Mask[l+i+1];
4403 if (!isUndefOrEqual(BitI, j))
4405 if (!isUndefOrEqual(BitI1, j))
4412 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4413 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4414 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4415 if (!VT.is512BitVector())
4418 unsigned NumElts = VT.getVectorNumElements();
4419 unsigned HalfSize = NumElts/2;
4420 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4421 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4435 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4436 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4437 /// MOVSD, and MOVD, i.e. setting the lowest element.
4438 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4439 if (VT.getVectorElementType().getSizeInBits() < 32)
4441 if (!VT.is128BitVector())
4444 unsigned NumElts = VT.getVectorNumElements();
4446 if (!isUndefOrEqual(Mask[0], NumElts))
4449 for (unsigned i = 1; i != NumElts; ++i)
4450 if (!isUndefOrEqual(Mask[i], i))
4456 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4457 /// as permutations between 128-bit chunks or halves. As an example: this
4459 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4460 /// The first half comes from the second half of V1 and the second half from the
4461 /// the second half of V2.
4462 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4463 if (!HasFp256 || !VT.is256BitVector())
4466 // The shuffle result is divided into half A and half B. In total the two
4467 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4468 // B must come from C, D, E or F.
4469 unsigned HalfSize = VT.getVectorNumElements()/2;
4470 bool MatchA = false, MatchB = false;
4472 // Check if A comes from one of C, D, E, F.
4473 for (unsigned Half = 0; Half != 4; ++Half) {
4474 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4480 // Check if B comes from one of C, D, E, F.
4481 for (unsigned Half = 0; Half != 4; ++Half) {
4482 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4488 return MatchA && MatchB;
4491 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4493 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4494 MVT VT = SVOp->getSimpleValueType(0);
4496 unsigned HalfSize = VT.getVectorNumElements()/2;
4498 unsigned FstHalf = 0, SndHalf = 0;
4499 for (unsigned i = 0; i < HalfSize; ++i) {
4500 if (SVOp->getMaskElt(i) > 0) {
4501 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4505 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4512 return (FstHalf | (SndHalf << 4));
4515 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4516 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4517 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4521 unsigned NumElts = VT.getVectorNumElements();
4523 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4524 for (unsigned i = 0; i != NumElts; ++i) {
4527 Imm8 |= Mask[i] << (i*2);
4532 unsigned LaneSize = 4;
4533 SmallVector<int, 4> MaskVal(LaneSize, -1);
4535 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4536 for (unsigned i = 0; i != LaneSize; ++i) {
4537 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4541 if (MaskVal[i] < 0) {
4542 MaskVal[i] = Mask[i+l] - l;
4543 Imm8 |= MaskVal[i] << (i*2);
4546 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4553 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4554 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4555 /// Note that VPERMIL mask matching is different depending whether theunderlying
4556 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4557 /// to the same elements of the low, but to the higher half of the source.
4558 /// In VPERMILPD the two lanes could be shuffled independently of each other
4559 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4560 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4561 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4562 if (VT.getSizeInBits() < 256 || EltSize < 32)
4564 bool symetricMaskRequired = (EltSize == 32);
4565 unsigned NumElts = VT.getVectorNumElements();
4567 unsigned NumLanes = VT.getSizeInBits()/128;
4568 unsigned LaneSize = NumElts/NumLanes;
4569 // 2 or 4 elements in one lane
4571 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4572 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4573 for (unsigned i = 0; i != LaneSize; ++i) {
4574 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4576 if (symetricMaskRequired) {
4577 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4578 ExpectedMaskVal[i] = Mask[i+l] - l;
4581 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4589 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4590 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4591 /// element of vector 2 and the other elements to come from vector 1 in order.
4592 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4593 bool V2IsSplat = false, bool V2IsUndef = false) {
4594 if (!VT.is128BitVector())
4597 unsigned NumOps = VT.getVectorNumElements();
4598 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4601 if (!isUndefOrEqual(Mask[0], 0))
4604 for (unsigned i = 1; i != NumOps; ++i)
4605 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4606 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4607 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4613 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4614 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4615 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4616 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4617 const X86Subtarget *Subtarget) {
4618 if (!Subtarget->hasSSE3())
4621 unsigned NumElems = VT.getVectorNumElements();
4623 if ((VT.is128BitVector() && NumElems != 4) ||
4624 (VT.is256BitVector() && NumElems != 8) ||
4625 (VT.is512BitVector() && NumElems != 16))
4628 // "i+1" is the value the indexed mask element must have
4629 for (unsigned i = 0; i != NumElems; i += 2)
4630 if (!isUndefOrEqual(Mask[i], i+1) ||
4631 !isUndefOrEqual(Mask[i+1], i+1))
4637 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4639 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4640 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4641 const X86Subtarget *Subtarget) {
4642 if (!Subtarget->hasSSE3())
4645 unsigned NumElems = VT.getVectorNumElements();
4647 if ((VT.is128BitVector() && NumElems != 4) ||
4648 (VT.is256BitVector() && NumElems != 8) ||
4649 (VT.is512BitVector() && NumElems != 16))
4652 // "i" is the value the indexed mask element must have
4653 for (unsigned i = 0; i != NumElems; i += 2)
4654 if (!isUndefOrEqual(Mask[i], i) ||
4655 !isUndefOrEqual(Mask[i+1], i))
4661 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4662 /// specifies a shuffle of elements that is suitable for input to 256-bit
4663 /// version of MOVDDUP.
4664 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4665 if (!HasFp256 || !VT.is256BitVector())
4668 unsigned NumElts = VT.getVectorNumElements();
4672 for (unsigned i = 0; i != NumElts/2; ++i)
4673 if (!isUndefOrEqual(Mask[i], 0))
4675 for (unsigned i = NumElts/2; i != NumElts; ++i)
4676 if (!isUndefOrEqual(Mask[i], NumElts/2))
4681 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4682 /// specifies a shuffle of elements that is suitable for input to 128-bit
4683 /// version of MOVDDUP.
4684 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4685 if (!VT.is128BitVector())
4688 unsigned e = VT.getVectorNumElements() / 2;
4689 for (unsigned i = 0; i != e; ++i)
4690 if (!isUndefOrEqual(Mask[i], i))
4692 for (unsigned i = 0; i != e; ++i)
4693 if (!isUndefOrEqual(Mask[e+i], i))
4698 /// isVEXTRACTIndex - Return true if the specified
4699 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4700 /// suitable for instruction that extract 128 or 256 bit vectors
4701 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4702 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4703 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4706 // The index should be aligned on a vecWidth-bit boundary.
4708 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4710 MVT VT = N->getSimpleValueType(0);
4711 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4712 bool Result = (Index * ElSize) % vecWidth == 0;
4717 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4718 /// operand specifies a subvector insert that is suitable for input to
4719 /// insertion of 128 or 256-bit subvectors
4720 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4721 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4722 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4724 // The index should be aligned on a vecWidth-bit boundary.
4726 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4728 MVT VT = N->getSimpleValueType(0);
4729 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4730 bool Result = (Index * ElSize) % vecWidth == 0;
4735 bool X86::isVINSERT128Index(SDNode *N) {
4736 return isVINSERTIndex(N, 128);
4739 bool X86::isVINSERT256Index(SDNode *N) {
4740 return isVINSERTIndex(N, 256);
4743 bool X86::isVEXTRACT128Index(SDNode *N) {
4744 return isVEXTRACTIndex(N, 128);
4747 bool X86::isVEXTRACT256Index(SDNode *N) {
4748 return isVEXTRACTIndex(N, 256);
4751 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4752 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4753 /// Handles 128-bit and 256-bit.
4754 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4755 MVT VT = N->getSimpleValueType(0);
4757 assert((VT.getSizeInBits() >= 128) &&
4758 "Unsupported vector type for PSHUF/SHUFP");
4760 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4761 // independently on 128-bit lanes.
4762 unsigned NumElts = VT.getVectorNumElements();
4763 unsigned NumLanes = VT.getSizeInBits()/128;
4764 unsigned NumLaneElts = NumElts/NumLanes;
4766 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4767 "Only supports 2, 4 or 8 elements per lane");
4769 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4771 for (unsigned i = 0; i != NumElts; ++i) {
4772 int Elt = N->getMaskElt(i);
4773 if (Elt < 0) continue;
4774 Elt &= NumLaneElts - 1;
4775 unsigned ShAmt = (i << Shift) % 8;
4776 Mask |= Elt << ShAmt;
4782 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4783 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4784 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4785 MVT VT = N->getSimpleValueType(0);
4787 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4788 "Unsupported vector type for PSHUFHW");
4790 unsigned NumElts = VT.getVectorNumElements();
4793 for (unsigned l = 0; l != NumElts; l += 8) {
4794 // 8 nodes per lane, but we only care about the last 4.
4795 for (unsigned i = 0; i < 4; ++i) {
4796 int Elt = N->getMaskElt(l+i+4);
4797 if (Elt < 0) continue;
4798 Elt &= 0x3; // only 2-bits.
4799 Mask |= Elt << (i * 2);
4806 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4807 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4808 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4809 MVT VT = N->getSimpleValueType(0);
4811 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4812 "Unsupported vector type for PSHUFHW");
4814 unsigned NumElts = VT.getVectorNumElements();
4817 for (unsigned l = 0; l != NumElts; l += 8) {
4818 // 8 nodes per lane, but we only care about the first 4.
4819 for (unsigned i = 0; i < 4; ++i) {
4820 int Elt = N->getMaskElt(l+i);
4821 if (Elt < 0) continue;
4822 Elt &= 0x3; // only 2-bits
4823 Mask |= Elt << (i * 2);
4830 /// \brief Return the appropriate immediate to shuffle the specified
4831 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4832 /// VALIGN (if Interlane is true) instructions.
4833 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4835 MVT VT = SVOp->getSimpleValueType(0);
4836 unsigned EltSize = InterLane ? 1 :
4837 VT.getVectorElementType().getSizeInBits() >> 3;
4839 unsigned NumElts = VT.getVectorNumElements();
4840 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4841 unsigned NumLaneElts = NumElts/NumLanes;
4845 for (i = 0; i != NumElts; ++i) {
4846 Val = SVOp->getMaskElt(i);
4850 if (Val >= (int)NumElts)
4851 Val -= NumElts - NumLaneElts;
4853 assert(Val - i > 0 && "PALIGNR imm should be positive");
4854 return (Val - i) * EltSize;
4857 /// \brief Return the appropriate immediate to shuffle the specified
4858 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4859 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4860 return getShuffleAlignrImmediate(SVOp, false);
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4865 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, true);
4870 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4871 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4872 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4873 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4876 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4878 MVT VecVT = N->getOperand(0).getSimpleValueType();
4879 MVT ElVT = VecVT.getVectorElementType();
4881 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4882 return Index / NumElemsPerChunk;
4885 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4886 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4887 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4888 llvm_unreachable("Illegal insert subvector for VINSERT");
4891 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4893 MVT VecVT = N->getSimpleValueType(0);
4894 MVT ElVT = VecVT.getVectorElementType();
4896 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4897 return Index / NumElemsPerChunk;
4900 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4901 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4902 /// and VINSERTI128 instructions.
4903 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4904 return getExtractVEXTRACTImmediate(N, 128);
4907 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4909 /// and VINSERTI64x4 instructions.
4910 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 256);
4914 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4915 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4918 return getInsertVINSERTImmediate(N, 128);
4921 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 256);
4928 /// isZero - Returns true if Elt is a constant integer zero
4929 static bool isZero(SDValue V) {
4930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4931 return C && C->isNullValue();
4934 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4936 bool X86::isZeroNode(SDValue Elt) {
4939 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4940 return CFP->getValueAPF().isPosZero();
4944 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4945 /// match movhlps. The lower half elements should come from upper half of
4946 /// V1 (and in order), and the upper half elements should come from the upper
4947 /// half of V2 (and in order).
4948 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4949 if (!VT.is128BitVector())
4951 if (VT.getVectorNumElements() != 4)
4953 for (unsigned i = 0, e = 2; i != e; ++i)
4954 if (!isUndefOrEqual(Mask[i], i+2))
4956 for (unsigned i = 2; i != 4; ++i)
4957 if (!isUndefOrEqual(Mask[i], i+4))
4962 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4963 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4965 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4966 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4968 N = N->getOperand(0).getNode();
4969 if (!ISD::isNON_EXTLoad(N))
4972 *LD = cast<LoadSDNode>(N);
4976 // Test whether the given value is a vector value which will be legalized
4978 static bool WillBeConstantPoolLoad(SDNode *N) {
4979 if (N->getOpcode() != ISD::BUILD_VECTOR)
4982 // Check for any non-constant elements.
4983 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4984 switch (N->getOperand(i).getNode()->getOpcode()) {
4986 case ISD::ConstantFP:
4993 // Vectors of all-zeros and all-ones are materialized with special
4994 // instructions rather than being loaded.
4995 return !ISD::isBuildVectorAllZeros(N) &&
4996 !ISD::isBuildVectorAllOnes(N);
4999 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5000 /// match movlp{s|d}. The lower half elements should come from lower half of
5001 /// V1 (and in order), and the upper half elements should come from the upper
5002 /// half of V2 (and in order). And since V1 will become the source of the
5003 /// MOVLP, it must be either a vector load or a scalar load to vector.
5004 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5005 ArrayRef<int> Mask, MVT VT) {
5006 if (!VT.is128BitVector())
5009 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5011 // Is V2 is a vector load, don't do this transformation. We will try to use
5012 // load folding shufps op.
5013 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5016 unsigned NumElems = VT.getVectorNumElements();
5018 if (NumElems != 2 && NumElems != 4)
5020 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5021 if (!isUndefOrEqual(Mask[i], i))
5023 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5024 if (!isUndefOrEqual(Mask[i], i+NumElems))
5029 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5030 /// to an zero vector.
5031 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5032 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5033 SDValue V1 = N->getOperand(0);
5034 SDValue V2 = N->getOperand(1);
5035 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5036 for (unsigned i = 0; i != NumElems; ++i) {
5037 int Idx = N->getMaskElt(i);
5038 if (Idx >= (int)NumElems) {
5039 unsigned Opc = V2.getOpcode();
5040 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5042 if (Opc != ISD::BUILD_VECTOR ||
5043 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5045 } else if (Idx >= 0) {
5046 unsigned Opc = V1.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V1.getOperand(Idx)))
5057 /// getZeroVector - Returns a vector of specified type with all zero elements.
5059 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5060 SelectionDAG &DAG, SDLoc dl) {
5061 assert(VT.isVector() && "Expected a vector type");
5063 // Always build SSE zero vectors as <4 x i32> bitcasted
5064 // to their dest type. This ensures they get CSE'd.
5066 if (VT.is128BitVector()) { // SSE
5067 if (Subtarget->hasSSE2()) { // SSE2
5068 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5071 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5074 } else if (VT.is256BitVector()) { // AVX
5075 if (Subtarget->hasInt256()) { // AVX2
5076 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5077 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5080 // 256-bit logic and arithmetic instructions in AVX are all
5081 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5082 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5086 } else if (VT.is512BitVector()) { // AVX-512
5087 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5088 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5089 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5091 } else if (VT.getScalarType() == MVT::i1) {
5092 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5093 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5094 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5095 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5097 llvm_unreachable("Unexpected vector type");
5099 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5102 /// getOnesVector - Returns a vector of specified type with all bits set.
5103 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5104 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5105 /// Then bitcast to their original type, ensuring they get CSE'd.
5106 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5108 assert(VT.isVector() && "Expected a vector type");
5110 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5112 if (VT.is256BitVector()) {
5113 if (HasInt256) { // AVX2
5114 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5115 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5117 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5118 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5120 } else if (VT.is128BitVector()) {
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5123 llvm_unreachable("Unexpected vector type");
5125 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5128 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5129 /// that point to V2 points to its first element.
5130 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5131 for (unsigned i = 0; i != NumElems; ++i) {
5132 if (Mask[i] > (int)NumElems) {
5138 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5139 /// operation of specified width.
5140 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5142 unsigned NumElems = VT.getVectorNumElements();
5143 SmallVector<int, 8> Mask;
5144 Mask.push_back(NumElems);
5145 for (unsigned i = 1; i != NumElems; ++i)
5147 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5150 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5151 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5153 unsigned NumElems = VT.getVectorNumElements();
5154 SmallVector<int, 8> Mask;
5155 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5157 Mask.push_back(i + NumElems);
5159 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5162 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5163 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5165 unsigned NumElems = VT.getVectorNumElements();
5166 SmallVector<int, 8> Mask;
5167 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5168 Mask.push_back(i + Half);
5169 Mask.push_back(i + NumElems + Half);
5171 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5174 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5175 // a generic shuffle instruction because the target has no such instructions.
5176 // Generate shuffles which repeat i16 and i8 several times until they can be
5177 // represented by v4f32 and then be manipulated by target suported shuffles.
5178 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5179 MVT VT = V.getSimpleValueType();
5180 int NumElems = VT.getVectorNumElements();
5183 while (NumElems > 4) {
5184 if (EltNo < NumElems/2) {
5185 V = getUnpackl(DAG, dl, VT, V, V);
5187 V = getUnpackh(DAG, dl, VT, V, V);
5188 EltNo -= NumElems/2;
5195 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5196 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5197 MVT VT = V.getSimpleValueType();
5200 if (VT.is128BitVector()) {
5201 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5202 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5203 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5205 } else if (VT.is256BitVector()) {
5206 // To use VPERMILPS to splat scalars, the second half of indicies must
5207 // refer to the higher part, which is a duplication of the lower one,
5208 // because VPERMILPS can only handle in-lane permutations.
5209 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5210 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5212 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5213 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5216 llvm_unreachable("Vector size not supported");
5218 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5221 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5222 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5223 MVT SrcVT = SV->getSimpleValueType(0);
5224 SDValue V1 = SV->getOperand(0);
5227 int EltNo = SV->getSplatIndex();
5228 int NumElems = SrcVT.getVectorNumElements();
5229 bool Is256BitVec = SrcVT.is256BitVector();
5231 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5232 "Unknown how to promote splat for type");
5234 // Extract the 128-bit part containing the splat element and update
5235 // the splat element index when it refers to the higher register.
5237 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5238 if (EltNo >= NumElems/2)
5239 EltNo -= NumElems/2;
5242 // All i16 and i8 vector types can't be used directly by a generic shuffle
5243 // instruction because the target has no such instruction. Generate shuffles
5244 // which repeat i16 and i8 several times until they fit in i32, and then can
5245 // be manipulated by target suported shuffles.
5246 MVT EltVT = SrcVT.getVectorElementType();
5247 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5248 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5250 // Recreate the 256-bit vector and place the same 128-bit vector
5251 // into the low and high part. This is necessary because we want
5252 // to use VPERM* to shuffle the vectors
5254 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5257 return getLegalSplat(DAG, V1, EltNo);
5260 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5261 /// vector of zero or undef vector. This produces a shuffle where the low
5262 /// element of V2 is swizzled into the zero/undef vector, landing at element
5263 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5264 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5266 const X86Subtarget *Subtarget,
5267 SelectionDAG &DAG) {
5268 MVT VT = V2.getSimpleValueType();
5270 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5271 unsigned NumElems = VT.getVectorNumElements();
5272 SmallVector<int, 16> MaskVec;
5273 for (unsigned i = 0; i != NumElems; ++i)
5274 // If this is the insertion idx, put the low elt of V2 here.
5275 MaskVec.push_back(i == Idx ? NumElems : i);
5276 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5279 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5280 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5281 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5282 /// shuffles which use a single input multiple times, and in those cases it will
5283 /// adjust the mask to only have indices within that single input.
5284 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5285 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5286 unsigned NumElems = VT.getVectorNumElements();
5290 bool IsFakeUnary = false;
5291 switch(N->getOpcode()) {
5292 case X86ISD::BLENDI:
5293 ImmN = N->getOperand(N->getNumOperands()-1);
5294 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5297 ImmN = N->getOperand(N->getNumOperands()-1);
5298 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5299 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5301 case X86ISD::UNPCKH:
5302 DecodeUNPCKHMask(VT, Mask);
5303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5305 case X86ISD::UNPCKL:
5306 DecodeUNPCKLMask(VT, Mask);
5307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5309 case X86ISD::MOVHLPS:
5310 DecodeMOVHLPSMask(NumElems, Mask);
5311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5313 case X86ISD::MOVLHPS:
5314 DecodeMOVLHPSMask(NumElems, Mask);
5315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 case X86ISD::PALIGNR:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5321 case X86ISD::PSHUFD:
5322 case X86ISD::VPERMILPI:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFHW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFLW:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 case X86ISD::PSHUFB: {
5339 SDValue MaskNode = N->getOperand(1);
5340 while (MaskNode->getOpcode() == ISD::BITCAST)
5341 MaskNode = MaskNode->getOperand(0);
5343 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5344 // If we have a build-vector, then things are easy.
5345 EVT VT = MaskNode.getValueType();
5346 assert(VT.isVector() &&
5347 "Can't produce a non-vector with a build_vector!");
5348 if (!VT.isInteger())
5351 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5353 SmallVector<uint64_t, 32> RawMask;
5354 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5355 SDValue Op = MaskNode->getOperand(i);
5356 if (Op->getOpcode() == ISD::UNDEF) {
5357 RawMask.push_back((uint64_t)SM_SentinelUndef);
5360 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5363 APInt MaskElement = CN->getAPIntValue();
5365 // We now have to decode the element which could be any integer size and
5366 // extract each byte of it.
5367 for (int j = 0; j < NumBytesPerElement; ++j) {
5368 // Note that this is x86 and so always little endian: the low byte is
5369 // the first byte of the mask.
5370 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5371 MaskElement = MaskElement.lshr(8);
5374 DecodePSHUFBMask(RawMask, Mask);
5378 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5382 SDValue Ptr = MaskLoad->getBasePtr();
5383 if (Ptr->getOpcode() == X86ISD::Wrapper)
5384 Ptr = Ptr->getOperand(0);
5386 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5387 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5390 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5391 // FIXME: Support AVX-512 here.
5392 Type *Ty = C->getType();
5393 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5394 Ty->getVectorNumElements() != 32))
5397 DecodePSHUFBMask(C, Mask);
5403 case X86ISD::VPERMI:
5404 ImmN = N->getOperand(N->getNumOperands()-1);
5405 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5409 case X86ISD::MOVSD: {
5410 // The index 0 always comes from the first element of the second source,
5411 // this is why MOVSS and MOVSD are used in the first place. The other
5412 // elements come from the other positions of the first source vector
5413 Mask.push_back(NumElems);
5414 for (unsigned i = 1; i != NumElems; ++i) {
5419 case X86ISD::VPERM2X128:
5420 ImmN = N->getOperand(N->getNumOperands()-1);
5421 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5422 if (Mask.empty()) return false;
5424 case X86ISD::MOVSLDUP:
5425 DecodeMOVSLDUPMask(VT, Mask);
5427 case X86ISD::MOVSHDUP:
5428 DecodeMOVSHDUPMask(VT, Mask);
5430 case X86ISD::MOVDDUP:
5431 case X86ISD::MOVLHPD:
5432 case X86ISD::MOVLPD:
5433 case X86ISD::MOVLPS:
5434 // Not yet implemented
5436 default: llvm_unreachable("unknown target shuffle node");
5439 // If we have a fake unary shuffle, the shuffle mask is spread across two
5440 // inputs that are actually the same node. Re-map the mask to always point
5441 // into the first input.
5444 if (M >= (int)Mask.size())
5450 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5451 /// element of the result of the vector shuffle.
5452 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5455 return SDValue(); // Limit search depth.
5457 SDValue V = SDValue(N, 0);
5458 EVT VT = V.getValueType();
5459 unsigned Opcode = V.getOpcode();
5461 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5462 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5463 int Elt = SV->getMaskElt(Index);
5466 return DAG.getUNDEF(VT.getVectorElementType());
5468 unsigned NumElems = VT.getVectorNumElements();
5469 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5470 : SV->getOperand(1);
5471 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5474 // Recurse into target specific vector shuffles to find scalars.
5475 if (isTargetShuffle(Opcode)) {
5476 MVT ShufVT = V.getSimpleValueType();
5477 unsigned NumElems = ShufVT.getVectorNumElements();
5478 SmallVector<int, 16> ShuffleMask;
5481 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5484 int Elt = ShuffleMask[Index];
5486 return DAG.getUNDEF(ShufVT.getVectorElementType());
5488 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5490 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5494 // Actual nodes that may contain scalar elements
5495 if (Opcode == ISD::BITCAST) {
5496 V = V.getOperand(0);
5497 EVT SrcVT = V.getValueType();
5498 unsigned NumElems = VT.getVectorNumElements();
5500 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5504 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5505 return (Index == 0) ? V.getOperand(0)
5506 : DAG.getUNDEF(VT.getVectorElementType());
5508 if (V.getOpcode() == ISD::BUILD_VECTOR)
5509 return V.getOperand(Index);
5514 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5515 /// shuffle operation which come from a consecutively from a zero. The
5516 /// search can start in two different directions, from left or right.
5517 /// We count undefs as zeros until PreferredNum is reached.
5518 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5519 unsigned NumElems, bool ZerosFromLeft,
5521 unsigned PreferredNum = -1U) {
5522 unsigned NumZeros = 0;
5523 for (unsigned i = 0; i != NumElems; ++i) {
5524 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5525 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5529 if (X86::isZeroNode(Elt))
5531 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5532 NumZeros = std::min(NumZeros + 1, PreferredNum);
5540 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5541 /// correspond consecutively to elements from one of the vector operands,
5542 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5544 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5545 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5546 unsigned NumElems, unsigned &OpNum) {
5547 bool SeenV1 = false;
5548 bool SeenV2 = false;
5550 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5551 int Idx = SVOp->getMaskElt(i);
5552 // Ignore undef indicies
5556 if (Idx < (int)NumElems)
5561 // Only accept consecutive elements from the same vector
5562 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5566 OpNum = SeenV1 ? 0 : 1;
5570 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5571 /// logical left shift of a vector.
5572 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5573 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5575 SVOp->getSimpleValueType(0).getVectorNumElements();
5576 unsigned NumZeros = getNumOfConsecutiveZeros(
5577 SVOp, NumElems, false /* check zeros from right */, DAG,
5578 SVOp->getMaskElt(0));
5584 // Considering the elements in the mask that are not consecutive zeros,
5585 // check if they consecutively come from only one of the source vectors.
5587 // V1 = {X, A, B, C} 0
5589 // vector_shuffle V1, V2 <1, 2, 3, X>
5591 if (!isShuffleMaskConsecutive(SVOp,
5592 0, // Mask Start Index
5593 NumElems-NumZeros, // Mask End Index(exclusive)
5594 NumZeros, // Where to start looking in the src vector
5595 NumElems, // Number of elements in vector
5596 OpSrc)) // Which source operand ?
5601 ShVal = SVOp->getOperand(OpSrc);
5605 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5606 /// logical left shift of a vector.
5607 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5608 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5610 SVOp->getSimpleValueType(0).getVectorNumElements();
5611 unsigned NumZeros = getNumOfConsecutiveZeros(
5612 SVOp, NumElems, true /* check zeros from left */, DAG,
5613 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5619 // Considering the elements in the mask that are not consecutive zeros,
5620 // check if they consecutively come from only one of the source vectors.
5622 // 0 { A, B, X, X } = V2
5624 // vector_shuffle V1, V2 <X, X, 4, 5>
5626 if (!isShuffleMaskConsecutive(SVOp,
5627 NumZeros, // Mask Start Index
5628 NumElems, // Mask End Index(exclusive)
5629 0, // Where to start looking in the src vector
5630 NumElems, // Number of elements in vector
5631 OpSrc)) // Which source operand ?
5636 ShVal = SVOp->getOperand(OpSrc);
5640 /// isVectorShift - Returns true if the shuffle can be implemented as a
5641 /// logical left or right shift of a vector.
5642 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5643 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5644 // Although the logic below support any bitwidth size, there are no
5645 // shift instructions which handle more than 128-bit vectors.
5646 if (!SVOp->getSimpleValueType(0).is128BitVector())
5649 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5650 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5656 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5658 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5659 unsigned NumNonZero, unsigned NumZero,
5661 const X86Subtarget* Subtarget,
5662 const TargetLowering &TLI) {
5669 for (unsigned i = 0; i < 16; ++i) {
5670 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5671 if (ThisIsNonZero && First) {
5673 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5675 V = DAG.getUNDEF(MVT::v8i16);
5680 SDValue ThisElt, LastElt;
5681 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5682 if (LastIsNonZero) {
5683 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5684 MVT::i16, Op.getOperand(i-1));
5686 if (ThisIsNonZero) {
5687 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5688 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5689 ThisElt, DAG.getConstant(8, MVT::i8));
5691 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5695 if (ThisElt.getNode())
5696 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5697 DAG.getIntPtrConstant(i/2));
5701 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5704 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5706 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5707 unsigned NumNonZero, unsigned NumZero,
5709 const X86Subtarget* Subtarget,
5710 const TargetLowering &TLI) {
5717 for (unsigned i = 0; i < 8; ++i) {
5718 bool isNonZero = (NonZeros & (1 << i)) != 0;
5722 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5724 V = DAG.getUNDEF(MVT::v8i16);
5727 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5728 MVT::v8i16, V, Op.getOperand(i),
5729 DAG.getIntPtrConstant(i));
5736 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5737 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5738 unsigned NonZeros, unsigned NumNonZero,
5739 unsigned NumZero, SelectionDAG &DAG,
5740 const X86Subtarget *Subtarget,
5741 const TargetLowering &TLI) {
5742 // We know there's at least one non-zero element
5743 unsigned FirstNonZeroIdx = 0;
5744 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5745 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5746 X86::isZeroNode(FirstNonZero)) {
5748 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5751 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5752 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5755 SDValue V = FirstNonZero.getOperand(0);
5756 MVT VVT = V.getSimpleValueType();
5757 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5760 unsigned FirstNonZeroDst =
5761 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5762 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5763 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5764 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5766 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5767 SDValue Elem = Op.getOperand(Idx);
5768 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5771 // TODO: What else can be here? Deal with it.
5772 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5775 // TODO: Some optimizations are still possible here
5776 // ex: Getting one element from a vector, and the rest from another.
5777 if (Elem.getOperand(0) != V)
5780 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5783 else if (IncorrectIdx == -1U) {
5787 // There was already one element with an incorrect index.
5788 // We can't optimize this case to an insertps.
5792 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5794 EVT VT = Op.getSimpleValueType();
5795 unsigned ElementMoveMask = 0;
5796 if (IncorrectIdx == -1U)
5797 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5799 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5801 SDValue InsertpsMask =
5802 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5803 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5809 /// getVShift - Return a vector logical shift node.
5811 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5812 unsigned NumBits, SelectionDAG &DAG,
5813 const TargetLowering &TLI, SDLoc dl) {
5814 assert(VT.is128BitVector() && "Unknown type for VShift");
5815 EVT ShVT = MVT::v2i64;
5816 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5817 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5818 return DAG.getNode(ISD::BITCAST, dl, VT,
5819 DAG.getNode(Opc, dl, ShVT, SrcOp,
5820 DAG.getConstant(NumBits,
5821 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5825 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5827 // Check if the scalar load can be widened into a vector load. And if
5828 // the address is "base + cst" see if the cst can be "absorbed" into
5829 // the shuffle mask.
5830 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5831 SDValue Ptr = LD->getBasePtr();
5832 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5834 EVT PVT = LD->getValueType(0);
5835 if (PVT != MVT::i32 && PVT != MVT::f32)
5840 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5841 FI = FINode->getIndex();
5843 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5844 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5845 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5846 Offset = Ptr.getConstantOperandVal(1);
5847 Ptr = Ptr.getOperand(0);
5852 // FIXME: 256-bit vector instructions don't require a strict alignment,
5853 // improve this code to support it better.
5854 unsigned RequiredAlign = VT.getSizeInBits()/8;
5855 SDValue Chain = LD->getChain();
5856 // Make sure the stack object alignment is at least 16 or 32.
5857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5858 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5859 if (MFI->isFixedObjectIndex(FI)) {
5860 // Can't change the alignment. FIXME: It's possible to compute
5861 // the exact stack offset and reference FI + adjust offset instead.
5862 // If someone *really* cares about this. That's the way to implement it.
5865 MFI->setObjectAlignment(FI, RequiredAlign);
5869 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5870 // Ptr + (Offset & ~15).
5873 if ((Offset % RequiredAlign) & 3)
5875 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5877 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5878 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5880 int EltNo = (Offset - StartOffset) >> 2;
5881 unsigned NumElems = VT.getVectorNumElements();
5883 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5884 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5885 LD->getPointerInfo().getWithOffset(StartOffset),
5886 false, false, false, 0);
5888 SmallVector<int, 8> Mask;
5889 for (unsigned i = 0; i != NumElems; ++i)
5890 Mask.push_back(EltNo);
5892 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5898 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5899 /// vector of type 'VT', see if the elements can be replaced by a single large
5900 /// load which has the same value as a build_vector whose operands are 'elts'.
5902 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5904 /// FIXME: we'd also like to handle the case where the last elements are zero
5905 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5906 /// There's even a handy isZeroNode for that purpose.
5907 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5908 SDLoc &DL, SelectionDAG &DAG,
5909 bool isAfterLegalize) {
5910 EVT EltVT = VT.getVectorElementType();
5911 unsigned NumElems = Elts.size();
5913 LoadSDNode *LDBase = nullptr;
5914 unsigned LastLoadedElt = -1U;
5916 // For each element in the initializer, see if we've found a load or an undef.
5917 // If we don't find an initial load element, or later load elements are
5918 // non-consecutive, bail out.
5919 for (unsigned i = 0; i < NumElems; ++i) {
5920 SDValue Elt = Elts[i];
5922 if (!Elt.getNode() ||
5923 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5926 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5928 LDBase = cast<LoadSDNode>(Elt.getNode());
5932 if (Elt.getOpcode() == ISD::UNDEF)
5935 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5936 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5941 // If we have found an entire vector of loads and undefs, then return a large
5942 // load of the entire vector width starting at the base pointer. If we found
5943 // consecutive loads for the low half, generate a vzext_load node.
5944 if (LastLoadedElt == NumElems - 1) {
5946 if (isAfterLegalize &&
5947 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5950 SDValue NewLd = SDValue();
5952 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5953 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5954 LDBase->getPointerInfo(),
5955 LDBase->isVolatile(), LDBase->isNonTemporal(),
5956 LDBase->isInvariant(), 0);
5957 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5958 LDBase->getPointerInfo(),
5959 LDBase->isVolatile(), LDBase->isNonTemporal(),
5960 LDBase->isInvariant(), LDBase->getAlignment());
5962 if (LDBase->hasAnyUseOfValue(1)) {
5963 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5965 SDValue(NewLd.getNode(), 1));
5966 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5967 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5968 SDValue(NewLd.getNode(), 1));
5973 if (NumElems == 4 && LastLoadedElt == 1 &&
5974 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5975 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5976 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5978 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5979 LDBase->getPointerInfo(),
5980 LDBase->getAlignment(),
5981 false/*isVolatile*/, true/*ReadMem*/,
5984 // Make sure the newly-created LOAD is in the same position as LDBase in
5985 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5986 // update uses of LDBase's output chain to use the TokenFactor.
5987 if (LDBase->hasAnyUseOfValue(1)) {
5988 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5989 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5990 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5991 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5992 SDValue(ResNode.getNode(), 1));
5995 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6000 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6001 /// to generate a splat value for the following cases:
6002 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6003 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6004 /// a scalar load, or a constant.
6005 /// The VBROADCAST node is returned when a pattern is found,
6006 /// or SDValue() otherwise.
6007 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6008 SelectionDAG &DAG) {
6009 // VBROADCAST requires AVX.
6010 // TODO: Splats could be generated for non-AVX CPUs using SSE
6011 // instructions, but there's less potential gain for only 128-bit vectors.
6012 if (!Subtarget->hasAVX())
6015 MVT VT = Op.getSimpleValueType();
6018 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6019 "Unsupported vector type for broadcast.");
6024 switch (Op.getOpcode()) {
6026 // Unknown pattern found.
6029 case ISD::BUILD_VECTOR: {
6030 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6031 BitVector UndefElements;
6032 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6034 // We need a splat of a single value to use broadcast, and it doesn't
6035 // make any sense if the value is only in one element of the vector.
6036 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6040 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6041 Ld.getOpcode() == ISD::ConstantFP);
6043 // Make sure that all of the users of a non-constant load are from the
6044 // BUILD_VECTOR node.
6045 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6050 case ISD::VECTOR_SHUFFLE: {
6051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6053 // Shuffles must have a splat mask where the first element is
6055 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6058 SDValue Sc = Op.getOperand(0);
6059 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6060 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6062 if (!Subtarget->hasInt256())
6065 // Use the register form of the broadcast instruction available on AVX2.
6066 if (VT.getSizeInBits() >= 256)
6067 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6071 Ld = Sc.getOperand(0);
6072 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6073 Ld.getOpcode() == ISD::ConstantFP);
6075 // The scalar_to_vector node and the suspected
6076 // load node must have exactly one user.
6077 // Constants may have multiple users.
6079 // AVX-512 has register version of the broadcast
6080 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6081 Ld.getValueType().getSizeInBits() >= 32;
6082 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6089 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6090 bool IsGE256 = (VT.getSizeInBits() >= 256);
6092 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6093 // instruction to save 8 or more bytes of constant pool data.
6094 // TODO: If multiple splats are generated to load the same constant,
6095 // it may be detrimental to overall size. There needs to be a way to detect
6096 // that condition to know if this is truly a size win.
6097 const Function *F = DAG.getMachineFunction().getFunction();
6098 bool OptForSize = F->getAttributes().
6099 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6101 // Handle broadcasting a single constant scalar from the constant pool
6103 // On Sandybridge (no AVX2), it is still better to load a constant vector
6104 // from the constant pool and not to broadcast it from a scalar.
6105 // But override that restriction when optimizing for size.
6106 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6107 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6108 EVT CVT = Ld.getValueType();
6109 assert(!CVT.isVector() && "Must not broadcast a vector type");
6111 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6112 // For size optimization, also splat v2f64 and v2i64, and for size opt
6113 // with AVX2, also splat i8 and i16.
6114 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6115 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6116 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6117 const Constant *C = nullptr;
6118 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6119 C = CI->getConstantIntValue();
6120 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6121 C = CF->getConstantFPValue();
6123 assert(C && "Invalid constant type");
6125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6126 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6127 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6128 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6129 MachinePointerInfo::getConstantPool(),
6130 false, false, false, Alignment);
6132 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6136 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6138 // Handle AVX2 in-register broadcasts.
6139 if (!IsLoad && Subtarget->hasInt256() &&
6140 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6141 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6143 // The scalar source must be a normal load.
6147 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6148 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6150 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6151 // double since there is no vbroadcastsd xmm
6152 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6153 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6154 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6157 // Unsupported broadcast.
6161 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6162 /// underlying vector and index.
6164 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6166 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6168 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6169 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6172 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6174 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6176 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6177 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6180 // In this case the vector is the extract_subvector expression and the index
6181 // is 2, as specified by the shuffle.
6182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6183 SDValue ShuffleVec = SVOp->getOperand(0);
6184 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6185 assert(ShuffleVecVT.getVectorElementType() ==
6186 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6188 int ShuffleIdx = SVOp->getMaskElt(Idx);
6189 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6190 ExtractedFromVec = ShuffleVec;
6196 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6197 MVT VT = Op.getSimpleValueType();
6199 // Skip if insert_vec_elt is not supported.
6200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6201 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6205 unsigned NumElems = Op.getNumOperands();
6209 SmallVector<unsigned, 4> InsertIndices;
6210 SmallVector<int, 8> Mask(NumElems, -1);
6212 for (unsigned i = 0; i != NumElems; ++i) {
6213 unsigned Opc = Op.getOperand(i).getOpcode();
6215 if (Opc == ISD::UNDEF)
6218 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6219 // Quit if more than 1 elements need inserting.
6220 if (InsertIndices.size() > 1)
6223 InsertIndices.push_back(i);
6227 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6228 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6229 // Quit if non-constant index.
6230 if (!isa<ConstantSDNode>(ExtIdx))
6232 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6234 // Quit if extracted from vector of different type.
6235 if (ExtractedFromVec.getValueType() != VT)
6238 if (!VecIn1.getNode())
6239 VecIn1 = ExtractedFromVec;
6240 else if (VecIn1 != ExtractedFromVec) {
6241 if (!VecIn2.getNode())
6242 VecIn2 = ExtractedFromVec;
6243 else if (VecIn2 != ExtractedFromVec)
6244 // Quit if more than 2 vectors to shuffle
6248 if (ExtractedFromVec == VecIn1)
6250 else if (ExtractedFromVec == VecIn2)
6251 Mask[i] = Idx + NumElems;
6254 if (!VecIn1.getNode())
6257 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6258 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6259 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6260 unsigned Idx = InsertIndices[i];
6261 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6262 DAG.getIntPtrConstant(Idx));
6268 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6270 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6272 MVT VT = Op.getSimpleValueType();
6273 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6274 "Unexpected type in LowerBUILD_VECTORvXi1!");
6277 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6278 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6279 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6280 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6283 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6284 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6285 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6289 bool AllContants = true;
6290 uint64_t Immediate = 0;
6291 int NonConstIdx = -1;
6292 bool IsSplat = true;
6293 unsigned NumNonConsts = 0;
6294 unsigned NumConsts = 0;
6295 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6296 SDValue In = Op.getOperand(idx);
6297 if (In.getOpcode() == ISD::UNDEF)
6299 if (!isa<ConstantSDNode>(In)) {
6300 AllContants = false;
6306 if (cast<ConstantSDNode>(In)->getZExtValue())
6307 Immediate |= (1ULL << idx);
6309 if (In != Op.getOperand(0))
6314 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6315 DAG.getConstant(Immediate, MVT::i16));
6316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6317 DAG.getIntPtrConstant(0));
6320 if (NumNonConsts == 1 && NonConstIdx != 0) {
6323 SDValue VecAsImm = DAG.getConstant(Immediate,
6324 MVT::getIntegerVT(VT.getSizeInBits()));
6325 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6328 DstVec = DAG.getUNDEF(VT);
6329 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6330 Op.getOperand(NonConstIdx),
6331 DAG.getIntPtrConstant(NonConstIdx));
6333 if (!IsSplat && (NonConstIdx != 0))
6334 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6335 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6338 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6339 DAG.getConstant(-1, SelectVT),
6340 DAG.getConstant(0, SelectVT));
6342 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6343 DAG.getConstant((Immediate | 1), SelectVT),
6344 DAG.getConstant(Immediate, SelectVT));
6345 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6348 /// \brief Return true if \p N implements a horizontal binop and return the
6349 /// operands for the horizontal binop into V0 and V1.
6351 /// This is a helper function of PerformBUILD_VECTORCombine.
6352 /// This function checks that the build_vector \p N in input implements a
6353 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6354 /// operation to match.
6355 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6356 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6357 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6360 /// This function only analyzes elements of \p N whose indices are
6361 /// in range [BaseIdx, LastIdx).
6362 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6364 unsigned BaseIdx, unsigned LastIdx,
6365 SDValue &V0, SDValue &V1) {
6366 EVT VT = N->getValueType(0);
6368 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6369 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6370 "Invalid Vector in input!");
6372 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6373 bool CanFold = true;
6374 unsigned ExpectedVExtractIdx = BaseIdx;
6375 unsigned NumElts = LastIdx - BaseIdx;
6376 V0 = DAG.getUNDEF(VT);
6377 V1 = DAG.getUNDEF(VT);
6379 // Check if N implements a horizontal binop.
6380 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6381 SDValue Op = N->getOperand(i + BaseIdx);
6384 if (Op->getOpcode() == ISD::UNDEF) {
6385 // Update the expected vector extract index.
6386 if (i * 2 == NumElts)
6387 ExpectedVExtractIdx = BaseIdx;
6388 ExpectedVExtractIdx += 2;
6392 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6397 SDValue Op0 = Op.getOperand(0);
6398 SDValue Op1 = Op.getOperand(1);
6400 // Try to match the following pattern:
6401 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6402 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6403 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op0.getOperand(0) == Op1.getOperand(0) &&
6405 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6406 isa<ConstantSDNode>(Op1.getOperand(1)));
6410 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6411 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6413 if (i * 2 < NumElts) {
6414 if (V0.getOpcode() == ISD::UNDEF)
6415 V0 = Op0.getOperand(0);
6417 if (V1.getOpcode() == ISD::UNDEF)
6418 V1 = Op0.getOperand(0);
6419 if (i * 2 == NumElts)
6420 ExpectedVExtractIdx = BaseIdx;
6423 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6424 if (I0 == ExpectedVExtractIdx)
6425 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6426 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6427 // Try to match the following dag sequence:
6428 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6429 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6433 ExpectedVExtractIdx += 2;
6439 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6440 /// a concat_vector.
6442 /// This is a helper function of PerformBUILD_VECTORCombine.
6443 /// This function expects two 256-bit vectors called V0 and V1.
6444 /// At first, each vector is split into two separate 128-bit vectors.
6445 /// Then, the resulting 128-bit vectors are used to implement two
6446 /// horizontal binary operations.
6448 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6450 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6451 /// the two new horizontal binop.
6452 /// When Mode is set, the first horizontal binop dag node would take as input
6453 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6454 /// horizontal binop dag node would take as input the lower 128-bit of V1
6455 /// and the upper 128-bit of V1.
6457 /// HADD V0_LO, V0_HI
6458 /// HADD V1_LO, V1_HI
6460 /// Otherwise, the first horizontal binop dag node takes as input the lower
6461 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6462 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6464 /// HADD V0_LO, V1_LO
6465 /// HADD V0_HI, V1_HI
6467 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6468 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6469 /// the upper 128-bits of the result.
6470 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6471 SDLoc DL, SelectionDAG &DAG,
6472 unsigned X86Opcode, bool Mode,
6473 bool isUndefLO, bool isUndefHI) {
6474 EVT VT = V0.getValueType();
6475 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6476 "Invalid nodes in input!");
6478 unsigned NumElts = VT.getVectorNumElements();
6479 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6480 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6481 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6482 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6483 EVT NewVT = V0_LO.getValueType();
6485 SDValue LO = DAG.getUNDEF(NewVT);
6486 SDValue HI = DAG.getUNDEF(NewVT);
6489 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6490 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6491 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6492 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6493 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6495 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6496 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6497 V1_LO->getOpcode() != ISD::UNDEF))
6498 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6500 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6501 V1_HI->getOpcode() != ISD::UNDEF))
6502 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6505 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6508 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6509 /// sequence of 'vadd + vsub + blendi'.
6510 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6511 const X86Subtarget *Subtarget) {
6513 EVT VT = BV->getValueType(0);
6514 unsigned NumElts = VT.getVectorNumElements();
6515 SDValue InVec0 = DAG.getUNDEF(VT);
6516 SDValue InVec1 = DAG.getUNDEF(VT);
6518 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6519 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6521 // Odd-numbered elements in the input build vector are obtained from
6522 // adding two integer/float elements.
6523 // Even-numbered elements in the input build vector are obtained from
6524 // subtracting two integer/float elements.
6525 unsigned ExpectedOpcode = ISD::FSUB;
6526 unsigned NextExpectedOpcode = ISD::FADD;
6527 bool AddFound = false;
6528 bool SubFound = false;
6530 for (unsigned i = 0, e = NumElts; i != e; i++) {
6531 SDValue Op = BV->getOperand(i);
6533 // Skip 'undef' values.
6534 unsigned Opcode = Op.getOpcode();
6535 if (Opcode == ISD::UNDEF) {
6536 std::swap(ExpectedOpcode, NextExpectedOpcode);
6540 // Early exit if we found an unexpected opcode.
6541 if (Opcode != ExpectedOpcode)
6544 SDValue Op0 = Op.getOperand(0);
6545 SDValue Op1 = Op.getOperand(1);
6547 // Try to match the following pattern:
6548 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6549 // Early exit if we cannot match that sequence.
6550 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6551 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6553 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6554 Op0.getOperand(1) != Op1.getOperand(1))
6557 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6561 // We found a valid add/sub node. Update the information accordingly.
6567 // Update InVec0 and InVec1.
6568 if (InVec0.getOpcode() == ISD::UNDEF)
6569 InVec0 = Op0.getOperand(0);
6570 if (InVec1.getOpcode() == ISD::UNDEF)
6571 InVec1 = Op1.getOperand(0);
6573 // Make sure that operands in input to each add/sub node always
6574 // come from a same pair of vectors.
6575 if (InVec0 != Op0.getOperand(0)) {
6576 if (ExpectedOpcode == ISD::FSUB)
6579 // FADD is commutable. Try to commute the operands
6580 // and then test again.
6581 std::swap(Op0, Op1);
6582 if (InVec0 != Op0.getOperand(0))
6586 if (InVec1 != Op1.getOperand(0))
6589 // Update the pair of expected opcodes.
6590 std::swap(ExpectedOpcode, NextExpectedOpcode);
6593 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6594 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6595 InVec1.getOpcode() != ISD::UNDEF)
6596 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6601 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6602 const X86Subtarget *Subtarget) {
6604 EVT VT = N->getValueType(0);
6605 unsigned NumElts = VT.getVectorNumElements();
6606 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6607 SDValue InVec0, InVec1;
6609 // Try to match an ADDSUB.
6610 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6611 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6612 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6613 if (Value.getNode())
6617 // Try to match horizontal ADD/SUB.
6618 unsigned NumUndefsLO = 0;
6619 unsigned NumUndefsHI = 0;
6620 unsigned Half = NumElts/2;
6622 // Count the number of UNDEF operands in the build_vector in input.
6623 for (unsigned i = 0, e = Half; i != e; ++i)
6624 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6627 for (unsigned i = Half, e = NumElts; i != e; ++i)
6628 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6631 // Early exit if this is either a build_vector of all UNDEFs or all the
6632 // operands but one are UNDEF.
6633 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6636 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6637 // Try to match an SSE3 float HADD/HSUB.
6638 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6641 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6642 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6643 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6644 // Try to match an SSSE3 integer HADD/HSUB.
6645 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6646 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6648 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6652 if (!Subtarget->hasAVX())
6655 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6656 // Try to match an AVX horizontal add/sub of packed single/double
6657 // precision floating point values from 256-bit vectors.
6658 SDValue InVec2, InVec3;
6659 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6660 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6661 ((InVec0.getOpcode() == ISD::UNDEF ||
6662 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6663 ((InVec1.getOpcode() == ISD::UNDEF ||
6664 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6665 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6667 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6668 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6669 ((InVec0.getOpcode() == ISD::UNDEF ||
6670 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6671 ((InVec1.getOpcode() == ISD::UNDEF ||
6672 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6673 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6674 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6675 // Try to match an AVX2 horizontal add/sub of signed integers.
6676 SDValue InVec2, InVec3;
6678 bool CanFold = true;
6680 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6681 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6682 ((InVec0.getOpcode() == ISD::UNDEF ||
6683 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6684 ((InVec1.getOpcode() == ISD::UNDEF ||
6685 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6686 X86Opcode = X86ISD::HADD;
6687 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6688 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6689 ((InVec0.getOpcode() == ISD::UNDEF ||
6690 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6691 ((InVec1.getOpcode() == ISD::UNDEF ||
6692 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6693 X86Opcode = X86ISD::HSUB;
6698 // Fold this build_vector into a single horizontal add/sub.
6699 // Do this only if the target has AVX2.
6700 if (Subtarget->hasAVX2())
6701 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6703 // Do not try to expand this build_vector into a pair of horizontal
6704 // add/sub if we can emit a pair of scalar add/sub.
6705 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6708 // Convert this build_vector into a pair of horizontal binop followed by
6710 bool isUndefLO = NumUndefsLO == Half;
6711 bool isUndefHI = NumUndefsHI == Half;
6712 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6713 isUndefLO, isUndefHI);
6717 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6718 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6721 X86Opcode = X86ISD::HADD;
6722 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6723 X86Opcode = X86ISD::HSUB;
6724 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6725 X86Opcode = X86ISD::FHADD;
6726 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6727 X86Opcode = X86ISD::FHSUB;
6731 // Don't try to expand this build_vector into a pair of horizontal add/sub
6732 // if we can simply emit a pair of scalar add/sub.
6733 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6736 // Convert this build_vector into two horizontal add/sub followed by
6738 bool isUndefLO = NumUndefsLO == Half;
6739 bool isUndefHI = NumUndefsHI == Half;
6740 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6741 isUndefLO, isUndefHI);
6748 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6751 MVT VT = Op.getSimpleValueType();
6752 MVT ExtVT = VT.getVectorElementType();
6753 unsigned NumElems = Op.getNumOperands();
6755 // Generate vectors for predicate vectors.
6756 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6757 return LowerBUILD_VECTORvXi1(Op, DAG);
6759 // Vectors containing all zeros can be matched by pxor and xorps later
6760 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6761 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6762 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6763 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6766 return getZeroVector(VT, Subtarget, DAG, dl);
6769 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6770 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6771 // vpcmpeqd on 256-bit vectors.
6772 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6773 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6776 if (!VT.is512BitVector())
6777 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6780 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6781 if (Broadcast.getNode())
6784 unsigned EVTBits = ExtVT.getSizeInBits();
6786 unsigned NumZero = 0;
6787 unsigned NumNonZero = 0;
6788 unsigned NonZeros = 0;
6789 bool IsAllConstants = true;
6790 SmallSet<SDValue, 8> Values;
6791 for (unsigned i = 0; i < NumElems; ++i) {
6792 SDValue Elt = Op.getOperand(i);
6793 if (Elt.getOpcode() == ISD::UNDEF)
6796 if (Elt.getOpcode() != ISD::Constant &&
6797 Elt.getOpcode() != ISD::ConstantFP)
6798 IsAllConstants = false;
6799 if (X86::isZeroNode(Elt))
6802 NonZeros |= (1 << i);
6807 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6808 if (NumNonZero == 0)
6809 return DAG.getUNDEF(VT);
6811 // Special case for single non-zero, non-undef, element.
6812 if (NumNonZero == 1) {
6813 unsigned Idx = countTrailingZeros(NonZeros);
6814 SDValue Item = Op.getOperand(Idx);
6816 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6817 // the value are obviously zero, truncate the value to i32 and do the
6818 // insertion that way. Only do this if the value is non-constant or if the
6819 // value is a constant being inserted into element 0. It is cheaper to do
6820 // a constant pool load than it is to do a movd + shuffle.
6821 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6822 (!IsAllConstants || Idx == 0)) {
6823 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6825 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6826 EVT VecVT = MVT::v4i32;
6827 unsigned VecElts = 4;
6829 // Truncate the value (which may itself be a constant) to i32, and
6830 // convert it to a vector with movd (S2V+shuffle to zero extend).
6831 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6832 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6834 // If using the new shuffle lowering, just directly insert this.
6835 if (ExperimentalVectorShuffleLowering)
6837 ISD::BITCAST, dl, VT,
6838 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6840 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6842 // Now we have our 32-bit value zero extended in the low element of
6843 // a vector. If Idx != 0, swizzle it into place.
6845 SmallVector<int, 4> Mask;
6846 Mask.push_back(Idx);
6847 for (unsigned i = 1; i != VecElts; ++i)
6849 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6852 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6856 // If we have a constant or non-constant insertion into the low element of
6857 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6858 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6859 // depending on what the source datatype is.
6862 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6864 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6865 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6866 if (VT.is256BitVector() || VT.is512BitVector()) {
6867 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6868 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6869 Item, DAG.getIntPtrConstant(0));
6871 assert(VT.is128BitVector() && "Expected an SSE value type!");
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6873 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6874 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6877 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6878 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6879 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6880 if (VT.is256BitVector()) {
6881 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6882 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6884 assert(VT.is128BitVector() && "Expected an SSE value type!");
6885 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6887 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6891 // Is it a vector logical left shift?
6892 if (NumElems == 2 && Idx == 1 &&
6893 X86::isZeroNode(Op.getOperand(0)) &&
6894 !X86::isZeroNode(Op.getOperand(1))) {
6895 unsigned NumBits = VT.getSizeInBits();
6896 return getVShift(true, VT,
6897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6898 VT, Op.getOperand(1)),
6899 NumBits/2, DAG, *this, dl);
6902 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6905 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6906 // is a non-constant being inserted into an element other than the low one,
6907 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6908 // movd/movss) to move this into the low element, then shuffle it into
6910 if (EVTBits == 32) {
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // If using the new shuffle lowering, just directly insert this.
6914 if (ExperimentalVectorShuffleLowering)
6915 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6917 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6918 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6919 SmallVector<int, 8> MaskVec;
6920 for (unsigned i = 0; i != NumElems; ++i)
6921 MaskVec.push_back(i == Idx ? 0 : 1);
6922 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6926 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6927 if (Values.size() == 1) {
6928 if (EVTBits == 32) {
6929 // Instead of a shuffle like this:
6930 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6931 // Check if it's possible to issue this instead.
6932 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6933 unsigned Idx = countTrailingZeros(NonZeros);
6934 SDValue Item = Op.getOperand(Idx);
6935 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6936 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6941 // A vector full of immediates; various special cases are already
6942 // handled, so this is best done with a single constant-pool load.
6946 // For AVX-length vectors, build the individual 128-bit pieces and use
6947 // shuffles to put them in place.
6948 if (VT.is256BitVector() || VT.is512BitVector()) {
6949 SmallVector<SDValue, 64> V;
6950 for (unsigned i = 0; i != NumElems; ++i)
6951 V.push_back(Op.getOperand(i));
6953 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6955 // Build both the lower and upper subvector.
6956 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6957 makeArrayRef(&V[0], NumElems/2));
6958 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6959 makeArrayRef(&V[NumElems / 2], NumElems/2));
6961 // Recreate the wider vector with the lower and upper part.
6962 if (VT.is256BitVector())
6963 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6964 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6967 // Let legalizer expand 2-wide build_vectors.
6968 if (EVTBits == 64) {
6969 if (NumNonZero == 1) {
6970 // One half is zero or undef.
6971 unsigned Idx = countTrailingZeros(NonZeros);
6972 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6973 Op.getOperand(Idx));
6974 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6979 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6980 if (EVTBits == 8 && NumElems == 16) {
6981 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6983 if (V.getNode()) return V;
6986 if (EVTBits == 16 && NumElems == 8) {
6987 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6989 if (V.getNode()) return V;
6992 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6993 if (EVTBits == 32 && NumElems == 4) {
6994 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6995 NumZero, DAG, Subtarget, *this);
7000 // If element VT is == 32 bits, turn it into a number of shuffles.
7001 SmallVector<SDValue, 8> V(NumElems);
7002 if (NumElems == 4 && NumZero > 0) {
7003 for (unsigned i = 0; i < 4; ++i) {
7004 bool isZero = !(NonZeros & (1 << i));
7006 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7008 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7011 for (unsigned i = 0; i < 2; ++i) {
7012 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7015 V[i] = V[i*2]; // Must be a zero vector.
7018 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7021 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7024 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7029 bool Reverse1 = (NonZeros & 0x3) == 2;
7030 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7034 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7035 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7037 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7040 if (Values.size() > 1 && VT.is128BitVector()) {
7041 // Check for a build vector of consecutive loads.
7042 for (unsigned i = 0; i < NumElems; ++i)
7043 V[i] = Op.getOperand(i);
7045 // Check for elements which are consecutive loads.
7046 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7050 // Check for a build vector from mostly shuffle plus few inserting.
7051 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7055 // For SSE 4.1, use insertps to put the high elements into the low element.
7056 if (getSubtarget()->hasSSE41()) {
7058 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7059 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7061 Result = DAG.getUNDEF(VT);
7063 for (unsigned i = 1; i < NumElems; ++i) {
7064 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7065 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7066 Op.getOperand(i), DAG.getIntPtrConstant(i));
7071 // Otherwise, expand into a number of unpckl*, start by extending each of
7072 // our (non-undef) elements to the full vector width with the element in the
7073 // bottom slot of the vector (which generates no code for SSE).
7074 for (unsigned i = 0; i < NumElems; ++i) {
7075 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7076 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7078 V[i] = DAG.getUNDEF(VT);
7081 // Next, we iteratively mix elements, e.g. for v4f32:
7082 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7083 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7084 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7085 unsigned EltStride = NumElems >> 1;
7086 while (EltStride != 0) {
7087 for (unsigned i = 0; i < EltStride; ++i) {
7088 // If V[i+EltStride] is undef and this is the first round of mixing,
7089 // then it is safe to just drop this shuffle: V[i] is already in the
7090 // right place, the one element (since it's the first round) being
7091 // inserted as undef can be dropped. This isn't safe for successive
7092 // rounds because they will permute elements within both vectors.
7093 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7094 EltStride == NumElems/2)
7097 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7106 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7107 // to create 256-bit vectors from two other 128-bit ones.
7108 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7110 MVT ResVT = Op.getSimpleValueType();
7112 assert((ResVT.is256BitVector() ||
7113 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7115 SDValue V1 = Op.getOperand(0);
7116 SDValue V2 = Op.getOperand(1);
7117 unsigned NumElems = ResVT.getVectorNumElements();
7118 if(ResVT.is256BitVector())
7119 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7121 if (Op.getNumOperands() == 4) {
7122 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7123 ResVT.getVectorNumElements()/2);
7124 SDValue V3 = Op.getOperand(2);
7125 SDValue V4 = Op.getOperand(3);
7126 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7127 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7129 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7132 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7133 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7134 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7135 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7136 Op.getNumOperands() == 4)));
7138 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7139 // from two other 128-bit ones.
7141 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7142 return LowerAVXCONCAT_VECTORS(Op, DAG);
7146 //===----------------------------------------------------------------------===//
7147 // Vector shuffle lowering
7149 // This is an experimental code path for lowering vector shuffles on x86. It is
7150 // designed to handle arbitrary vector shuffles and blends, gracefully
7151 // degrading performance as necessary. It works hard to recognize idiomatic
7152 // shuffles and lower them to optimal instruction patterns without leaving
7153 // a framework that allows reasonably efficient handling of all vector shuffle
7155 //===----------------------------------------------------------------------===//
7157 /// \brief Tiny helper function to identify a no-op mask.
7159 /// This is a somewhat boring predicate function. It checks whether the mask
7160 /// array input, which is assumed to be a single-input shuffle mask of the kind
7161 /// used by the X86 shuffle instructions (not a fully general
7162 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7163 /// in-place shuffle are 'no-op's.
7164 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7165 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7166 if (Mask[i] != -1 && Mask[i] != i)
7171 /// \brief Helper function to classify a mask as a single-input mask.
7173 /// This isn't a generic single-input test because in the vector shuffle
7174 /// lowering we canonicalize single inputs to be the first input operand. This
7175 /// means we can more quickly test for a single input by only checking whether
7176 /// an input from the second operand exists. We also assume that the size of
7177 /// mask corresponds to the size of the input vectors which isn't true in the
7178 /// fully general case.
7179 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7181 if (M >= (int)Mask.size())
7186 /// \brief Test whether there are elements crossing 128-bit lanes in this
7189 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7190 /// and we routinely test for these.
7191 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7192 int LaneSize = 128 / VT.getScalarSizeInBits();
7193 int Size = Mask.size();
7194 for (int i = 0; i < Size; ++i)
7195 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7200 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7202 /// This checks a shuffle mask to see if it is performing the same
7203 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7204 /// that it is also not lane-crossing. It may however involve a blend from the
7205 /// same lane of a second vector.
7207 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7208 /// non-trivial to compute in the face of undef lanes. The representation is
7209 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7210 /// entries from both V1 and V2 inputs to the wider mask.
7212 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7213 SmallVectorImpl<int> &RepeatedMask) {
7214 int LaneSize = 128 / VT.getScalarSizeInBits();
7215 RepeatedMask.resize(LaneSize, -1);
7216 int Size = Mask.size();
7217 for (int i = 0; i < Size; ++i) {
7220 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7221 // This entry crosses lanes, so there is no way to model this shuffle.
7224 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7225 if (RepeatedMask[i % LaneSize] == -1)
7226 // This is the first non-undef entry in this slot of a 128-bit lane.
7227 RepeatedMask[i % LaneSize] =
7228 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7229 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7230 // Found a mismatch with the repeated mask.
7236 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7237 // 2013 will allow us to use it as a non-type template parameter.
7240 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7242 /// See its documentation for details.
7243 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7244 if (Mask.size() != Args.size())
7246 for (int i = 0, e = Mask.size(); i < e; ++i) {
7247 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7248 if (Mask[i] != -1 && Mask[i] != *Args[i])
7256 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7259 /// This is a fast way to test a shuffle mask against a fixed pattern:
7261 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7263 /// It returns true if the mask is exactly as wide as the argument list, and
7264 /// each element of the mask is either -1 (signifying undef) or the value given
7265 /// in the argument.
7266 static const VariadicFunction1<
7267 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7269 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7271 /// This helper function produces an 8-bit shuffle immediate corresponding to
7272 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7273 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7276 /// NB: We rely heavily on "undef" masks preserving the input lane.
7277 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7278 SelectionDAG &DAG) {
7279 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7280 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7281 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7282 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7283 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7286 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7287 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7288 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7289 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7290 return DAG.getConstant(Imm, MVT::i8);
7293 /// \brief Try to emit a blend instruction for a shuffle.
7295 /// This doesn't do any checks for the availability of instructions for blending
7296 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7297 /// be matched in the backend with the type given. What it does check for is
7298 /// that the shuffle mask is in fact a blend.
7299 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7300 SDValue V2, ArrayRef<int> Mask,
7301 const X86Subtarget *Subtarget,
7302 SelectionDAG &DAG) {
7304 unsigned BlendMask = 0;
7305 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7306 if (Mask[i] >= Size) {
7307 if (Mask[i] != i + Size)
7308 return SDValue(); // Shuffled V2 input!
7309 BlendMask |= 1u << i;
7312 if (Mask[i] >= 0 && Mask[i] != i)
7313 return SDValue(); // Shuffled V1 input!
7315 switch (VT.SimpleTy) {
7320 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7321 DAG.getConstant(BlendMask, MVT::i8));
7325 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7329 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7330 // that instruction.
7331 if (Subtarget->hasAVX2()) {
7332 // Scale the blend by the number of 32-bit dwords per element.
7333 int Scale = VT.getScalarSizeInBits() / 32;
7335 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7336 if (Mask[i] >= Size)
7337 for (int j = 0; j < Scale; ++j)
7338 BlendMask |= 1u << (i * Scale + j);
7340 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7341 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7342 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7343 return DAG.getNode(ISD::BITCAST, DL, VT,
7344 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7345 DAG.getConstant(BlendMask, MVT::i8)));
7349 // For integer shuffles we need to expand the mask and cast the inputs to
7350 // v8i16s prior to blending.
7351 int Scale = 8 / VT.getVectorNumElements();
7353 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7354 if (Mask[i] >= Size)
7355 for (int j = 0; j < Scale; ++j)
7356 BlendMask |= 1u << (i * Scale + j);
7358 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7359 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7360 return DAG.getNode(ISD::BITCAST, DL, VT,
7361 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7362 DAG.getConstant(BlendMask, MVT::i8)));
7366 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7367 SmallVector<int, 8> RepeatedMask;
7368 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7369 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7370 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7372 for (int i = 0; i < 8; ++i)
7373 if (RepeatedMask[i] >= 16)
7374 BlendMask |= 1u << i;
7375 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7376 DAG.getConstant(BlendMask, MVT::i8));
7381 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7382 SDValue PBLENDVMask[32];
7383 // Scale the blend by the number of bytes per element.
7384 int Scale = VT.getScalarSizeInBits() / 8;
7385 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7386 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7387 for (int j = 0; j < Scale; ++j)
7388 PBLENDVMask[Scale * i + j] =
7389 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7390 : DAG.getConstant(Mask[i] < Size ? 0 : 0x80, MVT::i8);
7392 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7393 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7395 ISD::BITCAST, DL, VT,
7396 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7397 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PBLENDVMask),
7402 llvm_unreachable("Not a supported integer vector type!");
7406 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7407 /// unblended shuffles followed by an unshuffled blend.
7409 /// This matches the extremely common pattern for handling combined
7410 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7412 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7416 SelectionDAG &DAG) {
7417 // Shuffle the input elements into the desired positions in V1 and V2 and
7418 // blend them together.
7419 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7420 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7421 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7422 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7423 if (Mask[i] >= 0 && Mask[i] < Size) {
7424 V1Mask[i] = Mask[i];
7426 } else if (Mask[i] >= Size) {
7427 V2Mask[i] = Mask[i] - Size;
7428 BlendMask[i] = i + Size;
7431 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7432 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7433 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7436 /// \brief Try to lower a vector shuffle as a byte rotation.
7438 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7439 /// byte-rotation of a the concatentation of two vectors. This routine will
7440 /// try to generically lower a vector shuffle through such an instruction. It
7441 /// does not check for the availability of PALIGNR-based lowerings, only the
7442 /// applicability of this strategy to the given mask. This matches shuffle
7443 /// vectors that look like:
7445 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7447 /// Essentially it concatenates V1 and V2, shifts right by some number of
7448 /// elements, and takes the low elements as the result. Note that while this is
7449 /// specified as a *right shift* because x86 is little-endian, it is a *left
7450 /// rotate* of the vector lanes.
7452 /// Note that this only handles 128-bit vector widths currently.
7453 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7456 SelectionDAG &DAG) {
7457 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7459 // We need to detect various ways of spelling a rotation:
7460 // [11, 12, 13, 14, 15, 0, 1, 2]
7461 // [-1, 12, 13, 14, -1, -1, 1, -1]
7462 // [-1, -1, -1, -1, -1, -1, 1, 2]
7463 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7464 // [-1, 4, 5, 6, -1, -1, 9, -1]
7465 // [-1, 4, 5, 6, -1, -1, -1, -1]
7468 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7471 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7473 // Based on the mod-Size value of this mask element determine where
7474 // a rotated vector would have started.
7475 int StartIdx = i - (Mask[i] % Size);
7477 // The identity rotation isn't interesting, stop.
7480 // If we found the tail of a vector the rotation must be the missing
7481 // front. If we found the head of a vector, it must be how much of the head.
7482 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7485 Rotation = CandidateRotation;
7486 else if (Rotation != CandidateRotation)
7487 // The rotations don't match, so we can't match this mask.
7490 // Compute which value this mask is pointing at.
7491 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7493 // Compute which of the two target values this index should be assigned to.
7494 // This reflects whether the high elements are remaining or the low elements
7496 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7498 // Either set up this value if we've not encountered it before, or check
7499 // that it remains consistent.
7502 else if (TargetV != MaskV)
7503 // This may be a rotation, but it pulls from the inputs in some
7504 // unsupported interleaving.
7508 // Check that we successfully analyzed the mask, and normalize the results.
7509 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7510 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7516 // Cast the inputs to v16i8 to match PALIGNR.
7517 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7518 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7520 assert(VT.getSizeInBits() == 128 &&
7521 "Rotate-based lowering only supports 128-bit lowering!");
7522 assert(Mask.size() <= 16 &&
7523 "Can shuffle at most 16 bytes in a 128-bit vector!");
7524 // The actual rotate instruction rotates bytes, so we need to scale the
7525 // rotation based on how many bytes are in the vector.
7526 int Scale = 16 / Mask.size();
7528 return DAG.getNode(ISD::BITCAST, DL, VT,
7529 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7530 DAG.getConstant(Rotation * Scale, MVT::i8)));
7533 /// \brief Compute whether each element of a shuffle is zeroable.
7535 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7536 /// Either it is an undef element in the shuffle mask, the element of the input
7537 /// referenced is undef, or the element of the input referenced is known to be
7538 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7539 /// as many lanes with this technique as possible to simplify the remaining
7541 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7542 SDValue V1, SDValue V2) {
7543 SmallBitVector Zeroable(Mask.size(), false);
7545 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7546 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7548 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7550 // Handle the easy cases.
7551 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7556 // If this is an index into a build_vector node, dig out the input value and
7558 SDValue V = M < Size ? V1 : V2;
7559 if (V.getOpcode() != ISD::BUILD_VECTOR)
7562 SDValue Input = V.getOperand(M % Size);
7563 // The UNDEF opcode check really should be dead code here, but not quite
7564 // worth asserting on (it isn't invalid, just unexpected).
7565 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7572 /// \brief Lower a vector shuffle as a zero or any extension.
7574 /// Given a specific number of elements, element bit width, and extension
7575 /// stride, produce either a zero or any extension based on the available
7576 /// features of the subtarget.
7577 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7578 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7579 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7580 assert(Scale > 1 && "Need a scale to extend.");
7581 int EltBits = VT.getSizeInBits() / NumElements;
7582 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7583 "Only 8, 16, and 32 bit elements can be extended.");
7584 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7586 // Found a valid zext mask! Try various lowering strategies based on the
7587 // input type and available ISA extensions.
7588 if (Subtarget->hasSSE41()) {
7589 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7590 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7591 NumElements / Scale);
7592 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7593 return DAG.getNode(ISD::BITCAST, DL, VT,
7594 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7597 // For any extends we can cheat for larger element sizes and use shuffle
7598 // instructions that can fold with a load and/or copy.
7599 if (AnyExt && EltBits == 32) {
7600 int PSHUFDMask[4] = {0, -1, 1, -1};
7602 ISD::BITCAST, DL, VT,
7603 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7604 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7605 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7607 if (AnyExt && EltBits == 16 && Scale > 2) {
7608 int PSHUFDMask[4] = {0, -1, 0, -1};
7609 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7610 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7611 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7612 int PSHUFHWMask[4] = {1, -1, -1, -1};
7614 ISD::BITCAST, DL, VT,
7615 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7616 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7617 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7620 // If this would require more than 2 unpack instructions to expand, use
7621 // pshufb when available. We can only use more than 2 unpack instructions
7622 // when zero extending i8 elements which also makes it easier to use pshufb.
7623 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7624 assert(NumElements == 16 && "Unexpected byte vector width!");
7625 SDValue PSHUFBMask[16];
7626 for (int i = 0; i < 16; ++i)
7628 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7629 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7630 return DAG.getNode(ISD::BITCAST, DL, VT,
7631 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7632 DAG.getNode(ISD::BUILD_VECTOR, DL,
7633 MVT::v16i8, PSHUFBMask)));
7636 // Otherwise emit a sequence of unpacks.
7638 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7639 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7640 : getZeroVector(InputVT, Subtarget, DAG, DL);
7641 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7642 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7646 } while (Scale > 1);
7647 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7650 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7652 /// This routine will try to do everything in its power to cleverly lower
7653 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7654 /// check for the profitability of this lowering, it tries to aggressively
7655 /// match this pattern. It will use all of the micro-architectural details it
7656 /// can to emit an efficient lowering. It handles both blends with all-zero
7657 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7658 /// masking out later).
7660 /// The reason we have dedicated lowering for zext-style shuffles is that they
7661 /// are both incredibly common and often quite performance sensitive.
7662 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7663 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7664 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7665 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7667 int Bits = VT.getSizeInBits();
7668 int NumElements = Mask.size();
7670 // Define a helper function to check a particular ext-scale and lower to it if
7672 auto Lower = [&](int Scale) -> SDValue {
7675 for (int i = 0; i < NumElements; ++i) {
7677 continue; // Valid anywhere but doesn't tell us anything.
7678 if (i % Scale != 0) {
7679 // Each of the extend elements needs to be zeroable.
7683 // We no lorger are in the anyext case.
7688 // Each of the base elements needs to be consecutive indices into the
7689 // same input vector.
7690 SDValue V = Mask[i] < NumElements ? V1 : V2;
7693 else if (InputV != V)
7694 return SDValue(); // Flip-flopping inputs.
7696 if (Mask[i] % NumElements != i / Scale)
7697 return SDValue(); // Non-consecutive strided elemenst.
7700 // If we fail to find an input, we have a zero-shuffle which should always
7701 // have already been handled.
7702 // FIXME: Maybe handle this here in case during blending we end up with one?
7706 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7707 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7710 // The widest scale possible for extending is to a 64-bit integer.
7711 assert(Bits % 64 == 0 &&
7712 "The number of bits in a vector must be divisible by 64 on x86!");
7713 int NumExtElements = Bits / 64;
7715 // Each iteration, try extending the elements half as much, but into twice as
7717 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7718 assert(NumElements % NumExtElements == 0 &&
7719 "The input vector size must be divisble by the extended size.");
7720 if (SDValue V = Lower(NumElements / NumExtElements))
7724 // No viable ext lowering found.
7728 /// \brief Try to lower insertion of a single element into a zero vector.
7730 /// This is a common pattern that we have especially efficient patterns to lower
7731 /// across all subtarget feature sets.
7732 static SDValue lowerVectorShuffleAsElementInsertion(
7733 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7734 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7735 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7737 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7738 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7740 if (Mask.size() == 2) {
7741 if (!Zeroable[V2Index ^ 1]) {
7742 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7743 // with 2 to flip from {2,3} to {0,1} and vice versa.
7744 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7745 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7746 if (Zeroable[V2Index])
7747 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7753 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7754 if (i != V2Index && !Zeroable[i])
7755 return SDValue(); // Not inserting into a zero vector.
7758 // Step over any bitcasts on either input so we can scan the actual
7759 // BUILD_VECTOR nodes.
7760 while (V1.getOpcode() == ISD::BITCAST)
7761 V1 = V1.getOperand(0);
7762 while (V2.getOpcode() == ISD::BITCAST)
7763 V2 = V2.getOperand(0);
7765 // Check for a single input from a SCALAR_TO_VECTOR node.
7766 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7767 // all the smarts here sunk into that routine. However, the current
7768 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7769 // vector shuffle lowering is dead.
7770 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7771 Mask[V2Index] == (int)Mask.size()) ||
7772 V2.getOpcode() == ISD::BUILD_VECTOR))
7775 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7777 // First, we need to zext the scalar if it is smaller than an i32.
7779 MVT EltVT = VT.getVectorElementType();
7780 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7781 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7782 // Zero-extend directly to i32.
7784 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7787 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7788 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7790 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7793 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7794 // the desired position. Otherwise it is more efficient to do a vector
7795 // shift left. We know that we can do a vector shift left because all
7796 // the inputs are zero.
7797 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7798 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7799 V2Shuffle[V2Index] = 0;
7800 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7802 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7804 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7806 V2Index * EltVT.getSizeInBits(),
7807 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7808 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7814 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7816 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7817 /// support for floating point shuffles but not integer shuffles. These
7818 /// instructions will incur a domain crossing penalty on some chips though so
7819 /// it is better to avoid lowering through this for integer vectors where
7821 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7822 const X86Subtarget *Subtarget,
7823 SelectionDAG &DAG) {
7825 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7826 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7827 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7828 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7829 ArrayRef<int> Mask = SVOp->getMask();
7830 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7832 if (isSingleInputShuffleMask(Mask)) {
7833 // Straight shuffle of a single input vector. Simulate this by using the
7834 // single input as both of the "inputs" to this instruction..
7835 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7837 if (Subtarget->hasAVX()) {
7838 // If we have AVX, we can use VPERMILPS which will allow folding a load
7839 // into the shuffle.
7840 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7841 DAG.getConstant(SHUFPDMask, MVT::i8));
7844 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7845 DAG.getConstant(SHUFPDMask, MVT::i8));
7847 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7848 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7850 // Use dedicated unpack instructions for masks that match their pattern.
7851 if (isShuffleEquivalent(Mask, 0, 2))
7852 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7853 if (isShuffleEquivalent(Mask, 1, 3))
7854 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7856 // If we have a single input, insert that into V1 if we can do so cheaply.
7857 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7858 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7859 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7862 if (Subtarget->hasSSE41())
7863 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7867 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7868 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7869 DAG.getConstant(SHUFPDMask, MVT::i8));
7872 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7874 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7875 /// the integer unit to minimize domain crossing penalties. However, for blends
7876 /// it falls back to the floating point shuffle operation with appropriate bit
7878 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7879 const X86Subtarget *Subtarget,
7880 SelectionDAG &DAG) {
7882 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7883 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7884 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7885 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7886 ArrayRef<int> Mask = SVOp->getMask();
7887 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7889 if (isSingleInputShuffleMask(Mask)) {
7890 // Straight shuffle of a single input vector. For everything from SSE2
7891 // onward this has a single fast instruction with no scary immediates.
7892 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7893 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7894 int WidenedMask[4] = {
7895 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7896 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7898 ISD::BITCAST, DL, MVT::v2i64,
7899 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7900 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7903 // Use dedicated unpack instructions for masks that match their pattern.
7904 if (isShuffleEquivalent(Mask, 0, 2))
7905 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7906 if (isShuffleEquivalent(Mask, 1, 3))
7907 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7909 // If we have a single input from V2 insert that into V1 if we can do so
7911 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7912 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7913 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7916 if (Subtarget->hasSSE41())
7917 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7921 // Try to use rotation instructions if available.
7922 if (Subtarget->hasSSSE3())
7923 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7924 DL, MVT::v2i64, V1, V2, Mask, DAG))
7927 // We implement this with SHUFPD which is pretty lame because it will likely
7928 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7929 // However, all the alternatives are still more cycles and newer chips don't
7930 // have this problem. It would be really nice if x86 had better shuffles here.
7931 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7932 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7933 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7934 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7937 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7939 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7940 /// It makes no assumptions about whether this is the *best* lowering, it simply
7942 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7943 ArrayRef<int> Mask, SDValue V1,
7944 SDValue V2, SelectionDAG &DAG) {
7945 SDValue LowV = V1, HighV = V2;
7946 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7949 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7951 if (NumV2Elements == 1) {
7953 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7956 // Compute the index adjacent to V2Index and in the same half by toggling
7958 int V2AdjIndex = V2Index ^ 1;
7960 if (Mask[V2AdjIndex] == -1) {
7961 // Handles all the cases where we have a single V2 element and an undef.
7962 // This will only ever happen in the high lanes because we commute the
7963 // vector otherwise.
7965 std::swap(LowV, HighV);
7966 NewMask[V2Index] -= 4;
7968 // Handle the case where the V2 element ends up adjacent to a V1 element.
7969 // To make this work, blend them together as the first step.
7970 int V1Index = V2AdjIndex;
7971 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7972 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7973 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7975 // Now proceed to reconstruct the final blend as we have the necessary
7976 // high or low half formed.
7983 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7984 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7986 } else if (NumV2Elements == 2) {
7987 if (Mask[0] < 4 && Mask[1] < 4) {
7988 // Handle the easy case where we have V1 in the low lanes and V2 in the
7992 } else if (Mask[2] < 4 && Mask[3] < 4) {
7993 // We also handle the reversed case because this utility may get called
7994 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7995 // arrange things in the right direction.
8001 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8002 // trying to place elements directly, just blend them and set up the final
8003 // shuffle to place them.
8005 // The first two blend mask elements are for V1, the second two are for
8007 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8008 Mask[2] < 4 ? Mask[2] : Mask[3],
8009 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8010 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8011 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8012 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8014 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8017 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8018 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8019 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8020 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8023 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8024 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8027 /// \brief Lower 4-lane 32-bit floating point shuffles.
8029 /// Uses instructions exclusively from the floating point unit to minimize
8030 /// domain crossing penalties, as these are sufficient to implement all v4f32
8032 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8033 const X86Subtarget *Subtarget,
8034 SelectionDAG &DAG) {
8036 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8037 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8038 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8040 ArrayRef<int> Mask = SVOp->getMask();
8041 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8044 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8046 if (NumV2Elements == 0) {
8047 if (Subtarget->hasAVX()) {
8048 // If we have AVX, we can use VPERMILPS which will allow folding a load
8049 // into the shuffle.
8050 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8051 getV4X86ShuffleImm8ForMask(Mask, DAG));
8054 // Otherwise, use a straight shuffle of a single input vector. We pass the
8055 // input vector to both operands to simulate this with a SHUFPS.
8056 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8057 getV4X86ShuffleImm8ForMask(Mask, DAG));
8060 // Use dedicated unpack instructions for masks that match their pattern.
8061 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8062 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8063 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8064 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8066 // There are special ways we can lower some single-element blends. However, we
8067 // have custom ways we can lower more complex single-element blends below that
8068 // we defer to if both this and BLENDPS fail to match, so restrict this to
8069 // when the V2 input is targeting element 0 of the mask -- that is the fast
8071 if (NumV2Elements == 1 && Mask[0] >= 4)
8072 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8073 Mask, Subtarget, DAG))
8076 if (Subtarget->hasSSE41())
8077 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8081 // Check for whether we can use INSERTPS to perform the blend. We only use
8082 // INSERTPS when the V1 elements are already in the correct locations
8083 // because otherwise we can just always use two SHUFPS instructions which
8084 // are much smaller to encode than a SHUFPS and an INSERTPS.
8085 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8087 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8090 // When using INSERTPS we can zero any lane of the destination. Collect
8091 // the zero inputs into a mask and drop them from the lanes of V1 which
8092 // actually need to be present as inputs to the INSERTPS.
8093 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8095 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8096 bool InsertNeedsShuffle = false;
8098 for (int i = 0; i < 4; ++i)
8102 } else if (Mask[i] != i) {
8103 InsertNeedsShuffle = true;
8108 // We don't want to use INSERTPS or other insertion techniques if it will
8109 // require shuffling anyways.
8110 if (!InsertNeedsShuffle) {
8111 // If all of V1 is zeroable, replace it with undef.
8112 if ((ZMask | 1 << V2Index) == 0xF)
8113 V1 = DAG.getUNDEF(MVT::v4f32);
8115 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8116 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8118 // Insert the V2 element into the desired position.
8119 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8120 DAG.getConstant(InsertPSMask, MVT::i8));
8124 // Otherwise fall back to a SHUFPS lowering strategy.
8125 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8128 /// \brief Lower 4-lane i32 vector shuffles.
8130 /// We try to handle these with integer-domain shuffles where we can, but for
8131 /// blends we use the floating point domain blend instructions.
8132 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8133 const X86Subtarget *Subtarget,
8134 SelectionDAG &DAG) {
8136 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8137 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8138 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8139 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8140 ArrayRef<int> Mask = SVOp->getMask();
8141 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8144 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8146 if (NumV2Elements == 0) {
8147 // Straight shuffle of a single input vector. For everything from SSE2
8148 // onward this has a single fast instruction with no scary immediates.
8149 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8150 // but we aren't actually going to use the UNPCK instruction because doing
8151 // so prevents folding a load into this instruction or making a copy.
8152 const int UnpackLoMask[] = {0, 0, 1, 1};
8153 const int UnpackHiMask[] = {2, 2, 3, 3};
8154 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8155 Mask = UnpackLoMask;
8156 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8157 Mask = UnpackHiMask;
8159 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8160 getV4X86ShuffleImm8ForMask(Mask, DAG));
8163 // Whenever we can lower this as a zext, that instruction is strictly faster
8164 // than any alternative.
8165 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8166 Mask, Subtarget, DAG))
8169 // Use dedicated unpack instructions for masks that match their pattern.
8170 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8171 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8172 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8173 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8175 // There are special ways we can lower some single-element blends.
8176 if (NumV2Elements == 1)
8177 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8178 Mask, Subtarget, DAG))
8181 if (Subtarget->hasSSE41())
8182 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8186 // Try to use rotation instructions if available.
8187 if (Subtarget->hasSSSE3())
8188 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8189 DL, MVT::v4i32, V1, V2, Mask, DAG))
8192 // We implement this with SHUFPS because it can blend from two vectors.
8193 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8194 // up the inputs, bypassing domain shift penalties that we would encur if we
8195 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8197 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8198 DAG.getVectorShuffle(
8200 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8201 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8204 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8205 /// shuffle lowering, and the most complex part.
8207 /// The lowering strategy is to try to form pairs of input lanes which are
8208 /// targeted at the same half of the final vector, and then use a dword shuffle
8209 /// to place them onto the right half, and finally unpack the paired lanes into
8210 /// their final position.
8212 /// The exact breakdown of how to form these dword pairs and align them on the
8213 /// correct sides is really tricky. See the comments within the function for
8214 /// more of the details.
8215 static SDValue lowerV8I16SingleInputVectorShuffle(
8216 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8217 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8218 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8219 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8220 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8222 SmallVector<int, 4> LoInputs;
8223 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8224 [](int M) { return M >= 0; });
8225 std::sort(LoInputs.begin(), LoInputs.end());
8226 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8227 SmallVector<int, 4> HiInputs;
8228 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8229 [](int M) { return M >= 0; });
8230 std::sort(HiInputs.begin(), HiInputs.end());
8231 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8233 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8234 int NumHToL = LoInputs.size() - NumLToL;
8236 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8237 int NumHToH = HiInputs.size() - NumLToH;
8238 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8239 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8240 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8241 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8243 // Use dedicated unpack instructions for masks that match their pattern.
8244 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8245 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8246 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8247 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8249 // Try to use rotation instructions if available.
8250 if (Subtarget->hasSSSE3())
8251 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8252 DL, MVT::v8i16, V, V, Mask, DAG))
8255 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8256 // such inputs we can swap two of the dwords across the half mark and end up
8257 // with <=2 inputs to each half in each half. Once there, we can fall through
8258 // to the generic code below. For example:
8260 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8261 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8263 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8264 // and an existing 2-into-2 on the other half. In this case we may have to
8265 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8266 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8267 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8268 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8269 // half than the one we target for fixing) will be fixed when we re-enter this
8270 // path. We will also combine away any sequence of PSHUFD instructions that
8271 // result into a single instruction. Here is an example of the tricky case:
8273 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8274 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8276 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8278 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8279 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8281 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8282 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8284 // The result is fine to be handled by the generic logic.
8285 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8286 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8287 int AOffset, int BOffset) {
8288 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8289 "Must call this with A having 3 or 1 inputs from the A half.");
8290 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8291 "Must call this with B having 1 or 3 inputs from the B half.");
8292 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8293 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8295 // Compute the index of dword with only one word among the three inputs in
8296 // a half by taking the sum of the half with three inputs and subtracting
8297 // the sum of the actual three inputs. The difference is the remaining
8300 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8301 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8302 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8303 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8304 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8305 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8306 int TripleNonInputIdx =
8307 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8308 TripleDWord = TripleNonInputIdx / 2;
8310 // We use xor with one to compute the adjacent DWord to whichever one the
8312 OneInputDWord = (OneInput / 2) ^ 1;
8314 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8315 // and BToA inputs. If there is also such a problem with the BToB and AToB
8316 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8317 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8318 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8319 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8320 // Compute how many inputs will be flipped by swapping these DWords. We
8322 // to balance this to ensure we don't form a 3-1 shuffle in the other
8324 int NumFlippedAToBInputs =
8325 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8326 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8327 int NumFlippedBToBInputs =
8328 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8329 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8330 if ((NumFlippedAToBInputs == 1 &&
8331 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8332 (NumFlippedBToBInputs == 1 &&
8333 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8334 // We choose whether to fix the A half or B half based on whether that
8335 // half has zero flipped inputs. At zero, we may not be able to fix it
8336 // with that half. We also bias towards fixing the B half because that
8337 // will more commonly be the high half, and we have to bias one way.
8338 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8339 ArrayRef<int> Inputs) {
8340 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8341 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8342 PinnedIdx ^ 1) != Inputs.end();
8343 // Determine whether the free index is in the flipped dword or the
8344 // unflipped dword based on where the pinned index is. We use this bit
8345 // in an xor to conditionally select the adjacent dword.
8346 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8347 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8348 FixFreeIdx) != Inputs.end();
8349 if (IsFixIdxInput == IsFixFreeIdxInput)
8351 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8352 FixFreeIdx) != Inputs.end();
8353 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8354 "We need to be changing the number of flipped inputs!");
8355 int PSHUFHalfMask[] = {0, 1, 2, 3};
8356 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8357 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8359 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8362 if (M != -1 && M == FixIdx)
8364 else if (M != -1 && M == FixFreeIdx)
8367 if (NumFlippedBToBInputs != 0) {
8369 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8370 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8372 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8374 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8375 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8380 int PSHUFDMask[] = {0, 1, 2, 3};
8381 PSHUFDMask[ADWord] = BDWord;
8382 PSHUFDMask[BDWord] = ADWord;
8383 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8384 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8385 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8386 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8388 // Adjust the mask to match the new locations of A and B.
8390 if (M != -1 && M/2 == ADWord)
8391 M = 2 * BDWord + M % 2;
8392 else if (M != -1 && M/2 == BDWord)
8393 M = 2 * ADWord + M % 2;
8395 // Recurse back into this routine to re-compute state now that this isn't
8396 // a 3 and 1 problem.
8397 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8400 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8401 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8402 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8403 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8405 // At this point there are at most two inputs to the low and high halves from
8406 // each half. That means the inputs can always be grouped into dwords and
8407 // those dwords can then be moved to the correct half with a dword shuffle.
8408 // We use at most one low and one high word shuffle to collect these paired
8409 // inputs into dwords, and finally a dword shuffle to place them.
8410 int PSHUFLMask[4] = {-1, -1, -1, -1};
8411 int PSHUFHMask[4] = {-1, -1, -1, -1};
8412 int PSHUFDMask[4] = {-1, -1, -1, -1};
8414 // First fix the masks for all the inputs that are staying in their
8415 // original halves. This will then dictate the targets of the cross-half
8417 auto fixInPlaceInputs =
8418 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8419 MutableArrayRef<int> SourceHalfMask,
8420 MutableArrayRef<int> HalfMask, int HalfOffset) {
8421 if (InPlaceInputs.empty())
8423 if (InPlaceInputs.size() == 1) {
8424 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8425 InPlaceInputs[0] - HalfOffset;
8426 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8429 if (IncomingInputs.empty()) {
8430 // Just fix all of the in place inputs.
8431 for (int Input : InPlaceInputs) {
8432 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8433 PSHUFDMask[Input / 2] = Input / 2;
8438 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8439 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8440 InPlaceInputs[0] - HalfOffset;
8441 // Put the second input next to the first so that they are packed into
8442 // a dword. We find the adjacent index by toggling the low bit.
8443 int AdjIndex = InPlaceInputs[0] ^ 1;
8444 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8445 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8446 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8448 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8449 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8451 // Now gather the cross-half inputs and place them into a free dword of
8452 // their target half.
8453 // FIXME: This operation could almost certainly be simplified dramatically to
8454 // look more like the 3-1 fixing operation.
8455 auto moveInputsToRightHalf = [&PSHUFDMask](
8456 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8457 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8458 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8460 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8461 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8463 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8465 int LowWord = Word & ~1;
8466 int HighWord = Word | 1;
8467 return isWordClobbered(SourceHalfMask, LowWord) ||
8468 isWordClobbered(SourceHalfMask, HighWord);
8471 if (IncomingInputs.empty())
8474 if (ExistingInputs.empty()) {
8475 // Map any dwords with inputs from them into the right half.
8476 for (int Input : IncomingInputs) {
8477 // If the source half mask maps over the inputs, turn those into
8478 // swaps and use the swapped lane.
8479 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8480 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8481 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8482 Input - SourceOffset;
8483 // We have to swap the uses in our half mask in one sweep.
8484 for (int &M : HalfMask)
8485 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8487 else if (M == Input)
8488 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8490 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8491 Input - SourceOffset &&
8492 "Previous placement doesn't match!");
8494 // Note that this correctly re-maps both when we do a swap and when
8495 // we observe the other side of the swap above. We rely on that to
8496 // avoid swapping the members of the input list directly.
8497 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8500 // Map the input's dword into the correct half.
8501 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8502 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8504 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8506 "Previous placement doesn't match!");
8509 // And just directly shift any other-half mask elements to be same-half
8510 // as we will have mirrored the dword containing the element into the
8511 // same position within that half.
8512 for (int &M : HalfMask)
8513 if (M >= SourceOffset && M < SourceOffset + 4) {
8514 M = M - SourceOffset + DestOffset;
8515 assert(M >= 0 && "This should never wrap below zero!");
8520 // Ensure we have the input in a viable dword of its current half. This
8521 // is particularly tricky because the original position may be clobbered
8522 // by inputs being moved and *staying* in that half.
8523 if (IncomingInputs.size() == 1) {
8524 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8525 int InputFixed = std::find(std::begin(SourceHalfMask),
8526 std::end(SourceHalfMask), -1) -
8527 std::begin(SourceHalfMask) + SourceOffset;
8528 SourceHalfMask[InputFixed - SourceOffset] =
8529 IncomingInputs[0] - SourceOffset;
8530 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8532 IncomingInputs[0] = InputFixed;
8534 } else if (IncomingInputs.size() == 2) {
8535 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8536 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8537 // We have two non-adjacent or clobbered inputs we need to extract from
8538 // the source half. To do this, we need to map them into some adjacent
8539 // dword slot in the source mask.
8540 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8541 IncomingInputs[1] - SourceOffset};
8543 // If there is a free slot in the source half mask adjacent to one of
8544 // the inputs, place the other input in it. We use (Index XOR 1) to
8545 // compute an adjacent index.
8546 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8547 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8548 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8549 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8550 InputsFixed[1] = InputsFixed[0] ^ 1;
8551 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8552 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8553 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8554 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8555 InputsFixed[0] = InputsFixed[1] ^ 1;
8556 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8557 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8558 // The two inputs are in the same DWord but it is clobbered and the
8559 // adjacent DWord isn't used at all. Move both inputs to the free
8561 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8562 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8563 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8564 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8566 // The only way we hit this point is if there is no clobbering
8567 // (because there are no off-half inputs to this half) and there is no
8568 // free slot adjacent to one of the inputs. In this case, we have to
8569 // swap an input with a non-input.
8570 for (int i = 0; i < 4; ++i)
8571 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8572 "We can't handle any clobbers here!");
8573 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8574 "Cannot have adjacent inputs here!");
8576 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8577 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8579 // We also have to update the final source mask in this case because
8580 // it may need to undo the above swap.
8581 for (int &M : FinalSourceHalfMask)
8582 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8583 M = InputsFixed[1] + SourceOffset;
8584 else if (M == InputsFixed[1] + SourceOffset)
8585 M = (InputsFixed[0] ^ 1) + SourceOffset;
8587 InputsFixed[1] = InputsFixed[0] ^ 1;
8590 // Point everything at the fixed inputs.
8591 for (int &M : HalfMask)
8592 if (M == IncomingInputs[0])
8593 M = InputsFixed[0] + SourceOffset;
8594 else if (M == IncomingInputs[1])
8595 M = InputsFixed[1] + SourceOffset;
8597 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8598 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8601 llvm_unreachable("Unhandled input size!");
8604 // Now hoist the DWord down to the right half.
8605 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8606 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8607 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8608 for (int &M : HalfMask)
8609 for (int Input : IncomingInputs)
8611 M = FreeDWord * 2 + Input % 2;
8613 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8614 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8615 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8616 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8618 // Now enact all the shuffles we've computed to move the inputs into their
8620 if (!isNoopShuffleMask(PSHUFLMask))
8621 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8622 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8623 if (!isNoopShuffleMask(PSHUFHMask))
8624 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8625 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8626 if (!isNoopShuffleMask(PSHUFDMask))
8627 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8628 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8629 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8630 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8632 // At this point, each half should contain all its inputs, and we can then
8633 // just shuffle them into their final position.
8634 assert(std::count_if(LoMask.begin(), LoMask.end(),
8635 [](int M) { return M >= 4; }) == 0 &&
8636 "Failed to lift all the high half inputs to the low mask!");
8637 assert(std::count_if(HiMask.begin(), HiMask.end(),
8638 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8639 "Failed to lift all the low half inputs to the high mask!");
8641 // Do a half shuffle for the low mask.
8642 if (!isNoopShuffleMask(LoMask))
8643 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8644 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8646 // Do a half shuffle with the high mask after shifting its values down.
8647 for (int &M : HiMask)
8650 if (!isNoopShuffleMask(HiMask))
8651 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8652 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8657 /// \brief Detect whether the mask pattern should be lowered through
8660 /// This essentially tests whether viewing the mask as an interleaving of two
8661 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8662 /// lowering it through interleaving is a significantly better strategy.
8663 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8664 int NumEvenInputs[2] = {0, 0};
8665 int NumOddInputs[2] = {0, 0};
8666 int NumLoInputs[2] = {0, 0};
8667 int NumHiInputs[2] = {0, 0};
8668 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8672 int InputIdx = Mask[i] >= Size;
8675 ++NumLoInputs[InputIdx];
8677 ++NumHiInputs[InputIdx];
8680 ++NumEvenInputs[InputIdx];
8682 ++NumOddInputs[InputIdx];
8685 // The minimum number of cross-input results for both the interleaved and
8686 // split cases. If interleaving results in fewer cross-input results, return
8688 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8689 NumEvenInputs[0] + NumOddInputs[1]);
8690 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8691 NumLoInputs[0] + NumHiInputs[1]);
8692 return InterleavedCrosses < SplitCrosses;
8695 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8697 /// This strategy only works when the inputs from each vector fit into a single
8698 /// half of that vector, and generally there are not so many inputs as to leave
8699 /// the in-place shuffles required highly constrained (and thus expensive). It
8700 /// shifts all the inputs into a single side of both input vectors and then
8701 /// uses an unpack to interleave these inputs in a single vector. At that
8702 /// point, we will fall back on the generic single input shuffle lowering.
8703 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8705 MutableArrayRef<int> Mask,
8706 const X86Subtarget *Subtarget,
8707 SelectionDAG &DAG) {
8708 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8709 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8710 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8711 for (int i = 0; i < 8; ++i)
8712 if (Mask[i] >= 0 && Mask[i] < 4)
8713 LoV1Inputs.push_back(i);
8714 else if (Mask[i] >= 4 && Mask[i] < 8)
8715 HiV1Inputs.push_back(i);
8716 else if (Mask[i] >= 8 && Mask[i] < 12)
8717 LoV2Inputs.push_back(i);
8718 else if (Mask[i] >= 12)
8719 HiV2Inputs.push_back(i);
8721 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8722 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8725 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8726 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8727 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8729 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8730 HiV1Inputs.size() + HiV2Inputs.size();
8732 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8733 ArrayRef<int> HiInputs, bool MoveToLo,
8735 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8736 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8737 if (BadInputs.empty())
8740 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8741 int MoveOffset = MoveToLo ? 0 : 4;
8743 if (GoodInputs.empty()) {
8744 for (int BadInput : BadInputs) {
8745 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8746 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8749 if (GoodInputs.size() == 2) {
8750 // If the low inputs are spread across two dwords, pack them into
8752 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8753 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8754 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8755 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8757 // Otherwise pin the good inputs.
8758 for (int GoodInput : GoodInputs)
8759 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8762 if (BadInputs.size() == 2) {
8763 // If we have two bad inputs then there may be either one or two good
8764 // inputs fixed in place. Find a fixed input, and then find the *other*
8765 // two adjacent indices by using modular arithmetic.
8767 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8768 [](int M) { return M >= 0; }) -
8769 std::begin(MoveMask);
8771 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8772 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8773 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8774 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8775 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8776 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8777 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8779 assert(BadInputs.size() == 1 && "All sizes handled");
8780 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8781 std::end(MoveMask), -1) -
8782 std::begin(MoveMask);
8783 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8784 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8788 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8791 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8793 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8796 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8797 // cross-half traffic in the final shuffle.
8799 // Munge the mask to be a single-input mask after the unpack merges the
8803 M = 2 * (M % 4) + (M / 8);
8805 return DAG.getVectorShuffle(
8806 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8807 DL, MVT::v8i16, V1, V2),
8808 DAG.getUNDEF(MVT::v8i16), Mask);
8811 /// \brief Generic lowering of 8-lane i16 shuffles.
8813 /// This handles both single-input shuffles and combined shuffle/blends with
8814 /// two inputs. The single input shuffles are immediately delegated to
8815 /// a dedicated lowering routine.
8817 /// The blends are lowered in one of three fundamental ways. If there are few
8818 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8819 /// of the input is significantly cheaper when lowered as an interleaving of
8820 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8821 /// halves of the inputs separately (making them have relatively few inputs)
8822 /// and then concatenate them.
8823 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8824 const X86Subtarget *Subtarget,
8825 SelectionDAG &DAG) {
8827 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8828 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8829 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8830 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8831 ArrayRef<int> OrigMask = SVOp->getMask();
8832 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8833 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8834 MutableArrayRef<int> Mask(MaskStorage);
8836 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8838 // Whenever we can lower this as a zext, that instruction is strictly faster
8839 // than any alternative.
8840 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8841 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8844 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8845 auto isV2 = [](int M) { return M >= 8; };
8847 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8848 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8850 if (NumV2Inputs == 0)
8851 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8853 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8854 "to be V1-input shuffles.");
8856 // There are special ways we can lower some single-element blends.
8857 if (NumV2Inputs == 1)
8858 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8859 Mask, Subtarget, DAG))
8862 if (Subtarget->hasSSE41())
8863 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8867 // Try to use rotation instructions if available.
8868 if (Subtarget->hasSSSE3())
8869 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8872 if (NumV1Inputs + NumV2Inputs <= 4)
8873 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8875 // Check whether an interleaving lowering is likely to be more efficient.
8876 // This isn't perfect but it is a strong heuristic that tends to work well on
8877 // the kinds of shuffles that show up in practice.
8879 // FIXME: Handle 1x, 2x, and 4x interleaving.
8880 if (shouldLowerAsInterleaving(Mask)) {
8881 // FIXME: Figure out whether we should pack these into the low or high
8884 int EMask[8], OMask[8];
8885 for (int i = 0; i < 4; ++i) {
8886 EMask[i] = Mask[2*i];
8887 OMask[i] = Mask[2*i + 1];
8892 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8893 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8895 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8898 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8899 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8901 for (int i = 0; i < 4; ++i) {
8902 LoBlendMask[i] = Mask[i];
8903 HiBlendMask[i] = Mask[i + 4];
8906 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8907 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8908 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8909 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8911 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8912 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8915 /// \brief Check whether a compaction lowering can be done by dropping even
8916 /// elements and compute how many times even elements must be dropped.
8918 /// This handles shuffles which take every Nth element where N is a power of
8919 /// two. Example shuffle masks:
8921 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8922 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8923 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8924 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8925 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8926 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8928 /// Any of these lanes can of course be undef.
8930 /// This routine only supports N <= 3.
8931 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8934 /// \returns N above, or the number of times even elements must be dropped if
8935 /// there is such a number. Otherwise returns zero.
8936 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8937 // Figure out whether we're looping over two inputs or just one.
8938 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8940 // The modulus for the shuffle vector entries is based on whether this is
8941 // a single input or not.
8942 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8943 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8944 "We should only be called with masks with a power-of-2 size!");
8946 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8948 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8949 // and 2^3 simultaneously. This is because we may have ambiguity with
8950 // partially undef inputs.
8951 bool ViableForN[3] = {true, true, true};
8953 for (int i = 0, e = Mask.size(); i < e; ++i) {
8954 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8959 bool IsAnyViable = false;
8960 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8961 if (ViableForN[j]) {
8964 // The shuffle mask must be equal to (i * 2^N) % M.
8965 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8968 ViableForN[j] = false;
8970 // Early exit if we exhaust the possible powers of two.
8975 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8979 // Return 0 as there is no viable power of two.
8983 /// \brief Generic lowering of v16i8 shuffles.
8985 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8986 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8987 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8988 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8990 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8991 const X86Subtarget *Subtarget,
8992 SelectionDAG &DAG) {
8994 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8995 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8996 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8998 ArrayRef<int> OrigMask = SVOp->getMask();
8999 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9001 // Try to use rotation instructions if available.
9002 if (Subtarget->hasSSSE3())
9003 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
9007 // Try to use a zext lowering.
9008 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9009 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9012 int MaskStorage[16] = {
9013 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9014 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9015 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9016 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9017 MutableArrayRef<int> Mask(MaskStorage);
9018 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9019 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9022 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9024 // For single-input shuffles, there are some nicer lowering tricks we can use.
9025 if (NumV2Elements == 0) {
9026 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9027 // Notably, this handles splat and partial-splat shuffles more efficiently.
9028 // However, it only makes sense if the pre-duplication shuffle simplifies
9029 // things significantly. Currently, this means we need to be able to
9030 // express the pre-duplication shuffle as an i16 shuffle.
9032 // FIXME: We should check for other patterns which can be widened into an
9033 // i16 shuffle as well.
9034 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9035 for (int i = 0; i < 16; i += 2)
9036 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9041 auto tryToWidenViaDuplication = [&]() -> SDValue {
9042 if (!canWidenViaDuplication(Mask))
9044 SmallVector<int, 4> LoInputs;
9045 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9046 [](int M) { return M >= 0 && M < 8; });
9047 std::sort(LoInputs.begin(), LoInputs.end());
9048 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9050 SmallVector<int, 4> HiInputs;
9051 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9052 [](int M) { return M >= 8; });
9053 std::sort(HiInputs.begin(), HiInputs.end());
9054 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9057 bool TargetLo = LoInputs.size() >= HiInputs.size();
9058 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9059 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9061 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9062 SmallDenseMap<int, int, 8> LaneMap;
9063 for (int I : InPlaceInputs) {
9064 PreDupI16Shuffle[I/2] = I/2;
9067 int j = TargetLo ? 0 : 4, je = j + 4;
9068 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9069 // Check if j is already a shuffle of this input. This happens when
9070 // there are two adjacent bytes after we move the low one.
9071 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9072 // If we haven't yet mapped the input, search for a slot into which
9074 while (j < je && PreDupI16Shuffle[j] != -1)
9078 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9081 // Map this input with the i16 shuffle.
9082 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9085 // Update the lane map based on the mapping we ended up with.
9086 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9089 ISD::BITCAST, DL, MVT::v16i8,
9090 DAG.getVectorShuffle(MVT::v8i16, DL,
9091 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9092 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9094 // Unpack the bytes to form the i16s that will be shuffled into place.
9095 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9096 MVT::v16i8, V1, V1);
9098 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9099 for (int i = 0; i < 16; ++i)
9100 if (Mask[i] != -1) {
9101 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9102 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9103 if (PostDupI16Shuffle[i / 2] == -1)
9104 PostDupI16Shuffle[i / 2] = MappedMask;
9106 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9107 "Conflicting entrties in the original shuffle!");
9110 ISD::BITCAST, DL, MVT::v16i8,
9111 DAG.getVectorShuffle(MVT::v8i16, DL,
9112 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9113 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9115 if (SDValue V = tryToWidenViaDuplication())
9119 // Check whether an interleaving lowering is likely to be more efficient.
9120 // This isn't perfect but it is a strong heuristic that tends to work well on
9121 // the kinds of shuffles that show up in practice.
9123 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9124 if (shouldLowerAsInterleaving(Mask)) {
9125 // FIXME: Figure out whether we should pack these into the low or high
9128 int EMask[16], OMask[16];
9129 for (int i = 0; i < 8; ++i) {
9130 EMask[i] = Mask[2*i];
9131 OMask[i] = Mask[2*i + 1];
9136 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9137 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9139 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9142 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9143 // with PSHUFB. It is important to do this before we attempt to generate any
9144 // blends but after all of the single-input lowerings. If the single input
9145 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9146 // want to preserve that and we can DAG combine any longer sequences into
9147 // a PSHUFB in the end. But once we start blending from multiple inputs,
9148 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9149 // and there are *very* few patterns that would actually be faster than the
9150 // PSHUFB approach because of its ability to zero lanes.
9152 // FIXME: The only exceptions to the above are blends which are exact
9153 // interleavings with direct instructions supporting them. We currently don't
9154 // handle those well here.
9155 if (Subtarget->hasSSSE3()) {
9158 for (int i = 0; i < 16; ++i)
9159 if (Mask[i] == -1) {
9160 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9162 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9164 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9166 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9167 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9168 if (isSingleInputShuffleMask(Mask))
9169 return V1; // Single inputs are easy.
9171 // Otherwise, blend the two.
9172 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9173 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9174 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9177 // There are special ways we can lower some single-element blends.
9178 if (NumV2Elements == 1)
9179 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9180 Mask, Subtarget, DAG))
9183 // Check whether a compaction lowering can be done. This handles shuffles
9184 // which take every Nth element for some even N. See the helper function for
9187 // We special case these as they can be particularly efficiently handled with
9188 // the PACKUSB instruction on x86 and they show up in common patterns of
9189 // rearranging bytes to truncate wide elements.
9190 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9191 // NumEvenDrops is the power of two stride of the elements. Another way of
9192 // thinking about it is that we need to drop the even elements this many
9193 // times to get the original input.
9194 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9196 // First we need to zero all the dropped bytes.
9197 assert(NumEvenDrops <= 3 &&
9198 "No support for dropping even elements more than 3 times.");
9199 // We use the mask type to pick which bytes are preserved based on how many
9200 // elements are dropped.
9201 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9202 SDValue ByteClearMask =
9203 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9204 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9205 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9207 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9209 // Now pack things back together.
9210 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9211 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9212 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9213 for (int i = 1; i < NumEvenDrops; ++i) {
9214 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9215 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9221 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9222 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9223 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9224 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9226 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9227 MutableArrayRef<int> V1HalfBlendMask,
9228 MutableArrayRef<int> V2HalfBlendMask) {
9229 for (int i = 0; i < 8; ++i)
9230 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9231 V1HalfBlendMask[i] = HalfMask[i];
9233 } else if (HalfMask[i] >= 16) {
9234 V2HalfBlendMask[i] = HalfMask[i] - 16;
9235 HalfMask[i] = i + 8;
9238 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9239 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9241 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9243 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9244 MutableArrayRef<int> HiBlendMask) {
9246 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9247 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9249 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9250 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9251 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9252 [](int M) { return M >= 0 && M % 2 == 1; })) {
9253 // Use a mask to drop the high bytes.
9254 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9255 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9256 DAG.getConstant(0x00FF, MVT::v8i16));
9258 // This will be a single vector shuffle instead of a blend so nuke V2.
9259 V2 = DAG.getUNDEF(MVT::v8i16);
9261 // Squash the masks to point directly into V1.
9262 for (int &M : LoBlendMask)
9265 for (int &M : HiBlendMask)
9269 // Otherwise just unpack the low half of V into V1 and the high half into
9270 // V2 so that we can blend them as i16s.
9271 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9272 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9273 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9274 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9277 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9278 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9279 return std::make_pair(BlendedLo, BlendedHi);
9281 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9282 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9283 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9285 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9286 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9288 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9291 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9293 /// This routine breaks down the specific type of 128-bit shuffle and
9294 /// dispatches to the lowering routines accordingly.
9295 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9296 MVT VT, const X86Subtarget *Subtarget,
9297 SelectionDAG &DAG) {
9298 switch (VT.SimpleTy) {
9300 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9302 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9304 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9306 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9308 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9310 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9313 llvm_unreachable("Unimplemented!");
9317 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9320 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9321 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9322 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9323 /// we encode the logic here for specific shuffle lowering routines to bail to
9324 /// when they exhaust the features avaible to more directly handle the shuffle.
9325 static SDValue splitAndLower256BitVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9326 SDValue V2, ArrayRef<int> Mask,
9327 SelectionDAG &DAG) {
9328 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9329 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9330 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9332 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9333 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9335 int NumElements = VT.getVectorNumElements();
9336 int SplitNumElements = NumElements / 2;
9337 MVT ScalarVT = VT.getScalarType();
9338 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9340 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9341 DAG.getIntPtrConstant(0));
9342 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9343 DAG.getIntPtrConstant(SplitNumElements));
9344 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9345 DAG.getIntPtrConstant(0));
9346 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9347 DAG.getIntPtrConstant(SplitNumElements));
9349 // Now create two 4-way blends of these half-width vectors.
9350 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9351 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9352 for (int i = 0; i < SplitNumElements; ++i) {
9353 int M = HalfMask[i];
9354 if (M >= NumElements) {
9355 V2BlendMask.push_back(M - NumElements);
9356 V1BlendMask.push_back(-1);
9357 BlendMask.push_back(SplitNumElements + i);
9358 } else if (M >= 0) {
9359 V2BlendMask.push_back(-1);
9360 V1BlendMask.push_back(M);
9361 BlendMask.push_back(i);
9363 V2BlendMask.push_back(-1);
9364 V1BlendMask.push_back(-1);
9365 BlendMask.push_back(-1);
9368 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9369 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9370 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9372 SDValue Lo = HalfBlend(LoMask);
9373 SDValue Hi = HalfBlend(HiMask);
9374 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9377 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9378 /// a permutation and blend of those lanes.
9380 /// This essentially blends the out-of-lane inputs to each lane into the lane
9381 /// from a permuted copy of the vector. This lowering strategy results in four
9382 /// instructions in the worst case for a single-input cross lane shuffle which
9383 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9384 /// of. Special cases for each particular shuffle pattern should be handled
9385 /// prior to trying this lowering.
9386 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9387 SDValue V1, SDValue V2,
9389 SelectionDAG &DAG) {
9390 // FIXME: This should probably be generalized for 512-bit vectors as well.
9391 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9392 int LaneSize = Mask.size() / 2;
9394 // If there are only inputs from one 128-bit lane, splitting will in fact be
9395 // less expensive. The flags track wether the given lane contains an element
9396 // that crosses to another lane.
9397 bool LaneCrossing[2] = {false, false};
9398 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9399 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9400 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9401 if (!LaneCrossing[0] || !LaneCrossing[1])
9402 return splitAndLower256BitVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9404 if (isSingleInputShuffleMask(Mask)) {
9405 SmallVector<int, 32> FlippedBlendMask;
9406 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9407 FlippedBlendMask.push_back(
9408 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9410 : Mask[i] % LaneSize +
9411 (i / LaneSize) * LaneSize + Size));
9413 // Flip the vector, and blend the results which should now be in-lane. The
9414 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9415 // 5 for the high source. The value 3 selects the high half of source 2 and
9416 // the value 2 selects the low half of source 2. We only use source 2 to
9417 // allow folding it into a memory operand.
9418 unsigned PERMMask = 3 | 2 << 4;
9419 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9420 V1, DAG.getConstant(PERMMask, MVT::i8));
9421 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9424 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9425 // will be handled by the above logic and a blend of the results, much like
9426 // other patterns in AVX.
9427 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9430 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9432 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9433 /// isn't available.
9434 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9435 const X86Subtarget *Subtarget,
9436 SelectionDAG &DAG) {
9438 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9439 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9440 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9441 ArrayRef<int> Mask = SVOp->getMask();
9442 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9444 if (isSingleInputShuffleMask(Mask)) {
9445 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9446 // Non-half-crossing single input shuffles can be lowerid with an
9447 // interleaved permutation.
9448 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9449 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9450 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9451 DAG.getConstant(VPERMILPMask, MVT::i8));
9454 // With AVX2 we have direct support for this permutation.
9455 if (Subtarget->hasAVX2())
9456 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9457 getV4X86ShuffleImm8ForMask(Mask, DAG));
9459 // Otherwise, fall back.
9460 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9464 // X86 has dedicated unpack instructions that can handle specific blend
9465 // operations: UNPCKH and UNPCKL.
9466 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9467 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9468 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9469 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9471 // If we have a single input to the zero element, insert that into V1 if we
9472 // can do so cheaply.
9474 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9475 if (NumV2Elements == 1 && Mask[0] >= 4)
9476 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9477 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9480 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9484 // Check if the blend happens to exactly fit that of SHUFPD.
9485 if ((Mask[0] == -1 || Mask[0] < 2) &&
9486 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9487 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9488 (Mask[3] == -1 || Mask[3] >= 6)) {
9489 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9490 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9491 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9492 DAG.getConstant(SHUFPDMask, MVT::i8));
9494 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9495 (Mask[1] == -1 || Mask[1] < 2) &&
9496 (Mask[2] == -1 || Mask[2] >= 6) &&
9497 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9498 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9499 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9500 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9501 DAG.getConstant(SHUFPDMask, MVT::i8));
9504 // Otherwise fall back on generic blend lowering.
9505 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9509 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9511 /// This routine is only called when we have AVX2 and thus a reasonable
9512 /// instruction set for v4i64 shuffling..
9513 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9514 const X86Subtarget *Subtarget,
9515 SelectionDAG &DAG) {
9517 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9518 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9519 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9520 ArrayRef<int> Mask = SVOp->getMask();
9521 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9522 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9524 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9528 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9529 // use lower latency instructions that will operate on both 128-bit lanes.
9530 SmallVector<int, 2> RepeatedMask;
9531 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9532 if (isSingleInputShuffleMask(Mask)) {
9533 int PSHUFDMask[] = {-1, -1, -1, -1};
9534 for (int i = 0; i < 2; ++i)
9535 if (RepeatedMask[i] >= 0) {
9536 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9537 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9540 ISD::BITCAST, DL, MVT::v4i64,
9541 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9542 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9543 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9546 // Use dedicated unpack instructions for masks that match their pattern.
9547 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9548 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9549 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9550 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9553 // AVX2 provides a direct instruction for permuting a single input across
9555 if (isSingleInputShuffleMask(Mask))
9556 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9557 getV4X86ShuffleImm8ForMask(Mask, DAG));
9559 // Otherwise fall back on generic blend lowering.
9560 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9564 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9566 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9567 /// isn't available.
9568 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9569 const X86Subtarget *Subtarget,
9570 SelectionDAG &DAG) {
9572 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9573 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9574 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9575 ArrayRef<int> Mask = SVOp->getMask();
9576 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9578 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9582 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9583 // options to efficiently lower the shuffle.
9584 SmallVector<int, 4> RepeatedMask;
9585 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9586 assert(RepeatedMask.size() == 4 &&
9587 "Repeated masks must be half the mask width!");
9588 if (isSingleInputShuffleMask(Mask))
9589 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9590 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9592 // Use dedicated unpack instructions for masks that match their pattern.
9593 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9594 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9595 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9596 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9598 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9599 // have already handled any direct blends. We also need to squash the
9600 // repeated mask into a simulated v4f32 mask.
9601 for (int i = 0; i < 4; ++i)
9602 if (RepeatedMask[i] >= 8)
9603 RepeatedMask[i] -= 4;
9604 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9607 // If we have a single input shuffle with different shuffle patterns in the
9608 // two 128-bit lanes use the variable mask to VPERMILPS.
9609 if (isSingleInputShuffleMask(Mask)) {
9610 SDValue VPermMask[8];
9611 for (int i = 0; i < 8; ++i)
9612 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9613 : DAG.getConstant(Mask[i], MVT::i32);
9614 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9616 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9617 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9619 if (Subtarget->hasAVX2())
9620 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9621 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9622 DAG.getNode(ISD::BUILD_VECTOR, DL,
9623 MVT::v8i32, VPermMask)),
9626 // Otherwise, fall back.
9627 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9631 // Otherwise fall back on generic blend lowering.
9632 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9636 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9638 /// This routine is only called when we have AVX2 and thus a reasonable
9639 /// instruction set for v8i32 shuffling..
9640 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9641 const X86Subtarget *Subtarget,
9642 SelectionDAG &DAG) {
9644 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9645 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9646 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9647 ArrayRef<int> Mask = SVOp->getMask();
9648 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9649 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9651 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9655 // If the shuffle mask is repeated in each 128-bit lane we can use more
9656 // efficient instructions that mirror the shuffles across the two 128-bit
9658 SmallVector<int, 4> RepeatedMask;
9659 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9660 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9661 if (isSingleInputShuffleMask(Mask))
9662 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9663 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9665 // Use dedicated unpack instructions for masks that match their pattern.
9666 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9667 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9668 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9669 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9672 // If the shuffle patterns aren't repeated but it is a single input, directly
9673 // generate a cross-lane VPERMD instruction.
9674 if (isSingleInputShuffleMask(Mask)) {
9675 SDValue VPermMask[8];
9676 for (int i = 0; i < 8; ++i)
9677 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9678 : DAG.getConstant(Mask[i], MVT::i32);
9680 X86ISD::VPERMV, DL, MVT::v8i32,
9681 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9684 // Otherwise fall back on generic blend lowering.
9685 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9689 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9691 /// This routine is only called when we have AVX2 and thus a reasonable
9692 /// instruction set for v16i16 shuffling..
9693 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9694 const X86Subtarget *Subtarget,
9695 SelectionDAG &DAG) {
9697 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9698 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9699 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9700 ArrayRef<int> Mask = SVOp->getMask();
9701 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9702 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9704 // There are no generalized cross-lane shuffle operations available on i16
9706 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9707 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9710 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9714 // Use dedicated unpack instructions for masks that match their pattern.
9715 if (isShuffleEquivalent(Mask,
9716 // First 128-bit lane:
9717 0, 16, 1, 17, 2, 18, 3, 19,
9718 // Second 128-bit lane:
9719 8, 24, 9, 25, 10, 26, 11, 27))
9720 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9721 if (isShuffleEquivalent(Mask,
9722 // First 128-bit lane:
9723 4, 20, 5, 21, 6, 22, 7, 23,
9724 // Second 128-bit lane:
9725 12, 28, 13, 29, 14, 30, 15, 31))
9726 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9728 if (isSingleInputShuffleMask(Mask)) {
9729 SDValue PSHUFBMask[32];
9730 for (int i = 0; i < 16; ++i) {
9731 if (Mask[i] == -1) {
9732 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9736 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9737 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9738 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9739 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9742 ISD::BITCAST, DL, MVT::v16i16,
9744 X86ISD::PSHUFB, DL, MVT::v32i8,
9745 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9746 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9749 // Otherwise fall back on generic blend lowering.
9750 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
9754 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9756 /// This routine is only called when we have AVX2 and thus a reasonable
9757 /// instruction set for v32i8 shuffling..
9758 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9759 const X86Subtarget *Subtarget,
9760 SelectionDAG &DAG) {
9762 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9763 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9764 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9765 ArrayRef<int> Mask = SVOp->getMask();
9766 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9767 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9769 // There are no generalized cross-lane shuffle operations available on i8
9771 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9772 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9775 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9779 // Use dedicated unpack instructions for masks that match their pattern.
9780 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9782 if (isShuffleEquivalent(
9784 // First 128-bit lane:
9785 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9786 // Second 128-bit lane:
9787 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
9788 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9789 if (isShuffleEquivalent(
9791 // First 128-bit lane:
9792 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9793 // Second 128-bit lane:
9794 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
9795 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9797 if (isSingleInputShuffleMask(Mask)) {
9798 SDValue PSHUFBMask[32];
9799 for (int i = 0; i < 32; ++i)
9802 ? DAG.getUNDEF(MVT::i8)
9803 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9806 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9807 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9810 // Otherwise fall back on generic blend lowering.
9811 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
9815 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9817 /// This routine either breaks down the specific type of a 256-bit x86 vector
9818 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9819 /// together based on the available instructions.
9820 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9821 MVT VT, const X86Subtarget *Subtarget,
9822 SelectionDAG &DAG) {
9824 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9825 ArrayRef<int> Mask = SVOp->getMask();
9827 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9828 // check for those subtargets here and avoid much of the subtarget querying in
9829 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9830 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9831 // floating point types there eventually, just immediately cast everything to
9832 // a float and operate entirely in that domain.
9833 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9834 int ElementBits = VT.getScalarSizeInBits();
9835 if (ElementBits < 32)
9836 // No floating point type available, decompose into 128-bit vectors.
9837 return splitAndLower256BitVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9839 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9840 VT.getVectorNumElements());
9841 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9842 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9843 return DAG.getNode(ISD::BITCAST, DL, VT,
9844 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9847 switch (VT.SimpleTy) {
9849 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9851 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9853 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9855 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9857 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9859 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9862 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9866 /// \brief Helper function to test whether a shuffle mask could be
9867 /// simplified by widening the elements being shuffled.
9869 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9870 /// leaves it in an unspecified state.
9872 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9873 /// shuffle masks. The latter have the special property of a '-2' representing
9874 /// a zero-ed lane of a vector.
9875 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9876 SmallVectorImpl<int> &WidenedMask) {
9877 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9878 // If both elements are undef, its trivial.
9879 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9880 WidenedMask.push_back(SM_SentinelUndef);
9884 // Check for an undef mask and a mask value properly aligned to fit with
9885 // a pair of values. If we find such a case, use the non-undef mask's value.
9886 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9887 WidenedMask.push_back(Mask[i + 1] / 2);
9890 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9891 WidenedMask.push_back(Mask[i] / 2);
9895 // When zeroing, we need to spread the zeroing across both lanes to widen.
9896 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9897 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9898 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9899 WidenedMask.push_back(SM_SentinelZero);
9905 // Finally check if the two mask values are adjacent and aligned with
9907 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9908 WidenedMask.push_back(Mask[i] / 2);
9912 // Otherwise we can't safely widen the elements used in this shuffle.
9915 assert(WidenedMask.size() == Mask.size() / 2 &&
9916 "Incorrect size of mask after widening the elements!");
9921 /// \brief Top-level lowering for x86 vector shuffles.
9923 /// This handles decomposition, canonicalization, and lowering of all x86
9924 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9925 /// above in helper routines. The canonicalization attempts to widen shuffles
9926 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9927 /// s.t. only one of the two inputs needs to be tested, etc.
9928 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9929 SelectionDAG &DAG) {
9930 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9931 ArrayRef<int> Mask = SVOp->getMask();
9932 SDValue V1 = Op.getOperand(0);
9933 SDValue V2 = Op.getOperand(1);
9934 MVT VT = Op.getSimpleValueType();
9935 int NumElements = VT.getVectorNumElements();
9938 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9940 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9941 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9942 if (V1IsUndef && V2IsUndef)
9943 return DAG.getUNDEF(VT);
9945 // When we create a shuffle node we put the UNDEF node to second operand,
9946 // but in some cases the first operand may be transformed to UNDEF.
9947 // In this case we should just commute the node.
9949 return DAG.getCommutedVectorShuffle(*SVOp);
9951 // Check for non-undef masks pointing at an undef vector and make the masks
9952 // undef as well. This makes it easier to match the shuffle based solely on
9956 if (M >= NumElements) {
9957 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9958 for (int &M : NewMask)
9959 if (M >= NumElements)
9961 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9964 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9965 // lanes but wider integers. We cap this to not form integers larger than i64
9966 // but it might be interesting to form i128 integers to handle flipping the
9967 // low and high halves of AVX 256-bit vectors.
9968 SmallVector<int, 16> WidenedMask;
9969 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9970 canWidenShuffleElements(Mask, WidenedMask)) {
9972 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9973 VT.getVectorNumElements() / 2);
9974 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9975 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9976 return DAG.getNode(ISD::BITCAST, dl, VT,
9977 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
9980 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9981 for (int M : SVOp->getMask())
9984 else if (M < NumElements)
9989 // Commute the shuffle as needed such that more elements come from V1 than
9990 // V2. This allows us to match the shuffle pattern strictly on how many
9991 // elements come from V1 without handling the symmetric cases.
9992 if (NumV2Elements > NumV1Elements)
9993 return DAG.getCommutedVectorShuffle(*SVOp);
9995 // When the number of V1 and V2 elements are the same, try to minimize the
9996 // number of uses of V2 in the low half of the vector. When that is tied,
9997 // ensure that the sum of indices for V1 is equal to or lower than the sum
9999 if (NumV1Elements == NumV2Elements) {
10000 int LowV1Elements = 0, LowV2Elements = 0;
10001 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10002 if (M >= NumElements)
10006 if (LowV2Elements > LowV1Elements) {
10007 return DAG.getCommutedVectorShuffle(*SVOp);
10008 } else if (LowV2Elements == LowV1Elements) {
10009 int SumV1Indices = 0, SumV2Indices = 0;
10010 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10011 if (SVOp->getMask()[i] >= NumElements)
10013 else if (SVOp->getMask()[i] >= 0)
10015 if (SumV2Indices < SumV1Indices)
10016 return DAG.getCommutedVectorShuffle(*SVOp);
10020 // For each vector width, delegate to a specialized lowering routine.
10021 if (VT.getSizeInBits() == 128)
10022 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10024 if (VT.getSizeInBits() == 256)
10025 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10027 llvm_unreachable("Unimplemented!");
10031 //===----------------------------------------------------------------------===//
10032 // Legacy vector shuffle lowering
10034 // This code is the legacy code handling vector shuffles until the above
10035 // replaces its functionality and performance.
10036 //===----------------------------------------------------------------------===//
10038 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10039 bool hasInt256, unsigned *MaskOut = nullptr) {
10040 MVT EltVT = VT.getVectorElementType();
10042 // There is no blend with immediate in AVX-512.
10043 if (VT.is512BitVector())
10046 if (!hasSSE41 || EltVT == MVT::i8)
10048 if (!hasInt256 && VT == MVT::v16i16)
10051 unsigned MaskValue = 0;
10052 unsigned NumElems = VT.getVectorNumElements();
10053 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10054 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10055 unsigned NumElemsInLane = NumElems / NumLanes;
10057 // Blend for v16i16 should be symetric for the both lanes.
10058 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10060 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10061 int EltIdx = MaskVals[i];
10063 if ((EltIdx < 0 || EltIdx == (int)i) &&
10064 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10067 if (((unsigned)EltIdx == (i + NumElems)) &&
10068 (SndLaneEltIdx < 0 ||
10069 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10070 MaskValue |= (1 << i);
10076 *MaskOut = MaskValue;
10080 // Try to lower a shuffle node into a simple blend instruction.
10081 // This function assumes isBlendMask returns true for this
10082 // SuffleVectorSDNode
10083 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10084 unsigned MaskValue,
10085 const X86Subtarget *Subtarget,
10086 SelectionDAG &DAG) {
10087 MVT VT = SVOp->getSimpleValueType(0);
10088 MVT EltVT = VT.getVectorElementType();
10089 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10090 Subtarget->hasInt256() && "Trying to lower a "
10091 "VECTOR_SHUFFLE to a Blend but "
10092 "with the wrong mask"));
10093 SDValue V1 = SVOp->getOperand(0);
10094 SDValue V2 = SVOp->getOperand(1);
10096 unsigned NumElems = VT.getVectorNumElements();
10098 // Convert i32 vectors to floating point if it is not AVX2.
10099 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10101 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10102 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10104 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10105 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10108 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10109 DAG.getConstant(MaskValue, MVT::i32));
10110 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10113 /// In vector type \p VT, return true if the element at index \p InputIdx
10114 /// falls on a different 128-bit lane than \p OutputIdx.
10115 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10116 unsigned OutputIdx) {
10117 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10118 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10121 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10122 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10123 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10124 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10126 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10127 SelectionDAG &DAG) {
10128 MVT VT = V1.getSimpleValueType();
10129 assert(VT.is128BitVector() || VT.is256BitVector());
10131 MVT EltVT = VT.getVectorElementType();
10132 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10133 unsigned NumElts = VT.getVectorNumElements();
10135 SmallVector<SDValue, 32> PshufbMask;
10136 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10137 int InputIdx = MaskVals[OutputIdx];
10138 unsigned InputByteIdx;
10140 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10141 InputByteIdx = 0x80;
10143 // Cross lane is not allowed.
10144 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10146 InputByteIdx = InputIdx * EltSizeInBytes;
10147 // Index is an byte offset within the 128-bit lane.
10148 InputByteIdx &= 0xf;
10151 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10152 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10153 if (InputByteIdx != 0x80)
10158 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10160 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10161 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10162 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10165 // v8i16 shuffles - Prefer shuffles in the following order:
10166 // 1. [all] pshuflw, pshufhw, optional move
10167 // 2. [ssse3] 1 x pshufb
10168 // 3. [ssse3] 2 x pshufb + 1 x por
10169 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10171 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10172 SelectionDAG &DAG) {
10173 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10174 SDValue V1 = SVOp->getOperand(0);
10175 SDValue V2 = SVOp->getOperand(1);
10177 SmallVector<int, 8> MaskVals;
10179 // Determine if more than 1 of the words in each of the low and high quadwords
10180 // of the result come from the same quadword of one of the two inputs. Undef
10181 // mask values count as coming from any quadword, for better codegen.
10183 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10184 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10185 unsigned LoQuad[] = { 0, 0, 0, 0 };
10186 unsigned HiQuad[] = { 0, 0, 0, 0 };
10187 // Indices of quads used.
10188 std::bitset<4> InputQuads;
10189 for (unsigned i = 0; i < 8; ++i) {
10190 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10191 int EltIdx = SVOp->getMaskElt(i);
10192 MaskVals.push_back(EltIdx);
10200 ++Quad[EltIdx / 4];
10201 InputQuads.set(EltIdx / 4);
10204 int BestLoQuad = -1;
10205 unsigned MaxQuad = 1;
10206 for (unsigned i = 0; i < 4; ++i) {
10207 if (LoQuad[i] > MaxQuad) {
10209 MaxQuad = LoQuad[i];
10213 int BestHiQuad = -1;
10215 for (unsigned i = 0; i < 4; ++i) {
10216 if (HiQuad[i] > MaxQuad) {
10218 MaxQuad = HiQuad[i];
10222 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10223 // of the two input vectors, shuffle them into one input vector so only a
10224 // single pshufb instruction is necessary. If there are more than 2 input
10225 // quads, disable the next transformation since it does not help SSSE3.
10226 bool V1Used = InputQuads[0] || InputQuads[1];
10227 bool V2Used = InputQuads[2] || InputQuads[3];
10228 if (Subtarget->hasSSSE3()) {
10229 if (InputQuads.count() == 2 && V1Used && V2Used) {
10230 BestLoQuad = InputQuads[0] ? 0 : 1;
10231 BestHiQuad = InputQuads[2] ? 2 : 3;
10233 if (InputQuads.count() > 2) {
10239 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10240 // the shuffle mask. If a quad is scored as -1, that means that it contains
10241 // words from all 4 input quadwords.
10243 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10245 BestLoQuad < 0 ? 0 : BestLoQuad,
10246 BestHiQuad < 0 ? 1 : BestHiQuad
10248 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10249 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10250 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10251 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10253 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10254 // source words for the shuffle, to aid later transformations.
10255 bool AllWordsInNewV = true;
10256 bool InOrder[2] = { true, true };
10257 for (unsigned i = 0; i != 8; ++i) {
10258 int idx = MaskVals[i];
10260 InOrder[i/4] = false;
10261 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10263 AllWordsInNewV = false;
10267 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10268 if (AllWordsInNewV) {
10269 for (int i = 0; i != 8; ++i) {
10270 int idx = MaskVals[i];
10273 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10274 if ((idx != i) && idx < 4)
10276 if ((idx != i) && idx > 3)
10285 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10286 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10287 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10288 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10289 unsigned TargetMask = 0;
10290 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10291 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10292 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10293 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10294 getShufflePSHUFLWImmediate(SVOp);
10295 V1 = NewV.getOperand(0);
10296 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10300 // Promote splats to a larger type which usually leads to more efficient code.
10301 // FIXME: Is this true if pshufb is available?
10302 if (SVOp->isSplat())
10303 return PromoteSplat(SVOp, DAG);
10305 // If we have SSSE3, and all words of the result are from 1 input vector,
10306 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10307 // is present, fall back to case 4.
10308 if (Subtarget->hasSSSE3()) {
10309 SmallVector<SDValue,16> pshufbMask;
10311 // If we have elements from both input vectors, set the high bit of the
10312 // shuffle mask element to zero out elements that come from V2 in the V1
10313 // mask, and elements that come from V1 in the V2 mask, so that the two
10314 // results can be OR'd together.
10315 bool TwoInputs = V1Used && V2Used;
10316 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10318 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10320 // Calculate the shuffle mask for the second input, shuffle it, and
10321 // OR it with the first shuffled input.
10322 CommuteVectorShuffleMask(MaskVals, 8);
10323 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10324 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10325 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10328 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10329 // and update MaskVals with new element order.
10330 std::bitset<8> InOrder;
10331 if (BestLoQuad >= 0) {
10332 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10333 for (int i = 0; i != 4; ++i) {
10334 int idx = MaskVals[i];
10337 } else if ((idx / 4) == BestLoQuad) {
10338 MaskV[i] = idx & 3;
10342 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10345 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10346 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10347 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10348 NewV.getOperand(0),
10349 getShufflePSHUFLWImmediate(SVOp), DAG);
10353 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10354 // and update MaskVals with the new element order.
10355 if (BestHiQuad >= 0) {
10356 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10357 for (unsigned i = 4; i != 8; ++i) {
10358 int idx = MaskVals[i];
10361 } else if ((idx / 4) == BestHiQuad) {
10362 MaskV[i] = (idx & 3) + 4;
10366 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10369 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10371 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10372 NewV.getOperand(0),
10373 getShufflePSHUFHWImmediate(SVOp), DAG);
10377 // In case BestHi & BestLo were both -1, which means each quadword has a word
10378 // from each of the four input quadwords, calculate the InOrder bitvector now
10379 // before falling through to the insert/extract cleanup.
10380 if (BestLoQuad == -1 && BestHiQuad == -1) {
10382 for (int i = 0; i != 8; ++i)
10383 if (MaskVals[i] < 0 || MaskVals[i] == i)
10387 // The other elements are put in the right place using pextrw and pinsrw.
10388 for (unsigned i = 0; i != 8; ++i) {
10391 int EltIdx = MaskVals[i];
10394 SDValue ExtOp = (EltIdx < 8) ?
10395 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10396 DAG.getIntPtrConstant(EltIdx)) :
10397 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10398 DAG.getIntPtrConstant(EltIdx - 8));
10399 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10400 DAG.getIntPtrConstant(i));
10405 /// \brief v16i16 shuffles
10407 /// FIXME: We only support generation of a single pshufb currently. We can
10408 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10409 /// well (e.g 2 x pshufb + 1 x por).
10411 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10412 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10413 SDValue V1 = SVOp->getOperand(0);
10414 SDValue V2 = SVOp->getOperand(1);
10417 if (V2.getOpcode() != ISD::UNDEF)
10420 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10421 return getPSHUFB(MaskVals, V1, dl, DAG);
10424 // v16i8 shuffles - Prefer shuffles in the following order:
10425 // 1. [ssse3] 1 x pshufb
10426 // 2. [ssse3] 2 x pshufb + 1 x por
10427 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10428 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10429 const X86Subtarget* Subtarget,
10430 SelectionDAG &DAG) {
10431 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10432 SDValue V1 = SVOp->getOperand(0);
10433 SDValue V2 = SVOp->getOperand(1);
10435 ArrayRef<int> MaskVals = SVOp->getMask();
10437 // Promote splats to a larger type which usually leads to more efficient code.
10438 // FIXME: Is this true if pshufb is available?
10439 if (SVOp->isSplat())
10440 return PromoteSplat(SVOp, DAG);
10442 // If we have SSSE3, case 1 is generated when all result bytes come from
10443 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10444 // present, fall back to case 3.
10446 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10447 if (Subtarget->hasSSSE3()) {
10448 SmallVector<SDValue,16> pshufbMask;
10450 // If all result elements are from one input vector, then only translate
10451 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10453 // Otherwise, we have elements from both input vectors, and must zero out
10454 // elements that come from V2 in the first mask, and V1 in the second mask
10455 // so that we can OR them together.
10456 for (unsigned i = 0; i != 16; ++i) {
10457 int EltIdx = MaskVals[i];
10458 if (EltIdx < 0 || EltIdx >= 16)
10460 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10462 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10463 DAG.getNode(ISD::BUILD_VECTOR, dl,
10464 MVT::v16i8, pshufbMask));
10466 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10467 // the 2nd operand if it's undefined or zero.
10468 if (V2.getOpcode() == ISD::UNDEF ||
10469 ISD::isBuildVectorAllZeros(V2.getNode()))
10472 // Calculate the shuffle mask for the second input, shuffle it, and
10473 // OR it with the first shuffled input.
10474 pshufbMask.clear();
10475 for (unsigned i = 0; i != 16; ++i) {
10476 int EltIdx = MaskVals[i];
10477 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10478 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10480 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10481 DAG.getNode(ISD::BUILD_VECTOR, dl,
10482 MVT::v16i8, pshufbMask));
10483 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10486 // No SSSE3 - Calculate in place words and then fix all out of place words
10487 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10488 // the 16 different words that comprise the two doublequadword input vectors.
10489 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10490 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10492 for (int i = 0; i != 8; ++i) {
10493 int Elt0 = MaskVals[i*2];
10494 int Elt1 = MaskVals[i*2+1];
10496 // This word of the result is all undef, skip it.
10497 if (Elt0 < 0 && Elt1 < 0)
10500 // This word of the result is already in the correct place, skip it.
10501 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10504 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10505 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10508 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10509 // using a single extract together, load it and store it.
10510 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10511 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10512 DAG.getIntPtrConstant(Elt1 / 2));
10513 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10514 DAG.getIntPtrConstant(i));
10518 // If Elt1 is defined, extract it from the appropriate source. If the
10519 // source byte is not also odd, shift the extracted word left 8 bits
10520 // otherwise clear the bottom 8 bits if we need to do an or.
10522 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10523 DAG.getIntPtrConstant(Elt1 / 2));
10524 if ((Elt1 & 1) == 0)
10525 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10527 TLI.getShiftAmountTy(InsElt.getValueType())));
10528 else if (Elt0 >= 0)
10529 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10530 DAG.getConstant(0xFF00, MVT::i16));
10532 // If Elt0 is defined, extract it from the appropriate source. If the
10533 // source byte is not also even, shift the extracted word right 8 bits. If
10534 // Elt1 was also defined, OR the extracted values together before
10535 // inserting them in the result.
10537 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10538 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10539 if ((Elt0 & 1) != 0)
10540 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10542 TLI.getShiftAmountTy(InsElt0.getValueType())));
10543 else if (Elt1 >= 0)
10544 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10545 DAG.getConstant(0x00FF, MVT::i16));
10546 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10549 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10550 DAG.getIntPtrConstant(i));
10552 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10555 // v32i8 shuffles - Translate to VPSHUFB if possible.
10557 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10558 const X86Subtarget *Subtarget,
10559 SelectionDAG &DAG) {
10560 MVT VT = SVOp->getSimpleValueType(0);
10561 SDValue V1 = SVOp->getOperand(0);
10562 SDValue V2 = SVOp->getOperand(1);
10564 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10566 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10567 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10568 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10570 // VPSHUFB may be generated if
10571 // (1) one of input vector is undefined or zeroinitializer.
10572 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10573 // And (2) the mask indexes don't cross the 128-bit lane.
10574 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10575 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10578 if (V1IsAllZero && !V2IsAllZero) {
10579 CommuteVectorShuffleMask(MaskVals, 32);
10582 return getPSHUFB(MaskVals, V1, dl, DAG);
10585 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10586 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10587 /// done when every pair / quad of shuffle mask elements point to elements in
10588 /// the right sequence. e.g.
10589 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10591 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10592 SelectionDAG &DAG) {
10593 MVT VT = SVOp->getSimpleValueType(0);
10595 unsigned NumElems = VT.getVectorNumElements();
10598 switch (VT.SimpleTy) {
10599 default: llvm_unreachable("Unexpected!");
10602 return SDValue(SVOp, 0);
10603 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10604 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10605 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10606 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10607 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10608 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10611 SmallVector<int, 8> MaskVec;
10612 for (unsigned i = 0; i != NumElems; i += Scale) {
10614 for (unsigned j = 0; j != Scale; ++j) {
10615 int EltIdx = SVOp->getMaskElt(i+j);
10619 StartIdx = (EltIdx / Scale);
10620 if (EltIdx != (int)(StartIdx*Scale + j))
10623 MaskVec.push_back(StartIdx);
10626 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10627 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10628 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10631 /// getVZextMovL - Return a zero-extending vector move low node.
10633 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10634 SDValue SrcOp, SelectionDAG &DAG,
10635 const X86Subtarget *Subtarget, SDLoc dl) {
10636 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10637 LoadSDNode *LD = nullptr;
10638 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10639 LD = dyn_cast<LoadSDNode>(SrcOp);
10641 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10643 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10644 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10645 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10646 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10647 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10649 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10650 return DAG.getNode(ISD::BITCAST, dl, VT,
10651 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10652 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10654 SrcOp.getOperand(0)
10660 return DAG.getNode(ISD::BITCAST, dl, VT,
10661 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10662 DAG.getNode(ISD::BITCAST, dl,
10666 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10667 /// which could not be matched by any known target speficic shuffle
10669 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10671 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10672 if (NewOp.getNode())
10675 MVT VT = SVOp->getSimpleValueType(0);
10677 unsigned NumElems = VT.getVectorNumElements();
10678 unsigned NumLaneElems = NumElems / 2;
10681 MVT EltVT = VT.getVectorElementType();
10682 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10685 SmallVector<int, 16> Mask;
10686 for (unsigned l = 0; l < 2; ++l) {
10687 // Build a shuffle mask for the output, discovering on the fly which
10688 // input vectors to use as shuffle operands (recorded in InputUsed).
10689 // If building a suitable shuffle vector proves too hard, then bail
10690 // out with UseBuildVector set.
10691 bool UseBuildVector = false;
10692 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10693 unsigned LaneStart = l * NumLaneElems;
10694 for (unsigned i = 0; i != NumLaneElems; ++i) {
10695 // The mask element. This indexes into the input.
10696 int Idx = SVOp->getMaskElt(i+LaneStart);
10698 // the mask element does not index into any input vector.
10699 Mask.push_back(-1);
10703 // The input vector this mask element indexes into.
10704 int Input = Idx / NumLaneElems;
10706 // Turn the index into an offset from the start of the input vector.
10707 Idx -= Input * NumLaneElems;
10709 // Find or create a shuffle vector operand to hold this input.
10711 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10712 if (InputUsed[OpNo] == Input)
10713 // This input vector is already an operand.
10715 if (InputUsed[OpNo] < 0) {
10716 // Create a new operand for this input vector.
10717 InputUsed[OpNo] = Input;
10722 if (OpNo >= array_lengthof(InputUsed)) {
10723 // More than two input vectors used! Give up on trying to create a
10724 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10725 UseBuildVector = true;
10729 // Add the mask index for the new shuffle vector.
10730 Mask.push_back(Idx + OpNo * NumLaneElems);
10733 if (UseBuildVector) {
10734 SmallVector<SDValue, 16> SVOps;
10735 for (unsigned i = 0; i != NumLaneElems; ++i) {
10736 // The mask element. This indexes into the input.
10737 int Idx = SVOp->getMaskElt(i+LaneStart);
10739 SVOps.push_back(DAG.getUNDEF(EltVT));
10743 // The input vector this mask element indexes into.
10744 int Input = Idx / NumElems;
10746 // Turn the index into an offset from the start of the input vector.
10747 Idx -= Input * NumElems;
10749 // Extract the vector element by hand.
10750 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10751 SVOp->getOperand(Input),
10752 DAG.getIntPtrConstant(Idx)));
10755 // Construct the output using a BUILD_VECTOR.
10756 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10757 } else if (InputUsed[0] < 0) {
10758 // No input vectors were used! The result is undefined.
10759 Output[l] = DAG.getUNDEF(NVT);
10761 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10762 (InputUsed[0] % 2) * NumLaneElems,
10764 // If only one input was used, use an undefined vector for the other.
10765 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10766 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10767 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10768 // At least one input vector was used. Create a new shuffle vector.
10769 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10775 // Concatenate the result back
10776 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10779 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10780 /// 4 elements, and match them with several different shuffle types.
10782 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10783 SDValue V1 = SVOp->getOperand(0);
10784 SDValue V2 = SVOp->getOperand(1);
10786 MVT VT = SVOp->getSimpleValueType(0);
10788 assert(VT.is128BitVector() && "Unsupported vector size");
10790 std::pair<int, int> Locs[4];
10791 int Mask1[] = { -1, -1, -1, -1 };
10792 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10794 unsigned NumHi = 0;
10795 unsigned NumLo = 0;
10796 for (unsigned i = 0; i != 4; ++i) {
10797 int Idx = PermMask[i];
10799 Locs[i] = std::make_pair(-1, -1);
10801 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10803 Locs[i] = std::make_pair(0, NumLo);
10804 Mask1[NumLo] = Idx;
10807 Locs[i] = std::make_pair(1, NumHi);
10809 Mask1[2+NumHi] = Idx;
10815 if (NumLo <= 2 && NumHi <= 2) {
10816 // If no more than two elements come from either vector. This can be
10817 // implemented with two shuffles. First shuffle gather the elements.
10818 // The second shuffle, which takes the first shuffle as both of its
10819 // vector operands, put the elements into the right order.
10820 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10822 int Mask2[] = { -1, -1, -1, -1 };
10824 for (unsigned i = 0; i != 4; ++i)
10825 if (Locs[i].first != -1) {
10826 unsigned Idx = (i < 2) ? 0 : 4;
10827 Idx += Locs[i].first * 2 + Locs[i].second;
10831 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10834 if (NumLo == 3 || NumHi == 3) {
10835 // Otherwise, we must have three elements from one vector, call it X, and
10836 // one element from the other, call it Y. First, use a shufps to build an
10837 // intermediate vector with the one element from Y and the element from X
10838 // that will be in the same half in the final destination (the indexes don't
10839 // matter). Then, use a shufps to build the final vector, taking the half
10840 // containing the element from Y from the intermediate, and the other half
10843 // Normalize it so the 3 elements come from V1.
10844 CommuteVectorShuffleMask(PermMask, 4);
10848 // Find the element from V2.
10850 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10851 int Val = PermMask[HiIndex];
10858 Mask1[0] = PermMask[HiIndex];
10860 Mask1[2] = PermMask[HiIndex^1];
10862 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10864 if (HiIndex >= 2) {
10865 Mask1[0] = PermMask[0];
10866 Mask1[1] = PermMask[1];
10867 Mask1[2] = HiIndex & 1 ? 6 : 4;
10868 Mask1[3] = HiIndex & 1 ? 4 : 6;
10869 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10872 Mask1[0] = HiIndex & 1 ? 2 : 0;
10873 Mask1[1] = HiIndex & 1 ? 0 : 2;
10874 Mask1[2] = PermMask[2];
10875 Mask1[3] = PermMask[3];
10880 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10883 // Break it into (shuffle shuffle_hi, shuffle_lo).
10884 int LoMask[] = { -1, -1, -1, -1 };
10885 int HiMask[] = { -1, -1, -1, -1 };
10887 int *MaskPtr = LoMask;
10888 unsigned MaskIdx = 0;
10889 unsigned LoIdx = 0;
10890 unsigned HiIdx = 2;
10891 for (unsigned i = 0; i != 4; ++i) {
10898 int Idx = PermMask[i];
10900 Locs[i] = std::make_pair(-1, -1);
10901 } else if (Idx < 4) {
10902 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10903 MaskPtr[LoIdx] = Idx;
10906 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10907 MaskPtr[HiIdx] = Idx;
10912 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10913 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10914 int MaskOps[] = { -1, -1, -1, -1 };
10915 for (unsigned i = 0; i != 4; ++i)
10916 if (Locs[i].first != -1)
10917 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10918 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10921 static bool MayFoldVectorLoad(SDValue V) {
10922 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10923 V = V.getOperand(0);
10925 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10926 V = V.getOperand(0);
10927 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10928 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10929 // BUILD_VECTOR (load), undef
10930 V = V.getOperand(0);
10932 return MayFoldLoad(V);
10936 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10937 MVT VT = Op.getSimpleValueType();
10939 // Canonizalize to v2f64.
10940 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10941 return DAG.getNode(ISD::BITCAST, dl, VT,
10942 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10947 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10949 SDValue V1 = Op.getOperand(0);
10950 SDValue V2 = Op.getOperand(1);
10951 MVT VT = Op.getSimpleValueType();
10953 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10955 if (HasSSE2 && VT == MVT::v2f64)
10956 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10958 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10959 return DAG.getNode(ISD::BITCAST, dl, VT,
10960 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10961 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10962 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10966 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10967 SDValue V1 = Op.getOperand(0);
10968 SDValue V2 = Op.getOperand(1);
10969 MVT VT = Op.getSimpleValueType();
10971 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10972 "unsupported shuffle type");
10974 if (V2.getOpcode() == ISD::UNDEF)
10978 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10982 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10983 SDValue V1 = Op.getOperand(0);
10984 SDValue V2 = Op.getOperand(1);
10985 MVT VT = Op.getSimpleValueType();
10986 unsigned NumElems = VT.getVectorNumElements();
10988 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10989 // operand of these instructions is only memory, so check if there's a
10990 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10992 bool CanFoldLoad = false;
10994 // Trivial case, when V2 comes from a load.
10995 if (MayFoldVectorLoad(V2))
10996 CanFoldLoad = true;
10998 // When V1 is a load, it can be folded later into a store in isel, example:
10999 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11001 // (MOVLPSmr addr:$src1, VR128:$src2)
11002 // So, recognize this potential and also use MOVLPS or MOVLPD
11003 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11004 CanFoldLoad = true;
11006 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11008 if (HasSSE2 && NumElems == 2)
11009 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11012 // If we don't care about the second element, proceed to use movss.
11013 if (SVOp->getMaskElt(1) != -1)
11014 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11017 // movl and movlp will both match v2i64, but v2i64 is never matched by
11018 // movl earlier because we make it strict to avoid messing with the movlp load
11019 // folding logic (see the code above getMOVLP call). Match it here then,
11020 // this is horrible, but will stay like this until we move all shuffle
11021 // matching to x86 specific nodes. Note that for the 1st condition all
11022 // types are matched with movsd.
11024 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11025 // as to remove this logic from here, as much as possible
11026 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11027 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11028 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11031 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11033 // Invert the operand order and use SHUFPS to match it.
11034 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11035 getShuffleSHUFImmediate(SVOp), DAG);
11038 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11039 SelectionDAG &DAG) {
11041 MVT VT = Load->getSimpleValueType(0);
11042 MVT EVT = VT.getVectorElementType();
11043 SDValue Addr = Load->getOperand(1);
11044 SDValue NewAddr = DAG.getNode(
11045 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11046 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11049 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11050 DAG.getMachineFunction().getMachineMemOperand(
11051 Load->getMemOperand(), 0, EVT.getStoreSize()));
11055 // It is only safe to call this function if isINSERTPSMask is true for
11056 // this shufflevector mask.
11057 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11058 SelectionDAG &DAG) {
11059 // Generate an insertps instruction when inserting an f32 from memory onto a
11060 // v4f32 or when copying a member from one v4f32 to another.
11061 // We also use it for transferring i32 from one register to another,
11062 // since it simply copies the same bits.
11063 // If we're transferring an i32 from memory to a specific element in a
11064 // register, we output a generic DAG that will match the PINSRD
11066 MVT VT = SVOp->getSimpleValueType(0);
11067 MVT EVT = VT.getVectorElementType();
11068 SDValue V1 = SVOp->getOperand(0);
11069 SDValue V2 = SVOp->getOperand(1);
11070 auto Mask = SVOp->getMask();
11071 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11072 "unsupported vector type for insertps/pinsrd");
11074 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11075 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11076 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11080 unsigned DestIndex;
11084 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11087 // If we have 1 element from each vector, we have to check if we're
11088 // changing V1's element's place. If so, we're done. Otherwise, we
11089 // should assume we're changing V2's element's place and behave
11091 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11092 assert(DestIndex <= INT32_MAX && "truncated destination index");
11093 if (FromV1 == FromV2 &&
11094 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11098 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11101 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11102 "More than one element from V1 and from V2, or no elements from one "
11103 "of the vectors. This case should not have returned true from "
11108 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11111 // Get an index into the source vector in the range [0,4) (the mask is
11112 // in the range [0,8) because it can address V1 and V2)
11113 unsigned SrcIndex = Mask[DestIndex] % 4;
11114 if (MayFoldLoad(From)) {
11115 // Trivial case, when From comes from a load and is only used by the
11116 // shuffle. Make it use insertps from the vector that we need from that
11119 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11120 if (!NewLoad.getNode())
11123 if (EVT == MVT::f32) {
11124 // Create this as a scalar to vector to match the instruction pattern.
11125 SDValue LoadScalarToVector =
11126 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11127 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11128 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11130 } else { // EVT == MVT::i32
11131 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11132 // instruction, to match the PINSRD instruction, which loads an i32 to a
11133 // certain vector element.
11134 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11135 DAG.getConstant(DestIndex, MVT::i32));
11139 // Vector-element-to-vector
11140 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11141 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11144 // Reduce a vector shuffle to zext.
11145 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11146 SelectionDAG &DAG) {
11147 // PMOVZX is only available from SSE41.
11148 if (!Subtarget->hasSSE41())
11151 MVT VT = Op.getSimpleValueType();
11153 // Only AVX2 support 256-bit vector integer extending.
11154 if (!Subtarget->hasInt256() && VT.is256BitVector())
11157 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11159 SDValue V1 = Op.getOperand(0);
11160 SDValue V2 = Op.getOperand(1);
11161 unsigned NumElems = VT.getVectorNumElements();
11163 // Extending is an unary operation and the element type of the source vector
11164 // won't be equal to or larger than i64.
11165 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11166 VT.getVectorElementType() == MVT::i64)
11169 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11170 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11171 while ((1U << Shift) < NumElems) {
11172 if (SVOp->getMaskElt(1U << Shift) == 1)
11175 // The maximal ratio is 8, i.e. from i8 to i64.
11180 // Check the shuffle mask.
11181 unsigned Mask = (1U << Shift) - 1;
11182 for (unsigned i = 0; i != NumElems; ++i) {
11183 int EltIdx = SVOp->getMaskElt(i);
11184 if ((i & Mask) != 0 && EltIdx != -1)
11186 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11190 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11191 MVT NeVT = MVT::getIntegerVT(NBits);
11192 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11194 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11197 // Simplify the operand as it's prepared to be fed into shuffle.
11198 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
11199 if (V1.getOpcode() == ISD::BITCAST &&
11200 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
11201 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
11202 V1.getOperand(0).getOperand(0)
11203 .getSimpleValueType().getSizeInBits() == SignificantBits) {
11204 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
11205 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
11206 ConstantSDNode *CIdx =
11207 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
11208 // If it's foldable, i.e. normal load with single use, we will let code
11209 // selection to fold it. Otherwise, we will short the conversion sequence.
11210 if (CIdx && CIdx->getZExtValue() == 0 &&
11211 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
11212 MVT FullVT = V.getSimpleValueType();
11213 MVT V1VT = V1.getSimpleValueType();
11214 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
11215 // The "ext_vec_elt" node is wider than the result node.
11216 // In this case we should extract subvector from V.
11217 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
11218 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
11219 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
11220 FullVT.getVectorNumElements()/Ratio);
11221 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
11222 DAG.getIntPtrConstant(0));
11224 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
11228 return DAG.getNode(ISD::BITCAST, DL, VT,
11229 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11232 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11233 SelectionDAG &DAG) {
11234 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11235 MVT VT = Op.getSimpleValueType();
11237 SDValue V1 = Op.getOperand(0);
11238 SDValue V2 = Op.getOperand(1);
11240 if (isZeroShuffle(SVOp))
11241 return getZeroVector(VT, Subtarget, DAG, dl);
11243 // Handle splat operations
11244 if (SVOp->isSplat()) {
11245 // Use vbroadcast whenever the splat comes from a foldable load
11246 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11247 if (Broadcast.getNode())
11251 // Check integer expanding shuffles.
11252 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11253 if (NewOp.getNode())
11256 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11258 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11259 VT == MVT::v32i8) {
11260 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11261 if (NewOp.getNode())
11262 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11263 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11264 // FIXME: Figure out a cleaner way to do this.
11265 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11266 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11267 if (NewOp.getNode()) {
11268 MVT NewVT = NewOp.getSimpleValueType();
11269 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11270 NewVT, true, false))
11271 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11274 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11275 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11276 if (NewOp.getNode()) {
11277 MVT NewVT = NewOp.getSimpleValueType();
11278 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11279 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11288 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11289 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11290 SDValue V1 = Op.getOperand(0);
11291 SDValue V2 = Op.getOperand(1);
11292 MVT VT = Op.getSimpleValueType();
11294 unsigned NumElems = VT.getVectorNumElements();
11295 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11296 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11297 bool V1IsSplat = false;
11298 bool V2IsSplat = false;
11299 bool HasSSE2 = Subtarget->hasSSE2();
11300 bool HasFp256 = Subtarget->hasFp256();
11301 bool HasInt256 = Subtarget->hasInt256();
11302 MachineFunction &MF = DAG.getMachineFunction();
11303 bool OptForSize = MF.getFunction()->getAttributes().
11304 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11306 // Check if we should use the experimental vector shuffle lowering. If so,
11307 // delegate completely to that code path.
11308 if (ExperimentalVectorShuffleLowering)
11309 return lowerVectorShuffle(Op, Subtarget, DAG);
11311 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11313 if (V1IsUndef && V2IsUndef)
11314 return DAG.getUNDEF(VT);
11316 // When we create a shuffle node we put the UNDEF node to second operand,
11317 // but in some cases the first operand may be transformed to UNDEF.
11318 // In this case we should just commute the node.
11320 return DAG.getCommutedVectorShuffle(*SVOp);
11322 // Vector shuffle lowering takes 3 steps:
11324 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11325 // narrowing and commutation of operands should be handled.
11326 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11328 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11329 // so the shuffle can be broken into other shuffles and the legalizer can
11330 // try the lowering again.
11332 // The general idea is that no vector_shuffle operation should be left to
11333 // be matched during isel, all of them must be converted to a target specific
11336 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11337 // narrowing and commutation of operands should be handled. The actual code
11338 // doesn't include all of those, work in progress...
11339 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11340 if (NewOp.getNode())
11343 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11345 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11346 // unpckh_undef). Only use pshufd if speed is more important than size.
11347 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11348 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11349 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11350 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11352 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11353 V2IsUndef && MayFoldVectorLoad(V1))
11354 return getMOVDDup(Op, dl, V1, DAG);
11356 if (isMOVHLPS_v_undef_Mask(M, VT))
11357 return getMOVHighToLow(Op, dl, DAG);
11359 // Use to match splats
11360 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11361 (VT == MVT::v2f64 || VT == MVT::v2i64))
11362 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11364 if (isPSHUFDMask(M, VT)) {
11365 // The actual implementation will match the mask in the if above and then
11366 // during isel it can match several different instructions, not only pshufd
11367 // as its name says, sad but true, emulate the behavior for now...
11368 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11369 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11371 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11373 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11374 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11376 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11377 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11380 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11384 if (isPALIGNRMask(M, VT, Subtarget))
11385 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11386 getShufflePALIGNRImmediate(SVOp),
11389 if (isVALIGNMask(M, VT, Subtarget))
11390 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11391 getShuffleVALIGNImmediate(SVOp),
11394 // Check if this can be converted into a logical shift.
11395 bool isLeft = false;
11396 unsigned ShAmt = 0;
11398 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11399 if (isShift && ShVal.hasOneUse()) {
11400 // If the shifted value has multiple uses, it may be cheaper to use
11401 // v_set0 + movlhps or movhlps, etc.
11402 MVT EltVT = VT.getVectorElementType();
11403 ShAmt *= EltVT.getSizeInBits();
11404 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11407 if (isMOVLMask(M, VT)) {
11408 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11409 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11410 if (!isMOVLPMask(M, VT)) {
11411 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11412 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11414 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11415 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11419 // FIXME: fold these into legal mask.
11420 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11421 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11423 if (isMOVHLPSMask(M, VT))
11424 return getMOVHighToLow(Op, dl, DAG);
11426 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11427 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11429 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11430 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11432 if (isMOVLPMask(M, VT))
11433 return getMOVLP(Op, dl, DAG, HasSSE2);
11435 if (ShouldXformToMOVHLPS(M, VT) ||
11436 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11437 return DAG.getCommutedVectorShuffle(*SVOp);
11440 // No better options. Use a vshldq / vsrldq.
11441 MVT EltVT = VT.getVectorElementType();
11442 ShAmt *= EltVT.getSizeInBits();
11443 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11446 bool Commuted = false;
11447 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11448 // 1,1,1,1 -> v8i16 though.
11449 BitVector UndefElements;
11450 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11451 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11453 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11454 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11457 // Canonicalize the splat or undef, if present, to be on the RHS.
11458 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11459 CommuteVectorShuffleMask(M, NumElems);
11461 std::swap(V1IsSplat, V2IsSplat);
11465 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11466 // Shuffling low element of v1 into undef, just return v1.
11469 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11470 // the instruction selector will not match, so get a canonical MOVL with
11471 // swapped operands to undo the commute.
11472 return getMOVL(DAG, dl, VT, V2, V1);
11475 if (isUNPCKLMask(M, VT, HasInt256))
11476 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11478 if (isUNPCKHMask(M, VT, HasInt256))
11479 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11482 // Normalize mask so all entries that point to V2 points to its first
11483 // element then try to match unpck{h|l} again. If match, return a
11484 // new vector_shuffle with the corrected mask.p
11485 SmallVector<int, 8> NewMask(M.begin(), M.end());
11486 NormalizeMask(NewMask, NumElems);
11487 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11488 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11489 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11490 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11494 // Commute is back and try unpck* again.
11495 // FIXME: this seems wrong.
11496 CommuteVectorShuffleMask(M, NumElems);
11498 std::swap(V1IsSplat, V2IsSplat);
11500 if (isUNPCKLMask(M, VT, HasInt256))
11501 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11503 if (isUNPCKHMask(M, VT, HasInt256))
11504 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11507 // Normalize the node to match x86 shuffle ops if needed
11508 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11509 return DAG.getCommutedVectorShuffle(*SVOp);
11511 // The checks below are all present in isShuffleMaskLegal, but they are
11512 // inlined here right now to enable us to directly emit target specific
11513 // nodes, and remove one by one until they don't return Op anymore.
11515 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11516 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11517 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11518 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11521 if (isPSHUFHWMask(M, VT, HasInt256))
11522 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11523 getShufflePSHUFHWImmediate(SVOp),
11526 if (isPSHUFLWMask(M, VT, HasInt256))
11527 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11528 getShufflePSHUFLWImmediate(SVOp),
11531 unsigned MaskValue;
11532 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11534 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11536 if (isSHUFPMask(M, VT))
11537 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11538 getShuffleSHUFImmediate(SVOp), DAG);
11540 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11541 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11542 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11543 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11545 //===--------------------------------------------------------------------===//
11546 // Generate target specific nodes for 128 or 256-bit shuffles only
11547 // supported in the AVX instruction set.
11550 // Handle VMOVDDUPY permutations
11551 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11552 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11554 // Handle VPERMILPS/D* permutations
11555 if (isVPERMILPMask(M, VT)) {
11556 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11557 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11558 getShuffleSHUFImmediate(SVOp), DAG);
11559 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11560 getShuffleSHUFImmediate(SVOp), DAG);
11564 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11565 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11566 Idx*(NumElems/2), DAG, dl);
11568 // Handle VPERM2F128/VPERM2I128 permutations
11569 if (isVPERM2X128Mask(M, VT, HasFp256))
11570 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11571 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11573 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11574 return getINSERTPS(SVOp, dl, DAG);
11577 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11578 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11580 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11581 VT.is512BitVector()) {
11582 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11583 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11584 SmallVector<SDValue, 16> permclMask;
11585 for (unsigned i = 0; i != NumElems; ++i) {
11586 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11589 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11591 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11592 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11593 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11594 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11595 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11598 //===--------------------------------------------------------------------===//
11599 // Since no target specific shuffle was selected for this generic one,
11600 // lower it into other known shuffles. FIXME: this isn't true yet, but
11601 // this is the plan.
11604 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11605 if (VT == MVT::v8i16) {
11606 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11607 if (NewOp.getNode())
11611 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11612 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11613 if (NewOp.getNode())
11617 if (VT == MVT::v16i8) {
11618 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11619 if (NewOp.getNode())
11623 if (VT == MVT::v32i8) {
11624 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11625 if (NewOp.getNode())
11629 // Handle all 128-bit wide vectors with 4 elements, and match them with
11630 // several different shuffle types.
11631 if (NumElems == 4 && VT.is128BitVector())
11632 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11634 // Handle general 256-bit shuffles
11635 if (VT.is256BitVector())
11636 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11641 // This function assumes its argument is a BUILD_VECTOR of constants or
11642 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11644 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11645 unsigned &MaskValue) {
11647 unsigned NumElems = BuildVector->getNumOperands();
11648 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11649 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11650 unsigned NumElemsInLane = NumElems / NumLanes;
11652 // Blend for v16i16 should be symetric for the both lanes.
11653 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11654 SDValue EltCond = BuildVector->getOperand(i);
11655 SDValue SndLaneEltCond =
11656 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11658 int Lane1Cond = -1, Lane2Cond = -1;
11659 if (isa<ConstantSDNode>(EltCond))
11660 Lane1Cond = !isZero(EltCond);
11661 if (isa<ConstantSDNode>(SndLaneEltCond))
11662 Lane2Cond = !isZero(SndLaneEltCond);
11664 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11665 // Lane1Cond != 0, means we want the first argument.
11666 // Lane1Cond == 0, means we want the second argument.
11667 // The encoding of this argument is 0 for the first argument, 1
11668 // for the second. Therefore, invert the condition.
11669 MaskValue |= !Lane1Cond << i;
11670 else if (Lane1Cond < 0)
11671 MaskValue |= !Lane2Cond << i;
11678 // Try to lower a vselect node into a simple blend instruction.
11679 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11680 SelectionDAG &DAG) {
11681 SDValue Cond = Op.getOperand(0);
11682 SDValue LHS = Op.getOperand(1);
11683 SDValue RHS = Op.getOperand(2);
11685 MVT VT = Op.getSimpleValueType();
11686 MVT EltVT = VT.getVectorElementType();
11687 unsigned NumElems = VT.getVectorNumElements();
11689 // There is no blend with immediate in AVX-512.
11690 if (VT.is512BitVector())
11693 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11695 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11698 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11701 // Check the mask for BLEND and build the value.
11702 unsigned MaskValue = 0;
11703 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11706 // Convert i32 vectors to floating point if it is not AVX2.
11707 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11709 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11710 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11712 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11713 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11716 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11717 DAG.getConstant(MaskValue, MVT::i32));
11718 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11721 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11722 // A vselect where all conditions and data are constants can be optimized into
11723 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11724 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11725 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11726 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11729 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11730 if (BlendOp.getNode())
11733 // Some types for vselect were previously set to Expand, not Legal or
11734 // Custom. Return an empty SDValue so we fall-through to Expand, after
11735 // the Custom lowering phase.
11736 MVT VT = Op.getSimpleValueType();
11737 switch (VT.SimpleTy) {
11742 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11747 // We couldn't create a "Blend with immediate" node.
11748 // This node should still be legal, but we'll have to emit a blendv*
11753 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11754 MVT VT = Op.getSimpleValueType();
11757 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11760 if (VT.getSizeInBits() == 8) {
11761 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11762 Op.getOperand(0), Op.getOperand(1));
11763 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11764 DAG.getValueType(VT));
11765 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11768 if (VT.getSizeInBits() == 16) {
11769 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11770 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11772 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11773 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11774 DAG.getNode(ISD::BITCAST, dl,
11777 Op.getOperand(1)));
11778 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11779 Op.getOperand(0), Op.getOperand(1));
11780 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11781 DAG.getValueType(VT));
11782 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11785 if (VT == MVT::f32) {
11786 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11787 // the result back to FR32 register. It's only worth matching if the
11788 // result has a single use which is a store or a bitcast to i32. And in
11789 // the case of a store, it's not worth it if the index is a constant 0,
11790 // because a MOVSSmr can be used instead, which is smaller and faster.
11791 if (!Op.hasOneUse())
11793 SDNode *User = *Op.getNode()->use_begin();
11794 if ((User->getOpcode() != ISD::STORE ||
11795 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11796 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11797 (User->getOpcode() != ISD::BITCAST ||
11798 User->getValueType(0) != MVT::i32))
11800 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11801 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11804 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11807 if (VT == MVT::i32 || VT == MVT::i64) {
11808 // ExtractPS/pextrq works with constant index.
11809 if (isa<ConstantSDNode>(Op.getOperand(1)))
11815 /// Extract one bit from mask vector, like v16i1 or v8i1.
11816 /// AVX-512 feature.
11818 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11819 SDValue Vec = Op.getOperand(0);
11821 MVT VecVT = Vec.getSimpleValueType();
11822 SDValue Idx = Op.getOperand(1);
11823 MVT EltVT = Op.getSimpleValueType();
11825 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11827 // variable index can't be handled in mask registers,
11828 // extend vector to VR512
11829 if (!isa<ConstantSDNode>(Idx)) {
11830 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11831 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11832 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11833 ExtVT.getVectorElementType(), Ext, Idx);
11834 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11837 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11838 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11839 unsigned MaxSift = rc->getSize()*8 - 1;
11840 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11841 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11842 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11843 DAG.getConstant(MaxSift, MVT::i8));
11844 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11845 DAG.getIntPtrConstant(0));
11849 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11850 SelectionDAG &DAG) const {
11852 SDValue Vec = Op.getOperand(0);
11853 MVT VecVT = Vec.getSimpleValueType();
11854 SDValue Idx = Op.getOperand(1);
11856 if (Op.getSimpleValueType() == MVT::i1)
11857 return ExtractBitFromMaskVector(Op, DAG);
11859 if (!isa<ConstantSDNode>(Idx)) {
11860 if (VecVT.is512BitVector() ||
11861 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11862 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11865 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11866 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11867 MaskEltVT.getSizeInBits());
11869 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11870 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11871 getZeroVector(MaskVT, Subtarget, DAG, dl),
11872 Idx, DAG.getConstant(0, getPointerTy()));
11873 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11874 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11875 Perm, DAG.getConstant(0, getPointerTy()));
11880 // If this is a 256-bit vector result, first extract the 128-bit vector and
11881 // then extract the element from the 128-bit vector.
11882 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11884 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11885 // Get the 128-bit vector.
11886 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11887 MVT EltVT = VecVT.getVectorElementType();
11889 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11891 //if (IdxVal >= NumElems/2)
11892 // IdxVal -= NumElems/2;
11893 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11894 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11895 DAG.getConstant(IdxVal, MVT::i32));
11898 assert(VecVT.is128BitVector() && "Unexpected vector length");
11900 if (Subtarget->hasSSE41()) {
11901 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11906 MVT VT = Op.getSimpleValueType();
11907 // TODO: handle v16i8.
11908 if (VT.getSizeInBits() == 16) {
11909 SDValue Vec = Op.getOperand(0);
11910 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11912 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11913 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11914 DAG.getNode(ISD::BITCAST, dl,
11916 Op.getOperand(1)));
11917 // Transform it so it match pextrw which produces a 32-bit result.
11918 MVT EltVT = MVT::i32;
11919 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11920 Op.getOperand(0), Op.getOperand(1));
11921 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11922 DAG.getValueType(VT));
11923 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11926 if (VT.getSizeInBits() == 32) {
11927 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11931 // SHUFPS the element to the lowest double word, then movss.
11932 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11933 MVT VVT = Op.getOperand(0).getSimpleValueType();
11934 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11935 DAG.getUNDEF(VVT), Mask);
11936 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11937 DAG.getIntPtrConstant(0));
11940 if (VT.getSizeInBits() == 64) {
11941 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11942 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11943 // to match extract_elt for f64.
11944 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11948 // UNPCKHPD the element to the lowest double word, then movsd.
11949 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11950 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11951 int Mask[2] = { 1, -1 };
11952 MVT VVT = Op.getOperand(0).getSimpleValueType();
11953 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11954 DAG.getUNDEF(VVT), Mask);
11955 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11956 DAG.getIntPtrConstant(0));
11962 /// Insert one bit to mask vector, like v16i1 or v8i1.
11963 /// AVX-512 feature.
11965 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11967 SDValue Vec = Op.getOperand(0);
11968 SDValue Elt = Op.getOperand(1);
11969 SDValue Idx = Op.getOperand(2);
11970 MVT VecVT = Vec.getSimpleValueType();
11972 if (!isa<ConstantSDNode>(Idx)) {
11973 // Non constant index. Extend source and destination,
11974 // insert element and then truncate the result.
11975 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11976 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11977 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11978 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11979 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11980 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11983 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11984 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11985 if (Vec.getOpcode() == ISD::UNDEF)
11986 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11987 DAG.getConstant(IdxVal, MVT::i8));
11988 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11989 unsigned MaxSift = rc->getSize()*8 - 1;
11990 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11991 DAG.getConstant(MaxSift, MVT::i8));
11992 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11993 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11994 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11997 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11998 SelectionDAG &DAG) const {
11999 MVT VT = Op.getSimpleValueType();
12000 MVT EltVT = VT.getVectorElementType();
12002 if (EltVT == MVT::i1)
12003 return InsertBitToMaskVector(Op, DAG);
12006 SDValue N0 = Op.getOperand(0);
12007 SDValue N1 = Op.getOperand(1);
12008 SDValue N2 = Op.getOperand(2);
12009 if (!isa<ConstantSDNode>(N2))
12011 auto *N2C = cast<ConstantSDNode>(N2);
12012 unsigned IdxVal = N2C->getZExtValue();
12014 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12015 // into that, and then insert the subvector back into the result.
12016 if (VT.is256BitVector() || VT.is512BitVector()) {
12017 // Get the desired 128-bit vector half.
12018 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12020 // Insert the element into the desired half.
12021 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12022 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12024 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12025 DAG.getConstant(IdxIn128, MVT::i32));
12027 // Insert the changed part back to the 256-bit vector
12028 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12030 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12032 if (Subtarget->hasSSE41()) {
12033 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12035 if (VT == MVT::v8i16) {
12036 Opc = X86ISD::PINSRW;
12038 assert(VT == MVT::v16i8);
12039 Opc = X86ISD::PINSRB;
12042 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12044 if (N1.getValueType() != MVT::i32)
12045 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12046 if (N2.getValueType() != MVT::i32)
12047 N2 = DAG.getIntPtrConstant(IdxVal);
12048 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12051 if (EltVT == MVT::f32) {
12052 // Bits [7:6] of the constant are the source select. This will always be
12053 // zero here. The DAG Combiner may combine an extract_elt index into
12055 // bits. For example (insert (extract, 3), 2) could be matched by
12057 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12058 // Bits [5:4] of the constant are the destination select. This is the
12059 // value of the incoming immediate.
12060 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12061 // combine either bitwise AND or insert of float 0.0 to set these bits.
12062 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12063 // Create this as a scalar to vector..
12064 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12065 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12068 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12069 // PINSR* works with constant index.
12074 if (EltVT == MVT::i8)
12077 if (EltVT.getSizeInBits() == 16) {
12078 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12079 // as its second argument.
12080 if (N1.getValueType() != MVT::i32)
12081 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12082 if (N2.getValueType() != MVT::i32)
12083 N2 = DAG.getIntPtrConstant(IdxVal);
12084 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12089 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12091 MVT OpVT = Op.getSimpleValueType();
12093 // If this is a 256-bit vector result, first insert into a 128-bit
12094 // vector and then insert into the 256-bit vector.
12095 if (!OpVT.is128BitVector()) {
12096 // Insert into a 128-bit vector.
12097 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12098 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12099 OpVT.getVectorNumElements() / SizeFactor);
12101 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12103 // Insert the 128-bit vector.
12104 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12107 if (OpVT == MVT::v1i64 &&
12108 Op.getOperand(0).getValueType() == MVT::i64)
12109 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12111 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12112 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12113 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12114 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12117 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12118 // a simple subregister reference or explicit instructions to grab
12119 // upper bits of a vector.
12120 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12121 SelectionDAG &DAG) {
12123 SDValue In = Op.getOperand(0);
12124 SDValue Idx = Op.getOperand(1);
12125 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12126 MVT ResVT = Op.getSimpleValueType();
12127 MVT InVT = In.getSimpleValueType();
12129 if (Subtarget->hasFp256()) {
12130 if (ResVT.is128BitVector() &&
12131 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12132 isa<ConstantSDNode>(Idx)) {
12133 return Extract128BitVector(In, IdxVal, DAG, dl);
12135 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12136 isa<ConstantSDNode>(Idx)) {
12137 return Extract256BitVector(In, IdxVal, DAG, dl);
12143 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12144 // simple superregister reference or explicit instructions to insert
12145 // the upper bits of a vector.
12146 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12147 SelectionDAG &DAG) {
12148 if (Subtarget->hasFp256()) {
12149 SDLoc dl(Op.getNode());
12150 SDValue Vec = Op.getNode()->getOperand(0);
12151 SDValue SubVec = Op.getNode()->getOperand(1);
12152 SDValue Idx = Op.getNode()->getOperand(2);
12154 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12155 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12156 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12157 isa<ConstantSDNode>(Idx)) {
12158 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12159 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12162 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12163 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12164 isa<ConstantSDNode>(Idx)) {
12165 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12166 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12172 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12173 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12174 // one of the above mentioned nodes. It has to be wrapped because otherwise
12175 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12176 // be used to form addressing mode. These wrapped nodes will be selected
12179 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12180 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12182 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12183 // global base reg.
12184 unsigned char OpFlag = 0;
12185 unsigned WrapperKind = X86ISD::Wrapper;
12186 CodeModel::Model M = DAG.getTarget().getCodeModel();
12188 if (Subtarget->isPICStyleRIPRel() &&
12189 (M == CodeModel::Small || M == CodeModel::Kernel))
12190 WrapperKind = X86ISD::WrapperRIP;
12191 else if (Subtarget->isPICStyleGOT())
12192 OpFlag = X86II::MO_GOTOFF;
12193 else if (Subtarget->isPICStyleStubPIC())
12194 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12196 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12197 CP->getAlignment(),
12198 CP->getOffset(), OpFlag);
12200 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12201 // With PIC, the address is actually $g + Offset.
12203 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12204 DAG.getNode(X86ISD::GlobalBaseReg,
12205 SDLoc(), getPointerTy()),
12212 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12213 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12215 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12216 // global base reg.
12217 unsigned char OpFlag = 0;
12218 unsigned WrapperKind = X86ISD::Wrapper;
12219 CodeModel::Model M = DAG.getTarget().getCodeModel();
12221 if (Subtarget->isPICStyleRIPRel() &&
12222 (M == CodeModel::Small || M == CodeModel::Kernel))
12223 WrapperKind = X86ISD::WrapperRIP;
12224 else if (Subtarget->isPICStyleGOT())
12225 OpFlag = X86II::MO_GOTOFF;
12226 else if (Subtarget->isPICStyleStubPIC())
12227 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12229 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12232 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12234 // With PIC, the address is actually $g + Offset.
12236 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12237 DAG.getNode(X86ISD::GlobalBaseReg,
12238 SDLoc(), getPointerTy()),
12245 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12246 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12248 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12249 // global base reg.
12250 unsigned char OpFlag = 0;
12251 unsigned WrapperKind = X86ISD::Wrapper;
12252 CodeModel::Model M = DAG.getTarget().getCodeModel();
12254 if (Subtarget->isPICStyleRIPRel() &&
12255 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12256 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12257 OpFlag = X86II::MO_GOTPCREL;
12258 WrapperKind = X86ISD::WrapperRIP;
12259 } else if (Subtarget->isPICStyleGOT()) {
12260 OpFlag = X86II::MO_GOT;
12261 } else if (Subtarget->isPICStyleStubPIC()) {
12262 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12263 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12264 OpFlag = X86II::MO_DARWIN_NONLAZY;
12267 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12270 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12272 // With PIC, the address is actually $g + Offset.
12273 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12274 !Subtarget->is64Bit()) {
12275 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12276 DAG.getNode(X86ISD::GlobalBaseReg,
12277 SDLoc(), getPointerTy()),
12281 // For symbols that require a load from a stub to get the address, emit the
12283 if (isGlobalStubReference(OpFlag))
12284 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12285 MachinePointerInfo::getGOT(), false, false, false, 0);
12291 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12292 // Create the TargetBlockAddressAddress node.
12293 unsigned char OpFlags =
12294 Subtarget->ClassifyBlockAddressReference();
12295 CodeModel::Model M = DAG.getTarget().getCodeModel();
12296 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12297 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12299 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12302 if (Subtarget->isPICStyleRIPRel() &&
12303 (M == CodeModel::Small || M == CodeModel::Kernel))
12304 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12306 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12308 // With PIC, the address is actually $g + Offset.
12309 if (isGlobalRelativeToPICBase(OpFlags)) {
12310 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12311 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12319 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12320 int64_t Offset, SelectionDAG &DAG) const {
12321 // Create the TargetGlobalAddress node, folding in the constant
12322 // offset if it is legal.
12323 unsigned char OpFlags =
12324 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12325 CodeModel::Model M = DAG.getTarget().getCodeModel();
12327 if (OpFlags == X86II::MO_NO_FLAG &&
12328 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12329 // A direct static reference to a global.
12330 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12333 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12336 if (Subtarget->isPICStyleRIPRel() &&
12337 (M == CodeModel::Small || M == CodeModel::Kernel))
12338 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12340 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12342 // With PIC, the address is actually $g + Offset.
12343 if (isGlobalRelativeToPICBase(OpFlags)) {
12344 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12345 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12349 // For globals that require a load from a stub to get the address, emit the
12351 if (isGlobalStubReference(OpFlags))
12352 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12353 MachinePointerInfo::getGOT(), false, false, false, 0);
12355 // If there was a non-zero offset that we didn't fold, create an explicit
12356 // addition for it.
12358 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12359 DAG.getConstant(Offset, getPointerTy()));
12365 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12366 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12367 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12368 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12372 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12373 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12374 unsigned char OperandFlags, bool LocalDynamic = false) {
12375 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12376 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12378 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12379 GA->getValueType(0),
12383 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12387 SDValue Ops[] = { Chain, TGA, *InFlag };
12388 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12390 SDValue Ops[] = { Chain, TGA };
12391 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12394 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12395 MFI->setAdjustsStack(true);
12397 SDValue Flag = Chain.getValue(1);
12398 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12401 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12403 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12406 SDLoc dl(GA); // ? function entry point might be better
12407 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12408 DAG.getNode(X86ISD::GlobalBaseReg,
12409 SDLoc(), PtrVT), InFlag);
12410 InFlag = Chain.getValue(1);
12412 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12415 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12417 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12419 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12420 X86::RAX, X86II::MO_TLSGD);
12423 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12429 // Get the start address of the TLS block for this module.
12430 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12431 .getInfo<X86MachineFunctionInfo>();
12432 MFI->incNumLocalDynamicTLSAccesses();
12436 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12437 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12440 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12441 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12442 InFlag = Chain.getValue(1);
12443 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12444 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12447 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12451 unsigned char OperandFlags = X86II::MO_DTPOFF;
12452 unsigned WrapperKind = X86ISD::Wrapper;
12453 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12454 GA->getValueType(0),
12455 GA->getOffset(), OperandFlags);
12456 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12458 // Add x@dtpoff with the base.
12459 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12462 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12463 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12464 const EVT PtrVT, TLSModel::Model model,
12465 bool is64Bit, bool isPIC) {
12468 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12469 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12470 is64Bit ? 257 : 256));
12472 SDValue ThreadPointer =
12473 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12474 MachinePointerInfo(Ptr), false, false, false, 0);
12476 unsigned char OperandFlags = 0;
12477 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12479 unsigned WrapperKind = X86ISD::Wrapper;
12480 if (model == TLSModel::LocalExec) {
12481 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12482 } else if (model == TLSModel::InitialExec) {
12484 OperandFlags = X86II::MO_GOTTPOFF;
12485 WrapperKind = X86ISD::WrapperRIP;
12487 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12490 llvm_unreachable("Unexpected model");
12493 // emit "addl x@ntpoff,%eax" (local exec)
12494 // or "addl x@indntpoff,%eax" (initial exec)
12495 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12497 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12498 GA->getOffset(), OperandFlags);
12499 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12501 if (model == TLSModel::InitialExec) {
12502 if (isPIC && !is64Bit) {
12503 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12504 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12508 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12509 MachinePointerInfo::getGOT(), false, false, false, 0);
12512 // The address of the thread local variable is the add of the thread
12513 // pointer with the offset of the variable.
12514 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12518 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12520 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12521 const GlobalValue *GV = GA->getGlobal();
12523 if (Subtarget->isTargetELF()) {
12524 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12527 case TLSModel::GeneralDynamic:
12528 if (Subtarget->is64Bit())
12529 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12530 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12531 case TLSModel::LocalDynamic:
12532 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12533 Subtarget->is64Bit());
12534 case TLSModel::InitialExec:
12535 case TLSModel::LocalExec:
12536 return LowerToTLSExecModel(
12537 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12538 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12540 llvm_unreachable("Unknown TLS model.");
12543 if (Subtarget->isTargetDarwin()) {
12544 // Darwin only has one model of TLS. Lower to that.
12545 unsigned char OpFlag = 0;
12546 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12547 X86ISD::WrapperRIP : X86ISD::Wrapper;
12549 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12550 // global base reg.
12551 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12552 !Subtarget->is64Bit();
12554 OpFlag = X86II::MO_TLVP_PIC_BASE;
12556 OpFlag = X86II::MO_TLVP;
12558 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12559 GA->getValueType(0),
12560 GA->getOffset(), OpFlag);
12561 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12563 // With PIC32, the address is actually $g + Offset.
12565 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12566 DAG.getNode(X86ISD::GlobalBaseReg,
12567 SDLoc(), getPointerTy()),
12570 // Lowering the machine isd will make sure everything is in the right
12572 SDValue Chain = DAG.getEntryNode();
12573 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12574 SDValue Args[] = { Chain, Offset };
12575 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12577 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12578 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12579 MFI->setAdjustsStack(true);
12581 // And our return value (tls address) is in the standard call return value
12583 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12584 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12585 Chain.getValue(1));
12588 if (Subtarget->isTargetKnownWindowsMSVC() ||
12589 Subtarget->isTargetWindowsGNU()) {
12590 // Just use the implicit TLS architecture
12591 // Need to generate someting similar to:
12592 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12594 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12595 // mov rcx, qword [rdx+rcx*8]
12596 // mov eax, .tls$:tlsvar
12597 // [rax+rcx] contains the address
12598 // Windows 64bit: gs:0x58
12599 // Windows 32bit: fs:__tls_array
12602 SDValue Chain = DAG.getEntryNode();
12604 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12605 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12606 // use its literal value of 0x2C.
12607 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12608 ? Type::getInt8PtrTy(*DAG.getContext(),
12610 : Type::getInt32PtrTy(*DAG.getContext(),
12614 Subtarget->is64Bit()
12615 ? DAG.getIntPtrConstant(0x58)
12616 : (Subtarget->isTargetWindowsGNU()
12617 ? DAG.getIntPtrConstant(0x2C)
12618 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12620 SDValue ThreadPointer =
12621 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12622 MachinePointerInfo(Ptr), false, false, false, 0);
12624 // Load the _tls_index variable
12625 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12626 if (Subtarget->is64Bit())
12627 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12628 IDX, MachinePointerInfo(), MVT::i32,
12629 false, false, false, 0);
12631 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12632 false, false, false, 0);
12634 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12636 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12638 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12639 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12640 false, false, false, 0);
12642 // Get the offset of start of .tls section
12643 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12644 GA->getValueType(0),
12645 GA->getOffset(), X86II::MO_SECREL);
12646 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12648 // The address of the thread local variable is the add of the thread
12649 // pointer with the offset of the variable.
12650 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12653 llvm_unreachable("TLS not implemented for this target.");
12656 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12657 /// and take a 2 x i32 value to shift plus a shift amount.
12658 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12659 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12660 MVT VT = Op.getSimpleValueType();
12661 unsigned VTBits = VT.getSizeInBits();
12663 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12664 SDValue ShOpLo = Op.getOperand(0);
12665 SDValue ShOpHi = Op.getOperand(1);
12666 SDValue ShAmt = Op.getOperand(2);
12667 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12668 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12670 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12671 DAG.getConstant(VTBits - 1, MVT::i8));
12672 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12673 DAG.getConstant(VTBits - 1, MVT::i8))
12674 : DAG.getConstant(0, VT);
12676 SDValue Tmp2, Tmp3;
12677 if (Op.getOpcode() == ISD::SHL_PARTS) {
12678 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12679 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12681 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12682 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12685 // If the shift amount is larger or equal than the width of a part we can't
12686 // rely on the results of shld/shrd. Insert a test and select the appropriate
12687 // values for large shift amounts.
12688 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12689 DAG.getConstant(VTBits, MVT::i8));
12690 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12691 AndNode, DAG.getConstant(0, MVT::i8));
12694 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12695 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12696 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12698 if (Op.getOpcode() == ISD::SHL_PARTS) {
12699 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12700 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12702 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12703 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12706 SDValue Ops[2] = { Lo, Hi };
12707 return DAG.getMergeValues(Ops, dl);
12710 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12711 SelectionDAG &DAG) const {
12712 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12714 if (SrcVT.isVector())
12717 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12718 "Unknown SINT_TO_FP to lower!");
12720 // These are really Legal; return the operand so the caller accepts it as
12722 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12724 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12725 Subtarget->is64Bit()) {
12730 unsigned Size = SrcVT.getSizeInBits()/8;
12731 MachineFunction &MF = DAG.getMachineFunction();
12732 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12733 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12734 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12736 MachinePointerInfo::getFixedStack(SSFI),
12738 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12741 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12743 SelectionDAG &DAG) const {
12747 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12749 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12751 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12753 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12755 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12756 MachineMemOperand *MMO;
12758 int SSFI = FI->getIndex();
12760 DAG.getMachineFunction()
12761 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12762 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12764 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12765 StackSlot = StackSlot.getOperand(1);
12767 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12768 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12770 Tys, Ops, SrcVT, MMO);
12773 Chain = Result.getValue(1);
12774 SDValue InFlag = Result.getValue(2);
12776 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12777 // shouldn't be necessary except that RFP cannot be live across
12778 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12779 MachineFunction &MF = DAG.getMachineFunction();
12780 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12781 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12782 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12783 Tys = DAG.getVTList(MVT::Other);
12785 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12787 MachineMemOperand *MMO =
12788 DAG.getMachineFunction()
12789 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12790 MachineMemOperand::MOStore, SSFISize, SSFISize);
12792 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12793 Ops, Op.getValueType(), MMO);
12794 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12795 MachinePointerInfo::getFixedStack(SSFI),
12796 false, false, false, 0);
12802 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12803 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12804 SelectionDAG &DAG) const {
12805 // This algorithm is not obvious. Here it is what we're trying to output:
12808 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12809 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12811 haddpd %xmm0, %xmm0
12813 pshufd $0x4e, %xmm0, %xmm1
12819 LLVMContext *Context = DAG.getContext();
12821 // Build some magic constants.
12822 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12823 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12824 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12826 SmallVector<Constant*,2> CV1;
12828 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12829 APInt(64, 0x4330000000000000ULL))));
12831 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12832 APInt(64, 0x4530000000000000ULL))));
12833 Constant *C1 = ConstantVector::get(CV1);
12834 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12836 // Load the 64-bit value into an XMM register.
12837 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12839 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12840 MachinePointerInfo::getConstantPool(),
12841 false, false, false, 16);
12842 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12843 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12846 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12847 MachinePointerInfo::getConstantPool(),
12848 false, false, false, 16);
12849 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12850 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12853 if (Subtarget->hasSSE3()) {
12854 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12855 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12857 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12858 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12860 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12861 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12865 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12866 DAG.getIntPtrConstant(0));
12869 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12870 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12871 SelectionDAG &DAG) const {
12873 // FP constant to bias correct the final result.
12874 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12877 // Load the 32-bit value into an XMM register.
12878 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12881 // Zero out the upper parts of the register.
12882 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12884 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12885 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12886 DAG.getIntPtrConstant(0));
12888 // Or the load with the bias.
12889 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12890 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12891 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12892 MVT::v2f64, Load)),
12893 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12894 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12895 MVT::v2f64, Bias)));
12896 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12897 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12898 DAG.getIntPtrConstant(0));
12900 // Subtract the bias.
12901 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12903 // Handle final rounding.
12904 EVT DestVT = Op.getValueType();
12906 if (DestVT.bitsLT(MVT::f64))
12907 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12908 DAG.getIntPtrConstant(0));
12909 if (DestVT.bitsGT(MVT::f64))
12910 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12912 // Handle final rounding.
12916 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12917 SelectionDAG &DAG) const {
12918 SDValue N0 = Op.getOperand(0);
12919 MVT SVT = N0.getSimpleValueType();
12922 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12923 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12924 "Custom UINT_TO_FP is not supported!");
12926 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12927 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12928 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12931 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12932 SelectionDAG &DAG) const {
12933 SDValue N0 = Op.getOperand(0);
12936 if (Op.getValueType().isVector())
12937 return lowerUINT_TO_FP_vec(Op, DAG);
12939 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12940 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12941 // the optimization here.
12942 if (DAG.SignBitIsZero(N0))
12943 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12945 MVT SrcVT = N0.getSimpleValueType();
12946 MVT DstVT = Op.getSimpleValueType();
12947 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12948 return LowerUINT_TO_FP_i64(Op, DAG);
12949 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12950 return LowerUINT_TO_FP_i32(Op, DAG);
12951 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12954 // Make a 64-bit buffer, and use it to build an FILD.
12955 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12956 if (SrcVT == MVT::i32) {
12957 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12958 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12959 getPointerTy(), StackSlot, WordOff);
12960 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12961 StackSlot, MachinePointerInfo(),
12963 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12964 OffsetSlot, MachinePointerInfo(),
12966 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12970 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12971 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12972 StackSlot, MachinePointerInfo(),
12974 // For i64 source, we need to add the appropriate power of 2 if the input
12975 // was negative. This is the same as the optimization in
12976 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12977 // we must be careful to do the computation in x87 extended precision, not
12978 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12979 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12980 MachineMemOperand *MMO =
12981 DAG.getMachineFunction()
12982 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12983 MachineMemOperand::MOLoad, 8, 8);
12985 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12986 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12987 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12990 APInt FF(32, 0x5F800000ULL);
12992 // Check whether the sign bit is set.
12993 SDValue SignSet = DAG.getSetCC(dl,
12994 getSetCCResultType(*DAG.getContext(), MVT::i64),
12995 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12998 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12999 SDValue FudgePtr = DAG.getConstantPool(
13000 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13003 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13004 SDValue Zero = DAG.getIntPtrConstant(0);
13005 SDValue Four = DAG.getIntPtrConstant(4);
13006 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13008 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13010 // Load the value out, extending it from f32 to f80.
13011 // FIXME: Avoid the extend by constructing the right constant pool?
13012 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13013 FudgePtr, MachinePointerInfo::getConstantPool(),
13014 MVT::f32, false, false, false, 4);
13015 // Extend everything to 80 bits to force it to be done on x87.
13016 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13017 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13020 std::pair<SDValue,SDValue>
13021 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13022 bool IsSigned, bool IsReplace) const {
13025 EVT DstTy = Op.getValueType();
13027 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13028 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13032 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13033 DstTy.getSimpleVT() >= MVT::i16 &&
13034 "Unknown FP_TO_INT to lower!");
13036 // These are really Legal.
13037 if (DstTy == MVT::i32 &&
13038 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13039 return std::make_pair(SDValue(), SDValue());
13040 if (Subtarget->is64Bit() &&
13041 DstTy == MVT::i64 &&
13042 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13043 return std::make_pair(SDValue(), SDValue());
13045 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13046 // stack slot, or into the FTOL runtime function.
13047 MachineFunction &MF = DAG.getMachineFunction();
13048 unsigned MemSize = DstTy.getSizeInBits()/8;
13049 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13050 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13053 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13054 Opc = X86ISD::WIN_FTOL;
13056 switch (DstTy.getSimpleVT().SimpleTy) {
13057 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13058 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13059 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13060 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13063 SDValue Chain = DAG.getEntryNode();
13064 SDValue Value = Op.getOperand(0);
13065 EVT TheVT = Op.getOperand(0).getValueType();
13066 // FIXME This causes a redundant load/store if the SSE-class value is already
13067 // in memory, such as if it is on the callstack.
13068 if (isScalarFPTypeInSSEReg(TheVT)) {
13069 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13070 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13071 MachinePointerInfo::getFixedStack(SSFI),
13073 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13075 Chain, StackSlot, DAG.getValueType(TheVT)
13078 MachineMemOperand *MMO =
13079 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13080 MachineMemOperand::MOLoad, MemSize, MemSize);
13081 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13082 Chain = Value.getValue(1);
13083 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13084 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13087 MachineMemOperand *MMO =
13088 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13089 MachineMemOperand::MOStore, MemSize, MemSize);
13091 if (Opc != X86ISD::WIN_FTOL) {
13092 // Build the FP_TO_INT*_IN_MEM
13093 SDValue Ops[] = { Chain, Value, StackSlot };
13094 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13096 return std::make_pair(FIST, StackSlot);
13098 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13099 DAG.getVTList(MVT::Other, MVT::Glue),
13101 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13102 MVT::i32, ftol.getValue(1));
13103 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13104 MVT::i32, eax.getValue(2));
13105 SDValue Ops[] = { eax, edx };
13106 SDValue pair = IsReplace
13107 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13108 : DAG.getMergeValues(Ops, DL);
13109 return std::make_pair(pair, SDValue());
13113 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13114 const X86Subtarget *Subtarget) {
13115 MVT VT = Op->getSimpleValueType(0);
13116 SDValue In = Op->getOperand(0);
13117 MVT InVT = In.getSimpleValueType();
13120 // Optimize vectors in AVX mode:
13123 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13124 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13125 // Concat upper and lower parts.
13128 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13129 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13130 // Concat upper and lower parts.
13133 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13134 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13135 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13138 if (Subtarget->hasInt256())
13139 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13141 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13142 SDValue Undef = DAG.getUNDEF(InVT);
13143 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13144 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13145 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13147 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13148 VT.getVectorNumElements()/2);
13150 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13151 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13153 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13156 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13157 SelectionDAG &DAG) {
13158 MVT VT = Op->getSimpleValueType(0);
13159 SDValue In = Op->getOperand(0);
13160 MVT InVT = In.getSimpleValueType();
13162 unsigned int NumElts = VT.getVectorNumElements();
13163 if (NumElts != 8 && NumElts != 16)
13166 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13167 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13169 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13170 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13171 // Now we have only mask extension
13172 assert(InVT.getVectorElementType() == MVT::i1);
13173 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13174 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13175 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13176 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13177 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13178 MachinePointerInfo::getConstantPool(),
13179 false, false, false, Alignment);
13181 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13182 if (VT.is512BitVector())
13184 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13187 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13188 SelectionDAG &DAG) {
13189 if (Subtarget->hasFp256()) {
13190 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13198 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13199 SelectionDAG &DAG) {
13201 MVT VT = Op.getSimpleValueType();
13202 SDValue In = Op.getOperand(0);
13203 MVT SVT = In.getSimpleValueType();
13205 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13206 return LowerZERO_EXTEND_AVX512(Op, DAG);
13208 if (Subtarget->hasFp256()) {
13209 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13214 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13215 VT.getVectorNumElements() != SVT.getVectorNumElements());
13219 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13221 MVT VT = Op.getSimpleValueType();
13222 SDValue In = Op.getOperand(0);
13223 MVT InVT = In.getSimpleValueType();
13225 if (VT == MVT::i1) {
13226 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13227 "Invalid scalar TRUNCATE operation");
13228 if (InVT.getSizeInBits() >= 32)
13230 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13231 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13233 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13234 "Invalid TRUNCATE operation");
13236 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13237 if (VT.getVectorElementType().getSizeInBits() >=8)
13238 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13240 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13241 unsigned NumElts = InVT.getVectorNumElements();
13242 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13243 if (InVT.getSizeInBits() < 512) {
13244 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13245 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13249 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13250 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13251 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13252 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13253 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13254 MachinePointerInfo::getConstantPool(),
13255 false, false, false, Alignment);
13256 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13257 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13258 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13261 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13262 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13263 if (Subtarget->hasInt256()) {
13264 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13265 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13266 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13268 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13269 DAG.getIntPtrConstant(0));
13272 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13273 DAG.getIntPtrConstant(0));
13274 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13275 DAG.getIntPtrConstant(2));
13276 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13277 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13278 static const int ShufMask[] = {0, 2, 4, 6};
13279 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13282 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13283 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13284 if (Subtarget->hasInt256()) {
13285 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13287 SmallVector<SDValue,32> pshufbMask;
13288 for (unsigned i = 0; i < 2; ++i) {
13289 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13290 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13291 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13292 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13293 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13294 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13295 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13296 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13297 for (unsigned j = 0; j < 8; ++j)
13298 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13300 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13301 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13302 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13304 static const int ShufMask[] = {0, 2, -1, -1};
13305 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13307 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13308 DAG.getIntPtrConstant(0));
13309 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13312 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13313 DAG.getIntPtrConstant(0));
13315 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13316 DAG.getIntPtrConstant(4));
13318 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13319 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13321 // The PSHUFB mask:
13322 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13323 -1, -1, -1, -1, -1, -1, -1, -1};
13325 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13326 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13327 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13329 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13330 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13332 // The MOVLHPS Mask:
13333 static const int ShufMask2[] = {0, 1, 4, 5};
13334 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13335 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13338 // Handle truncation of V256 to V128 using shuffles.
13339 if (!VT.is128BitVector() || !InVT.is256BitVector())
13342 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13344 unsigned NumElems = VT.getVectorNumElements();
13345 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13347 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13348 // Prepare truncation shuffle mask
13349 for (unsigned i = 0; i != NumElems; ++i)
13350 MaskVec[i] = i * 2;
13351 SDValue V = DAG.getVectorShuffle(NVT, DL,
13352 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13353 DAG.getUNDEF(NVT), &MaskVec[0]);
13354 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13355 DAG.getIntPtrConstant(0));
13358 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13359 SelectionDAG &DAG) const {
13360 assert(!Op.getSimpleValueType().isVector());
13362 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13363 /*IsSigned=*/ true, /*IsReplace=*/ false);
13364 SDValue FIST = Vals.first, StackSlot = Vals.second;
13365 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13366 if (!FIST.getNode()) return Op;
13368 if (StackSlot.getNode())
13369 // Load the result.
13370 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13371 FIST, StackSlot, MachinePointerInfo(),
13372 false, false, false, 0);
13374 // The node is the result.
13378 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13379 SelectionDAG &DAG) const {
13380 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13381 /*IsSigned=*/ false, /*IsReplace=*/ false);
13382 SDValue FIST = Vals.first, StackSlot = Vals.second;
13383 assert(FIST.getNode() && "Unexpected failure");
13385 if (StackSlot.getNode())
13386 // Load the result.
13387 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13388 FIST, StackSlot, MachinePointerInfo(),
13389 false, false, false, 0);
13391 // The node is the result.
13395 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13397 MVT VT = Op.getSimpleValueType();
13398 SDValue In = Op.getOperand(0);
13399 MVT SVT = In.getSimpleValueType();
13401 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13403 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13404 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13405 In, DAG.getUNDEF(SVT)));
13408 // The only differences between FABS and FNEG are the mask and the logic op.
13409 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13410 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13411 "Wrong opcode for lowering FABS or FNEG.");
13413 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13415 MVT VT = Op.getSimpleValueType();
13416 // Assume scalar op for initialization; update for vector if needed.
13417 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13418 // generate a 16-byte vector constant and logic op even for the scalar case.
13419 // Using a 16-byte mask allows folding the load of the mask with
13420 // the logic op, so it can save (~4 bytes) on code size.
13422 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13423 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13424 // decide if we should generate a 16-byte constant mask when we only need 4 or
13425 // 8 bytes for the scalar case.
13426 if (VT.isVector()) {
13427 EltVT = VT.getVectorElementType();
13428 NumElts = VT.getVectorNumElements();
13431 unsigned EltBits = EltVT.getSizeInBits();
13432 LLVMContext *Context = DAG.getContext();
13433 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13435 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13436 Constant *C = ConstantInt::get(*Context, MaskElt);
13437 C = ConstantVector::getSplat(NumElts, C);
13438 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13439 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13440 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13441 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13442 MachinePointerInfo::getConstantPool(),
13443 false, false, false, Alignment);
13445 if (VT.isVector()) {
13446 // For a vector, cast operands to a vector type, perform the logic op,
13447 // and cast the result back to the original value type.
13448 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13449 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13450 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13451 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13452 return DAG.getNode(ISD::BITCAST, dl, VT,
13453 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13455 // If not vector, then scalar.
13456 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13457 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13460 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13461 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13462 LLVMContext *Context = DAG.getContext();
13463 SDValue Op0 = Op.getOperand(0);
13464 SDValue Op1 = Op.getOperand(1);
13466 MVT VT = Op.getSimpleValueType();
13467 MVT SrcVT = Op1.getSimpleValueType();
13469 // If second operand is smaller, extend it first.
13470 if (SrcVT.bitsLT(VT)) {
13471 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13474 // And if it is bigger, shrink it first.
13475 if (SrcVT.bitsGT(VT)) {
13476 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13480 // At this point the operands and the result should have the same
13481 // type, and that won't be f80 since that is not custom lowered.
13483 // First get the sign bit of second operand.
13484 SmallVector<Constant*,4> CV;
13485 if (SrcVT == MVT::f64) {
13486 const fltSemantics &Sem = APFloat::IEEEdouble;
13487 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13488 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13490 const fltSemantics &Sem = APFloat::IEEEsingle;
13491 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13492 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13493 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13494 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13496 Constant *C = ConstantVector::get(CV);
13497 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13498 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13499 MachinePointerInfo::getConstantPool(),
13500 false, false, false, 16);
13501 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13503 // Shift sign bit right or left if the two operands have different types.
13504 if (SrcVT.bitsGT(VT)) {
13505 // Op0 is MVT::f32, Op1 is MVT::f64.
13506 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13507 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13508 DAG.getConstant(32, MVT::i32));
13509 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13510 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13511 DAG.getIntPtrConstant(0));
13514 // Clear first operand sign bit.
13516 if (VT == MVT::f64) {
13517 const fltSemantics &Sem = APFloat::IEEEdouble;
13518 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13519 APInt(64, ~(1ULL << 63)))));
13520 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13522 const fltSemantics &Sem = APFloat::IEEEsingle;
13523 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13524 APInt(32, ~(1U << 31)))));
13525 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13526 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13527 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13529 C = ConstantVector::get(CV);
13530 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13531 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13532 MachinePointerInfo::getConstantPool(),
13533 false, false, false, 16);
13534 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13536 // Or the value with the sign bit.
13537 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13540 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13541 SDValue N0 = Op.getOperand(0);
13543 MVT VT = Op.getSimpleValueType();
13545 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13546 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13547 DAG.getConstant(1, VT));
13548 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13551 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13553 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13554 SelectionDAG &DAG) {
13555 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13557 if (!Subtarget->hasSSE41())
13560 if (!Op->hasOneUse())
13563 SDNode *N = Op.getNode();
13566 SmallVector<SDValue, 8> Opnds;
13567 DenseMap<SDValue, unsigned> VecInMap;
13568 SmallVector<SDValue, 8> VecIns;
13569 EVT VT = MVT::Other;
13571 // Recognize a special case where a vector is casted into wide integer to
13573 Opnds.push_back(N->getOperand(0));
13574 Opnds.push_back(N->getOperand(1));
13576 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13577 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13578 // BFS traverse all OR'd operands.
13579 if (I->getOpcode() == ISD::OR) {
13580 Opnds.push_back(I->getOperand(0));
13581 Opnds.push_back(I->getOperand(1));
13582 // Re-evaluate the number of nodes to be traversed.
13583 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13587 // Quit if a non-EXTRACT_VECTOR_ELT
13588 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13591 // Quit if without a constant index.
13592 SDValue Idx = I->getOperand(1);
13593 if (!isa<ConstantSDNode>(Idx))
13596 SDValue ExtractedFromVec = I->getOperand(0);
13597 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13598 if (M == VecInMap.end()) {
13599 VT = ExtractedFromVec.getValueType();
13600 // Quit if not 128/256-bit vector.
13601 if (!VT.is128BitVector() && !VT.is256BitVector())
13603 // Quit if not the same type.
13604 if (VecInMap.begin() != VecInMap.end() &&
13605 VT != VecInMap.begin()->first.getValueType())
13607 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13608 VecIns.push_back(ExtractedFromVec);
13610 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13613 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13614 "Not extracted from 128-/256-bit vector.");
13616 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13618 for (DenseMap<SDValue, unsigned>::const_iterator
13619 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13620 // Quit if not all elements are used.
13621 if (I->second != FullMask)
13625 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13627 // Cast all vectors into TestVT for PTEST.
13628 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13629 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13631 // If more than one full vectors are evaluated, OR them first before PTEST.
13632 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13633 // Each iteration will OR 2 nodes and append the result until there is only
13634 // 1 node left, i.e. the final OR'd value of all vectors.
13635 SDValue LHS = VecIns[Slot];
13636 SDValue RHS = VecIns[Slot + 1];
13637 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13640 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13641 VecIns.back(), VecIns.back());
13644 /// \brief return true if \c Op has a use that doesn't just read flags.
13645 static bool hasNonFlagsUse(SDValue Op) {
13646 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13648 SDNode *User = *UI;
13649 unsigned UOpNo = UI.getOperandNo();
13650 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13651 // Look pass truncate.
13652 UOpNo = User->use_begin().getOperandNo();
13653 User = *User->use_begin();
13656 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13657 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13663 /// Emit nodes that will be selected as "test Op0,Op0", or something
13665 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13666 SelectionDAG &DAG) const {
13667 if (Op.getValueType() == MVT::i1)
13668 // KORTEST instruction should be selected
13669 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13670 DAG.getConstant(0, Op.getValueType()));
13672 // CF and OF aren't always set the way we want. Determine which
13673 // of these we need.
13674 bool NeedCF = false;
13675 bool NeedOF = false;
13678 case X86::COND_A: case X86::COND_AE:
13679 case X86::COND_B: case X86::COND_BE:
13682 case X86::COND_G: case X86::COND_GE:
13683 case X86::COND_L: case X86::COND_LE:
13684 case X86::COND_O: case X86::COND_NO: {
13685 // Check if we really need to set the
13686 // Overflow flag. If NoSignedWrap is present
13687 // that is not actually needed.
13688 switch (Op->getOpcode()) {
13693 const BinaryWithFlagsSDNode *BinNode =
13694 cast<BinaryWithFlagsSDNode>(Op.getNode());
13695 if (BinNode->hasNoSignedWrap())
13705 // See if we can use the EFLAGS value from the operand instead of
13706 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13707 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13708 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13709 // Emit a CMP with 0, which is the TEST pattern.
13710 //if (Op.getValueType() == MVT::i1)
13711 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13712 // DAG.getConstant(0, MVT::i1));
13713 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13714 DAG.getConstant(0, Op.getValueType()));
13716 unsigned Opcode = 0;
13717 unsigned NumOperands = 0;
13719 // Truncate operations may prevent the merge of the SETCC instruction
13720 // and the arithmetic instruction before it. Attempt to truncate the operands
13721 // of the arithmetic instruction and use a reduced bit-width instruction.
13722 bool NeedTruncation = false;
13723 SDValue ArithOp = Op;
13724 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13725 SDValue Arith = Op->getOperand(0);
13726 // Both the trunc and the arithmetic op need to have one user each.
13727 if (Arith->hasOneUse())
13728 switch (Arith.getOpcode()) {
13735 NeedTruncation = true;
13741 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13742 // which may be the result of a CAST. We use the variable 'Op', which is the
13743 // non-casted variable when we check for possible users.
13744 switch (ArithOp.getOpcode()) {
13746 // Due to an isel shortcoming, be conservative if this add is likely to be
13747 // selected as part of a load-modify-store instruction. When the root node
13748 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13749 // uses of other nodes in the match, such as the ADD in this case. This
13750 // leads to the ADD being left around and reselected, with the result being
13751 // two adds in the output. Alas, even if none our users are stores, that
13752 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13753 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13754 // climbing the DAG back to the root, and it doesn't seem to be worth the
13756 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13757 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13758 if (UI->getOpcode() != ISD::CopyToReg &&
13759 UI->getOpcode() != ISD::SETCC &&
13760 UI->getOpcode() != ISD::STORE)
13763 if (ConstantSDNode *C =
13764 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13765 // An add of one will be selected as an INC.
13766 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13767 Opcode = X86ISD::INC;
13772 // An add of negative one (subtract of one) will be selected as a DEC.
13773 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13774 Opcode = X86ISD::DEC;
13780 // Otherwise use a regular EFLAGS-setting add.
13781 Opcode = X86ISD::ADD;
13786 // If we have a constant logical shift that's only used in a comparison
13787 // against zero turn it into an equivalent AND. This allows turning it into
13788 // a TEST instruction later.
13789 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13790 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13791 EVT VT = Op.getValueType();
13792 unsigned BitWidth = VT.getSizeInBits();
13793 unsigned ShAmt = Op->getConstantOperandVal(1);
13794 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13796 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13797 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13798 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13799 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13801 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13802 DAG.getConstant(Mask, VT));
13803 DAG.ReplaceAllUsesWith(Op, New);
13809 // If the primary and result isn't used, don't bother using X86ISD::AND,
13810 // because a TEST instruction will be better.
13811 if (!hasNonFlagsUse(Op))
13817 // Due to the ISEL shortcoming noted above, be conservative if this op is
13818 // likely to be selected as part of a load-modify-store instruction.
13819 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13820 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13821 if (UI->getOpcode() == ISD::STORE)
13824 // Otherwise use a regular EFLAGS-setting instruction.
13825 switch (ArithOp.getOpcode()) {
13826 default: llvm_unreachable("unexpected operator!");
13827 case ISD::SUB: Opcode = X86ISD::SUB; break;
13828 case ISD::XOR: Opcode = X86ISD::XOR; break;
13829 case ISD::AND: Opcode = X86ISD::AND; break;
13831 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13832 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13833 if (EFLAGS.getNode())
13836 Opcode = X86ISD::OR;
13850 return SDValue(Op.getNode(), 1);
13856 // If we found that truncation is beneficial, perform the truncation and
13858 if (NeedTruncation) {
13859 EVT VT = Op.getValueType();
13860 SDValue WideVal = Op->getOperand(0);
13861 EVT WideVT = WideVal.getValueType();
13862 unsigned ConvertedOp = 0;
13863 // Use a target machine opcode to prevent further DAGCombine
13864 // optimizations that may separate the arithmetic operations
13865 // from the setcc node.
13866 switch (WideVal.getOpcode()) {
13868 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13869 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13870 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13871 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13872 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13876 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13877 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13878 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13879 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13880 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13886 // Emit a CMP with 0, which is the TEST pattern.
13887 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13888 DAG.getConstant(0, Op.getValueType()));
13890 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13891 SmallVector<SDValue, 4> Ops;
13892 for (unsigned i = 0; i != NumOperands; ++i)
13893 Ops.push_back(Op.getOperand(i));
13895 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13896 DAG.ReplaceAllUsesWith(Op, New);
13897 return SDValue(New.getNode(), 1);
13900 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13902 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13903 SDLoc dl, SelectionDAG &DAG) const {
13904 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13905 if (C->getAPIntValue() == 0)
13906 return EmitTest(Op0, X86CC, dl, DAG);
13908 if (Op0.getValueType() == MVT::i1)
13909 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13912 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13913 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13914 // Do the comparison at i32 if it's smaller, besides the Atom case.
13915 // This avoids subregister aliasing issues. Keep the smaller reference
13916 // if we're optimizing for size, however, as that'll allow better folding
13917 // of memory operations.
13918 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13919 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13920 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13921 !Subtarget->isAtom()) {
13922 unsigned ExtendOp =
13923 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13924 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13925 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13927 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13928 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13929 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13931 return SDValue(Sub.getNode(), 1);
13933 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13936 /// Convert a comparison if required by the subtarget.
13937 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13938 SelectionDAG &DAG) const {
13939 // If the subtarget does not support the FUCOMI instruction, floating-point
13940 // comparisons have to be converted.
13941 if (Subtarget->hasCMov() ||
13942 Cmp.getOpcode() != X86ISD::CMP ||
13943 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13944 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13947 // The instruction selector will select an FUCOM instruction instead of
13948 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13949 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13950 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13952 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13953 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13954 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13955 DAG.getConstant(8, MVT::i8));
13956 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13957 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13960 static bool isAllOnes(SDValue V) {
13961 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13962 return C && C->isAllOnesValue();
13965 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13966 /// if it's possible.
13967 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13968 SDLoc dl, SelectionDAG &DAG) const {
13969 SDValue Op0 = And.getOperand(0);
13970 SDValue Op1 = And.getOperand(1);
13971 if (Op0.getOpcode() == ISD::TRUNCATE)
13972 Op0 = Op0.getOperand(0);
13973 if (Op1.getOpcode() == ISD::TRUNCATE)
13974 Op1 = Op1.getOperand(0);
13977 if (Op1.getOpcode() == ISD::SHL)
13978 std::swap(Op0, Op1);
13979 if (Op0.getOpcode() == ISD::SHL) {
13980 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13981 if (And00C->getZExtValue() == 1) {
13982 // If we looked past a truncate, check that it's only truncating away
13984 unsigned BitWidth = Op0.getValueSizeInBits();
13985 unsigned AndBitWidth = And.getValueSizeInBits();
13986 if (BitWidth > AndBitWidth) {
13988 DAG.computeKnownBits(Op0, Zeros, Ones);
13989 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13993 RHS = Op0.getOperand(1);
13995 } else if (Op1.getOpcode() == ISD::Constant) {
13996 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13997 uint64_t AndRHSVal = AndRHS->getZExtValue();
13998 SDValue AndLHS = Op0;
14000 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14001 LHS = AndLHS.getOperand(0);
14002 RHS = AndLHS.getOperand(1);
14005 // Use BT if the immediate can't be encoded in a TEST instruction.
14006 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14008 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14012 if (LHS.getNode()) {
14013 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14014 // instruction. Since the shift amount is in-range-or-undefined, we know
14015 // that doing a bittest on the i32 value is ok. We extend to i32 because
14016 // the encoding for the i16 version is larger than the i32 version.
14017 // Also promote i16 to i32 for performance / code size reason.
14018 if (LHS.getValueType() == MVT::i8 ||
14019 LHS.getValueType() == MVT::i16)
14020 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14022 // If the operand types disagree, extend the shift amount to match. Since
14023 // BT ignores high bits (like shifts) we can use anyextend.
14024 if (LHS.getValueType() != RHS.getValueType())
14025 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14027 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14028 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14029 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14030 DAG.getConstant(Cond, MVT::i8), BT);
14036 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14038 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14043 // SSE Condition code mapping:
14052 switch (SetCCOpcode) {
14053 default: llvm_unreachable("Unexpected SETCC condition");
14055 case ISD::SETEQ: SSECC = 0; break;
14057 case ISD::SETGT: Swap = true; // Fallthrough
14059 case ISD::SETOLT: SSECC = 1; break;
14061 case ISD::SETGE: Swap = true; // Fallthrough
14063 case ISD::SETOLE: SSECC = 2; break;
14064 case ISD::SETUO: SSECC = 3; break;
14066 case ISD::SETNE: SSECC = 4; break;
14067 case ISD::SETULE: Swap = true; // Fallthrough
14068 case ISD::SETUGE: SSECC = 5; break;
14069 case ISD::SETULT: Swap = true; // Fallthrough
14070 case ISD::SETUGT: SSECC = 6; break;
14071 case ISD::SETO: SSECC = 7; break;
14073 case ISD::SETONE: SSECC = 8; break;
14076 std::swap(Op0, Op1);
14081 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14082 // ones, and then concatenate the result back.
14083 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14084 MVT VT = Op.getSimpleValueType();
14086 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14087 "Unsupported value type for operation");
14089 unsigned NumElems = VT.getVectorNumElements();
14091 SDValue CC = Op.getOperand(2);
14093 // Extract the LHS vectors
14094 SDValue LHS = Op.getOperand(0);
14095 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14096 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14098 // Extract the RHS vectors
14099 SDValue RHS = Op.getOperand(1);
14100 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14101 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14103 // Issue the operation on the smaller types and concatenate the result back
14104 MVT EltVT = VT.getVectorElementType();
14105 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14106 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14107 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14108 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14111 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14112 const X86Subtarget *Subtarget) {
14113 SDValue Op0 = Op.getOperand(0);
14114 SDValue Op1 = Op.getOperand(1);
14115 SDValue CC = Op.getOperand(2);
14116 MVT VT = Op.getSimpleValueType();
14119 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14120 Op.getValueType().getScalarType() == MVT::i1 &&
14121 "Cannot set masked compare for this operation");
14123 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14125 bool Unsigned = false;
14128 switch (SetCCOpcode) {
14129 default: llvm_unreachable("Unexpected SETCC condition");
14130 case ISD::SETNE: SSECC = 4; break;
14131 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14132 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14133 case ISD::SETLT: Swap = true; //fall-through
14134 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14135 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14136 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14137 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14138 case ISD::SETULE: Unsigned = true; //fall-through
14139 case ISD::SETLE: SSECC = 2; break;
14143 std::swap(Op0, Op1);
14145 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14146 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14147 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14148 DAG.getConstant(SSECC, MVT::i8));
14151 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14152 /// operand \p Op1. If non-trivial (for example because it's not constant)
14153 /// return an empty value.
14154 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14156 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14160 MVT VT = Op1.getSimpleValueType();
14161 MVT EVT = VT.getVectorElementType();
14162 unsigned n = VT.getVectorNumElements();
14163 SmallVector<SDValue, 8> ULTOp1;
14165 for (unsigned i = 0; i < n; ++i) {
14166 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14167 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14170 // Avoid underflow.
14171 APInt Val = Elt->getAPIntValue();
14175 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14178 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14181 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14182 SelectionDAG &DAG) {
14183 SDValue Op0 = Op.getOperand(0);
14184 SDValue Op1 = Op.getOperand(1);
14185 SDValue CC = Op.getOperand(2);
14186 MVT VT = Op.getSimpleValueType();
14187 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14188 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14193 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14194 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14197 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14198 unsigned Opc = X86ISD::CMPP;
14199 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14200 assert(VT.getVectorNumElements() <= 16);
14201 Opc = X86ISD::CMPM;
14203 // In the two special cases we can't handle, emit two comparisons.
14206 unsigned CombineOpc;
14207 if (SetCCOpcode == ISD::SETUEQ) {
14208 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14210 assert(SetCCOpcode == ISD::SETONE);
14211 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14214 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14215 DAG.getConstant(CC0, MVT::i8));
14216 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14217 DAG.getConstant(CC1, MVT::i8));
14218 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14220 // Handle all other FP comparisons here.
14221 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14222 DAG.getConstant(SSECC, MVT::i8));
14225 // Break 256-bit integer vector compare into smaller ones.
14226 if (VT.is256BitVector() && !Subtarget->hasInt256())
14227 return Lower256IntVSETCC(Op, DAG);
14229 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14230 EVT OpVT = Op1.getValueType();
14231 if (Subtarget->hasAVX512()) {
14232 if (Op1.getValueType().is512BitVector() ||
14233 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14234 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14235 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14237 // In AVX-512 architecture setcc returns mask with i1 elements,
14238 // But there is no compare instruction for i8 and i16 elements in KNL.
14239 // We are not talking about 512-bit operands in this case, these
14240 // types are illegal.
14242 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14243 OpVT.getVectorElementType().getSizeInBits() >= 8))
14244 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14245 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14248 // We are handling one of the integer comparisons here. Since SSE only has
14249 // GT and EQ comparisons for integer, swapping operands and multiple
14250 // operations may be required for some comparisons.
14252 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14253 bool Subus = false;
14255 switch (SetCCOpcode) {
14256 default: llvm_unreachable("Unexpected SETCC condition");
14257 case ISD::SETNE: Invert = true;
14258 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14259 case ISD::SETLT: Swap = true;
14260 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14261 case ISD::SETGE: Swap = true;
14262 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14263 Invert = true; break;
14264 case ISD::SETULT: Swap = true;
14265 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14266 FlipSigns = true; break;
14267 case ISD::SETUGE: Swap = true;
14268 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14269 FlipSigns = true; Invert = true; break;
14272 // Special case: Use min/max operations for SETULE/SETUGE
14273 MVT VET = VT.getVectorElementType();
14275 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14276 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14279 switch (SetCCOpcode) {
14281 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14282 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14285 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14288 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14289 if (!MinMax && hasSubus) {
14290 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14292 // t = psubus Op0, Op1
14293 // pcmpeq t, <0..0>
14294 switch (SetCCOpcode) {
14296 case ISD::SETULT: {
14297 // If the comparison is against a constant we can turn this into a
14298 // setule. With psubus, setule does not require a swap. This is
14299 // beneficial because the constant in the register is no longer
14300 // destructed as the destination so it can be hoisted out of a loop.
14301 // Only do this pre-AVX since vpcmp* is no longer destructive.
14302 if (Subtarget->hasAVX())
14304 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14305 if (ULEOp1.getNode()) {
14307 Subus = true; Invert = false; Swap = false;
14311 // Psubus is better than flip-sign because it requires no inversion.
14312 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14313 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14317 Opc = X86ISD::SUBUS;
14323 std::swap(Op0, Op1);
14325 // Check that the operation in question is available (most are plain SSE2,
14326 // but PCMPGTQ and PCMPEQQ have different requirements).
14327 if (VT == MVT::v2i64) {
14328 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14329 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14331 // First cast everything to the right type.
14332 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14333 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14335 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14336 // bits of the inputs before performing those operations. The lower
14337 // compare is always unsigned.
14340 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14342 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14343 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14344 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14345 Sign, Zero, Sign, Zero);
14347 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14348 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14350 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14351 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14352 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14354 // Create masks for only the low parts/high parts of the 64 bit integers.
14355 static const int MaskHi[] = { 1, 1, 3, 3 };
14356 static const int MaskLo[] = { 0, 0, 2, 2 };
14357 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14358 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14359 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14361 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14362 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14365 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14367 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14370 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14371 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14372 // pcmpeqd + pshufd + pand.
14373 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14375 // First cast everything to the right type.
14376 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14377 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14380 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14382 // Make sure the lower and upper halves are both all-ones.
14383 static const int Mask[] = { 1, 0, 3, 2 };
14384 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14385 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14388 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14390 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14394 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14395 // bits of the inputs before performing those operations.
14397 EVT EltVT = VT.getVectorElementType();
14398 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14399 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14400 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14403 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14405 // If the logical-not of the result is required, perform that now.
14407 Result = DAG.getNOT(dl, Result, VT);
14410 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14413 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14414 getZeroVector(VT, Subtarget, DAG, dl));
14419 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14421 MVT VT = Op.getSimpleValueType();
14423 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14425 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14426 && "SetCC type must be 8-bit or 1-bit integer");
14427 SDValue Op0 = Op.getOperand(0);
14428 SDValue Op1 = Op.getOperand(1);
14430 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14432 // Optimize to BT if possible.
14433 // Lower (X & (1 << N)) == 0 to BT(X, N).
14434 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14435 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14436 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14437 Op1.getOpcode() == ISD::Constant &&
14438 cast<ConstantSDNode>(Op1)->isNullValue() &&
14439 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14440 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14441 if (NewSetCC.getNode())
14445 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14447 if (Op1.getOpcode() == ISD::Constant &&
14448 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14449 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14450 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14452 // If the input is a setcc, then reuse the input setcc or use a new one with
14453 // the inverted condition.
14454 if (Op0.getOpcode() == X86ISD::SETCC) {
14455 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14456 bool Invert = (CC == ISD::SETNE) ^
14457 cast<ConstantSDNode>(Op1)->isNullValue();
14461 CCode = X86::GetOppositeBranchCondition(CCode);
14462 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14463 DAG.getConstant(CCode, MVT::i8),
14464 Op0.getOperand(1));
14466 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14470 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14471 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14472 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14474 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14475 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14478 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14479 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14480 if (X86CC == X86::COND_INVALID)
14483 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14484 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14485 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14486 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14488 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14492 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14493 static bool isX86LogicalCmp(SDValue Op) {
14494 unsigned Opc = Op.getNode()->getOpcode();
14495 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14496 Opc == X86ISD::SAHF)
14498 if (Op.getResNo() == 1 &&
14499 (Opc == X86ISD::ADD ||
14500 Opc == X86ISD::SUB ||
14501 Opc == X86ISD::ADC ||
14502 Opc == X86ISD::SBB ||
14503 Opc == X86ISD::SMUL ||
14504 Opc == X86ISD::UMUL ||
14505 Opc == X86ISD::INC ||
14506 Opc == X86ISD::DEC ||
14507 Opc == X86ISD::OR ||
14508 Opc == X86ISD::XOR ||
14509 Opc == X86ISD::AND))
14512 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14518 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14519 if (V.getOpcode() != ISD::TRUNCATE)
14522 SDValue VOp0 = V.getOperand(0);
14523 unsigned InBits = VOp0.getValueSizeInBits();
14524 unsigned Bits = V.getValueSizeInBits();
14525 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14528 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14529 bool addTest = true;
14530 SDValue Cond = Op.getOperand(0);
14531 SDValue Op1 = Op.getOperand(1);
14532 SDValue Op2 = Op.getOperand(2);
14534 EVT VT = Op1.getValueType();
14537 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14538 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14539 // sequence later on.
14540 if (Cond.getOpcode() == ISD::SETCC &&
14541 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14542 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14543 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14544 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14545 int SSECC = translateX86FSETCC(
14546 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14549 if (Subtarget->hasAVX512()) {
14550 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14551 DAG.getConstant(SSECC, MVT::i8));
14552 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14554 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14555 DAG.getConstant(SSECC, MVT::i8));
14556 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14557 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14558 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14562 if (Cond.getOpcode() == ISD::SETCC) {
14563 SDValue NewCond = LowerSETCC(Cond, DAG);
14564 if (NewCond.getNode())
14568 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14569 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14570 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14571 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14572 if (Cond.getOpcode() == X86ISD::SETCC &&
14573 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14574 isZero(Cond.getOperand(1).getOperand(1))) {
14575 SDValue Cmp = Cond.getOperand(1);
14577 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14579 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14580 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14581 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14583 SDValue CmpOp0 = Cmp.getOperand(0);
14584 // Apply further optimizations for special cases
14585 // (select (x != 0), -1, 0) -> neg & sbb
14586 // (select (x == 0), 0, -1) -> neg & sbb
14587 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14588 if (YC->isNullValue() &&
14589 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14590 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14591 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14592 DAG.getConstant(0, CmpOp0.getValueType()),
14594 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14595 DAG.getConstant(X86::COND_B, MVT::i8),
14596 SDValue(Neg.getNode(), 1));
14600 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14601 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14602 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14604 SDValue Res = // Res = 0 or -1.
14605 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14606 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14608 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14609 Res = DAG.getNOT(DL, Res, Res.getValueType());
14611 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14612 if (!N2C || !N2C->isNullValue())
14613 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14618 // Look past (and (setcc_carry (cmp ...)), 1).
14619 if (Cond.getOpcode() == ISD::AND &&
14620 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14621 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14622 if (C && C->getAPIntValue() == 1)
14623 Cond = Cond.getOperand(0);
14626 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14627 // setting operand in place of the X86ISD::SETCC.
14628 unsigned CondOpcode = Cond.getOpcode();
14629 if (CondOpcode == X86ISD::SETCC ||
14630 CondOpcode == X86ISD::SETCC_CARRY) {
14631 CC = Cond.getOperand(0);
14633 SDValue Cmp = Cond.getOperand(1);
14634 unsigned Opc = Cmp.getOpcode();
14635 MVT VT = Op.getSimpleValueType();
14637 bool IllegalFPCMov = false;
14638 if (VT.isFloatingPoint() && !VT.isVector() &&
14639 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14640 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14642 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14643 Opc == X86ISD::BT) { // FIXME
14647 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14648 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14649 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14650 Cond.getOperand(0).getValueType() != MVT::i8)) {
14651 SDValue LHS = Cond.getOperand(0);
14652 SDValue RHS = Cond.getOperand(1);
14653 unsigned X86Opcode;
14656 switch (CondOpcode) {
14657 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14658 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14659 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14660 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14661 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14662 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14663 default: llvm_unreachable("unexpected overflowing operator");
14665 if (CondOpcode == ISD::UMULO)
14666 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14669 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14671 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14673 if (CondOpcode == ISD::UMULO)
14674 Cond = X86Op.getValue(2);
14676 Cond = X86Op.getValue(1);
14678 CC = DAG.getConstant(X86Cond, MVT::i8);
14683 // Look pass the truncate if the high bits are known zero.
14684 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14685 Cond = Cond.getOperand(0);
14687 // We know the result of AND is compared against zero. Try to match
14689 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14690 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14691 if (NewSetCC.getNode()) {
14692 CC = NewSetCC.getOperand(0);
14693 Cond = NewSetCC.getOperand(1);
14700 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14701 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14704 // a < b ? -1 : 0 -> RES = ~setcc_carry
14705 // a < b ? 0 : -1 -> RES = setcc_carry
14706 // a >= b ? -1 : 0 -> RES = setcc_carry
14707 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14708 if (Cond.getOpcode() == X86ISD::SUB) {
14709 Cond = ConvertCmpIfNecessary(Cond, DAG);
14710 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14712 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14713 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14714 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14715 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14716 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14717 return DAG.getNOT(DL, Res, Res.getValueType());
14722 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14723 // widen the cmov and push the truncate through. This avoids introducing a new
14724 // branch during isel and doesn't add any extensions.
14725 if (Op.getValueType() == MVT::i8 &&
14726 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14727 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14728 if (T1.getValueType() == T2.getValueType() &&
14729 // Blacklist CopyFromReg to avoid partial register stalls.
14730 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14731 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14732 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14733 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14737 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14738 // condition is true.
14739 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14740 SDValue Ops[] = { Op2, Op1, CC, Cond };
14741 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14744 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14745 MVT VT = Op->getSimpleValueType(0);
14746 SDValue In = Op->getOperand(0);
14747 MVT InVT = In.getSimpleValueType();
14750 unsigned int NumElts = VT.getVectorNumElements();
14751 if (NumElts != 8 && NumElts != 16)
14754 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14755 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14757 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14758 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14760 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14761 Constant *C = ConstantInt::get(*DAG.getContext(),
14762 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14764 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14765 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14766 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14767 MachinePointerInfo::getConstantPool(),
14768 false, false, false, Alignment);
14769 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14770 if (VT.is512BitVector())
14772 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14775 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14776 SelectionDAG &DAG) {
14777 MVT VT = Op->getSimpleValueType(0);
14778 SDValue In = Op->getOperand(0);
14779 MVT InVT = In.getSimpleValueType();
14782 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14783 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14785 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14786 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14787 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14790 if (Subtarget->hasInt256())
14791 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14793 // Optimize vectors in AVX mode
14794 // Sign extend v8i16 to v8i32 and
14797 // Divide input vector into two parts
14798 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14799 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14800 // concat the vectors to original VT
14802 unsigned NumElems = InVT.getVectorNumElements();
14803 SDValue Undef = DAG.getUNDEF(InVT);
14805 SmallVector<int,8> ShufMask1(NumElems, -1);
14806 for (unsigned i = 0; i != NumElems/2; ++i)
14809 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14811 SmallVector<int,8> ShufMask2(NumElems, -1);
14812 for (unsigned i = 0; i != NumElems/2; ++i)
14813 ShufMask2[i] = i + NumElems/2;
14815 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14817 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14818 VT.getVectorNumElements()/2);
14820 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14821 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14823 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14826 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14827 // may emit an illegal shuffle but the expansion is still better than scalar
14828 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14829 // we'll emit a shuffle and a arithmetic shift.
14830 // TODO: It is possible to support ZExt by zeroing the undef values during
14831 // the shuffle phase or after the shuffle.
14832 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14833 SelectionDAG &DAG) {
14834 MVT RegVT = Op.getSimpleValueType();
14835 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14836 assert(RegVT.isInteger() &&
14837 "We only custom lower integer vector sext loads.");
14839 // Nothing useful we can do without SSE2 shuffles.
14840 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14842 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14844 EVT MemVT = Ld->getMemoryVT();
14845 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14846 unsigned RegSz = RegVT.getSizeInBits();
14848 ISD::LoadExtType Ext = Ld->getExtensionType();
14850 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14851 && "Only anyext and sext are currently implemented.");
14852 assert(MemVT != RegVT && "Cannot extend to the same type");
14853 assert(MemVT.isVector() && "Must load a vector from memory");
14855 unsigned NumElems = RegVT.getVectorNumElements();
14856 unsigned MemSz = MemVT.getSizeInBits();
14857 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14859 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14860 // The only way in which we have a legal 256-bit vector result but not the
14861 // integer 256-bit operations needed to directly lower a sextload is if we
14862 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14863 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14864 // correctly legalized. We do this late to allow the canonical form of
14865 // sextload to persist throughout the rest of the DAG combiner -- it wants
14866 // to fold together any extensions it can, and so will fuse a sign_extend
14867 // of an sextload into a sextload targeting a wider value.
14869 if (MemSz == 128) {
14870 // Just switch this to a normal load.
14871 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14872 "it must be a legal 128-bit vector "
14874 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14875 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14876 Ld->isInvariant(), Ld->getAlignment());
14878 assert(MemSz < 128 &&
14879 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14880 // Do an sext load to a 128-bit vector type. We want to use the same
14881 // number of elements, but elements half as wide. This will end up being
14882 // recursively lowered by this routine, but will succeed as we definitely
14883 // have all the necessary features if we're using AVX1.
14885 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14886 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14888 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14889 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14890 Ld->isNonTemporal(), Ld->isInvariant(),
14891 Ld->getAlignment());
14894 // Replace chain users with the new chain.
14895 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14896 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14898 // Finally, do a normal sign-extend to the desired register.
14899 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14902 // All sizes must be a power of two.
14903 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14904 "Non-power-of-two elements are not custom lowered!");
14906 // Attempt to load the original value using scalar loads.
14907 // Find the largest scalar type that divides the total loaded size.
14908 MVT SclrLoadTy = MVT::i8;
14909 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14910 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14911 MVT Tp = (MVT::SimpleValueType)tp;
14912 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14917 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14918 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14920 SclrLoadTy = MVT::f64;
14922 // Calculate the number of scalar loads that we need to perform
14923 // in order to load our vector from memory.
14924 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14926 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14927 "Can only lower sext loads with a single scalar load!");
14929 unsigned loadRegZize = RegSz;
14930 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14933 // Represent our vector as a sequence of elements which are the
14934 // largest scalar that we can load.
14935 EVT LoadUnitVecVT = EVT::getVectorVT(
14936 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14938 // Represent the data using the same element type that is stored in
14939 // memory. In practice, we ''widen'' MemVT.
14941 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14942 loadRegZize / MemVT.getScalarType().getSizeInBits());
14944 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14945 "Invalid vector type");
14947 // We can't shuffle using an illegal type.
14948 assert(TLI.isTypeLegal(WideVecVT) &&
14949 "We only lower types that form legal widened vector types");
14951 SmallVector<SDValue, 8> Chains;
14952 SDValue Ptr = Ld->getBasePtr();
14953 SDValue Increment =
14954 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14955 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14957 for (unsigned i = 0; i < NumLoads; ++i) {
14958 // Perform a single load.
14959 SDValue ScalarLoad =
14960 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14961 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14962 Ld->getAlignment());
14963 Chains.push_back(ScalarLoad.getValue(1));
14964 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14965 // another round of DAGCombining.
14967 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14969 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14970 ScalarLoad, DAG.getIntPtrConstant(i));
14972 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14975 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14977 // Bitcast the loaded value to a vector of the original element type, in
14978 // the size of the target vector type.
14979 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14980 unsigned SizeRatio = RegSz / MemSz;
14982 if (Ext == ISD::SEXTLOAD) {
14983 // If we have SSE4.1, we can directly emit a VSEXT node.
14984 if (Subtarget->hasSSE41()) {
14985 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14986 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14990 // Otherwise we'll shuffle the small elements in the high bits of the
14991 // larger type and perform an arithmetic shift. If the shift is not legal
14992 // it's better to scalarize.
14993 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14994 "We can't implement a sext load without an arithmetic right shift!");
14996 // Redistribute the loaded elements into the different locations.
14997 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14998 for (unsigned i = 0; i != NumElems; ++i)
14999 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15001 SDValue Shuff = DAG.getVectorShuffle(
15002 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15004 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15006 // Build the arithmetic shift.
15007 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15008 MemVT.getVectorElementType().getSizeInBits();
15010 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15012 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15016 // Redistribute the loaded elements into the different locations.
15017 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15018 for (unsigned i = 0; i != NumElems; ++i)
15019 ShuffleVec[i * SizeRatio] = i;
15021 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15022 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15024 // Bitcast to the requested type.
15025 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15026 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15030 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15031 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15032 // from the AND / OR.
15033 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15034 Opc = Op.getOpcode();
15035 if (Opc != ISD::OR && Opc != ISD::AND)
15037 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15038 Op.getOperand(0).hasOneUse() &&
15039 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15040 Op.getOperand(1).hasOneUse());
15043 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15044 // 1 and that the SETCC node has a single use.
15045 static bool isXor1OfSetCC(SDValue Op) {
15046 if (Op.getOpcode() != ISD::XOR)
15048 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15049 if (N1C && N1C->getAPIntValue() == 1) {
15050 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15051 Op.getOperand(0).hasOneUse();
15056 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15057 bool addTest = true;
15058 SDValue Chain = Op.getOperand(0);
15059 SDValue Cond = Op.getOperand(1);
15060 SDValue Dest = Op.getOperand(2);
15063 bool Inverted = false;
15065 if (Cond.getOpcode() == ISD::SETCC) {
15066 // Check for setcc([su]{add,sub,mul}o == 0).
15067 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15068 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15069 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15070 Cond.getOperand(0).getResNo() == 1 &&
15071 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15072 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15073 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15074 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15075 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15076 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15078 Cond = Cond.getOperand(0);
15080 SDValue NewCond = LowerSETCC(Cond, DAG);
15081 if (NewCond.getNode())
15086 // FIXME: LowerXALUO doesn't handle these!!
15087 else if (Cond.getOpcode() == X86ISD::ADD ||
15088 Cond.getOpcode() == X86ISD::SUB ||
15089 Cond.getOpcode() == X86ISD::SMUL ||
15090 Cond.getOpcode() == X86ISD::UMUL)
15091 Cond = LowerXALUO(Cond, DAG);
15094 // Look pass (and (setcc_carry (cmp ...)), 1).
15095 if (Cond.getOpcode() == ISD::AND &&
15096 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15097 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15098 if (C && C->getAPIntValue() == 1)
15099 Cond = Cond.getOperand(0);
15102 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15103 // setting operand in place of the X86ISD::SETCC.
15104 unsigned CondOpcode = Cond.getOpcode();
15105 if (CondOpcode == X86ISD::SETCC ||
15106 CondOpcode == X86ISD::SETCC_CARRY) {
15107 CC = Cond.getOperand(0);
15109 SDValue Cmp = Cond.getOperand(1);
15110 unsigned Opc = Cmp.getOpcode();
15111 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15112 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15116 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15120 // These can only come from an arithmetic instruction with overflow,
15121 // e.g. SADDO, UADDO.
15122 Cond = Cond.getNode()->getOperand(1);
15128 CondOpcode = Cond.getOpcode();
15129 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15130 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15131 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15132 Cond.getOperand(0).getValueType() != MVT::i8)) {
15133 SDValue LHS = Cond.getOperand(0);
15134 SDValue RHS = Cond.getOperand(1);
15135 unsigned X86Opcode;
15138 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15139 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15141 switch (CondOpcode) {
15142 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15144 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15146 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15149 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15150 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15154 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15157 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15158 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15159 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15160 default: llvm_unreachable("unexpected overflowing operator");
15163 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15164 if (CondOpcode == ISD::UMULO)
15165 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15168 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15170 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15172 if (CondOpcode == ISD::UMULO)
15173 Cond = X86Op.getValue(2);
15175 Cond = X86Op.getValue(1);
15177 CC = DAG.getConstant(X86Cond, MVT::i8);
15181 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15182 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15183 if (CondOpc == ISD::OR) {
15184 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15185 // two branches instead of an explicit OR instruction with a
15187 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15188 isX86LogicalCmp(Cmp)) {
15189 CC = Cond.getOperand(0).getOperand(0);
15190 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15191 Chain, Dest, CC, Cmp);
15192 CC = Cond.getOperand(1).getOperand(0);
15196 } else { // ISD::AND
15197 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15198 // two branches instead of an explicit AND instruction with a
15199 // separate test. However, we only do this if this block doesn't
15200 // have a fall-through edge, because this requires an explicit
15201 // jmp when the condition is false.
15202 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15203 isX86LogicalCmp(Cmp) &&
15204 Op.getNode()->hasOneUse()) {
15205 X86::CondCode CCode =
15206 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15207 CCode = X86::GetOppositeBranchCondition(CCode);
15208 CC = DAG.getConstant(CCode, MVT::i8);
15209 SDNode *User = *Op.getNode()->use_begin();
15210 // Look for an unconditional branch following this conditional branch.
15211 // We need this because we need to reverse the successors in order
15212 // to implement FCMP_OEQ.
15213 if (User->getOpcode() == ISD::BR) {
15214 SDValue FalseBB = User->getOperand(1);
15216 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15217 assert(NewBR == User);
15221 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15222 Chain, Dest, CC, Cmp);
15223 X86::CondCode CCode =
15224 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15225 CCode = X86::GetOppositeBranchCondition(CCode);
15226 CC = DAG.getConstant(CCode, MVT::i8);
15232 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15233 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15234 // It should be transformed during dag combiner except when the condition
15235 // is set by a arithmetics with overflow node.
15236 X86::CondCode CCode =
15237 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15238 CCode = X86::GetOppositeBranchCondition(CCode);
15239 CC = DAG.getConstant(CCode, MVT::i8);
15240 Cond = Cond.getOperand(0).getOperand(1);
15242 } else if (Cond.getOpcode() == ISD::SETCC &&
15243 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15244 // For FCMP_OEQ, we can emit
15245 // two branches instead of an explicit AND instruction with a
15246 // separate test. However, we only do this if this block doesn't
15247 // have a fall-through edge, because this requires an explicit
15248 // jmp when the condition is false.
15249 if (Op.getNode()->hasOneUse()) {
15250 SDNode *User = *Op.getNode()->use_begin();
15251 // Look for an unconditional branch following this conditional branch.
15252 // We need this because we need to reverse the successors in order
15253 // to implement FCMP_OEQ.
15254 if (User->getOpcode() == ISD::BR) {
15255 SDValue FalseBB = User->getOperand(1);
15257 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15258 assert(NewBR == User);
15262 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15263 Cond.getOperand(0), Cond.getOperand(1));
15264 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15265 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15266 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15267 Chain, Dest, CC, Cmp);
15268 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15273 } else if (Cond.getOpcode() == ISD::SETCC &&
15274 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15275 // For FCMP_UNE, we can emit
15276 // two branches instead of an explicit AND instruction with a
15277 // separate test. However, we only do this if this block doesn't
15278 // have a fall-through edge, because this requires an explicit
15279 // jmp when the condition is false.
15280 if (Op.getNode()->hasOneUse()) {
15281 SDNode *User = *Op.getNode()->use_begin();
15282 // Look for an unconditional branch following this conditional branch.
15283 // We need this because we need to reverse the successors in order
15284 // to implement FCMP_UNE.
15285 if (User->getOpcode() == ISD::BR) {
15286 SDValue FalseBB = User->getOperand(1);
15288 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15289 assert(NewBR == User);
15292 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15293 Cond.getOperand(0), Cond.getOperand(1));
15294 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15295 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15296 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15297 Chain, Dest, CC, Cmp);
15298 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15308 // Look pass the truncate if the high bits are known zero.
15309 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15310 Cond = Cond.getOperand(0);
15312 // We know the result of AND is compared against zero. Try to match
15314 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15315 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15316 if (NewSetCC.getNode()) {
15317 CC = NewSetCC.getOperand(0);
15318 Cond = NewSetCC.getOperand(1);
15325 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15326 CC = DAG.getConstant(X86Cond, MVT::i8);
15327 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15329 Cond = ConvertCmpIfNecessary(Cond, DAG);
15330 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15331 Chain, Dest, CC, Cond);
15334 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15335 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15336 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15337 // that the guard pages used by the OS virtual memory manager are allocated in
15338 // correct sequence.
15340 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15341 SelectionDAG &DAG) const {
15342 MachineFunction &MF = DAG.getMachineFunction();
15343 bool SplitStack = MF.shouldSplitStack();
15344 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15349 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15350 SDNode* Node = Op.getNode();
15352 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15353 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15354 " not tell us which reg is the stack pointer!");
15355 EVT VT = Node->getValueType(0);
15356 SDValue Tmp1 = SDValue(Node, 0);
15357 SDValue Tmp2 = SDValue(Node, 1);
15358 SDValue Tmp3 = Node->getOperand(2);
15359 SDValue Chain = Tmp1.getOperand(0);
15361 // Chain the dynamic stack allocation so that it doesn't modify the stack
15362 // pointer when other instructions are using the stack.
15363 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15366 SDValue Size = Tmp2.getOperand(1);
15367 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15368 Chain = SP.getValue(1);
15369 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15370 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15371 unsigned StackAlign = TFI.getStackAlignment();
15372 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15373 if (Align > StackAlign)
15374 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15375 DAG.getConstant(-(uint64_t)Align, VT));
15376 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15378 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15379 DAG.getIntPtrConstant(0, true), SDValue(),
15382 SDValue Ops[2] = { Tmp1, Tmp2 };
15383 return DAG.getMergeValues(Ops, dl);
15387 SDValue Chain = Op.getOperand(0);
15388 SDValue Size = Op.getOperand(1);
15389 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15390 EVT VT = Op.getNode()->getValueType(0);
15392 bool Is64Bit = Subtarget->is64Bit();
15393 EVT SPTy = getPointerTy();
15396 MachineRegisterInfo &MRI = MF.getRegInfo();
15399 // The 64 bit implementation of segmented stacks needs to clobber both r10
15400 // r11. This makes it impossible to use it along with nested parameters.
15401 const Function *F = MF.getFunction();
15403 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15405 if (I->hasNestAttr())
15406 report_fatal_error("Cannot use segmented stacks with functions that "
15407 "have nested arguments.");
15410 const TargetRegisterClass *AddrRegClass =
15411 getRegClassFor(getPointerTy());
15412 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15413 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15414 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15415 DAG.getRegister(Vreg, SPTy));
15416 SDValue Ops1[2] = { Value, Chain };
15417 return DAG.getMergeValues(Ops1, dl);
15420 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15422 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15423 Flag = Chain.getValue(1);
15424 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15426 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15428 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15429 DAG.getSubtarget().getRegisterInfo());
15430 unsigned SPReg = RegInfo->getStackRegister();
15431 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15432 Chain = SP.getValue(1);
15435 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15436 DAG.getConstant(-(uint64_t)Align, VT));
15437 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15440 SDValue Ops1[2] = { SP, Chain };
15441 return DAG.getMergeValues(Ops1, dl);
15445 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15446 MachineFunction &MF = DAG.getMachineFunction();
15447 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15449 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15452 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15453 // vastart just stores the address of the VarArgsFrameIndex slot into the
15454 // memory location argument.
15455 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15457 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15458 MachinePointerInfo(SV), false, false, 0);
15462 // gp_offset (0 - 6 * 8)
15463 // fp_offset (48 - 48 + 8 * 16)
15464 // overflow_arg_area (point to parameters coming in memory).
15466 SmallVector<SDValue, 8> MemOps;
15467 SDValue FIN = Op.getOperand(1);
15469 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15470 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15472 FIN, MachinePointerInfo(SV), false, false, 0);
15473 MemOps.push_back(Store);
15476 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15477 FIN, DAG.getIntPtrConstant(4));
15478 Store = DAG.getStore(Op.getOperand(0), DL,
15479 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15481 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15482 MemOps.push_back(Store);
15484 // Store ptr to overflow_arg_area
15485 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15486 FIN, DAG.getIntPtrConstant(4));
15487 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15489 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15490 MachinePointerInfo(SV, 8),
15492 MemOps.push_back(Store);
15494 // Store ptr to reg_save_area.
15495 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15496 FIN, DAG.getIntPtrConstant(8));
15497 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15499 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15500 MachinePointerInfo(SV, 16), false, false, 0);
15501 MemOps.push_back(Store);
15502 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15505 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15506 assert(Subtarget->is64Bit() &&
15507 "LowerVAARG only handles 64-bit va_arg!");
15508 assert((Subtarget->isTargetLinux() ||
15509 Subtarget->isTargetDarwin()) &&
15510 "Unhandled target in LowerVAARG");
15511 assert(Op.getNode()->getNumOperands() == 4);
15512 SDValue Chain = Op.getOperand(0);
15513 SDValue SrcPtr = Op.getOperand(1);
15514 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15515 unsigned Align = Op.getConstantOperandVal(3);
15518 EVT ArgVT = Op.getNode()->getValueType(0);
15519 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15520 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15523 // Decide which area this value should be read from.
15524 // TODO: Implement the AMD64 ABI in its entirety. This simple
15525 // selection mechanism works only for the basic types.
15526 if (ArgVT == MVT::f80) {
15527 llvm_unreachable("va_arg for f80 not yet implemented");
15528 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15529 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15530 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15531 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15533 llvm_unreachable("Unhandled argument type in LowerVAARG");
15536 if (ArgMode == 2) {
15537 // Sanity Check: Make sure using fp_offset makes sense.
15538 assert(!DAG.getTarget().Options.UseSoftFloat &&
15539 !(DAG.getMachineFunction()
15540 .getFunction()->getAttributes()
15541 .hasAttribute(AttributeSet::FunctionIndex,
15542 Attribute::NoImplicitFloat)) &&
15543 Subtarget->hasSSE1());
15546 // Insert VAARG_64 node into the DAG
15547 // VAARG_64 returns two values: Variable Argument Address, Chain
15548 SmallVector<SDValue, 11> InstOps;
15549 InstOps.push_back(Chain);
15550 InstOps.push_back(SrcPtr);
15551 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15552 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15553 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15554 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15555 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15556 VTs, InstOps, MVT::i64,
15557 MachinePointerInfo(SV),
15559 /*Volatile=*/false,
15561 /*WriteMem=*/true);
15562 Chain = VAARG.getValue(1);
15564 // Load the next argument and return it
15565 return DAG.getLoad(ArgVT, dl,
15568 MachinePointerInfo(),
15569 false, false, false, 0);
15572 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15573 SelectionDAG &DAG) {
15574 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15575 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15576 SDValue Chain = Op.getOperand(0);
15577 SDValue DstPtr = Op.getOperand(1);
15578 SDValue SrcPtr = Op.getOperand(2);
15579 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15580 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15583 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15584 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15586 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15589 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15590 // amount is a constant. Takes immediate version of shift as input.
15591 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15592 SDValue SrcOp, uint64_t ShiftAmt,
15593 SelectionDAG &DAG) {
15594 MVT ElementType = VT.getVectorElementType();
15596 // Fold this packed shift into its first operand if ShiftAmt is 0.
15600 // Check for ShiftAmt >= element width
15601 if (ShiftAmt >= ElementType.getSizeInBits()) {
15602 if (Opc == X86ISD::VSRAI)
15603 ShiftAmt = ElementType.getSizeInBits() - 1;
15605 return DAG.getConstant(0, VT);
15608 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15609 && "Unknown target vector shift-by-constant node");
15611 // Fold this packed vector shift into a build vector if SrcOp is a
15612 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15613 if (VT == SrcOp.getSimpleValueType() &&
15614 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15615 SmallVector<SDValue, 8> Elts;
15616 unsigned NumElts = SrcOp->getNumOperands();
15617 ConstantSDNode *ND;
15620 default: llvm_unreachable(nullptr);
15621 case X86ISD::VSHLI:
15622 for (unsigned i=0; i!=NumElts; ++i) {
15623 SDValue CurrentOp = SrcOp->getOperand(i);
15624 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15625 Elts.push_back(CurrentOp);
15628 ND = cast<ConstantSDNode>(CurrentOp);
15629 const APInt &C = ND->getAPIntValue();
15630 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15633 case X86ISD::VSRLI:
15634 for (unsigned i=0; i!=NumElts; ++i) {
15635 SDValue CurrentOp = SrcOp->getOperand(i);
15636 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15637 Elts.push_back(CurrentOp);
15640 ND = cast<ConstantSDNode>(CurrentOp);
15641 const APInt &C = ND->getAPIntValue();
15642 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15645 case X86ISD::VSRAI:
15646 for (unsigned i=0; i!=NumElts; ++i) {
15647 SDValue CurrentOp = SrcOp->getOperand(i);
15648 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15649 Elts.push_back(CurrentOp);
15652 ND = cast<ConstantSDNode>(CurrentOp);
15653 const APInt &C = ND->getAPIntValue();
15654 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15659 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15662 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15665 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15666 // may or may not be a constant. Takes immediate version of shift as input.
15667 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15668 SDValue SrcOp, SDValue ShAmt,
15669 SelectionDAG &DAG) {
15670 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15672 // Catch shift-by-constant.
15673 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15674 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15675 CShAmt->getZExtValue(), DAG);
15677 // Change opcode to non-immediate version
15679 default: llvm_unreachable("Unknown target vector shift node");
15680 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15681 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15682 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15685 // Need to build a vector containing shift amount
15686 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15689 ShOps[1] = DAG.getConstant(0, MVT::i32);
15690 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15691 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15693 // The return type has to be a 128-bit type with the same element
15694 // type as the input type.
15695 MVT EltVT = VT.getVectorElementType();
15696 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15698 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15699 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15702 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15703 /// necessary casting for \p Mask when lowering masking intrinsics.
15704 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15705 SDValue PreservedSrc, SelectionDAG &DAG) {
15706 EVT VT = Op.getValueType();
15707 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15708 MVT::i1, VT.getVectorNumElements());
15711 assert(MaskVT.isSimple() && "invalid mask type");
15712 return DAG.getNode(ISD::VSELECT, dl, VT,
15713 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15717 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15719 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15720 case Intrinsic::x86_fma_vfmadd_ps:
15721 case Intrinsic::x86_fma_vfmadd_pd:
15722 case Intrinsic::x86_fma_vfmadd_ps_256:
15723 case Intrinsic::x86_fma_vfmadd_pd_256:
15724 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15725 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15726 return X86ISD::FMADD;
15727 case Intrinsic::x86_fma_vfmsub_ps:
15728 case Intrinsic::x86_fma_vfmsub_pd:
15729 case Intrinsic::x86_fma_vfmsub_ps_256:
15730 case Intrinsic::x86_fma_vfmsub_pd_256:
15731 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15732 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15733 return X86ISD::FMSUB;
15734 case Intrinsic::x86_fma_vfnmadd_ps:
15735 case Intrinsic::x86_fma_vfnmadd_pd:
15736 case Intrinsic::x86_fma_vfnmadd_ps_256:
15737 case Intrinsic::x86_fma_vfnmadd_pd_256:
15738 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15739 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15740 return X86ISD::FNMADD;
15741 case Intrinsic::x86_fma_vfnmsub_ps:
15742 case Intrinsic::x86_fma_vfnmsub_pd:
15743 case Intrinsic::x86_fma_vfnmsub_ps_256:
15744 case Intrinsic::x86_fma_vfnmsub_pd_256:
15745 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15746 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15747 return X86ISD::FNMSUB;
15748 case Intrinsic::x86_fma_vfmaddsub_ps:
15749 case Intrinsic::x86_fma_vfmaddsub_pd:
15750 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15751 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15752 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15753 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15754 return X86ISD::FMADDSUB;
15755 case Intrinsic::x86_fma_vfmsubadd_ps:
15756 case Intrinsic::x86_fma_vfmsubadd_pd:
15757 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15758 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15759 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15760 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15761 return X86ISD::FMSUBADD;
15765 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15767 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15769 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15771 switch(IntrData->Type) {
15772 case INTR_TYPE_1OP:
15773 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15774 case INTR_TYPE_2OP:
15775 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15777 case INTR_TYPE_3OP:
15778 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15779 Op.getOperand(2), Op.getOperand(3));
15780 case COMI: { // Comparison intrinsics
15781 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15782 SDValue LHS = Op.getOperand(1);
15783 SDValue RHS = Op.getOperand(2);
15784 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15785 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15786 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15787 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15788 DAG.getConstant(X86CC, MVT::i8), Cond);
15789 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15792 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15793 Op.getOperand(1), Op.getOperand(2), DAG);
15800 default: return SDValue(); // Don't custom lower most intrinsics.
15802 // Arithmetic intrinsics.
15803 case Intrinsic::x86_sse2_pmulu_dq:
15804 case Intrinsic::x86_avx2_pmulu_dq:
15805 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15806 Op.getOperand(1), Op.getOperand(2));
15808 case Intrinsic::x86_sse41_pmuldq:
15809 case Intrinsic::x86_avx2_pmul_dq:
15810 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15811 Op.getOperand(1), Op.getOperand(2));
15813 case Intrinsic::x86_sse2_pmulhu_w:
15814 case Intrinsic::x86_avx2_pmulhu_w:
15815 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15816 Op.getOperand(1), Op.getOperand(2));
15818 case Intrinsic::x86_sse2_pmulh_w:
15819 case Intrinsic::x86_avx2_pmulh_w:
15820 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15821 Op.getOperand(1), Op.getOperand(2));
15823 // SSE/SSE2/AVX floating point max/min intrinsics.
15824 case Intrinsic::x86_sse_max_ps:
15825 case Intrinsic::x86_sse2_max_pd:
15826 case Intrinsic::x86_avx_max_ps_256:
15827 case Intrinsic::x86_avx_max_pd_256:
15828 case Intrinsic::x86_sse_min_ps:
15829 case Intrinsic::x86_sse2_min_pd:
15830 case Intrinsic::x86_avx_min_ps_256:
15831 case Intrinsic::x86_avx_min_pd_256: {
15834 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15835 case Intrinsic::x86_sse_max_ps:
15836 case Intrinsic::x86_sse2_max_pd:
15837 case Intrinsic::x86_avx_max_ps_256:
15838 case Intrinsic::x86_avx_max_pd_256:
15839 Opcode = X86ISD::FMAX;
15841 case Intrinsic::x86_sse_min_ps:
15842 case Intrinsic::x86_sse2_min_pd:
15843 case Intrinsic::x86_avx_min_ps_256:
15844 case Intrinsic::x86_avx_min_pd_256:
15845 Opcode = X86ISD::FMIN;
15848 return DAG.getNode(Opcode, dl, Op.getValueType(),
15849 Op.getOperand(1), Op.getOperand(2));
15852 // AVX2 variable shift intrinsics
15853 case Intrinsic::x86_avx2_psllv_d:
15854 case Intrinsic::x86_avx2_psllv_q:
15855 case Intrinsic::x86_avx2_psllv_d_256:
15856 case Intrinsic::x86_avx2_psllv_q_256:
15857 case Intrinsic::x86_avx2_psrlv_d:
15858 case Intrinsic::x86_avx2_psrlv_q:
15859 case Intrinsic::x86_avx2_psrlv_d_256:
15860 case Intrinsic::x86_avx2_psrlv_q_256:
15861 case Intrinsic::x86_avx2_psrav_d:
15862 case Intrinsic::x86_avx2_psrav_d_256: {
15865 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15866 case Intrinsic::x86_avx2_psllv_d:
15867 case Intrinsic::x86_avx2_psllv_q:
15868 case Intrinsic::x86_avx2_psllv_d_256:
15869 case Intrinsic::x86_avx2_psllv_q_256:
15872 case Intrinsic::x86_avx2_psrlv_d:
15873 case Intrinsic::x86_avx2_psrlv_q:
15874 case Intrinsic::x86_avx2_psrlv_d_256:
15875 case Intrinsic::x86_avx2_psrlv_q_256:
15878 case Intrinsic::x86_avx2_psrav_d:
15879 case Intrinsic::x86_avx2_psrav_d_256:
15883 return DAG.getNode(Opcode, dl, Op.getValueType(),
15884 Op.getOperand(1), Op.getOperand(2));
15887 case Intrinsic::x86_sse2_packssdw_128:
15888 case Intrinsic::x86_sse2_packsswb_128:
15889 case Intrinsic::x86_avx2_packssdw:
15890 case Intrinsic::x86_avx2_packsswb:
15891 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15892 Op.getOperand(1), Op.getOperand(2));
15894 case Intrinsic::x86_sse2_packuswb_128:
15895 case Intrinsic::x86_sse41_packusdw:
15896 case Intrinsic::x86_avx2_packuswb:
15897 case Intrinsic::x86_avx2_packusdw:
15898 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15899 Op.getOperand(1), Op.getOperand(2));
15901 case Intrinsic::x86_ssse3_pshuf_b_128:
15902 case Intrinsic::x86_avx2_pshuf_b:
15903 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15904 Op.getOperand(1), Op.getOperand(2));
15906 case Intrinsic::x86_sse2_pshuf_d:
15907 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15908 Op.getOperand(1), Op.getOperand(2));
15910 case Intrinsic::x86_sse2_pshufl_w:
15911 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15912 Op.getOperand(1), Op.getOperand(2));
15914 case Intrinsic::x86_sse2_pshufh_w:
15915 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15916 Op.getOperand(1), Op.getOperand(2));
15918 case Intrinsic::x86_ssse3_psign_b_128:
15919 case Intrinsic::x86_ssse3_psign_w_128:
15920 case Intrinsic::x86_ssse3_psign_d_128:
15921 case Intrinsic::x86_avx2_psign_b:
15922 case Intrinsic::x86_avx2_psign_w:
15923 case Intrinsic::x86_avx2_psign_d:
15924 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15925 Op.getOperand(1), Op.getOperand(2));
15927 case Intrinsic::x86_avx2_permd:
15928 case Intrinsic::x86_avx2_permps:
15929 // Operands intentionally swapped. Mask is last operand to intrinsic,
15930 // but second operand for node/instruction.
15931 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15932 Op.getOperand(2), Op.getOperand(1));
15934 case Intrinsic::x86_avx512_mask_valign_q_512:
15935 case Intrinsic::x86_avx512_mask_valign_d_512:
15936 // Vector source operands are swapped.
15937 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15938 Op.getValueType(), Op.getOperand(2),
15941 Op.getOperand(5), Op.getOperand(4), DAG);
15943 // ptest and testp intrinsics. The intrinsic these come from are designed to
15944 // return an integer value, not just an instruction so lower it to the ptest
15945 // or testp pattern and a setcc for the result.
15946 case Intrinsic::x86_sse41_ptestz:
15947 case Intrinsic::x86_sse41_ptestc:
15948 case Intrinsic::x86_sse41_ptestnzc:
15949 case Intrinsic::x86_avx_ptestz_256:
15950 case Intrinsic::x86_avx_ptestc_256:
15951 case Intrinsic::x86_avx_ptestnzc_256:
15952 case Intrinsic::x86_avx_vtestz_ps:
15953 case Intrinsic::x86_avx_vtestc_ps:
15954 case Intrinsic::x86_avx_vtestnzc_ps:
15955 case Intrinsic::x86_avx_vtestz_pd:
15956 case Intrinsic::x86_avx_vtestc_pd:
15957 case Intrinsic::x86_avx_vtestnzc_pd:
15958 case Intrinsic::x86_avx_vtestz_ps_256:
15959 case Intrinsic::x86_avx_vtestc_ps_256:
15960 case Intrinsic::x86_avx_vtestnzc_ps_256:
15961 case Intrinsic::x86_avx_vtestz_pd_256:
15962 case Intrinsic::x86_avx_vtestc_pd_256:
15963 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15964 bool IsTestPacked = false;
15967 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15968 case Intrinsic::x86_avx_vtestz_ps:
15969 case Intrinsic::x86_avx_vtestz_pd:
15970 case Intrinsic::x86_avx_vtestz_ps_256:
15971 case Intrinsic::x86_avx_vtestz_pd_256:
15972 IsTestPacked = true; // Fallthrough
15973 case Intrinsic::x86_sse41_ptestz:
15974 case Intrinsic::x86_avx_ptestz_256:
15976 X86CC = X86::COND_E;
15978 case Intrinsic::x86_avx_vtestc_ps:
15979 case Intrinsic::x86_avx_vtestc_pd:
15980 case Intrinsic::x86_avx_vtestc_ps_256:
15981 case Intrinsic::x86_avx_vtestc_pd_256:
15982 IsTestPacked = true; // Fallthrough
15983 case Intrinsic::x86_sse41_ptestc:
15984 case Intrinsic::x86_avx_ptestc_256:
15986 X86CC = X86::COND_B;
15988 case Intrinsic::x86_avx_vtestnzc_ps:
15989 case Intrinsic::x86_avx_vtestnzc_pd:
15990 case Intrinsic::x86_avx_vtestnzc_ps_256:
15991 case Intrinsic::x86_avx_vtestnzc_pd_256:
15992 IsTestPacked = true; // Fallthrough
15993 case Intrinsic::x86_sse41_ptestnzc:
15994 case Intrinsic::x86_avx_ptestnzc_256:
15996 X86CC = X86::COND_A;
16000 SDValue LHS = Op.getOperand(1);
16001 SDValue RHS = Op.getOperand(2);
16002 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16003 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16004 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16005 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16006 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16008 case Intrinsic::x86_avx512_kortestz_w:
16009 case Intrinsic::x86_avx512_kortestc_w: {
16010 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16011 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16012 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16013 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16014 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16015 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16016 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16019 case Intrinsic::x86_sse42_pcmpistria128:
16020 case Intrinsic::x86_sse42_pcmpestria128:
16021 case Intrinsic::x86_sse42_pcmpistric128:
16022 case Intrinsic::x86_sse42_pcmpestric128:
16023 case Intrinsic::x86_sse42_pcmpistrio128:
16024 case Intrinsic::x86_sse42_pcmpestrio128:
16025 case Intrinsic::x86_sse42_pcmpistris128:
16026 case Intrinsic::x86_sse42_pcmpestris128:
16027 case Intrinsic::x86_sse42_pcmpistriz128:
16028 case Intrinsic::x86_sse42_pcmpestriz128: {
16032 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16033 case Intrinsic::x86_sse42_pcmpistria128:
16034 Opcode = X86ISD::PCMPISTRI;
16035 X86CC = X86::COND_A;
16037 case Intrinsic::x86_sse42_pcmpestria128:
16038 Opcode = X86ISD::PCMPESTRI;
16039 X86CC = X86::COND_A;
16041 case Intrinsic::x86_sse42_pcmpistric128:
16042 Opcode = X86ISD::PCMPISTRI;
16043 X86CC = X86::COND_B;
16045 case Intrinsic::x86_sse42_pcmpestric128:
16046 Opcode = X86ISD::PCMPESTRI;
16047 X86CC = X86::COND_B;
16049 case Intrinsic::x86_sse42_pcmpistrio128:
16050 Opcode = X86ISD::PCMPISTRI;
16051 X86CC = X86::COND_O;
16053 case Intrinsic::x86_sse42_pcmpestrio128:
16054 Opcode = X86ISD::PCMPESTRI;
16055 X86CC = X86::COND_O;
16057 case Intrinsic::x86_sse42_pcmpistris128:
16058 Opcode = X86ISD::PCMPISTRI;
16059 X86CC = X86::COND_S;
16061 case Intrinsic::x86_sse42_pcmpestris128:
16062 Opcode = X86ISD::PCMPESTRI;
16063 X86CC = X86::COND_S;
16065 case Intrinsic::x86_sse42_pcmpistriz128:
16066 Opcode = X86ISD::PCMPISTRI;
16067 X86CC = X86::COND_E;
16069 case Intrinsic::x86_sse42_pcmpestriz128:
16070 Opcode = X86ISD::PCMPESTRI;
16071 X86CC = X86::COND_E;
16074 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16075 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16076 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16077 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16078 DAG.getConstant(X86CC, MVT::i8),
16079 SDValue(PCMP.getNode(), 1));
16080 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16083 case Intrinsic::x86_sse42_pcmpistri128:
16084 case Intrinsic::x86_sse42_pcmpestri128: {
16086 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16087 Opcode = X86ISD::PCMPISTRI;
16089 Opcode = X86ISD::PCMPESTRI;
16091 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16092 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16093 return DAG.getNode(Opcode, dl, VTs, NewOps);
16096 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16097 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16098 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16099 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16100 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16101 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16102 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16103 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16104 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16105 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16106 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16107 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16108 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16109 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16110 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16111 dl, Op.getValueType(),
16115 Op.getOperand(4), Op.getOperand(1), DAG);
16120 case Intrinsic::x86_fma_vfmadd_ps:
16121 case Intrinsic::x86_fma_vfmadd_pd:
16122 case Intrinsic::x86_fma_vfmsub_ps:
16123 case Intrinsic::x86_fma_vfmsub_pd:
16124 case Intrinsic::x86_fma_vfnmadd_ps:
16125 case Intrinsic::x86_fma_vfnmadd_pd:
16126 case Intrinsic::x86_fma_vfnmsub_ps:
16127 case Intrinsic::x86_fma_vfnmsub_pd:
16128 case Intrinsic::x86_fma_vfmaddsub_ps:
16129 case Intrinsic::x86_fma_vfmaddsub_pd:
16130 case Intrinsic::x86_fma_vfmsubadd_ps:
16131 case Intrinsic::x86_fma_vfmsubadd_pd:
16132 case Intrinsic::x86_fma_vfmadd_ps_256:
16133 case Intrinsic::x86_fma_vfmadd_pd_256:
16134 case Intrinsic::x86_fma_vfmsub_ps_256:
16135 case Intrinsic::x86_fma_vfmsub_pd_256:
16136 case Intrinsic::x86_fma_vfnmadd_ps_256:
16137 case Intrinsic::x86_fma_vfnmadd_pd_256:
16138 case Intrinsic::x86_fma_vfnmsub_ps_256:
16139 case Intrinsic::x86_fma_vfnmsub_pd_256:
16140 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16141 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16142 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16143 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16144 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16145 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16149 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16150 SDValue Src, SDValue Mask, SDValue Base,
16151 SDValue Index, SDValue ScaleOp, SDValue Chain,
16152 const X86Subtarget * Subtarget) {
16154 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16155 assert(C && "Invalid scale type");
16156 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16157 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16158 Index.getSimpleValueType().getVectorNumElements());
16160 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16162 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16164 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16165 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16166 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16167 SDValue Segment = DAG.getRegister(0, MVT::i32);
16168 if (Src.getOpcode() == ISD::UNDEF)
16169 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16170 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16171 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16172 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16173 return DAG.getMergeValues(RetOps, dl);
16176 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16177 SDValue Src, SDValue Mask, SDValue Base,
16178 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16180 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16181 assert(C && "Invalid scale type");
16182 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16183 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16184 SDValue Segment = DAG.getRegister(0, MVT::i32);
16185 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16186 Index.getSimpleValueType().getVectorNumElements());
16188 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16190 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16192 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16193 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16194 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16195 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16196 return SDValue(Res, 1);
16199 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16200 SDValue Mask, SDValue Base, SDValue Index,
16201 SDValue ScaleOp, SDValue Chain) {
16203 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16204 assert(C && "Invalid scale type");
16205 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16206 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16207 SDValue Segment = DAG.getRegister(0, MVT::i32);
16209 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16211 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16213 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16215 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16216 //SDVTList VTs = DAG.getVTList(MVT::Other);
16217 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16218 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16219 return SDValue(Res, 0);
16222 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16223 // read performance monitor counters (x86_rdpmc).
16224 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16225 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16226 SmallVectorImpl<SDValue> &Results) {
16227 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16228 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16231 // The ECX register is used to select the index of the performance counter
16233 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16235 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16237 // Reads the content of a 64-bit performance counter and returns it in the
16238 // registers EDX:EAX.
16239 if (Subtarget->is64Bit()) {
16240 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16241 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16244 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16245 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16248 Chain = HI.getValue(1);
16250 if (Subtarget->is64Bit()) {
16251 // The EAX register is loaded with the low-order 32 bits. The EDX register
16252 // is loaded with the supported high-order bits of the counter.
16253 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16254 DAG.getConstant(32, MVT::i8));
16255 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16256 Results.push_back(Chain);
16260 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16261 SDValue Ops[] = { LO, HI };
16262 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16263 Results.push_back(Pair);
16264 Results.push_back(Chain);
16267 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16268 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16269 // also used to custom lower READCYCLECOUNTER nodes.
16270 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16271 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16272 SmallVectorImpl<SDValue> &Results) {
16273 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16274 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16277 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16278 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16279 // and the EAX register is loaded with the low-order 32 bits.
16280 if (Subtarget->is64Bit()) {
16281 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16282 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16285 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16286 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16289 SDValue Chain = HI.getValue(1);
16291 if (Opcode == X86ISD::RDTSCP_DAG) {
16292 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16294 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16295 // the ECX register. Add 'ecx' explicitly to the chain.
16296 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16298 // Explicitly store the content of ECX at the location passed in input
16299 // to the 'rdtscp' intrinsic.
16300 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16301 MachinePointerInfo(), false, false, 0);
16304 if (Subtarget->is64Bit()) {
16305 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16306 // the EAX register is loaded with the low-order 32 bits.
16307 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16308 DAG.getConstant(32, MVT::i8));
16309 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16310 Results.push_back(Chain);
16314 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16315 SDValue Ops[] = { LO, HI };
16316 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16317 Results.push_back(Pair);
16318 Results.push_back(Chain);
16321 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16322 SelectionDAG &DAG) {
16323 SmallVector<SDValue, 2> Results;
16325 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16327 return DAG.getMergeValues(Results, DL);
16331 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16332 SelectionDAG &DAG) {
16333 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16335 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16340 switch(IntrData->Type) {
16342 llvm_unreachable("Unknown Intrinsic Type");
16346 // Emit the node with the right value type.
16347 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16348 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16350 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16351 // Otherwise return the value from Rand, which is always 0, casted to i32.
16352 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16353 DAG.getConstant(1, Op->getValueType(1)),
16354 DAG.getConstant(X86::COND_B, MVT::i32),
16355 SDValue(Result.getNode(), 1) };
16356 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16357 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16360 // Return { result, isValid, chain }.
16361 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16362 SDValue(Result.getNode(), 2));
16365 //gather(v1, mask, index, base, scale);
16366 SDValue Chain = Op.getOperand(0);
16367 SDValue Src = Op.getOperand(2);
16368 SDValue Base = Op.getOperand(3);
16369 SDValue Index = Op.getOperand(4);
16370 SDValue Mask = Op.getOperand(5);
16371 SDValue Scale = Op.getOperand(6);
16372 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16376 //scatter(base, mask, index, v1, scale);
16377 SDValue Chain = Op.getOperand(0);
16378 SDValue Base = Op.getOperand(2);
16379 SDValue Mask = Op.getOperand(3);
16380 SDValue Index = Op.getOperand(4);
16381 SDValue Src = Op.getOperand(5);
16382 SDValue Scale = Op.getOperand(6);
16383 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16386 SDValue Hint = Op.getOperand(6);
16388 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16389 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16390 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16391 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16392 SDValue Chain = Op.getOperand(0);
16393 SDValue Mask = Op.getOperand(2);
16394 SDValue Index = Op.getOperand(3);
16395 SDValue Base = Op.getOperand(4);
16396 SDValue Scale = Op.getOperand(5);
16397 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16399 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16401 SmallVector<SDValue, 2> Results;
16402 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16403 return DAG.getMergeValues(Results, dl);
16405 // Read Performance Monitoring Counters.
16407 SmallVector<SDValue, 2> Results;
16408 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16409 return DAG.getMergeValues(Results, dl);
16411 // XTEST intrinsics.
16413 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16414 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16415 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16416 DAG.getConstant(X86::COND_NE, MVT::i8),
16418 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16419 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16420 Ret, SDValue(InTrans.getNode(), 1));
16424 SmallVector<SDValue, 2> Results;
16425 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16426 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16427 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16428 DAG.getConstant(-1, MVT::i8));
16429 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16430 Op.getOperand(4), GenCF.getValue(1));
16431 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16432 Op.getOperand(5), MachinePointerInfo(),
16434 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16435 DAG.getConstant(X86::COND_B, MVT::i8),
16437 Results.push_back(SetCC);
16438 Results.push_back(Store);
16439 return DAG.getMergeValues(Results, dl);
16444 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16445 SelectionDAG &DAG) const {
16446 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16447 MFI->setReturnAddressIsTaken(true);
16449 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16452 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16454 EVT PtrVT = getPointerTy();
16457 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16458 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16459 DAG.getSubtarget().getRegisterInfo());
16460 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16461 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16462 DAG.getNode(ISD::ADD, dl, PtrVT,
16463 FrameAddr, Offset),
16464 MachinePointerInfo(), false, false, false, 0);
16467 // Just load the return address.
16468 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16469 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16470 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16473 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16474 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16475 MFI->setFrameAddressIsTaken(true);
16477 EVT VT = Op.getValueType();
16478 SDLoc dl(Op); // FIXME probably not meaningful
16479 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16480 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16481 DAG.getSubtarget().getRegisterInfo());
16482 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16483 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16484 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16485 "Invalid Frame Register!");
16486 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16488 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16489 MachinePointerInfo(),
16490 false, false, false, 0);
16494 // FIXME? Maybe this could be a TableGen attribute on some registers and
16495 // this table could be generated automatically from RegInfo.
16496 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16498 unsigned Reg = StringSwitch<unsigned>(RegName)
16499 .Case("esp", X86::ESP)
16500 .Case("rsp", X86::RSP)
16504 report_fatal_error("Invalid register name global variable");
16507 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16508 SelectionDAG &DAG) const {
16509 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16510 DAG.getSubtarget().getRegisterInfo());
16511 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16514 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16515 SDValue Chain = Op.getOperand(0);
16516 SDValue Offset = Op.getOperand(1);
16517 SDValue Handler = Op.getOperand(2);
16520 EVT PtrVT = getPointerTy();
16521 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16522 DAG.getSubtarget().getRegisterInfo());
16523 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16524 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16525 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16526 "Invalid Frame Register!");
16527 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16528 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16530 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16531 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16532 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16533 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16535 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16537 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16538 DAG.getRegister(StoreAddrReg, PtrVT));
16541 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16542 SelectionDAG &DAG) const {
16544 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16545 DAG.getVTList(MVT::i32, MVT::Other),
16546 Op.getOperand(0), Op.getOperand(1));
16549 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16550 SelectionDAG &DAG) const {
16552 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16553 Op.getOperand(0), Op.getOperand(1));
16556 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16557 return Op.getOperand(0);
16560 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16561 SelectionDAG &DAG) const {
16562 SDValue Root = Op.getOperand(0);
16563 SDValue Trmp = Op.getOperand(1); // trampoline
16564 SDValue FPtr = Op.getOperand(2); // nested function
16565 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16568 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16569 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16571 if (Subtarget->is64Bit()) {
16572 SDValue OutChains[6];
16574 // Large code-model.
16575 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16576 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16578 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16579 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16581 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16583 // Load the pointer to the nested function into R11.
16584 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16585 SDValue Addr = Trmp;
16586 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16587 Addr, MachinePointerInfo(TrmpAddr),
16590 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16591 DAG.getConstant(2, MVT::i64));
16592 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16593 MachinePointerInfo(TrmpAddr, 2),
16596 // Load the 'nest' parameter value into R10.
16597 // R10 is specified in X86CallingConv.td
16598 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16599 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16600 DAG.getConstant(10, MVT::i64));
16601 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16602 Addr, MachinePointerInfo(TrmpAddr, 10),
16605 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16606 DAG.getConstant(12, MVT::i64));
16607 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16608 MachinePointerInfo(TrmpAddr, 12),
16611 // Jump to the nested function.
16612 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16613 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16614 DAG.getConstant(20, MVT::i64));
16615 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16616 Addr, MachinePointerInfo(TrmpAddr, 20),
16619 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16620 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16621 DAG.getConstant(22, MVT::i64));
16622 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16623 MachinePointerInfo(TrmpAddr, 22),
16626 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16628 const Function *Func =
16629 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16630 CallingConv::ID CC = Func->getCallingConv();
16635 llvm_unreachable("Unsupported calling convention");
16636 case CallingConv::C:
16637 case CallingConv::X86_StdCall: {
16638 // Pass 'nest' parameter in ECX.
16639 // Must be kept in sync with X86CallingConv.td
16640 NestReg = X86::ECX;
16642 // Check that ECX wasn't needed by an 'inreg' parameter.
16643 FunctionType *FTy = Func->getFunctionType();
16644 const AttributeSet &Attrs = Func->getAttributes();
16646 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16647 unsigned InRegCount = 0;
16650 for (FunctionType::param_iterator I = FTy->param_begin(),
16651 E = FTy->param_end(); I != E; ++I, ++Idx)
16652 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16653 // FIXME: should only count parameters that are lowered to integers.
16654 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16656 if (InRegCount > 2) {
16657 report_fatal_error("Nest register in use - reduce number of inreg"
16663 case CallingConv::X86_FastCall:
16664 case CallingConv::X86_ThisCall:
16665 case CallingConv::Fast:
16666 // Pass 'nest' parameter in EAX.
16667 // Must be kept in sync with X86CallingConv.td
16668 NestReg = X86::EAX;
16672 SDValue OutChains[4];
16673 SDValue Addr, Disp;
16675 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16676 DAG.getConstant(10, MVT::i32));
16677 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16679 // This is storing the opcode for MOV32ri.
16680 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16681 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16682 OutChains[0] = DAG.getStore(Root, dl,
16683 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16684 Trmp, MachinePointerInfo(TrmpAddr),
16687 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16688 DAG.getConstant(1, MVT::i32));
16689 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16690 MachinePointerInfo(TrmpAddr, 1),
16693 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16694 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16695 DAG.getConstant(5, MVT::i32));
16696 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16697 MachinePointerInfo(TrmpAddr, 5),
16700 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16701 DAG.getConstant(6, MVT::i32));
16702 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16703 MachinePointerInfo(TrmpAddr, 6),
16706 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16710 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16711 SelectionDAG &DAG) const {
16713 The rounding mode is in bits 11:10 of FPSR, and has the following
16715 00 Round to nearest
16720 FLT_ROUNDS, on the other hand, expects the following:
16727 To perform the conversion, we do:
16728 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16731 MachineFunction &MF = DAG.getMachineFunction();
16732 const TargetMachine &TM = MF.getTarget();
16733 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16734 unsigned StackAlignment = TFI.getStackAlignment();
16735 MVT VT = Op.getSimpleValueType();
16738 // Save FP Control Word to stack slot
16739 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16740 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16742 MachineMemOperand *MMO =
16743 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16744 MachineMemOperand::MOStore, 2, 2);
16746 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16747 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16748 DAG.getVTList(MVT::Other),
16749 Ops, MVT::i16, MMO);
16751 // Load FP Control Word from stack slot
16752 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16753 MachinePointerInfo(), false, false, false, 0);
16755 // Transform as necessary
16757 DAG.getNode(ISD::SRL, DL, MVT::i16,
16758 DAG.getNode(ISD::AND, DL, MVT::i16,
16759 CWD, DAG.getConstant(0x800, MVT::i16)),
16760 DAG.getConstant(11, MVT::i8));
16762 DAG.getNode(ISD::SRL, DL, MVT::i16,
16763 DAG.getNode(ISD::AND, DL, MVT::i16,
16764 CWD, DAG.getConstant(0x400, MVT::i16)),
16765 DAG.getConstant(9, MVT::i8));
16768 DAG.getNode(ISD::AND, DL, MVT::i16,
16769 DAG.getNode(ISD::ADD, DL, MVT::i16,
16770 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16771 DAG.getConstant(1, MVT::i16)),
16772 DAG.getConstant(3, MVT::i16));
16774 return DAG.getNode((VT.getSizeInBits() < 16 ?
16775 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16778 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16779 MVT VT = Op.getSimpleValueType();
16781 unsigned NumBits = VT.getSizeInBits();
16784 Op = Op.getOperand(0);
16785 if (VT == MVT::i8) {
16786 // Zero extend to i32 since there is not an i8 bsr.
16788 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16791 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16792 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16793 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16795 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16798 DAG.getConstant(NumBits+NumBits-1, OpVT),
16799 DAG.getConstant(X86::COND_E, MVT::i8),
16802 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16804 // Finally xor with NumBits-1.
16805 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16808 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16812 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16813 MVT VT = Op.getSimpleValueType();
16815 unsigned NumBits = VT.getSizeInBits();
16818 Op = Op.getOperand(0);
16819 if (VT == MVT::i8) {
16820 // Zero extend to i32 since there is not an i8 bsr.
16822 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16825 // Issue a bsr (scan bits in reverse).
16826 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16827 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16829 // And xor with NumBits-1.
16830 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16833 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16837 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16838 MVT VT = Op.getSimpleValueType();
16839 unsigned NumBits = VT.getSizeInBits();
16841 Op = Op.getOperand(0);
16843 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16844 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16845 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16847 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16850 DAG.getConstant(NumBits, VT),
16851 DAG.getConstant(X86::COND_E, MVT::i8),
16854 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16857 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16858 // ones, and then concatenate the result back.
16859 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16860 MVT VT = Op.getSimpleValueType();
16862 assert(VT.is256BitVector() && VT.isInteger() &&
16863 "Unsupported value type for operation");
16865 unsigned NumElems = VT.getVectorNumElements();
16868 // Extract the LHS vectors
16869 SDValue LHS = Op.getOperand(0);
16870 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16871 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16873 // Extract the RHS vectors
16874 SDValue RHS = Op.getOperand(1);
16875 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16876 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16878 MVT EltVT = VT.getVectorElementType();
16879 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16881 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16882 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16883 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16886 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16887 assert(Op.getSimpleValueType().is256BitVector() &&
16888 Op.getSimpleValueType().isInteger() &&
16889 "Only handle AVX 256-bit vector integer operation");
16890 return Lower256IntArith(Op, DAG);
16893 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16894 assert(Op.getSimpleValueType().is256BitVector() &&
16895 Op.getSimpleValueType().isInteger() &&
16896 "Only handle AVX 256-bit vector integer operation");
16897 return Lower256IntArith(Op, DAG);
16900 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16901 SelectionDAG &DAG) {
16903 MVT VT = Op.getSimpleValueType();
16905 // Decompose 256-bit ops into smaller 128-bit ops.
16906 if (VT.is256BitVector() && !Subtarget->hasInt256())
16907 return Lower256IntArith(Op, DAG);
16909 SDValue A = Op.getOperand(0);
16910 SDValue B = Op.getOperand(1);
16912 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16913 if (VT == MVT::v4i32) {
16914 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16915 "Should not custom lower when pmuldq is available!");
16917 // Extract the odd parts.
16918 static const int UnpackMask[] = { 1, -1, 3, -1 };
16919 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16920 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16922 // Multiply the even parts.
16923 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16924 // Now multiply odd parts.
16925 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16927 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16928 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16930 // Merge the two vectors back together with a shuffle. This expands into 2
16932 static const int ShufMask[] = { 0, 4, 2, 6 };
16933 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16936 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16937 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16939 // Ahi = psrlqi(a, 32);
16940 // Bhi = psrlqi(b, 32);
16942 // AloBlo = pmuludq(a, b);
16943 // AloBhi = pmuludq(a, Bhi);
16944 // AhiBlo = pmuludq(Ahi, b);
16946 // AloBhi = psllqi(AloBhi, 32);
16947 // AhiBlo = psllqi(AhiBlo, 32);
16948 // return AloBlo + AloBhi + AhiBlo;
16950 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16951 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16953 // Bit cast to 32-bit vectors for MULUDQ
16954 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16955 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16956 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16957 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16958 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16959 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16961 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16962 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16963 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16965 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16966 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16968 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16969 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16972 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16973 assert(Subtarget->isTargetWin64() && "Unexpected target");
16974 EVT VT = Op.getValueType();
16975 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16976 "Unexpected return type for lowering");
16980 switch (Op->getOpcode()) {
16981 default: llvm_unreachable("Unexpected request for libcall!");
16982 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16983 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16984 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16985 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16986 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16987 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16991 SDValue InChain = DAG.getEntryNode();
16993 TargetLowering::ArgListTy Args;
16994 TargetLowering::ArgListEntry Entry;
16995 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16996 EVT ArgVT = Op->getOperand(i).getValueType();
16997 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16998 "Unexpected argument type for lowering");
16999 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17000 Entry.Node = StackPtr;
17001 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17003 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17004 Entry.Ty = PointerType::get(ArgTy,0);
17005 Entry.isSExt = false;
17006 Entry.isZExt = false;
17007 Args.push_back(Entry);
17010 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17013 TargetLowering::CallLoweringInfo CLI(DAG);
17014 CLI.setDebugLoc(dl).setChain(InChain)
17015 .setCallee(getLibcallCallingConv(LC),
17016 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17017 Callee, std::move(Args), 0)
17018 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17020 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17021 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17024 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17025 SelectionDAG &DAG) {
17026 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17027 EVT VT = Op0.getValueType();
17030 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17031 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17033 // PMULxD operations multiply each even value (starting at 0) of LHS with
17034 // the related value of RHS and produce a widen result.
17035 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17036 // => <2 x i64> <ae|cg>
17038 // In other word, to have all the results, we need to perform two PMULxD:
17039 // 1. one with the even values.
17040 // 2. one with the odd values.
17041 // To achieve #2, with need to place the odd values at an even position.
17043 // Place the odd value at an even position (basically, shift all values 1
17044 // step to the left):
17045 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17046 // <a|b|c|d> => <b|undef|d|undef>
17047 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17048 // <e|f|g|h> => <f|undef|h|undef>
17049 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17051 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17053 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17054 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17056 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17057 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17058 // => <2 x i64> <ae|cg>
17059 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17060 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17061 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17062 // => <2 x i64> <bf|dh>
17063 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17064 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17066 // Shuffle it back into the right order.
17067 SDValue Highs, Lows;
17068 if (VT == MVT::v8i32) {
17069 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17070 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17071 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17072 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17074 const int HighMask[] = {1, 5, 3, 7};
17075 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17076 const int LowMask[] = {0, 4, 2, 6};
17077 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17080 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17081 // unsigned multiply.
17082 if (IsSigned && !Subtarget->hasSSE41()) {
17084 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17085 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17086 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17087 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17088 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17090 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17091 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17094 // The first result of MUL_LOHI is actually the low value, followed by the
17096 SDValue Ops[] = {Lows, Highs};
17097 return DAG.getMergeValues(Ops, dl);
17100 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17101 const X86Subtarget *Subtarget) {
17102 MVT VT = Op.getSimpleValueType();
17104 SDValue R = Op.getOperand(0);
17105 SDValue Amt = Op.getOperand(1);
17107 // Optimize shl/srl/sra with constant shift amount.
17108 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17109 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17110 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17112 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17113 (Subtarget->hasInt256() &&
17114 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17115 (Subtarget->hasAVX512() &&
17116 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17117 if (Op.getOpcode() == ISD::SHL)
17118 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17120 if (Op.getOpcode() == ISD::SRL)
17121 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17123 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17124 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17128 if (VT == MVT::v16i8) {
17129 if (Op.getOpcode() == ISD::SHL) {
17130 // Make a large shift.
17131 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17132 MVT::v8i16, R, ShiftAmt,
17134 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17135 // Zero out the rightmost bits.
17136 SmallVector<SDValue, 16> V(16,
17137 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17139 return DAG.getNode(ISD::AND, dl, VT, SHL,
17140 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17142 if (Op.getOpcode() == ISD::SRL) {
17143 // Make a large shift.
17144 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17145 MVT::v8i16, R, ShiftAmt,
17147 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17148 // Zero out the leftmost bits.
17149 SmallVector<SDValue, 16> V(16,
17150 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17152 return DAG.getNode(ISD::AND, dl, VT, SRL,
17153 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17155 if (Op.getOpcode() == ISD::SRA) {
17156 if (ShiftAmt == 7) {
17157 // R s>> 7 === R s< 0
17158 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17159 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17162 // R s>> a === ((R u>> a) ^ m) - m
17163 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17164 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17166 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17167 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17168 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17171 llvm_unreachable("Unknown shift opcode.");
17174 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17175 if (Op.getOpcode() == ISD::SHL) {
17176 // Make a large shift.
17177 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17178 MVT::v16i16, R, ShiftAmt,
17180 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17181 // Zero out the rightmost bits.
17182 SmallVector<SDValue, 32> V(32,
17183 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17185 return DAG.getNode(ISD::AND, dl, VT, SHL,
17186 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17188 if (Op.getOpcode() == ISD::SRL) {
17189 // Make a large shift.
17190 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17191 MVT::v16i16, R, ShiftAmt,
17193 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17194 // Zero out the leftmost bits.
17195 SmallVector<SDValue, 32> V(32,
17196 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17198 return DAG.getNode(ISD::AND, dl, VT, SRL,
17199 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17201 if (Op.getOpcode() == ISD::SRA) {
17202 if (ShiftAmt == 7) {
17203 // R s>> 7 === R s< 0
17204 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17205 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17208 // R s>> a === ((R u>> a) ^ m) - m
17209 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17210 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17212 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17213 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17214 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17217 llvm_unreachable("Unknown shift opcode.");
17222 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17223 if (!Subtarget->is64Bit() &&
17224 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17225 Amt.getOpcode() == ISD::BITCAST &&
17226 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17227 Amt = Amt.getOperand(0);
17228 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17229 VT.getVectorNumElements();
17230 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17231 uint64_t ShiftAmt = 0;
17232 for (unsigned i = 0; i != Ratio; ++i) {
17233 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17237 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17239 // Check remaining shift amounts.
17240 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17241 uint64_t ShAmt = 0;
17242 for (unsigned j = 0; j != Ratio; ++j) {
17243 ConstantSDNode *C =
17244 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17248 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17250 if (ShAmt != ShiftAmt)
17253 switch (Op.getOpcode()) {
17255 llvm_unreachable("Unknown shift opcode!");
17257 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17260 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17263 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17271 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17272 const X86Subtarget* Subtarget) {
17273 MVT VT = Op.getSimpleValueType();
17275 SDValue R = Op.getOperand(0);
17276 SDValue Amt = Op.getOperand(1);
17278 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17279 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17280 (Subtarget->hasInt256() &&
17281 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17282 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17283 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17285 EVT EltVT = VT.getVectorElementType();
17287 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17288 unsigned NumElts = VT.getVectorNumElements();
17290 for (i = 0; i != NumElts; ++i) {
17291 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17295 for (j = i; j != NumElts; ++j) {
17296 SDValue Arg = Amt.getOperand(j);
17297 if (Arg.getOpcode() == ISD::UNDEF) continue;
17298 if (Arg != Amt.getOperand(i))
17301 if (i != NumElts && j == NumElts)
17302 BaseShAmt = Amt.getOperand(i);
17304 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17305 Amt = Amt.getOperand(0);
17306 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17307 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17308 SDValue InVec = Amt.getOperand(0);
17309 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17310 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17312 for (; i != NumElts; ++i) {
17313 SDValue Arg = InVec.getOperand(i);
17314 if (Arg.getOpcode() == ISD::UNDEF) continue;
17318 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17319 if (ConstantSDNode *C =
17320 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17321 unsigned SplatIdx =
17322 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17323 if (C->getZExtValue() == SplatIdx)
17324 BaseShAmt = InVec.getOperand(1);
17327 if (!BaseShAmt.getNode())
17328 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17329 DAG.getIntPtrConstant(0));
17333 if (BaseShAmt.getNode()) {
17334 if (EltVT.bitsGT(MVT::i32))
17335 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17336 else if (EltVT.bitsLT(MVT::i32))
17337 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17339 switch (Op.getOpcode()) {
17341 llvm_unreachable("Unknown shift opcode!");
17343 switch (VT.SimpleTy) {
17344 default: return SDValue();
17353 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17356 switch (VT.SimpleTy) {
17357 default: return SDValue();
17364 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17367 switch (VT.SimpleTy) {
17368 default: return SDValue();
17377 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17383 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17384 if (!Subtarget->is64Bit() &&
17385 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17386 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17387 Amt.getOpcode() == ISD::BITCAST &&
17388 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17389 Amt = Amt.getOperand(0);
17390 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17391 VT.getVectorNumElements();
17392 std::vector<SDValue> Vals(Ratio);
17393 for (unsigned i = 0; i != Ratio; ++i)
17394 Vals[i] = Amt.getOperand(i);
17395 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17396 for (unsigned j = 0; j != Ratio; ++j)
17397 if (Vals[j] != Amt.getOperand(i + j))
17400 switch (Op.getOpcode()) {
17402 llvm_unreachable("Unknown shift opcode!");
17404 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17406 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17408 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17415 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17416 SelectionDAG &DAG) {
17417 MVT VT = Op.getSimpleValueType();
17419 SDValue R = Op.getOperand(0);
17420 SDValue Amt = Op.getOperand(1);
17423 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17424 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17426 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17430 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17434 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17436 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17437 if (Subtarget->hasInt256()) {
17438 if (Op.getOpcode() == ISD::SRL &&
17439 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17440 VT == MVT::v4i64 || VT == MVT::v8i32))
17442 if (Op.getOpcode() == ISD::SHL &&
17443 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17444 VT == MVT::v4i64 || VT == MVT::v8i32))
17446 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17450 // If possible, lower this packed shift into a vector multiply instead of
17451 // expanding it into a sequence of scalar shifts.
17452 // Do this only if the vector shift count is a constant build_vector.
17453 if (Op.getOpcode() == ISD::SHL &&
17454 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17455 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17456 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17457 SmallVector<SDValue, 8> Elts;
17458 EVT SVT = VT.getScalarType();
17459 unsigned SVTBits = SVT.getSizeInBits();
17460 const APInt &One = APInt(SVTBits, 1);
17461 unsigned NumElems = VT.getVectorNumElements();
17463 for (unsigned i=0; i !=NumElems; ++i) {
17464 SDValue Op = Amt->getOperand(i);
17465 if (Op->getOpcode() == ISD::UNDEF) {
17466 Elts.push_back(Op);
17470 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17471 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17472 uint64_t ShAmt = C.getZExtValue();
17473 if (ShAmt >= SVTBits) {
17474 Elts.push_back(DAG.getUNDEF(SVT));
17477 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17479 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17480 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17483 // Lower SHL with variable shift amount.
17484 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17485 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17487 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17488 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17489 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17490 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17493 // If possible, lower this shift as a sequence of two shifts by
17494 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17496 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17498 // Could be rewritten as:
17499 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17501 // The advantage is that the two shifts from the example would be
17502 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17503 // the vector shift into four scalar shifts plus four pairs of vector
17505 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17506 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17507 unsigned TargetOpcode = X86ISD::MOVSS;
17508 bool CanBeSimplified;
17509 // The splat value for the first packed shift (the 'X' from the example).
17510 SDValue Amt1 = Amt->getOperand(0);
17511 // The splat value for the second packed shift (the 'Y' from the example).
17512 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17513 Amt->getOperand(2);
17515 // See if it is possible to replace this node with a sequence of
17516 // two shifts followed by a MOVSS/MOVSD
17517 if (VT == MVT::v4i32) {
17518 // Check if it is legal to use a MOVSS.
17519 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17520 Amt2 == Amt->getOperand(3);
17521 if (!CanBeSimplified) {
17522 // Otherwise, check if we can still simplify this node using a MOVSD.
17523 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17524 Amt->getOperand(2) == Amt->getOperand(3);
17525 TargetOpcode = X86ISD::MOVSD;
17526 Amt2 = Amt->getOperand(2);
17529 // Do similar checks for the case where the machine value type
17531 CanBeSimplified = Amt1 == Amt->getOperand(1);
17532 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17533 CanBeSimplified = Amt2 == Amt->getOperand(i);
17535 if (!CanBeSimplified) {
17536 TargetOpcode = X86ISD::MOVSD;
17537 CanBeSimplified = true;
17538 Amt2 = Amt->getOperand(4);
17539 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17540 CanBeSimplified = Amt1 == Amt->getOperand(i);
17541 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17542 CanBeSimplified = Amt2 == Amt->getOperand(j);
17546 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17547 isa<ConstantSDNode>(Amt2)) {
17548 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17549 EVT CastVT = MVT::v4i32;
17551 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17552 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17554 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17555 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17556 if (TargetOpcode == X86ISD::MOVSD)
17557 CastVT = MVT::v2i64;
17558 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17559 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17560 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17562 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17566 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17567 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17570 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17571 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17573 // Turn 'a' into a mask suitable for VSELECT
17574 SDValue VSelM = DAG.getConstant(0x80, VT);
17575 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17576 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17578 SDValue CM1 = DAG.getConstant(0x0f, VT);
17579 SDValue CM2 = DAG.getConstant(0x3f, VT);
17581 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17582 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17583 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17584 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17585 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17588 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17589 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17590 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17592 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17593 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17594 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17595 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17596 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17599 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17600 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17601 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17603 // return VSELECT(r, r+r, a);
17604 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17605 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17609 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17610 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17611 // solution better.
17612 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17613 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17615 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17616 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17617 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17618 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17619 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17622 // Decompose 256-bit shifts into smaller 128-bit shifts.
17623 if (VT.is256BitVector()) {
17624 unsigned NumElems = VT.getVectorNumElements();
17625 MVT EltVT = VT.getVectorElementType();
17626 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17628 // Extract the two vectors
17629 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17630 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17632 // Recreate the shift amount vectors
17633 SDValue Amt1, Amt2;
17634 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17635 // Constant shift amount
17636 SmallVector<SDValue, 4> Amt1Csts;
17637 SmallVector<SDValue, 4> Amt2Csts;
17638 for (unsigned i = 0; i != NumElems/2; ++i)
17639 Amt1Csts.push_back(Amt->getOperand(i));
17640 for (unsigned i = NumElems/2; i != NumElems; ++i)
17641 Amt2Csts.push_back(Amt->getOperand(i));
17643 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17644 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17646 // Variable shift amount
17647 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17648 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17651 // Issue new vector shifts for the smaller types
17652 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17653 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17655 // Concatenate the result back
17656 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17662 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17663 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17664 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17665 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17666 // has only one use.
17667 SDNode *N = Op.getNode();
17668 SDValue LHS = N->getOperand(0);
17669 SDValue RHS = N->getOperand(1);
17670 unsigned BaseOp = 0;
17673 switch (Op.getOpcode()) {
17674 default: llvm_unreachable("Unknown ovf instruction!");
17676 // A subtract of one will be selected as a INC. Note that INC doesn't
17677 // set CF, so we can't do this for UADDO.
17678 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17680 BaseOp = X86ISD::INC;
17681 Cond = X86::COND_O;
17684 BaseOp = X86ISD::ADD;
17685 Cond = X86::COND_O;
17688 BaseOp = X86ISD::ADD;
17689 Cond = X86::COND_B;
17692 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17693 // set CF, so we can't do this for USUBO.
17694 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17696 BaseOp = X86ISD::DEC;
17697 Cond = X86::COND_O;
17700 BaseOp = X86ISD::SUB;
17701 Cond = X86::COND_O;
17704 BaseOp = X86ISD::SUB;
17705 Cond = X86::COND_B;
17708 BaseOp = X86ISD::SMUL;
17709 Cond = X86::COND_O;
17711 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17712 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17714 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17717 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17718 DAG.getConstant(X86::COND_O, MVT::i32),
17719 SDValue(Sum.getNode(), 2));
17721 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17725 // Also sets EFLAGS.
17726 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17727 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17730 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17731 DAG.getConstant(Cond, MVT::i32),
17732 SDValue(Sum.getNode(), 1));
17734 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17737 // Sign extension of the low part of vector elements. This may be used either
17738 // when sign extend instructions are not available or if the vector element
17739 // sizes already match the sign-extended size. If the vector elements are in
17740 // their pre-extended size and sign extend instructions are available, that will
17741 // be handled by LowerSIGN_EXTEND.
17742 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17743 SelectionDAG &DAG) const {
17745 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17746 MVT VT = Op.getSimpleValueType();
17748 if (!Subtarget->hasSSE2() || !VT.isVector())
17751 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17752 ExtraVT.getScalarType().getSizeInBits();
17754 switch (VT.SimpleTy) {
17755 default: return SDValue();
17758 if (!Subtarget->hasFp256())
17760 if (!Subtarget->hasInt256()) {
17761 // needs to be split
17762 unsigned NumElems = VT.getVectorNumElements();
17764 // Extract the LHS vectors
17765 SDValue LHS = Op.getOperand(0);
17766 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17767 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17769 MVT EltVT = VT.getVectorElementType();
17770 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17772 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17773 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17774 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17776 SDValue Extra = DAG.getValueType(ExtraVT);
17778 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17779 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17781 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17786 SDValue Op0 = Op.getOperand(0);
17788 // This is a sign extension of some low part of vector elements without
17789 // changing the size of the vector elements themselves:
17790 // Shift-Left + Shift-Right-Algebraic.
17791 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17793 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17799 /// Returns true if the operand type is exactly twice the native width, and
17800 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17801 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17802 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17803 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17804 const X86Subtarget &Subtarget =
17805 getTargetMachine().getSubtarget<X86Subtarget>();
17806 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17809 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17810 else if (OpWidth == 128)
17811 return Subtarget.hasCmpxchg16b();
17816 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17817 return needsCmpXchgNb(SI->getValueOperand()->getType());
17820 // Note: this turns large loads into lock cmpxchg8b/16b.
17821 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17822 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17823 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17824 return needsCmpXchgNb(PTy->getElementType());
17827 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17828 const X86Subtarget &Subtarget =
17829 getTargetMachine().getSubtarget<X86Subtarget>();
17830 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17831 const Type *MemType = AI->getType();
17833 // If the operand is too big, we must see if cmpxchg8/16b is available
17834 // and default to library calls otherwise.
17835 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17836 return needsCmpXchgNb(MemType);
17838 AtomicRMWInst::BinOp Op = AI->getOperation();
17841 llvm_unreachable("Unknown atomic operation");
17842 case AtomicRMWInst::Xchg:
17843 case AtomicRMWInst::Add:
17844 case AtomicRMWInst::Sub:
17845 // It's better to use xadd, xsub or xchg for these in all cases.
17847 case AtomicRMWInst::Or:
17848 case AtomicRMWInst::And:
17849 case AtomicRMWInst::Xor:
17850 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17851 // prefix to a normal instruction for these operations.
17852 return !AI->use_empty();
17853 case AtomicRMWInst::Nand:
17854 case AtomicRMWInst::Max:
17855 case AtomicRMWInst::Min:
17856 case AtomicRMWInst::UMax:
17857 case AtomicRMWInst::UMin:
17858 // These always require a non-trivial set of data operations on x86. We must
17859 // use a cmpxchg loop.
17864 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17865 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17866 // no-sse2). There isn't any reason to disable it if the target processor
17868 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17872 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17873 const X86Subtarget &Subtarget =
17874 getTargetMachine().getSubtarget<X86Subtarget>();
17875 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17876 const Type *MemType = AI->getType();
17877 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17878 // there is no benefit in turning such RMWs into loads, and it is actually
17879 // harmful as it introduces a mfence.
17880 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17883 auto Builder = IRBuilder<>(AI);
17884 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17885 auto SynchScope = AI->getSynchScope();
17886 // We must restrict the ordering to avoid generating loads with Release or
17887 // ReleaseAcquire orderings.
17888 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17889 auto Ptr = AI->getPointerOperand();
17891 // Before the load we need a fence. Here is an example lifted from
17892 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17895 // x.store(1, relaxed);
17896 // r1 = y.fetch_add(0, release);
17898 // y.fetch_add(42, acquire);
17899 // r2 = x.load(relaxed);
17900 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17901 // lowered to just a load without a fence. A mfence flushes the store buffer,
17902 // making the optimization clearly correct.
17903 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17904 // otherwise, we might be able to be more agressive on relaxed idempotent
17905 // rmw. In practice, they do not look useful, so we don't try to be
17906 // especially clever.
17907 if (SynchScope == SingleThread) {
17908 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17909 // the IR level, so we must wrap it in an intrinsic.
17911 } else if (hasMFENCE(Subtarget)) {
17912 Function *MFence = llvm::Intrinsic::getDeclaration(M,
17913 Intrinsic::x86_sse2_mfence);
17914 Builder.CreateCall(MFence);
17916 // FIXME: it might make sense to use a locked operation here but on a
17917 // different cache-line to prevent cache-line bouncing. In practice it
17918 // is probably a small win, and x86 processors without mfence are rare
17919 // enough that we do not bother.
17923 // Finally we can emit the atomic load.
17924 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17925 AI->getType()->getPrimitiveSizeInBits());
17926 Loaded->setAtomic(Order, SynchScope);
17927 AI->replaceAllUsesWith(Loaded);
17928 AI->eraseFromParent();
17932 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17933 SelectionDAG &DAG) {
17935 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17936 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17937 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17938 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17940 // The only fence that needs an instruction is a sequentially-consistent
17941 // cross-thread fence.
17942 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17943 if (hasMFENCE(*Subtarget))
17944 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17946 SDValue Chain = Op.getOperand(0);
17947 SDValue Zero = DAG.getConstant(0, MVT::i32);
17949 DAG.getRegister(X86::ESP, MVT::i32), // Base
17950 DAG.getTargetConstant(1, MVT::i8), // Scale
17951 DAG.getRegister(0, MVT::i32), // Index
17952 DAG.getTargetConstant(0, MVT::i32), // Disp
17953 DAG.getRegister(0, MVT::i32), // Segment.
17957 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17958 return SDValue(Res, 0);
17961 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17962 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17965 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17966 SelectionDAG &DAG) {
17967 MVT T = Op.getSimpleValueType();
17971 switch(T.SimpleTy) {
17972 default: llvm_unreachable("Invalid value type!");
17973 case MVT::i8: Reg = X86::AL; size = 1; break;
17974 case MVT::i16: Reg = X86::AX; size = 2; break;
17975 case MVT::i32: Reg = X86::EAX; size = 4; break;
17977 assert(Subtarget->is64Bit() && "Node not type legal!");
17978 Reg = X86::RAX; size = 8;
17981 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17982 Op.getOperand(2), SDValue());
17983 SDValue Ops[] = { cpIn.getValue(0),
17986 DAG.getTargetConstant(size, MVT::i8),
17987 cpIn.getValue(1) };
17988 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17989 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17990 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17994 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17995 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17996 MVT::i32, cpOut.getValue(2));
17997 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17998 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18000 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18001 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18002 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18006 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18007 SelectionDAG &DAG) {
18008 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18009 MVT DstVT = Op.getSimpleValueType();
18011 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18012 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18013 if (DstVT != MVT::f64)
18014 // This conversion needs to be expanded.
18017 SDValue InVec = Op->getOperand(0);
18019 unsigned NumElts = SrcVT.getVectorNumElements();
18020 EVT SVT = SrcVT.getVectorElementType();
18022 // Widen the vector in input in the case of MVT::v2i32.
18023 // Example: from MVT::v2i32 to MVT::v4i32.
18024 SmallVector<SDValue, 16> Elts;
18025 for (unsigned i = 0, e = NumElts; i != e; ++i)
18026 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18027 DAG.getIntPtrConstant(i)));
18029 // Explicitly mark the extra elements as Undef.
18030 SDValue Undef = DAG.getUNDEF(SVT);
18031 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18032 Elts.push_back(Undef);
18034 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18035 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18036 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18037 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18038 DAG.getIntPtrConstant(0));
18041 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18042 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18043 assert((DstVT == MVT::i64 ||
18044 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18045 "Unexpected custom BITCAST");
18046 // i64 <=> MMX conversions are Legal.
18047 if (SrcVT==MVT::i64 && DstVT.isVector())
18049 if (DstVT==MVT::i64 && SrcVT.isVector())
18051 // MMX <=> MMX conversions are Legal.
18052 if (SrcVT.isVector() && DstVT.isVector())
18054 // All other conversions need to be expanded.
18058 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18059 SDNode *Node = Op.getNode();
18061 EVT T = Node->getValueType(0);
18062 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18063 DAG.getConstant(0, T), Node->getOperand(2));
18064 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18065 cast<AtomicSDNode>(Node)->getMemoryVT(),
18066 Node->getOperand(0),
18067 Node->getOperand(1), negOp,
18068 cast<AtomicSDNode>(Node)->getMemOperand(),
18069 cast<AtomicSDNode>(Node)->getOrdering(),
18070 cast<AtomicSDNode>(Node)->getSynchScope());
18073 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18074 SDNode *Node = Op.getNode();
18076 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18078 // Convert seq_cst store -> xchg
18079 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18080 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18081 // (The only way to get a 16-byte store is cmpxchg16b)
18082 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18083 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18084 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18085 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18086 cast<AtomicSDNode>(Node)->getMemoryVT(),
18087 Node->getOperand(0),
18088 Node->getOperand(1), Node->getOperand(2),
18089 cast<AtomicSDNode>(Node)->getMemOperand(),
18090 cast<AtomicSDNode>(Node)->getOrdering(),
18091 cast<AtomicSDNode>(Node)->getSynchScope());
18092 return Swap.getValue(1);
18094 // Other atomic stores have a simple pattern.
18098 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18099 EVT VT = Op.getNode()->getSimpleValueType(0);
18101 // Let legalize expand this if it isn't a legal type yet.
18102 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18105 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18108 bool ExtraOp = false;
18109 switch (Op.getOpcode()) {
18110 default: llvm_unreachable("Invalid code");
18111 case ISD::ADDC: Opc = X86ISD::ADD; break;
18112 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18113 case ISD::SUBC: Opc = X86ISD::SUB; break;
18114 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18118 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18120 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18121 Op.getOperand(1), Op.getOperand(2));
18124 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18125 SelectionDAG &DAG) {
18126 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18128 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18129 // which returns the values as { float, float } (in XMM0) or
18130 // { double, double } (which is returned in XMM0, XMM1).
18132 SDValue Arg = Op.getOperand(0);
18133 EVT ArgVT = Arg.getValueType();
18134 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18136 TargetLowering::ArgListTy Args;
18137 TargetLowering::ArgListEntry Entry;
18141 Entry.isSExt = false;
18142 Entry.isZExt = false;
18143 Args.push_back(Entry);
18145 bool isF64 = ArgVT == MVT::f64;
18146 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18147 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18148 // the results are returned via SRet in memory.
18149 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18150 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18151 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18153 Type *RetTy = isF64
18154 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18155 : (Type*)VectorType::get(ArgTy, 4);
18157 TargetLowering::CallLoweringInfo CLI(DAG);
18158 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18159 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18161 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18164 // Returned in xmm0 and xmm1.
18165 return CallResult.first;
18167 // Returned in bits 0:31 and 32:64 xmm0.
18168 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18169 CallResult.first, DAG.getIntPtrConstant(0));
18170 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18171 CallResult.first, DAG.getIntPtrConstant(1));
18172 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18173 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18176 /// LowerOperation - Provide custom lowering hooks for some operations.
18178 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18179 switch (Op.getOpcode()) {
18180 default: llvm_unreachable("Should not custom lower this!");
18181 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18182 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18183 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18184 return LowerCMP_SWAP(Op, Subtarget, DAG);
18185 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18186 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18187 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18188 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18189 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18190 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18191 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18192 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18193 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18194 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18195 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18196 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18197 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18198 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18199 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18200 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18201 case ISD::SHL_PARTS:
18202 case ISD::SRA_PARTS:
18203 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18204 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18205 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18206 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18207 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18208 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18209 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18210 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18211 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18212 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18213 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18215 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18216 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18217 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18218 case ISD::SETCC: return LowerSETCC(Op, DAG);
18219 case ISD::SELECT: return LowerSELECT(Op, DAG);
18220 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18221 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18222 case ISD::VASTART: return LowerVASTART(Op, DAG);
18223 case ISD::VAARG: return LowerVAARG(Op, DAG);
18224 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18225 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18226 case ISD::INTRINSIC_VOID:
18227 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18228 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18229 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18230 case ISD::FRAME_TO_ARGS_OFFSET:
18231 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18232 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18233 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18234 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18235 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18236 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18237 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18238 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18239 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18240 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18241 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18242 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18243 case ISD::UMUL_LOHI:
18244 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18247 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18253 case ISD::UMULO: return LowerXALUO(Op, DAG);
18254 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18255 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18259 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18260 case ISD::ADD: return LowerADD(Op, DAG);
18261 case ISD::SUB: return LowerSUB(Op, DAG);
18262 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18266 /// ReplaceNodeResults - Replace a node with an illegal result type
18267 /// with a new node built out of custom code.
18268 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18269 SmallVectorImpl<SDValue>&Results,
18270 SelectionDAG &DAG) const {
18272 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18273 switch (N->getOpcode()) {
18275 llvm_unreachable("Do not know how to custom type legalize this operation!");
18276 case ISD::SIGN_EXTEND_INREG:
18281 // We don't want to expand or promote these.
18288 case ISD::UDIVREM: {
18289 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18290 Results.push_back(V);
18293 case ISD::FP_TO_SINT:
18294 case ISD::FP_TO_UINT: {
18295 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18297 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18300 std::pair<SDValue,SDValue> Vals =
18301 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18302 SDValue FIST = Vals.first, StackSlot = Vals.second;
18303 if (FIST.getNode()) {
18304 EVT VT = N->getValueType(0);
18305 // Return a load from the stack slot.
18306 if (StackSlot.getNode())
18307 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18308 MachinePointerInfo(),
18309 false, false, false, 0));
18311 Results.push_back(FIST);
18315 case ISD::UINT_TO_FP: {
18316 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18317 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18318 N->getValueType(0) != MVT::v2f32)
18320 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18322 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18324 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18325 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18326 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18327 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18328 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18329 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18332 case ISD::FP_ROUND: {
18333 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18335 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18336 Results.push_back(V);
18339 case ISD::INTRINSIC_W_CHAIN: {
18340 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18342 default : llvm_unreachable("Do not know how to custom type "
18343 "legalize this intrinsic operation!");
18344 case Intrinsic::x86_rdtsc:
18345 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18347 case Intrinsic::x86_rdtscp:
18348 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18350 case Intrinsic::x86_rdpmc:
18351 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18354 case ISD::READCYCLECOUNTER: {
18355 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18358 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18359 EVT T = N->getValueType(0);
18360 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18361 bool Regs64bit = T == MVT::i128;
18362 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18363 SDValue cpInL, cpInH;
18364 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18365 DAG.getConstant(0, HalfT));
18366 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18367 DAG.getConstant(1, HalfT));
18368 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18369 Regs64bit ? X86::RAX : X86::EAX,
18371 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18372 Regs64bit ? X86::RDX : X86::EDX,
18373 cpInH, cpInL.getValue(1));
18374 SDValue swapInL, swapInH;
18375 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18376 DAG.getConstant(0, HalfT));
18377 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18378 DAG.getConstant(1, HalfT));
18379 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18380 Regs64bit ? X86::RBX : X86::EBX,
18381 swapInL, cpInH.getValue(1));
18382 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18383 Regs64bit ? X86::RCX : X86::ECX,
18384 swapInH, swapInL.getValue(1));
18385 SDValue Ops[] = { swapInH.getValue(0),
18387 swapInH.getValue(1) };
18388 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18389 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18390 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18391 X86ISD::LCMPXCHG8_DAG;
18392 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18393 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18394 Regs64bit ? X86::RAX : X86::EAX,
18395 HalfT, Result.getValue(1));
18396 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18397 Regs64bit ? X86::RDX : X86::EDX,
18398 HalfT, cpOutL.getValue(2));
18399 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18401 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18402 MVT::i32, cpOutH.getValue(2));
18404 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18405 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18406 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18408 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18409 Results.push_back(Success);
18410 Results.push_back(EFLAGS.getValue(1));
18413 case ISD::ATOMIC_SWAP:
18414 case ISD::ATOMIC_LOAD_ADD:
18415 case ISD::ATOMIC_LOAD_SUB:
18416 case ISD::ATOMIC_LOAD_AND:
18417 case ISD::ATOMIC_LOAD_OR:
18418 case ISD::ATOMIC_LOAD_XOR:
18419 case ISD::ATOMIC_LOAD_NAND:
18420 case ISD::ATOMIC_LOAD_MIN:
18421 case ISD::ATOMIC_LOAD_MAX:
18422 case ISD::ATOMIC_LOAD_UMIN:
18423 case ISD::ATOMIC_LOAD_UMAX:
18424 case ISD::ATOMIC_LOAD: {
18425 // Delegate to generic TypeLegalization. Situations we can really handle
18426 // should have already been dealt with by AtomicExpandPass.cpp.
18429 case ISD::BITCAST: {
18430 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18431 EVT DstVT = N->getValueType(0);
18432 EVT SrcVT = N->getOperand(0)->getValueType(0);
18434 if (SrcVT != MVT::f64 ||
18435 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18438 unsigned NumElts = DstVT.getVectorNumElements();
18439 EVT SVT = DstVT.getVectorElementType();
18440 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18441 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18442 MVT::v2f64, N->getOperand(0));
18443 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18445 if (ExperimentalVectorWideningLegalization) {
18446 // If we are legalizing vectors by widening, we already have the desired
18447 // legal vector type, just return it.
18448 Results.push_back(ToVecInt);
18452 SmallVector<SDValue, 8> Elts;
18453 for (unsigned i = 0, e = NumElts; i != e; ++i)
18454 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18455 ToVecInt, DAG.getIntPtrConstant(i)));
18457 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18462 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18464 default: return nullptr;
18465 case X86ISD::BSF: return "X86ISD::BSF";
18466 case X86ISD::BSR: return "X86ISD::BSR";
18467 case X86ISD::SHLD: return "X86ISD::SHLD";
18468 case X86ISD::SHRD: return "X86ISD::SHRD";
18469 case X86ISD::FAND: return "X86ISD::FAND";
18470 case X86ISD::FANDN: return "X86ISD::FANDN";
18471 case X86ISD::FOR: return "X86ISD::FOR";
18472 case X86ISD::FXOR: return "X86ISD::FXOR";
18473 case X86ISD::FSRL: return "X86ISD::FSRL";
18474 case X86ISD::FILD: return "X86ISD::FILD";
18475 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18476 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18477 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18478 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18479 case X86ISD::FLD: return "X86ISD::FLD";
18480 case X86ISD::FST: return "X86ISD::FST";
18481 case X86ISD::CALL: return "X86ISD::CALL";
18482 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18483 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18484 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18485 case X86ISD::BT: return "X86ISD::BT";
18486 case X86ISD::CMP: return "X86ISD::CMP";
18487 case X86ISD::COMI: return "X86ISD::COMI";
18488 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18489 case X86ISD::CMPM: return "X86ISD::CMPM";
18490 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18491 case X86ISD::SETCC: return "X86ISD::SETCC";
18492 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18493 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18494 case X86ISD::CMOV: return "X86ISD::CMOV";
18495 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18496 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18497 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18498 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18499 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18500 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18501 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18502 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18503 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18504 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18505 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18506 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18507 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18508 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18509 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18510 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18511 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18512 case X86ISD::HADD: return "X86ISD::HADD";
18513 case X86ISD::HSUB: return "X86ISD::HSUB";
18514 case X86ISD::FHADD: return "X86ISD::FHADD";
18515 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18516 case X86ISD::UMAX: return "X86ISD::UMAX";
18517 case X86ISD::UMIN: return "X86ISD::UMIN";
18518 case X86ISD::SMAX: return "X86ISD::SMAX";
18519 case X86ISD::SMIN: return "X86ISD::SMIN";
18520 case X86ISD::FMAX: return "X86ISD::FMAX";
18521 case X86ISD::FMIN: return "X86ISD::FMIN";
18522 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18523 case X86ISD::FMINC: return "X86ISD::FMINC";
18524 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18525 case X86ISD::FRCP: return "X86ISD::FRCP";
18526 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18527 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18528 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18529 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18530 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18531 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18532 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18533 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18534 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18535 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18536 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18537 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18538 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18539 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18540 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18541 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18542 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18543 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18544 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18545 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18546 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18547 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18548 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18549 case X86ISD::VSHL: return "X86ISD::VSHL";
18550 case X86ISD::VSRL: return "X86ISD::VSRL";
18551 case X86ISD::VSRA: return "X86ISD::VSRA";
18552 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18553 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18554 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18555 case X86ISD::CMPP: return "X86ISD::CMPP";
18556 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18557 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18558 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18559 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18560 case X86ISD::ADD: return "X86ISD::ADD";
18561 case X86ISD::SUB: return "X86ISD::SUB";
18562 case X86ISD::ADC: return "X86ISD::ADC";
18563 case X86ISD::SBB: return "X86ISD::SBB";
18564 case X86ISD::SMUL: return "X86ISD::SMUL";
18565 case X86ISD::UMUL: return "X86ISD::UMUL";
18566 case X86ISD::INC: return "X86ISD::INC";
18567 case X86ISD::DEC: return "X86ISD::DEC";
18568 case X86ISD::OR: return "X86ISD::OR";
18569 case X86ISD::XOR: return "X86ISD::XOR";
18570 case X86ISD::AND: return "X86ISD::AND";
18571 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18572 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18573 case X86ISD::PTEST: return "X86ISD::PTEST";
18574 case X86ISD::TESTP: return "X86ISD::TESTP";
18575 case X86ISD::TESTM: return "X86ISD::TESTM";
18576 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18577 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18578 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18579 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18580 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18581 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18582 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18583 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18584 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18585 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18586 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18587 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18588 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18589 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18590 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18591 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18592 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18593 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18594 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18595 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18596 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18597 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18598 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18599 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18600 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18601 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18602 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18603 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18604 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18605 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18606 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18607 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18608 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18609 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18610 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18611 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18612 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18613 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18614 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18615 case X86ISD::SAHF: return "X86ISD::SAHF";
18616 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18617 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18618 case X86ISD::FMADD: return "X86ISD::FMADD";
18619 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18620 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18621 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18622 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18623 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18624 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18625 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18626 case X86ISD::XTEST: return "X86ISD::XTEST";
18630 // isLegalAddressingMode - Return true if the addressing mode represented
18631 // by AM is legal for this target, for a load/store of the specified type.
18632 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18634 // X86 supports extremely general addressing modes.
18635 CodeModel::Model M = getTargetMachine().getCodeModel();
18636 Reloc::Model R = getTargetMachine().getRelocationModel();
18638 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18639 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18644 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18646 // If a reference to this global requires an extra load, we can't fold it.
18647 if (isGlobalStubReference(GVFlags))
18650 // If BaseGV requires a register for the PIC base, we cannot also have a
18651 // BaseReg specified.
18652 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18655 // If lower 4G is not available, then we must use rip-relative addressing.
18656 if ((M != CodeModel::Small || R != Reloc::Static) &&
18657 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18661 switch (AM.Scale) {
18667 // These scales always work.
18672 // These scales are formed with basereg+scalereg. Only accept if there is
18677 default: // Other stuff never works.
18684 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18685 unsigned Bits = Ty->getScalarSizeInBits();
18687 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18688 // particularly cheaper than those without.
18692 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18693 // variable shifts just as cheap as scalar ones.
18694 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18697 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18698 // fully general vector.
18702 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18703 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18705 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18706 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18707 return NumBits1 > NumBits2;
18710 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18711 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18714 if (!isTypeLegal(EVT::getEVT(Ty1)))
18717 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18719 // Assuming the caller doesn't have a zeroext or signext return parameter,
18720 // truncation all the way down to i1 is valid.
18724 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18725 return isInt<32>(Imm);
18728 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18729 // Can also use sub to handle negated immediates.
18730 return isInt<32>(Imm);
18733 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18734 if (!VT1.isInteger() || !VT2.isInteger())
18736 unsigned NumBits1 = VT1.getSizeInBits();
18737 unsigned NumBits2 = VT2.getSizeInBits();
18738 return NumBits1 > NumBits2;
18741 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18742 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18743 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18746 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18747 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18748 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18751 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18752 EVT VT1 = Val.getValueType();
18753 if (isZExtFree(VT1, VT2))
18756 if (Val.getOpcode() != ISD::LOAD)
18759 if (!VT1.isSimple() || !VT1.isInteger() ||
18760 !VT2.isSimple() || !VT2.isInteger())
18763 switch (VT1.getSimpleVT().SimpleTy) {
18768 // X86 has 8, 16, and 32-bit zero-extending loads.
18776 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18777 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18780 VT = VT.getScalarType();
18782 if (!VT.isSimple())
18785 switch (VT.getSimpleVT().SimpleTy) {
18796 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18797 // i16 instructions are longer (0x66 prefix) and potentially slower.
18798 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18801 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18802 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18803 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18804 /// are assumed to be legal.
18806 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18808 if (!VT.isSimple())
18811 MVT SVT = VT.getSimpleVT();
18813 // Very little shuffling can be done for 64-bit vectors right now.
18814 if (VT.getSizeInBits() == 64)
18817 // If this is a single-input shuffle with no 128 bit lane crossings we can
18818 // lower it into pshufb.
18819 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18820 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18821 bool isLegal = true;
18822 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18823 if (M[I] >= (int)SVT.getVectorNumElements() ||
18824 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18833 // FIXME: blends, shifts.
18834 return (SVT.getVectorNumElements() == 2 ||
18835 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18836 isMOVLMask(M, SVT) ||
18837 isMOVHLPSMask(M, SVT) ||
18838 isSHUFPMask(M, SVT) ||
18839 isPSHUFDMask(M, SVT) ||
18840 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18841 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18842 isPALIGNRMask(M, SVT, Subtarget) ||
18843 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18844 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18845 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18846 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18847 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18851 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18853 if (!VT.isSimple())
18856 MVT SVT = VT.getSimpleVT();
18857 unsigned NumElts = SVT.getVectorNumElements();
18858 // FIXME: This collection of masks seems suspect.
18861 if (NumElts == 4 && SVT.is128BitVector()) {
18862 return (isMOVLMask(Mask, SVT) ||
18863 isCommutedMOVLMask(Mask, SVT, true) ||
18864 isSHUFPMask(Mask, SVT) ||
18865 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18870 //===----------------------------------------------------------------------===//
18871 // X86 Scheduler Hooks
18872 //===----------------------------------------------------------------------===//
18874 /// Utility function to emit xbegin specifying the start of an RTM region.
18875 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18876 const TargetInstrInfo *TII) {
18877 DebugLoc DL = MI->getDebugLoc();
18879 const BasicBlock *BB = MBB->getBasicBlock();
18880 MachineFunction::iterator I = MBB;
18883 // For the v = xbegin(), we generate
18894 MachineBasicBlock *thisMBB = MBB;
18895 MachineFunction *MF = MBB->getParent();
18896 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18897 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18898 MF->insert(I, mainMBB);
18899 MF->insert(I, sinkMBB);
18901 // Transfer the remainder of BB and its successor edges to sinkMBB.
18902 sinkMBB->splice(sinkMBB->begin(), MBB,
18903 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18904 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18908 // # fallthrough to mainMBB
18909 // # abortion to sinkMBB
18910 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18911 thisMBB->addSuccessor(mainMBB);
18912 thisMBB->addSuccessor(sinkMBB);
18916 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18917 mainMBB->addSuccessor(sinkMBB);
18920 // EAX is live into the sinkMBB
18921 sinkMBB->addLiveIn(X86::EAX);
18922 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18923 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18926 MI->eraseFromParent();
18930 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18931 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18932 // in the .td file.
18933 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18934 const TargetInstrInfo *TII) {
18936 switch (MI->getOpcode()) {
18937 default: llvm_unreachable("illegal opcode!");
18938 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18939 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18940 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18941 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18942 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18943 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18944 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18945 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18948 DebugLoc dl = MI->getDebugLoc();
18949 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18951 unsigned NumArgs = MI->getNumOperands();
18952 for (unsigned i = 1; i < NumArgs; ++i) {
18953 MachineOperand &Op = MI->getOperand(i);
18954 if (!(Op.isReg() && Op.isImplicit()))
18955 MIB.addOperand(Op);
18957 if (MI->hasOneMemOperand())
18958 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18960 BuildMI(*BB, MI, dl,
18961 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18962 .addReg(X86::XMM0);
18964 MI->eraseFromParent();
18968 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18969 // defs in an instruction pattern
18970 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18971 const TargetInstrInfo *TII) {
18973 switch (MI->getOpcode()) {
18974 default: llvm_unreachable("illegal opcode!");
18975 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18976 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18977 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18978 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18979 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18980 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18981 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18982 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18985 DebugLoc dl = MI->getDebugLoc();
18986 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18988 unsigned NumArgs = MI->getNumOperands(); // remove the results
18989 for (unsigned i = 1; i < NumArgs; ++i) {
18990 MachineOperand &Op = MI->getOperand(i);
18991 if (!(Op.isReg() && Op.isImplicit()))
18992 MIB.addOperand(Op);
18994 if (MI->hasOneMemOperand())
18995 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18997 BuildMI(*BB, MI, dl,
18998 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19001 MI->eraseFromParent();
19005 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19006 const TargetInstrInfo *TII,
19007 const X86Subtarget* Subtarget) {
19008 DebugLoc dl = MI->getDebugLoc();
19010 // Address into RAX/EAX, other two args into ECX, EDX.
19011 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19012 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19013 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19014 for (int i = 0; i < X86::AddrNumOperands; ++i)
19015 MIB.addOperand(MI->getOperand(i));
19017 unsigned ValOps = X86::AddrNumOperands;
19018 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19019 .addReg(MI->getOperand(ValOps).getReg());
19020 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19021 .addReg(MI->getOperand(ValOps+1).getReg());
19023 // The instruction doesn't actually take any operands though.
19024 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19026 MI->eraseFromParent(); // The pseudo is gone now.
19030 MachineBasicBlock *
19031 X86TargetLowering::EmitVAARG64WithCustomInserter(
19033 MachineBasicBlock *MBB) const {
19034 // Emit va_arg instruction on X86-64.
19036 // Operands to this pseudo-instruction:
19037 // 0 ) Output : destination address (reg)
19038 // 1-5) Input : va_list address (addr, i64mem)
19039 // 6 ) ArgSize : Size (in bytes) of vararg type
19040 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19041 // 8 ) Align : Alignment of type
19042 // 9 ) EFLAGS (implicit-def)
19044 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19045 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19047 unsigned DestReg = MI->getOperand(0).getReg();
19048 MachineOperand &Base = MI->getOperand(1);
19049 MachineOperand &Scale = MI->getOperand(2);
19050 MachineOperand &Index = MI->getOperand(3);
19051 MachineOperand &Disp = MI->getOperand(4);
19052 MachineOperand &Segment = MI->getOperand(5);
19053 unsigned ArgSize = MI->getOperand(6).getImm();
19054 unsigned ArgMode = MI->getOperand(7).getImm();
19055 unsigned Align = MI->getOperand(8).getImm();
19057 // Memory Reference
19058 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19059 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19060 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19062 // Machine Information
19063 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19064 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19065 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19066 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19067 DebugLoc DL = MI->getDebugLoc();
19069 // struct va_list {
19072 // i64 overflow_area (address)
19073 // i64 reg_save_area (address)
19075 // sizeof(va_list) = 24
19076 // alignment(va_list) = 8
19078 unsigned TotalNumIntRegs = 6;
19079 unsigned TotalNumXMMRegs = 8;
19080 bool UseGPOffset = (ArgMode == 1);
19081 bool UseFPOffset = (ArgMode == 2);
19082 unsigned MaxOffset = TotalNumIntRegs * 8 +
19083 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19085 /* Align ArgSize to a multiple of 8 */
19086 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19087 bool NeedsAlign = (Align > 8);
19089 MachineBasicBlock *thisMBB = MBB;
19090 MachineBasicBlock *overflowMBB;
19091 MachineBasicBlock *offsetMBB;
19092 MachineBasicBlock *endMBB;
19094 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19095 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19096 unsigned OffsetReg = 0;
19098 if (!UseGPOffset && !UseFPOffset) {
19099 // If we only pull from the overflow region, we don't create a branch.
19100 // We don't need to alter control flow.
19101 OffsetDestReg = 0; // unused
19102 OverflowDestReg = DestReg;
19104 offsetMBB = nullptr;
19105 overflowMBB = thisMBB;
19108 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19109 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19110 // If not, pull from overflow_area. (branch to overflowMBB)
19115 // offsetMBB overflowMBB
19120 // Registers for the PHI in endMBB
19121 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19122 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19124 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19125 MachineFunction *MF = MBB->getParent();
19126 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19127 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19128 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19130 MachineFunction::iterator MBBIter = MBB;
19133 // Insert the new basic blocks
19134 MF->insert(MBBIter, offsetMBB);
19135 MF->insert(MBBIter, overflowMBB);
19136 MF->insert(MBBIter, endMBB);
19138 // Transfer the remainder of MBB and its successor edges to endMBB.
19139 endMBB->splice(endMBB->begin(), thisMBB,
19140 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19141 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19143 // Make offsetMBB and overflowMBB successors of thisMBB
19144 thisMBB->addSuccessor(offsetMBB);
19145 thisMBB->addSuccessor(overflowMBB);
19147 // endMBB is a successor of both offsetMBB and overflowMBB
19148 offsetMBB->addSuccessor(endMBB);
19149 overflowMBB->addSuccessor(endMBB);
19151 // Load the offset value into a register
19152 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19153 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19157 .addDisp(Disp, UseFPOffset ? 4 : 0)
19158 .addOperand(Segment)
19159 .setMemRefs(MMOBegin, MMOEnd);
19161 // Check if there is enough room left to pull this argument.
19162 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19164 .addImm(MaxOffset + 8 - ArgSizeA8);
19166 // Branch to "overflowMBB" if offset >= max
19167 // Fall through to "offsetMBB" otherwise
19168 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19169 .addMBB(overflowMBB);
19172 // In offsetMBB, emit code to use the reg_save_area.
19174 assert(OffsetReg != 0);
19176 // Read the reg_save_area address.
19177 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19178 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19183 .addOperand(Segment)
19184 .setMemRefs(MMOBegin, MMOEnd);
19186 // Zero-extend the offset
19187 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19188 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19191 .addImm(X86::sub_32bit);
19193 // Add the offset to the reg_save_area to get the final address.
19194 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19195 .addReg(OffsetReg64)
19196 .addReg(RegSaveReg);
19198 // Compute the offset for the next argument
19199 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19200 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19202 .addImm(UseFPOffset ? 16 : 8);
19204 // Store it back into the va_list.
19205 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19209 .addDisp(Disp, UseFPOffset ? 4 : 0)
19210 .addOperand(Segment)
19211 .addReg(NextOffsetReg)
19212 .setMemRefs(MMOBegin, MMOEnd);
19215 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19220 // Emit code to use overflow area
19223 // Load the overflow_area address into a register.
19224 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19225 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19230 .addOperand(Segment)
19231 .setMemRefs(MMOBegin, MMOEnd);
19233 // If we need to align it, do so. Otherwise, just copy the address
19234 // to OverflowDestReg.
19236 // Align the overflow address
19237 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19238 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19240 // aligned_addr = (addr + (align-1)) & ~(align-1)
19241 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19242 .addReg(OverflowAddrReg)
19245 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19247 .addImm(~(uint64_t)(Align-1));
19249 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19250 .addReg(OverflowAddrReg);
19253 // Compute the next overflow address after this argument.
19254 // (the overflow address should be kept 8-byte aligned)
19255 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19256 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19257 .addReg(OverflowDestReg)
19258 .addImm(ArgSizeA8);
19260 // Store the new overflow address.
19261 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19266 .addOperand(Segment)
19267 .addReg(NextAddrReg)
19268 .setMemRefs(MMOBegin, MMOEnd);
19270 // If we branched, emit the PHI to the front of endMBB.
19272 BuildMI(*endMBB, endMBB->begin(), DL,
19273 TII->get(X86::PHI), DestReg)
19274 .addReg(OffsetDestReg).addMBB(offsetMBB)
19275 .addReg(OverflowDestReg).addMBB(overflowMBB);
19278 // Erase the pseudo instruction
19279 MI->eraseFromParent();
19284 MachineBasicBlock *
19285 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19287 MachineBasicBlock *MBB) const {
19288 // Emit code to save XMM registers to the stack. The ABI says that the
19289 // number of registers to save is given in %al, so it's theoretically
19290 // possible to do an indirect jump trick to avoid saving all of them,
19291 // however this code takes a simpler approach and just executes all
19292 // of the stores if %al is non-zero. It's less code, and it's probably
19293 // easier on the hardware branch predictor, and stores aren't all that
19294 // expensive anyway.
19296 // Create the new basic blocks. One block contains all the XMM stores,
19297 // and one block is the final destination regardless of whether any
19298 // stores were performed.
19299 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19300 MachineFunction *F = MBB->getParent();
19301 MachineFunction::iterator MBBIter = MBB;
19303 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19304 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19305 F->insert(MBBIter, XMMSaveMBB);
19306 F->insert(MBBIter, EndMBB);
19308 // Transfer the remainder of MBB and its successor edges to EndMBB.
19309 EndMBB->splice(EndMBB->begin(), MBB,
19310 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19311 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19313 // The original block will now fall through to the XMM save block.
19314 MBB->addSuccessor(XMMSaveMBB);
19315 // The XMMSaveMBB will fall through to the end block.
19316 XMMSaveMBB->addSuccessor(EndMBB);
19318 // Now add the instructions.
19319 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19320 DebugLoc DL = MI->getDebugLoc();
19322 unsigned CountReg = MI->getOperand(0).getReg();
19323 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19324 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19326 if (!Subtarget->isTargetWin64()) {
19327 // If %al is 0, branch around the XMM save block.
19328 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19329 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19330 MBB->addSuccessor(EndMBB);
19333 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19334 // that was just emitted, but clearly shouldn't be "saved".
19335 assert((MI->getNumOperands() <= 3 ||
19336 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19337 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19338 && "Expected last argument to be EFLAGS");
19339 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19340 // In the XMM save block, save all the XMM argument registers.
19341 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19342 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19343 MachineMemOperand *MMO =
19344 F->getMachineMemOperand(
19345 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19346 MachineMemOperand::MOStore,
19347 /*Size=*/16, /*Align=*/16);
19348 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19349 .addFrameIndex(RegSaveFrameIndex)
19350 .addImm(/*Scale=*/1)
19351 .addReg(/*IndexReg=*/0)
19352 .addImm(/*Disp=*/Offset)
19353 .addReg(/*Segment=*/0)
19354 .addReg(MI->getOperand(i).getReg())
19355 .addMemOperand(MMO);
19358 MI->eraseFromParent(); // The pseudo instruction is gone now.
19363 // The EFLAGS operand of SelectItr might be missing a kill marker
19364 // because there were multiple uses of EFLAGS, and ISel didn't know
19365 // which to mark. Figure out whether SelectItr should have had a
19366 // kill marker, and set it if it should. Returns the correct kill
19368 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19369 MachineBasicBlock* BB,
19370 const TargetRegisterInfo* TRI) {
19371 // Scan forward through BB for a use/def of EFLAGS.
19372 MachineBasicBlock::iterator miI(std::next(SelectItr));
19373 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19374 const MachineInstr& mi = *miI;
19375 if (mi.readsRegister(X86::EFLAGS))
19377 if (mi.definesRegister(X86::EFLAGS))
19378 break; // Should have kill-flag - update below.
19381 // If we hit the end of the block, check whether EFLAGS is live into a
19383 if (miI == BB->end()) {
19384 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19385 sEnd = BB->succ_end();
19386 sItr != sEnd; ++sItr) {
19387 MachineBasicBlock* succ = *sItr;
19388 if (succ->isLiveIn(X86::EFLAGS))
19393 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19394 // out. SelectMI should have a kill flag on EFLAGS.
19395 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19399 MachineBasicBlock *
19400 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19401 MachineBasicBlock *BB) const {
19402 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19403 DebugLoc DL = MI->getDebugLoc();
19405 // To "insert" a SELECT_CC instruction, we actually have to insert the
19406 // diamond control-flow pattern. The incoming instruction knows the
19407 // destination vreg to set, the condition code register to branch on, the
19408 // true/false values to select between, and a branch opcode to use.
19409 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19410 MachineFunction::iterator It = BB;
19416 // cmpTY ccX, r1, r2
19418 // fallthrough --> copy0MBB
19419 MachineBasicBlock *thisMBB = BB;
19420 MachineFunction *F = BB->getParent();
19421 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19422 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19423 F->insert(It, copy0MBB);
19424 F->insert(It, sinkMBB);
19426 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19427 // live into the sink and copy blocks.
19428 const TargetRegisterInfo *TRI =
19429 BB->getParent()->getSubtarget().getRegisterInfo();
19430 if (!MI->killsRegister(X86::EFLAGS) &&
19431 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19432 copy0MBB->addLiveIn(X86::EFLAGS);
19433 sinkMBB->addLiveIn(X86::EFLAGS);
19436 // Transfer the remainder of BB and its successor edges to sinkMBB.
19437 sinkMBB->splice(sinkMBB->begin(), BB,
19438 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19439 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19441 // Add the true and fallthrough blocks as its successors.
19442 BB->addSuccessor(copy0MBB);
19443 BB->addSuccessor(sinkMBB);
19445 // Create the conditional branch instruction.
19447 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19448 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19451 // %FalseValue = ...
19452 // # fallthrough to sinkMBB
19453 copy0MBB->addSuccessor(sinkMBB);
19456 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19458 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19459 TII->get(X86::PHI), MI->getOperand(0).getReg())
19460 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19461 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19463 MI->eraseFromParent(); // The pseudo instruction is gone now.
19467 MachineBasicBlock *
19468 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19469 MachineBasicBlock *BB) const {
19470 MachineFunction *MF = BB->getParent();
19471 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19472 DebugLoc DL = MI->getDebugLoc();
19473 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19475 assert(MF->shouldSplitStack());
19477 const bool Is64Bit = Subtarget->is64Bit();
19478 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19480 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19481 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19484 // ... [Till the alloca]
19485 // If stacklet is not large enough, jump to mallocMBB
19488 // Allocate by subtracting from RSP
19489 // Jump to continueMBB
19492 // Allocate by call to runtime
19496 // [rest of original BB]
19499 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19500 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19501 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19503 MachineRegisterInfo &MRI = MF->getRegInfo();
19504 const TargetRegisterClass *AddrRegClass =
19505 getRegClassFor(getPointerTy());
19507 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19508 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19509 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19510 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19511 sizeVReg = MI->getOperand(1).getReg(),
19512 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19514 MachineFunction::iterator MBBIter = BB;
19517 MF->insert(MBBIter, bumpMBB);
19518 MF->insert(MBBIter, mallocMBB);
19519 MF->insert(MBBIter, continueMBB);
19521 continueMBB->splice(continueMBB->begin(), BB,
19522 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19523 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19525 // Add code to the main basic block to check if the stack limit has been hit,
19526 // and if so, jump to mallocMBB otherwise to bumpMBB.
19527 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19528 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19529 .addReg(tmpSPVReg).addReg(sizeVReg);
19530 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19531 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19532 .addReg(SPLimitVReg);
19533 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19535 // bumpMBB simply decreases the stack pointer, since we know the current
19536 // stacklet has enough space.
19537 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19538 .addReg(SPLimitVReg);
19539 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19540 .addReg(SPLimitVReg);
19541 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19543 // Calls into a routine in libgcc to allocate more space from the heap.
19544 const uint32_t *RegMask = MF->getTarget()
19545 .getSubtargetImpl()
19546 ->getRegisterInfo()
19547 ->getCallPreservedMask(CallingConv::C);
19549 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19551 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19552 .addExternalSymbol("__morestack_allocate_stack_space")
19553 .addRegMask(RegMask)
19554 .addReg(X86::RDI, RegState::Implicit)
19555 .addReg(X86::RAX, RegState::ImplicitDefine);
19556 } else if (Is64Bit) {
19557 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19559 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19560 .addExternalSymbol("__morestack_allocate_stack_space")
19561 .addRegMask(RegMask)
19562 .addReg(X86::EDI, RegState::Implicit)
19563 .addReg(X86::EAX, RegState::ImplicitDefine);
19565 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19567 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19568 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19569 .addExternalSymbol("__morestack_allocate_stack_space")
19570 .addRegMask(RegMask)
19571 .addReg(X86::EAX, RegState::ImplicitDefine);
19575 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19578 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19579 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19580 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19582 // Set up the CFG correctly.
19583 BB->addSuccessor(bumpMBB);
19584 BB->addSuccessor(mallocMBB);
19585 mallocMBB->addSuccessor(continueMBB);
19586 bumpMBB->addSuccessor(continueMBB);
19588 // Take care of the PHI nodes.
19589 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19590 MI->getOperand(0).getReg())
19591 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19592 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19594 // Delete the original pseudo instruction.
19595 MI->eraseFromParent();
19598 return continueMBB;
19601 MachineBasicBlock *
19602 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19603 MachineBasicBlock *BB) const {
19604 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19605 DebugLoc DL = MI->getDebugLoc();
19607 assert(!Subtarget->isTargetMacho());
19609 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19610 // non-trivial part is impdef of ESP.
19612 if (Subtarget->isTargetWin64()) {
19613 if (Subtarget->isTargetCygMing()) {
19614 // ___chkstk(Mingw64):
19615 // Clobbers R10, R11, RAX and EFLAGS.
19617 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19618 .addExternalSymbol("___chkstk")
19619 .addReg(X86::RAX, RegState::Implicit)
19620 .addReg(X86::RSP, RegState::Implicit)
19621 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19622 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19623 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19625 // __chkstk(MSVCRT): does not update stack pointer.
19626 // Clobbers R10, R11 and EFLAGS.
19627 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19628 .addExternalSymbol("__chkstk")
19629 .addReg(X86::RAX, RegState::Implicit)
19630 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19631 // RAX has the offset to be subtracted from RSP.
19632 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19637 const char *StackProbeSymbol =
19638 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19640 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19641 .addExternalSymbol(StackProbeSymbol)
19642 .addReg(X86::EAX, RegState::Implicit)
19643 .addReg(X86::ESP, RegState::Implicit)
19644 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19645 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19646 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19649 MI->eraseFromParent(); // The pseudo instruction is gone now.
19653 MachineBasicBlock *
19654 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19655 MachineBasicBlock *BB) const {
19656 // This is pretty easy. We're taking the value that we received from
19657 // our load from the relocation, sticking it in either RDI (x86-64)
19658 // or EAX and doing an indirect call. The return value will then
19659 // be in the normal return register.
19660 MachineFunction *F = BB->getParent();
19661 const X86InstrInfo *TII =
19662 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19663 DebugLoc DL = MI->getDebugLoc();
19665 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19666 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19668 // Get a register mask for the lowered call.
19669 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19670 // proper register mask.
19671 const uint32_t *RegMask = F->getTarget()
19672 .getSubtargetImpl()
19673 ->getRegisterInfo()
19674 ->getCallPreservedMask(CallingConv::C);
19675 if (Subtarget->is64Bit()) {
19676 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19677 TII->get(X86::MOV64rm), X86::RDI)
19679 .addImm(0).addReg(0)
19680 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19681 MI->getOperand(3).getTargetFlags())
19683 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19684 addDirectMem(MIB, X86::RDI);
19685 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19686 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19687 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19688 TII->get(X86::MOV32rm), X86::EAX)
19690 .addImm(0).addReg(0)
19691 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19692 MI->getOperand(3).getTargetFlags())
19694 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19695 addDirectMem(MIB, X86::EAX);
19696 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19698 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19699 TII->get(X86::MOV32rm), X86::EAX)
19700 .addReg(TII->getGlobalBaseReg(F))
19701 .addImm(0).addReg(0)
19702 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19703 MI->getOperand(3).getTargetFlags())
19705 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19706 addDirectMem(MIB, X86::EAX);
19707 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19710 MI->eraseFromParent(); // The pseudo instruction is gone now.
19714 MachineBasicBlock *
19715 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19716 MachineBasicBlock *MBB) const {
19717 DebugLoc DL = MI->getDebugLoc();
19718 MachineFunction *MF = MBB->getParent();
19719 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19720 MachineRegisterInfo &MRI = MF->getRegInfo();
19722 const BasicBlock *BB = MBB->getBasicBlock();
19723 MachineFunction::iterator I = MBB;
19726 // Memory Reference
19727 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19728 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19731 unsigned MemOpndSlot = 0;
19733 unsigned CurOp = 0;
19735 DstReg = MI->getOperand(CurOp++).getReg();
19736 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19737 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19738 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19739 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19741 MemOpndSlot = CurOp;
19743 MVT PVT = getPointerTy();
19744 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19745 "Invalid Pointer Size!");
19747 // For v = setjmp(buf), we generate
19750 // buf[LabelOffset] = restoreMBB
19751 // SjLjSetup restoreMBB
19757 // v = phi(main, restore)
19762 MachineBasicBlock *thisMBB = MBB;
19763 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19764 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19765 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19766 MF->insert(I, mainMBB);
19767 MF->insert(I, sinkMBB);
19768 MF->push_back(restoreMBB);
19770 MachineInstrBuilder MIB;
19772 // Transfer the remainder of BB and its successor edges to sinkMBB.
19773 sinkMBB->splice(sinkMBB->begin(), MBB,
19774 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19775 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19778 unsigned PtrStoreOpc = 0;
19779 unsigned LabelReg = 0;
19780 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19781 Reloc::Model RM = MF->getTarget().getRelocationModel();
19782 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19783 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19785 // Prepare IP either in reg or imm.
19786 if (!UseImmLabel) {
19787 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19788 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19789 LabelReg = MRI.createVirtualRegister(PtrRC);
19790 if (Subtarget->is64Bit()) {
19791 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19795 .addMBB(restoreMBB)
19798 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19799 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19800 .addReg(XII->getGlobalBaseReg(MF))
19803 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19807 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19809 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19810 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19811 if (i == X86::AddrDisp)
19812 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19814 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19817 MIB.addReg(LabelReg);
19819 MIB.addMBB(restoreMBB);
19820 MIB.setMemRefs(MMOBegin, MMOEnd);
19822 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19823 .addMBB(restoreMBB);
19825 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19826 MF->getSubtarget().getRegisterInfo());
19827 MIB.addRegMask(RegInfo->getNoPreservedMask());
19828 thisMBB->addSuccessor(mainMBB);
19829 thisMBB->addSuccessor(restoreMBB);
19833 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19834 mainMBB->addSuccessor(sinkMBB);
19837 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19838 TII->get(X86::PHI), DstReg)
19839 .addReg(mainDstReg).addMBB(mainMBB)
19840 .addReg(restoreDstReg).addMBB(restoreMBB);
19843 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19844 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19845 restoreMBB->addSuccessor(sinkMBB);
19847 MI->eraseFromParent();
19851 MachineBasicBlock *
19852 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19853 MachineBasicBlock *MBB) const {
19854 DebugLoc DL = MI->getDebugLoc();
19855 MachineFunction *MF = MBB->getParent();
19856 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19857 MachineRegisterInfo &MRI = MF->getRegInfo();
19859 // Memory Reference
19860 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19861 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19863 MVT PVT = getPointerTy();
19864 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19865 "Invalid Pointer Size!");
19867 const TargetRegisterClass *RC =
19868 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19869 unsigned Tmp = MRI.createVirtualRegister(RC);
19870 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19871 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19872 MF->getSubtarget().getRegisterInfo());
19873 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19874 unsigned SP = RegInfo->getStackRegister();
19876 MachineInstrBuilder MIB;
19878 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19879 const int64_t SPOffset = 2 * PVT.getStoreSize();
19881 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19882 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19885 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19886 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19887 MIB.addOperand(MI->getOperand(i));
19888 MIB.setMemRefs(MMOBegin, MMOEnd);
19890 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19891 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19892 if (i == X86::AddrDisp)
19893 MIB.addDisp(MI->getOperand(i), LabelOffset);
19895 MIB.addOperand(MI->getOperand(i));
19897 MIB.setMemRefs(MMOBegin, MMOEnd);
19899 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19900 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19901 if (i == X86::AddrDisp)
19902 MIB.addDisp(MI->getOperand(i), SPOffset);
19904 MIB.addOperand(MI->getOperand(i));
19906 MIB.setMemRefs(MMOBegin, MMOEnd);
19908 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19910 MI->eraseFromParent();
19914 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19915 // accumulator loops. Writing back to the accumulator allows the coalescer
19916 // to remove extra copies in the loop.
19917 MachineBasicBlock *
19918 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19919 MachineBasicBlock *MBB) const {
19920 MachineOperand &AddendOp = MI->getOperand(3);
19922 // Bail out early if the addend isn't a register - we can't switch these.
19923 if (!AddendOp.isReg())
19926 MachineFunction &MF = *MBB->getParent();
19927 MachineRegisterInfo &MRI = MF.getRegInfo();
19929 // Check whether the addend is defined by a PHI:
19930 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19931 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19932 if (!AddendDef.isPHI())
19935 // Look for the following pattern:
19937 // %addend = phi [%entry, 0], [%loop, %result]
19939 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19943 // %addend = phi [%entry, 0], [%loop, %result]
19945 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19947 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19948 assert(AddendDef.getOperand(i).isReg());
19949 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19950 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19951 if (&PHISrcInst == MI) {
19952 // Found a matching instruction.
19953 unsigned NewFMAOpc = 0;
19954 switch (MI->getOpcode()) {
19955 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19956 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19957 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19958 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19959 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19960 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19961 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19962 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19963 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19964 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19965 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19966 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19967 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19968 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19969 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19970 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19971 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19972 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19973 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19974 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19975 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19976 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19977 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19978 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19979 default: llvm_unreachable("Unrecognized FMA variant.");
19982 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19983 MachineInstrBuilder MIB =
19984 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19985 .addOperand(MI->getOperand(0))
19986 .addOperand(MI->getOperand(3))
19987 .addOperand(MI->getOperand(2))
19988 .addOperand(MI->getOperand(1));
19989 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19990 MI->eraseFromParent();
19997 MachineBasicBlock *
19998 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19999 MachineBasicBlock *BB) const {
20000 switch (MI->getOpcode()) {
20001 default: llvm_unreachable("Unexpected instr type to insert");
20002 case X86::TAILJMPd64:
20003 case X86::TAILJMPr64:
20004 case X86::TAILJMPm64:
20005 llvm_unreachable("TAILJMP64 would not be touched here.");
20006 case X86::TCRETURNdi64:
20007 case X86::TCRETURNri64:
20008 case X86::TCRETURNmi64:
20010 case X86::WIN_ALLOCA:
20011 return EmitLoweredWinAlloca(MI, BB);
20012 case X86::SEG_ALLOCA_32:
20013 case X86::SEG_ALLOCA_64:
20014 return EmitLoweredSegAlloca(MI, BB);
20015 case X86::TLSCall_32:
20016 case X86::TLSCall_64:
20017 return EmitLoweredTLSCall(MI, BB);
20018 case X86::CMOV_GR8:
20019 case X86::CMOV_FR32:
20020 case X86::CMOV_FR64:
20021 case X86::CMOV_V4F32:
20022 case X86::CMOV_V2F64:
20023 case X86::CMOV_V2I64:
20024 case X86::CMOV_V8F32:
20025 case X86::CMOV_V4F64:
20026 case X86::CMOV_V4I64:
20027 case X86::CMOV_V16F32:
20028 case X86::CMOV_V8F64:
20029 case X86::CMOV_V8I64:
20030 case X86::CMOV_GR16:
20031 case X86::CMOV_GR32:
20032 case X86::CMOV_RFP32:
20033 case X86::CMOV_RFP64:
20034 case X86::CMOV_RFP80:
20035 return EmitLoweredSelect(MI, BB);
20037 case X86::FP32_TO_INT16_IN_MEM:
20038 case X86::FP32_TO_INT32_IN_MEM:
20039 case X86::FP32_TO_INT64_IN_MEM:
20040 case X86::FP64_TO_INT16_IN_MEM:
20041 case X86::FP64_TO_INT32_IN_MEM:
20042 case X86::FP64_TO_INT64_IN_MEM:
20043 case X86::FP80_TO_INT16_IN_MEM:
20044 case X86::FP80_TO_INT32_IN_MEM:
20045 case X86::FP80_TO_INT64_IN_MEM: {
20046 MachineFunction *F = BB->getParent();
20047 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20048 DebugLoc DL = MI->getDebugLoc();
20050 // Change the floating point control register to use "round towards zero"
20051 // mode when truncating to an integer value.
20052 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20053 addFrameReference(BuildMI(*BB, MI, DL,
20054 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20056 // Load the old value of the high byte of the control word...
20058 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20059 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20062 // Set the high part to be round to zero...
20063 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20066 // Reload the modified control word now...
20067 addFrameReference(BuildMI(*BB, MI, DL,
20068 TII->get(X86::FLDCW16m)), CWFrameIdx);
20070 // Restore the memory image of control word to original value
20071 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20074 // Get the X86 opcode to use.
20076 switch (MI->getOpcode()) {
20077 default: llvm_unreachable("illegal opcode!");
20078 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20079 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20080 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20081 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20082 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20083 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20084 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20085 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20086 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20090 MachineOperand &Op = MI->getOperand(0);
20092 AM.BaseType = X86AddressMode::RegBase;
20093 AM.Base.Reg = Op.getReg();
20095 AM.BaseType = X86AddressMode::FrameIndexBase;
20096 AM.Base.FrameIndex = Op.getIndex();
20098 Op = MI->getOperand(1);
20100 AM.Scale = Op.getImm();
20101 Op = MI->getOperand(2);
20103 AM.IndexReg = Op.getImm();
20104 Op = MI->getOperand(3);
20105 if (Op.isGlobal()) {
20106 AM.GV = Op.getGlobal();
20108 AM.Disp = Op.getImm();
20110 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20111 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20113 // Reload the original control word now.
20114 addFrameReference(BuildMI(*BB, MI, DL,
20115 TII->get(X86::FLDCW16m)), CWFrameIdx);
20117 MI->eraseFromParent(); // The pseudo instruction is gone now.
20120 // String/text processing lowering.
20121 case X86::PCMPISTRM128REG:
20122 case X86::VPCMPISTRM128REG:
20123 case X86::PCMPISTRM128MEM:
20124 case X86::VPCMPISTRM128MEM:
20125 case X86::PCMPESTRM128REG:
20126 case X86::VPCMPESTRM128REG:
20127 case X86::PCMPESTRM128MEM:
20128 case X86::VPCMPESTRM128MEM:
20129 assert(Subtarget->hasSSE42() &&
20130 "Target must have SSE4.2 or AVX features enabled");
20131 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20133 // String/text processing lowering.
20134 case X86::PCMPISTRIREG:
20135 case X86::VPCMPISTRIREG:
20136 case X86::PCMPISTRIMEM:
20137 case X86::VPCMPISTRIMEM:
20138 case X86::PCMPESTRIREG:
20139 case X86::VPCMPESTRIREG:
20140 case X86::PCMPESTRIMEM:
20141 case X86::VPCMPESTRIMEM:
20142 assert(Subtarget->hasSSE42() &&
20143 "Target must have SSE4.2 or AVX features enabled");
20144 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20146 // Thread synchronization.
20148 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20153 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20155 case X86::VASTART_SAVE_XMM_REGS:
20156 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20158 case X86::VAARG_64:
20159 return EmitVAARG64WithCustomInserter(MI, BB);
20161 case X86::EH_SjLj_SetJmp32:
20162 case X86::EH_SjLj_SetJmp64:
20163 return emitEHSjLjSetJmp(MI, BB);
20165 case X86::EH_SjLj_LongJmp32:
20166 case X86::EH_SjLj_LongJmp64:
20167 return emitEHSjLjLongJmp(MI, BB);
20169 case TargetOpcode::STACKMAP:
20170 case TargetOpcode::PATCHPOINT:
20171 return emitPatchPoint(MI, BB);
20173 case X86::VFMADDPDr213r:
20174 case X86::VFMADDPSr213r:
20175 case X86::VFMADDSDr213r:
20176 case X86::VFMADDSSr213r:
20177 case X86::VFMSUBPDr213r:
20178 case X86::VFMSUBPSr213r:
20179 case X86::VFMSUBSDr213r:
20180 case X86::VFMSUBSSr213r:
20181 case X86::VFNMADDPDr213r:
20182 case X86::VFNMADDPSr213r:
20183 case X86::VFNMADDSDr213r:
20184 case X86::VFNMADDSSr213r:
20185 case X86::VFNMSUBPDr213r:
20186 case X86::VFNMSUBPSr213r:
20187 case X86::VFNMSUBSDr213r:
20188 case X86::VFNMSUBSSr213r:
20189 case X86::VFMADDPDr213rY:
20190 case X86::VFMADDPSr213rY:
20191 case X86::VFMSUBPDr213rY:
20192 case X86::VFMSUBPSr213rY:
20193 case X86::VFNMADDPDr213rY:
20194 case X86::VFNMADDPSr213rY:
20195 case X86::VFNMSUBPDr213rY:
20196 case X86::VFNMSUBPSr213rY:
20197 return emitFMA3Instr(MI, BB);
20201 //===----------------------------------------------------------------------===//
20202 // X86 Optimization Hooks
20203 //===----------------------------------------------------------------------===//
20205 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20208 const SelectionDAG &DAG,
20209 unsigned Depth) const {
20210 unsigned BitWidth = KnownZero.getBitWidth();
20211 unsigned Opc = Op.getOpcode();
20212 assert((Opc >= ISD::BUILTIN_OP_END ||
20213 Opc == ISD::INTRINSIC_WO_CHAIN ||
20214 Opc == ISD::INTRINSIC_W_CHAIN ||
20215 Opc == ISD::INTRINSIC_VOID) &&
20216 "Should use MaskedValueIsZero if you don't know whether Op"
20217 " is a target node!");
20219 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20233 // These nodes' second result is a boolean.
20234 if (Op.getResNo() == 0)
20237 case X86ISD::SETCC:
20238 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20240 case ISD::INTRINSIC_WO_CHAIN: {
20241 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20242 unsigned NumLoBits = 0;
20245 case Intrinsic::x86_sse_movmsk_ps:
20246 case Intrinsic::x86_avx_movmsk_ps_256:
20247 case Intrinsic::x86_sse2_movmsk_pd:
20248 case Intrinsic::x86_avx_movmsk_pd_256:
20249 case Intrinsic::x86_mmx_pmovmskb:
20250 case Intrinsic::x86_sse2_pmovmskb_128:
20251 case Intrinsic::x86_avx2_pmovmskb: {
20252 // High bits of movmskp{s|d}, pmovmskb are known zero.
20254 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20255 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20256 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20257 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20258 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20259 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20260 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20261 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20263 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20272 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20274 const SelectionDAG &,
20275 unsigned Depth) const {
20276 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20277 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20278 return Op.getValueType().getScalarType().getSizeInBits();
20284 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20285 /// node is a GlobalAddress + offset.
20286 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20287 const GlobalValue* &GA,
20288 int64_t &Offset) const {
20289 if (N->getOpcode() == X86ISD::Wrapper) {
20290 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20291 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20292 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20296 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20299 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20300 /// same as extracting the high 128-bit part of 256-bit vector and then
20301 /// inserting the result into the low part of a new 256-bit vector
20302 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20303 EVT VT = SVOp->getValueType(0);
20304 unsigned NumElems = VT.getVectorNumElements();
20306 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20307 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20308 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20309 SVOp->getMaskElt(j) >= 0)
20315 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20316 /// same as extracting the low 128-bit part of 256-bit vector and then
20317 /// inserting the result into the high part of a new 256-bit vector
20318 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20319 EVT VT = SVOp->getValueType(0);
20320 unsigned NumElems = VT.getVectorNumElements();
20322 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20323 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20324 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20325 SVOp->getMaskElt(j) >= 0)
20331 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20332 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20333 TargetLowering::DAGCombinerInfo &DCI,
20334 const X86Subtarget* Subtarget) {
20336 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20337 SDValue V1 = SVOp->getOperand(0);
20338 SDValue V2 = SVOp->getOperand(1);
20339 EVT VT = SVOp->getValueType(0);
20340 unsigned NumElems = VT.getVectorNumElements();
20342 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20343 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20347 // V UNDEF BUILD_VECTOR UNDEF
20349 // CONCAT_VECTOR CONCAT_VECTOR
20352 // RESULT: V + zero extended
20354 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20355 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20356 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20359 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20362 // To match the shuffle mask, the first half of the mask should
20363 // be exactly the first vector, and all the rest a splat with the
20364 // first element of the second one.
20365 for (unsigned i = 0; i != NumElems/2; ++i)
20366 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20367 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20370 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20371 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20372 if (Ld->hasNUsesOfValue(1, 0)) {
20373 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20374 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20376 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20378 Ld->getPointerInfo(),
20379 Ld->getAlignment(),
20380 false/*isVolatile*/, true/*ReadMem*/,
20381 false/*WriteMem*/);
20383 // Make sure the newly-created LOAD is in the same position as Ld in
20384 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20385 // and update uses of Ld's output chain to use the TokenFactor.
20386 if (Ld->hasAnyUseOfValue(1)) {
20387 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20388 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20389 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20390 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20391 SDValue(ResNode.getNode(), 1));
20394 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20398 // Emit a zeroed vector and insert the desired subvector on its
20400 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20401 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20402 return DCI.CombineTo(N, InsV);
20405 //===--------------------------------------------------------------------===//
20406 // Combine some shuffles into subvector extracts and inserts:
20409 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20410 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20411 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20412 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20413 return DCI.CombineTo(N, InsV);
20416 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20417 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20418 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20419 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20420 return DCI.CombineTo(N, InsV);
20426 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20429 /// This is the leaf of the recursive combinine below. When we have found some
20430 /// chain of single-use x86 shuffle instructions and accumulated the combined
20431 /// shuffle mask represented by them, this will try to pattern match that mask
20432 /// into either a single instruction if there is a special purpose instruction
20433 /// for this operation, or into a PSHUFB instruction which is a fully general
20434 /// instruction but should only be used to replace chains over a certain depth.
20435 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20436 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20437 TargetLowering::DAGCombinerInfo &DCI,
20438 const X86Subtarget *Subtarget) {
20439 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20441 // Find the operand that enters the chain. Note that multiple uses are OK
20442 // here, we're not going to remove the operand we find.
20443 SDValue Input = Op.getOperand(0);
20444 while (Input.getOpcode() == ISD::BITCAST)
20445 Input = Input.getOperand(0);
20447 MVT VT = Input.getSimpleValueType();
20448 MVT RootVT = Root.getSimpleValueType();
20451 // Just remove no-op shuffle masks.
20452 if (Mask.size() == 1) {
20453 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20458 // Use the float domain if the operand type is a floating point type.
20459 bool FloatDomain = VT.isFloatingPoint();
20461 // For floating point shuffles, we don't have free copies in the shuffle
20462 // instructions or the ability to load as part of the instruction, so
20463 // canonicalize their shuffles to UNPCK or MOV variants.
20465 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20466 // vectors because it can have a load folded into it that UNPCK cannot. This
20467 // doesn't preclude something switching to the shorter encoding post-RA.
20469 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20470 bool Lo = Mask.equals(0, 0);
20473 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20474 // is no slower than UNPCKLPD but has the option to fold the input operand
20475 // into even an unaligned memory load.
20476 if (Lo && Subtarget->hasSSE3()) {
20477 Shuffle = X86ISD::MOVDDUP;
20478 ShuffleVT = MVT::v2f64;
20480 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20481 // than the UNPCK variants.
20482 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20483 ShuffleVT = MVT::v4f32;
20485 if (Depth == 1 && Root->getOpcode() == Shuffle)
20486 return false; // Nothing to do!
20487 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20488 DCI.AddToWorklist(Op.getNode());
20489 if (Shuffle == X86ISD::MOVDDUP)
20490 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20492 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20493 DCI.AddToWorklist(Op.getNode());
20494 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20498 if (Subtarget->hasSSE3() &&
20499 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20500 bool Lo = Mask.equals(0, 0, 2, 2);
20501 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20502 MVT ShuffleVT = MVT::v4f32;
20503 if (Depth == 1 && Root->getOpcode() == Shuffle)
20504 return false; // Nothing to do!
20505 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20506 DCI.AddToWorklist(Op.getNode());
20507 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20508 DCI.AddToWorklist(Op.getNode());
20509 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20513 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20514 bool Lo = Mask.equals(0, 0, 1, 1);
20515 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20516 MVT ShuffleVT = MVT::v4f32;
20517 if (Depth == 1 && Root->getOpcode() == Shuffle)
20518 return false; // Nothing to do!
20519 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20520 DCI.AddToWorklist(Op.getNode());
20521 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20522 DCI.AddToWorklist(Op.getNode());
20523 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20529 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20530 // variants as none of these have single-instruction variants that are
20531 // superior to the UNPCK formulation.
20532 if (!FloatDomain &&
20533 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20534 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20535 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20536 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20538 bool Lo = Mask[0] == 0;
20539 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20540 if (Depth == 1 && Root->getOpcode() == Shuffle)
20541 return false; // Nothing to do!
20543 switch (Mask.size()) {
20545 ShuffleVT = MVT::v8i16;
20548 ShuffleVT = MVT::v16i8;
20551 llvm_unreachable("Impossible mask size!");
20553 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20554 DCI.AddToWorklist(Op.getNode());
20555 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20556 DCI.AddToWorklist(Op.getNode());
20557 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20562 // Don't try to re-form single instruction chains under any circumstances now
20563 // that we've done encoding canonicalization for them.
20567 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20568 // can replace them with a single PSHUFB instruction profitably. Intel's
20569 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20570 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20571 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20572 SmallVector<SDValue, 16> PSHUFBMask;
20573 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20574 int Ratio = 16 / Mask.size();
20575 for (unsigned i = 0; i < 16; ++i) {
20576 if (Mask[i / Ratio] == SM_SentinelUndef) {
20577 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20580 int M = Mask[i / Ratio] != SM_SentinelZero
20581 ? Ratio * Mask[i / Ratio] + i % Ratio
20583 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20585 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20586 DCI.AddToWorklist(Op.getNode());
20587 SDValue PSHUFBMaskOp =
20588 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20589 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20590 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20591 DCI.AddToWorklist(Op.getNode());
20592 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20597 // Failed to find any combines.
20601 /// \brief Fully generic combining of x86 shuffle instructions.
20603 /// This should be the last combine run over the x86 shuffle instructions. Once
20604 /// they have been fully optimized, this will recursively consider all chains
20605 /// of single-use shuffle instructions, build a generic model of the cumulative
20606 /// shuffle operation, and check for simpler instructions which implement this
20607 /// operation. We use this primarily for two purposes:
20609 /// 1) Collapse generic shuffles to specialized single instructions when
20610 /// equivalent. In most cases, this is just an encoding size win, but
20611 /// sometimes we will collapse multiple generic shuffles into a single
20612 /// special-purpose shuffle.
20613 /// 2) Look for sequences of shuffle instructions with 3 or more total
20614 /// instructions, and replace them with the slightly more expensive SSSE3
20615 /// PSHUFB instruction if available. We do this as the last combining step
20616 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20617 /// a suitable short sequence of other instructions. The PHUFB will either
20618 /// use a register or have to read from memory and so is slightly (but only
20619 /// slightly) more expensive than the other shuffle instructions.
20621 /// Because this is inherently a quadratic operation (for each shuffle in
20622 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20623 /// This should never be an issue in practice as the shuffle lowering doesn't
20624 /// produce sequences of more than 8 instructions.
20626 /// FIXME: We will currently miss some cases where the redundant shuffling
20627 /// would simplify under the threshold for PSHUFB formation because of
20628 /// combine-ordering. To fix this, we should do the redundant instruction
20629 /// combining in this recursive walk.
20630 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20631 ArrayRef<int> RootMask,
20632 int Depth, bool HasPSHUFB,
20634 TargetLowering::DAGCombinerInfo &DCI,
20635 const X86Subtarget *Subtarget) {
20636 // Bound the depth of our recursive combine because this is ultimately
20637 // quadratic in nature.
20641 // Directly rip through bitcasts to find the underlying operand.
20642 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20643 Op = Op.getOperand(0);
20645 MVT VT = Op.getSimpleValueType();
20646 if (!VT.isVector())
20647 return false; // Bail if we hit a non-vector.
20648 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20649 // version should be added.
20650 if (VT.getSizeInBits() != 128)
20653 assert(Root.getSimpleValueType().isVector() &&
20654 "Shuffles operate on vector types!");
20655 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20656 "Can only combine shuffles of the same vector register size.");
20658 if (!isTargetShuffle(Op.getOpcode()))
20660 SmallVector<int, 16> OpMask;
20662 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20663 // We only can combine unary shuffles which we can decode the mask for.
20664 if (!HaveMask || !IsUnary)
20667 assert(VT.getVectorNumElements() == OpMask.size() &&
20668 "Different mask size from vector size!");
20669 assert(((RootMask.size() > OpMask.size() &&
20670 RootMask.size() % OpMask.size() == 0) ||
20671 (OpMask.size() > RootMask.size() &&
20672 OpMask.size() % RootMask.size() == 0) ||
20673 OpMask.size() == RootMask.size()) &&
20674 "The smaller number of elements must divide the larger.");
20675 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20676 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20677 assert(((RootRatio == 1 && OpRatio == 1) ||
20678 (RootRatio == 1) != (OpRatio == 1)) &&
20679 "Must not have a ratio for both incoming and op masks!");
20681 SmallVector<int, 16> Mask;
20682 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20684 // Merge this shuffle operation's mask into our accumulated mask. Note that
20685 // this shuffle's mask will be the first applied to the input, followed by the
20686 // root mask to get us all the way to the root value arrangement. The reason
20687 // for this order is that we are recursing up the operation chain.
20688 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20689 int RootIdx = i / RootRatio;
20690 if (RootMask[RootIdx] < 0) {
20691 // This is a zero or undef lane, we're done.
20692 Mask.push_back(RootMask[RootIdx]);
20696 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20697 int OpIdx = RootMaskedIdx / OpRatio;
20698 if (OpMask[OpIdx] < 0) {
20699 // The incoming lanes are zero or undef, it doesn't matter which ones we
20701 Mask.push_back(OpMask[OpIdx]);
20705 // Ok, we have non-zero lanes, map them through.
20706 Mask.push_back(OpMask[OpIdx] * OpRatio +
20707 RootMaskedIdx % OpRatio);
20710 // See if we can recurse into the operand to combine more things.
20711 switch (Op.getOpcode()) {
20712 case X86ISD::PSHUFB:
20714 case X86ISD::PSHUFD:
20715 case X86ISD::PSHUFHW:
20716 case X86ISD::PSHUFLW:
20717 if (Op.getOperand(0).hasOneUse() &&
20718 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20719 HasPSHUFB, DAG, DCI, Subtarget))
20723 case X86ISD::UNPCKL:
20724 case X86ISD::UNPCKH:
20725 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20726 // We can't check for single use, we have to check that this shuffle is the only user.
20727 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20728 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20729 HasPSHUFB, DAG, DCI, Subtarget))
20734 // Minor canonicalization of the accumulated shuffle mask to make it easier
20735 // to match below. All this does is detect masks with squential pairs of
20736 // elements, and shrink them to the half-width mask. It does this in a loop
20737 // so it will reduce the size of the mask to the minimal width mask which
20738 // performs an equivalent shuffle.
20739 SmallVector<int, 16> WidenedMask;
20740 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20741 Mask = std::move(WidenedMask);
20742 WidenedMask.clear();
20745 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20749 /// \brief Get the PSHUF-style mask from PSHUF node.
20751 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20752 /// PSHUF-style masks that can be reused with such instructions.
20753 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20754 SmallVector<int, 4> Mask;
20756 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20760 switch (N.getOpcode()) {
20761 case X86ISD::PSHUFD:
20763 case X86ISD::PSHUFLW:
20766 case X86ISD::PSHUFHW:
20767 Mask.erase(Mask.begin(), Mask.begin() + 4);
20768 for (int &M : Mask)
20772 llvm_unreachable("No valid shuffle instruction found!");
20776 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20778 /// We walk up the chain and look for a combinable shuffle, skipping over
20779 /// shuffles that we could hoist this shuffle's transformation past without
20780 /// altering anything.
20782 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20784 TargetLowering::DAGCombinerInfo &DCI) {
20785 assert(N.getOpcode() == X86ISD::PSHUFD &&
20786 "Called with something other than an x86 128-bit half shuffle!");
20789 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20790 // of the shuffles in the chain so that we can form a fresh chain to replace
20792 SmallVector<SDValue, 8> Chain;
20793 SDValue V = N.getOperand(0);
20794 for (; V.hasOneUse(); V = V.getOperand(0)) {
20795 switch (V.getOpcode()) {
20797 return SDValue(); // Nothing combined!
20800 // Skip bitcasts as we always know the type for the target specific
20804 case X86ISD::PSHUFD:
20805 // Found another dword shuffle.
20808 case X86ISD::PSHUFLW:
20809 // Check that the low words (being shuffled) are the identity in the
20810 // dword shuffle, and the high words are self-contained.
20811 if (Mask[0] != 0 || Mask[1] != 1 ||
20812 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20815 Chain.push_back(V);
20818 case X86ISD::PSHUFHW:
20819 // Check that the high words (being shuffled) are the identity in the
20820 // dword shuffle, and the low words are self-contained.
20821 if (Mask[2] != 2 || Mask[3] != 3 ||
20822 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20825 Chain.push_back(V);
20828 case X86ISD::UNPCKL:
20829 case X86ISD::UNPCKH:
20830 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20831 // shuffle into a preceding word shuffle.
20832 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20835 // Search for a half-shuffle which we can combine with.
20836 unsigned CombineOp =
20837 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20838 if (V.getOperand(0) != V.getOperand(1) ||
20839 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20841 Chain.push_back(V);
20842 V = V.getOperand(0);
20844 switch (V.getOpcode()) {
20846 return SDValue(); // Nothing to combine.
20848 case X86ISD::PSHUFLW:
20849 case X86ISD::PSHUFHW:
20850 if (V.getOpcode() == CombineOp)
20853 Chain.push_back(V);
20857 V = V.getOperand(0);
20861 } while (V.hasOneUse());
20864 // Break out of the loop if we break out of the switch.
20868 if (!V.hasOneUse())
20869 // We fell out of the loop without finding a viable combining instruction.
20872 // Merge this node's mask and our incoming mask.
20873 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20874 for (int &M : Mask)
20876 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20877 getV4X86ShuffleImm8ForMask(Mask, DAG));
20879 // Rebuild the chain around this new shuffle.
20880 while (!Chain.empty()) {
20881 SDValue W = Chain.pop_back_val();
20883 if (V.getValueType() != W.getOperand(0).getValueType())
20884 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20886 switch (W.getOpcode()) {
20888 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20890 case X86ISD::UNPCKL:
20891 case X86ISD::UNPCKH:
20892 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20895 case X86ISD::PSHUFD:
20896 case X86ISD::PSHUFLW:
20897 case X86ISD::PSHUFHW:
20898 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20902 if (V.getValueType() != N.getValueType())
20903 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20905 // Return the new chain to replace N.
20909 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20911 /// We walk up the chain, skipping shuffles of the other half and looking
20912 /// through shuffles which switch halves trying to find a shuffle of the same
20913 /// pair of dwords.
20914 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20916 TargetLowering::DAGCombinerInfo &DCI) {
20918 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20919 "Called with something other than an x86 128-bit half shuffle!");
20921 unsigned CombineOpcode = N.getOpcode();
20923 // Walk up a single-use chain looking for a combinable shuffle.
20924 SDValue V = N.getOperand(0);
20925 for (; V.hasOneUse(); V = V.getOperand(0)) {
20926 switch (V.getOpcode()) {
20928 return false; // Nothing combined!
20931 // Skip bitcasts as we always know the type for the target specific
20935 case X86ISD::PSHUFLW:
20936 case X86ISD::PSHUFHW:
20937 if (V.getOpcode() == CombineOpcode)
20940 // Other-half shuffles are no-ops.
20943 // Break out of the loop if we break out of the switch.
20947 if (!V.hasOneUse())
20948 // We fell out of the loop without finding a viable combining instruction.
20951 // Combine away the bottom node as its shuffle will be accumulated into
20952 // a preceding shuffle.
20953 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20955 // Record the old value.
20958 // Merge this node's mask and our incoming mask (adjusted to account for all
20959 // the pshufd instructions encountered).
20960 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20961 for (int &M : Mask)
20963 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20964 getV4X86ShuffleImm8ForMask(Mask, DAG));
20966 // Check that the shuffles didn't cancel each other out. If not, we need to
20967 // combine to the new one.
20969 // Replace the combinable shuffle with the combined one, updating all users
20970 // so that we re-evaluate the chain here.
20971 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20976 /// \brief Try to combine x86 target specific shuffles.
20977 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20978 TargetLowering::DAGCombinerInfo &DCI,
20979 const X86Subtarget *Subtarget) {
20981 MVT VT = N.getSimpleValueType();
20982 SmallVector<int, 4> Mask;
20984 switch (N.getOpcode()) {
20985 case X86ISD::PSHUFD:
20986 case X86ISD::PSHUFLW:
20987 case X86ISD::PSHUFHW:
20988 Mask = getPSHUFShuffleMask(N);
20989 assert(Mask.size() == 4);
20995 // Nuke no-op shuffles that show up after combining.
20996 if (isNoopShuffleMask(Mask))
20997 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20999 // Look for simplifications involving one or two shuffle instructions.
21000 SDValue V = N.getOperand(0);
21001 switch (N.getOpcode()) {
21004 case X86ISD::PSHUFLW:
21005 case X86ISD::PSHUFHW:
21006 assert(VT == MVT::v8i16);
21009 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21010 return SDValue(); // We combined away this shuffle, so we're done.
21012 // See if this reduces to a PSHUFD which is no more expensive and can
21013 // combine with more operations. Note that it has to at least flip the
21014 // dwords as otherwise it would have been removed as a no-op.
21015 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21016 int DMask[] = {0, 1, 2, 3};
21017 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21018 DMask[DOffset + 0] = DOffset + 1;
21019 DMask[DOffset + 1] = DOffset + 0;
21020 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21021 DCI.AddToWorklist(V.getNode());
21022 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21023 getV4X86ShuffleImm8ForMask(DMask, DAG));
21024 DCI.AddToWorklist(V.getNode());
21025 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21028 // Look for shuffle patterns which can be implemented as a single unpack.
21029 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21030 // only works when we have a PSHUFD followed by two half-shuffles.
21031 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21032 (V.getOpcode() == X86ISD::PSHUFLW ||
21033 V.getOpcode() == X86ISD::PSHUFHW) &&
21034 V.getOpcode() != N.getOpcode() &&
21036 SDValue D = V.getOperand(0);
21037 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21038 D = D.getOperand(0);
21039 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21040 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21041 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21042 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21043 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21045 for (int i = 0; i < 4; ++i) {
21046 WordMask[i + NOffset] = Mask[i] + NOffset;
21047 WordMask[i + VOffset] = VMask[i] + VOffset;
21049 // Map the word mask through the DWord mask.
21051 for (int i = 0; i < 8; ++i)
21052 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21053 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21054 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21055 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21056 std::begin(UnpackLoMask)) ||
21057 std::equal(std::begin(MappedMask), std::end(MappedMask),
21058 std::begin(UnpackHiMask))) {
21059 // We can replace all three shuffles with an unpack.
21060 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21061 DCI.AddToWorklist(V.getNode());
21062 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21064 DL, MVT::v8i16, V, V);
21071 case X86ISD::PSHUFD:
21072 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21081 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21083 /// We combine this directly on the abstract vector shuffle nodes so it is
21084 /// easier to generically match. We also insert dummy vector shuffle nodes for
21085 /// the operands which explicitly discard the lanes which are unused by this
21086 /// operation to try to flow through the rest of the combiner the fact that
21087 /// they're unused.
21088 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21090 EVT VT = N->getValueType(0);
21092 // We only handle target-independent shuffles.
21093 // FIXME: It would be easy and harmless to use the target shuffle mask
21094 // extraction tool to support more.
21095 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21098 auto *SVN = cast<ShuffleVectorSDNode>(N);
21099 ArrayRef<int> Mask = SVN->getMask();
21100 SDValue V1 = N->getOperand(0);
21101 SDValue V2 = N->getOperand(1);
21103 // We require the first shuffle operand to be the SUB node, and the second to
21104 // be the ADD node.
21105 // FIXME: We should support the commuted patterns.
21106 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21109 // If there are other uses of these operations we can't fold them.
21110 if (!V1->hasOneUse() || !V2->hasOneUse())
21113 // Ensure that both operations have the same operands. Note that we can
21114 // commute the FADD operands.
21115 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21116 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21117 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21120 // We're looking for blends between FADD and FSUB nodes. We insist on these
21121 // nodes being lined up in a specific expected pattern.
21122 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21123 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21124 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21127 // Only specific types are legal at this point, assert so we notice if and
21128 // when these change.
21129 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21130 VT == MVT::v4f64) &&
21131 "Unknown vector type encountered!");
21133 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21136 /// PerformShuffleCombine - Performs several different shuffle combines.
21137 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21138 TargetLowering::DAGCombinerInfo &DCI,
21139 const X86Subtarget *Subtarget) {
21141 SDValue N0 = N->getOperand(0);
21142 SDValue N1 = N->getOperand(1);
21143 EVT VT = N->getValueType(0);
21145 // Don't create instructions with illegal types after legalize types has run.
21146 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21147 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21150 // If we have legalized the vector types, look for blends of FADD and FSUB
21151 // nodes that we can fuse into an ADDSUB node.
21152 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21153 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21156 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21157 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21158 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21159 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21161 // During Type Legalization, when promoting illegal vector types,
21162 // the backend might introduce new shuffle dag nodes and bitcasts.
21164 // This code performs the following transformation:
21165 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21166 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21168 // We do this only if both the bitcast and the BINOP dag nodes have
21169 // one use. Also, perform this transformation only if the new binary
21170 // operation is legal. This is to avoid introducing dag nodes that
21171 // potentially need to be further expanded (or custom lowered) into a
21172 // less optimal sequence of dag nodes.
21173 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21174 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21175 N0.getOpcode() == ISD::BITCAST) {
21176 SDValue BC0 = N0.getOperand(0);
21177 EVT SVT = BC0.getValueType();
21178 unsigned Opcode = BC0.getOpcode();
21179 unsigned NumElts = VT.getVectorNumElements();
21181 if (BC0.hasOneUse() && SVT.isVector() &&
21182 SVT.getVectorNumElements() * 2 == NumElts &&
21183 TLI.isOperationLegal(Opcode, VT)) {
21184 bool CanFold = false;
21196 unsigned SVTNumElts = SVT.getVectorNumElements();
21197 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21198 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21199 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21200 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21201 CanFold = SVOp->getMaskElt(i) < 0;
21204 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21205 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21206 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21207 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21212 // Only handle 128 wide vector from here on.
21213 if (!VT.is128BitVector())
21216 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21217 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21218 // consecutive, non-overlapping, and in the right order.
21219 SmallVector<SDValue, 16> Elts;
21220 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21221 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21223 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21227 if (isTargetShuffle(N->getOpcode())) {
21229 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21230 if (Shuffle.getNode())
21233 // Try recursively combining arbitrary sequences of x86 shuffle
21234 // instructions into higher-order shuffles. We do this after combining
21235 // specific PSHUF instruction sequences into their minimal form so that we
21236 // can evaluate how many specialized shuffle instructions are involved in
21237 // a particular chain.
21238 SmallVector<int, 1> NonceMask; // Just a placeholder.
21239 NonceMask.push_back(0);
21240 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21241 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21243 return SDValue(); // This routine will use CombineTo to replace N.
21249 /// PerformTruncateCombine - Converts truncate operation to
21250 /// a sequence of vector shuffle operations.
21251 /// It is possible when we truncate 256-bit vector to 128-bit vector
21252 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21253 TargetLowering::DAGCombinerInfo &DCI,
21254 const X86Subtarget *Subtarget) {
21258 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21259 /// specific shuffle of a load can be folded into a single element load.
21260 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21261 /// shuffles have been customed lowered so we need to handle those here.
21262 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21263 TargetLowering::DAGCombinerInfo &DCI) {
21264 if (DCI.isBeforeLegalizeOps())
21267 SDValue InVec = N->getOperand(0);
21268 SDValue EltNo = N->getOperand(1);
21270 if (!isa<ConstantSDNode>(EltNo))
21273 EVT VT = InVec.getValueType();
21275 if (InVec.getOpcode() == ISD::BITCAST) {
21276 // Don't duplicate a load with other uses.
21277 if (!InVec.hasOneUse())
21279 EVT BCVT = InVec.getOperand(0).getValueType();
21280 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21282 InVec = InVec.getOperand(0);
21285 if (!isTargetShuffle(InVec.getOpcode()))
21288 // Don't duplicate a load with other uses.
21289 if (!InVec.hasOneUse())
21292 SmallVector<int, 16> ShuffleMask;
21294 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21298 // Select the input vector, guarding against out of range extract vector.
21299 unsigned NumElems = VT.getVectorNumElements();
21300 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21301 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21302 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21303 : InVec.getOperand(1);
21305 // If inputs to shuffle are the same for both ops, then allow 2 uses
21306 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21308 if (LdNode.getOpcode() == ISD::BITCAST) {
21309 // Don't duplicate a load with other uses.
21310 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21313 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21314 LdNode = LdNode.getOperand(0);
21317 if (!ISD::isNormalLoad(LdNode.getNode()))
21320 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21322 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21325 EVT EltVT = N->getValueType(0);
21326 // If there's a bitcast before the shuffle, check if the load type and
21327 // alignment is valid.
21328 unsigned Align = LN0->getAlignment();
21329 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21330 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21331 EltVT.getTypeForEVT(*DAG.getContext()));
21333 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21336 // All checks match so transform back to vector_shuffle so that DAG combiner
21337 // can finish the job
21340 // Create shuffle node taking into account the case that its a unary shuffle
21341 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21342 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21343 InVec.getOperand(0), Shuffle,
21345 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21346 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21350 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21351 /// generation and convert it from being a bunch of shuffles and extracts
21352 /// to a simple store and scalar loads to extract the elements.
21353 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21354 TargetLowering::DAGCombinerInfo &DCI) {
21355 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21356 if (NewOp.getNode())
21359 SDValue InputVector = N->getOperand(0);
21361 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21362 // from mmx to v2i32 has a single usage.
21363 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21364 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21365 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21366 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21367 N->getValueType(0),
21368 InputVector.getNode()->getOperand(0));
21370 // Only operate on vectors of 4 elements, where the alternative shuffling
21371 // gets to be more expensive.
21372 if (InputVector.getValueType() != MVT::v4i32)
21375 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21376 // single use which is a sign-extend or zero-extend, and all elements are
21378 SmallVector<SDNode *, 4> Uses;
21379 unsigned ExtractedElements = 0;
21380 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21381 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21382 if (UI.getUse().getResNo() != InputVector.getResNo())
21385 SDNode *Extract = *UI;
21386 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21389 if (Extract->getValueType(0) != MVT::i32)
21391 if (!Extract->hasOneUse())
21393 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21394 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21396 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21399 // Record which element was extracted.
21400 ExtractedElements |=
21401 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21403 Uses.push_back(Extract);
21406 // If not all the elements were used, this may not be worthwhile.
21407 if (ExtractedElements != 15)
21410 // Ok, we've now decided to do the transformation.
21411 SDLoc dl(InputVector);
21413 // Store the value to a temporary stack slot.
21414 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21415 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21416 MachinePointerInfo(), false, false, 0);
21418 // Replace each use (extract) with a load of the appropriate element.
21419 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21420 UE = Uses.end(); UI != UE; ++UI) {
21421 SDNode *Extract = *UI;
21423 // cOMpute the element's address.
21424 SDValue Idx = Extract->getOperand(1);
21426 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21427 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21428 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21429 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21431 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21432 StackPtr, OffsetVal);
21434 // Load the scalar.
21435 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21436 ScalarAddr, MachinePointerInfo(),
21437 false, false, false, 0);
21439 // Replace the exact with the load.
21440 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21443 // The replacement was made in place; don't return anything.
21447 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21448 static std::pair<unsigned, bool>
21449 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21450 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21451 if (!VT.isVector())
21452 return std::make_pair(0, false);
21454 bool NeedSplit = false;
21455 switch (VT.getSimpleVT().SimpleTy) {
21456 default: return std::make_pair(0, false);
21460 if (!Subtarget->hasAVX2())
21462 if (!Subtarget->hasAVX())
21463 return std::make_pair(0, false);
21468 if (!Subtarget->hasSSE2())
21469 return std::make_pair(0, false);
21472 // SSE2 has only a small subset of the operations.
21473 bool hasUnsigned = Subtarget->hasSSE41() ||
21474 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21475 bool hasSigned = Subtarget->hasSSE41() ||
21476 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21478 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21481 // Check for x CC y ? x : y.
21482 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21483 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21488 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21491 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21494 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21497 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21499 // Check for x CC y ? y : x -- a min/max with reversed arms.
21500 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21501 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21506 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21509 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21512 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21515 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21519 return std::make_pair(Opc, NeedSplit);
21523 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21524 const X86Subtarget *Subtarget) {
21526 SDValue Cond = N->getOperand(0);
21527 SDValue LHS = N->getOperand(1);
21528 SDValue RHS = N->getOperand(2);
21530 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21531 SDValue CondSrc = Cond->getOperand(0);
21532 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21533 Cond = CondSrc->getOperand(0);
21536 MVT VT = N->getSimpleValueType(0);
21537 MVT EltVT = VT.getVectorElementType();
21538 unsigned NumElems = VT.getVectorNumElements();
21539 // There is no blend with immediate in AVX-512.
21540 if (VT.is512BitVector())
21543 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21545 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21548 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21551 // A vselect where all conditions and data are constants can be optimized into
21552 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21553 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21554 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21557 unsigned MaskValue = 0;
21558 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21561 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21562 for (unsigned i = 0; i < NumElems; ++i) {
21563 // Be sure we emit undef where we can.
21564 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21565 ShuffleMask[i] = -1;
21567 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21570 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21573 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21575 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21576 TargetLowering::DAGCombinerInfo &DCI,
21577 const X86Subtarget *Subtarget) {
21579 SDValue Cond = N->getOperand(0);
21580 // Get the LHS/RHS of the select.
21581 SDValue LHS = N->getOperand(1);
21582 SDValue RHS = N->getOperand(2);
21583 EVT VT = LHS.getValueType();
21584 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21586 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21587 // instructions match the semantics of the common C idiom x<y?x:y but not
21588 // x<=y?x:y, because of how they handle negative zero (which can be
21589 // ignored in unsafe-math mode).
21590 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21591 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21592 (Subtarget->hasSSE2() ||
21593 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21594 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21596 unsigned Opcode = 0;
21597 // Check for x CC y ? x : y.
21598 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21599 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21603 // Converting this to a min would handle NaNs incorrectly, and swapping
21604 // the operands would cause it to handle comparisons between positive
21605 // and negative zero incorrectly.
21606 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21607 if (!DAG.getTarget().Options.UnsafeFPMath &&
21608 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21610 std::swap(LHS, RHS);
21612 Opcode = X86ISD::FMIN;
21615 // Converting this to a min would handle comparisons between positive
21616 // and negative zero incorrectly.
21617 if (!DAG.getTarget().Options.UnsafeFPMath &&
21618 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21620 Opcode = X86ISD::FMIN;
21623 // Converting this to a min would handle both negative zeros and NaNs
21624 // incorrectly, but we can swap the operands to fix both.
21625 std::swap(LHS, RHS);
21629 Opcode = X86ISD::FMIN;
21633 // Converting this to a max would handle comparisons between positive
21634 // and negative zero incorrectly.
21635 if (!DAG.getTarget().Options.UnsafeFPMath &&
21636 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21638 Opcode = X86ISD::FMAX;
21641 // Converting this to a max would handle NaNs incorrectly, and swapping
21642 // the operands would cause it to handle comparisons between positive
21643 // and negative zero incorrectly.
21644 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21645 if (!DAG.getTarget().Options.UnsafeFPMath &&
21646 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21648 std::swap(LHS, RHS);
21650 Opcode = X86ISD::FMAX;
21653 // Converting this to a max would handle both negative zeros and NaNs
21654 // incorrectly, but we can swap the operands to fix both.
21655 std::swap(LHS, RHS);
21659 Opcode = X86ISD::FMAX;
21662 // Check for x CC y ? y : x -- a min/max with reversed arms.
21663 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21664 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21668 // Converting this to a min would handle comparisons between positive
21669 // and negative zero incorrectly, and swapping the operands would
21670 // cause it to handle NaNs incorrectly.
21671 if (!DAG.getTarget().Options.UnsafeFPMath &&
21672 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21673 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21675 std::swap(LHS, RHS);
21677 Opcode = X86ISD::FMIN;
21680 // Converting this to a min would handle NaNs incorrectly.
21681 if (!DAG.getTarget().Options.UnsafeFPMath &&
21682 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21684 Opcode = X86ISD::FMIN;
21687 // Converting this to a min would handle both negative zeros and NaNs
21688 // incorrectly, but we can swap the operands to fix both.
21689 std::swap(LHS, RHS);
21693 Opcode = X86ISD::FMIN;
21697 // Converting this to a max would handle NaNs incorrectly.
21698 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21700 Opcode = X86ISD::FMAX;
21703 // Converting this to a max would handle comparisons between positive
21704 // and negative zero incorrectly, and swapping the operands would
21705 // cause it to handle NaNs incorrectly.
21706 if (!DAG.getTarget().Options.UnsafeFPMath &&
21707 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21708 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21710 std::swap(LHS, RHS);
21712 Opcode = X86ISD::FMAX;
21715 // Converting this to a max would handle both negative zeros and NaNs
21716 // incorrectly, but we can swap the operands to fix both.
21717 std::swap(LHS, RHS);
21721 Opcode = X86ISD::FMAX;
21727 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21730 EVT CondVT = Cond.getValueType();
21731 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21732 CondVT.getVectorElementType() == MVT::i1) {
21733 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21734 // lowering on KNL. In this case we convert it to
21735 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21736 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21737 // Since SKX these selects have a proper lowering.
21738 EVT OpVT = LHS.getValueType();
21739 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21740 (OpVT.getVectorElementType() == MVT::i8 ||
21741 OpVT.getVectorElementType() == MVT::i16) &&
21742 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21743 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21744 DCI.AddToWorklist(Cond.getNode());
21745 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21748 // If this is a select between two integer constants, try to do some
21750 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21751 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21752 // Don't do this for crazy integer types.
21753 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21754 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21755 // so that TrueC (the true value) is larger than FalseC.
21756 bool NeedsCondInvert = false;
21758 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21759 // Efficiently invertible.
21760 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21761 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21762 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21763 NeedsCondInvert = true;
21764 std::swap(TrueC, FalseC);
21767 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21768 if (FalseC->getAPIntValue() == 0 &&
21769 TrueC->getAPIntValue().isPowerOf2()) {
21770 if (NeedsCondInvert) // Invert the condition if needed.
21771 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21772 DAG.getConstant(1, Cond.getValueType()));
21774 // Zero extend the condition if needed.
21775 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21777 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21778 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21779 DAG.getConstant(ShAmt, MVT::i8));
21782 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21783 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21784 if (NeedsCondInvert) // Invert the condition if needed.
21785 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21786 DAG.getConstant(1, Cond.getValueType()));
21788 // Zero extend the condition if needed.
21789 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21790 FalseC->getValueType(0), Cond);
21791 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21792 SDValue(FalseC, 0));
21795 // Optimize cases that will turn into an LEA instruction. This requires
21796 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21797 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21798 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21799 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21801 bool isFastMultiplier = false;
21803 switch ((unsigned char)Diff) {
21805 case 1: // result = add base, cond
21806 case 2: // result = lea base( , cond*2)
21807 case 3: // result = lea base(cond, cond*2)
21808 case 4: // result = lea base( , cond*4)
21809 case 5: // result = lea base(cond, cond*4)
21810 case 8: // result = lea base( , cond*8)
21811 case 9: // result = lea base(cond, cond*8)
21812 isFastMultiplier = true;
21817 if (isFastMultiplier) {
21818 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21819 if (NeedsCondInvert) // Invert the condition if needed.
21820 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21821 DAG.getConstant(1, Cond.getValueType()));
21823 // Zero extend the condition if needed.
21824 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21826 // Scale the condition by the difference.
21828 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21829 DAG.getConstant(Diff, Cond.getValueType()));
21831 // Add the base if non-zero.
21832 if (FalseC->getAPIntValue() != 0)
21833 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21834 SDValue(FalseC, 0));
21841 // Canonicalize max and min:
21842 // (x > y) ? x : y -> (x >= y) ? x : y
21843 // (x < y) ? x : y -> (x <= y) ? x : y
21844 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21845 // the need for an extra compare
21846 // against zero. e.g.
21847 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21849 // testl %edi, %edi
21851 // cmovgl %edi, %eax
21855 // cmovsl %eax, %edi
21856 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21857 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21858 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21859 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21864 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21865 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21866 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21867 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21872 // Early exit check
21873 if (!TLI.isTypeLegal(VT))
21876 // Match VSELECTs into subs with unsigned saturation.
21877 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21878 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21879 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21880 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21881 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21883 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21884 // left side invert the predicate to simplify logic below.
21886 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21888 CC = ISD::getSetCCInverse(CC, true);
21889 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21893 if (Other.getNode() && Other->getNumOperands() == 2 &&
21894 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21895 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21896 SDValue CondRHS = Cond->getOperand(1);
21898 // Look for a general sub with unsigned saturation first.
21899 // x >= y ? x-y : 0 --> subus x, y
21900 // x > y ? x-y : 0 --> subus x, y
21901 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21902 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21903 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21905 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21906 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21907 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21908 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21909 // If the RHS is a constant we have to reverse the const
21910 // canonicalization.
21911 // x > C-1 ? x+-C : 0 --> subus x, C
21912 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21913 CondRHSConst->getAPIntValue() ==
21914 (-OpRHSConst->getAPIntValue() - 1))
21915 return DAG.getNode(
21916 X86ISD::SUBUS, DL, VT, OpLHS,
21917 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21919 // Another special case: If C was a sign bit, the sub has been
21920 // canonicalized into a xor.
21921 // FIXME: Would it be better to use computeKnownBits to determine
21922 // whether it's safe to decanonicalize the xor?
21923 // x s< 0 ? x^C : 0 --> subus x, C
21924 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21925 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21926 OpRHSConst->getAPIntValue().isSignBit())
21927 // Note that we have to rebuild the RHS constant here to ensure we
21928 // don't rely on particular values of undef lanes.
21929 return DAG.getNode(
21930 X86ISD::SUBUS, DL, VT, OpLHS,
21931 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21936 // Try to match a min/max vector operation.
21937 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21938 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21939 unsigned Opc = ret.first;
21940 bool NeedSplit = ret.second;
21942 if (Opc && NeedSplit) {
21943 unsigned NumElems = VT.getVectorNumElements();
21944 // Extract the LHS vectors
21945 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21946 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21948 // Extract the RHS vectors
21949 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21950 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21952 // Create min/max for each subvector
21953 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21954 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21956 // Merge the result
21957 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21959 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21962 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21963 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21964 // Check if SETCC has already been promoted
21965 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21966 // Check that condition value type matches vselect operand type
21969 assert(Cond.getValueType().isVector() &&
21970 "vector select expects a vector selector!");
21972 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21973 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21975 if (!TValIsAllOnes && !FValIsAllZeros) {
21976 // Try invert the condition if true value is not all 1s and false value
21978 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21979 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21981 if (TValIsAllZeros || FValIsAllOnes) {
21982 SDValue CC = Cond.getOperand(2);
21983 ISD::CondCode NewCC =
21984 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21985 Cond.getOperand(0).getValueType().isInteger());
21986 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21987 std::swap(LHS, RHS);
21988 TValIsAllOnes = FValIsAllOnes;
21989 FValIsAllZeros = TValIsAllZeros;
21993 if (TValIsAllOnes || FValIsAllZeros) {
21996 if (TValIsAllOnes && FValIsAllZeros)
21998 else if (TValIsAllOnes)
21999 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22000 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22001 else if (FValIsAllZeros)
22002 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22003 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22005 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22009 // Try to fold this VSELECT into a MOVSS/MOVSD
22010 if (N->getOpcode() == ISD::VSELECT &&
22011 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22012 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22013 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22014 bool CanFold = false;
22015 unsigned NumElems = Cond.getNumOperands();
22019 if (isZero(Cond.getOperand(0))) {
22022 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22023 // fold (vselect <0,-1> -> (movsd A, B)
22024 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22025 CanFold = isAllOnes(Cond.getOperand(i));
22026 } else if (isAllOnes(Cond.getOperand(0))) {
22030 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22031 // fold (vselect <-1,0> -> (movsd B, A)
22032 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22033 CanFold = isZero(Cond.getOperand(i));
22037 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22038 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22039 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22042 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22043 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22044 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22045 // (v2i64 (bitcast B)))))
22047 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22048 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22049 // (v2f64 (bitcast B)))))
22051 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22052 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22053 // (v2i64 (bitcast A)))))
22055 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22056 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22057 // (v2f64 (bitcast A)))))
22059 CanFold = (isZero(Cond.getOperand(0)) &&
22060 isZero(Cond.getOperand(1)) &&
22061 isAllOnes(Cond.getOperand(2)) &&
22062 isAllOnes(Cond.getOperand(3)));
22064 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22065 isAllOnes(Cond.getOperand(1)) &&
22066 isZero(Cond.getOperand(2)) &&
22067 isZero(Cond.getOperand(3))) {
22069 std::swap(LHS, RHS);
22073 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22074 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22075 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22076 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22078 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22084 // If we know that this node is legal then we know that it is going to be
22085 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22086 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22087 // to simplify previous instructions.
22088 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22089 !DCI.isBeforeLegalize() &&
22090 // We explicitly check against v8i16 and v16i16 because, although
22091 // they're marked as Custom, they might only be legal when Cond is a
22092 // build_vector of constants. This will be taken care in a later
22094 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22095 VT != MVT::v8i16)) {
22096 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22098 // Don't optimize vector selects that map to mask-registers.
22102 // Check all uses of that condition operand to check whether it will be
22103 // consumed by non-BLEND instructions, which may depend on all bits are set
22105 for (SDNode::use_iterator I = Cond->use_begin(),
22106 E = Cond->use_end(); I != E; ++I)
22107 if (I->getOpcode() != ISD::VSELECT)
22108 // TODO: Add other opcodes eventually lowered into BLEND.
22111 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22112 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22114 APInt KnownZero, KnownOne;
22115 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22116 DCI.isBeforeLegalizeOps());
22117 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22118 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
22119 DCI.CommitTargetLoweringOpt(TLO);
22122 // We should generate an X86ISD::BLENDI from a vselect if its argument
22123 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22124 // constants. This specific pattern gets generated when we split a
22125 // selector for a 512 bit vector in a machine without AVX512 (but with
22126 // 256-bit vectors), during legalization:
22128 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22130 // Iff we find this pattern and the build_vectors are built from
22131 // constants, we translate the vselect into a shuffle_vector that we
22132 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22133 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
22134 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22135 if (Shuffle.getNode())
22142 // Check whether a boolean test is testing a boolean value generated by
22143 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22146 // Simplify the following patterns:
22147 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22148 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22149 // to (Op EFLAGS Cond)
22151 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22152 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22153 // to (Op EFLAGS !Cond)
22155 // where Op could be BRCOND or CMOV.
22157 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22158 // Quit if not CMP and SUB with its value result used.
22159 if (Cmp.getOpcode() != X86ISD::CMP &&
22160 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22163 // Quit if not used as a boolean value.
22164 if (CC != X86::COND_E && CC != X86::COND_NE)
22167 // Check CMP operands. One of them should be 0 or 1 and the other should be
22168 // an SetCC or extended from it.
22169 SDValue Op1 = Cmp.getOperand(0);
22170 SDValue Op2 = Cmp.getOperand(1);
22173 const ConstantSDNode* C = nullptr;
22174 bool needOppositeCond = (CC == X86::COND_E);
22175 bool checkAgainstTrue = false; // Is it a comparison against 1?
22177 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22179 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22181 else // Quit if all operands are not constants.
22184 if (C->getZExtValue() == 1) {
22185 needOppositeCond = !needOppositeCond;
22186 checkAgainstTrue = true;
22187 } else if (C->getZExtValue() != 0)
22188 // Quit if the constant is neither 0 or 1.
22191 bool truncatedToBoolWithAnd = false;
22192 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22193 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22194 SetCC.getOpcode() == ISD::TRUNCATE ||
22195 SetCC.getOpcode() == ISD::AND) {
22196 if (SetCC.getOpcode() == ISD::AND) {
22198 ConstantSDNode *CS;
22199 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22200 CS->getZExtValue() == 1)
22202 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22203 CS->getZExtValue() == 1)
22207 SetCC = SetCC.getOperand(OpIdx);
22208 truncatedToBoolWithAnd = true;
22210 SetCC = SetCC.getOperand(0);
22213 switch (SetCC.getOpcode()) {
22214 case X86ISD::SETCC_CARRY:
22215 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22216 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22217 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22218 // truncated to i1 using 'and'.
22219 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22221 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22222 "Invalid use of SETCC_CARRY!");
22224 case X86ISD::SETCC:
22225 // Set the condition code or opposite one if necessary.
22226 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22227 if (needOppositeCond)
22228 CC = X86::GetOppositeBranchCondition(CC);
22229 return SetCC.getOperand(1);
22230 case X86ISD::CMOV: {
22231 // Check whether false/true value has canonical one, i.e. 0 or 1.
22232 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22233 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22234 // Quit if true value is not a constant.
22237 // Quit if false value is not a constant.
22239 SDValue Op = SetCC.getOperand(0);
22240 // Skip 'zext' or 'trunc' node.
22241 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22242 Op.getOpcode() == ISD::TRUNCATE)
22243 Op = Op.getOperand(0);
22244 // A special case for rdrand/rdseed, where 0 is set if false cond is
22246 if ((Op.getOpcode() != X86ISD::RDRAND &&
22247 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22250 // Quit if false value is not the constant 0 or 1.
22251 bool FValIsFalse = true;
22252 if (FVal && FVal->getZExtValue() != 0) {
22253 if (FVal->getZExtValue() != 1)
22255 // If FVal is 1, opposite cond is needed.
22256 needOppositeCond = !needOppositeCond;
22257 FValIsFalse = false;
22259 // Quit if TVal is not the constant opposite of FVal.
22260 if (FValIsFalse && TVal->getZExtValue() != 1)
22262 if (!FValIsFalse && TVal->getZExtValue() != 0)
22264 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22265 if (needOppositeCond)
22266 CC = X86::GetOppositeBranchCondition(CC);
22267 return SetCC.getOperand(3);
22274 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22275 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22276 TargetLowering::DAGCombinerInfo &DCI,
22277 const X86Subtarget *Subtarget) {
22280 // If the flag operand isn't dead, don't touch this CMOV.
22281 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22284 SDValue FalseOp = N->getOperand(0);
22285 SDValue TrueOp = N->getOperand(1);
22286 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22287 SDValue Cond = N->getOperand(3);
22289 if (CC == X86::COND_E || CC == X86::COND_NE) {
22290 switch (Cond.getOpcode()) {
22294 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22295 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22296 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22302 Flags = checkBoolTestSetCCCombine(Cond, CC);
22303 if (Flags.getNode() &&
22304 // Extra check as FCMOV only supports a subset of X86 cond.
22305 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22306 SDValue Ops[] = { FalseOp, TrueOp,
22307 DAG.getConstant(CC, MVT::i8), Flags };
22308 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22311 // If this is a select between two integer constants, try to do some
22312 // optimizations. Note that the operands are ordered the opposite of SELECT
22314 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22315 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22316 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22317 // larger than FalseC (the false value).
22318 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22319 CC = X86::GetOppositeBranchCondition(CC);
22320 std::swap(TrueC, FalseC);
22321 std::swap(TrueOp, FalseOp);
22324 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22325 // This is efficient for any integer data type (including i8/i16) and
22327 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22328 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22329 DAG.getConstant(CC, MVT::i8), Cond);
22331 // Zero extend the condition if needed.
22332 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22334 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22335 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22336 DAG.getConstant(ShAmt, MVT::i8));
22337 if (N->getNumValues() == 2) // Dead flag value?
22338 return DCI.CombineTo(N, Cond, SDValue());
22342 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22343 // for any integer data type, including i8/i16.
22344 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22345 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22346 DAG.getConstant(CC, MVT::i8), Cond);
22348 // Zero extend the condition if needed.
22349 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22350 FalseC->getValueType(0), Cond);
22351 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22352 SDValue(FalseC, 0));
22354 if (N->getNumValues() == 2) // Dead flag value?
22355 return DCI.CombineTo(N, Cond, SDValue());
22359 // Optimize cases that will turn into an LEA instruction. This requires
22360 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22361 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22362 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22363 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22365 bool isFastMultiplier = false;
22367 switch ((unsigned char)Diff) {
22369 case 1: // result = add base, cond
22370 case 2: // result = lea base( , cond*2)
22371 case 3: // result = lea base(cond, cond*2)
22372 case 4: // result = lea base( , cond*4)
22373 case 5: // result = lea base(cond, cond*4)
22374 case 8: // result = lea base( , cond*8)
22375 case 9: // result = lea base(cond, cond*8)
22376 isFastMultiplier = true;
22381 if (isFastMultiplier) {
22382 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22383 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22384 DAG.getConstant(CC, MVT::i8), Cond);
22385 // Zero extend the condition if needed.
22386 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22388 // Scale the condition by the difference.
22390 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22391 DAG.getConstant(Diff, Cond.getValueType()));
22393 // Add the base if non-zero.
22394 if (FalseC->getAPIntValue() != 0)
22395 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22396 SDValue(FalseC, 0));
22397 if (N->getNumValues() == 2) // Dead flag value?
22398 return DCI.CombineTo(N, Cond, SDValue());
22405 // Handle these cases:
22406 // (select (x != c), e, c) -> select (x != c), e, x),
22407 // (select (x == c), c, e) -> select (x == c), x, e)
22408 // where the c is an integer constant, and the "select" is the combination
22409 // of CMOV and CMP.
22411 // The rationale for this change is that the conditional-move from a constant
22412 // needs two instructions, however, conditional-move from a register needs
22413 // only one instruction.
22415 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22416 // some instruction-combining opportunities. This opt needs to be
22417 // postponed as late as possible.
22419 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22420 // the DCI.xxxx conditions are provided to postpone the optimization as
22421 // late as possible.
22423 ConstantSDNode *CmpAgainst = nullptr;
22424 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22425 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22426 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22428 if (CC == X86::COND_NE &&
22429 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22430 CC = X86::GetOppositeBranchCondition(CC);
22431 std::swap(TrueOp, FalseOp);
22434 if (CC == X86::COND_E &&
22435 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22436 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22437 DAG.getConstant(CC, MVT::i8), Cond };
22438 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22446 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22447 const X86Subtarget *Subtarget) {
22448 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22450 default: return SDValue();
22451 // SSE/AVX/AVX2 blend intrinsics.
22452 case Intrinsic::x86_avx2_pblendvb:
22453 case Intrinsic::x86_avx2_pblendw:
22454 case Intrinsic::x86_avx2_pblendd_128:
22455 case Intrinsic::x86_avx2_pblendd_256:
22456 // Don't try to simplify this intrinsic if we don't have AVX2.
22457 if (!Subtarget->hasAVX2())
22460 case Intrinsic::x86_avx_blend_pd_256:
22461 case Intrinsic::x86_avx_blend_ps_256:
22462 case Intrinsic::x86_avx_blendv_pd_256:
22463 case Intrinsic::x86_avx_blendv_ps_256:
22464 // Don't try to simplify this intrinsic if we don't have AVX.
22465 if (!Subtarget->hasAVX())
22468 case Intrinsic::x86_sse41_pblendw:
22469 case Intrinsic::x86_sse41_blendpd:
22470 case Intrinsic::x86_sse41_blendps:
22471 case Intrinsic::x86_sse41_blendvps:
22472 case Intrinsic::x86_sse41_blendvpd:
22473 case Intrinsic::x86_sse41_pblendvb: {
22474 SDValue Op0 = N->getOperand(1);
22475 SDValue Op1 = N->getOperand(2);
22476 SDValue Mask = N->getOperand(3);
22478 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22479 if (!Subtarget->hasSSE41())
22482 // fold (blend A, A, Mask) -> A
22485 // fold (blend A, B, allZeros) -> A
22486 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22488 // fold (blend A, B, allOnes) -> B
22489 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22492 // Simplify the case where the mask is a constant i32 value.
22493 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22494 if (C->isNullValue())
22496 if (C->isAllOnesValue())
22503 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22504 case Intrinsic::x86_sse2_psrai_w:
22505 case Intrinsic::x86_sse2_psrai_d:
22506 case Intrinsic::x86_avx2_psrai_w:
22507 case Intrinsic::x86_avx2_psrai_d:
22508 case Intrinsic::x86_sse2_psra_w:
22509 case Intrinsic::x86_sse2_psra_d:
22510 case Intrinsic::x86_avx2_psra_w:
22511 case Intrinsic::x86_avx2_psra_d: {
22512 SDValue Op0 = N->getOperand(1);
22513 SDValue Op1 = N->getOperand(2);
22514 EVT VT = Op0.getValueType();
22515 assert(VT.isVector() && "Expected a vector type!");
22517 if (isa<BuildVectorSDNode>(Op1))
22518 Op1 = Op1.getOperand(0);
22520 if (!isa<ConstantSDNode>(Op1))
22523 EVT SVT = VT.getVectorElementType();
22524 unsigned SVTBits = SVT.getSizeInBits();
22526 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22527 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22528 uint64_t ShAmt = C.getZExtValue();
22530 // Don't try to convert this shift into a ISD::SRA if the shift
22531 // count is bigger than or equal to the element size.
22532 if (ShAmt >= SVTBits)
22535 // Trivial case: if the shift count is zero, then fold this
22536 // into the first operand.
22540 // Replace this packed shift intrinsic with a target independent
22542 SDValue Splat = DAG.getConstant(C, VT);
22543 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22548 /// PerformMulCombine - Optimize a single multiply with constant into two
22549 /// in order to implement it with two cheaper instructions, e.g.
22550 /// LEA + SHL, LEA + LEA.
22551 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22552 TargetLowering::DAGCombinerInfo &DCI) {
22553 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22556 EVT VT = N->getValueType(0);
22557 if (VT != MVT::i64)
22560 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22563 uint64_t MulAmt = C->getZExtValue();
22564 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22567 uint64_t MulAmt1 = 0;
22568 uint64_t MulAmt2 = 0;
22569 if ((MulAmt % 9) == 0) {
22571 MulAmt2 = MulAmt / 9;
22572 } else if ((MulAmt % 5) == 0) {
22574 MulAmt2 = MulAmt / 5;
22575 } else if ((MulAmt % 3) == 0) {
22577 MulAmt2 = MulAmt / 3;
22580 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22583 if (isPowerOf2_64(MulAmt2) &&
22584 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22585 // If second multiplifer is pow2, issue it first. We want the multiply by
22586 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22588 std::swap(MulAmt1, MulAmt2);
22591 if (isPowerOf2_64(MulAmt1))
22592 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22593 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22595 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22596 DAG.getConstant(MulAmt1, VT));
22598 if (isPowerOf2_64(MulAmt2))
22599 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22600 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22602 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22603 DAG.getConstant(MulAmt2, VT));
22605 // Do not add new nodes to DAG combiner worklist.
22606 DCI.CombineTo(N, NewMul, false);
22611 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22612 SDValue N0 = N->getOperand(0);
22613 SDValue N1 = N->getOperand(1);
22614 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22615 EVT VT = N0.getValueType();
22617 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22618 // since the result of setcc_c is all zero's or all ones.
22619 if (VT.isInteger() && !VT.isVector() &&
22620 N1C && N0.getOpcode() == ISD::AND &&
22621 N0.getOperand(1).getOpcode() == ISD::Constant) {
22622 SDValue N00 = N0.getOperand(0);
22623 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22624 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22625 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22626 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22627 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22628 APInt ShAmt = N1C->getAPIntValue();
22629 Mask = Mask.shl(ShAmt);
22631 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22632 N00, DAG.getConstant(Mask, VT));
22636 // Hardware support for vector shifts is sparse which makes us scalarize the
22637 // vector operations in many cases. Also, on sandybridge ADD is faster than
22639 // (shl V, 1) -> add V,V
22640 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22641 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22642 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22643 // We shift all of the values by one. In many cases we do not have
22644 // hardware support for this operation. This is better expressed as an ADD
22646 if (N1SplatC->getZExtValue() == 1)
22647 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22653 /// \brief Returns a vector of 0s if the node in input is a vector logical
22654 /// shift by a constant amount which is known to be bigger than or equal
22655 /// to the vector element size in bits.
22656 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22657 const X86Subtarget *Subtarget) {
22658 EVT VT = N->getValueType(0);
22660 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22661 (!Subtarget->hasInt256() ||
22662 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22665 SDValue Amt = N->getOperand(1);
22667 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22668 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22669 APInt ShiftAmt = AmtSplat->getAPIntValue();
22670 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22672 // SSE2/AVX2 logical shifts always return a vector of 0s
22673 // if the shift amount is bigger than or equal to
22674 // the element size. The constant shift amount will be
22675 // encoded as a 8-bit immediate.
22676 if (ShiftAmt.trunc(8).uge(MaxAmount))
22677 return getZeroVector(VT, Subtarget, DAG, DL);
22683 /// PerformShiftCombine - Combine shifts.
22684 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22685 TargetLowering::DAGCombinerInfo &DCI,
22686 const X86Subtarget *Subtarget) {
22687 if (N->getOpcode() == ISD::SHL) {
22688 SDValue V = PerformSHLCombine(N, DAG);
22689 if (V.getNode()) return V;
22692 if (N->getOpcode() != ISD::SRA) {
22693 // Try to fold this logical shift into a zero vector.
22694 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22695 if (V.getNode()) return V;
22701 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22702 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22703 // and friends. Likewise for OR -> CMPNEQSS.
22704 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22705 TargetLowering::DAGCombinerInfo &DCI,
22706 const X86Subtarget *Subtarget) {
22709 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22710 // we're requiring SSE2 for both.
22711 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22712 SDValue N0 = N->getOperand(0);
22713 SDValue N1 = N->getOperand(1);
22714 SDValue CMP0 = N0->getOperand(1);
22715 SDValue CMP1 = N1->getOperand(1);
22718 // The SETCCs should both refer to the same CMP.
22719 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22722 SDValue CMP00 = CMP0->getOperand(0);
22723 SDValue CMP01 = CMP0->getOperand(1);
22724 EVT VT = CMP00.getValueType();
22726 if (VT == MVT::f32 || VT == MVT::f64) {
22727 bool ExpectingFlags = false;
22728 // Check for any users that want flags:
22729 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22730 !ExpectingFlags && UI != UE; ++UI)
22731 switch (UI->getOpcode()) {
22736 ExpectingFlags = true;
22738 case ISD::CopyToReg:
22739 case ISD::SIGN_EXTEND:
22740 case ISD::ZERO_EXTEND:
22741 case ISD::ANY_EXTEND:
22745 if (!ExpectingFlags) {
22746 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22747 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22749 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22750 X86::CondCode tmp = cc0;
22755 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22756 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22757 // FIXME: need symbolic constants for these magic numbers.
22758 // See X86ATTInstPrinter.cpp:printSSECC().
22759 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22760 if (Subtarget->hasAVX512()) {
22761 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22762 CMP01, DAG.getConstant(x86cc, MVT::i8));
22763 if (N->getValueType(0) != MVT::i1)
22764 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22768 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22769 CMP00.getValueType(), CMP00, CMP01,
22770 DAG.getConstant(x86cc, MVT::i8));
22772 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22773 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22775 if (is64BitFP && !Subtarget->is64Bit()) {
22776 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22777 // 64-bit integer, since that's not a legal type. Since
22778 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22779 // bits, but can do this little dance to extract the lowest 32 bits
22780 // and work with those going forward.
22781 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22783 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22785 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22786 Vector32, DAG.getIntPtrConstant(0));
22790 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22791 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22792 DAG.getConstant(1, IntVT));
22793 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22794 return OneBitOfTruth;
22802 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22803 /// so it can be folded inside ANDNP.
22804 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22805 EVT VT = N->getValueType(0);
22807 // Match direct AllOnes for 128 and 256-bit vectors
22808 if (ISD::isBuildVectorAllOnes(N))
22811 // Look through a bit convert.
22812 if (N->getOpcode() == ISD::BITCAST)
22813 N = N->getOperand(0).getNode();
22815 // Sometimes the operand may come from a insert_subvector building a 256-bit
22817 if (VT.is256BitVector() &&
22818 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22819 SDValue V1 = N->getOperand(0);
22820 SDValue V2 = N->getOperand(1);
22822 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22823 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22824 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22825 ISD::isBuildVectorAllOnes(V2.getNode()))
22832 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22833 // register. In most cases we actually compare or select YMM-sized registers
22834 // and mixing the two types creates horrible code. This method optimizes
22835 // some of the transition sequences.
22836 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22837 TargetLowering::DAGCombinerInfo &DCI,
22838 const X86Subtarget *Subtarget) {
22839 EVT VT = N->getValueType(0);
22840 if (!VT.is256BitVector())
22843 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22844 N->getOpcode() == ISD::ZERO_EXTEND ||
22845 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22847 SDValue Narrow = N->getOperand(0);
22848 EVT NarrowVT = Narrow->getValueType(0);
22849 if (!NarrowVT.is128BitVector())
22852 if (Narrow->getOpcode() != ISD::XOR &&
22853 Narrow->getOpcode() != ISD::AND &&
22854 Narrow->getOpcode() != ISD::OR)
22857 SDValue N0 = Narrow->getOperand(0);
22858 SDValue N1 = Narrow->getOperand(1);
22861 // The Left side has to be a trunc.
22862 if (N0.getOpcode() != ISD::TRUNCATE)
22865 // The type of the truncated inputs.
22866 EVT WideVT = N0->getOperand(0)->getValueType(0);
22870 // The right side has to be a 'trunc' or a constant vector.
22871 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22872 ConstantSDNode *RHSConstSplat = nullptr;
22873 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22874 RHSConstSplat = RHSBV->getConstantSplatNode();
22875 if (!RHSTrunc && !RHSConstSplat)
22878 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22880 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22883 // Set N0 and N1 to hold the inputs to the new wide operation.
22884 N0 = N0->getOperand(0);
22885 if (RHSConstSplat) {
22886 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22887 SDValue(RHSConstSplat, 0));
22888 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22889 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22890 } else if (RHSTrunc) {
22891 N1 = N1->getOperand(0);
22894 // Generate the wide operation.
22895 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22896 unsigned Opcode = N->getOpcode();
22898 case ISD::ANY_EXTEND:
22900 case ISD::ZERO_EXTEND: {
22901 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22902 APInt Mask = APInt::getAllOnesValue(InBits);
22903 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22904 return DAG.getNode(ISD::AND, DL, VT,
22905 Op, DAG.getConstant(Mask, VT));
22907 case ISD::SIGN_EXTEND:
22908 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22909 Op, DAG.getValueType(NarrowVT));
22911 llvm_unreachable("Unexpected opcode");
22915 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22916 TargetLowering::DAGCombinerInfo &DCI,
22917 const X86Subtarget *Subtarget) {
22918 EVT VT = N->getValueType(0);
22919 if (DCI.isBeforeLegalizeOps())
22922 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22926 // Create BEXTR instructions
22927 // BEXTR is ((X >> imm) & (2**size-1))
22928 if (VT == MVT::i32 || VT == MVT::i64) {
22929 SDValue N0 = N->getOperand(0);
22930 SDValue N1 = N->getOperand(1);
22933 // Check for BEXTR.
22934 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22935 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22936 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22937 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22938 if (MaskNode && ShiftNode) {
22939 uint64_t Mask = MaskNode->getZExtValue();
22940 uint64_t Shift = ShiftNode->getZExtValue();
22941 if (isMask_64(Mask)) {
22942 uint64_t MaskSize = CountPopulation_64(Mask);
22943 if (Shift + MaskSize <= VT.getSizeInBits())
22944 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22945 DAG.getConstant(Shift | (MaskSize << 8), VT));
22953 // Want to form ANDNP nodes:
22954 // 1) In the hopes of then easily combining them with OR and AND nodes
22955 // to form PBLEND/PSIGN.
22956 // 2) To match ANDN packed intrinsics
22957 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22960 SDValue N0 = N->getOperand(0);
22961 SDValue N1 = N->getOperand(1);
22964 // Check LHS for vnot
22965 if (N0.getOpcode() == ISD::XOR &&
22966 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22967 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22968 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22970 // Check RHS for vnot
22971 if (N1.getOpcode() == ISD::XOR &&
22972 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22973 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22974 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22979 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22980 TargetLowering::DAGCombinerInfo &DCI,
22981 const X86Subtarget *Subtarget) {
22982 if (DCI.isBeforeLegalizeOps())
22985 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22989 SDValue N0 = N->getOperand(0);
22990 SDValue N1 = N->getOperand(1);
22991 EVT VT = N->getValueType(0);
22993 // look for psign/blend
22994 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22995 if (!Subtarget->hasSSSE3() ||
22996 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22999 // Canonicalize pandn to RHS
23000 if (N0.getOpcode() == X86ISD::ANDNP)
23002 // or (and (m, y), (pandn m, x))
23003 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23004 SDValue Mask = N1.getOperand(0);
23005 SDValue X = N1.getOperand(1);
23007 if (N0.getOperand(0) == Mask)
23008 Y = N0.getOperand(1);
23009 if (N0.getOperand(1) == Mask)
23010 Y = N0.getOperand(0);
23012 // Check to see if the mask appeared in both the AND and ANDNP and
23016 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23017 // Look through mask bitcast.
23018 if (Mask.getOpcode() == ISD::BITCAST)
23019 Mask = Mask.getOperand(0);
23020 if (X.getOpcode() == ISD::BITCAST)
23021 X = X.getOperand(0);
23022 if (Y.getOpcode() == ISD::BITCAST)
23023 Y = Y.getOperand(0);
23025 EVT MaskVT = Mask.getValueType();
23027 // Validate that the Mask operand is a vector sra node.
23028 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23029 // there is no psrai.b
23030 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23031 unsigned SraAmt = ~0;
23032 if (Mask.getOpcode() == ISD::SRA) {
23033 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23034 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23035 SraAmt = AmtConst->getZExtValue();
23036 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23037 SDValue SraC = Mask.getOperand(1);
23038 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23040 if ((SraAmt + 1) != EltBits)
23045 // Now we know we at least have a plendvb with the mask val. See if
23046 // we can form a psignb/w/d.
23047 // psign = x.type == y.type == mask.type && y = sub(0, x);
23048 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23049 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23050 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23051 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23052 "Unsupported VT for PSIGN");
23053 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23054 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23056 // PBLENDVB only available on SSE 4.1
23057 if (!Subtarget->hasSSE41())
23060 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23062 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23063 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23064 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23065 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23066 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23070 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23073 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23074 MachineFunction &MF = DAG.getMachineFunction();
23075 bool OptForSize = MF.getFunction()->getAttributes().
23076 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23078 // SHLD/SHRD instructions have lower register pressure, but on some
23079 // platforms they have higher latency than the equivalent
23080 // series of shifts/or that would otherwise be generated.
23081 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23082 // have higher latencies and we are not optimizing for size.
23083 if (!OptForSize && Subtarget->isSHLDSlow())
23086 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23088 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23090 if (!N0.hasOneUse() || !N1.hasOneUse())
23093 SDValue ShAmt0 = N0.getOperand(1);
23094 if (ShAmt0.getValueType() != MVT::i8)
23096 SDValue ShAmt1 = N1.getOperand(1);
23097 if (ShAmt1.getValueType() != MVT::i8)
23099 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23100 ShAmt0 = ShAmt0.getOperand(0);
23101 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23102 ShAmt1 = ShAmt1.getOperand(0);
23105 unsigned Opc = X86ISD::SHLD;
23106 SDValue Op0 = N0.getOperand(0);
23107 SDValue Op1 = N1.getOperand(0);
23108 if (ShAmt0.getOpcode() == ISD::SUB) {
23109 Opc = X86ISD::SHRD;
23110 std::swap(Op0, Op1);
23111 std::swap(ShAmt0, ShAmt1);
23114 unsigned Bits = VT.getSizeInBits();
23115 if (ShAmt1.getOpcode() == ISD::SUB) {
23116 SDValue Sum = ShAmt1.getOperand(0);
23117 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23118 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23119 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23120 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23121 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23122 return DAG.getNode(Opc, DL, VT,
23124 DAG.getNode(ISD::TRUNCATE, DL,
23127 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23128 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23130 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23131 return DAG.getNode(Opc, DL, VT,
23132 N0.getOperand(0), N1.getOperand(0),
23133 DAG.getNode(ISD::TRUNCATE, DL,
23140 // Generate NEG and CMOV for integer abs.
23141 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23142 EVT VT = N->getValueType(0);
23144 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23145 // 8-bit integer abs to NEG and CMOV.
23146 if (VT.isInteger() && VT.getSizeInBits() == 8)
23149 SDValue N0 = N->getOperand(0);
23150 SDValue N1 = N->getOperand(1);
23153 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23154 // and change it to SUB and CMOV.
23155 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23156 N0.getOpcode() == ISD::ADD &&
23157 N0.getOperand(1) == N1 &&
23158 N1.getOpcode() == ISD::SRA &&
23159 N1.getOperand(0) == N0.getOperand(0))
23160 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23161 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23162 // Generate SUB & CMOV.
23163 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23164 DAG.getConstant(0, VT), N0.getOperand(0));
23166 SDValue Ops[] = { N0.getOperand(0), Neg,
23167 DAG.getConstant(X86::COND_GE, MVT::i8),
23168 SDValue(Neg.getNode(), 1) };
23169 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23174 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23175 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23176 TargetLowering::DAGCombinerInfo &DCI,
23177 const X86Subtarget *Subtarget) {
23178 if (DCI.isBeforeLegalizeOps())
23181 if (Subtarget->hasCMov()) {
23182 SDValue RV = performIntegerAbsCombine(N, DAG);
23190 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23191 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23192 TargetLowering::DAGCombinerInfo &DCI,
23193 const X86Subtarget *Subtarget) {
23194 LoadSDNode *Ld = cast<LoadSDNode>(N);
23195 EVT RegVT = Ld->getValueType(0);
23196 EVT MemVT = Ld->getMemoryVT();
23198 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23200 // On Sandybridge unaligned 256bit loads are inefficient.
23201 ISD::LoadExtType Ext = Ld->getExtensionType();
23202 unsigned Alignment = Ld->getAlignment();
23203 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23204 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23205 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23206 unsigned NumElems = RegVT.getVectorNumElements();
23210 SDValue Ptr = Ld->getBasePtr();
23211 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23213 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23215 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23216 Ld->getPointerInfo(), Ld->isVolatile(),
23217 Ld->isNonTemporal(), Ld->isInvariant(),
23219 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23220 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23221 Ld->getPointerInfo(), Ld->isVolatile(),
23222 Ld->isNonTemporal(), Ld->isInvariant(),
23223 std::min(16U, Alignment));
23224 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23226 Load2.getValue(1));
23228 SDValue NewVec = DAG.getUNDEF(RegVT);
23229 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23230 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23231 return DCI.CombineTo(N, NewVec, TF, true);
23237 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23238 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23239 const X86Subtarget *Subtarget) {
23240 StoreSDNode *St = cast<StoreSDNode>(N);
23241 EVT VT = St->getValue().getValueType();
23242 EVT StVT = St->getMemoryVT();
23244 SDValue StoredVal = St->getOperand(1);
23245 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23247 // If we are saving a concatenation of two XMM registers, perform two stores.
23248 // On Sandy Bridge, 256-bit memory operations are executed by two
23249 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23250 // memory operation.
23251 unsigned Alignment = St->getAlignment();
23252 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23253 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23254 StVT == VT && !IsAligned) {
23255 unsigned NumElems = VT.getVectorNumElements();
23259 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23260 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23262 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23263 SDValue Ptr0 = St->getBasePtr();
23264 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23266 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23267 St->getPointerInfo(), St->isVolatile(),
23268 St->isNonTemporal(), Alignment);
23269 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23270 St->getPointerInfo(), St->isVolatile(),
23271 St->isNonTemporal(),
23272 std::min(16U, Alignment));
23273 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23276 // Optimize trunc store (of multiple scalars) to shuffle and store.
23277 // First, pack all of the elements in one place. Next, store to memory
23278 // in fewer chunks.
23279 if (St->isTruncatingStore() && VT.isVector()) {
23280 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23281 unsigned NumElems = VT.getVectorNumElements();
23282 assert(StVT != VT && "Cannot truncate to the same type");
23283 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23284 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23286 // From, To sizes and ElemCount must be pow of two
23287 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23288 // We are going to use the original vector elt for storing.
23289 // Accumulated smaller vector elements must be a multiple of the store size.
23290 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23292 unsigned SizeRatio = FromSz / ToSz;
23294 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23296 // Create a type on which we perform the shuffle
23297 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23298 StVT.getScalarType(), NumElems*SizeRatio);
23300 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23302 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23303 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23304 for (unsigned i = 0; i != NumElems; ++i)
23305 ShuffleVec[i] = i * SizeRatio;
23307 // Can't shuffle using an illegal type.
23308 if (!TLI.isTypeLegal(WideVecVT))
23311 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23312 DAG.getUNDEF(WideVecVT),
23314 // At this point all of the data is stored at the bottom of the
23315 // register. We now need to save it to mem.
23317 // Find the largest store unit
23318 MVT StoreType = MVT::i8;
23319 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23320 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23321 MVT Tp = (MVT::SimpleValueType)tp;
23322 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23326 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23327 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23328 (64 <= NumElems * ToSz))
23329 StoreType = MVT::f64;
23331 // Bitcast the original vector into a vector of store-size units
23332 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23333 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23334 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23335 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23336 SmallVector<SDValue, 8> Chains;
23337 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23338 TLI.getPointerTy());
23339 SDValue Ptr = St->getBasePtr();
23341 // Perform one or more big stores into memory.
23342 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23343 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23344 StoreType, ShuffWide,
23345 DAG.getIntPtrConstant(i));
23346 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23347 St->getPointerInfo(), St->isVolatile(),
23348 St->isNonTemporal(), St->getAlignment());
23349 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23350 Chains.push_back(Ch);
23353 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23356 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23357 // the FP state in cases where an emms may be missing.
23358 // A preferable solution to the general problem is to figure out the right
23359 // places to insert EMMS. This qualifies as a quick hack.
23361 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23362 if (VT.getSizeInBits() != 64)
23365 const Function *F = DAG.getMachineFunction().getFunction();
23366 bool NoImplicitFloatOps = F->getAttributes().
23367 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23368 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23369 && Subtarget->hasSSE2();
23370 if ((VT.isVector() ||
23371 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23372 isa<LoadSDNode>(St->getValue()) &&
23373 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23374 St->getChain().hasOneUse() && !St->isVolatile()) {
23375 SDNode* LdVal = St->getValue().getNode();
23376 LoadSDNode *Ld = nullptr;
23377 int TokenFactorIndex = -1;
23378 SmallVector<SDValue, 8> Ops;
23379 SDNode* ChainVal = St->getChain().getNode();
23380 // Must be a store of a load. We currently handle two cases: the load
23381 // is a direct child, and it's under an intervening TokenFactor. It is
23382 // possible to dig deeper under nested TokenFactors.
23383 if (ChainVal == LdVal)
23384 Ld = cast<LoadSDNode>(St->getChain());
23385 else if (St->getValue().hasOneUse() &&
23386 ChainVal->getOpcode() == ISD::TokenFactor) {
23387 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23388 if (ChainVal->getOperand(i).getNode() == LdVal) {
23389 TokenFactorIndex = i;
23390 Ld = cast<LoadSDNode>(St->getValue());
23392 Ops.push_back(ChainVal->getOperand(i));
23396 if (!Ld || !ISD::isNormalLoad(Ld))
23399 // If this is not the MMX case, i.e. we are just turning i64 load/store
23400 // into f64 load/store, avoid the transformation if there are multiple
23401 // uses of the loaded value.
23402 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23407 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23408 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23410 if (Subtarget->is64Bit() || F64IsLegal) {
23411 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23412 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23413 Ld->getPointerInfo(), Ld->isVolatile(),
23414 Ld->isNonTemporal(), Ld->isInvariant(),
23415 Ld->getAlignment());
23416 SDValue NewChain = NewLd.getValue(1);
23417 if (TokenFactorIndex != -1) {
23418 Ops.push_back(NewChain);
23419 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23421 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23422 St->getPointerInfo(),
23423 St->isVolatile(), St->isNonTemporal(),
23424 St->getAlignment());
23427 // Otherwise, lower to two pairs of 32-bit loads / stores.
23428 SDValue LoAddr = Ld->getBasePtr();
23429 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23430 DAG.getConstant(4, MVT::i32));
23432 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23433 Ld->getPointerInfo(),
23434 Ld->isVolatile(), Ld->isNonTemporal(),
23435 Ld->isInvariant(), Ld->getAlignment());
23436 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23437 Ld->getPointerInfo().getWithOffset(4),
23438 Ld->isVolatile(), Ld->isNonTemporal(),
23440 MinAlign(Ld->getAlignment(), 4));
23442 SDValue NewChain = LoLd.getValue(1);
23443 if (TokenFactorIndex != -1) {
23444 Ops.push_back(LoLd);
23445 Ops.push_back(HiLd);
23446 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23449 LoAddr = St->getBasePtr();
23450 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23451 DAG.getConstant(4, MVT::i32));
23453 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23454 St->getPointerInfo(),
23455 St->isVolatile(), St->isNonTemporal(),
23456 St->getAlignment());
23457 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23458 St->getPointerInfo().getWithOffset(4),
23460 St->isNonTemporal(),
23461 MinAlign(St->getAlignment(), 4));
23462 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23467 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23468 /// and return the operands for the horizontal operation in LHS and RHS. A
23469 /// horizontal operation performs the binary operation on successive elements
23470 /// of its first operand, then on successive elements of its second operand,
23471 /// returning the resulting values in a vector. For example, if
23472 /// A = < float a0, float a1, float a2, float a3 >
23474 /// B = < float b0, float b1, float b2, float b3 >
23475 /// then the result of doing a horizontal operation on A and B is
23476 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23477 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23478 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23479 /// set to A, RHS to B, and the routine returns 'true'.
23480 /// Note that the binary operation should have the property that if one of the
23481 /// operands is UNDEF then the result is UNDEF.
23482 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23483 // Look for the following pattern: if
23484 // A = < float a0, float a1, float a2, float a3 >
23485 // B = < float b0, float b1, float b2, float b3 >
23487 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23488 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23489 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23490 // which is A horizontal-op B.
23492 // At least one of the operands should be a vector shuffle.
23493 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23494 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23497 MVT VT = LHS.getSimpleValueType();
23499 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23500 "Unsupported vector type for horizontal add/sub");
23502 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23503 // operate independently on 128-bit lanes.
23504 unsigned NumElts = VT.getVectorNumElements();
23505 unsigned NumLanes = VT.getSizeInBits()/128;
23506 unsigned NumLaneElts = NumElts / NumLanes;
23507 assert((NumLaneElts % 2 == 0) &&
23508 "Vector type should have an even number of elements in each lane");
23509 unsigned HalfLaneElts = NumLaneElts/2;
23511 // View LHS in the form
23512 // LHS = VECTOR_SHUFFLE A, B, LMask
23513 // If LHS is not a shuffle then pretend it is the shuffle
23514 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23515 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23518 SmallVector<int, 16> LMask(NumElts);
23519 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23520 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23521 A = LHS.getOperand(0);
23522 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23523 B = LHS.getOperand(1);
23524 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23525 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23527 if (LHS.getOpcode() != ISD::UNDEF)
23529 for (unsigned i = 0; i != NumElts; ++i)
23533 // Likewise, view RHS in the form
23534 // RHS = VECTOR_SHUFFLE C, D, RMask
23536 SmallVector<int, 16> RMask(NumElts);
23537 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23538 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23539 C = RHS.getOperand(0);
23540 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23541 D = RHS.getOperand(1);
23542 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23543 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23545 if (RHS.getOpcode() != ISD::UNDEF)
23547 for (unsigned i = 0; i != NumElts; ++i)
23551 // Check that the shuffles are both shuffling the same vectors.
23552 if (!(A == C && B == D) && !(A == D && B == C))
23555 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23556 if (!A.getNode() && !B.getNode())
23559 // If A and B occur in reverse order in RHS, then "swap" them (which means
23560 // rewriting the mask).
23562 CommuteVectorShuffleMask(RMask, NumElts);
23564 // At this point LHS and RHS are equivalent to
23565 // LHS = VECTOR_SHUFFLE A, B, LMask
23566 // RHS = VECTOR_SHUFFLE A, B, RMask
23567 // Check that the masks correspond to performing a horizontal operation.
23568 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23569 for (unsigned i = 0; i != NumLaneElts; ++i) {
23570 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23572 // Ignore any UNDEF components.
23573 if (LIdx < 0 || RIdx < 0 ||
23574 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23575 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23578 // Check that successive elements are being operated on. If not, this is
23579 // not a horizontal operation.
23580 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23581 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23582 if (!(LIdx == Index && RIdx == Index + 1) &&
23583 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23588 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23589 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23593 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23594 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23595 const X86Subtarget *Subtarget) {
23596 EVT VT = N->getValueType(0);
23597 SDValue LHS = N->getOperand(0);
23598 SDValue RHS = N->getOperand(1);
23600 // Try to synthesize horizontal adds from adds of shuffles.
23601 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23602 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23603 isHorizontalBinOp(LHS, RHS, true))
23604 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23608 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23609 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23610 const X86Subtarget *Subtarget) {
23611 EVT VT = N->getValueType(0);
23612 SDValue LHS = N->getOperand(0);
23613 SDValue RHS = N->getOperand(1);
23615 // Try to synthesize horizontal subs from subs of shuffles.
23616 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23617 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23618 isHorizontalBinOp(LHS, RHS, false))
23619 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23623 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23624 /// X86ISD::FXOR nodes.
23625 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23626 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23627 // F[X]OR(0.0, x) -> x
23628 // F[X]OR(x, 0.0) -> x
23629 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23630 if (C->getValueAPF().isPosZero())
23631 return N->getOperand(1);
23632 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23633 if (C->getValueAPF().isPosZero())
23634 return N->getOperand(0);
23638 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23639 /// X86ISD::FMAX nodes.
23640 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23641 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23643 // Only perform optimizations if UnsafeMath is used.
23644 if (!DAG.getTarget().Options.UnsafeFPMath)
23647 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23648 // into FMINC and FMAXC, which are Commutative operations.
23649 unsigned NewOp = 0;
23650 switch (N->getOpcode()) {
23651 default: llvm_unreachable("unknown opcode");
23652 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23653 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23656 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23657 N->getOperand(0), N->getOperand(1));
23660 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23661 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23662 // FAND(0.0, x) -> 0.0
23663 // FAND(x, 0.0) -> 0.0
23664 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23665 if (C->getValueAPF().isPosZero())
23666 return N->getOperand(0);
23667 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23668 if (C->getValueAPF().isPosZero())
23669 return N->getOperand(1);
23673 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23674 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23675 // FANDN(x, 0.0) -> 0.0
23676 // FANDN(0.0, x) -> x
23677 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23678 if (C->getValueAPF().isPosZero())
23679 return N->getOperand(1);
23680 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23681 if (C->getValueAPF().isPosZero())
23682 return N->getOperand(1);
23686 static SDValue PerformBTCombine(SDNode *N,
23688 TargetLowering::DAGCombinerInfo &DCI) {
23689 // BT ignores high bits in the bit index operand.
23690 SDValue Op1 = N->getOperand(1);
23691 if (Op1.hasOneUse()) {
23692 unsigned BitWidth = Op1.getValueSizeInBits();
23693 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23694 APInt KnownZero, KnownOne;
23695 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23696 !DCI.isBeforeLegalizeOps());
23697 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23698 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23699 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23700 DCI.CommitTargetLoweringOpt(TLO);
23705 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23706 SDValue Op = N->getOperand(0);
23707 if (Op.getOpcode() == ISD::BITCAST)
23708 Op = Op.getOperand(0);
23709 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23710 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23711 VT.getVectorElementType().getSizeInBits() ==
23712 OpVT.getVectorElementType().getSizeInBits()) {
23713 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23718 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23719 const X86Subtarget *Subtarget) {
23720 EVT VT = N->getValueType(0);
23721 if (!VT.isVector())
23724 SDValue N0 = N->getOperand(0);
23725 SDValue N1 = N->getOperand(1);
23726 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23729 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23730 // both SSE and AVX2 since there is no sign-extended shift right
23731 // operation on a vector with 64-bit elements.
23732 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23733 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23734 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23735 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23736 SDValue N00 = N0.getOperand(0);
23738 // EXTLOAD has a better solution on AVX2,
23739 // it may be replaced with X86ISD::VSEXT node.
23740 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23741 if (!ISD::isNormalLoad(N00.getNode()))
23744 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23745 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23747 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23753 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23754 TargetLowering::DAGCombinerInfo &DCI,
23755 const X86Subtarget *Subtarget) {
23756 if (!DCI.isBeforeLegalizeOps())
23759 if (!Subtarget->hasFp256())
23762 EVT VT = N->getValueType(0);
23763 if (VT.isVector() && VT.getSizeInBits() == 256) {
23764 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23772 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23773 const X86Subtarget* Subtarget) {
23775 EVT VT = N->getValueType(0);
23777 // Let legalize expand this if it isn't a legal type yet.
23778 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23781 EVT ScalarVT = VT.getScalarType();
23782 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23783 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23786 SDValue A = N->getOperand(0);
23787 SDValue B = N->getOperand(1);
23788 SDValue C = N->getOperand(2);
23790 bool NegA = (A.getOpcode() == ISD::FNEG);
23791 bool NegB = (B.getOpcode() == ISD::FNEG);
23792 bool NegC = (C.getOpcode() == ISD::FNEG);
23794 // Negative multiplication when NegA xor NegB
23795 bool NegMul = (NegA != NegB);
23797 A = A.getOperand(0);
23799 B = B.getOperand(0);
23801 C = C.getOperand(0);
23805 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23807 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23809 return DAG.getNode(Opcode, dl, VT, A, B, C);
23812 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23813 TargetLowering::DAGCombinerInfo &DCI,
23814 const X86Subtarget *Subtarget) {
23815 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23816 // (and (i32 x86isd::setcc_carry), 1)
23817 // This eliminates the zext. This transformation is necessary because
23818 // ISD::SETCC is always legalized to i8.
23820 SDValue N0 = N->getOperand(0);
23821 EVT VT = N->getValueType(0);
23823 if (N0.getOpcode() == ISD::AND &&
23825 N0.getOperand(0).hasOneUse()) {
23826 SDValue N00 = N0.getOperand(0);
23827 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23828 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23829 if (!C || C->getZExtValue() != 1)
23831 return DAG.getNode(ISD::AND, dl, VT,
23832 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23833 N00.getOperand(0), N00.getOperand(1)),
23834 DAG.getConstant(1, VT));
23838 if (N0.getOpcode() == ISD::TRUNCATE &&
23840 N0.getOperand(0).hasOneUse()) {
23841 SDValue N00 = N0.getOperand(0);
23842 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23843 return DAG.getNode(ISD::AND, dl, VT,
23844 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23845 N00.getOperand(0), N00.getOperand(1)),
23846 DAG.getConstant(1, VT));
23849 if (VT.is256BitVector()) {
23850 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23858 // Optimize x == -y --> x+y == 0
23859 // x != -y --> x+y != 0
23860 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23861 const X86Subtarget* Subtarget) {
23862 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23863 SDValue LHS = N->getOperand(0);
23864 SDValue RHS = N->getOperand(1);
23865 EVT VT = N->getValueType(0);
23868 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23869 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23870 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23871 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23872 LHS.getValueType(), RHS, LHS.getOperand(1));
23873 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23874 addV, DAG.getConstant(0, addV.getValueType()), CC);
23876 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23877 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23878 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23879 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23880 RHS.getValueType(), LHS, RHS.getOperand(1));
23881 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23882 addV, DAG.getConstant(0, addV.getValueType()), CC);
23885 if (VT.getScalarType() == MVT::i1) {
23886 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23887 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23888 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23889 if (!IsSEXT0 && !IsVZero0)
23891 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23892 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23893 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23895 if (!IsSEXT1 && !IsVZero1)
23898 if (IsSEXT0 && IsVZero1) {
23899 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23900 if (CC == ISD::SETEQ)
23901 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23902 return LHS.getOperand(0);
23904 if (IsSEXT1 && IsVZero0) {
23905 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23906 if (CC == ISD::SETEQ)
23907 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23908 return RHS.getOperand(0);
23915 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23916 const X86Subtarget *Subtarget) {
23918 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23919 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23920 "X86insertps is only defined for v4x32");
23922 SDValue Ld = N->getOperand(1);
23923 if (MayFoldLoad(Ld)) {
23924 // Extract the countS bits from the immediate so we can get the proper
23925 // address when narrowing the vector load to a specific element.
23926 // When the second source op is a memory address, interps doesn't use
23927 // countS and just gets an f32 from that address.
23928 unsigned DestIndex =
23929 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23930 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23934 // Create this as a scalar to vector to match the instruction pattern.
23935 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23936 // countS bits are ignored when loading from memory on insertps, which
23937 // means we don't need to explicitly set them to 0.
23938 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23939 LoadScalarToVector, N->getOperand(2));
23942 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23943 // as "sbb reg,reg", since it can be extended without zext and produces
23944 // an all-ones bit which is more useful than 0/1 in some cases.
23945 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23948 return DAG.getNode(ISD::AND, DL, VT,
23949 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23950 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23951 DAG.getConstant(1, VT));
23952 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23953 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23954 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23955 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23958 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23959 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23960 TargetLowering::DAGCombinerInfo &DCI,
23961 const X86Subtarget *Subtarget) {
23963 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23964 SDValue EFLAGS = N->getOperand(1);
23966 if (CC == X86::COND_A) {
23967 // Try to convert COND_A into COND_B in an attempt to facilitate
23968 // materializing "setb reg".
23970 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23971 // cannot take an immediate as its first operand.
23973 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23974 EFLAGS.getValueType().isInteger() &&
23975 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23976 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23977 EFLAGS.getNode()->getVTList(),
23978 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23979 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23980 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23984 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23985 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23987 if (CC == X86::COND_B)
23988 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23992 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23993 if (Flags.getNode()) {
23994 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23995 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24001 // Optimize branch condition evaluation.
24003 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24004 TargetLowering::DAGCombinerInfo &DCI,
24005 const X86Subtarget *Subtarget) {
24007 SDValue Chain = N->getOperand(0);
24008 SDValue Dest = N->getOperand(1);
24009 SDValue EFLAGS = N->getOperand(3);
24010 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24014 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24015 if (Flags.getNode()) {
24016 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24017 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24024 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24025 SelectionDAG &DAG) {
24026 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24027 // optimize away operation when it's from a constant.
24029 // The general transformation is:
24030 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24031 // AND(VECTOR_CMP(x,y), constant2)
24032 // constant2 = UNARYOP(constant)
24034 // Early exit if this isn't a vector operation, the operand of the
24035 // unary operation isn't a bitwise AND, or if the sizes of the operations
24036 // aren't the same.
24037 EVT VT = N->getValueType(0);
24038 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24039 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24040 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24043 // Now check that the other operand of the AND is a constant. We could
24044 // make the transformation for non-constant splats as well, but it's unclear
24045 // that would be a benefit as it would not eliminate any operations, just
24046 // perform one more step in scalar code before moving to the vector unit.
24047 if (BuildVectorSDNode *BV =
24048 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24049 // Bail out if the vector isn't a constant.
24050 if (!BV->isConstant())
24053 // Everything checks out. Build up the new and improved node.
24055 EVT IntVT = BV->getValueType(0);
24056 // Create a new constant of the appropriate type for the transformed
24058 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24059 // The AND node needs bitcasts to/from an integer vector type around it.
24060 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24061 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24062 N->getOperand(0)->getOperand(0), MaskConst);
24063 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24070 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24071 const X86TargetLowering *XTLI) {
24072 // First try to optimize away the conversion entirely when it's
24073 // conditionally from a constant. Vectors only.
24074 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24075 if (Res != SDValue())
24078 // Now move on to more general possibilities.
24079 SDValue Op0 = N->getOperand(0);
24080 EVT InVT = Op0->getValueType(0);
24082 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24083 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24085 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24086 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24087 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24090 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24091 // a 32-bit target where SSE doesn't support i64->FP operations.
24092 if (Op0.getOpcode() == ISD::LOAD) {
24093 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24094 EVT VT = Ld->getValueType(0);
24095 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24096 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24097 !XTLI->getSubtarget()->is64Bit() &&
24099 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24100 Ld->getChain(), Op0, DAG);
24101 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24108 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24109 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24110 X86TargetLowering::DAGCombinerInfo &DCI) {
24111 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24112 // the result is either zero or one (depending on the input carry bit).
24113 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24114 if (X86::isZeroNode(N->getOperand(0)) &&
24115 X86::isZeroNode(N->getOperand(1)) &&
24116 // We don't have a good way to replace an EFLAGS use, so only do this when
24118 SDValue(N, 1).use_empty()) {
24120 EVT VT = N->getValueType(0);
24121 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24122 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24123 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24124 DAG.getConstant(X86::COND_B,MVT::i8),
24126 DAG.getConstant(1, VT));
24127 return DCI.CombineTo(N, Res1, CarryOut);
24133 // fold (add Y, (sete X, 0)) -> adc 0, Y
24134 // (add Y, (setne X, 0)) -> sbb -1, Y
24135 // (sub (sete X, 0), Y) -> sbb 0, Y
24136 // (sub (setne X, 0), Y) -> adc -1, Y
24137 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24140 // Look through ZExts.
24141 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24142 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24145 SDValue SetCC = Ext.getOperand(0);
24146 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24149 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24150 if (CC != X86::COND_E && CC != X86::COND_NE)
24153 SDValue Cmp = SetCC.getOperand(1);
24154 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24155 !X86::isZeroNode(Cmp.getOperand(1)) ||
24156 !Cmp.getOperand(0).getValueType().isInteger())
24159 SDValue CmpOp0 = Cmp.getOperand(0);
24160 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24161 DAG.getConstant(1, CmpOp0.getValueType()));
24163 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24164 if (CC == X86::COND_NE)
24165 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24166 DL, OtherVal.getValueType(), OtherVal,
24167 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24168 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24169 DL, OtherVal.getValueType(), OtherVal,
24170 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24173 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24174 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24175 const X86Subtarget *Subtarget) {
24176 EVT VT = N->getValueType(0);
24177 SDValue Op0 = N->getOperand(0);
24178 SDValue Op1 = N->getOperand(1);
24180 // Try to synthesize horizontal adds from adds of shuffles.
24181 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24182 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24183 isHorizontalBinOp(Op0, Op1, true))
24184 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24186 return OptimizeConditionalInDecrement(N, DAG);
24189 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24190 const X86Subtarget *Subtarget) {
24191 SDValue Op0 = N->getOperand(0);
24192 SDValue Op1 = N->getOperand(1);
24194 // X86 can't encode an immediate LHS of a sub. See if we can push the
24195 // negation into a preceding instruction.
24196 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24197 // If the RHS of the sub is a XOR with one use and a constant, invert the
24198 // immediate. Then add one to the LHS of the sub so we can turn
24199 // X-Y -> X+~Y+1, saving one register.
24200 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24201 isa<ConstantSDNode>(Op1.getOperand(1))) {
24202 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24203 EVT VT = Op0.getValueType();
24204 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24206 DAG.getConstant(~XorC, VT));
24207 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24208 DAG.getConstant(C->getAPIntValue()+1, VT));
24212 // Try to synthesize horizontal adds from adds of shuffles.
24213 EVT VT = N->getValueType(0);
24214 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24215 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24216 isHorizontalBinOp(Op0, Op1, true))
24217 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24219 return OptimizeConditionalInDecrement(N, DAG);
24222 /// performVZEXTCombine - Performs build vector combines
24223 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24224 TargetLowering::DAGCombinerInfo &DCI,
24225 const X86Subtarget *Subtarget) {
24226 // (vzext (bitcast (vzext (x)) -> (vzext x)
24227 SDValue In = N->getOperand(0);
24228 while (In.getOpcode() == ISD::BITCAST)
24229 In = In.getOperand(0);
24231 if (In.getOpcode() != X86ISD::VZEXT)
24234 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
24238 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24239 DAGCombinerInfo &DCI) const {
24240 SelectionDAG &DAG = DCI.DAG;
24241 switch (N->getOpcode()) {
24243 case ISD::EXTRACT_VECTOR_ELT:
24244 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24246 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24247 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24248 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24249 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24250 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24251 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24254 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24255 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24256 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24257 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24258 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24259 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24260 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24261 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24262 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24264 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24266 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24267 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24268 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24269 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24270 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24271 case ISD::ANY_EXTEND:
24272 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24273 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24274 case ISD::SIGN_EXTEND_INREG:
24275 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24276 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24277 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24278 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24279 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24280 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24281 case X86ISD::SHUFP: // Handle all target specific shuffles
24282 case X86ISD::PALIGNR:
24283 case X86ISD::UNPCKH:
24284 case X86ISD::UNPCKL:
24285 case X86ISD::MOVHLPS:
24286 case X86ISD::MOVLHPS:
24287 case X86ISD::PSHUFB:
24288 case X86ISD::PSHUFD:
24289 case X86ISD::PSHUFHW:
24290 case X86ISD::PSHUFLW:
24291 case X86ISD::MOVSS:
24292 case X86ISD::MOVSD:
24293 case X86ISD::VPERMILPI:
24294 case X86ISD::VPERM2X128:
24295 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24296 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24297 case ISD::INTRINSIC_WO_CHAIN:
24298 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24299 case X86ISD::INSERTPS:
24300 return PerformINSERTPSCombine(N, DAG, Subtarget);
24301 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24307 /// isTypeDesirableForOp - Return true if the target has native support for
24308 /// the specified value type and it is 'desirable' to use the type for the
24309 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24310 /// instruction encodings are longer and some i16 instructions are slow.
24311 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24312 if (!isTypeLegal(VT))
24314 if (VT != MVT::i16)
24321 case ISD::SIGN_EXTEND:
24322 case ISD::ZERO_EXTEND:
24323 case ISD::ANY_EXTEND:
24336 /// IsDesirableToPromoteOp - This method query the target whether it is
24337 /// beneficial for dag combiner to promote the specified node. If true, it
24338 /// should return the desired promotion type by reference.
24339 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24340 EVT VT = Op.getValueType();
24341 if (VT != MVT::i16)
24344 bool Promote = false;
24345 bool Commute = false;
24346 switch (Op.getOpcode()) {
24349 LoadSDNode *LD = cast<LoadSDNode>(Op);
24350 // If the non-extending load has a single use and it's not live out, then it
24351 // might be folded.
24352 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24353 Op.hasOneUse()*/) {
24354 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24355 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24356 // The only case where we'd want to promote LOAD (rather then it being
24357 // promoted as an operand is when it's only use is liveout.
24358 if (UI->getOpcode() != ISD::CopyToReg)
24365 case ISD::SIGN_EXTEND:
24366 case ISD::ZERO_EXTEND:
24367 case ISD::ANY_EXTEND:
24372 SDValue N0 = Op.getOperand(0);
24373 // Look out for (store (shl (load), x)).
24374 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24387 SDValue N0 = Op.getOperand(0);
24388 SDValue N1 = Op.getOperand(1);
24389 if (!Commute && MayFoldLoad(N1))
24391 // Avoid disabling potential load folding opportunities.
24392 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24394 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24404 //===----------------------------------------------------------------------===//
24405 // X86 Inline Assembly Support
24406 //===----------------------------------------------------------------------===//
24409 // Helper to match a string separated by whitespace.
24410 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24411 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24413 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24414 StringRef piece(*args[i]);
24415 if (!s.startswith(piece)) // Check if the piece matches.
24418 s = s.substr(piece.size());
24419 StringRef::size_type pos = s.find_first_not_of(" \t");
24420 if (pos == 0) // We matched a prefix.
24428 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24431 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24433 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24434 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24435 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24436 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24438 if (AsmPieces.size() == 3)
24440 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24447 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24448 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24450 std::string AsmStr = IA->getAsmString();
24452 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24453 if (!Ty || Ty->getBitWidth() % 16 != 0)
24456 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24457 SmallVector<StringRef, 4> AsmPieces;
24458 SplitString(AsmStr, AsmPieces, ";\n");
24460 switch (AsmPieces.size()) {
24461 default: return false;
24463 // FIXME: this should verify that we are targeting a 486 or better. If not,
24464 // we will turn this bswap into something that will be lowered to logical
24465 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24466 // lower so don't worry about this.
24468 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24469 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24470 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24471 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24472 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24473 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24474 // No need to check constraints, nothing other than the equivalent of
24475 // "=r,0" would be valid here.
24476 return IntrinsicLowering::LowerToByteSwap(CI);
24479 // rorw $$8, ${0:w} --> llvm.bswap.i16
24480 if (CI->getType()->isIntegerTy(16) &&
24481 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24482 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24483 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24485 const std::string &ConstraintsStr = IA->getConstraintString();
24486 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24487 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24488 if (clobbersFlagRegisters(AsmPieces))
24489 return IntrinsicLowering::LowerToByteSwap(CI);
24493 if (CI->getType()->isIntegerTy(32) &&
24494 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24495 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24496 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24497 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24499 const std::string &ConstraintsStr = IA->getConstraintString();
24500 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24501 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24502 if (clobbersFlagRegisters(AsmPieces))
24503 return IntrinsicLowering::LowerToByteSwap(CI);
24506 if (CI->getType()->isIntegerTy(64)) {
24507 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24508 if (Constraints.size() >= 2 &&
24509 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24510 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24511 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24512 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24513 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24514 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24515 return IntrinsicLowering::LowerToByteSwap(CI);
24523 /// getConstraintType - Given a constraint letter, return the type of
24524 /// constraint it is for this target.
24525 X86TargetLowering::ConstraintType
24526 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24527 if (Constraint.size() == 1) {
24528 switch (Constraint[0]) {
24539 return C_RegisterClass;
24563 return TargetLowering::getConstraintType(Constraint);
24566 /// Examine constraint type and operand type and determine a weight value.
24567 /// This object must already have been set up with the operand type
24568 /// and the current alternative constraint selected.
24569 TargetLowering::ConstraintWeight
24570 X86TargetLowering::getSingleConstraintMatchWeight(
24571 AsmOperandInfo &info, const char *constraint) const {
24572 ConstraintWeight weight = CW_Invalid;
24573 Value *CallOperandVal = info.CallOperandVal;
24574 // If we don't have a value, we can't do a match,
24575 // but allow it at the lowest weight.
24576 if (!CallOperandVal)
24578 Type *type = CallOperandVal->getType();
24579 // Look at the constraint type.
24580 switch (*constraint) {
24582 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24593 if (CallOperandVal->getType()->isIntegerTy())
24594 weight = CW_SpecificReg;
24599 if (type->isFloatingPointTy())
24600 weight = CW_SpecificReg;
24603 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24604 weight = CW_SpecificReg;
24608 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24609 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24610 weight = CW_Register;
24613 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24614 if (C->getZExtValue() <= 31)
24615 weight = CW_Constant;
24619 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24620 if (C->getZExtValue() <= 63)
24621 weight = CW_Constant;
24625 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24626 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24627 weight = CW_Constant;
24631 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24632 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24633 weight = CW_Constant;
24637 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24638 if (C->getZExtValue() <= 3)
24639 weight = CW_Constant;
24643 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24644 if (C->getZExtValue() <= 0xff)
24645 weight = CW_Constant;
24650 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24651 weight = CW_Constant;
24655 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24656 if ((C->getSExtValue() >= -0x80000000LL) &&
24657 (C->getSExtValue() <= 0x7fffffffLL))
24658 weight = CW_Constant;
24662 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24663 if (C->getZExtValue() <= 0xffffffff)
24664 weight = CW_Constant;
24671 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24672 /// with another that has more specific requirements based on the type of the
24673 /// corresponding operand.
24674 const char *X86TargetLowering::
24675 LowerXConstraint(EVT ConstraintVT) const {
24676 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24677 // 'f' like normal targets.
24678 if (ConstraintVT.isFloatingPoint()) {
24679 if (Subtarget->hasSSE2())
24681 if (Subtarget->hasSSE1())
24685 return TargetLowering::LowerXConstraint(ConstraintVT);
24688 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24689 /// vector. If it is invalid, don't add anything to Ops.
24690 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24691 std::string &Constraint,
24692 std::vector<SDValue>&Ops,
24693 SelectionDAG &DAG) const {
24696 // Only support length 1 constraints for now.
24697 if (Constraint.length() > 1) return;
24699 char ConstraintLetter = Constraint[0];
24700 switch (ConstraintLetter) {
24703 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24704 if (C->getZExtValue() <= 31) {
24705 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24711 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24712 if (C->getZExtValue() <= 63) {
24713 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24719 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24720 if (isInt<8>(C->getSExtValue())) {
24721 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24727 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24728 if (C->getZExtValue() <= 255) {
24729 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24735 // 32-bit signed value
24736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24737 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24738 C->getSExtValue())) {
24739 // Widen to 64 bits here to get it sign extended.
24740 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24743 // FIXME gcc accepts some relocatable values here too, but only in certain
24744 // memory models; it's complicated.
24749 // 32-bit unsigned value
24750 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24751 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24752 C->getZExtValue())) {
24753 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24757 // FIXME gcc accepts some relocatable values here too, but only in certain
24758 // memory models; it's complicated.
24762 // Literal immediates are always ok.
24763 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24764 // Widen to 64 bits here to get it sign extended.
24765 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24769 // In any sort of PIC mode addresses need to be computed at runtime by
24770 // adding in a register or some sort of table lookup. These can't
24771 // be used as immediates.
24772 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24775 // If we are in non-pic codegen mode, we allow the address of a global (with
24776 // an optional displacement) to be used with 'i'.
24777 GlobalAddressSDNode *GA = nullptr;
24778 int64_t Offset = 0;
24780 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24782 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24783 Offset += GA->getOffset();
24785 } else if (Op.getOpcode() == ISD::ADD) {
24786 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24787 Offset += C->getZExtValue();
24788 Op = Op.getOperand(0);
24791 } else if (Op.getOpcode() == ISD::SUB) {
24792 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24793 Offset += -C->getZExtValue();
24794 Op = Op.getOperand(0);
24799 // Otherwise, this isn't something we can handle, reject it.
24803 const GlobalValue *GV = GA->getGlobal();
24804 // If we require an extra load to get this address, as in PIC mode, we
24805 // can't accept it.
24806 if (isGlobalStubReference(
24807 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24810 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24811 GA->getValueType(0), Offset);
24816 if (Result.getNode()) {
24817 Ops.push_back(Result);
24820 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24823 std::pair<unsigned, const TargetRegisterClass*>
24824 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24826 // First, see if this is a constraint that directly corresponds to an LLVM
24828 if (Constraint.size() == 1) {
24829 // GCC Constraint Letters
24830 switch (Constraint[0]) {
24832 // TODO: Slight differences here in allocation order and leaving
24833 // RIP in the class. Do they matter any more here than they do
24834 // in the normal allocation?
24835 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24836 if (Subtarget->is64Bit()) {
24837 if (VT == MVT::i32 || VT == MVT::f32)
24838 return std::make_pair(0U, &X86::GR32RegClass);
24839 if (VT == MVT::i16)
24840 return std::make_pair(0U, &X86::GR16RegClass);
24841 if (VT == MVT::i8 || VT == MVT::i1)
24842 return std::make_pair(0U, &X86::GR8RegClass);
24843 if (VT == MVT::i64 || VT == MVT::f64)
24844 return std::make_pair(0U, &X86::GR64RegClass);
24847 // 32-bit fallthrough
24848 case 'Q': // Q_REGS
24849 if (VT == MVT::i32 || VT == MVT::f32)
24850 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24851 if (VT == MVT::i16)
24852 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24853 if (VT == MVT::i8 || VT == MVT::i1)
24854 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24855 if (VT == MVT::i64)
24856 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24858 case 'r': // GENERAL_REGS
24859 case 'l': // INDEX_REGS
24860 if (VT == MVT::i8 || VT == MVT::i1)
24861 return std::make_pair(0U, &X86::GR8RegClass);
24862 if (VT == MVT::i16)
24863 return std::make_pair(0U, &X86::GR16RegClass);
24864 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24865 return std::make_pair(0U, &X86::GR32RegClass);
24866 return std::make_pair(0U, &X86::GR64RegClass);
24867 case 'R': // LEGACY_REGS
24868 if (VT == MVT::i8 || VT == MVT::i1)
24869 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24870 if (VT == MVT::i16)
24871 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24872 if (VT == MVT::i32 || !Subtarget->is64Bit())
24873 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24874 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24875 case 'f': // FP Stack registers.
24876 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24877 // value to the correct fpstack register class.
24878 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24879 return std::make_pair(0U, &X86::RFP32RegClass);
24880 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24881 return std::make_pair(0U, &X86::RFP64RegClass);
24882 return std::make_pair(0U, &X86::RFP80RegClass);
24883 case 'y': // MMX_REGS if MMX allowed.
24884 if (!Subtarget->hasMMX()) break;
24885 return std::make_pair(0U, &X86::VR64RegClass);
24886 case 'Y': // SSE_REGS if SSE2 allowed
24887 if (!Subtarget->hasSSE2()) break;
24889 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24890 if (!Subtarget->hasSSE1()) break;
24892 switch (VT.SimpleTy) {
24894 // Scalar SSE types.
24897 return std::make_pair(0U, &X86::FR32RegClass);
24900 return std::make_pair(0U, &X86::FR64RegClass);
24908 return std::make_pair(0U, &X86::VR128RegClass);
24916 return std::make_pair(0U, &X86::VR256RegClass);
24921 return std::make_pair(0U, &X86::VR512RegClass);
24927 // Use the default implementation in TargetLowering to convert the register
24928 // constraint into a member of a register class.
24929 std::pair<unsigned, const TargetRegisterClass*> Res;
24930 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24932 // Not found as a standard register?
24934 // Map st(0) -> st(7) -> ST0
24935 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24936 tolower(Constraint[1]) == 's' &&
24937 tolower(Constraint[2]) == 't' &&
24938 Constraint[3] == '(' &&
24939 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24940 Constraint[5] == ')' &&
24941 Constraint[6] == '}') {
24943 Res.first = X86::FP0+Constraint[4]-'0';
24944 Res.second = &X86::RFP80RegClass;
24948 // GCC allows "st(0)" to be called just plain "st".
24949 if (StringRef("{st}").equals_lower(Constraint)) {
24950 Res.first = X86::FP0;
24951 Res.second = &X86::RFP80RegClass;
24956 if (StringRef("{flags}").equals_lower(Constraint)) {
24957 Res.first = X86::EFLAGS;
24958 Res.second = &X86::CCRRegClass;
24962 // 'A' means EAX + EDX.
24963 if (Constraint == "A") {
24964 Res.first = X86::EAX;
24965 Res.second = &X86::GR32_ADRegClass;
24971 // Otherwise, check to see if this is a register class of the wrong value
24972 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24973 // turn into {ax},{dx}.
24974 if (Res.second->hasType(VT))
24975 return Res; // Correct type already, nothing to do.
24977 // All of the single-register GCC register classes map their values onto
24978 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24979 // really want an 8-bit or 32-bit register, map to the appropriate register
24980 // class and return the appropriate register.
24981 if (Res.second == &X86::GR16RegClass) {
24982 if (VT == MVT::i8 || VT == MVT::i1) {
24983 unsigned DestReg = 0;
24984 switch (Res.first) {
24986 case X86::AX: DestReg = X86::AL; break;
24987 case X86::DX: DestReg = X86::DL; break;
24988 case X86::CX: DestReg = X86::CL; break;
24989 case X86::BX: DestReg = X86::BL; break;
24992 Res.first = DestReg;
24993 Res.second = &X86::GR8RegClass;
24995 } else if (VT == MVT::i32 || VT == MVT::f32) {
24996 unsigned DestReg = 0;
24997 switch (Res.first) {
24999 case X86::AX: DestReg = X86::EAX; break;
25000 case X86::DX: DestReg = X86::EDX; break;
25001 case X86::CX: DestReg = X86::ECX; break;
25002 case X86::BX: DestReg = X86::EBX; break;
25003 case X86::SI: DestReg = X86::ESI; break;
25004 case X86::DI: DestReg = X86::EDI; break;
25005 case X86::BP: DestReg = X86::EBP; break;
25006 case X86::SP: DestReg = X86::ESP; break;
25009 Res.first = DestReg;
25010 Res.second = &X86::GR32RegClass;
25012 } else if (VT == MVT::i64 || VT == MVT::f64) {
25013 unsigned DestReg = 0;
25014 switch (Res.first) {
25016 case X86::AX: DestReg = X86::RAX; break;
25017 case X86::DX: DestReg = X86::RDX; break;
25018 case X86::CX: DestReg = X86::RCX; break;
25019 case X86::BX: DestReg = X86::RBX; break;
25020 case X86::SI: DestReg = X86::RSI; break;
25021 case X86::DI: DestReg = X86::RDI; break;
25022 case X86::BP: DestReg = X86::RBP; break;
25023 case X86::SP: DestReg = X86::RSP; break;
25026 Res.first = DestReg;
25027 Res.second = &X86::GR64RegClass;
25030 } else if (Res.second == &X86::FR32RegClass ||
25031 Res.second == &X86::FR64RegClass ||
25032 Res.second == &X86::VR128RegClass ||
25033 Res.second == &X86::VR256RegClass ||
25034 Res.second == &X86::FR32XRegClass ||
25035 Res.second == &X86::FR64XRegClass ||
25036 Res.second == &X86::VR128XRegClass ||
25037 Res.second == &X86::VR256XRegClass ||
25038 Res.second == &X86::VR512RegClass) {
25039 // Handle references to XMM physical registers that got mapped into the
25040 // wrong class. This can happen with constraints like {xmm0} where the
25041 // target independent register mapper will just pick the first match it can
25042 // find, ignoring the required type.
25044 if (VT == MVT::f32 || VT == MVT::i32)
25045 Res.second = &X86::FR32RegClass;
25046 else if (VT == MVT::f64 || VT == MVT::i64)
25047 Res.second = &X86::FR64RegClass;
25048 else if (X86::VR128RegClass.hasType(VT))
25049 Res.second = &X86::VR128RegClass;
25050 else if (X86::VR256RegClass.hasType(VT))
25051 Res.second = &X86::VR256RegClass;
25052 else if (X86::VR512RegClass.hasType(VT))
25053 Res.second = &X86::VR512RegClass;
25059 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25061 // Scaling factors are not free at all.
25062 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25063 // will take 2 allocations in the out of order engine instead of 1
25064 // for plain addressing mode, i.e. inst (reg1).
25066 // vaddps (%rsi,%drx), %ymm0, %ymm1
25067 // Requires two allocations (one for the load, one for the computation)
25069 // vaddps (%rsi), %ymm0, %ymm1
25070 // Requires just 1 allocation, i.e., freeing allocations for other operations
25071 // and having less micro operations to execute.
25073 // For some X86 architectures, this is even worse because for instance for
25074 // stores, the complex addressing mode forces the instruction to use the
25075 // "load" ports instead of the dedicated "store" port.
25076 // E.g., on Haswell:
25077 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25078 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25079 if (isLegalAddressingMode(AM, Ty))
25080 // Scale represents reg2 * scale, thus account for 1
25081 // as soon as we use a second register.
25082 return AM.Scale != 0;
25086 bool X86TargetLowering::isTargetFTOL() const {
25087 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();